impl bsp for ch32v003xx

bsp/wch/ch32/LICENSE

@@ -0,0 +1,19 @@
+Copyright (c) Zig Embedded Group contributors
+
+This software is provided 'as-is', without any express or implied warranty. In
+no event will the authors be held liable for any damages arising from the use
+of this software.
+
+Permission is granted to anyone to use this software for any purpose, including
+commercial applications, and to alter it and redistribute it freely, subject to
+the following restrictions:
+
+1. The origin of this software must not be misrepresented; you must not claim
+   that you wrote the original software. If you use this software in a product,
+   an acknowledgment in the product documentation would be appreciated but is
+   not required.
+
+2. Altered source versions must be plainly marked as such, and must not be
+   misrepresented as being the original software.
+
+3. This notice may not be removed or altered from any source distribution.

bsp/wch/ch32/README.md

@@ -0,0 +1,3 @@
+# ch32
+
+HALs and register definitions for CH32 (WCH) devices

bsp/wch/ch32/build.zig

@@ -0,0 +1,48 @@
+const std = @import("std");
+const MicroZig = @import("microzig/build");
+
+const KiB = 1024;
+
+fn path(comptime suffix: []const u8) std.Build.LazyPath {
+    return .{
+        .cwd_relative = comptime ((std.fs.path.dirname(@src().file) orelse ".") ++ suffix),
+    };
+}
+
+const wch_qingke_v2 = .{
+    .name = "WCH QingKe V2",
+    .root_source_file = path("/src/cpus/wch_qingke_v2.zig"),
+    .target = std.Target.Query{
+        .cpu_arch = .riscv32,
+        .cpu_model = .{ .explicit = &std.Target.riscv.cpu.generic_rv32 },
+        .cpu_features_add = std.Target.riscv.featureSet(&.{
+            std.Target.riscv.Feature.e,
+            std.Target.riscv.Feature.c,
+        }),
+        .os_tag = .freestanding,
+        .abi = .eabi,
+    },
+};
+
+pub const chips = struct {
+    pub const ch32v003xx = MicroZig.Target{
+        .preferred_format = .elf,
+        .chip = .{
+            .name = "CH32V00xxx",
+            .cpu = wch_qingke_v2,
+            .memory_regions = &.{
+                .{ .offset = 0x0800_0000, .length = 16 * KiB, .kind = .flash },
+                .{ .offset = 0x2000_0000, .length = 2 * KiB, .kind = .ram },
+            },
+            .register_definition = .{
+                .svd = path("/src/chips/CH32V00xxx.svd"),
+            },
+        },
+    };
+};
+
+pub const boards = struct {};
+
+pub fn build(b: *std.Build) !void {
+    _ = b.step("test", "Run platform agnostic unit tests");
+}

bsp/wch/ch32/build.zig.zon

@@ -0,0 +1,15 @@
+.{
+    .name = "bsp/wch/ch32",
+    .version = "0.0.0",
+    .dependencies = .{
+        .@"microzig/build" = .{ .path = "../../../build" },
+    },
+    .paths = .{
+        "LICENSE",
+        "README.md",
+        "build.zig",
+        "build.zig.zon",
+        "src",
+        "test",
+    },
+}

bsp/wch/ch32/src/cpus/wch_qingke_v2.zig

@@ -0,0 +1,47 @@
+const std = @import("std");
+const root = @import("root");
+const microzig = @import("microzig");
+
+pub fn enable_interrupts() void {
+    asm volatile ("csrsi mstatus, 0b1000");
+}
+
+pub fn disable_interrupts() void {
+    asm volatile ("csrci mstatus, 0b1000");
+}
+
+pub fn wfi() void {
+    asm volatile ("wfi");
+}
+
+pub fn wfe() void {
+    const PFIC = microzig.chip.peripherals.PFIC;
+    // Treats the subsequent wfi instruction as wfe
+    PFIC.SCTLR.modify(.{ .WFITOWFE = 1 });
+    asm volatile ("wfi");
+}
+
+pub const startup_logic = struct {
+    extern fn microzig_main() noreturn;
+
+    pub fn _start() callconv(.C) noreturn {
+        asm volatile ("la gp, __global_pointer$");
+        asm volatile ("mv sp, %[eos]"
+            :
+            : [eos] "r" (@as(u32, microzig.config.end_of_stack)),
+        );
+        root.initialize_system_memories();
+        asm volatile ("csrsi 0x804, 0b111"); // INTSYSCR: enable EABI + Interrupt nesting + HPE
+        asm volatile ("csrsi mtvec, 0b11"); // mtvec: absolute address + vector table mode
+        microzig.cpu.enable_interrupts();
+        microzig_main();
+    }
+
+    export fn _reset_vector() linksection("microzig_flash_start") callconv(.Naked) void {
+        asm volatile ("j _start");
+    }
+};
+
+pub fn export_startup_logic() void {
+    @export(startup_logic._start, .{ .name = "_start" });
+}

build.zig

@@ -23,6 +23,7 @@ const bsps = .{
     .{ "bsp/stmicro/stm32", @import("bsp/stmicro/stm32") },
     .{ "bsp/espressif/esp", @import("bsp/espressif/esp") },
     .{ "bsp/raspberrypi/rp2040", @import("bsp/raspberrypi/rp2040") },
+    .{ "bsp/wch/ch32", @import("bsp/wch/ch32") },
 };
 
 pub fn build(b: *Build) void {

examples/wch/ch32/LICENSE

@@ -0,0 +1,19 @@
+Copyright (c) Zig Embedded Group contributors
+
+This software is provided 'as-is', without any express or implied warranty. In
+no event will the authors be held liable for any damages arising from the use
+of this software.
+
+Permission is granted to anyone to use this software for any purpose, including
+commercial applications, and to alter it and redistribute it freely, subject to
+the following restrictions:
+
+1. The origin of this software must not be misrepresented; you must not claim
+   that you wrote the original software. If you use this software in a product,
+   an acknowledgment in the product documentation would be appreciated but is
+   not required.
+
+2. Altered source versions must be plainly marked as such, and must not be
+   misrepresented as being the original software.
+
+3. This notice may not be removed or altered from any source distribution.

examples/wch/ch32/build.zig

@@ -0,0 +1,29 @@
+const std = @import("std");
+const MicroZig = @import("microzig/build");
+const ch32 = @import("microzig/bsp/wch/ch32");
+
+const available_examples = [_]Example{
+    .{ .target = ch32.chips.ch32v003xx, .name = "ch32v003xx", .file = "src/empty.zig" },
+};
+
+pub fn build(b: *std.Build) void {
+    const microzig = MicroZig.init(b, .{});
+    const optimize = b.standardOptimizeOption(.{});
+
+    for (available_examples) |example| {
+        const firmware = microzig.add_firmware(b, .{
+            .name = example.name,
+            .target = example.target,
+            .optimize = optimize,
+            .root_source_file = b.path(example.file),
+        });
+        microzig.install_firmware(b, firmware, .{});
+        microzig.install_firmware(b, firmware, .{ .format = .bin });
+    }
+}
+
+const Example = struct {
+    target: MicroZig.Target,
+    name: []const u8,
+    file: []const u8,
+};

examples/wch/ch32/build.zig.zon

@@ -0,0 +1,15 @@
+.{
+    .name = "examples/wch/ch32",
+    .version = "0.0.0",
+    .dependencies = .{
+        .@"microzig/build" = .{ .path = "../../../build" },
+        .@"microzig/bsp/wch/ch32" = .{ .path = "../../../bsp/wch/ch32" },
+    },
+
+    .paths = .{
+        "LICENSE",
+        "build.zig",
+        "build.zig.zon",
+        "src",
+    },
+}

examples/wch/ch32/src/empty.zig

@@ -0,0 +1,6 @@
+const std = @import("std");
+const microzig = @import("microzig");
+
+pub fn main() !void {
+    asm volatile ("nop");
+}