From b5d657a0090a820f1904e687050864d7822905fe Mon Sep 17 00:00:00 2001 From: akiroz Date: Fri, 19 Jul 2024 03:52:46 +0900 Subject: [PATCH] impl bsp for ch32v003xx --- bsp/wch/ch32/LICENSE | 19 + bsp/wch/ch32/README.md | 3 + bsp/wch/ch32/build.zig | 48 + bsp/wch/ch32/build.zig.zon | 15 + bsp/wch/ch32/src/chips/CH32V00xxx.svd | 9234 +++++++++++++++++++++++ bsp/wch/ch32/src/cpus/wch_qingke_v2.zig | 47 + build.zig | 1 + examples/wch/ch32/LICENSE | 19 + examples/wch/ch32/build.zig | 29 + examples/wch/ch32/build.zig.zon | 15 + examples/wch/ch32/src/empty.zig | 6 + 11 files changed, 9436 insertions(+) create mode 100644 bsp/wch/ch32/LICENSE create mode 100644 bsp/wch/ch32/README.md create mode 100644 bsp/wch/ch32/build.zig create mode 100644 bsp/wch/ch32/build.zig.zon create mode 100644 bsp/wch/ch32/src/chips/CH32V00xxx.svd create mode 100644 bsp/wch/ch32/src/cpus/wch_qingke_v2.zig create mode 100644 examples/wch/ch32/LICENSE create mode 100644 examples/wch/ch32/build.zig create mode 100644 examples/wch/ch32/build.zig.zon create mode 100644 examples/wch/ch32/src/empty.zig diff --git a/bsp/wch/ch32/LICENSE b/bsp/wch/ch32/LICENSE new file mode 100644 index 0000000..3364097 --- /dev/null +++ b/bsp/wch/ch32/LICENSE @@ -0,0 +1,19 @@ +Copyright (c) Zig Embedded Group contributors + +This software is provided 'as-is', without any express or implied warranty. In +no event will the authors be held liable for any damages arising from the use +of this software. + +Permission is granted to anyone to use this software for any purpose, including +commercial applications, and to alter it and redistribute it freely, subject to +the following restrictions: + +1. The origin of this software must not be misrepresented; you must not claim + that you wrote the original software. If you use this software in a product, + an acknowledgment in the product documentation would be appreciated but is + not required. + +2. Altered source versions must be plainly marked as such, and must not be + misrepresented as being the original software. + +3. This notice may not be removed or altered from any source distribution. diff --git a/bsp/wch/ch32/README.md b/bsp/wch/ch32/README.md new file mode 100644 index 0000000..78b160d --- /dev/null +++ b/bsp/wch/ch32/README.md @@ -0,0 +1,3 @@ +# ch32 + +HALs and register definitions for CH32 (WCH) devices diff --git a/bsp/wch/ch32/build.zig b/bsp/wch/ch32/build.zig new file mode 100644 index 0000000..673fa89 --- /dev/null +++ b/bsp/wch/ch32/build.zig @@ -0,0 +1,48 @@ +const std = @import("std"); +const MicroZig = @import("microzig/build"); + +const KiB = 1024; + +fn path(comptime suffix: []const u8) std.Build.LazyPath { + return .{ + .cwd_relative = comptime ((std.fs.path.dirname(@src().file) orelse ".") ++ suffix), + }; +} + +const wch_qingke_v2 = .{ + .name = "WCH QingKe V2", + .root_source_file = path("/src/cpus/wch_qingke_v2.zig"), + .target = std.Target.Query{ + .cpu_arch = .riscv32, + .cpu_model = .{ .explicit = &std.Target.riscv.cpu.generic_rv32 }, + .cpu_features_add = std.Target.riscv.featureSet(&.{ + std.Target.riscv.Feature.e, + std.Target.riscv.Feature.c, + }), + .os_tag = .freestanding, + .abi = .eabi, + }, +}; + +pub const chips = struct { + pub const ch32v003xx = MicroZig.Target{ + .preferred_format = .elf, + .chip = .{ + .name = "CH32V00xxx", + .cpu = wch_qingke_v2, + .memory_regions = &.{ + .{ .offset = 0x0800_0000, .length = 16 * KiB, .kind = .flash }, + .{ .offset = 0x2000_0000, .length = 2 * KiB, .kind = .ram }, + }, + .register_definition = .{ + .svd = path("/src/chips/CH32V00xxx.svd"), + }, + }, + }; +}; + +pub const boards = struct {}; + +pub fn build(b: *std.Build) !void { + _ = b.step("test", "Run platform agnostic unit tests"); +} diff --git a/bsp/wch/ch32/build.zig.zon b/bsp/wch/ch32/build.zig.zon new file mode 100644 index 0000000..84eae81 --- /dev/null +++ b/bsp/wch/ch32/build.zig.zon @@ -0,0 +1,15 @@ +.{ + .name = "bsp/wch/ch32", + .version = "0.0.0", + .dependencies = .{ + .@"microzig/build" = .{ .path = "../../../build" }, + }, + .paths = .{ + "LICENSE", + "README.md", + "build.zig", + "build.zig.zon", + "src", + "test", + }, +} diff --git a/bsp/wch/ch32/src/chips/CH32V00xxx.svd b/bsp/wch/ch32/src/chips/CH32V00xxx.svd new file mode 100644 index 0000000..8eac916 --- /dev/null +++ b/bsp/wch/ch32/src/chips/CH32V00xxx.svd @@ -0,0 +1,9234 @@ + + + WCH Ltd. + WCH + CH32V00xxx + 1.2 + CH32V00xxx View File + + + + 8 + + 32 + + 0x20 + 0x0 + 0xFFFFFFFF + + + PWR + Power control + PWR + 0x40007000 + + 0x0 + 0x400 + registers + + + PVD + PVD through EXTI line detection + interrupt + 17 + + + AWU + AWU global + interrupt + 21 + + + + CTLR + CTLR + Power control register + (PWR_CTRL) + 0x0 + 0x20 + read-write + 0x00000000 + + + PDDS + Power Down Deep Sleep + 1 + 1 + + + PVDE + Power Voltage Detector + Enable + 4 + 1 + + + PLS + PVD Level Selection + 5 + 3 + + + + + CSR + CSR + Power control state register + (PWR_CSR) + 0x04 + 0x20 + 0x00000000 + + + PVDO + PVD Output + 2 + 1 + read-only + + + + + AWUCSR + AWUCSR + Automatic wake-up control state register + (PWR_AWUCSR) + 0x08 + 0x20 + 0x00000000 + + + AWUEN + Automatic wake-up enable + 1 + 1 + read-write + + + + + AWUWR + AWUWR + Automatic wake window comparison value register + (PWR_AWUWR) + 0x0C + 0x20 + 0x0000003F + + + AWUWR + AWU window value + 0 + 6 + read-write + + + + + AWUPSC + AWUPSC + Automatic wake-up prescaler register + (PWR_AWUPSC) + 0x10 + 0x20 + 0x00000000 + + + AWUPSC + Wake-up prescaler + 0 + 4 + read-write + + + + + + + RCC + Reset and clock control + RCC + 0x40021000 + + 0x00 + 0x400 + registers + + + RCC + Reset and clock control interrupt + 19 + + + + CTLR + CTLR + Clock control register + 0x00 + 0x20 + 0x00000083 + + + HSION + Internal High Speed clock + enable + 0 + 1 + read-write + + + HSIRDY + Internal High Speed clock ready + flag + 1 + 1 + read-only + + + HSITRIM + Internal High Speed clock + trimming + 3 + 5 + read-write + + + HSICAL + Internal High Speed clock + Calibration + 8 + 8 + read-only + + + HSEON + External High Speed clock + enable + 16 + 1 + read-write + + + HSERDY + External High Speed clock ready + flag + 17 + 1 + read-only + + + HSEBYP + External High Speed clock + Bypass + 18 + 1 + read-write + + + CSSON + Clock Security System + enable + 19 + 1 + read-write + + + PLLON + PLL enable + 24 + 1 + read-write + + + PLLRDY + PLL clock ready flag + 25 + 1 + read-only + + + + + CFGR0 + CFGR0 + Clock configuration register + (RCC_CFGR0) + 0x04 + 0x20 + 0x00000020 + + + SW + System clock Switch + 0 + 2 + read-write + + + SWS + System Clock Switch Status + 2 + 2 + read-only + + + HPRE + HB prescaler + 4 + 4 + read-write + + + ADCPRE + ADC prescaler + 11 + 5 + read-write + + + PLLSRC + PLL entry clock source + 16 + 1 + read-write + + + MCO + Microcontroller clock + output + 24 + 3 + read-write + + + + + INTR + INTR + Clock interrupt register + (RCC_INTR) + 0x08 + 0x20 + 0x00000000 + + + LSIRDYF + LSI Ready Interrupt flag + 0 + 1 + read-only + + + HSIRDYF + HSI Ready Interrupt flag + 2 + 1 + read-only + + + HSERDYF + HSE Ready Interrupt flag + 3 + 1 + read-only + + + PLLRDYF + PLL Ready Interrupt flag + 4 + 1 + read-only + + + CSSF + Clock Security System Interrupt + flag + 7 + 1 + read-only + + + LSIRDYIE + LSI Ready Interrupt Enable + 8 + 1 + read-write + + + HSIRDYIE + HSI Ready Interrupt Enable + 10 + 1 + read-write + + + HSERDYIE + HSE Ready Interrupt Enable + 11 + 1 + read-write + + + PLLRDYIE + PLL Ready Interrupt Enable + 12 + 1 + read-write + + + LSIRDYC + LSI Ready Interrupt Clear + 16 + 1 + write-only + + + HSIRDYC + HSI Ready Interrupt Clear + 18 + 1 + write-only + + + HSERDYC + HSE Ready Interrupt Clear + 19 + 1 + write-only + + + PLLRDYC + PLL Ready Interrupt Clear + 20 + 1 + write-only + + + CSSC + Clock security system interrupt + clear + 23 + 1 + write-only + + + + + APB2PRSTR + APB2PRSTR + PB2 peripheral reset register + (RCC_APB2PRSTR) + 0x0C + 0x20 + read-write + 0x00000000 + + + AFIORST + Alternate function I/O + reset + 0 + 1 + + + IOPARST + IO port A reset + 2 + 1 + + + IOPCRST + IO port C reset + 4 + 1 + + + IOPDRST + IO port D reset + 5 + 1 + + + ADC1RST + ADC 1 interface reset + 9 + 1 + + + TIM1RST + TIM1 timer reset + 11 + 1 + + + SPI1RST + SPI 1 reset + 12 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + + + APB1PRSTR + APB1PRSTR + PB1 peripheral reset register + (RCC_APB1PRSTR) + 0x10 + 0x20 + read-write + 0x00000000 + + + TIM2RST + TIM2 reset + 0 + 1 + + + WWDGRST + Window watchdog reset + 11 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + PWRRST + Power interface reset + 28 + 1 + + + + + AHBPCENR + AHBPCENR + HB Peripheral Clock enable register + (RCC_AHBPCENR) + 0x14 + 0x20 + read-write + 0x00000004 + + + DMA1EN + DMA clock enable + 0 + 1 + + + SRAMEN + SRAM interface clock + enable + 2 + 1 + + + + + APB2PCENR + APB2PCENR + PB2 peripheral clock enable register + (RCC_APB2PCENR) + 0x18 + 0x20 + read-write + 0x00000000 + + + AFIOEN + Alternate function I/O clock + enable + 0 + 1 + + + IOPAEN + I/O port A clock enable + 2 + 1 + + + IOPCEN + I/O port C clock enable + 4 + 1 + + + IOPDEN + I/O port D clock enable + 5 + 1 + + + ADC1EN + ADC1 interface clock + enable + 9 + 1 + + + TIM1EN + TIM1 Timer clock enable + 11 + 1 + + + SPI1EN + SPI 1 clock enable + 12 + 1 + + + USART1EN + USART1 clock enable + 14 + 1 + + + + + APB1PCENR + APB1PCENR + PB1 peripheral clock enable register + (RCC_APB1PCENR) + 0x1C + 0x20 + read-write + 0x00000000 + + + TIM2EN + Timer 2 clock enable + 0 + 1 + + + WWDGEN + Window watchdog clock + enable + 11 + 1 + + + I2C1EN + I2C 1 clock enable + 21 + 1 + + + PWREN + Power interface clock + enable + 28 + 1 + + + + + RSTSCKR + RSTSCKR + Control/status register + (RCC_RSTSCKR) + 0x24 + 0x20 + 0x0C000000 + + + LSION + Internal low speed oscillator + enable + 0 + 1 + read-write + + + LSIRDY + Internal low speed oscillator + ready + 1 + 1 + read-only + + + RMVF + Remove reset flag + 24 + 1 + read-write + + + PINRSTF + PIN reset flag + 26 + 1 + read-only + + + PORRSTF + POR/PDR reset flag + 27 + 1 + read-only + + + SFTRSTF + Software reset flag + 28 + 1 + read-only + + + IWDGRSTF + Independent watchdog reset + flag + 29 + 1 + read-only + + + WWDGRSTF + Window watchdog reset flag + 30 + 1 + read-only + + + LPWRRSTF + Low-power reset flag + 31 + 1 + read-only + + + + + + + EXTEN + Extend configuration + EXTEN + 0x40023800 + + 0x00 + 0x400 + registers + + + + EXTEN_CTR + EXTEND + Configure the extended control register + 0x00 + 0x20 + 0x00000400 + + + LKUPEN + LOCKUP_Enable + 6 + 1 + read-write + + + LKUPRST + LOCKUP RESET + 7 + 1 + read-write + + + LDO_TRIM + LDO_TRIM + 10 + 1 + read-write + + + OPAEN + OPA Enalbe + 16 + 1 + read-write + + + OPANSEL + OPA negative end channel selection + 17 + 1 + read-write + + + OPAPSEL + OPA positive end channel selection + 18 + 1 + read-write + + + + + + + GPIOA + General purpose I/O + GPIO + 0x40010800 + + 0x0 + 0x400 + registers + + + + CFGLR + CFGLR + Port configuration register low + (GPIOn_CFGLR) + 0x0 + 0x20 + read-write + 0x44444444 + + + MODE0 + Port n.0 mode bits + 0 + 2 + + + CNF0 + Port n.0 configuration + bits + 2 + 2 + + + MODE1 + Port n.1 mode bits + 4 + 2 + + + CNF1 + Port n.1 configuration + bits + 6 + 2 + + + MODE2 + Port n.2 mode bits + 8 + 2 + + + CNF2 + Port n.2 configuration + bits + 10 + 2 + + + MODE3 + Port n.3 mode bits + 12 + 2 + + + CNF3 + Port n.3 configuration + bits + 14 + 2 + + + MODE4 + Port n.4 mode bits + 16 + 2 + + + CNF4 + Port n.4 configuration + bits + 18 + 2 + + + MODE5 + Port n.5 mode bits + 20 + 2 + + + CNF5 + Port n.5 configuration + bits + 22 + 2 + + + MODE6 + Port n.6 mode bits + 24 + 2 + + + CNF6 + Port n.6 configuration + bits + 26 + 2 + + + MODE7 + Port n.7 mode bits + 28 + 2 + + + CNF7 + Port n.7 configuration + bits + 30 + 2 + + + + + INDR + INDR + Port input data register + (GPIOn_INDR) + 0x8 + 0x20 + read-only + 0x00000000 + + + IDR0 + Port input data + 0 + 1 + + + IDR1 + Port input data + 1 + 1 + + + IDR2 + Port input data + 2 + 1 + + + IDR3 + Port input data + 3 + 1 + + + IDR4 + Port input data + 4 + 1 + + + IDR5 + Port input data + 5 + 1 + + + IDR6 + Port input data + 6 + 1 + + + IDR7 + Port input data + 7 + 1 + + + + + OUTDR + OUTDR + Port output data register + (GPIOn_OUTDR) + 0xC + 0x20 + read-write + 0x00000000 + + + ODR0 + Port output data + 0 + 1 + + + ODR1 + Port output data + 1 + 1 + + + ODR2 + Port output data + 2 + 1 + + + ODR3 + Port output data + 3 + 1 + + + ODR4 + Port output data + 4 + 1 + + + ODR5 + Port output data + 5 + 1 + + + ODR6 + Port output data + 6 + 1 + + + ODR7 + Port output data + 7 + 1 + + + + + BSHR + BSHR + Port bit set/reset register + (GPIOn_BSHR) + 0x10 + 0x20 + write-only + 0x00000000 + + + BS0 + Set bit 0 + 0 + 1 + + + BS1 + Set bit 1 + 1 + 1 + + + BS2 + Set bit 1 + 2 + 1 + + + BS3 + Set bit 3 + 3 + 1 + + + BS4 + Set bit 4 + 4 + 1 + + + BS5 + Set bit 5 + 5 + 1 + + + BS6 + Set bit 6 + 6 + 1 + + + BS7 + Set bit 7 + 7 + 1 + + + BR0 + Reset bit 0 + 16 + 1 + + + BR1 + Reset bit 1 + 17 + 1 + + + BR2 + Reset bit 2 + 18 + 1 + + + BR3 + Reset bit 3 + 19 + 1 + + + BR4 + Reset bit 4 + 20 + 1 + + + BR5 + Reset bit 5 + 21 + 1 + + + BR6 + Reset bit 6 + 22 + 1 + + + BR7 + Reset bit 7 + 23 + 1 + + + + + BCR + BCR + Port bit reset register + (GPIOn_BCR) + 0x14 + 0x20 + write-only + 0x00000000 + + + BR0 + Reset bit 0 + 0 + 1 + + + BR1 + Reset bit 1 + 1 + 1 + + + BR2 + Reset bit 1 + 2 + 1 + + + BR3 + Reset bit 3 + 3 + 1 + + + BR4 + Reset bit 4 + 4 + 1 + + + BR5 + Reset bit 5 + 5 + 1 + + + BR6 + Reset bit 6 + 6 + 1 + + + BR7 + Reset bit 7 + 7 + 1 + + + + + LCKR + LCKR + Port configuration lock + register + 0x18 + 0x20 + read-write + 0x00000000 + + + LCK0 + Port A Lock bit 0 + 0 + 1 + + + LCK1 + Port A Lock bit 1 + 1 + 1 + + + LCK2 + Port A Lock bit 2 + 2 + 1 + + + LCK3 + Port A Lock bit 3 + 3 + 1 + + + LCK4 + Port A Lock bit 4 + 4 + 1 + + + LCK5 + Port A Lock bit 5 + 5 + 1 + + + LCK6 + Port A Lock bit 6 + 6 + 1 + + + LCK7 + Port A Lock bit 7 + 7 + 1 + + + LCKK + Lock key + 8 + 1 + + + + + + + GPIOC + 0x40011000 + + + GPIOD + 0x40011400 + + + AFIO + Alternate function I/O + AFIO + 0x40010000 + + 0x0 + 0x400 + registers + + + + PCFR1 + PCFR1 + AF remap and debug I/O configuration + register (AFIO_PCFR1) + 0x4 + 0x20 + 0x00000000 + + + SPI1_RM + SPI1 remapping + 0 + 1 + read-write + + + I2C1_RM + I2C1 remapping + 1 + 1 + read-write + + + USART1_RM + USART1 remapping + 2 + 1 + read-write + + + TIM1_RM + TIM1 remapping + 6 + 2 + read-write + + + TIM2_RM + TIM2 remapping + 8 + 2 + read-write + + + PA12_RM + Port A1/Port A2 mapping on + OSCIN/OSCOUT + 15 + 1 + read-write + + + ADC1_ETRGINJ_RM + ADC 1 External trigger injected conversion remapping + 17 + 1 + read-write + + + ADC1_ETRGREG_RM + ADC 1 external trigger regular conversion remapping + 18 + 1 + read-write + + + USART1REMAP1 + USART1 remapping + 21 + 1 + read-write + + + I2C1REMAP1 + I2C1 remapping + 22 + 1 + read-write + + + TIM1_1_RM + TIM1_CH1 channel selection + 23 + 1 + read-write + + + SWCFG + Serial wire JTAG + configuration + 24 + 3 + write-only + + + + + EXTICR + EXTICR + External interrupt configuration register + (AFIO_EXTICR) + 0x08 + 0x20 + read-write + 0x00000000 + + + EXTI0 + EXTI0 configuration + 0 + 2 + + + EXTI1 + EXTI1 configuration + 2 + 2 + + + EXTI2 + EXTI2 configuration + 4 + 2 + + + EXTI3 + EXTI3 configuration + 6 + 2 + + + EXTI4 + EXTI4 configuration + 8 + 2 + + + EXTI5 + EXTI5 configuration + 10 + 2 + + + EXTI6 + EXTI6 configuration + 12 + 2 + + + EXTI7 + EXTI7 configuration + 14 + 2 + + + + + + + EXTI + EXTI + EXTI + 0x40010400 + + 0x00 + 0x400 + registers + + + EXTI7_0 + EXTI Line[7:0] interrupt + 20 + + + + INTENR + INTENR + Interrupt mask register + (EXTI_INTENR) + 0x00 + 0x20 + read-write + 0x00000000 + + + MR0 + Interrupt Mask on line 0 + 0 + 1 + + + MR1 + Interrupt Mask on line 1 + 1 + 1 + + + MR2 + Interrupt Mask on line 2 + 2 + 1 + + + MR3 + Interrupt Mask on line 3 + 3 + 1 + + + MR4 + Interrupt Mask on line 4 + 4 + 1 + + + MR5 + Interrupt Mask on line 5 + 5 + 1 + + + MR6 + Interrupt Mask on line 6 + 6 + 1 + + + MR7 + Interrupt Mask on line 7 + 7 + 1 + + + MR8 + Interrupt Mask on line 8 + 8 + 1 + + + MR9 + Interrupt Mask on line 9 + 9 + 1 + + + + + EVENR + EVENR + Event mask register (EXTI_EVENR) + 0x04 + 0x20 + read-write + 0x00000000 + + + MR0 + Event Mask on line 0 + 0 + 1 + + + MR1 + Event Mask on line 1 + 1 + 1 + + + MR2 + Event Mask on line 2 + 2 + 1 + + + MR3 + Event Mask on line 3 + 3 + 1 + + + MR4 + Event Mask on line 4 + 4 + 1 + + + MR5 + Event Mask on line 5 + 5 + 1 + + + MR6 + Event Mask on line 6 + 6 + 1 + + + MR7 + Event Mask on line 7 + 7 + 1 + + + MR8 + Event Mask on line 8 + 8 + 1 + + + MR9 + Event Mask on line 9 + 9 + 1 + + + + + RTENR + RTENR + Rising Trigger selection register + (EXTI_RTENR) + 0x08 + 0x20 + read-write + 0x00000000 + + + TR0 + Rising trigger event configuration of + line 0 + 0 + 1 + + + TR1 + Rising trigger event configuration of + line 1 + 1 + 1 + + + TR2 + Rising trigger event configuration of + line 2 + 2 + 1 + + + TR3 + Rising trigger event configuration of + line 3 + 3 + 1 + + + TR4 + Rising trigger event configuration of + line 4 + 4 + 1 + + + TR5 + Rising trigger event configuration of + line 5 + 5 + 1 + + + TR6 + Rising trigger event configuration of + line 6 + 6 + 1 + + + TR7 + Rising trigger event configuration of + line 7 + 7 + 1 + + + TR8 + Rising trigger event configuration of + line 8 + 8 + 1 + + + TR9 + Rising trigger event configuration of + line 9 + 9 + 1 + + + + + FTENR + FTENR + Falling Trigger selection register + (EXTI_FTENR) + 0xC + 0x20 + read-write + 0x00000000 + + + TR0 + Falling trigger event configuration of + line 0 + 0 + 1 + + + TR1 + Falling trigger event configuration of + line 1 + 1 + 1 + + + TR2 + Falling trigger event configuration of + line 2 + 2 + 1 + + + TR3 + Falling trigger event configuration of + line 3 + 3 + 1 + + + TR4 + Falling trigger event configuration of + line 4 + 4 + 1 + + + TR5 + Falling trigger event configuration of + line 5 + 5 + 1 + + + TR6 + Falling trigger event configuration of + line 6 + 6 + 1 + + + TR7 + Falling trigger event configuration of + line 7 + 7 + 1 + + + TR8 + Falling trigger event configuration of + line 8 + 8 + 1 + + + TR9 + Falling trigger event configuration of + line 9 + 9 + 1 + + + + + SWIEVR + SWIEVR + Software interrupt event register + (EXTI_SWIEVR) + 0x10 + 0x20 + read-write + 0x00000000 + + + SWIER0 + Software Interrupt on line + 0 + 0 + 1 + + + SWIER1 + Software Interrupt on line + 1 + 1 + 1 + + + SWIER2 + Software Interrupt on line + 2 + 2 + 1 + + + SWIER3 + Software Interrupt on line + 3 + 3 + 1 + + + SWIER4 + Software Interrupt on line + 4 + 4 + 1 + + + SWIER5 + Software Interrupt on line + 5 + 5 + 1 + + + SWIER6 + Software Interrupt on line + 6 + 6 + 1 + + + SWIER7 + Software Interrupt on line + 7 + 7 + 1 + + + SWIER8 + Software Interrupt on line + 8 + 8 + 1 + + + SWIER9 + Software Interrupt on line + 9 + 9 + 1 + + + + + INTFR + INTFR + Pending register (EXTI_INTFR) + 0x14 + 0x20 + read-write + 0x00000000 + + + IF0 + Pending bit 0 + 0 + 1 + + + IF1 + Pending bit 1 + 1 + 1 + + + IF2 + Pending bit 2 + 2 + 1 + + + IF3 + Pending bit 3 + 3 + 1 + + + IF4 + Pending bit 4 + 4 + 1 + + + IF5 + Pending bit 5 + 5 + 1 + + + IF6 + Pending bit 6 + 6 + 1 + + + IF7 + Pending bit 7 + 7 + 1 + + + IF8 + Pending bit 8 + 8 + 1 + + + IF9 + Pending bit 9 + 9 + 1 + + + + + + + DMA1 + DMA1 controller + DMA1 + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_Channel1 + DMA1 Channel 1 global interrupt + 22 + + + DMA1_Channel2 + DMA1 Channel 2 global interrupt + 23 + + + DMA1_Channel3 + DMA1 Channel 3 global interrupt + 24 + + + DMA1_Channel4 + DMA1 Channel 4 global interrupt + 25 + + + DMA1_Channel5 + DMA1 Channel 5 global interrupt + 26 + + + DMA1_Channel6 + DMA1 Channel 6 global interrupt + 27 + + + DMA1_Channel7 + DMA1 Channel 7 global interrupt + 28 + + + + INTFR + INTFR + DMA interrupt status register + (DMA_INTFR) + 0x0 + 0x20 + read-only + 0x00000000 + + + GIF1 + Channel 1 Global interrupt + flag + 0 + 1 + + + TCIF1 + Channel 1 Transfer Complete + flag + 1 + 1 + + + HTIF1 + Channel 1 Half Transfer Complete + flag + 2 + 1 + + + TEIF1 + Channel 1 Transfer Error + flag + 3 + 1 + + + GIF2 + Channel 2 Global interrupt + flag + 4 + 1 + + + TCIF2 + Channel 2 Transfer Complete + flag + 5 + 1 + + + HTIF2 + Channel 2 Half Transfer Complete + flag + 6 + 1 + + + TEIF2 + Channel 2 Transfer Error + flag + 7 + 1 + + + GIF3 + Channel 3 Global interrupt + flag + 8 + 1 + + + TCIF3 + Channel 3 Transfer Complete + flag + 9 + 1 + + + HTIF3 + Channel 3 Half Transfer Complete + flag + 10 + 1 + + + TEIF3 + Channel 3 Transfer Error + flag + 11 + 1 + + + GIF4 + Channel 4 Global interrupt + flag + 12 + 1 + + + TCIF4 + Channel 4 Transfer Complete + flag + 13 + 1 + + + HTIF4 + Channel 4 Half Transfer Complete + flag + 14 + 1 + + + TEIF4 + Channel 4 Transfer Error + flag + 15 + 1 + + + GIF5 + Channel 5 Global interrupt + flag + 16 + 1 + + + TCIF5 + Channel 5 Transfer Complete + flag + 17 + 1 + + + HTIF5 + Channel 5 Half Transfer Complete + flag + 18 + 1 + + + TEIF5 + Channel 5 Transfer Error + flag + 19 + 1 + + + GIF6 + Channel 6 Global interrupt + flag + 20 + 1 + + + TCIF6 + Channel 6 Transfer Complete + flag + 21 + 1 + + + HTIF6 + Channel 6 Half Transfer Complete + flag + 22 + 1 + + + TEIF6 + Channel 6 Transfer Error + flag + 23 + 1 + + + GIF7 + Channel 7 Global interrupt + flag + 24 + 1 + + + TCIF7 + Channel 7 Transfer Complete + flag + 25 + 1 + + + HTIF7 + Channel 7 Half Transfer Complete + flag + 26 + 1 + + + TEIF7 + Channel 7 Transfer Error + flag + 27 + 1 + + + + + INTFCR + INTFCR + DMA interrupt flag clear register + (DMA_INTFCR) + 0x4 + 0x20 + write-only + 0x00000000 + + + CGIF1 + Channel 1 Global interrupt + clear + 0 + 1 + + + CGIF2 + Channel 2 Global interrupt + clear + 4 + 1 + + + CGIF3 + Channel 3 Global interrupt + clear + 8 + 1 + + + CGIF4 + Channel 4 Global interrupt + clear + 12 + 1 + + + CGIF5 + Channel 5 Global interrupt + clear + 16 + 1 + + + CGIF6 + Channel 6 Global interrupt + clear + 20 + 1 + + + CGIF7 + Channel 7 Global interrupt + clear + 24 + 1 + + + CTCIF1 + Channel 1 Transfer Complete + clear + 1 + 1 + + + CTCIF2 + Channel 2 Transfer Complete + clear + 5 + 1 + + + CTCIF3 + Channel 3 Transfer Complete + clear + 9 + 1 + + + CTCIF4 + Channel 4 Transfer Complete + clear + 13 + 1 + + + CTCIF5 + Channel 5 Transfer Complete + clear + 17 + 1 + + + CTCIF6 + Channel 6 Transfer Complete + clear + 21 + 1 + + + CTCIF7 + Channel 7 Transfer Complete + clear + 25 + 1 + + + CHTIF1 + Channel 1 Half Transfer + clear + 2 + 1 + + + CHTIF2 + Channel 2 Half Transfer + clear + 6 + 1 + + + CHTIF3 + Channel 3 Half Transfer + clear + 10 + 1 + + + CHTIF4 + Channel 4 Half Transfer + clear + 14 + 1 + + + CHTIF5 + Channel 5 Half Transfer + clear + 18 + 1 + + + CHTIF6 + Channel 6 Half Transfer + clear + 22 + 1 + + + CHTIF7 + Channel 7 Half Transfer + clear + 26 + 1 + + + CTEIF1 + Channel 1 Transfer Error + clear + 3 + 1 + + + CTEIF2 + Channel 2 Transfer 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+ + + + DATAR + DATAR + data register + 0xC + 0x20 + read-write + 0x0000 + + + DATAR + Data register + 0 + 16 + + + + + CRCR + CRCR + CRCR polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CRCPOLY + CRC polynomial register + 0 + 16 + + + + + RCRCR + RCRCR + RX CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RXCRC + Rx CRC register + 0 + 16 + + + + + TCRCR + TCRCR + send CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TXCRC + Tx CRC register + 0 + 16 + + + + + HSCR + HSCR + high speed control register + 0x24 + 0x20 + 0x0000 + + + HSRXEN + High speed mode read enable + 0 + 1 + write-only + + + + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 32 + + + + STATR + STATR + Status register + 0x0 + 0x20 + 0x000000C0 + + + CTS + CTS flag + 9 + 1 + read-write + + + LBD + LIN break detection flag + 8 + 1 + read-write + + + TXE + Transmit data register + empty + 7 + 1 + read-only + + + TC + Transmission complete + 6 + 1 + read-write + + + RXNE + Read data register not + empty + 5 + 1 + read-write + + + IDLE + IDLE line detected + 4 + 1 + read-only + + + ORE + Overrun error + 3 + 1 + read-only + + + NE + Noise error flag + 2 + 1 + read-only + + + FE + Framing error + 1 + 1 + read-only + + + PE + Parity error + 0 + 1 + read-only + + + + + DATAR + DATAR + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DR + Data value + 0 + 9 + + + + + BRR + BRR + Baud rate register + 0x8 + 0x20 + read-write + 0x00000000 + + + DIV_Mantissa + mantissa of USARTDIV + 4 + 12 + + + DIV_Fraction + fraction of USARTDIV + 0 + 4 + + + + + CTLR1 + CTLR1 + Control register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + UE + USART enable + 13 + 1 + + + M + Word length + 12 + 1 + + + WAKE + Wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + TXE interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + RWU + Receiver wakeup + 1 + 1 + + + SBK + Send break + 0 + 1 + + + + + CTLR2 + CTLR2 + Control register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + LINEN + LIN mode enable + 14 + 1 + + + STOP + STOP bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CPOL + Clock polarity + 10 + 1 + + + CPHA + Clock phase + 9 + 1 + + + LBCL + Last bit clock pulse + 8 + 1 + + + LBDIE + LIN break detection interrupt + enable + 6 + 1 + + + LBDL + lin break detection length + 5 + 1 + + + ADD + Address of the USART node + 0 + 4 + + + + + CTLR3 + CTLR3 + Control register 3 + 0x14 + 0x20 + read-write + 0x00000000 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + SCEN + Smartcard mode enable + 5 + 1 + + + NACK + Smartcard NACK enable + 4 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + IrDA low-power + 2 + 1 + + + IREN + IrDA mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + GPR + GPR + Guard time and prescaler + register + 0x18 + 0x20 + read-write + 0x00000000 + + + GT + Guard time value + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + + + ADC1 + Analog to digital converter + ADC1 + 0x40012400 + + 0x0 + 0x400 + registers + + + ADC + ADC global interrupt + 29 + + + + STATR + STATR + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + STRT + Regular channel start flag + 4 + 1 + + + JSTRT + Injected channel start + flag + 3 + 1 + + + JEOC + Injected channel end of + conversion + 2 + 1 + + + EOC + Regular channel end of + conversion + 1 + 1 + + + AWD + Analog watchdog flag + 0 + 1 + + + + + CTLR1 + CTLR1 + control register 1/TKEY_V_CTLR + 0x4 + 0x20 + read-write + 0x00000000 + + + CALVOL + ADC Calibration voltage selection + 25 + 2 + + + AWDEN + Analog watchdog enable on regular + channels + 23 + 1 + + + JAWDEN + Analog watchdog enable on injected + channels + 22 + 1 + + + DISCNUM + Discontinuous mode channel + count + 13 + 3 + + + JDISCEN + Discontinuous mode on injected + channels + 12 + 1 + + + DISCEN + Discontinuous mode on regular + channels + 11 + 1 + + + JAUTO + Automatic injected group + conversion + 10 + 1 + + + AWDSGL + Enable the watchdog on a single channel + in scan mode + 9 + 1 + + + SCAN + Scan mode enable + 8 + 1 + + + JEOCIE + Interrupt enable for injected + channels + 7 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 6 + 1 + + + EOCIE + Interrupt enable for EOC + 5 + 1 + + + AWDCH + Analog watchdog channel select + bits + 0 + 5 + + + + + CTLR2 + CTLR2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + SWSTART + Start conversion of regular + channels + 22 + 1 + + + JSWSTART + Start conversion of injected + channels + 21 + 1 + + + EXTTRIG + External trigger conversion mode for + regular channels + 20 + 1 + + + EXTSEL + External event select for regular + group + 17 + 3 + + + JEXTTRIG + External trigger conversion mode for + injected channels + 15 + 1 + + + JEXTSEL + External event select for injected + group + 12 + 3 + + + ALIGN + Data alignment + 11 + 1 + + + DMA + Direct memory access mode + 8 + 1 + + + RSTCAL + Reset calibration + 3 + 1 + + + CAL + A/D calibration + 2 + 1 + + + CONT + Continuous conversion + 1 + 1 + + + ADON + A/D converter ON / OFF + 0 + 1 + + + + + SAMPTR1 + SAMPTR1_CHARGE1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + SMP10 + Channel 10 sample time + selection + 0 + 3 + + + SMP11 + Channel 11 sample time + selection + 3 + 3 + + + SMP12_TKCG12 + Channel 12 sample time + selection + 6 + 3 + + + SMP13 + Channel 13 sample time + selection + 9 + 3 + + + SMP14 + Channel 14 sample time + selection + 12 + 3 + + + SMP15 + Channel 15 sample time + selection + 15 + 3 + + + + + SAMPTR2 + SAMPTR2_CHARGE2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + SMP0 + Channel 0 sample time + selection + 0 + 3 + + + SMP1 + Channel 1 sample time + selection + 3 + 3 + + + SMP2 + Channel 2 sample time + selection + 6 + 3 + + + SMP3 + Channel 3 sample time + selection + 9 + 3 + + + SMP4 + Channel 4 sample time + selection + 12 + 3 + + + SMP5 + Channel 5 sample time + selection + 15 + 3 + + + SMP6_TKCG6 + Channel 6 sample time + selection + 18 + 3 + + + SMP7 + Channel 7 sample time + selection + 21 + 3 + + + SMP8 + Channel 8 sample time + selection + 24 + 3 + + + SMP9 + Channel 9 sample time + selection + 27 + 3 + + + + + IOFR1 + IOFR1 + injected channel data offset register + x + 0x14 + 0x20 + read-write + 0x00000000 + + + JOFFSET1 + Data offset for injected channel + x + 0 + 10 + + + + + IOFR2 + IOFR2 + injected channel data offset register + x + 0x18 + 0x20 + read-write + 0x00000000 + + + JOFFSET2 + Data offset for injected channel + x + 0 + 10 + + + + + IOFR3 + IOFR3 + injected channel data offset register + x + 0x1C + 0x20 + read-write + 0x00000000 + + + JOFFSET3 + Data offset for injected channel + x + 0 + 10 + + + + + IOFR4 + IOFR4 + injected channel data offset register + x + 0x20 + 0x20 + read-write + 0x00000000 + + + JOFFSET4 + Data offset for injected channel + x + 0 + 10 + + + + + WDHTR + WDHTR + watchdog higher threshold + register + 0x24 + 0x20 + read-write + 0x000003FF + + + HT + Analog watchdog higher + threshold + 0 + 10 + + + + + WDLTR + WDLTR + watchdog lower threshold + register + 0x28 + 0x20 + read-write + 0x00000000 + + + LT + Analog watchdog lower + threshold + 0 + 10 + + + + + RSQR1 + RSQR1 + regular sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + L + Regular channel sequence + length + 20 + 4 + + + SQ16 + 16th conversion in regular + sequence + 15 + 5 + + + SQ15 + 15th conversion in regular + sequence + 10 + 5 + + + SQ14 + 14th conversion in regular + sequence + 5 + 5 + + + SQ13 + 13th conversion in regular + sequence + 0 + 5 + + + + + RSQR2 + RSQR2 + regular sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + SQ12 + 12th conversion in regular + sequence + 25 + 5 + + + SQ11 + 11th conversion in regular + sequence + 20 + 5 + + + SQ10 + 10th conversion in regular + sequence + 15 + 5 + + + SQ9 + 9th conversion in regular + sequence + 10 + 5 + + + SQ8 + 8th conversion in regular + sequence + 5 + 5 + + + SQ7 + 7th conversion in regular + sequence + 0 + 5 + + + + + RSQR3 + RSQR3 + regular sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + SQ6 + 6th conversion in regular + sequence + 25 + 5 + + + SQ5 + 5th conversion in regular + sequence + 20 + 5 + + + SQ4 + 4th conversion in regular + sequence + 15 + 5 + + + SQ3 + 3rd conversion in regular + sequence + 10 + 5 + + + SQ2 + 2nd conversion in regular + sequence + 5 + 5 + + + SQ1 + 1st conversion in regular + sequence + 0 + 5 + + + + + ISQR + ISQR + injected sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + JL + Injected sequence length + 20 + 2 + + + JSQ4 + 4th conversion in injected + sequence + 15 + 5 + + + JSQ3 + 3rd conversion in injected + sequence + 10 + 5 + + + JSQ2 + 2nd conversion in injected + sequence + 5 + 5 + + + JSQ1 + 1st conversion in injected + sequence + 0 + 5 + + + + + IDATAR1 + IDATAR1 + injected data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + IDATA + Injected data + 0 + 16 + + + + + IDATAR2 + IDATAR2 + injected data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + IDATA + Injected data + 0 + 16 + + + + + IDATAR3 + IDATAR3 + injected data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + IDATA + Injected data + 0 + 16 + + + + + IDATAR4 + IDATAR4 + injected data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + IDATA + Injected data + 0 + 16 + + + + + RDATAR + RDATAR + regular data register + 0x4C + 0x20 + read-only + 0x00000000 + + + DATA + Regular data + 0 + 32 + + + + + DLYR + DLYR + delay data register + 0x50 + 0x20 + read-write + 0x00000000 + + + DLYVLU + External trigger data delay time configuration + 0 + 9 + + + DLYSRC + External trigger source delay selection + 9 + 1 + + + + + + + DBG + Debug support + DBG + 0xE000D000 + + 0x0 + 0x400 + registers + + + + CR + CR + DBGMCU_CFGR1 + 0x0 + 0x20 + read-write + 0x0 + + + SLEEP + Debug Sleep mode + 0 + 1 + + + STOP + Debug stop mode + 1 + 1 + + + STANDBY + Debug standby mode + 2 + 1 + + + IWDG_STOP + IWDG_STOP + 8 + 1 + + + WWDG_STOP + WWDG_STOP + 9 + 1 + + + TIM1_STOP + TIM1_STOP + 12 + 1 + + + TIM2_STOP + TIM2_STOP + 13 + 1 + + + + + + + ESIG + Device electronic signature + ESIG + 0x1FFFF7E0 + + 0x0 + 0x14 + registers + + + + FLACAP + FLACAP + Flash capacity register + 0x0 + 0x10 + read-only + 0x0000 + + + F_SIZE_15_0 + Flash size + 0 + 16 + + + + + UNIID1 + UNIID1 + Unique identity 1 + 0x8 + 0x20 + read-only + 0x00000000 + + + U_ID + Unique identity[31:0] + 0 + 32 + + + + + UNIID2 + UNIID2 + Unique identity 2 + 0xC + 0x20 + read-only + 0x00000000 + + + U_ID + Unique identity[63:32] + 0 + 32 + + + + + UNIID3 + UNIID3 + Unique identity 3 + 0x10 + 0x20 + read-only + 0x00000000 + + + U_ID + Unique identity[95:64] + 0 + 32 + + + + + + + FLASH + FLASH + FLASH + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + Flash global interrupt + 18 + + + + ACTLR + ACTLR + Flash key register + 0x0 + 0x20 + 0x00000000 + + + LATENCY + Number of FLASH wait states + 0 + 2 + read-write + + + + + KEYR + KEYR + Flash key register + 0x4 + 0x20 + write-only + 0x00000000 + + + KEYR + FPEC key + 0 + 32 + + + + + OBKEYR + OBKEYR + Flash option key register + 0x8 + 0x20 + write-only + 0x00000000 + + + OPTKEY + Option byte key + 0 + 32 + + + + + STATR + STATR + Status register + 0xC + 0x20 + 0x00008000 + + + BOOT_LOCK + BOOT lock + 15 + 1 + read-write + + + BOOT_MODE + BOOT mode + 14 + 1 + read-write + + + EOP + End of operation + 5 + 1 + read-write + + + WRPRTERR + Write protection error + 4 + 1 + read-write + + + BSY + Busy + 0 + 1 + read-only + + + + + CTLR + CTLR + Control register + 0x10 + 0x20 + read-write + 0x00008080 + + + PG + Programming + 0 + 1 + + + PER + Page Erase + 1 + 1 + + + MER + Mass Erase + 2 + 1 + + + OBPG + Option byte programming + 4 + 1 + + + OBER + Option byte erase + 5 + 1 + + + STRT + Start + 6 + 1 + + + LOCK + Lock + 7 + 1 + + + OBWRE + Option bytes write enable + 9 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + EOPIE + End of operation interrupt + enable + 12 + 1 + + + FLOCK + Fast programmable lock + 15 + 1 + + + FTPG + Fast programming + 16 + 1 + + + FTER + Fast erase + 17 + 1 + + + BUFLOAD + Buffer load + 18 + 1 + + + BUFRST + Buffer reset + 19 + 1 + + + + + ADDR + ADDR + Flash address register + 0x14 + 0x20 + write-only + 0x00000000 + + + FAR + Flash Address + 0 + 32 + + + + + OBR + OBR + Option byte register + 0x1C + 0x20 + read-only + 0x00000000 + + + OBERR + Option byte error + 0 + 1 + + + RDPRT + Read protection + 1 + 1 + + + IWDG_SW + IWDG_SW + 2 + 1 + + + STANDY_RST + STANDY_RST + 4 + 1 + + + RST_MODE + CFG_RST_MODE + 5 + 2 + + + STATR_MODE + STATR MODE + 7 + 1 + + + DATA0 + DATA0 + 10 + 8 + + + DATA1 + DATA1 + 18 + 8 + + + + + WPR + WPR + Write protection register + 0x20 + 0x20 + read-only + 0xFFFFFFFF + + + WRP + Write protect + 0 + 16 + + + + + MODEKEYR + MODEKEYR + Mode select register + 0x24 + 0x20 + write-only + 0x00000000 + + + MODEKEYR + Mode select + 0 + 32 + + + + + BOOT_MODEKEYP + BOOT_MODEKEYP + Boot mode key register + 0x28 + 0x20 + write-only + 0x00000000 + + + MODEKEYR + Boot mode key + 0 + 32 + + + + + + + PFIC + Programmable Fast Interrupt + Controller + PFIC + 0xE000E000 + + 0x00 + 0x1100 + registers + + + + ISR1 + ISR1 + Interrupt Status + Register + 0x00 + 0x20 + read-only + 0x0000000C + + + INTENSTA2_3 + Interrupt ID Status + 2 + 2 + + + INTENSTA12 + Interrupt ID Status + 12 + 1 + + + INTENSTA14 + Interrupt ID Status + 14 + 1 + + + INTENSTA16_31 + Interrupt ID Status + 16 + 16 + + + + + ISR2 + ISR2 + Interrupt Status + Register + 0x04 + 0x20 + read-only + 0x00000000 + + + INTENSTA + Interrupt ID Status + 0 + 7 + + + + + IPR1 + IPR1 + Interrupt Pending Register + 0x20 + 0x20 + read-only + 0x00000000 + + + PENDSTA2_3 + PENDSTA + 2 + 2 + + + PENDSTA12 + PENDSTA + 12 + 1 + + + INTENSTA14 + PENDSTA + 14 + 1 + + + INTENSTA16_31 + PENDSTA + 16 + 16 + + + + + IPR2 + IPR2 + Interrupt Pending Register + 0x24 + 0x20 + read-only + 0x00000000 + + + PENDSTA32_38 + PENDSTA + 0 + 7 + + + + + ITHRESDR + ITHRESDR + Interrupt Priority + Register + 0x40 + 0x20 + read-write + 0x00000000 + + + THRESHOLD + THRESHOLD + 0 + 8 + + + + + CFGR + CFGR + Interrupt Config Register + 0x48 + 0x20 + 0x00000000 + + + RSTSYS + RESET System + write-only + 7 + 1 + + + KEYCODE + KEYCODE + write-only + 16 + 16 + + + + + GISR + GISR + Interrupt Global Register + 0x4C + 0x20 + read-only + 0x00000000 + + + NESTSTA + NESTSTA + 0 + 8 + + + GACTSTA + GACTSTA + 8 + 1 + + + GPENDSTA + GPENDSTA + 9 + 1 + + + + + VTFIDR + VTFIDR + ID Config Register + 0x50 + 0x20 + read-write + 0x00000000 + + + VTFID0 + VTFID0 + 0 + 8 + + + VTFID1 + VTFID1 + 8 + 8 + + + + + VTFADDRR0 + VTFADDRR0 + Interrupt 0 address + Register + 0x60 + 0x20 + read-write + 0x00000000 + + + VTF0EN + VTF0EN + 0 + 1 + + + ADDR0 + ADDR0 + 1 + 31 + + + + + VTFADDRR1 + VTFADDRR1 + Interrupt 1 address + Register + 0x64 + 0x20 + read-write + 0x00000000 + + + VTF1EN + VTF1EN + 0 + 1 + + + ADDR1 + ADDR1 + 1 + 31 + + + + + IENR1 + IENR1 + Interrupt Setting Register + 0x100 + 0x20 + write-only + 0x00000000 + + + INTEN12 + INTEN12 + 12 + 1 + + + INTEN14 + INTEN14 + 14 + 1 + + + INTEN16_31 + INTEN16_31 + 16 + 16 + + + + + IENR2 + IENR2 + Interrupt Setting Register + 0x104 + 0x20 + write-only + 0x00000000 + + + INTEN + INTEN32_38 + 0 + 7 + + + + + IRER1 + IRER1 + Interrupt Clear Register + 0x180 + 0x20 + write-only + 0x00000000 + + + INTRSET12 + INTRSET12 + 12 + 1 + + + INTRSET14 + INTRSET14 + 14 + 1 + + + INTRSET16_31 + INTRSET16_31 + 16 + 16 + + + + + IRER2 + IRER2 + Interrupt Clear Register + 0x184 + 0x20 + write-only + 0x00000000 + + + INTRSET38_32 + INTRSET38_32 + 0 + 7 + + + + + IPSR1 + IPSR1 + Interrupt Pending Register + 0x200 + 0x20 + write-only + 0x00000000 + + + PENDSET2_3 + PENDSET + 2 + 2 + + + PENDSET12 + PENDSET + 12 + 1 + + + PENDSET14 + PENDSET + 14 + 1 + + + PENDSET16_31 + PENDSET + 16 + 16 + + + + + IPSR2 + IPSR2 + Interrupt Pending Register + 0x204 + 0x20 + write-only + 0x00000000 + + + PENDSET32_38 + PENDSET32_38 + 0 + 7 + + + + + IPRR1 + IPRR1 + Interrupt Pending Clear Register + 0x280 + 0x20 + write-only + 0x00000000 + + + PENDRST2_3 + PENDRESET + 2 + 2 + + + PENDRST12 + PENDRESET + 12 + 1 + + + PENDRST14 + PENDRESET + 14 + 1 + + + PENDRST16_31 + PENDRESET + 16 + 16 + + + + + IPRR2 + IPRR2 + Interrupt Pending Clear Register + 0x284 + 0x20 + write-only + 0x00000000 + + + PENDRST32_38 + PENDRESET32_38 + 0 + 7 + + + + + IACTR1 + IACTR1 + Interrupt ACTIVE Register + 0x300 + 0x20 + write-only + 0x00000000 + + + IACTS2_3 + IACTS + 2 + 2 + + + IACTS12 + IACTS + 12 + 1 + + + IACTS14 + IACTS + 14 + 1 + + + IACTS16_31 + IACTS + 16 + 16 + + + + + IACTR2 + IACTR2 + Interrupt ACTIVE Register + 0x304 + 0x20 + write-only + 0x00000000 + + + IACTS + IACTS + 0 + 7 + + + + + IPRIOR0 + IPRIOR0 + Interrupt Priority Register + 0x400 + 0x8 + read-write + 0x00000000 + + + IPRIOR1 + IPRIOR1 + Interrupt Priority Register + 0x401 + 0x8 + read-write + 0x00000000 + + + IPRIOR2 + IPRIOR2 + Interrupt Priority Register + 0x402 + 0x8 + read-write + 0x00000000 + + + IPRIOR3 + IPRIOR3 + Interrupt Priority Register + 0x403 + 0x8 + read-write + 0x00000000 + + + IPRIOR4 + IPRIOR4 + Interrupt Priority Register + 0x404 + 0x8 + read-write + 0x00000000 + + + IPRIOR5 + IPRIOR5 + Interrupt Priority Register + 0x405 + 0x8 + read-write + 0x00000000 + + + IPRIOR6 + IPRIOR6 + Interrupt Priority Register + 0x406 + 0x8 + read-write + 0x00000000 + + + IPRIOR7 + IPRIOR7 + Interrupt Priority Register + 0x407 + 0x8 + read-write + 0x00000000 + + + IPRIOR8 + IPRIOR8 + Interrupt Priority Register + 0x408 + 0x8 + read-write + 0x00000000 + + + IPRIOR9 + IPRIOR9 + Interrupt Priority Register + 0x409 + 0x8 + read-write + 0x00000000 + + + IPRIOR10 + IPRIOR10 + Interrupt Priority Register + 0x40A + 0x8 + read-write + 0x00000000 + + + + IPRIOR11 + IPRIOR11 + Interrupt Priority Register + 0x40B + 0x8 + read-write + 0x00000000 + + + IPRIOR12 + IPRIOR12 + Interrupt Priority Register + 0x40C + 0x8 + read-write + 0x00000000 + + + IPRIOR13 + IPRIOR13 + Interrupt Priority Register + 0x40D + 0x8 + read-write + 0x00000000 + + + IPRIOR14 + IPRIOR14 + Interrupt Priority Register + 0x40E + 0x8 + read-write + 0x00000000 + + + IPRIOR15 + IPRIOR15 + Interrupt Priority Register + 0x40F + 0x8 + read-write + 0x00000000 + + + IPRIOR16 + IPRIOR6 + Interrupt Priority Register + 0x410 + 0x8 + read-write + 0x00000000 + + + IPRIOR17 + IPRIOR7 + Interrupt Priority Register + 0x411 + 0x8 + read-write + 0x00000000 + + + IPRIOR18 + IPRIOR8 + Interrupt Priority Register + 0x412 + 0x8 + read-write + 0x00000000 + + + IPRIOR19 + IPRIOR9 + Interrupt Priority Register + 0x413 + 0x8 + read-write + 0x00000000 + + + IPRIOR20 + IPRIOR20 + Interrupt Priority Register + 0x414 + 0x8 + read-write + 0x00000000 + + + + IPRIOR21 + IPRIOR21 + Interrupt Priority Register + 0x415 + 0x8 + read-write + 0x00000000 + + + IPRIOR22 + IPRIOR22 + Interrupt Priority Register + 0x416 + 0x8 + read-write + 0x00000000 + + + IPRIOR23 + IPRIOR23 + Interrupt Priority Register + 0x417 + 0x8 + read-write + 0x00000000 + + + IPRIOR24 + IPRIOR24 + Interrupt Priority Register + 0x418 + 0x8 + read-write + 0x00000000 + + + IPRIOR25 + IPRIOR25 + Interrupt Priority Register + 0x419 + 0x8 + read-write + 0x00000000 + + + IPRIOR26 + IPRIOR26 + Interrupt Priority Register + 0x41A + 0x8 + read-write + 0x00000000 + + + IPRIOR27 + IPRIOR27 + Interrupt Priority Register + 0x41B + 0x8 + read-write + 0x00000000 + + + IPRIOR28 + IPRIOR28 + Interrupt Priority Register + 0x41C + 0x8 + read-write + 0x00000000 + + + IPRIOR29 + IPRIOR29 + Interrupt Priority Register + 0x41D + 0x8 + read-write + 0x00000000 + + + + IPRIOR30 + IPRIOR30 + Interrupt Priority Register + 0x41E + 0x8 + read-write + 0x00000000 + + + IPRIOR31 + IPRIOR31 + Interrupt Priority Register + 0x41F + 0x8 + read-write + 0x00000000 + + + IPRIOR32 + IPRIOR32 + Interrupt Priority Register + 0x420 + 0x8 + read-write + 0x00000000 + + + IPRIOR33 + IPRIOR33 + Interrupt Priority Register + 0x421 + 0x8 + read-write + 0x00000000 + + + IPRIOR34 + IPRIOR34 + Interrupt Priority Register + 0x422 + 0x8 + read-write + 0x00000000 + + + IPRIOR35 + IPRIOR35 + Interrupt Priority Register + 0x423 + 0x8 + read-write + 0x00000000 + + + IPRIOR36 + IPRIOR36 + Interrupt Priority Register + 0x424 + 0x8 + read-write + 0x00000000 + + + IPRIOR37 + IPRIOR37 + Interrupt Priority Register + 0x425 + 0x8 + read-write + 0x00000000 + + + IPRIOR38 + IPRIOR38 + Interrupt Priority Register + 0x426 + 0x8 + read-write + 0x00000000 + + + IPRIOR39 + IPRIOR39 + Interrupt Priority Register + 0x427 + 0x8 + read-write + 0x00000000 + + + + IPRIOR40 + IPRIOR40 + Interrupt Priority Register + 0x428 + 0x8 + read-write + 0x00000000 + + + IPRIOR41 + IPRIOR41 + Interrupt Priority Register + 0x429 + 0x8 + read-write + 0x00000000 + + + IPRIOR42 + IPRIOR42 + Interrupt Priority Register + 0x42A + 0x8 + read-write + 0x00000000 + + + IPRIOR43 + IPRIOR43 + Interrupt Priority Register + 0x42B + 0x8 + read-write + 0x00000000 + + + IPRIOR44 + IPRIOR44 + Interrupt Priority Register + 0x42C + 0x8 + read-write + 0x00000000 + + + IPRIOR45 + IPRIOR45 + Interrupt Priority Register + 0x42D + 0x8 + read-write + 0x00000000 + + + IPRIOR46 + IPRIOR46 + Interrupt Priority Register + 0x42E + 0x8 + read-write + 0x00000000 + + + IPRIOR47 + IPRIOR47 + Interrupt Priority Register + 0x42F + 0x8 + read-write + 0x00000000 + + + IPRIOR48 + IPRIOR48 + Interrupt Priority Register + 0x430 + 0x8 + read-write + 0x00000000 + + + IPRIOR49 + IPRIOR49 + Interrupt Priority Register + 0x431 + 0x8 + read-write + 0x00000000 + + + + IPRIOR50 + IPRIOR50 + Interrupt Priority Register + 0x432 + 0x8 + read-write + 0x00000000 + + + IPRIOR51 + IPRIOR51 + Interrupt Priority Register + 0x433 + 0x8 + read-write + 0x00000000 + + + IPRIOR52 + IPRIOR52 + Interrupt Priority Register + 0x434 + 0x8 + read-write + 0x00000000 + + + IPRIOR53 + IPRIOR53 + Interrupt Priority Register + 0x435 + 0x8 + read-write + 0x00000000 + + + IPRIOR54 + IPRIOR54 + Interrupt Priority Register + 0x436 + 0x8 + read-write + 0x00000000 + + + IPRIOR55 + IPRIOR55 + Interrupt Priority Register + 0x437 + 0x8 + read-write + 0x00000000 + + + IPRIOR56 + IPRIOR56 + Interrupt Priority Register + 0x438 + 0x8 + read-write + 0x00000000 + + + IPRIOR57 + IPRIOR57 + Interrupt Priority Register + 0x439 + 0x8 + read-write + 0x00000000 + + + IPRIOR58 + IPRIOR58 + Interrupt Priority Register + 0x43A + 0x8 + read-write + 0x00000000 + + + IPRIOR59 + IPRIOR59 + Interrupt Priority Register + 0x43B + 0x8 + read-write + 0x00000000 + + + + IPRIOR60 + IPRIOR60 + Interrupt Priority Register + 0x43C + 0x8 + read-write + 0x00000000 + + + IPRIOR61 + IPRIOR61 + Interrupt Priority Register + 0x43D + 0x8 + read-write + 0x00000000 + + + IPRIOR62 + IPRIOR62 + Interrupt Priority Register + 0x43E + 0x8 + read-write + 0x00000000 + + + IPRIOR63 + IPRIOR63 + Interrupt Priority Register + 0x43F + 0x8 + read-write + 0x00000000 + + + SCTLR + SCTLR + System Control Register + 0xd10 + 0x20 + read-write + 0x00000000 + + + SLEEPONEXIT + SLEEPONEXIT + 1 + 1 + + + SLEEPDEEP + SLEEPDEEP + 2 + 1 + + + WFITOWFE + WFITOWFE + 3 + 1 + + + SEVONPEND + SEVONPEND + 4 + 1 + + + SETEVENT + SETEVENT + 5 + 1 + + + SYSRST + SYSRESET + 31 + 1 + + + + + STK_CTLR + STK_CTLR + System counter control register + 0x1000 + 0x20 + 0x00000000 + + + STE + System counter enable + read-write + 0 + 1 + + + STIE + System counter interrupt enable + read-write + 1 + 1 + + + STCLK + System selects the clock source + read-write + 2 + 1 + + + STRE + System reload register + read-write + 3 + 1 + + + MODE + System Mode + read-write + 4 + 1 + + + INIT + System Initialization update + read-write + 5 + 1 + + + SWIE + System software triggered interrupts enable + read-write + 31 + 1 + + + + + STK_SR + System START + 0x1004 + 0x20 + read-write + 0x00000000 + + + CNTIF + CNTIF + 0 + 1 + + + + + STK_CNTL + System counter low register + 0x1008 + 0x20 + read-write + 0x00000000 + + + CNT + CNT + 0 + 32 + + + + + STK_CMPLR + System compare low register + 0x1010 + 0x20 + read-write + 0x00000000 + + + CMP + CMP + 0 + 32 + + + + + + + diff --git a/bsp/wch/ch32/src/cpus/wch_qingke_v2.zig b/bsp/wch/ch32/src/cpus/wch_qingke_v2.zig new file mode 100644 index 0000000..6a18dc1 --- /dev/null +++ b/bsp/wch/ch32/src/cpus/wch_qingke_v2.zig @@ -0,0 +1,47 @@ +const std = @import("std"); +const root = @import("root"); +const microzig = @import("microzig"); + +pub fn enable_interrupts() void { + asm volatile ("csrsi mstatus, 0b1000"); +} + +pub fn disable_interrupts() void { + asm volatile ("csrci mstatus, 0b1000"); +} + +pub fn wfi() void { + asm volatile ("wfi"); +} + +pub fn wfe() void { + const PFIC = microzig.chip.peripherals.PFIC; + // Treats the subsequent wfi instruction as wfe + PFIC.SCTLR.modify(.{ .WFITOWFE = 1 }); + asm volatile ("wfi"); +} + +pub const startup_logic = struct { + extern fn microzig_main() noreturn; + + pub fn _start() callconv(.C) noreturn { + asm volatile ("la gp, __global_pointer$"); + asm volatile ("mv sp, %[eos]" + : + : [eos] "r" (@as(u32, microzig.config.end_of_stack)), + ); + root.initialize_system_memories(); + asm volatile ("csrsi 0x804, 0b111"); // INTSYSCR: enable EABI + Interrupt nesting + HPE + asm volatile ("csrsi mtvec, 0b11"); // mtvec: absolute address + vector table mode + microzig.cpu.enable_interrupts(); + microzig_main(); + } + + export fn _reset_vector() linksection("microzig_flash_start") callconv(.Naked) void { + asm volatile ("j _start"); + } +}; + +pub fn export_startup_logic() void { + @export(startup_logic._start, .{ .name = "_start" }); +} diff --git a/build.zig b/build.zig index a91eb11..8c663ff 100644 --- a/build.zig +++ b/build.zig @@ -23,6 +23,7 @@ const bsps = .{ .{ "bsp/stmicro/stm32", @import("bsp/stmicro/stm32") }, .{ "bsp/espressif/esp", @import("bsp/espressif/esp") }, .{ "bsp/raspberrypi/rp2040", @import("bsp/raspberrypi/rp2040") }, + .{ "bsp/wch/ch32", @import("bsp/wch/ch32") }, }; pub fn build(b: *Build) void { diff --git a/examples/wch/ch32/LICENSE b/examples/wch/ch32/LICENSE new file mode 100644 index 0000000..3364097 --- /dev/null +++ b/examples/wch/ch32/LICENSE @@ -0,0 +1,19 @@ +Copyright (c) Zig Embedded Group contributors + +This software is provided 'as-is', without any express or implied warranty. In +no event will the authors be held liable for any damages arising from the use +of this software. + +Permission is granted to anyone to use this software for any purpose, including +commercial applications, and to alter it and redistribute it freely, subject to +the following restrictions: + +1. The origin of this software must not be misrepresented; you must not claim + that you wrote the original software. If you use this software in a product, + an acknowledgment in the product documentation would be appreciated but is + not required. + +2. Altered source versions must be plainly marked as such, and must not be + misrepresented as being the original software. + +3. This notice may not be removed or altered from any source distribution. diff --git a/examples/wch/ch32/build.zig b/examples/wch/ch32/build.zig new file mode 100644 index 0000000..ec694a8 --- /dev/null +++ b/examples/wch/ch32/build.zig @@ -0,0 +1,29 @@ +const std = @import("std"); +const MicroZig = @import("microzig/build"); +const ch32 = @import("microzig/bsp/wch/ch32"); + +const available_examples = [_]Example{ + .{ .target = ch32.chips.ch32v003xx, .name = "ch32v003xx", .file = "src/empty.zig" }, +}; + +pub fn build(b: *std.Build) void { + const microzig = MicroZig.init(b, .{}); + const optimize = b.standardOptimizeOption(.{}); + + for (available_examples) |example| { + const firmware = microzig.add_firmware(b, .{ + .name = example.name, + .target = example.target, + .optimize = optimize, + .root_source_file = b.path(example.file), + }); + microzig.install_firmware(b, firmware, .{}); + microzig.install_firmware(b, firmware, .{ .format = .bin }); + } +} + +const Example = struct { + target: MicroZig.Target, + name: []const u8, + file: []const u8, +}; diff --git a/examples/wch/ch32/build.zig.zon b/examples/wch/ch32/build.zig.zon new file mode 100644 index 0000000..e1dac9b --- /dev/null +++ b/examples/wch/ch32/build.zig.zon @@ -0,0 +1,15 @@ +.{ + .name = "examples/wch/ch32", + .version = "0.0.0", + .dependencies = .{ + .@"microzig/build" = .{ .path = "../../../build" }, + .@"microzig/bsp/wch/ch32" = .{ .path = "../../../bsp/wch/ch32" }, + }, + + .paths = .{ + "LICENSE", + "build.zig", + "build.zig.zon", + "src", + }, +} diff --git a/examples/wch/ch32/src/empty.zig b/examples/wch/ch32/src/empty.zig new file mode 100644 index 0000000..ea26b5b --- /dev/null +++ b/examples/wch/ch32/src/empty.zig @@ -0,0 +1,6 @@ +const std = @import("std"); +const microzig = @import("microzig"); + +pub fn main() !void { + asm volatile ("nop"); +}