Brings AVR up to date (blink builds and blinks again! (#27)

* Brings AVR up to date (blink builds and blinks again!

* Fixes vector tables and build.

Co-authored-by: Felix "xq" Queißner <git@masterq32.de>

build.zig

@@ -16,33 +16,34 @@ pub fn build(b: *std.build.Builder) !void {
 
     const BuildConfig = struct { name: []const u8, backing: Backing, supports_uart_test: bool = true };
     const all_backings = [_]BuildConfig{
-        //BuildConfig{ .name = "boards.arduino_nano", .backing = Backing{ .board = boards.arduino_nano } },
+        BuildConfig{ .name = "boards.arduino_nano", .backing = Backing{ .board = boards.arduino_nano } },
         BuildConfig{ .name = "boards.mbed_lpc1768", .backing = Backing{ .board = boards.mbed_lpc1768 } },
-        //BuildConfig{ .name = "chips.atmega328p", .backing = Backing{ .chip = pkgs.chips.atmega328p } },
+        BuildConfig{ .name = "chips.atmega328p", .backing = Backing{ .chip = chips.atmega328p } },
         BuildConfig{ .name = "chips.lpc1768", .backing = Backing{ .chip = chips.lpc1768 } },
         //BuildConfig{ .name = "chips.stm32f103x8", .backing = Backing{ .chip = chips.stm32f103x8 } },
         BuildConfig{ .name = "boards.stm32f3discovery", .backing = Backing{ .board = boards.stm32f3discovery }, .supports_uart_test = false },
     };
 
-    const Test = struct { name: []const u8, source: []const u8, uses_uart: bool = false };
+    const Test = struct { name: []const u8, source: []const u8, uses_uart: bool = false, on_avr: bool = true };
     const all_tests = [_]Test{
         Test{ .name = "minimal", .source = "tests/minimal.zig" },
         Test{ .name = "blinky", .source = "tests/blinky.zig" },
-        Test{ .name = "uart-sync", .source = "tests/uart-sync.zig", .uses_uart = true },
+        Test{ .name = "uart-sync", .source = "tests/uart-sync.zig", .uses_uart = true, .on_avr = false },
 
         // Note: this example uses the systick interrupt and therefore only for arm microcontrollers
-        Test{ .name = "interrupt", .source = "tests/interrupt.zig" },
+        Test{ .name = "interrupt", .source = "tests/interrupt.zig", .on_avr = false },
     };
 
     const filter = b.option(std.Target.Cpu.Arch, "filter-target", "Filters for a certain cpu target");
 
-    inline for (all_backings) |cfg| {
+    for (all_backings) |cfg| {
-        inline for (all_tests) |tst| {
+        for (all_tests) |tst| {
             if (tst.uses_uart and !cfg.supports_uart_test) continue;
+            if ((cfg.backing.getTarget().cpu_arch.?) == .avr and tst.on_avr == false) continue;
 
             const exe = try microzig.addEmbeddedExecutable(
                 b,
-                "test-" ++ tst.name ++ "-" ++ cfg.name ++ ".elf",
+                b.fmt("test-{s}-{s}.elf", .{ tst.name, cfg.name }),
                 tst.source,
                 cfg.backing,
                 .{},
@@ -56,7 +57,7 @@ pub fn build(b: *std.build.Builder) !void {
 
                 const bin = b.addInstallRaw(
                     exe,
-                    "test-" ++ tst.name ++ "-" ++ cfg.name ++ ".bin",
+                    b.fmt("test-{s}-{s}.bin", .{ tst.name, cfg.name }),
                     .{},
                 );
                 b.getInstallStep().dependOn(&bin.step);

src/core/microzig.zig

@@ -1,5 +1,6 @@
 const std = @import("std");
 const root = @import("root");
+const builtin = @import("builtin");
 
 /// Contains build-time generated configuration options for microzig.
 /// Contains a CPU target description, chip, board and cpu information
@@ -39,16 +40,17 @@ pub const debug = @import("debug.zig");
 /// pub const panic = micro.panic;
 /// ```
 pub fn panic(message: []const u8, maybe_stack_trace: ?*std.builtin.StackTrace) noreturn {
+
     // utilize logging functions
     std.log.err("microzig PANIC: {s}", .{message});
 
-    // then use the current debug channel
+    if (builtin.cpu.arch != .avr) {
         var writer = debug.writer();
         writer.print("microzig PANIC: {s}\r\n", .{message}) catch unreachable;
+
         if (maybe_stack_trace) |stack_trace| {
             var frame_index: usize = 0;
             var frames_left: usize = std.math.min(stack_trace.index, stack_trace.instruction_addresses.len);
-
             while (frames_left != 0) : ({
                 frames_left -= 1;
                 frame_index = (frame_index + 1) % stack_trace.instruction_addresses.len;
@@ -57,6 +59,7 @@ pub fn panic(message: []const u8, maybe_stack_trace: ?*std.builtin.StackTrace) n
                 writer.print("0x{X:0>8}\r\n", .{return_address}) catch unreachable;
             }
         }
+    }
     hang();
 }
 

src/core/start.zig

@@ -1,5 +1,6 @@
 const std = @import("std");
 const app = @import("app");
+const builtin = @import("builtin");
 const microzig = @import("microzig");
 
 pub usingnamespace app;
@@ -10,12 +11,23 @@ fn isValidField(field_name: []const u8) bool {
         !std.mem.eql(u8, field_name, "reset");
 }
 
+comptime {
+    if (builtin.cpu.arch == .arm or builtin.cpu.arch == .thumb) {
+        @export(vector_table, .{
+            .name = "vector_table",
+            .section = "microzig_flash_start",
+            .linkage = .Strong,
+        });
+    }
+}
+
 const VectorTable = microzig.chip.VectorTable;
-export const vector_table: VectorTable linksection("microzig_flash_start") = blk: {
+const vector_table: VectorTable = blk: {
     var tmp: microzig.chip.VectorTable = .{
         .initial_stack_pointer = microzig.config.end_of_stack,
         .Reset = .{ .C = microzig.cpu.startup_logic._start },
     };
+
     if (@hasDecl(app, "interrupts")) {
         if (@typeInfo(app.interrupts) != .Struct)
             @compileLog("root.interrupts must be a struct");

src/main.zig

@@ -7,9 +7,17 @@ pub const cpus = @import("modules/cpus.zig");
 pub const Board = @import("modules/Board.zig");
 pub const Chip = @import("modules/Chip.zig");
 pub const Cpu = @import("modules/Cpu.zig");
+
 pub const Backing = union(enum) {
     board: Board,
     chip: Chip,
+
+    pub fn getTarget(self: @This()) std.zig.CrossTarget {
+        return switch (self) {
+            .board => |brd| brd.chip.cpu.target,
+            .chip => |chip| chip.cpu.target,
+        };
+    }
 };
 
 const Pkg = std.build.Pkg;
@@ -133,7 +141,7 @@ pub fn addEmbeddedExecutable(
     // - Generate the linker scripts from the "chip" or "board" package instead of using hardcoded ones.
     //   - This requires building another tool that runs on the host that compiles those files and emits the linker script.
     //    - src/tools/linkerscript-gen.zig is the source file for this
-    exe.bundle_compiler_rt = true;
+    exe.bundle_compiler_rt = (exe.target.cpu_arch.? != .avr); // don't bundle compiler_rt for AVR as it doesn't compile right now
     switch (backing) {
         .chip => {
             var app_pkgs = std.ArrayList(Pkg).init(builder.allocator);

src/modules/chips/atmega328p/atmega328p.zig

@@ -1,4 +1,5 @@
 const std = @import("std");
+const micro = @import("microzig");
 
 pub const cpu = @import("cpu");
 const Port = enum(u8) {
@@ -42,15 +43,15 @@ pub const gpio = struct {
         cpu.cbi(regs(pin).dir_addr, pin.pin);
     }
 
-    pub fn read(comptime pin: type) u1 {
+    pub fn read(comptime pin: type) micro.gpio.State {
         return if ((regs(pin).pin.* & (1 << pin.pin)) != 0)
-            @as(u1, 1)
+            .high
         else
-            0;
+            .low;
     }
 
-    pub fn write(comptime pin: type, state: u1) void {
+    pub fn write(comptime pin: type, state: micro.gpio.State) void {
-        if (state == 1) {
+        if (state == .high) {
             cpu.sbi(regs(pin).port_addr, pin.pin);
         } else {
             cpu.cbi(regs(pin).port_addr, pin.pin);

src/modules/chips/lpc1768/registers.zig

@@ -3,7 +3,7 @@
 // device: LPC176x5x
 // cpu: CM3
 
-pub const VectorTable = struct {
+pub const VectorTable = extern struct {
     initial_stack_pointer: u32,
     Reset: InterruptVector = unhandled,
     NMI: InterruptVector = unhandled,

src/modules/chips/nrf52/registers.zig

@@ -4,7 +4,7 @@
 // device: nrf52
 // cpu: CM4
 
-pub const VectorTable = struct {
+pub const VectorTable = extern struct {
     initial_stack_pointer: u32,
     Reset: InterruptVector = unhandled,
     NMI: InterruptVector = unhandled,

src/modules/chips/stm32f303/registers.zig

@@ -3,7 +3,7 @@
 // device: STM32F303
 // cpu: CM4
 
-pub const VectorTable = struct {
+pub const VectorTable = extern struct {
     initial_stack_pointer: u32,
     Reset: InterruptVector = unhandled,
     NMI: InterruptVector = unhandled,