Uart (#8)
* refined clock configuration, uart works with clk_peri at xosc frequency * fix pll_sys configurationwch-ch32v003
Matt Knight
2 years ago
committed by
GitHub
parent
f75a019aa5
commit
f0e51f8302
@ -0,0 +1,212 @@
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const std = @import("std");
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const microzig = @import("microzig");
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const gpio = @import("gpio.zig");
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const clocks = @import("clocks.zig");
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const assert = std.debug.assert;
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const regs = microzig.chip.registers;
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pub const WordBits = enum {
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five,
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six,
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seven,
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eight,
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};
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pub const StopBits = enum {
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one,
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two,
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};
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pub const Parity = enum {
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none,
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even,
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odd,
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};
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pub const Config = struct {
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clock_config: clocks.GlobalConfiguration,
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tx_pin: u32,
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rx_pin: u32,
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baud_rate: u32,
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word_bits: WordBits = .eight,
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stop_bits: StopBits = .one,
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parity: Parity = .none,
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};
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pub const UartRegs = extern struct {
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dr: u32,
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rsr: u32,
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reserved0: [4]u32,
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fr: @typeInfo(@TypeOf(regs.UART0.UARTFR)).Pointer.child,
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resertev1: [1]u32,
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ilpr: u32,
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ibrd: u32,
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fbrd: u32,
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lcr_h: @typeInfo(@TypeOf(regs.UART0.UARTLCR_H)).Pointer.child,
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cr: @typeInfo(@TypeOf(regs.UART0.UARTCR)).Pointer.child,
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ifls: u32,
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imsc: u32,
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ris: u32,
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mis: u32,
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icr: u32,
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dmacr: @typeInfo(@TypeOf(regs.UART0.UARTDMACR)).Pointer.child,
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periphid0: u32,
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periphid1: u32,
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periphid2: u32,
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periphid3: u32,
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cellid0: u32,
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cellid1: u32,
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cellid2: u32,
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cellid3: u32,
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padding: [4069]u32,
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};
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const uarts = @intToPtr(*volatile [2]UartRegs, regs.UART0.base_address);
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comptime {
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assert(@sizeOf(UartRegs) == (regs.UART1.base_address - regs.UART0.base_address));
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}
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pub const UART = enum {
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uart0,
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uart1,
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const WriteError = error{};
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pub const Writer = std.io.Writer(UART, WriteError, write);
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pub fn writer(uart: UART) Writer {
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return .{ .context = uart };
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}
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fn getRegs(uart: UART) *volatile UartRegs {
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return &uarts[@enumToInt(uart)];
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}
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pub fn init(comptime id: u32, comptime config: Config) UART {
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const uart: UART = switch (id) {
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0 => .uart0,
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1 => .uart1,
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else => @compileError("there is only uart0 and uart1"),
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};
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assert(config.baud_rate > 0);
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uart.reset();
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const uart_regs = uart.getRegs();
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const peri_freq = config.clock_config.peri.?.output_freq;
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uart.setBaudRate(config.baud_rate, peri_freq);
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uart.setFormat(config.word_bits, config.stop_bits, config.parity);
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uart_regs.cr.modify(.{
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.UARTEN = 1,
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.TXE = 1,
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.RXE = 1,
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});
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uart_regs.lcr_h.modify(.{ .FEN = 1 });
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// - always enable DREQ signals -- no harm if dma isn't listening
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uart_regs.dmacr.modify(.{
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.TXDMAE = 1,
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.RXDMAE = 1,
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});
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// TODO comptime assertions
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gpio.setFunction(config.tx_pin, .uart);
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gpio.setFunction(config.rx_pin, .uart);
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return uart;
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}
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pub fn isReadable(uart: UART) bool {
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return (0 == uart.getRegs().fr.read().RXFE);
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}
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pub fn isWritable(uart: UART) bool {
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return (0 == uart.getRegs().fr.read().TXFF);
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}
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// TODO: implement tx fifo
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pub fn write(uart: UART, payload: []const u8) WriteError!usize {
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const uart_regs = uart.getRegs();
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for (payload) |byte| {
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while (!uart.isWritable()) {}
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uart_regs.dr = byte;
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}
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return payload.len;
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}
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pub fn readWord(uart: UART) u8 {
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const uart_regs = uart.getRegs();
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while (!uart.isReadable()) {}
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return @truncate(u8, uart_regs.dr);
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}
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pub fn reset(uart: UART) void {
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switch (uart) {
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.uart0 => {
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regs.RESETS.RESET.modify(.{ .uart0 = 1 });
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regs.RESETS.RESET.modify(.{ .uart0 = 0 });
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while (regs.RESETS.RESET_DONE.read().uart0 != 1) {}
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},
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.uart1 => {
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regs.RESETS.RESET.modify(.{ .uart1 = 1 });
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regs.RESETS.RESET.modify(.{ .uart1 = 0 });
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while (regs.RESETS.RESET_DONE.read().uart1 != 1) {}
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},
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}
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}
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pub fn setFormat(
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uart: UART,
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word_bits: WordBits,
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stop_bits: StopBits,
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parity: Parity,
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) void {
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const uart_regs = uart.getRegs();
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uart_regs.lcr_h.modify(.{
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.WLEN = switch (word_bits) {
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.eight => @as(u2, 0b11),
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.seven => @as(u2, 0b10),
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.six => @as(u2, 0b01),
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.five => @as(u2, 0b00),
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},
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.STP2 = switch (stop_bits) {
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.one => @as(u1, 0),
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.two => @as(u1, 1),
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},
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.PEN = if (parity != .none) @as(u1, 1) else @as(u1, 0),
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.EPS = switch (parity) {
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.even => @as(u1, 1),
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.odd => @as(u1, 0),
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else => @as(u1, 0),
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},
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});
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}
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fn setBaudRate(uart: UART, baud_rate: u32, peri_freq: u32) void {
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assert(baud_rate > 0);
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const uart_regs = uart.getRegs();
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const baud_rate_div = (8 * peri_freq / baud_rate);
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var baud_ibrd = baud_rate_div >> 7;
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const baud_fbrd = if (baud_ibrd == 0) baud_fbrd: {
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baud_ibrd = 1;
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break :baud_fbrd 0;
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} else if (baud_ibrd >= 65535) baud_fbrd: {
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baud_ibrd = 65535;
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break :baud_fbrd 0;
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} else ((baud_rate_div & 0x7f) + 1) / 2;
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uart_regs.ibrd = baud_ibrd;
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uart_regs.fbrd = baud_fbrd;
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// just want a write, don't want to change these values
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uart_regs.lcr_h.modify(.{});
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}
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};
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