Microzig Generation 2 Build Interface (#28)

* Removes old build code.
* Makes basic build work again.
* First build
* Drops CI

---------

Co-authored-by: Felix "xq" Queißner <git@random-projects.net>

.github/FUNDING.yml

@@ -1 +0,0 @@
-github: MasterQ32

.github/workflows/build.yml

@@ -1,19 +0,0 @@
-name: Build
-on:
-  push:
-
-jobs:
-  build:
-    runs-on: ${{ matrix.os }}
-    strategy:
-      matrix:
-        os: [ubuntu-latest, windows-latest, macos-latest]
-        optimize: [Debug, ReleaseSmall, ReleaseFast, ReleaseSafe]
-    steps:
-      - uses: actions/checkout@v2
-      - uses: goto-bus-stop/setup-zig@v2.1.1
-        with:
-          version: 0.11.0
-
-      - name: Build
-        run: zig build install "-Doptimize=${{matrix.optimize}}"

build.zig

@@ -1,30 +1,74 @@
 const std = @import("std");
-const microzig = @import("microzig");
 
-pub const chips = @import("src/chips.zig");
+fn path(comptime suffix: []const u8) std.Build.LazyPath {
-pub const cpus = @import("src/cpus.zig");
+    return .{
+        .cwd_relative = comptime ((std.fs.path.dirname(@src().file) orelse ".") ++ suffix),
+    };
+}
 
-pub fn build(b: *std.Build) void {
+const esp_riscv = .{
-    const optimize = b.standardOptimizeOption(.{});
+    .name = "Espressif RISC-V",
+    .source_file = path("/src/cpus/espressif-riscv.zig"),
+    .target = std.zig.CrossTarget{
+        .cpu_arch = .riscv32,
+        .cpu_model = .{ .explicit = &std.Target.riscv.cpu.generic_rv32 },
+        .cpu_features_add = std.Target.riscv.featureSet(&.{
+            std.Target.riscv.Feature.c,
+            std.Target.riscv.Feature.m,
+        }),
+        .os_tag = .freestanding,
+        .abi = .eabi,
+    },
+};
+
+const hal = .{
+    .source_file = path("/src/hals/ESP32_C3.zig"),
+};
+
+pub const chips = struct {
+    pub const esp32_c3 = .{
+        .preferred_format = .bin, // TODO: Exchange FLAT format with .esp format
+        .chip = .{
+            .name = "ESP32-C3",
+            .url = "https://www.espressif.com/en/products/socs/esp32-c3",
+
+            .cpu = .{ .custom = &esp_riscv },
 
-    var exe = microzig.addEmbeddedExecutable(b, .{
+            .register_definition = .{
-        .name = "esp-bringup",
+                .svd = path("/src/chips/ESP32-C3.svd"),
-        .source_file = .{
-            .path = "src/example/blinky.zig",
             },
-        .backing = .{ .chip = chips.esp32_c3 },
-        .optimize = optimize,
-    });
 
-    const fw_objcopy = b.addObjCopy(exe.inner.getEmittedBin(), .{
+            .memory_regions = &.{
-        .format = .bin,
+                .{ .kind = .flash, .offset = 0x4200_0000, .length = 0x0080_0000 }, // external memory, ibus
-    });
+                .{ .kind = .ram, .offset = 0x3FC8_0000, .length = 0x0006_0000 }, // sram 1, data bus
+            },
+        },
+        .hal = hal,
+    };
+};
+
+pub fn build(b: *std.Build) void {
+    _ = b;
+    // const optimize = b.standardOptimizeOption(.{});
+
+    // var exe = microzig.addEmbeddedExecutable(b, .{
+    //     .name = "esp-bringup",
+    //     .source_file = .{
+    //         .path = "src/example/blinky.zig",
+    //     },
+    //     .backing = .{ .chip = chips.esp32_c3 },
+    //     .optimize = optimize,
+    // });
+
+    // const fw_objcopy = b.addObjCopy(exe.inner.getEmittedBin(), .{
+    //     .format = .bin,
+    // });
 
-    const fw_bin = fw_objcopy.getOutput();
+    // const fw_bin = fw_objcopy.getOutput();
 
-    const install_fw_bin = b.addInstallFile(fw_bin, "firmware/blinky.bin");
+    // const install_fw_bin = b.addInstallFile(fw_bin, "firmware/blinky.bin");
 
-    b.getInstallStep().dependOn(&install_fw_bin.step);
+    // b.getInstallStep().dependOn(&install_fw_bin.step);
 
-    b.installArtifact(exe.inner);
+    // b.installArtifact(exe.inner);
 }

build.zig.zon

@@ -1,10 +1,5 @@
 .{
     .name = "microzig-espressif-esp",
     .version = "0.1.0",
-    .dependencies = .{
+    .dependencies = .{},
-        .microzig = .{
-            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/0b3be0a4cc7e6d45714cb09961efc771e364723c.tar.gz",
-            .hash = "1220ada6d01db7b3d0aa8642df89b1af9ee71b681438249e9a7efb2275fc4cf32152",
-        },
-    },
 }

src/chips.zig

@@ -1,23 +0,0 @@
-const std = @import("std");
-const microzig = @import("microzig");
-const cpus = @import("cpus.zig");
-
-fn root_dir() []const u8 {
-    return std.fs.path.dirname(@src().file) orelse unreachable;
-}
-
-pub const esp32_c3 = microzig.Chip{
-    .name = "ESP32-C3",
-    .source = .{
-        .path = root_dir() ++ "/chips/ESP32_C3.zig",
-    },
-    .hal = .{
-        .path = root_dir() ++ "/hals/ESP32_C3.zig",
-    },
-
-    .cpu = cpus.esp32_c3,
-    .memory_regions = &.{
-        .{ .kind = .flash, .offset = 0x4200_0000, .length = 0x0080_0000 }, // external memory, ibus
-        .{ .kind = .ram, .offset = 0x3FC8_0000, .length = 0x0006_0000 }, // sram 1, data bus
-    },
-};

src/cpus.zig

@@ -1,23 +0,0 @@
-const std = @import("std");
-const microzig = @import("microzig");
-
-fn root_dir() []const u8 {
-    return std.fs.path.dirname(@src().file) orelse unreachable;
-}
-
-pub const esp32_c3 = microzig.Cpu{
-    .name = "Espressif RISC-V",
-    .source = .{
-        .path = root_dir() ++ "/cpus/espressif-riscv.zig",
-    },
-    .target = std.zig.CrossTarget{
-        .cpu_arch = .riscv32,
-        .cpu_model = .{ .explicit = &std.Target.riscv.cpu.generic_rv32 },
-        .cpu_features_add = std.Target.riscv.featureSet(&.{
-            std.Target.riscv.Feature.c,
-            std.Target.riscv.Feature.m,
-        }),
-        .os_tag = .freestanding,
-        .abi = .eabi,
-    },
-};