Merge branch 'merge_lpc'
Felix "xq" Queißner
9 months ago
commit
c703e15706
@ -0,0 +1,19 @@
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Copyright (c) 2022 Zig Embedded Group Contributors
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This software is provided 'as-is', without any express or implied warranty. In
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no event will the authors be held liable for any damages arising from the use
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of this software.
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Permission is granted to anyone to use this software for any purpose, including
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commercial applications, and to alter it and redistribute it freely, subject to
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the following restrictions:
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1. The origin of this software must not be misrepresented; you must not claim
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that you wrote the original software. If you use this software in a product, an
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acknowledgment in the product documentation would be appreciated but is not
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required.
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2. Altered source versions must be plainly marked as such, and must not be
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misrepresented as being the original software.
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3. This notice may not be removed or altered from any source distribution.
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@ -0,0 +1,7 @@
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= NXP LPC Hardware Support Package
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Please see https://github.com/ZigEmbeddedGroup/lpcboot[lpcboot] as well
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== What version of Zig to use
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Right now we are following https://ziglang.org/download/[master], but once 0.11.0 is released, we will be switching to the latest stable version of Zig.
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@ -0,0 +1,95 @@
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const std = @import("std");
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fn path(comptime suffix: []const u8) std.Build.LazyPath {
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return .{
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.cwd_relative = comptime ((std.fs.path.dirname(@src().file) orelse ".") ++ suffix),
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};
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}
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const hal = .{
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.source_file = path("/src/hals/LPC176x5x.zig"),
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};
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pub const chips = struct {
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pub const lpc176x5x = .{
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.preferred_format = .elf,
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.chip = .{
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// TODO: Separate over those chips, this is not generic!
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.name = "LPC176x5x",
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.cpu = .cortex_m3,
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.memory_regions = &.{
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.{ .offset = 0x00000000, .length = 512 * 1024, .kind = .flash },
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.{ .offset = 0x10000000, .length = 32 * 1024, .kind = .ram },
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.{ .offset = 0x2007C000, .length = 32 * 1024, .kind = .ram },
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},
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.register_definition = .{
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.json = path("/src/chips/LPC176x5x.json"),
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},
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},
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.hal = hal,
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.binary_post_process = postprocess,
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};
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};
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pub const boards = struct {
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pub const mbed = struct {
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pub const lpc1768 = .{
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.preferred_format = .hex,
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.chip = chips.lpc176x5x.chip,
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.hal = hal,
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.board = .{
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.name = "mbed LPC1768",
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.url = "https://os.mbed.com/platforms/mbed-LPC1768/",
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.source_file = path("/src/boards/mbed_LPC1768.zig"),
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},
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.binary_post_process = postprocess,
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};
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};
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};
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/// Post-processes an ELF file to add a checksum over the first 8 words so the
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/// cpu will properly boot.
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fn postprocess(b: *std.Build, input: std.Build.LazyPath) std.Build.LazyPath {
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const patchelf = b.addExecutable(.{
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.name = "lpc176x5x-patchelf",
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.root_source_file = path("/src/tools/patchelf.zig"),
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});
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const patch = b.addRunArtifact(patchelf);
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patch.addFileArg(input);
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return patch.addOutputFileArg("firmware.elf");
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}
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pub fn build(b: *std.Build) void {
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_ = b;
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// const optimize = b.standardOptimizeOption(.{});
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// inline for (@typeInfo(boards).Struct.decls) |decl| {
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// if (!decl.is_pub)
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// continue;
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// const exe = microzig.addEmbeddedExecutable(b, .{
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// .name = @field(boards, decl.name).name ++ ".minimal",
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// .source_file = .{
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// .path = "test/programs/minimal.zig",
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// },
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// .backing = .{ .board = @field(boards, decl.name) },
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// .optimize = optimize,
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// });
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// exe.installArtifact(b);
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// }
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// inline for (@typeInfo(chips).Struct.decls) |decl| {
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// if (!decl.is_pub)
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// continue;
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// const exe = microzig.addEmbeddedExecutable(b, .{
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// .name = @field(chips, decl.name).name ++ ".minimal",
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// .source_file = .{
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// .path = "test/programs/minimal.zig",
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// },
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// .backing = .{ .chip = @field(chips, decl.name) },
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// .optimize = optimize,
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// });
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// exe.installArtifact(b);
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// }
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}
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@ -0,0 +1,84 @@
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pub const chip = @import("chip");
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pub const micro = @import("microzig");
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pub const clock_frequencies = .{
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.cpu = 100_000_000, // 100 Mhz
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};
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pub fn debug_write(string: []const u8) void {
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const clk_pin = micro.Pin("DIP5");
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const dat_pin = micro.Pin("DIP6");
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const clk = micro.core.experimental.Gpio(clk_pin, .{ .mode = .output, .initial_state = .low });
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const dat = micro.core.experimental.Gpio(dat_pin, .{ .mode = .output, .initial_state = .low });
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clk.init();
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dat.init();
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micro.debug.busy_sleep(1_000);
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for (string) |c| {
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comptime var i: usize = 128;
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inline while (i > 0) : (i = i >> 1) {
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if ((c & i) != 0) {
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dat.write(.high);
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} else {
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dat.write(.low);
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}
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clk.write(.high);
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micro.debug.busy_sleep(1_000);
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clk.write(.low);
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micro.debug.busy_sleep(1_000);
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}
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}
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dat.write(.low);
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clk.write(.low);
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}
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pub const pin_map = .{
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// Onboard-LEDs
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.@"LED-1" = "P1.18",
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.@"LED-2" = "P1.20",
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.@"LED-3" = "P1.21",
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.@"LED-4" = "P1.23",
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.LED_LINK = "P1.25",
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.LED_SPEED = "P1.26",
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// Ethernet
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.@"TD+" = "P1.0",
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.@"TD-" = "P1.1",
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.@"RD+" = "P1.9",
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.@"RD-" = "P1.10",
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// USB
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.@"D+" = "P0.29",
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.@"D-" = "P0.30",
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// GPIO pins
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.DIP5 = "P0.9",
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.DIP6 = "P0.8",
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.DIP7 = "P0.7",
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.DIP8 = "P0.6",
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.DIP9 = "P0.0",
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.DIP10 = "P0.1",
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.DIP11 = "P0.18",
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.DIP12 = "P0.17",
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.DIP13 = "P0.15",
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.DIP14 = "P0.16",
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.DIP15 = "P0.23",
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.DIP16 = "P0.24",
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.DIP17 = "P0.25",
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.DIP18 = "P0.26",
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.DIP19 = "P1.30",
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.DIP20 = "P1.31",
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.DIP21 = "P2.5",
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.DIP22 = "P2.4",
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.DIP23 = "P2.3",
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.DIP24 = "P2.2",
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.DIP25 = "P2.1",
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.DIP26 = "P2.0",
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.DIP27 = "P0.11",
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.DIP28 = "P0.10",
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.DIP29 = "P0.5",
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.DIP30 = "P0.4",
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};
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File diff suppressed because it is too large
Load Diff
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const std = @import("std");
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const micro = @import("microzig");
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const peripherals = micro.chip.peripherals;
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const GPIO = peripherals.GPIO;
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const PINCONNECT = peripherals.PINCONNECT;
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const UART0 = peripherals.UART0;
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const UART1 = peripherals.UART1;
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const UART2 = peripherals.UART2;
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const UART3 = peripherals.UART3;
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const SYSCON = peripherals.SYSCON;
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pub const clock = struct {
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pub const Domain = enum {
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cpu,
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};
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};
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pub const clock_frequencies = .{
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.cpu = 100_000_000, // 100 Mhz
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};
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pub const PinTarget = enum(u2) {
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func00 = 0b00,
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func01 = 0b01,
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func10 = 0b10,
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func11 = 0b11,
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};
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pub fn parse_pin(comptime spec: []const u8) type {
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const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}.{Pin}\" scheme.";
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if (spec[0] != 'P')
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@compileError(invalid_format_msg);
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const index = std.mem.indexOfScalar(u8, spec, '.') orelse @compileError(invalid_format_msg);
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const _port: comptime_int = std.fmt.parseInt(u3, spec[1..index], 10) catch @compileError(invalid_format_msg);
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const _pin: comptime_int = std.fmt.parseInt(u5, spec[index + 1 ..], 10) catch @compileError(invalid_format_msg);
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const sel_reg_name = std.fmt.comptimePrint("PINSEL{d}", .{(2 * _port + _pin / 16)});
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const _regs = struct {
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const name_suffix = std.fmt.comptimePrint("{d}", .{_port});
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const pinsel_reg = @field(PINCONNECT, sel_reg_name);
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const pinsel_field = std.fmt.comptimePrint("P{d}_{d}", .{ _port, _pin });
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const dir = @field(GPIO, "DIR" ++ name_suffix);
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const pin = @field(GPIO, "PIN" ++ name_suffix);
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const set = @field(GPIO, "SET" ++ name_suffix);
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const clr = @field(GPIO, "CLR" ++ name_suffix);
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const mask = @field(GPIO, "MASK" ++ name_suffix);
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};
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return struct {
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pub const port: u3 = _port;
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pub const pin: u5 = _pin;
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pub const regs = _regs;
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const gpio_mask: u32 = (1 << pin);
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pub const Targets = PinTarget;
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};
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}
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pub fn route_pin(comptime pin: type, function: PinTarget) void {
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var val = pin.regs.pinsel_reg.read();
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@field(val, pin.regs.pinsel_field) = @intFromEnum(function);
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pin.regs.pinsel_reg.write(val);
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}
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pub const gpio = struct {
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pub fn set_output(comptime pin: type) void {
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pin.regs.dir.raw |= pin.gpio_mask;
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}
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pub fn set_input(comptime pin: type) void {
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pin.regs.dir.raw &= ~pin.gpio_mask;
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}
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pub fn read(comptime pin: type) micro.gpio.State {
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return if ((pin.regs.pin.raw & pin.gpio_mask) != 0)
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micro.gpio.State.high
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else
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micro.gpio.State.low;
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}
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pub fn write(comptime pin: type, state: micro.gpio.State) void {
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if (state == .high) {
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pin.regs.set.raw = pin.gpio_mask;
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} else {
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pin.regs.clr.raw = pin.gpio_mask;
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}
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}
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};
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pub const uart = struct {
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pub const DataBits = enum(u2) {
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five = 0,
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six = 1,
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seven = 2,
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eight = 3,
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};
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pub const StopBits = enum(u1) {
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one = 0,
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two = 1,
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};
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pub const Parity = enum(u2) {
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odd = 0,
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even = 1,
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mark = 2,
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space = 3,
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};
|
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pub const CClkDiv = enum(u2) {
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four = 0,
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one = 1,
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two = 2,
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eight = 3,
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};
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};
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|
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pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type {
|
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if (pins.tx != null or pins.rx != null)
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@compileError("TODO: custom pins are not currently supported");
|
||||
|
||||
return struct {
|
||||
const UARTn = switch (index) {
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||||
0 => UART0,
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1 => UART1,
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2 => UART2,
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||||
3 => UART3,
|
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else => @compileError("LPC1768 has 4 UARTs available."),
|
||||
};
|
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const Self = @This();
|
||||
|
||||
pub fn init(config: micro.uart.Config) !Self {
|
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micro.debug.write("0");
|
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switch (index) {
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0 => {
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SYSCON.PCONP.modify(.{ .PCUART0 = 1 });
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||||
SYSCON.PCLKSEL0.modify(.{ .PCLK_UART0 = @intFromEnum(uart.CClkDiv.four) });
|
||||
},
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||||
1 => {
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||||
SYSCON.PCONP.modify(.{ .PCUART1 = 1 });
|
||||
SYSCON.PCLKSEL0.modify(.{ .PCLK_UART1 = @intFromEnum(uart.CClkDiv.four) });
|
||||
},
|
||||
2 => {
|
||||
SYSCON.PCONP.modify(.{ .PCUART2 = 1 });
|
||||
SYSCON.PCLKSEL1.modify(.{ .PCLK_UART2 = @intFromEnum(uart.CClkDiv.four) });
|
||||
},
|
||||
3 => {
|
||||
SYSCON.PCONP.modify(.{ .PCUART3 = 1 });
|
||||
SYSCON.PCLKSEL1.modify(.{ .PCLK_UART3 = @intFromEnum(uart.CClkDiv.four) });
|
||||
},
|
||||
else => unreachable,
|
||||
}
|
||||
micro.debug.write("1");
|
||||
|
||||
UARTn.LCR.modify(.{
|
||||
// 8N1
|
||||
.WLS = @intFromEnum(config.data_bits),
|
||||
.SBS = @intFromEnum(config.stop_bits),
|
||||
.PE = if (config.parity != null) @as(u1, 1) else @as(u1, 0),
|
||||
.PS = if (config.parity) |p| @intFromEnum(p) else @intFromEnum(uart.Parity.odd),
|
||||
.BC = 0,
|
||||
.DLAB = 1,
|
||||
});
|
||||
micro.debug.write("2");
|
||||
|
||||
// TODO: UARTN_FIFOS_ARE_DISA is not available in all uarts
|
||||
//UARTn.FCR.modify(.{ .FIFOEN = .UARTN_FIFOS_ARE_DISA });
|
||||
|
||||
micro.debug.writer().print("clock: {} baud: {} ", .{
|
||||
micro.clock.get().cpu,
|
||||
config.baud_rate,
|
||||
}) catch {};
|
||||
|
||||
const pclk = micro.clock.get().cpu / 4;
|
||||
const divider = (pclk / (16 * config.baud_rate));
|
||||
|
||||
const regval = std.math.cast(u16, divider) orelse return error.UnsupportedBaudRate;
|
||||
|
||||
UARTn.DLL.modify(.{ .DLLSB = @as(u8, @truncate(regval >> 0x00)) });
|
||||
UARTn.DLM.modify(.{ .DLMSB = @as(u8, @truncate(regval >> 0x08)) });
|
||||
|
||||
UARTn.LCR.modify(.{ .DLAB = 0 });
|
||||
|
||||
return Self{};
|
||||
}
|
||||
|
||||
pub fn can_write(self: Self) bool {
|
||||
_ = self;
|
||||
return (UARTn.LSR.read().THRE == 1);
|
||||
}
|
||||
pub fn tx(self: Self, ch: u8) void {
|
||||
while (!self.can_write()) {} // Wait for Previous transmission
|
||||
UARTn.THR.raw = ch; // Load the data to be transmitted
|
||||
}
|
||||
|
||||
pub fn can_read(self: Self) bool {
|
||||
_ = self;
|
||||
return (UARTn.LSR.read().RDR == 1);
|
||||
}
|
||||
pub fn rx(self: Self) u8 {
|
||||
while (!self.can_read()) {} // Wait till the data is received
|
||||
return UARTn.RBR.read().RBR; // Read received data
|
||||
}
|
||||
};
|
||||
}
|
||||
@ -0,0 +1,66 @@
|
||||
const std = @import("std");
|
||||
|
||||
pub fn main() !u8 {
|
||||
const argv = try std.process.argsAlloc(std.heap.page_allocator);
|
||||
defer std.process.argsFree(std.heap.page_allocator, argv);
|
||||
|
||||
if (argv.len != 3) {
|
||||
std.log.err("usage: lpc-patchelf <input> <output>", .{});
|
||||
return 1;
|
||||
}
|
||||
|
||||
const input_file_name = argv[1];
|
||||
const output_file_name = argv[2];
|
||||
|
||||
try std.fs.Dir.copyFile(
|
||||
std.fs.cwd(),
|
||||
input_file_name,
|
||||
std.fs.cwd(),
|
||||
output_file_name,
|
||||
.{},
|
||||
);
|
||||
|
||||
var file = try std.fs.cwd().openFile(output_file_name, .{ .mode = .read_write });
|
||||
defer file.close();
|
||||
|
||||
const header = try std.elf.Header.read(file);
|
||||
|
||||
var iter = header.program_header_iterator(file);
|
||||
while (try iter.next()) |phdr| {
|
||||
if (phdr.p_type != std.elf.PT_LOAD) {
|
||||
continue;
|
||||
}
|
||||
|
||||
if (phdr.p_paddr != 0) {
|
||||
// std.log.warn("LOAD program header is not located at address 0x00000000!", .{});
|
||||
break;
|
||||
}
|
||||
|
||||
const boot_sector_items = 8;
|
||||
const boot_sector_size = @sizeOf([boot_sector_items]u32);
|
||||
|
||||
if (phdr.p_filesz < boot_sector_size) {
|
||||
std.log.warn("boot header is too small! Expected {} bytes, but sector only has {} bytes!", .{
|
||||
boot_sector_size,
|
||||
phdr.p_filesz,
|
||||
});
|
||||
continue;
|
||||
}
|
||||
|
||||
try file.seekTo(phdr.p_offset);
|
||||
var reader = file.reader();
|
||||
var writer = file.writer();
|
||||
|
||||
var checksum: u32 = 0;
|
||||
|
||||
var i: usize = 0;
|
||||
while (i < boot_sector_items - 1) : (i += 1) {
|
||||
const item = try reader.readIntLittle(u32);
|
||||
checksum -%= item;
|
||||
}
|
||||
|
||||
try writer.writeIntLittle(u32, checksum);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -0,0 +1,5 @@
|
||||
const micro = @import("microzig");
|
||||
|
||||
pub fn main() void {
|
||||
// This function will contain the application logic.
|
||||
}
|
||||
Loading…
Reference in New Issue