init
Matt Knight
2 years ago
commit
a501e63286
@ -0,0 +1,2 @@
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zig-cache
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zig-out
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@ -0,0 +1,3 @@
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[submodule "microzig"]
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path = microzig
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url = git@github.com:ZigEmbeddedGroup/microzig.git
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@ -0,0 +1,51 @@
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const std = @import("std");
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const Builder = std.build.Builder;
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const Pkg = std.build.Pkg;
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pub const BuildOptions = struct {
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packages: ?[]const Pkg = null,
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};
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pub fn addPiPicoExecutable(
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comptime microzig: type,
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builder: *Builder,
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name: []const u8,
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source: []const u8,
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options: BuildOptions,
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) *std.build.LibExeObjStep {
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const rp2040 = microzig.Chip{
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.name = "RP2040",
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.path = root() ++ "src/rp2040.zig",
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.cpu = microzig.cpus.cortex_m0plus,
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.memory_regions = &.{
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.{ .kind = .flash, .offset = 0x10000100, .length = (2048 * 1024) - 256 },
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.{ .kind = .flash, .offset = 0x10000000, .length = 256 },
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.{ .kind = .ram, .offset = 0x20000000, .length = 256 * 1024 },
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},
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};
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const raspberry_pi_pico = microzig.Board{
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.name = "Raspberry Pi Pico",
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.path = root() ++ "src/raspberry_pi_pico.zig",
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.chip = rp2040,
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};
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const ret = microzig.addEmbeddedExecutable(
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builder,
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name,
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source,
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.{ .board = raspberry_pi_pico },
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.{
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.packages = options.packages,
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.hal_package_path = .{ .path = root() ++ "src/hal.zig" },
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},
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) catch @panic("failed to create embedded executable");
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ret.setLinkerScriptPath(.{ .path = root() ++ "rp2040.ld" });
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return ret;
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}
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fn root() []const u8 {
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return (std.fs.path.dirname(@src().file) orelse unreachable) ++ "/";
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}
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@ -0,0 +1 @@
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Subproject commit ac19b7de8eb1551e603b3ce23a4aab69c71d1216
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@ -0,0 +1,58 @@
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/*
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* This file was auto-generated by microzig
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*
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* Target CPU: ARM Cortex-M0+
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* Target Chip: RP2040
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*/
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ENTRY(microzig_main);
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MEMORY
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{
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flash0 (rx!w) : ORIGIN = 0x10000000, LENGTH = 0x00200000
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ram0 (rw!x) : ORIGIN = 0x20000000, LENGTH = 0x00040000
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}
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SECTIONS
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{
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.boot2 : {
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__boot2_start__ = .;
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KEEP (*(.boot2))
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__boot2_end__ = .;
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} > flash0
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ASSERT(__boot2_end__ - __boot2_start__ == 256,
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"ERROR: Pico second stage bootloader must be 256 bytes in size")
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.text :
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{
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KEEP(*(microzig_flash_start))
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*(.text*)
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*(.rodata*)
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} > flash0
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.ARM.exidx : {
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} >flash0
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.flash1 :
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{
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*(.flash1)
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} > flash1
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.data :
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{
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microzig_data_start = .;
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*(.data*)
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microzig_data_end = .;
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} > ram0 AT> flash0
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.bss (NOLOAD) :
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{
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microzig_bss_start = .;
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*(.bss*)
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microzig_bss_end = .;
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} > ram0
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microzig_data_load_start = LOADADDR(.data);
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}
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@ -0,0 +1,20 @@
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const microzig = @import("microzig");
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const regs = microzig.chip.regsisters;
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pub const gpio = @import("hal/gpio.zig");
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pub const clocks = @import("hal/clocks.zig");
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pub const default_clock_config = clocks.GlobalConfiguration.init(.{
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//.ref = .{ .source = .src_xosc },
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.sys = .{
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.source = .pll_sys,
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.freq = 125_000_000,
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},
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.usb = .{ .source = .pll_usb },
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//.adc = .{ .source = .pll_usb },
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//.rtc = .{ .source = .pll_usb },
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.peri = .{ .source = .clk_sys },
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});
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pub fn getCpuId() u32 {
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return regs.SIO.CPUID.*;
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}
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@ -0,0 +1,438 @@
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const std = @import("std");
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const microzig = @import("microzig");
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const pll = @import("pll.zig");
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const assert = std.debug.assert;
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const regs = microzig.chip.registers;
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const xosc_freq = microzig.board.xosc_freq;
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// TODO: move to board file
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/// this is only nominal, very imprecise and prone to drift over time
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const rosc_freq = 6_500_000;
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comptime {
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assert(xosc_freq <= 15_000_000 and xosc_freq >= 1_000_000); // xosc limits
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}
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pub const xosc = struct {
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const startup_delay_ms = 1;
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const startup_delay_value = xosc_freq * startup_delay_ms / 1000 / 256;
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pub fn init() void {
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regs.XOSC.STARTUP.modify(.{ .DELAY = startup_delay_value });
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regs.XOSC.CTRL.modify(.{ .ENABLE = 4011 });
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// wait for xosc startup to complete:
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while (regs.XOSC.STATUS.read().STABLE == 0) {}
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}
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pub fn waitCycles(value: u8) void {
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assert(is_enabled: {
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const status = regs.XOSC.STATUS.read();
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break :is_enabled status.STABLE != 0 and status.ENABLED != 0;
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});
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regs.XOSC.COUNT.modify(value);
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while (regs.XOSC.COUNT.read() != 0) {}
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}
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};
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fn formatUppercase(
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bytes: []const u8,
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comptime fmt: []const u8,
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options: std.fmt.FormatOptions,
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writer: anytype,
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) !void {
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_ = fmt;
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_ = options;
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for (bytes) |c|
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try writer.writeByte(std.ascii.toUpper(c));
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}
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fn uppercase(bytes: []const u8) std.fmt.Formatter(formatUppercase) {
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return .{ .data = bytes };
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}
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pub const Generator = enum {
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gpout0,
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gpout1,
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gpout2,
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gpout3,
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ref,
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sys,
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peri,
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usb,
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adc,
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rtc,
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// source directly from register definitions
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const Source = enum {
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rosc_clksrc_ph,
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clksrc_clk_ref_aux,
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xosc_clksrc,
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clk_ref,
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clksrc_clk_sys_aux,
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};
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// aux sources directly from register definitions
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const AuxilarySource = enum {
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clksrc_pll_sys,
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clksrc_gpin0,
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clksrc_gpin1,
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clksrc_pll_usb,
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rosc_clksrc,
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xosc_clksrc,
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clk_sys,
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clk_usb,
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clk_adc,
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clk_rtc,
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clk_ref,
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rosc_clksrc_ph,
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};
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const source_map = struct {
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const ref = [_]Generator.Source{ .rosc_clksrc_ph, .clksrc_clk_ref, .xosc_clksrc };
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const sys = [_]Generator.Source{ .clk_ref, .clksrc_clk_sys_aux };
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};
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const aux_map = struct {};
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pub fn hasGlitchlessMux(generator: Generator) bool {
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return switch (generator) {
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.sys, .ref => true,
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else => false,
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};
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}
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pub fn enable(generator: Generator) void {
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inline for (std.meta.fields(Generator)) |field| {
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if (generator == @field(Generator, field.name)) {
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const reg_name = comptime std.fmt.comptimePrint("CLK_{s}_CTRL", .{
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uppercase(field.name),
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});
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if (@hasField(@TypeOf(@field(regs.CLOCKS, reg_name).*).underlying_type, "ENABLE"))
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@field(regs.CLOCKS, reg_name).modify(.{ .ENABLE = 1 });
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}
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}
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}
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pub fn setDiv(generator: Generator, div: u32) void {
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inline for (std.meta.fields(Generator)) |field| {
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if (generator == @field(Generator, field.name)) {
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const reg_name = comptime std.fmt.comptimePrint("CLK_{s}_DIV", .{
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uppercase(field.name),
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});
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if (@hasDecl(regs.CLOCKS, reg_name))
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@field(regs.CLOCKS, reg_name).raw = div
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else
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assert(false); // doesn't have a divider
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}
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}
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}
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pub fn getDiv(generator: Generator) u32 {
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return inline for (std.meta.fields(Generator)) |field| {
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if (generator == @field(Generator, field.name)) {
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const reg_name = comptime std.fmt.comptimePrint("CLK_{s}_DIV", .{
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uppercase(field.name),
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});
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break if (@hasDecl(regs.CLOCKS, reg_name))
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@field(regs.CLOCKS, reg_name).raw
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else
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1;
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}
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} else unreachable;
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}
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// The bitfields for the *_SELECTED registers are actually a mask of which
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// source is selected. While switching sources it may read as 0, and that's
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// what this function is indended for: checking if the new source has
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// switched over yet.
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//
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// Some mention that this is only for the glitchless mux, so if it is non-glitchless then return true
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pub fn selected(generator: Generator) bool {
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inline for (std.meta.fields(Generator)) |field| {
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if (generator == @field(Generator, field.name)) {
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return if (@field(Generator, field.name).hasGlitchlessMux()) ret: {
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const reg_name = comptime std.fmt.comptimePrint("CLK_{s}_SELECTED", .{
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uppercase(field.name),
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});
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break :ret @field(regs.CLOCKS, reg_name).* != 0;
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} else true;
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}
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} else unreachable;
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}
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};
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pub const Source = enum {
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src_rosc,
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src_xosc,
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src_aux,
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pll_sys,
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pll_usb,
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clk_sys,
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};
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pub const GlobalConfiguration = struct {
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xosc_configured: bool,
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sys: ?Configuration,
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ref: ?Configuration,
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usb: ?Configuration,
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adc: ?Configuration,
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rtc: ?Configuration,
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peri: ?Configuration,
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pll_sys: ?pll.Configuration,
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pll_usb: ?pll.Configuration,
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pub const Option = struct {
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source: Source,
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freq: ?u32 = null,
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};
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pub const Options = struct {
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sys: ?Option = null,
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ref: ?Option = null,
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usb: ?Option = null,
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adc: ?Option = null,
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rtc: ?Option = null,
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peri: ?Option = null,
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// TODO: allow user to configure PLLs to optimize for low-jitter, low-power, or manually specify
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};
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/// this function reasons about how to configure the clock system. It will
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/// assert if the configuration is invalid
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pub fn init(comptime opts: Options) GlobalConfiguration {
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var xosc_configured = false;
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var pll_sys: ?pll.Configuration = null;
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var pll_usb: ?pll.Configuration = null;
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return GlobalConfiguration{
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// the system clock can either use rosc, xosc, or the sys PLL
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.sys = if (opts.sys) |sys_opts| sys_config: {
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var output_freq: ?u32 = null;
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break :sys_config .{
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.generator = .sys,
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.input = switch (sys_opts.source) {
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.src_rosc => input: {
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output_freq = sys_opts.freq orelse rosc_freq;
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assert(output_freq.? <= rosc_freq);
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break :input .{
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.source = .rosc,
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.freq = rosc_freq,
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};
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},
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.src_xosc => input: {
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xosc_configured = true;
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output_freq = sys_opts.freq orelse xosc_freq;
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assert(output_freq.? <= xosc_freq);
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break :input .{
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.source = .xosc,
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.freq = xosc_freq,
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};
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},
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.pll_sys => input: {
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xosc_configured = true;
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output_freq = sys_opts.freq orelse 125_000_000;
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assert(output_freq.? <= 125_000_000);
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// TODO: proper values for 125MHz
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pll_sys = .{
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.refdiv = 2,
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.vco_freq = 1_440_000_000,
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.postdiv1 = 6,
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.postdiv2 = 5,
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};
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break :input .{
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.source = .pll_sys,
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// TODO: not really sure what frequency to
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// drive pll at yet, but this is an okay start
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.freq = 125_000_000,
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};
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},
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else => unreachable, // not an available input
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},
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.output_freq = output_freq.?,
|
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};
|
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} else null,
|
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|
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// to keep things simple for now, we'll make it so that the usb
|
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// generator can only be hooked up to the usb PLL, and only have
|
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// one configuration for the usb PLL
|
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.usb = if (opts.usb) |usb_opts| usb_config: {
|
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assert(pll_usb == null);
|
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assert(usb_opts.source == .pll_usb);
|
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|
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xosc_configured = true;
|
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pll_usb = .{
|
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.refdiv = 1,
|
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.vco_freq = 1_440_000_000,
|
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.postdiv1 = 6,
|
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.postdiv2 = 5,
|
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};
|
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|
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break :usb_config .{
|
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.generator = .usb,
|
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.input = .{
|
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.source = .pll_usb,
|
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.freq = 48_000_000,
|
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},
|
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.output_freq = 48_000_000,
|
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};
|
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} else null,
|
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|
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// I THINK that if either pll is configured here, then that means
|
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// that the ref clock generator MUST use xosc to feed the PLLs?
|
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.ref = if (opts.ref) |_|
|
||||
unreachable // don't explicitly configure for now
|
||||
else if (pll_sys != null or pll_usb != null) ref_config: {
|
||||
xosc_configured = true;
|
||||
break :ref_config .{
|
||||
.generator = .ref,
|
||||
.input = .{
|
||||
.source = .src_xosc,
|
||||
.freq = xosc_freq,
|
||||
},
|
||||
.output_freq = xosc_freq,
|
||||
};
|
||||
} else null,
|
||||
|
||||
// for the rest of the generators we'll make it so that they can
|
||||
// either use the ROSC, XOSC, or sys PLL, with whatever dividing
|
||||
// they need
|
||||
|
||||
.adc = if (opts.adc) |_|
|
||||
unreachable // TODO
|
||||
else
|
||||
null,
|
||||
|
||||
.rtc = if (opts.rtc) |_|
|
||||
unreachable // TODO
|
||||
else
|
||||
null,
|
||||
|
||||
.peri = if (opts.peri) |peri_opts| peri_config: {
|
||||
if (peri_opts.source == .src_xosc)
|
||||
xosc_configured = true;
|
||||
|
||||
// TODO
|
||||
break :peri_config .{
|
||||
.generator = .peri,
|
||||
.input = .{
|
||||
.source = peri_opts.source,
|
||||
.freq = xosc_freq,
|
||||
},
|
||||
.output_freq = xosc_freq,
|
||||
};
|
||||
} else null,
|
||||
|
||||
.xosc_configured = xosc_configured,
|
||||
.pll_sys = pll_sys,
|
||||
.pll_usb = pll_usb,
|
||||
};
|
||||
}
|
||||
|
||||
/// this is explicitly comptime to encourage the user to have separate
|
||||
/// clock configuration declarations instead of mutating them at runtime
|
||||
pub fn apply(comptime config: GlobalConfiguration) !void {
|
||||
|
||||
// disable resus if it has been turned on elsewhere
|
||||
regs.CLOCKS.CLK_SYS_RESUS_CTRL.raw = 0;
|
||||
|
||||
if (config.xosc_configured) {
|
||||
regs.WATCHDOG.TICK.modify(.{
|
||||
.CYCLES = xosc_freq / 1_000_000,
|
||||
.ENABLE = 1,
|
||||
});
|
||||
xosc.init();
|
||||
}
|
||||
|
||||
// switch sys and ref cleanly away from aux sources if they're
|
||||
// configured to use/be used from PLLs
|
||||
if (config.sys) |sys| switch (sys.input.source) {
|
||||
.pll_usb, .pll_sys => {
|
||||
regs.CLOCKS.CLK_SYS_CTRL.modify(.{ .SRC = 0 });
|
||||
while (regs.CLOCKS.CLK_SYS_SELECTED.* != 1) {}
|
||||
},
|
||||
else => {},
|
||||
};
|
||||
|
||||
if (config.ref) |ref| switch (ref.input.source) {
|
||||
.pll_usb, .pll_sys => {
|
||||
regs.CLOCKS.CLK_REF_CTRL.modify(.{ .SRC = 0 });
|
||||
while (regs.CLOCKS.CLK_REF_SELECTED.* != 1) {}
|
||||
},
|
||||
else => {},
|
||||
};
|
||||
|
||||
// initialize PLLs
|
||||
if (config.pll_sys) |pll_sys_config| pll.sys.apply(pll_sys_config);
|
||||
if (config.pll_usb) |pll_usb_config| pll.usb.apply(pll_usb_config);
|
||||
|
||||
// initialize clock generators
|
||||
if (config.ref) |ref| try ref.apply();
|
||||
if (config.usb) |usb| try usb.apply();
|
||||
if (config.adc) |adc| try adc.apply();
|
||||
if (config.rtc) |rtc| try rtc.apply();
|
||||
if (config.peri) |peri| try peri.apply();
|
||||
}
|
||||
|
||||
/// returns frequency of a clock or pll, if unconfigured it returns null
|
||||
pub fn getFrequency(config: GlobalConfiguration) ?u32 {
|
||||
_ = config;
|
||||
return null;
|
||||
}
|
||||
};
|
||||
|
||||
pub const Configuration = struct {
|
||||
generator: Generator,
|
||||
input: struct {
|
||||
source: Source,
|
||||
freq: u32,
|
||||
},
|
||||
output_freq: u32,
|
||||
|
||||
pub fn apply(config: Configuration) !void {
|
||||
const generator = config.generator;
|
||||
const input = config.input;
|
||||
const output_freq = config.output_freq;
|
||||
|
||||
// source frequency has to be faster because dividing will always reduce.
|
||||
assert(input.freq >= output_freq);
|
||||
if (output_freq < input.freq)
|
||||
return error.InvalidArgs;
|
||||
|
||||
const div = @intCast(u32, (@intCast(u64, input.freq) << 8) / 8);
|
||||
|
||||
// check divisor
|
||||
if (div > generator.getDiv())
|
||||
generator.setDiv(div);
|
||||
|
||||
if (generator.hasGlitchlessMux() and input.source == .src_aux) {
|
||||
// TODO: clear bits
|
||||
while (!generator.selected()) {
|
||||
// TODO: is leaving this empty good enough? pico sdk has `tight_loop_contents()`
|
||||
}
|
||||
} else {
|
||||
// uh stuff
|
||||
}
|
||||
|
||||
// set aux mux first and then glitchless mex if this clock has one
|
||||
if (generator.hasGlitchlessMux()) {
|
||||
// write to clock ctrl
|
||||
while (!generator.selected()) {}
|
||||
}
|
||||
|
||||
generator.enable();
|
||||
generator.setDiv(div);
|
||||
// should we store global state on configured clocks?
|
||||
}
|
||||
};
|
||||
|
||||
//pub fn countFrequencyKhz(source: Source) u32 {}
|
||||
|
||||
@ -0,0 +1,153 @@
|
||||
//! ### Function Select Table
|
||||
//!
|
||||
//! GPIO | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9
|
||||
//! -------|----------|-----------|----------|--------|-----|------|------|---------------|----
|
||||
//! 0 | SPI0 RX | UART0 TX | I2C0 SDA | PWM0 A | SIO | PIO0 | PIO1 | | USB OVCUR DET
|
||||
//! 1 | SPI0 CSn | UART0 RX | I2C0 SCL | PWM0 B | SIO | PIO0 | PIO1 | | USB VBUS DET
|
||||
//! 2 | SPI0 SCK | UART0 CTS | I2C1 SDA | PWM1 A | SIO | PIO0 | PIO1 | | USB VBUS EN
|
||||
//! 3 | SPI0 TX | UART0 RTS | I2C1 SCL | PWM1 B | SIO | PIO0 | PIO1 | | USB OVCUR DET
|
||||
//! 4 | SPI0 RX | UART1 TX | I2C0 SDA | PWM2 A | SIO | PIO0 | PIO1 | | USB VBUS DET
|
||||
//! 5 | SPI0 CSn | UART1 RX | I2C0 SCL | PWM2 B | SIO | PIO0 | PIO1 | | USB VBUS EN
|
||||
//! 6 | SPI0 SCK | UART1 CTS | I2C1 SDA | PWM3 A | SIO | PIO0 | PIO1 | | USB OVCUR DET
|
||||
//! 7 | SPI0 TX | UART1 RTS | I2C1 SCL | PWM3 B | SIO | PIO0 | PIO1 | | USB VBUS DET
|
||||
//! 8 | SPI1 RX | UART1 TX | I2C0 SDA | PWM4 A | SIO | PIO0 | PIO1 | | USB VBUS EN
|
||||
//! 9 | SPI1 CSn | UART1 RX | I2C0 SCL | PWM4 B | SIO | PIO0 | PIO1 | | USB OVCUR DET
|
||||
//! 10 | SPI1 SCK | UART1 CTS | I2C1 SDA | PWM5 A | SIO | PIO0 | PIO1 | | USB VBUS DET
|
||||
//! 11 | SPI1 TX | UART1 RTS | I2C1 SCL | PWM5 B | SIO | PIO0 | PIO1 | | USB VBUS EN
|
||||
//! 12 | SPI1 RX | UART0 TX | I2C0 SDA | PWM6 A | SIO | PIO0 | PIO1 | | USB OVCUR DET
|
||||
//! 13 | SPI1 CSn | UART0 RX | I2C0 SCL | PWM6 B | SIO | PIO0 | PIO1 | | USB VBUS DET
|
||||
//! 14 | SPI1 SCK | UART0 CTS | I2C1 SDA | PWM7 A | SIO | PIO0 | PIO1 | | USB VBUS EN
|
||||
//! 15 | SPI1 TX | UART0 RTS | I2C1 SCL | PWM7 B | SIO | PIO0 | PIO1 | | USB OVCUR DET
|
||||
//! 16 | SPI0 RX | UART0 TX | I2C0 SDA | PWM0 A | SIO | PIO0 | PIO1 | | USB VBUS DET
|
||||
//! 17 | SPI0 CSn | UART0 RX | I2C0 SCL | PWM0 B | SIO | PIO0 | PIO1 | | USB VBUS EN
|
||||
//! 18 | SPI0 SCK | UART0 CTS | I2C1 SDA | PWM1 A | SIO | PIO0 | PIO1 | | USB OVCUR DET
|
||||
//! 19 | SPI0 TX | UART0 RTS | I2C1 SCL | PWM1 B | SIO | PIO0 | PIO1 | | USB VBUS DET
|
||||
//! 20 | SPI0 RX | UART1 TX | I2C0 SDA | PWM2 A | SIO | PIO0 | PIO1 | CLOCK GPIN0 | USB VBUS EN
|
||||
//! 21 | SPI0 CSn | UART1 RX | I2C0 SCL | PWM2 B | SIO | PIO0 | PIO1 | CLOCK GPOUT0 | USB OVCUR DET
|
||||
//! 22 | SPI0 SCK | UART1 CTS | I2C1 SDA | PWM3 A | SIO | PIO0 | PIO1 | CLOCK GPIN1 | USB VBUS DET
|
||||
//! 23 | SPI0 TX | UART1 RTS | I2C1 SCL | PWM3 B | SIO | PIO0 | PIO1 | CLOCK GPOUT1 | USB VBUS EN
|
||||
//! 24 | SPI1 RX | UART1 TX | I2C0 SDA | PWM4 A | SIO | PIO0 | PIO1 | CLOCK GPOUT2 | USB OVCUR DET
|
||||
//! 25 | SPI1 CSn | UART1 RX | I2C0 SCL | PWM4 B | SIO | PIO0 | PIO1 | CLOCK GPOUT3 | USB VBUS DET
|
||||
//! 26 | SPI1 SCK | UART1 CTS | I2C1 SDA | PWM5 A | SIO | PIO0 | PIO1 | | USB VBUS EN
|
||||
//! 27 | SPI1 TX | UART1 RTS | I2C1 SCL | PWM5 B | SIO | PIO0 | PIO1 | | USB OVCUR DET
|
||||
//! 28 | SPI1 RX | UART0 TX | I2C0 SDA | PWM6 A | SIO | PIO0 | PIO1 | | USB VBUS DET
|
||||
//! 29 | SPI1 CSn | UART0 RX | I2C0 SCL | PWM6 B | SIO | PIO0 | PIO1 | | USB VBUS EN
|
||||
|
||||
const std = @import("std");
|
||||
const microzig = @import("microzig");
|
||||
const regs = microzig.chip.registers;
|
||||
const assert = std.debug.assert;
|
||||
|
||||
pub const Function = enum(u5) {
|
||||
xip,
|
||||
spi,
|
||||
uart,
|
||||
i2c,
|
||||
pwm,
|
||||
sio,
|
||||
pio0,
|
||||
pio1,
|
||||
gpck,
|
||||
usb,
|
||||
@"null" = 0x1f,
|
||||
};
|
||||
|
||||
pub const Direction = enum(u1) {
|
||||
in,
|
||||
out,
|
||||
};
|
||||
|
||||
pub const IrqLevel = enum(u2) {
|
||||
low,
|
||||
high,
|
||||
fall,
|
||||
rise,
|
||||
};
|
||||
|
||||
pub const IrqCallback = fn (gpio: u32, events: u32) callconv(.C) void;
|
||||
|
||||
pub const Override = enum {
|
||||
normal,
|
||||
invert,
|
||||
low,
|
||||
high,
|
||||
};
|
||||
|
||||
pub const SlewRate = enum {
|
||||
slow,
|
||||
fast,
|
||||
};
|
||||
|
||||
pub const DriveStrength = enum {
|
||||
ma_2,
|
||||
ma_4,
|
||||
ma_8,
|
||||
ma_12,
|
||||
};
|
||||
|
||||
pub const Enabled = enum {
|
||||
disabled,
|
||||
enabled,
|
||||
};
|
||||
|
||||
//const gpio_num = gpio_num: {
|
||||
// // calculate max gpios using comptime parsing
|
||||
//};
|
||||
|
||||
/// Initialize a GPIO, set func to SIO
|
||||
pub inline fn init(comptime gpio: u32) void {
|
||||
regs.SIO.GPIO_OE_CLR.raw = 1 << gpio;
|
||||
regs.SIO.GPIO_OUT_CLR.raw = 1 << gpio;
|
||||
setFunction(gpio, .sio);
|
||||
}
|
||||
|
||||
/// Reset GPIO back to null function (disables it)
|
||||
pub inline fn deinit(comptime gpio: u32) void {
|
||||
setFunction(gpio, .@"null");
|
||||
}
|
||||
|
||||
pub inline fn setDir(comptime gpio: u32, direction: Direction) void {
|
||||
switch (direction) {
|
||||
.in => regs.SIO.GPIO_OE_CLR.raw |= (1 << gpio),
|
||||
.out => regs.SIO.GPIO_OE_SET.raw &= (1 << gpio),
|
||||
}
|
||||
}
|
||||
|
||||
/// Drive a single GPIO high/low
|
||||
pub inline fn put(comptime gpio: u32, value: u1) void {
|
||||
switch (value) {
|
||||
0 => regs.SIO.GPIO_OUT.raw &= ~@as(u32, 1 << gpio),
|
||||
1 => regs.SIO.GPIO_OUT.raw |= (1 << gpio),
|
||||
}
|
||||
}
|
||||
|
||||
pub inline fn setFunction(comptime gpio: u32, function: Function) void {
|
||||
const reg_name = comptime std.fmt.comptimePrint("GPIO{}_CTRL", .{gpio});
|
||||
@field(regs.IO_BANK0, reg_name).write(.{
|
||||
.FUNCSEL = @enumToInt(function),
|
||||
.OUTOVER = 0,
|
||||
.INOVER = 0,
|
||||
.IRQOVER = 0,
|
||||
.OEOVER = 0,
|
||||
});
|
||||
}
|
||||
|
||||
// setting both uplls enables a "bus keep" function, a weak pull to whatever
|
||||
// is current high/low state of GPIO
|
||||
//pub fn setPulls(gpio: u32, up: bool, down: bool) void {}
|
||||
//
|
||||
//pub fn pullUp(gpio: u32) void {}
|
||||
//
|
||||
//pub fn pullDown(gpio: u32) void {}
|
||||
//pub fn disablePulls(gpio: u32) void {}
|
||||
//pub fn setIrqOver(gpio: u32, value: u32) void {}
|
||||
//pub fn setOutOver(gpio: u32, value: u32) void {}
|
||||
//pub fn setInOver(gpio: u32, value: u32) void {}
|
||||
//pub fn setOeOver(gpio: u32, value: u32) void {}
|
||||
//pub fn setInputEnabled(gpio: u32, enabled: Enabled) void {}
|
||||
//pub fn setinputHysteresisEnabled(gpio: u32, enabled: Enabled) void {}
|
||||
//pub fn setSlewRate(gpio: u32, slew_rate: SlewRate) void {}
|
||||
//pub fn setDriveStrength(gpio: u32, drive: DriveStrength) void {}
|
||||
//pub fn setIrqEnabled(gpio: u32, events: IrqEvents) void {}
|
||||
//pub fn acknowledgeIrq(gpio: u32, events: IrqEvents) void {}
|
||||
|
||||
@ -0,0 +1,97 @@
|
||||
const std = @import("std");
|
||||
const microzig = @import("microzig");
|
||||
const assert = std.debug.assert;
|
||||
|
||||
const regs = microzig.chip.registers;
|
||||
const xosc_freq = microzig.board.xosc_freq;
|
||||
|
||||
pub const Configuration = struct {
|
||||
refdiv: u6,
|
||||
vco_freq: u32,
|
||||
postdiv1: u3,
|
||||
postdiv2: u3,
|
||||
};
|
||||
|
||||
pub const sys = @intToPtr(*volatile PLL, regs.PLL_SYS.base_address);
|
||||
pub const usb = @intToPtr(*volatile PLL, regs.PLL_USB.base_address);
|
||||
|
||||
pub const PLL = packed struct {
|
||||
cs: @TypeOf(regs.PLL_SYS.CS),
|
||||
pwr: @TypeOf(regs.PLL_SYS.PWR),
|
||||
fbdiv_int: @TypeOf(regs.PLL_SYS.FBDIV_INT),
|
||||
prim: @TypeOf(regs.PLL_SYS.PRIM),
|
||||
|
||||
comptime {
|
||||
// bunch of comptime checks in here to validate the layout
|
||||
assert(0 == @bitOffsetOf(PLL, "cs"));
|
||||
assert(32 == @bitOffsetOf(PLL, "pwr"));
|
||||
assert(64 == @bitOffsetOf(PLL, "fbdiv_int"));
|
||||
assert(96 == @bitOffsetOf(PLL, "prim"));
|
||||
}
|
||||
|
||||
pub fn isLocked(pll: *const volatile PLL) bool {
|
||||
return pll.cs.read().LOCK == 1;
|
||||
}
|
||||
|
||||
pub fn reset(pll: *const volatile PLL) void {
|
||||
switch (pll) {
|
||||
sys => {
|
||||
regs.RESETS.RESET.modify(.{ .pll_sys = 1 });
|
||||
regs.RESETS.RESET.modify(.{ .pll_sys = 0 });
|
||||
while (regs.RESETS.RESET_DONE.read().pll_sys == 1) {}
|
||||
},
|
||||
usb => {
|
||||
regs.RESETS.RESET.modify(.{ .pll_usb = 1 });
|
||||
regs.RESETS.RESET.modify(.{ .pll_usb = 0 });
|
||||
while (regs.RESETS.RESET_DONE.read().pll_usb == 1) {}
|
||||
},
|
||||
else => unreachable,
|
||||
}
|
||||
}
|
||||
|
||||
pub fn apply(pll: *volatile PLL, comptime config: Configuration) void {
|
||||
const ref_freq = xosc_freq / @as(u32, config.refdiv);
|
||||
const fbdiv = @intCast(u12, config.vco_freq / ref_freq);
|
||||
|
||||
assert(fbdiv >= 16 and fbdiv <= 320);
|
||||
assert(config.postdiv1 >= 1 and config.postdiv1 <= 7);
|
||||
assert(config.postdiv2 >= 1 and config.postdiv2 <= 7);
|
||||
assert(config.postdiv2 <= config.postdiv1);
|
||||
assert(ref_freq <= config.vco_freq / 16);
|
||||
|
||||
// 1. program reference clock divider
|
||||
// 2. program feedback divider
|
||||
// 3. turn on the main power and vco
|
||||
// 4. wait for vco to lock
|
||||
// 5. set up post dividers and turn them on
|
||||
|
||||
// do not bother a PLL which is already configured
|
||||
if (pll.isLocked() and
|
||||
config.refdiv == pll.cs.read().REFDIV and
|
||||
fbdiv == pll.fbdiv_int.read() and
|
||||
config.postdiv1 == pll.prim.read().POSTDIV1 and
|
||||
config.postdiv2 == pll.prim.read().POSTDIV2)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
pll.reset();
|
||||
|
||||
// load vco related dividers
|
||||
pll.cs.modify(.{ .REFDIV = config.refdiv });
|
||||
pll.fbdiv_int.modify(fbdiv);
|
||||
|
||||
// turn on PLL
|
||||
pll.pwr.modify(.{ .PD = 0, .VCOPD = 0 });
|
||||
|
||||
// wait for PLL to lock
|
||||
while (!pll.isLocked()) {}
|
||||
|
||||
pll.prim.modify(.{
|
||||
.POSTDIV1 = config.postdiv1,
|
||||
.POSTDIV2 = config.postdiv2,
|
||||
});
|
||||
|
||||
pll.pwr.modify(.{ .POSTDIVPD = 0 });
|
||||
}
|
||||
};
|
||||
@ -0,0 +1,38 @@
|
||||
pub const xosc_freq = 12_000_000;
|
||||
|
||||
// TODO: improve interface so that user can use a custom implementation and
|
||||
// automatically checksum it.
|
||||
pub export const _BOOT2: [256]u8 linksection(".boot2") = [_]u8{
|
||||
0x00, 0xb5, 0x32, 0x4b, 0x21, 0x20, 0x58, 0x60,
|
||||
0x98, 0x68, 0x02, 0x21, 0x88, 0x43, 0x98, 0x60,
|
||||
0xd8, 0x60, 0x18, 0x61, 0x58, 0x61, 0x2e, 0x4b,
|
||||
0x00, 0x21, 0x99, 0x60, 0x02, 0x21, 0x59, 0x61,
|
||||
0x01, 0x21, 0xf0, 0x22, 0x99, 0x50, 0x2b, 0x49,
|
||||
0x19, 0x60, 0x01, 0x21, 0x99, 0x60, 0x35, 0x20,
|
||||
0x00, 0xf0, 0x44, 0xf8, 0x02, 0x22, 0x90, 0x42,
|
||||
0x14, 0xd0, 0x06, 0x21, 0x19, 0x66, 0x00, 0xf0,
|
||||
0x34, 0xf8, 0x19, 0x6e, 0x01, 0x21, 0x19, 0x66,
|
||||
0x00, 0x20, 0x18, 0x66, 0x1a, 0x66, 0x00, 0xf0,
|
||||
0x2c, 0xf8, 0x19, 0x6e, 0x19, 0x6e, 0x19, 0x6e,
|
||||
0x05, 0x20, 0x00, 0xf0, 0x2f, 0xf8, 0x01, 0x21,
|
||||
0x08, 0x42, 0xf9, 0xd1, 0x00, 0x21, 0x99, 0x60,
|
||||
0x1b, 0x49, 0x19, 0x60, 0x00, 0x21, 0x59, 0x60,
|
||||
0x1a, 0x49, 0x1b, 0x48, 0x01, 0x60, 0x01, 0x21,
|
||||
0x99, 0x60, 0xeb, 0x21, 0x19, 0x66, 0xa0, 0x21,
|
||||
0x19, 0x66, 0x00, 0xf0, 0x12, 0xf8, 0x00, 0x21,
|
||||
0x99, 0x60, 0x16, 0x49, 0x14, 0x48, 0x01, 0x60,
|
||||
0x01, 0x21, 0x99, 0x60, 0x01, 0xbc, 0x00, 0x28,
|
||||
0x00, 0xd0, 0x00, 0x47, 0x12, 0x48, 0x13, 0x49,
|
||||
0x08, 0x60, 0x03, 0xc8, 0x80, 0xf3, 0x08, 0x88,
|
||||
0x08, 0x47, 0x03, 0xb5, 0x99, 0x6a, 0x04, 0x20,
|
||||
0x01, 0x42, 0xfb, 0xd0, 0x01, 0x20, 0x01, 0x42,
|
||||
0xf8, 0xd1, 0x03, 0xbd, 0x02, 0xb5, 0x18, 0x66,
|
||||
0x18, 0x66, 0xff, 0xf7, 0xf2, 0xff, 0x18, 0x6e,
|
||||
0x18, 0x6e, 0x02, 0xbd, 0x00, 0x00, 0x02, 0x40,
|
||||
0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x07, 0x00,
|
||||
0x00, 0x03, 0x5f, 0x00, 0x21, 0x22, 0x00, 0x00,
|
||||
0xf4, 0x00, 0x00, 0x18, 0x22, 0x20, 0x00, 0xa0,
|
||||
0x00, 0x01, 0x00, 0x10, 0x08, 0xed, 0x00, 0xe0,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x74, 0xb2, 0x4e, 0x7a,
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue