core registers for the m0plus (#26)
* core registers for the m0plus * do proper optional handlingwch-ch32v003
Matt Knight
2 years ago
committed by
Matt Knight
parent
6f4850dab7
commit
9af2e274f1
@ -0,0 +1,82 @@
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const std = @import("std");
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const svd = @import("svd.zig");
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const Database = @import("Database.zig");
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const cores = struct {
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const cortex_m0plus = @import("cmsis/cortex_m0plus.zig");
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};
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fn addSysTickRegisters(db: *Database, scs: Database.PeripheralIndex) !void {
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const systick = try db.addClusterToPeripheral(scs, .{
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.name = "SysTick",
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.description = "System Tick Timer",
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.addr_offset = 0x10,
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});
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const regs = try db.addRegistersToCluster(systick, &.{
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.{
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.name = "CTRL",
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.description = "SysTick Control and Status Register",
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.addr_offset = 0x0,
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},
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.{
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.name = "LOAD",
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.description = "SysTick Reload Value Register",
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.addr_offset = 0x4,
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},
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.{
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.name = "VAL",
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.description = "SysTick Current Value Register",
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.addr_offset = 0x8,
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},
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.{
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.name = "CALIB",
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.description = "SysTick Calibration Register",
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.access = .read_only,
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.addr_offset = 0xc,
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},
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});
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const ctrl = regs.begin;
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try db.addFieldsToRegister(ctrl, &.{
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.{ .name = "ENABLE", .offset = 0, .width = 1 },
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.{ .name = "TICKINT", .offset = 1, .width = 1 },
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.{ .name = "CLKSOURCE", .offset = 2, .width = 1 },
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.{ .name = "COUNTFLAG", .offset = 16, .width = 1 },
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});
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const load = regs.begin + 1;
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try db.addFieldsToRegister(load, &.{
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.{ .name = "RELOAD", .offset = 0, .width = 24 },
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});
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const val = regs.begin + 2;
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try db.addFieldsToRegister(val, &.{
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.{ .name = "CURRENT", .offset = 0, .width = 24 },
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});
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const calib = regs.begin + 3;
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try db.addFieldsToRegister(calib, &.{
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.{ .name = "TENMS", .offset = 0, .width = 24 },
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.{ .name = "SKEW", .offset = 30, .width = 1 },
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.{ .name = "NOREF", .offset = 31, .width = 1 },
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});
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}
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pub fn addCoreRegisters(db: *Database, cpu_name: svd.CpuName) !void {
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const scs = @intCast(Database.PeripheralIndex, db.peripherals.items.len);
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try db.peripherals.append(db.gpa, .{
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.name = "SCS",
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.version = null,
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.description = "System Control Space",
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.base_addr = 0xe000e000,
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});
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try db.register_properties.peripheral.size.put(db.gpa, scs, 32);
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if (db.cpu) |cpu| if (!cpu.vendor_systick_config)
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try addSysTickRegisters(db, scs);
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inline for (@typeInfo(cores).Struct.decls) |decl|
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if (cpu_name == @field(svd.CpuName, decl.name))
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try @field(cores, decl.name).addCoreRegisters(db, scs);
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}
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@ -0,0 +1,241 @@
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const std = @import("std");
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const Database = @import("../Database.zig");
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const Register = @import("../Register.zig");
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pub fn addCoreRegisters(db: *Database, scs: Database.PeripheralIndex) !void {
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_ = db;
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_ = scs;
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const nvic = try db.addClusterToPeripheral(scs, .{
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.name = "NVIC",
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.description = "Nested Vectored Interrupt Controller",
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.addr_offset = 0x100,
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});
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_ = try db.addRegistersToCluster(nvic, &.{
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.{
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.name = "ISER",
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.description = "Interrupt Set Enable Register",
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.addr_offset = 0x000,
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},
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.{
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.name = "ICER",
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.description = "Interrupt Clear Enable Register",
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.addr_offset = 0x80,
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},
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.{
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.name = "ISPR",
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.description = "Interrupt Set Pending Register",
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.addr_offset = 0x100,
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},
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.{
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.name = "ICPR",
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.description = "Interrupt Clear Pending Register",
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.addr_offset = 0x180,
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},
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.{
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.name = "IP",
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.description = "Interrupt Priority Register",
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.addr_offset = 0x300,
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//.dimension = .{
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// .dim = 8,
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//},
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},
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});
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const scb = try db.addClusterToPeripheral(scs, .{
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.name = "SCB",
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.description = "System Control Block",
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.addr_offset = 0xd00,
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});
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var scb_regs = std.ArrayList(Register).init(db.gpa);
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defer scb_regs.deinit();
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try scb_regs.appendSlice(&.{
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.{
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.name = "CPUID",
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.addr_offset = 0x000,
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.access = .read_only,
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},
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.{
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.name = "ICSR",
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.description = "Interrupt Control and State Register",
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.addr_offset = 0x004,
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},
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.{
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.name = "AIRCR",
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.description = "Application Interrupt and Reset Control Register",
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.addr_offset = 0x00c,
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},
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.{
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.name = "SCR",
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.description = "System Control Register",
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.addr_offset = 0x010,
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},
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.{
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.name = "CCR",
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.description = "Configuration Control Register",
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.addr_offset = 0x014,
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},
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.{
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.name = "SHP",
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.description = "System Handlers Priority Registers. [0] is RESERVED",
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.addr_offset = 0x01c,
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//.dimension = .{
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// .dim = 2,
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//},
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},
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.{
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.name = "SHCSR",
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.description = "System Handler Control and State Register",
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.addr_offset = 0x024,
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},
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});
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if (db.cpu) |cpu| if (cpu.vtor_present) {
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try scb_regs.append(.{
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.name = "VTOR",
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.description = "Vector Table Offset Register",
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.addr_offset = 0x08,
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});
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};
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var regs = try db.addRegistersToCluster(scb, scb_regs.items);
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const cpuid = regs.begin;
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try db.addFieldsToRegister(cpuid, &.{
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.{ .name = "REVISION", .offset = 0, .width = 4 },
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.{ .name = "PARTNO", .offset = 4, .width = 12 },
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.{ .name = "ARCHITECTURE", .offset = 16, .width = 4 },
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.{ .name = "VARIANT", .offset = 20, .width = 4 },
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.{ .name = "IMPLEMENTER", .offset = 24, .width = 8 },
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});
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const icsr = regs.begin + 1;
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try db.addFieldsToRegister(icsr, &.{
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.{ .name = "VECTACTIVE", .offset = 0, .width = 9 },
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.{ .name = "VECTPENDING", .offset = 12, .width = 9 },
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.{ .name = "ISRPENDING", .offset = 22, .width = 1 },
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.{ .name = "ISRPREEMPT", .offset = 23, .width = 1 },
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.{ .name = "PENDSTCLR", .offset = 25, .width = 1 },
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.{ .name = "PENDSTSET", .offset = 26, .width = 1 },
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.{ .name = "PENDSVCLR", .offset = 27, .width = 1 },
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.{ .name = "PENDSVSET", .offset = 28, .width = 1 },
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.{ .name = "NMIPENDSET", .offset = 31, .width = 1 },
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});
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const aircr = regs.begin + 2;
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try db.addFieldsToRegister(aircr, &.{
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.{ .name = "VECTCLRACTIVE", .offset = 1, .width = 1 },
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.{ .name = "SYSRESETREQ", .offset = 2, .width = 1 },
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.{ .name = "ENDIANESS", .offset = 15, .width = 1 },
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.{ .name = "VECTKEY", .offset = 16, .width = 16 },
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});
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const scr = regs.begin + 3;
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try db.addFieldsToRegister(scr, &.{
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.{ .name = "SLEEPONEXIT", .offset = 1, .width = 1 },
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.{ .name = "SLEEPDEEP", .offset = 2, .width = 1 },
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.{ .name = "SEVONPEND", .offset = 4, .width = 1 },
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});
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const ccr = regs.begin + 4;
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try db.addFieldsToRegister(ccr, &.{
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.{ .name = "UNALIGN_TRP", .offset = 3, .width = 1 },
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.{ .name = "STKALIGN", .offset = 9, .width = 1 },
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});
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const shcsr = regs.begin + 6;
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try db.addFieldsToRegister(shcsr, &.{
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.{ .name = "SVCALLPENDED", .offset = 15, .width = 1 },
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});
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if (db.cpu) |cpu| if (cpu.vtor_present) {
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const vtor = regs.begin + 7;
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try db.addFieldsToRegister(vtor, &.{.{
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.name = "TBLOFF",
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.offset = 8,
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.width = 24,
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}});
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};
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if (db.cpu) |cpu| if (cpu.mpu_present)
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try addMpuRegisters(db, scs);
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}
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fn addMpuRegisters(db: *Database, scs: Database.PeripheralIndex) !void {
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const mpu = try db.addClusterToPeripheral(scs, .{
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.name = "MPU",
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.description = "Memory Protection Unit",
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.addr_offset = 0xd90,
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});
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const regs = try db.addRegistersToCluster(mpu, &.{
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.{
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.name = "TYPE",
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.description = "MPU Type Register",
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.addr_offset = 0x00,
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.access = .read_only,
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},
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.{
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.name = "CTRL",
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.description = "MPU Control Register",
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.addr_offset = 0x04,
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},
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.{
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.name = "RNR",
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.description = "MPU Region RNRber Register",
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.addr_offset = 0x08,
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},
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.{
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.name = "RBAR",
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.description = "MPU Region Base Address Register",
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.addr_offset = 0x0c,
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},
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.{
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.name = "RASR",
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.description = "MPU Region Attribute and Size Register",
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.addr_offset = 0x10,
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},
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});
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const type_reg = regs.begin;
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try db.addFieldsToRegister(type_reg, &.{
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.{ .name = "SEPARATE", .offset = 0, .width = 1 },
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.{ .name = "DREGION", .offset = 8, .width = 8 },
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.{ .name = "IREGION", .offset = 16, .width = 8 },
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});
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const ctrl = regs.begin + 1;
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try db.addFieldsToRegister(ctrl, &.{
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.{ .name = "ENABLE", .offset = 0, .width = 1 },
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.{ .name = "HFNMIENA", .offset = 1, .width = 1 },
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.{ .name = "PRIVDEFENA", .offset = 2, .width = 1 },
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});
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const rnr = regs.begin + 2;
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try db.addFieldsToRegister(rnr, &.{
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.{ .name = "REGION", .offset = 0, .width = 8 },
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});
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const rbar = regs.begin + 3;
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try db.addFieldsToRegister(rbar, &.{
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.{ .name = "REGION", .offset = 0, .width = 4 },
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.{ .name = "VALID", .offset = 4, .width = 1 },
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.{ .name = "ADDR", .offset = 8, .width = 24 },
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});
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const rasr = regs.begin + 4;
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try db.addFieldsToRegister(rasr, &.{
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.{ .name = "ENABLE", .offset = 0, .width = 1 },
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.{ .name = "SIZE", .offset = 1, .width = 5 },
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.{ .name = "SRD", .offset = 8, .width = 8 },
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.{ .name = "B", .offset = 16, .width = 1 },
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.{ .name = "C", .offset = 17, .width = 1 },
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.{ .name = "S", .offset = 18, .width = 1 },
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.{ .name = "TEX", .offset = 19, .width = 3 },
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.{ .name = "AP", .offset = 24, .width = 3 },
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.{ .name = "XN", .offset = 28, .width = 1 },
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});
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}
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