Makes UART compile for LPC1768.

build.zig

@@ -48,6 +48,11 @@ pub fn build(b: *std.build.Builder) void {
 fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source: []const u8, backing: Backing) *std.build.LibExeObjStep {
     const Pkg = std.build.Pkg;
 
+    const microzig_base = Pkg{
+        .name = "microzig",
+        .path = "src/core/microzig.zig",
+    };
+
     const chip = switch (backing) {
         .chip => |c| c,
         .board => |b| b.chip,
@@ -59,11 +64,12 @@ fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source:
         .name = "chip",
         .path = chip.path,
         .dependencies = &[_]Pkg{
+            microzig_base,
             pkgs.mmio,
             Pkg{
                 .name = "cpu",
                 .path = chip.cpu.path,
-                .dependencies = &[_]Pkg{pkgs.mmio},
+                .dependencies = &[_]Pkg{ microzig_base, pkgs.mmio },
             },
             Pkg{
                 .name = "microzig-linker",
@@ -184,22 +190,22 @@ fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source:
     switch (backing) {
         .chip => {
             exe.addPackage(Pkg{
-                .name = "microzig",
-                .path = "src/core/microzig.zig",
+                .name = microzig_base.name,
+                .path = microzig_base.path,
                 .dependencies = &[_]Pkg{ config_pkg, chip_package },
             });
         },
         .board => |board| {
             exe.addPackage(Pkg{
-                .name = "microzig",
-                .path = "src/core/microzig.zig",
+                .name = microzig_base.name,
+                .path = microzig_base.path,
                 .dependencies = &[_]Pkg{
                     config_pkg,
                     chip_package,
                     Pkg{
                         .name = "board",
                         .path = board.path,
-                        .dependencies = &[_]Pkg{ chip_package, pkgs.mmio },
+                        .dependencies = &[_]Pkg{ microzig_base, chip_package, pkgs.mmio },
                     },
                 },
             });

src/core/clock.zig

@@ -1,11 +1,32 @@
 const std = @import("std");
 const root = @import("root");
+const micro = @import("microzig.zig");
+
+/// An enumeration of clock sources.
+pub const Source = enum {
+    none,
+    application,
+    board,
+    chip,
+    cpu,
+};
 
 /// Is `true` when microzig has a clock frequency available.
-pub const has_clock = @hasDecl(root, "cpu_frequency");
+/// Clock can be provided by several clock sources
+pub const has_clock = (clock_source_type != void);
 
 /// Returns `true` when the frequency can change at runtime.
-pub const is_dynamic = has_clock and !@typeInfo(@TypeOf(&root.cpu_frequency)).Pointer.is_const;
+pub const is_dynamic = has_clock and !@typeInfo(@TypeOf(&@field(clock_source_type, freq_decl_name))).Pointer.is_const;
+
+/// Contains the source which provides microzig with clock information.
+pub const source: Source = switch (clock_source_type) {
+    root => .application,
+    micro.board => .board,
+    micro.chip => .chip,
+    micro.cpu => .cpu,
+    no_clock_source_type => .none,
+    else => unreachable,
+};
 
 /// Ensures that microzig has a clock available. This will @compileError when no clock is available, otherwise, it will be a no-op.
 pub fn ensure() void {
@@ -16,5 +37,26 @@ pub fn ensure() void {
 /// Returns the current cpu frequency in hertz.
 pub fn get() callconv(.Inline) u32 {
     ensure();
-    return root.cpu_frequency;
+    return @field(clock_source_type, freq_decl_name);
+}
+
+const freq_decl_name = "cpu_frequency";
+
+const no_clock_source_type = opaque {};
+const clock_source_type = if (@hasDecl(root, freq_decl_name))
+    root
+else if (micro.config.has_board and @hasDecl(micro.board, freq_decl_name))
+    micro.board
+else if (@hasDecl(micro.chip, freq_decl_name))
+    micro.chip
+else if (@hasDecl(micro.cpu, freq_decl_name))
+    micro.cpu
+else
+    no_clock_source_type;
+
+comptime {
+    if (source != .application) {
+        if (is_dynamic)
+            @compileError("clock source " ++ @tagName(source) ++ " is not allowed to be dynamic. Only the application (root file) is allowed to provide a dynamic clock frequency!");
+    }
 }

src/core/microzig.zig

@@ -9,6 +9,9 @@ pub const config = @import("microzig-config");
 /// Provides access to the low level features of the current microchip.
 pub const chip = @import("chip");
 
+/// Provides access to board features or is `void` when no board is present.
+pub const board = if (config.has_board) @import("board") else void;
+
 /// Provides access to the low level features of the CPU.
 pub const cpu = chip.cpu;
 
@@ -18,13 +21,13 @@ pub const interrupts = @import("interrupts.zig");
 /// Module that provides clock related functions
 pub const clock = @import("clock.zig");
 
-const gpio = @import("gpio.zig");
+pub const gpio = @import("gpio.zig");
 pub const Gpio = gpio.Gpio;
 
-const pin = @import("pin.zig");
+pub const pin = @import("pin.zig");
 pub const Pin = pin.Pin;
 
-const uart = @import("uart.zig");
+pub const uart = @import("uart.zig");
 pub const Uart = uart.Uart;
 
 /// The microzig panic handler. Will disable interrupts and loop endlessly.

src/core/mmio.zig

@@ -1,4 +1,3 @@
-
 const std = @import("std");
 
 pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile MMIO(size, PackedT) {
@@ -32,20 +31,20 @@ pub fn MMIO(comptime size: u8, comptime PackedT: type) type {
             addr.* = @bitCast(IntT, val);
         }
 
-        pub fn set(addr: *volatile Self, fields: anytype) void {
-            var val = read();
+        pub fn modify(addr: *volatile Self, fields: anytype) void {
+            var val = read(addr);
             inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| {
                 @field(val, field.name) = @field(fields, field.name);
             }
-            write(val);
+            write(addr, val);
         }
 
         pub fn toggle(addr: *volatile Self, fields: anytype) void {
-            var val = read();
+            var val = read(addr);
             inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| {
                 @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?));
             }
-            write(val);
+            write(addr, val);
         }
     };
 }

src/core/uart.zig

@@ -2,6 +2,55 @@ const std = @import("std");
 const micro = @import("microzig.zig");
 const chip = @import("chip");
 
+pub fn Uart(comptime index: usize) type {
+    const SystemUart = chip.Uart(index);
+    return struct {
+        const Self = @This();
+
+        internal: SystemUart,
+
+        /// Initializes the UART with the given config and returns a handle to the uart.
+        pub fn init(config: Config) InitError!Self {
+            micro.clock.ensure();
+            return Self{
+                .internal = try SystemUart.init(config),
+            };
+        }
+
+        pub fn canRead(self: Self) bool {
+            return self.internal.canRead();
+        }
+
+        pub fn canWrite(self: Self) bool {
+            return self.internal.canWrite();
+        }
+
+        pub fn reader(self: Self) Reader {
+            return Reader{ .context = self };
+        }
+
+        pub fn writer(self: Self) Writer {
+            return Writer{ .context = self };
+        }
+
+        pub const Reader = std.io.Reader(Self, ReadError, readSome);
+        pub const Writer = std.io.Writer(Self, WriteError, writeSome);
+
+        fn readSome(self: Self, buffer: []u8) ReadError!usize {
+            for (buffer) |*c| {
+                c.* = self.internal.rx();
+            }
+            return buffer.len;
+        }
+        fn writeSome(self: Self, buffer: []const u8) WriteError!usize {
+            for (buffer) |c| {
+                self.internal.tx(c);
+            }
+            return buffer.len;
+        }
+    };
+}
+
 /// A UART configuration. The config defaults to the *8N1* setting, so "8 data bits, no parity, 1 stop bit" which is the 
 /// most common serial format.
 pub const Config = struct {
@@ -11,7 +60,7 @@ pub const Config = struct {
     data_bits: DataBits = .@"8",
 };
 
-const DataBits = enum {
+pub const DataBits = enum {
     @"5",
     @"6",
     @"7",
@@ -19,35 +68,23 @@ const DataBits = enum {
     @"9",
 };
 
-const StopBits = enum { one, two };
+pub const StopBits = enum { one, two };
 
-const Parity = enum {
+pub const Parity = enum {
     none,
     even,
     odd,
     mark,
     space,
 };
+pub const InitError = error{
+    UnsupportedWordSize,
+    UnsupportedParity,
+    UnsupportedStopBitCount,
+    UnsupportedBaudRate,
+};
 
-pub fn Uart(comptime index: usize) type {
-    return struct {
-        const Self = @This();
-
-        /// Initializes the UART with the given config and returns a handle to the uart.
-        pub fn init(config: Config) Self {
-            micro.clock.ensure();
-            return Self{};
-        }
-
-        pub fn reader(self: Self) Reader {
-            return Reader{ .context = self };
-        }
-
-        pub fn writer(self: Self) Writer {
-            return Writer{ .context = self };
-        }
-
-        const ReadError = error{
+pub const ReadError = error{
     /// The input buffer received a byte while the receive fifo is already full.
     /// Devices with no fifo fill overrun as soon as a second byte arrives.
     Overrun,
@@ -59,15 +96,4 @@ pub fn Uart(comptime index: usize) type {
     /// the duration of a full byte.
     BreakInterrupt,
 };
-        const WriteError = error{};
-        pub const Reader = std.io.Reader(Self, ReadError, readSome);
-        pub const Writer = std.io.Writer(Self, WriteError, writeSome);
-
-        fn readSome(self: Self, buffer: []u8) ReadError!usize {
-            return 0;
-        }
-        fn writeSome(self: Self, buffer: []const u8) WriteError!usize {
-            return 0;
-        }
-    };
-}
+pub const WriteError = error{};

src/modules/boards/arduino-nano/arduino-nano.zig

@@ -1,5 +1,7 @@
 pub const chip = @import("chip");
 
+pub const cpu_frequency = 16_000_000;
+
 pub const pin_map = .{
     // Port A
     .D0 = "PD0",

src/modules/chips/lpc1768/lpc1768.zig

@@ -1,4 +1,5 @@
 const std = @import("std");
+const micro = @import("microzig");
 const micro_linker = @import("microzig-linker");
 
 pub const cpu = @import("cpu");
@@ -61,3 +62,91 @@ pub const gpio = struct {
         }
     }
 };
+
+pub fn Uart(comptime index: usize) type {
+    return struct {
+        const UARTn = switch (index) {
+            0 => registers.UART0,
+            1 => registers.UART1,
+            2 => registers.UART2,
+            3 => registers.UART3,
+            else => @compileError("LPC1768 has 4 UARTs available."),
+        };
+        const Self = @This();
+
+        pub fn init(config: micro.uart.Config) !Self {
+            switch (index) {
+                0 => {
+                    registers.SYSCON.PCONP.modify(.{ .PCUART0 = true });
+                    registers.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART0 = 0 });
+                },
+                1 => {
+                    registers.SYSCON.PCONP.modify(.{ .PCUART1 = true });
+                    registers.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART1 = 0 });
+                },
+                2 => {
+                    registers.SYSCON.PCONP.modify(.{ .PCUART2 = true });
+                    registers.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART2 = 0 });
+                },
+                3 => {
+                    registers.SYSCON.PCONP.modify(.{ .PCUART3 = true });
+                    registers.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART3 = 0 });
+                },
+                else => unreachable,
+            }
+
+            UARTn.LCR.write(.{
+                // 8N1
+                .WLS = switch (config.data_bits) {
+                    .@"5" => 0b00,
+                    .@"6" => 0b01,
+                    .@"7" => 0b10,
+                    .@"8" => 0b11,
+                    .@"9" => return error.UnsupportedWordSize,
+                },
+                .SBS = switch (config.stop_bits) {
+                    .one => false,
+                    .two => true,
+                },
+                .PE = (config.parity != .none),
+                .PS = switch (config.parity) {
+                    .none, .odd => @as(u2, 0b00),
+                    .even => 0b01,
+                    .mark => 0b10,
+                    .space => 0b11,
+                },
+                .BC = false,
+                .DLAB = true,
+            });
+            UARTn.FCR.modify(.{ .FIFOEN = false });
+
+            const pclk = micro.clock.get() / 4;
+            const divider = (pclk / (16 * config.baud_rate));
+
+            const regval = std.math.cast(u16, divider) catch return error.UnsupportedBaudRate;
+
+            UARTn.DLL.write(.{ .DLLSB = @truncate(u8, regval >> 0x00) });
+            UARTn.DLM.write(.{ .DLMSB = @truncate(u8, regval >> 0x08) });
+
+            UARTn.LCR.modify(.{ .DLAB = false });
+
+            return Self{};
+        }
+
+        pub fn canWrite(self: Self) bool {
+            return UARTn.LSR.read().THRE;
+        }
+        pub fn tx(self: Self, ch: u8) void {
+            while (!self.canWrite()) {} // Wait for Previous transmission
+            UARTn.THR.raw = ch; // Load the data to be transmitted
+        }
+
+        pub fn canRead(self: Self) bool {
+            return UARTn.LSR.read().RDR;
+        }
+        pub fn rx(self: Self) u8 {
+            while (!self.canRead()) {} // Wait till the data is received
+            return UARTn.RBR.read().RBR; // Read received data
+        }
+    };
+}

src/modules/chips/lpc1768/registers.zig

@@ -2618,12 +2618,12 @@ pub const RTC = extern struct {
         reserved2: u1 = 0,
         reserved1: u1 = 0,
         MINUTES: u6, // bit offset: 8 desc: Minutes value in the range of 0 to 59
-        reserved3: u1 = 0,
-        reserved2: u1 = 0,
+        reserved8: u1 = 0,
+        reserved7: u1 = 0,
         HOURS: u5, // bit offset: 16 desc: Hours value in the range of 0 to 23
-        reserved5: u1 = 0,
-        reserved4: u1 = 0,
-        reserved3: u1 = 0,
+        reserved14: u1 = 0,
+        reserved13: u1 = 0,
+        reserved12: u1 = 0,
         DOW: u3, // bit offset: 24 desc: Day of week value in the range of 0 to 6
         padding5: u1 = 0,
         padding4: u1 = 0,
@@ -2638,10 +2638,10 @@ pub const RTC = extern struct {
         reserved2: u1 = 0,
         reserved1: u1 = 0,
         MONTH: u4, // bit offset: 8 desc: Month value in the range of 1 to 12.
+        reserved8: u1 = 0,
+        reserved7: u1 = 0,
+        reserved6: u1 = 0,
         reserved5: u1 = 0,
-        reserved4: u1 = 0,
-        reserved3: u1 = 0,
-        reserved2: u1 = 0,
         YEAR: u12, // bit offset: 16 desc: Year value in the range of 0 to 4095.
         padding4: u1 = 0,
         padding3: u1 = 0,
@@ -3699,22 +3699,22 @@ pub const PINCONNECT = extern struct {
         reserved2: u1 = 0,
         reserved1: u1 = 0,
         P1_4: u2, // bit offset: 8 desc: Pin function select P1.4.
+        reserved8: u1 = 0,
         reserved7: u1 = 0,
         reserved6: u1 = 0,
         reserved5: u1 = 0,
         reserved4: u1 = 0,
         reserved3: u1 = 0,
-        reserved2: u1 = 0,
         P1_8: u2, // bit offset: 16 desc: Pin function select P1.8.
         P1_9: u2, // bit offset: 18 desc: Pin function select P1.9.
         P1_10: u2, // bit offset: 20 desc: Pin function select P1.10.
         P1_14: u2, // bit offset: 22 desc: Pin function select P1.14.
+        reserved10: u1 = 0,
+        reserved9: u1 = 0,
         reserved8: u1 = 0,
         reserved7: u1 = 0,
         reserved6: u1 = 0,
         reserved5: u1 = 0,
-        reserved4: u1 = 0,
-        reserved3: u1 = 0,
         P1_15: u2, // bit offset: 30 desc: Pin function select P1.15.
     });
     // byte offset: 12 Pin function select register 3.
@@ -3913,21 +3913,21 @@ pub const PINCONNECT = extern struct {
         reserved2: u1 = 0,
         reserved1: u1 = 0,
         P1_04MODE: u2, // bit offset: 8 desc: Port 1 pin 4 control.
+        reserved8: u1 = 0,
         reserved7: u1 = 0,
         reserved6: u1 = 0,
         reserved5: u1 = 0,
         reserved4: u1 = 0,
         reserved3: u1 = 0,
-        reserved2: u1 = 0,
         P1_08MODE: u2, // bit offset: 16 desc: Port 1 pin 8 control.
         P1_09MODE: u2, // bit offset: 18 desc: Port 1 pin 9 control.
         P1_10MODE: u2, // bit offset: 20 desc: Port 1 pin 10 control.
+        reserved10: u1 = 0,
+        reserved9: u1 = 0,
         reserved8: u1 = 0,
         reserved7: u1 = 0,
         reserved6: u1 = 0,
         reserved5: u1 = 0,
-        reserved4: u1 = 0,
-        reserved3: u1 = 0,
         P1_14MODE: u2, // bit offset: 28 desc: Port 1 pin 14 control.
         P1_15MODE: u2, // bit offset: 30 desc: Port 1 pin 15 control.
     });
@@ -4596,18 +4596,18 @@ pub const ADC = extern struct {
         reserved2: u1 = 0,
         reserved1: u1 = 0,
         RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin selected by the SEL field, as it falls within the range of VREFP to VSS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
-        reserved9: u1 = 0,
-        reserved8: u1 = 0,
-        reserved7: u1 = 0,
-        reserved6: u1 = 0,
-        reserved5: u1 = 0,
-        reserved4: u1 = 0,
-        reserved3: u1 = 0,
-        reserved2: u1 = 0,
+        reserved20: u1 = 0,
+        reserved19: u1 = 0,
+        reserved18: u1 = 0,
+        reserved17: u1 = 0,
+        reserved16: u1 = 0,
+        reserved15: u1 = 0,
+        reserved14: u1 = 0,
+        reserved13: u1 = 0,
         CHN: u3, // bit offset: 24 desc: These bits contain the channel from which the RESULT bits were converted (e.g. 000 identifies channel 0, 001 channel 1...).
-        reserved5: u1 = 0,
-        reserved4: u1 = 0,
-        reserved3: u1 = 0,
+        reserved18: u1 = 0,
+        reserved17: u1 = 0,
+        reserved16: u1 = 0,
         OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits. This bit is cleared by reading this register.
         DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started.
     });
@@ -4653,20 +4653,20 @@ pub const ADC = extern struct {
         reserved2: u1 = 0,
         reserved1: u1 = 0,
         RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
+        reserved26: u1 = 0,
+        reserved25: u1 = 0,
+        reserved24: u1 = 0,
+        reserved23: u1 = 0,
+        reserved22: u1 = 0,
+        reserved21: u1 = 0,
+        reserved20: u1 = 0,
+        reserved19: u1 = 0,
+        reserved18: u1 = 0,
+        reserved17: u1 = 0,
+        reserved16: u1 = 0,
         reserved15: u1 = 0,
         reserved14: u1 = 0,
         reserved13: u1 = 0,
-        reserved12: u1 = 0,
-        reserved11: u1 = 0,
-        reserved10: u1 = 0,
-        reserved9: u1 = 0,
-        reserved8: u1 = 0,
-        reserved7: u1 = 0,
-        reserved6: u1 = 0,
-        reserved5: u1 = 0,
-        reserved4: u1 = 0,
-        reserved3: u1 = 0,
-        reserved2: u1 = 0,
         OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register.
         DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
     });
@@ -4677,20 +4677,20 @@ pub const ADC = extern struct {
         reserved2: u1 = 0,
         reserved1: u1 = 0,
         RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
+        reserved26: u1 = 0,
+        reserved25: u1 = 0,
+        reserved24: u1 = 0,
+        reserved23: u1 = 0,
+        reserved22: u1 = 0,
+        reserved21: u1 = 0,
+        reserved20: u1 = 0,
+        reserved19: u1 = 0,
+        reserved18: u1 = 0,
+        reserved17: u1 = 0,
+        reserved16: u1 = 0,
         reserved15: u1 = 0,
         reserved14: u1 = 0,
         reserved13: u1 = 0,
-        reserved12: u1 = 0,
-        reserved11: u1 = 0,
-        reserved10: u1 = 0,
-        reserved9: u1 = 0,
-        reserved8: u1 = 0,
-        reserved7: u1 = 0,
-        reserved6: u1 = 0,
-        reserved5: u1 = 0,
-        reserved4: u1 = 0,
-        reserved3: u1 = 0,
-        reserved2: u1 = 0,
         OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register.
         DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
     });
@@ -4701,20 +4701,20 @@ pub const ADC = extern struct {
         reserved2: u1 = 0,
         reserved1: u1 = 0,
         RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
+        reserved26: u1 = 0,
+        reserved25: u1 = 0,
+        reserved24: u1 = 0,
+        reserved23: u1 = 0,
+        reserved22: u1 = 0,
+        reserved21: u1 = 0,
+        reserved20: u1 = 0,
+        reserved19: u1 = 0,
+        reserved18: u1 = 0,
+        reserved17: u1 = 0,
+        reserved16: u1 = 0,
         reserved15: u1 = 0,
         reserved14: u1 = 0,
         reserved13: u1 = 0,
-        reserved12: u1 = 0,
-        reserved11: u1 = 0,
-        reserved10: u1 = 0,
-        reserved9: u1 = 0,
-        reserved8: u1 = 0,
-        reserved7: u1 = 0,
-        reserved6: u1 = 0,
-        reserved5: u1 = 0,
-        reserved4: u1 = 0,
-        reserved3: u1 = 0,
-        reserved2: u1 = 0,
         OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register.
         DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
     });
@@ -4725,20 +4725,20 @@ pub const ADC = extern struct {
         reserved2: u1 = 0,
         reserved1: u1 = 0,
         RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
+        reserved26: u1 = 0,
+        reserved25: u1 = 0,
+        reserved24: u1 = 0,
+        reserved23: u1 = 0,
+        reserved22: u1 = 0,
+        reserved21: u1 = 0,
+        reserved20: u1 = 0,
+        reserved19: u1 = 0,
+        reserved18: u1 = 0,
+        reserved17: u1 = 0,
+        reserved16: u1 = 0,
         reserved15: u1 = 0,
         reserved14: u1 = 0,
         reserved13: u1 = 0,
-        reserved12: u1 = 0,
-        reserved11: u1 = 0,
-        reserved10: u1 = 0,
-        reserved9: u1 = 0,
-        reserved8: u1 = 0,
-        reserved7: u1 = 0,
-        reserved6: u1 = 0,
-        reserved5: u1 = 0,
-        reserved4: u1 = 0,
-        reserved3: u1 = 0,
-        reserved2: u1 = 0,
         OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register.
         DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
     });
@@ -4749,20 +4749,20 @@ pub const ADC = extern struct {
         reserved2: u1 = 0,
         reserved1: u1 = 0,
         RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
+        reserved26: u1 = 0,
+        reserved25: u1 = 0,
+        reserved24: u1 = 0,
+        reserved23: u1 = 0,
+        reserved22: u1 = 0,
+        reserved21: u1 = 0,
+        reserved20: u1 = 0,
+        reserved19: u1 = 0,
+        reserved18: u1 = 0,
+        reserved17: u1 = 0,
+        reserved16: u1 = 0,
         reserved15: u1 = 0,
         reserved14: u1 = 0,
         reserved13: u1 = 0,
-        reserved12: u1 = 0,
-        reserved11: u1 = 0,
-        reserved10: u1 = 0,
-        reserved9: u1 = 0,
-        reserved8: u1 = 0,
-        reserved7: u1 = 0,
-        reserved6: u1 = 0,
-        reserved5: u1 = 0,
-        reserved4: u1 = 0,
-        reserved3: u1 = 0,
-        reserved2: u1 = 0,
         OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register.
         DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
     });
@@ -4773,20 +4773,20 @@ pub const ADC = extern struct {
         reserved2: u1 = 0,
         reserved1: u1 = 0,
         RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
+        reserved26: u1 = 0,
+        reserved25: u1 = 0,
+        reserved24: u1 = 0,
+        reserved23: u1 = 0,
+        reserved22: u1 = 0,
+        reserved21: u1 = 0,
+        reserved20: u1 = 0,
+        reserved19: u1 = 0,
+        reserved18: u1 = 0,
+        reserved17: u1 = 0,
+        reserved16: u1 = 0,
         reserved15: u1 = 0,
         reserved14: u1 = 0,
         reserved13: u1 = 0,
-        reserved12: u1 = 0,
-        reserved11: u1 = 0,
-        reserved10: u1 = 0,
-        reserved9: u1 = 0,
-        reserved8: u1 = 0,
-        reserved7: u1 = 0,
-        reserved6: u1 = 0,
-        reserved5: u1 = 0,
-        reserved4: u1 = 0,
-        reserved3: u1 = 0,
-        reserved2: u1 = 0,
         OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register.
         DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
     });
@@ -4797,20 +4797,20 @@ pub const ADC = extern struct {
         reserved2: u1 = 0,
         reserved1: u1 = 0,
         RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
+        reserved26: u1 = 0,
+        reserved25: u1 = 0,
+        reserved24: u1 = 0,
+        reserved23: u1 = 0,
+        reserved22: u1 = 0,
+        reserved21: u1 = 0,
+        reserved20: u1 = 0,
+        reserved19: u1 = 0,
+        reserved18: u1 = 0,
+        reserved17: u1 = 0,
+        reserved16: u1 = 0,
         reserved15: u1 = 0,
         reserved14: u1 = 0,
         reserved13: u1 = 0,
-        reserved12: u1 = 0,
-        reserved11: u1 = 0,
-        reserved10: u1 = 0,
-        reserved9: u1 = 0,
-        reserved8: u1 = 0,
-        reserved7: u1 = 0,
-        reserved6: u1 = 0,
-        reserved5: u1 = 0,
-        reserved4: u1 = 0,
-        reserved3: u1 = 0,
-        reserved2: u1 = 0,
         OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register.
         DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
     });
@@ -4821,20 +4821,20 @@ pub const ADC = extern struct {
         reserved2: u1 = 0,
         reserved1: u1 = 0,
         RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
+        reserved26: u1 = 0,
+        reserved25: u1 = 0,
+        reserved24: u1 = 0,
+        reserved23: u1 = 0,
+        reserved22: u1 = 0,
+        reserved21: u1 = 0,
+        reserved20: u1 = 0,
+        reserved19: u1 = 0,
+        reserved18: u1 = 0,
+        reserved17: u1 = 0,
+        reserved16: u1 = 0,
         reserved15: u1 = 0,
         reserved14: u1 = 0,
         reserved13: u1 = 0,
-        reserved12: u1 = 0,
-        reserved11: u1 = 0,
-        reserved10: u1 = 0,
-        reserved9: u1 = 0,
-        reserved8: u1 = 0,
-        reserved7: u1 = 0,
-        reserved6: u1 = 0,
-        reserved5: u1 = 0,
-        reserved4: u1 = 0,
-        reserved3: u1 = 0,
-        reserved2: u1 = 0,
         OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register.
         DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
     });
@@ -7581,6 +7581,9 @@ pub const CAN1 = extern struct {
         reserved2: u1 = 0,
         reserved1: u1 = 0,
         DLC: u4, // bit offset: 16 desc: The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding.
+        reserved14: u1 = 0,
+        reserved13: u1 = 0,
+        reserved12: u1 = 0,
         reserved11: u1 = 0,
         reserved10: u1 = 0,
         reserved9: u1 = 0,
@@ -7588,9 +7591,6 @@ pub const CAN1 = extern struct {
         reserved7: u1 = 0,
         reserved6: u1 = 0,
         reserved5: u1 = 0,
-        reserved4: u1 = 0,
-        reserved3: u1 = 0,
-        reserved2: u1 = 0,
         RTR: bool, // bit offset: 30 desc: This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier.
         FF: bool, // bit offset: 31 desc: A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below.
     });
@@ -7645,6 +7645,9 @@ pub const CAN1 = extern struct {
         reserved2: u1 = 0,
         reserved1: u1 = 0,
         DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes
+        reserved14: u1 = 0,
+        reserved13: u1 = 0,
+        reserved12: u1 = 0,
         reserved11: u1 = 0,
         reserved10: u1 = 0,
         reserved9: u1 = 0,
@@ -7652,9 +7655,6 @@ pub const CAN1 = extern struct {
         reserved7: u1 = 0,
         reserved6: u1 = 0,
         reserved5: u1 = 0,
-        reserved4: u1 = 0,
-        reserved3: u1 = 0,
-        reserved2: u1 = 0,
         RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes.
         FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format).
     });
@@ -7688,6 +7688,9 @@ pub const CAN1 = extern struct {
         reserved2: u1 = 0,
         reserved1: u1 = 0,
         DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes
+        reserved14: u1 = 0,
+        reserved13: u1 = 0,
+        reserved12: u1 = 0,
         reserved11: u1 = 0,
         reserved10: u1 = 0,
         reserved9: u1 = 0,
@@ -7695,9 +7698,6 @@ pub const CAN1 = extern struct {
         reserved7: u1 = 0,
         reserved6: u1 = 0,
         reserved5: u1 = 0,
-        reserved4: u1 = 0,
-        reserved3: u1 = 0,
-        reserved2: u1 = 0,
         RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes.
         FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format).
     });
@@ -7731,6 +7731,9 @@ pub const CAN1 = extern struct {
         reserved2: u1 = 0,
         reserved1: u1 = 0,
         DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes
+        reserved14: u1 = 0,
+        reserved13: u1 = 0,
+        reserved12: u1 = 0,
         reserved11: u1 = 0,
         reserved10: u1 = 0,
         reserved9: u1 = 0,
@@ -7738,9 +7741,6 @@ pub const CAN1 = extern struct {
         reserved7: u1 = 0,
         reserved6: u1 = 0,
         reserved5: u1 = 0,
-        reserved4: u1 = 0,
-        reserved3: u1 = 0,
-        reserved2: u1 = 0,
         RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes.
         FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format).
     });
@@ -8007,6 +8007,9 @@ pub const CAN2 = extern struct {
         reserved2: u1 = 0,
         reserved1: u1 = 0,
         DLC: u4, // bit offset: 16 desc: The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding.
+        reserved14: u1 = 0,
+        reserved13: u1 = 0,
+        reserved12: u1 = 0,
         reserved11: u1 = 0,
         reserved10: u1 = 0,
         reserved9: u1 = 0,
@@ -8014,9 +8017,6 @@ pub const CAN2 = extern struct {
         reserved7: u1 = 0,
         reserved6: u1 = 0,
         reserved5: u1 = 0,
-        reserved4: u1 = 0,
-        reserved3: u1 = 0,
-        reserved2: u1 = 0,
         RTR: bool, // bit offset: 30 desc: This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier.
         FF: bool, // bit offset: 31 desc: A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below.
     });
@@ -8071,6 +8071,9 @@ pub const CAN2 = extern struct {
         reserved2: u1 = 0,
         reserved1: u1 = 0,
         DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes
+        reserved14: u1 = 0,
+        reserved13: u1 = 0,
+        reserved12: u1 = 0,
         reserved11: u1 = 0,
         reserved10: u1 = 0,
         reserved9: u1 = 0,
@@ -8078,9 +8081,6 @@ pub const CAN2 = extern struct {
         reserved7: u1 = 0,
         reserved6: u1 = 0,
         reserved5: u1 = 0,
-        reserved4: u1 = 0,
-        reserved3: u1 = 0,
-        reserved2: u1 = 0,
         RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes.
         FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format).
     });
@@ -8096,6 +8096,9 @@ pub const CAN2 = extern struct {
         reserved2: u1 = 0,
         reserved1: u1 = 0,
         DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes
+        reserved14: u1 = 0,
+        reserved13: u1 = 0,
+        reserved12: u1 = 0,
         reserved11: u1 = 0,
         reserved10: u1 = 0,
         reserved9: u1 = 0,
@@ -8103,9 +8106,6 @@ pub const CAN2 = extern struct {
         reserved7: u1 = 0,
         reserved6: u1 = 0,
         reserved5: u1 = 0,
-        reserved4: u1 = 0,
-        reserved3: u1 = 0,
-        reserved2: u1 = 0,
         RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes.
         FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format).
     });
@@ -8157,6 +8157,9 @@ pub const CAN2 = extern struct {
         reserved2: u1 = 0,
         reserved1: u1 = 0,
         DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes
+        reserved14: u1 = 0,
+        reserved13: u1 = 0,
+        reserved12: u1 = 0,
         reserved11: u1 = 0,
         reserved10: u1 = 0,
         reserved9: u1 = 0,
@@ -8164,9 +8167,6 @@ pub const CAN2 = extern struct {
         reserved7: u1 = 0,
         reserved6: u1 = 0,
         reserved5: u1 = 0,
-        reserved4: u1 = 0,
-        reserved3: u1 = 0,
-        reserved2: u1 = 0,
         RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes.
         FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format).
     });
@@ -8182,6 +8182,9 @@ pub const CAN2 = extern struct {
         reserved2: u1 = 0,
         reserved1: u1 = 0,
         DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes
+        reserved14: u1 = 0,
+        reserved13: u1 = 0,
+        reserved12: u1 = 0,
         reserved11: u1 = 0,
         reserved10: u1 = 0,
         reserved9: u1 = 0,
@@ -8189,9 +8192,6 @@ pub const CAN2 = extern struct {
         reserved7: u1 = 0,
         reserved6: u1 = 0,
         reserved5: u1 = 0,
-        reserved4: u1 = 0,
-        reserved3: u1 = 0,
-        reserved2: u1 = 0,
         RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes.
         FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format).
     });
@@ -8243,6 +8243,9 @@ pub const CAN2 = extern struct {
         reserved2: u1 = 0,
         reserved1: u1 = 0,
         DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes
+        reserved14: u1 = 0,
+        reserved13: u1 = 0,
+        reserved12: u1 = 0,
         reserved11: u1 = 0,
         reserved10: u1 = 0,
         reserved9: u1 = 0,
@@ -8250,9 +8253,6 @@ pub const CAN2 = extern struct {
         reserved7: u1 = 0,
         reserved6: u1 = 0,
         reserved5: u1 = 0,
-        reserved4: u1 = 0,
-        reserved3: u1 = 0,
-        reserved2: u1 = 0,
         RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes.
         FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format).
     });
@@ -8268,6 +8268,9 @@ pub const CAN2 = extern struct {
         reserved2: u1 = 0,
         reserved1: u1 = 0,
         DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes
+        reserved14: u1 = 0,
+        reserved13: u1 = 0,
+        reserved12: u1 = 0,
         reserved11: u1 = 0,
         reserved10: u1 = 0,
         reserved9: u1 = 0,
@@ -8275,9 +8278,6 @@ pub const CAN2 = extern struct {
         reserved7: u1 = 0,
         reserved6: u1 = 0,
         reserved5: u1 = 0,
-        reserved4: u1 = 0,
-        reserved3: u1 = 0,
-        reserved2: u1 = 0,
         RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes.
         FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format).
     });
@@ -11001,10 +11001,10 @@ pub const I2S = extern struct {
         reserved2: u1 = 0,
         reserved1: u1 = 0,
         RX_LEVEL: u4, // bit offset: 8 desc: Reflects the current level of the Receive FIFO.
+        reserved8: u1 = 0,
+        reserved7: u1 = 0,
+        reserved6: u1 = 0,
         reserved5: u1 = 0,
-        reserved4: u1 = 0,
-        reserved3: u1 = 0,
-        reserved2: u1 = 0,
         TX_LEVEL: u4, // bit offset: 16 desc: Reflects the current level of the Transmit FIFO.
         padding12: u1 = 0,
         padding11: u1 = 0,
@@ -11030,10 +11030,10 @@ pub const I2S = extern struct {
         reserved2: u1 = 0,
         reserved1: u1 = 0,
         RX_DEPTH_DMA1: u4, // bit offset: 8 desc: Set the FIFO level that triggers a receive DMA request on DMA1.
+        reserved8: u1 = 0,
+        reserved7: u1 = 0,
+        reserved6: u1 = 0,
         reserved5: u1 = 0,
-        reserved4: u1 = 0,
-        reserved3: u1 = 0,
-        reserved2: u1 = 0,
         TX_DEPTH_DMA1: u4, // bit offset: 16 desc: Set the FIFO level that triggers a transmit DMA request on DMA1.
         padding12: u1 = 0,
         padding11: u1 = 0,
@@ -11059,10 +11059,10 @@ pub const I2S = extern struct {
         reserved2: u1 = 0,
         reserved1: u1 = 0,
         RX_DEPTH_DMA2: u4, // bit offset: 8 desc: Set the FIFO level that triggers a receive DMA request on DMA2.
+        reserved8: u1 = 0,
+        reserved7: u1 = 0,
+        reserved6: u1 = 0,
         reserved5: u1 = 0,
-        reserved4: u1 = 0,
-        reserved3: u1 = 0,
-        reserved2: u1 = 0,
         TX_DEPTH_DMA2: u4, // bit offset: 16 desc: Set the FIFO level that triggers a transmit DMA request on DMA2.
         padding12: u1 = 0,
         padding11: u1 = 0,
@@ -11088,10 +11088,10 @@ pub const I2S = extern struct {
         reserved2: u1 = 0,
         reserved1: u1 = 0,
         RX_DEPTH_IRQ: u4, // bit offset: 8 desc: Set the FIFO level on which to create an irq request.
+        reserved8: u1 = 0,
+        reserved7: u1 = 0,
+        reserved6: u1 = 0,
         reserved5: u1 = 0,
-        reserved4: u1 = 0,
-        reserved3: u1 = 0,
-        reserved2: u1 = 0,
         TX_DEPTH_IRQ: u4, // bit offset: 16 desc: Set the FIFO level on which to create an irq request.
         padding12: u1 = 0,
         padding11: u1 = 0,
@@ -13017,8 +13017,8 @@ pub const SYSCON = extern struct {
         PCLK_PWM1: u2, // bit offset: 12 desc: Peripheral clock selection for PWM1.
         PCLK_I2C0: u2, // bit offset: 14 desc: Peripheral clock selection for I2C0.
         PCLK_SPI: u2, // bit offset: 16 desc: Peripheral clock selection for SPI.
+        reserved4: u1 = 0,
         reserved3: u1 = 0,
-        reserved2: u1 = 0,
         PCLK_SSP1: u2, // bit offset: 20 desc: Peripheral clock selection for SSP1.
         PCLK_DAC: u2, // bit offset: 22 desc: Peripheral clock selection for DAC.
         PCLK_ADC: u2, // bit offset: 24 desc: Peripheral clock selection for ADC.
@@ -13041,8 +13041,8 @@ pub const SYSCON = extern struct {
         PCLK_UART3: u2, // bit offset: 18 desc: Peripheral clock selection for UART3.
         PCLK_I2C2: u2, // bit offset: 20 desc: Peripheral clock selection for I2C2.
         PCLK_I2S: u2, // bit offset: 22 desc: Peripheral clock selection for I2S.
+        reserved4: u1 = 0,
         reserved3: u1 = 0,
-        reserved2: u1 = 0,
         PCLK_RIT: u2, // bit offset: 26 desc: Peripheral clock selection for Repetitive Interrupt Timer.
         PCLK_SYSCON: u2, // bit offset: 28 desc: Peripheral clock selection for the System Control block.
         PCLK_MC: u2, // bit offset: 30 desc: Peripheral clock selection for the Motor Control PWM.

src/tools/svd2zig.py

@@ -22,7 +22,7 @@ class MMIOFileGenerator:
     def __init__(self, f):
         self.f = f
 
-    def generate_padding(self, count, name="padding", offset=0):
+    def generate_padding(self, count, name, offset):
         while count > 0:
             self.write_line(f"{name}{offset + count}: u1 = 0,")
             count = count - 1
@@ -55,12 +55,12 @@ class MMIOFileGenerator:
         for field in sorted(register.fields, key=lambda f: f.bit_offset):
             if last_offset != field.bit_offset:
                 self.generate_padding(field.bit_offset - last_offset, "reserved", reserved_index)
-                reserved_index = reserved_index + 1
+                reserved_index = reserved_index + field.bit_width
 
             last_offset = self.generate_register_field(field)
 
         if register.size is not None:
-            self.generate_padding(register.size - last_offset)
+            self.generate_padding(register.size - last_offset, "padding", 0)
 
         self.write_line("});")
 

tests/uart-sync.zig

@@ -10,7 +10,7 @@ const uart_rxd_pin = micro.Pin("P0.16");
 pub const cpu_frequency: u32 = 10_000_000; // 10 MHz
 
 pub fn main() !void {
-    var debug_port = micro.Uart(0).init(.{
+    var debug_port = try micro.Uart(0).init(.{
         .baud_rate = 9600,
         .stop_bits = .one,
         .parity = .none, // { none, even, odd, mark, space }