Support STM32F3DISCOVERY board (#11)
* Support disabling UART test configs
* `zig build [install]` also builds .bin files
* Support one blinking LD3 on STM32F3DISCOVERY board
These changes were mostly copied from the stm32f103 already there.
But this is far from complete, many shortcuts were taken:
- Most importantly,
only a single LED on the board, and its port/pin, is supported,
viz. the 'north' LD3 on bit 9 of GPIOE.
- Setting RCC_AHBENR bit IOPEEN ("I/O port E clock enable") is done
at the same as setting the mode (input or output) on one of its pins.
No idea if that is the right place to do this.
- In cortex-m4.zig, using 'max ram' as the initial stack pointer.
The rest is completely copied from cortex-m3.zig.
- UART test is disabled.
(It seems to assume mbed-lpc1768 pin numbers.)
* Nicer initial stack pointer: exactly after RAM
* Fix build error
(How was this code working earlier?!?)
* stm32f30x: Allow all 16 pins, all GPIOx registers
* STM32F3DISCOVERY: map all LED pins
wch-ch32v003
Marnix Klooster
3 years ago
committed by
GitHub
parent
f46c2e4ea9
commit
1b5cc2ad1f
@ -0,0 +1,24 @@
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pub const chip = @import("chip");
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pub const cpu_frequency = 8_000_000;
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pub const pin_map = .{
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// circle of LEDs, connected to GPIOE bits 8..15
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// NW blue
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.@"LD4" = "PE8",
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// N red
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.@"LD3" = "PE9",
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// NE orange
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.@"LD5" = "PE10",
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// E green
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.@"LD7" = "PE11",
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// SE blue
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.@"LD9" = "PE12",
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// S red
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.@"LD10" = "PE13",
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// SW orange
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.@"LD8" = "PE14",
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// W green
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.@"LD6" = "PE15",
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};
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,55 @@
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const std = @import("std");
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const micro = @import("microzig");
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pub const cpu = @import("cpu");
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pub const registers = @import("registers.zig");
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pub fn parsePin(comptime spec: []const u8) type {
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const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme.";
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if (spec[0] != 'P')
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@compileError(invalid_format_msg);
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if (spec[1] < 'A' or spec[1] > 'H')
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@compileError(invalid_format_msg);
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const pin_number: comptime_int = std.fmt.parseInt(u4, spec[2..], 10) catch @compileError(invalid_format_msg);
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return struct {
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/// 'A'...'H'
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const gpio_port_name = spec[1..2];
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const gpio_port = @field(registers, "GPIO" ++ gpio_port_name);
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const suffix = std.fmt.comptimePrint("{d}", .{pin_number});
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};
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}
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fn setRegField(reg: anytype, comptime field_name: anytype, value: anytype) void {
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var temp = reg.read();
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@field(temp, field_name) = value;
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reg.write(temp);
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}
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pub const gpio = struct {
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pub fn setOutput(comptime pin: type) void {
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setRegField(registers.RCC.AHBENR, "IOP" ++ pin.gpio_port_name ++ "EN", 1);
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setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b01);
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}
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pub fn setInput(comptime pin: type) void {
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setRegField(registers.RCC.AHBENR, "IOP" ++ pin.gpio_port_name ++ "EN", 1);
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setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b00);
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}
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pub fn read(comptime pin: type) micro.gpio.State {
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const idr_reg = pin.gpio_port.IDR;
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const reg_value = @field(idr_reg.read(), "IDR" ++ pin.suffix); // TODO extract to getRegField()?
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return @intToEnum(micro.gpio.State, reg_value);
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}
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pub fn write(comptime pin: type, state: micro.gpio.State) void {
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_ = pin;
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switch (state) {
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.low => setRegField(pin.gpio_port.BRR, "BR" ++ pin.suffix, 1),
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.high => setRegField(pin.gpio_port.BSRR, "BS" ++ pin.suffix, 1),
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}
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}
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};
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@ -0,0 +1,103 @@
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const std = @import("std");
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pub fn sei() void {
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asm volatile ("cpsie i");
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}
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pub fn cli() void {
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asm volatile ("cpsid i");
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}
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pub fn enable_fault_irq() void {
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asm volatile ("cpsie f");
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}
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pub fn disable_fault_irq() void {
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asm volatile ("cpsid f");
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}
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pub fn nop() void {
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asm volatile ("nop");
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}
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pub fn wfi() void {
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asm volatile ("wfi");
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}
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pub fn wfe() void {
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asm volatile ("wfe");
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}
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pub fn sev() void {
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asm volatile ("sev");
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}
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pub fn isb() void {
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asm volatile ("isb");
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}
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pub fn dsb() void {
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asm volatile ("dsb");
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}
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pub fn dmb() void {
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asm volatile ("dmb");
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}
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pub fn clrex() void {
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asm volatile ("clrex");
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}
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pub const startup_logic = struct {
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const InterruptVector = fn () callconv(.C) void;
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const VectorTable = extern struct {
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initial_stack_pointer: u32,
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reset: InterruptVector,
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nmi: InterruptVector = makeUnhandledHandler("nmi"),
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hard_fault: InterruptVector = makeUnhandledHandler("hard_fault"),
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mpu_fault: InterruptVector = makeUnhandledHandler("mpu_fault"),
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bus_fault: InterruptVector = makeUnhandledHandler("bus_fault"),
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usage_fault: InterruptVector = makeUnhandledHandler("usage_fault"),
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reserved: u32 = 0,
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};
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export const vectors linksection("microzig_flash_start") = VectorTable{
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// TODO: How to compute/get the initial stack pointer?
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.initial_stack_pointer = 0x2000_A000, // HACK: hardcoded, do not keep!
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.reset = _start,
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};
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fn makeUnhandledHandler(comptime str: []const u8) fn () callconv(.C) noreturn {
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return struct {
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fn unhandledInterrupt() callconv(.C) noreturn {
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@panic("unhandled interrupt: " ++ str);
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}
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}.unhandledInterrupt;
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}
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extern fn microzig_main() noreturn;
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extern var microzig_data_start: anyopaque;
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extern var microzig_data_end: anyopaque;
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extern var microzig_bss_start: anyopaque;
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extern var microzig_bss_end: anyopaque;
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extern const microzig_data_load_start: anyopaque;
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fn _start() callconv(.C) noreturn {
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// fill .bss with zeroes
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{
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const bss_start = @ptrCast([*]u8, µzig_bss_start);
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const bss_end = @ptrCast([*]u8, µzig_bss_end);
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const bss_len = @ptrToInt(bss_end) - @ptrToInt(bss_start);
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std.mem.set(u8, bss_start[0..bss_len], 0);
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}
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// load .data from flash
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{
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const data_start = @ptrCast([*]u8, µzig_data_start);
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const data_end = @ptrCast([*]u8, µzig_data_end);
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const data_len = @ptrToInt(data_end) - @ptrToInt(data_start);
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const data_src = @ptrCast([*]const u8, µzig_data_load_start);
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std.mem.copy(u8, data_start[0..data_len], data_src[0..data_len]);
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}
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microzig_main();
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}
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};
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