Rework for MicroZig Gen 2 (#26)

Co-authored-by: Felix "xq" Queißner <git@random-projects.net>

build.zig

@@ -1,38 +1,152 @@
 const std = @import("std");
-const microzig = @import("deps/microzig/build.zig");
+const microzig = @import("root").dependencies.imports.microzig; // HACK: Please import MicroZig always under the name `microzig`. Otherwise the RP2040 module will fail to be properly imported.
-
+
-pub const boards = @import("src/boards.zig");
+fn root() []const u8 {
-pub const chips = @import("src/chips.zig");
+    return comptime (std.fs.path.dirname(@src().file) orelse ".");
-
-pub fn build(b: *std.build.Builder) void {
-    const optimize = b.standardOptimizeOption(.{});
-    inline for (@typeInfo(boards).Struct.decls) |decl| {
-        if (!decl.is_pub)
-            continue;
-
-        const exe = microzig.addEmbeddedExecutable(b, .{
-            .name = @field(boards, decl.name).name ++ ".minimal",
-            .source_file = .{
-                .path = "test/programs/minimal.zig",
-            },
-            .backing = .{ .board = @field(boards, decl.name) },
-            .optimize = optimize,
-        });
-        exe.installArtifact(b);
 }
+const build_root = root();
 
-    inline for (@typeInfo(chips).Struct.decls) |decl| {
+////////////////////////////////////////
-        if (!decl.is_pub)
+//      MicroZig Gen 2 Interface      //
-            continue;
+////////////////////////////////////////
 
-        const exe = microzig.addEmbeddedExecutable(b, .{
+pub fn build(b: *std.Build) !void {
-            .name = @field(chips, decl.name).name ++ ".minimal",
+    _ = b;
-            .source_file = .{
+    //  Dummy func to make package manager happy
-                .path = "test/programs/minimal.zig",
-            },
-            .backing = .{ .chip = @field(chips, decl.name) },
-            .optimize = optimize,
-        });
-        exe.installArtifact(b);
-    }
 }
+
+pub const chips = struct {
+    pub const stm32f103x8 = .{
+        .preferred_format = .elf,
+        .chip = .{
+            .name = "STM32F103",
+            .cpu = .cortex_m3,
+            .memory_regions = &.{
+                .{ .offset = 0x08000000, .length = 64 * 1024, .kind = .flash },
+                .{ .offset = 0x20000000, .length = 20 * 1024, .kind = .ram },
+            },
+            .register_definition = .{
+                .json = .{ .cwd_relative = build_root ++ "/src/chips/STM32F103.json" },
+            },
+        },
+    };
+
+    pub const stm32f303vc = .{
+        .preferred_format = .elf,
+        .chip = .{
+            .name = "STM32F303",
+            .cpu = .cortex_m4,
+            .memory_regions = &.{
+                .{ .offset = 0x08000000, .length = 256 * 1024, .kind = .flash },
+                .{ .offset = 0x20000000, .length = 40 * 1024, .kind = .ram },
+            },
+            .register_definition = .{
+                .json = .{ .cwd_relative = build_root ++ "/src/chips/STM32F303.json" },
+            },
+        },
+    };
+
+    pub const stm32f407vg = .{
+        .preferred_format = .elf,
+        .chip = .{
+            .name = "STM32F407",
+            .cpu = .cortex_m4,
+            .memory_regions = &.{
+                .{ .offset = 0x08000000, .length = 1024 * 1024, .kind = .flash },
+                .{ .offset = 0x20000000, .length = 128 * 1024, .kind = .ram },
+                .{ .offset = 0x10000000, .length = 64 * 1024, .kind = .ram }, // CCM RAM
+            },
+            .register_definition = .{
+                .json = .{ .cwd_relative = build_root ++ "/src/chips/STM32F407.json" },
+            },
+        },
+    };
+
+    pub const stm32f429zit6u = .{
+        .preferred_format = .elf,
+        .chip = .{
+            .name = "STM32F429",
+            .cpu = .cortex_m4,
+            .memory_regions = &.{
+                .{ .offset = 0x08000000, .length = 2048 * 1024, .kind = .flash },
+                .{ .offset = 0x20000000, .length = 192 * 1024, .kind = .ram },
+                .{ .offset = 0x10000000, .length = 64 * 1024, .kind = .ram }, // CCM RAM
+            },
+            .register_definition = .{
+                .json = .{ .cwd_relative = build_root ++ "/src/chips/STM32F429.json" },
+            },
+        },
+    };
+};
+
+pub const boards = struct {
+    pub const stm32f3discovery = .{
+        .preferred_format = .elf,
+        .chip = chips.stm32f303vc.chip,
+        .board = .{
+            .name = "STM32F3DISCOVERY",
+            .source_file = .{ .path = build_root ++ "/src/boards/STM32F3DISCOVERY.zig" },
+        },
+    };
+
+    pub const stm32f4discovery = .{
+        .preferred_format = .elf,
+        .chip = chips.stm32f407vg.chip,
+        .board = .{
+            .name = "STM32F4DISCOVERY",
+            .source_file = .{ .path = build_root ++ "/src/boards/STM32F4DISCOVERY.zig" },
+        },
+    };
+
+    pub const stm3240geval = .{
+        .preferred_format = .elf,
+        .chip = chips.stm32f407vg.chip,
+        .board = .{
+            .name = "STM3240G_EVAL",
+            .source_file = .{ .path = build_root ++ "/src/boards/STM3240G_EVAL.zig" },
+        },
+    };
+
+    pub const stm32f429idiscovery = .{
+        .preferred_format = .elf,
+        .chip = chips.stm32f429zit6u.chip,
+        .board = .{
+            .name = "STM32F429IDISCOVERY",
+            .source_file = .{ .path = build_root ++ "/src/boards/STM32F429IDISCOVERY.zig" },
+        },
+    };
+};
+
+// pub fn build(b: *std.build.Builder) void {
+//     _ = b;
+// const optimize = b.standardOptimizeOption(.{});
+// inline for (@typeInfo(boards).Struct.decls) |decl| {
+//     if (!decl.is_pub)
+//         continue;
+
+//     const exe = microzig.addEmbeddedExecutable(b, .{
+//         .name = @field(boards, decl.name).name ++ ".minimal",
+//         .source_file = .{
+//             .path = "test/programs/minimal.zig",
+//         },
+//         .backing = .{ .board = @field(boards, decl.name) },
+//         .optimize = optimize,
+//     });
+//     exe.installArtifact(b);
+// }
+
+// inline for (@typeInfo(chips).Struct.decls) |decl| {
+//     if (!decl.is_pub)
+//         continue;
+
+//     const exe = microzig.addEmbeddedExecutable(b, .{
+//         .name = @field(chips, decl.name).name ++ ".minimal",
+//         .source_file = .{
+//             .path = "test/programs/minimal.zig",
+//         },
+//         .backing = .{ .chip = @field(chips, decl.name) },
+//         .optimize = optimize,
+//     });
+//     exe.installArtifact(b);
+// }
+// }

src/boards.zig

@@ -1,35 +0,0 @@
-const std = @import("std");
-const microzig = @import("../deps/microzig/build.zig");
-const Board = microzig.Board;
-
-const chips = @import("chips.zig");
-
-fn root() []const u8 {
-    return std.fs.path.dirname(@src().file) orelse unreachable;
-}
-
-const root_path = root() ++ "/";
-
-pub const stm32f3discovery = Board{
-    .name = "STM32F3DISCOVERY",
-    .source = .{ .path = root_path ++ "boards/STM32F3DISCOVERY.zig" },
-    .chip = chips.stm32f303vc,
-};
-
-pub const stm32f4discovery = Board{
-    .name = "STM32F4DISCOVERY",
-    .source = .{ .path = root_path ++ "boards/STM32F4DISCOVERY.zig" },
-    .chip = chips.stm32f407vg,
-};
-
-pub const stm3240geval = Board{
-    .name = "STM3240G_EVAL",
-    .source = .{ .path = root_path ++ "boards/STM3240G_EVAL.zig" },
-    .chip = chips.stm32f407vg,
-};
-
-pub const stm32f429idiscovery = Board{
-    .name = "STM32F429IDISCOVERY",
-    .source = .{ .path = root_path ++ "boards/STM32F429IDISCOVERY.zig" },
-    .chip = chips.stm32f429zit6u,
-};

src/chips.zig

@@ -1,48 +0,0 @@
-const std = @import("std");
-const microzig = @import("../deps/microzig/build.zig");
-const Chip = microzig.Chip;
-const MemoryRegion = microzig.MemoryRegion;
-
-fn root_dir() []const u8 {
-    return std.fs.path.dirname(@src().file) orelse ".";
-}
-
-pub const stm32f103x8 = Chip.from_standard_paths(root_dir(), .{
-    .name = "STM32F103",
-    .cpu = microzig.cpus.cortex_m3,
-    .memory_regions = &.{
-        MemoryRegion{ .offset = 0x08000000, .length = 64 * 1024, .kind = .flash },
-        MemoryRegion{ .offset = 0x20000000, .length = 20 * 1024, .kind = .ram },
-    },
-});
-
-pub const stm32f303vc = Chip.from_standard_paths(root_dir(), .{
-    .name = "STM32F303",
-    .cpu = microzig.cpus.cortex_m4,
-    .memory_regions = &.{
-        MemoryRegion{ .offset = 0x08000000, .length = 256 * 1024, .kind = .flash },
-        MemoryRegion{ .offset = 0x20000000, .length = 40 * 1024, .kind = .ram },
-    },
-});
-
-pub const stm32f407vg = Chip.from_standard_paths(root_dir(), .{
-    .name = "STM32F407",
-    .cpu = microzig.cpus.cortex_m4,
-    .memory_regions = &.{
-        MemoryRegion{ .offset = 0x08000000, .length = 1024 * 1024, .kind = .flash },
-        MemoryRegion{ .offset = 0x20000000, .length = 128 * 1024, .kind = .ram },
-        // CCM RAM
-        MemoryRegion{ .offset = 0x10000000, .length = 64 * 1024, .kind = .ram },
-    },
-});
-
-pub const stm32f429zit6u = Chip.from_standard_paths(root_dir(), .{
-    .name = "STM32F429",
-    .cpu = microzig.cpus.cortex_m4,
-    .memory_regions = &.{
-        MemoryRegion{ .offset = 0x08000000, .length = 2048 * 1024, .kind = .flash },
-        MemoryRegion{ .offset = 0x20000000, .length = 192 * 1024, .kind = .ram },
-        // CCM RAM
-        MemoryRegion{ .offset = 0x10000000, .length = 64 * 1024, .kind = .ram },
-    },
-});