DRAM Init

src/io/mod.rs

@@ -1,4 +1,4 @@
-#[inline(always)]
+// #[inline(always)]
 pub fn write32(addr:u32, value:u32)
 {
     unsafe {        
@@ -6,7 +6,7 @@ pub fn write32(addr:u32, value:u32)
     }
 }
 
-#[inline(always)]
+// #[inline(always)]
 pub fn read32(addr:u32)->u32
 {
     let value:u32;

src/main.rs

@@ -1,6 +1,7 @@
 #![no_std]
 #![no_main]
 
+
 use core::panic::PanicInfo;
 extern crate rt;
 
@@ -48,7 +49,8 @@ fn main() -> ! {
 	let val  = (1 << 16) | (1 << 0);
 	write32(addr, val);
 	delay();
-
+    let mut dram=dram::DramPara_t::default();
+    dram.init();
     //мигаем
     loop {
         unsafe {