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CLK copy

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Трушников Николай Дмитриевич 2 years ago
parent 4575d588cb
commit 1df7de30ef
1 changed files with 36 additions and 55 deletions
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91
src/uart/mod.rs
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@ -1,6 +1,6 @@
use crate::ccu; use crate::ccu;
use crate::gpio; use crate::gpio;
use crate::io::{read32, write32};
use core::fmt; use core::fmt;
pub const UART_BASE: u32 = 0x0250_0000; pub const UART_BASE: u32 = 0x0250_0000;
@ -56,13 +56,11 @@ impl fmt::Write for UartRegT {
#[inline(always)] #[inline(always)]
fn write_str(&mut self, s: &str) -> fmt::Result { fn write_str(&mut self, s: &str) -> fmt::Result {
for c in s.chars() { for c in s.chars() {
let addr = (UART_0_BASE + 0x7c) as *mut u32; let addr = UART_0_BASE + 0x7c;
unsafe { while (read32(addr) & (0x1 << 1)) == 0 {}
while (core::ptr::read_volatile(addr) & (0x1 << 1)) == 0 {} write32(UART_0_BASE, c as u32);
core::ptr::write_volatile((UART_0_BASE) as *mut u32, c as u32); let addr = UART_0_BASE + 0x7c;
let addr = (UART_0_BASE + 0x7c) as *mut u32; while read32(addr) & (0x1 << 0) == 1 {}
while core::ptr::read_volatile(addr) & (0x1 << 0) == 1 {}
}
} }
Ok(()) Ok(())
@ -79,53 +77,36 @@ pub fn init() {
gpio::init(gpio_e, 3, gpio::PE3_Select::Uart0Rx as u8); gpio::init(gpio_e, 3, gpio::PE3_Select::Uart0Rx as u8);
/* Open the clock gate for usart */ /* Open the clock gate for usart */
let addr = (ccu::BASE + ccu::USART_BGR_REG) as *mut u32; let addr = ccu::BASE + ccu::USART_BGR_REG;
unsafe { let mut val = read32(addr);
let mut val = core::ptr::read_volatile(addr); val |= 1 << 0;
val |= 1 << 0; write32(addr, val);
core::ptr::write_volatile(addr, val); /* Deassert USART reset */
/* Deassert USART reset */ let mut val = read32(addr);
let mut val = core::ptr::read_volatile(addr); val |= 1 << (16 + 0);
val |= 1 << (16 + 0); write32(addr, val);
core::ptr::write_volatile(addr, val);
}
/* Config USART to 115200-8-1-0 */ /* Config USART to 115200-8-1-0 */
let addr = (UART_0_BASE + 0x04) as *mut u32; let addr = UART_0_BASE + 0x04;
unsafe { write32(addr, 0x0);
core::ptr::write_volatile(addr, 0x0); let addr = UART_0_BASE + 0x08;
} write32(addr, 0xf7);
let addr = (UART_0_BASE + 0x08) as *mut u32; let addr = UART_0_BASE + 0x10;
unsafe { write32(addr, 0x0);
core::ptr::write_volatile(addr, 0xf7); let addr = UART_0_BASE + 0x0c;
} let mut val = read32(addr);
let addr = (UART_0_BASE + 0x10) as *mut u32; val |= 1 << 7;
unsafe { write32(addr, val);
core::ptr::write_volatile(addr, 0x0); let addr = UART_0_BASE + 0x00;
} write32(addr, 0xd & 0xff);
let addr = (UART_0_BASE + 0x0c) as *mut u32; let addr = UART_0_BASE + 0x04;
unsafe { write32(addr, (0xd >> 8) & 0xff);
let mut val = core::ptr::read_volatile(addr); let addr = UART_0_BASE + 0x0c;
val |= 1 << 7; let mut val = read32(addr);
core::ptr::write_volatile(addr, val); val &= !(1 << 7);
} write32(addr, val);
let addr = (UART_0_BASE + 0x00) as *mut u32; val = read32(addr);
unsafe { val &= !(0x1f);
core::ptr::write_volatile(addr, 0xd & 0xff); val |= (0x3 << 0) | (0 << 2) | (0x0 << 3);
} write32(addr, val);
let addr = (UART_0_BASE + 0x04) as *mut u32;
unsafe {
core::ptr::write_volatile(addr, (0xd >> 8) & 0xff);
}
let addr = (UART_0_BASE + 0x0c) as *mut u32;
unsafe {
let mut val = core::ptr::read_volatile(addr);
val &= !(1 << 7);
core::ptr::write_volatile(addr, val);
val = core::ptr::read_volatile(addr);
val &= !(0x1f);
val |= (0x3 << 0) | (0 << 2) | (0x0 << 3);
core::ptr::write_volatile(addr, val);
}
} }

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