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Трушников Николай Дмитриевич 1 year ago
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15
.cargo/config.toml
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# [target.riscv32ec-unknown-none-elf]
# linker = "riscv-none-embed-gcc"
# rustflags = [
# "-C", "link-arg=-march=rv32e",
# "-C", "link-arg=-mabi=ilp32e",
# "-C", "link-arg=-nostartfiles",
# "-C", "link-arg=-Tlink.x",
# "-C", "link-arg=-Tmemory.x",
# ]
[build]
target = "riscv32ec-unknown-none-elf"
[unstable]
build-std = ["core","compiler_builtins"]

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.gitignore vendored
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/target
**/*.rs.bk
Cargo.lock

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.sync-exclude.lst
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target/*
target/

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.vscode/settings.json vendored
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{
"rust-analyzer.check.allTargets": false,
"rust-analyzer.cargo.target": "riscv32ec-unknown-none-elf",
}

23
Cargo.toml
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[package]
name = "ch32v003-experiments"
edition = "2021"
# license = "MIT/Apache-2.0"
version = "0.1.0"
[dependencies]
ch32v003-pac = { path = "./ch32v003-pac", features = ["rt"] }
# ch32v003-rt = { path = "./ch32v003-rt" }
riscv-rt = "0.11"
panic-halt = "0.2.0"
[patch.crates-io]
riscv-rt = { git = "https://github.com/9names/riscv-rt", branch = "rv32e" }
[profile.dev]
incremental = false
opt-level = 2
[profile.release]
incremental = false
lto = true
opt-level = "z"

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200
LICENSE-APACHE
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Apache License
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21
LICENSE-MIT
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MIT LICENSE
Copyright (c) 2022 Vitaly Domnikov <oss@vitaly.codes>
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
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3
build.bat
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cargo build --release
llvm-objcopy -O ihex target/riscv32ec-unknown-none-elf/release/ch32v003-experiments out.hex
llvm-objcopy -O binary target/riscv32ec-unknown-none-elf/release/ch32v003-experiments out.bin

9
build.rs
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fn main() {
// Tell rustc to pass linker scripts to LLD
println!("cargo:rustc-link-arg=-Tmemory.x");
println!("cargo:rustc-link-arg=-Tlink.x");
// Rerun this script only when necesary
println!("cargo:rerun-if-changed=memory.x");
println!("cargo:rerun-if-changed=build.rs");
}

4
ch32v003-pac/.gitignore vendored
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/target
**/*.rs.bk
Cargo.lock
*.svd.patched

664
ch32v003-pac/CMSIS-SVD.xsd
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<?xml version="1.0" encoding="UTF-8"?>
<!--
Copyright (c) 2013-2022 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the License); you may
not use this file except in compliance with the License.
You may obtain a copy of the License at
www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an AS IS BASIS, WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
$Date: 05. April 2022
$Revision: 1.3.8
Version 1.3.8:
- add SMC1 as enumerated value for cpuNameType.
Version 1.3.7:
- add CM55 as enumerated value for cpuNameType.
Version 1.3.6:
- add ARMV81MML as enumeration value for cpuNameType.
Version 1.3.5:
- add CM35P as enumeration value for cpuNameType.
Version 1.3.4:
- add dspPresent element to cpuType as SIMD instructions became optional for new processors.
Version 1.3.3:
- update file header to Apache 2.0 License
- add dimableIdentifierType, as a copy of previous identifierType adding "%s",
- update identifierType to only allow names without %s included.
- remove enumerationNameType.
- add headerEnumName to enumerationType and to dimArrayIndexType for peripheral arrays
overwriting hierarchically generated names
- add dimName to dimElementGroup. Only valid in <cluster> context, ignored otherwise.
Version 1.3.2:
adding dimIndexArray to peripheral-, cluster- and register-array to describe
enumeration of array indices.
Version 1.3.1:
fixed peripheral name element type to identifierType to support %s for peripheral arrays
added optional protection element to addressBlockType and added p=privileged
Version 1.3:
added dim to peripherals to describe an array of peripherals.
added nesting of clusters to support hierarchical register structures.
added protection element as part of the registerPropertiesGroup indicating
special permissions are required for accessing a register.
CPU Section extended with description of the Secure Attribution Unit.
Version 1.2:
Cortex-M7 support items have been added as optional tags for the device header file generation:
fpuDP, icachePresent, dcachePresent, itcmPresent, dtcmPresent
Version 1.1:
For backward compatibility all additional tags have been made optional.
Extensions may be mandatory for successful device header file generation
Other changes are related to some restructuring of the schema.
Note that the memory section has been removed since this would limit the
reuse of descriptions for a series of devices.
-->
<xs:schema xmlns:xs="http://www.w3.org/2001/XMLSchema" elementFormDefault="qualified" attributeFormDefault="qualified" version="1.3">
<!-- stringType requires a none empty string of a least one character length -->
<xs:simpleType name="stringType">
<xs:restriction base="xs:string">
<xs:minLength value="1"/>
</xs:restriction>
</xs:simpleType>
<xs:simpleType name="descriptionStringType">
<xs:restriction base="xs:string">
<xs:pattern value="[\p{IsBasicLatin}\p{IsLatin-1Supplement}]*" />
</xs:restriction>
</xs:simpleType>
<!-- cpuType specifies a selection of Cortex-M and Secure-Cores. This list will get extended as new processors are released -->
<xs:simpleType name="cpuNameType">
<xs:restriction base="xs:token">
<xs:enumeration value="CM0"/>
<xs:enumeration value="CM0PLUS"/>
<xs:enumeration value="CM0+"/>
<xs:enumeration value="CM1"/>
<xs:enumeration value="SC000"/>
<xs:enumeration value="CM23"/>
<xs:enumeration value="CM3"/>
<xs:enumeration value="CM33"/>
<xs:enumeration value="CM35P"/>
<xs:enumeration value="CM55"/>
<xs:enumeration value="SC300"/>
<xs:enumeration value="CM4"/>
<xs:enumeration value="CM7"/>
<xs:enumeration value="ARMV8MML"/>
<xs:enumeration value="ARMV8MBL"/>
<xs:enumeration value="ARMV81MML"/>
<xs:enumeration value="CA5"/>
<xs:enumeration value="CA7"/>
<xs:enumeration value="CA8"/>
<xs:enumeration value="CA9"/>
<xs:enumeration value="CA15"/>
<xs:enumeration value="CA17"/>
<xs:enumeration value="CA53"/>
<xs:enumeration value="CA57"/>
<xs:enumeration value="CA72"/>
<xs:enumeration value="SMC1"/>
<xs:enumeration value="other"/>
</xs:restriction>
</xs:simpleType>
<!-- revisionType specifies the CPU revision format as defined by ARM (rNpM) -->
<xs:simpleType name="revisionType">
<xs:restriction base="xs:string">
<xs:pattern value="r[0-9]*p[0-9]*"/>
</xs:restriction>
</xs:simpleType>
<!-- EndianType pre-defines the tokens for specifying the endianess of the device -->
<xs:simpleType name="endianType">
<xs:restriction base="xs:token">
<xs:enumeration value="little"/>
<xs:enumeration value="big"/>
<xs:enumeration value="selectable"/>
<xs:enumeration value="other"/>
</xs:restriction>
</xs:simpleType>
<!-- dataType pre-defines the tokens in line with CMSIS data type definitions -->
<xs:simpleType name="dataTypeType">
<xs:restriction base="xs:token">
<xs:enumeration value="uint8_t"/>
<xs:enumeration value="uint16_t"/>
<xs:enumeration value="uint32_t"/>
<xs:enumeration value="uint64_t"/>
<xs:enumeration value="int8_t"/>
<xs:enumeration value="int16_t"/>
<xs:enumeration value="int32_t"/>
<xs:enumeration value="int64_t"/>
<xs:enumeration value="uint8_t *"/>
<xs:enumeration value="uint16_t *"/>
<xs:enumeration value="uint32_t *"/>
<xs:enumeration value="uint64_t *"/>
<xs:enumeration value="int8_t *"/>
<xs:enumeration value="int16_t *"/>
<xs:enumeration value="int32_t *"/>
<xs:enumeration value="int64_t *"/>
</xs:restriction>
</xs:simpleType>
<!-- dimableIdentifierType specifies the subset and sequence of characters used for specifying identifiers that may contain %s from dim. -->
<!-- this is particularly important as these are used in ANSI C Structures during the device header file generation -->
<xs:simpleType name="dimableIdentifierType">
<xs:restriction base="xs:string">
<xs:pattern value="((%s)|(%s)[_A-Za-z]{1}[_A-Za-z0-9]*)|([_A-Za-z]{1}[_A-Za-z0-9]*(\[%s\])?)|([_A-Za-z]{1}[_A-Za-z0-9]*(%s)?[_A-Za-z0-9]*)"/>
</xs:restriction>
</xs:simpleType>
<!-- identifierType specifies the subset and sequence of characters used for specifying identifiers that must not contain %s from dim. -->
<!-- this is particularly important as these are used in ANSI C Structures during the device header file generation -->
<xs:simpleType name="identifierType">
<xs:restriction base="xs:string">
<xs:pattern value="[_A-Za-z0-9]*"/>
</xs:restriction>
</xs:simpleType>
<!-- V1.3: Protection Access Attribute Strings -->
<xs:simpleType name="protectionStringType">
<xs:restriction base="xs:string">
<!-- s = Secure -->
<!-- n = Non-secure -->
<!-- p = Privileged -->
<xs:pattern value="[snp]"/>
</xs:restriction>
</xs:simpleType>
<!-- V1.3: SAU Access Type -->
<xs:simpleType name="sauAccessType">
<xs:restriction base="xs:string">
<!-- c = non-secure Callable / Secure -->
<!-- n = Non-secure -->
<xs:pattern value="[cn]"/>
</xs:restriction>
</xs:simpleType>
<!-- dimIndexType specifies the subset and sequence of characters used for specifying the sequence of indices in register arrays -->
<xs:simpleType name="dimIndexType">
<xs:restriction base="xs:string">
<xs:pattern value="[0-9]+\-[0-9]+|[A-Z]-[A-Z]|[_0-9a-zA-Z]+(,\s*[_0-9a-zA-Z]+)+"/>
</xs:restriction>
</xs:simpleType>
<!-- scaledNonNegativeInteger specifies the format in which numbers are represented in hexadecimal or decimal format -->
<xs:simpleType name="scaledNonNegativeInteger">
<xs:restriction base="xs:string">
<xs:pattern value="[+]?(0x|0X|#)?[0-9a-fA-F]+[kmgtKMGT]?"/>
</xs:restriction>
</xs:simpleType>
<!-- enumeratedValueDataType specifies the number formats for the values in enumeratedValues -->
<xs:simpleType name="enumeratedValueDataType">
<xs:restriction base="xs:string">
<xs:pattern value="[+]?(((0x|0X)[0-9a-fA-F]+)|([0-9]+)|((#|0b)[01xX]+))"/>
</xs:restriction>
</xs:simpleType>
<!-- accessType specfies the pre-defined tokens for the available accesses -->
<xs:simpleType name="accessType">
<xs:restriction base="xs:token">
<xs:enumeration value="read-only"/>
<xs:enumeration value="write-only"/>
<xs:enumeration value="read-write"/>
<xs:enumeration value="writeOnce"/>
<xs:enumeration value="read-writeOnce"/>
</xs:restriction>
</xs:simpleType>
<!-- modifiedWriteValuesType specifies the pre-defined tokens for the write side effects -->
<xs:simpleType name="modifiedWriteValuesType">
<xs:restriction base="xs:token">
<xs:enumeration value="oneToClear"/>
<xs:enumeration value="oneToSet"/>
<xs:enumeration value="oneToToggle"/>
<xs:enumeration value="zeroToClear"/>
<xs:enumeration value="zeroToSet"/>
<xs:enumeration value="zeroToToggle"/>
<xs:enumeration value="clear"/>
<xs:enumeration value="set"/>
<xs:enumeration value="modify"/>
</xs:restriction>
</xs:simpleType>
<!-- readAction type specifies the pre-defined tokens for read side effects -->
<xs:simpleType name="readActionType">
<xs:restriction base="xs:token">
<xs:enumeration value="clear"/>
<xs:enumeration value="set"/>
<xs:enumeration value="modify"/>
<xs:enumeration value="modifyExternal"/>
</xs:restriction>
</xs:simpleType>
<!-- enumUsageType specifies the pre-defined tokens for selecting what access types an enumeratedValues set is associated with -->
<xs:simpleType name="enumUsageType">
<xs:restriction base="xs:token">
<xs:enumeration value="read"/>
<xs:enumeration value="write"/>
<xs:enumeration value="read-write"/>
</xs:restriction>
</xs:simpleType>
<!-- bitRangeType specifies the bit numbers to be restricted values from 0 - 69 -->
<xs:simpleType name="bitRangeType">
<xs:restriction base="xs:token">
<xs:pattern value="\[([0-4])?[0-9]:([0-4])?[0-9]\]"/>
</xs:restriction>
</xs:simpleType>
<!-- writeContraintType specifies how to describe the restriction of the allowed values that can be written to a resource -->
<xs:complexType name="writeConstraintType">
<xs:choice>
<xs:element name="writeAsRead" type="xs:boolean"/>
<xs:element name="useEnumeratedValues" type="xs:boolean"/>
<xs:element name="range">
<xs:complexType>
<xs:sequence>
<xs:element name="minimum" type="scaledNonNegativeInteger"/>
<xs:element name="maximum" type="scaledNonNegativeInteger"/>
</xs:sequence>
</xs:complexType>
</xs:element>
</xs:choice>
</xs:complexType>
<!-- addressBlockType specifies the elements to describe an address block -->
<xs:complexType name="addressBlockType">
<xs:sequence>
<xs:element name="offset" type="scaledNonNegativeInteger"/>
<xs:element name="size" type="scaledNonNegativeInteger"/>
<xs:element name="usage">
<xs:simpleType>
<xs:restriction base="xs:token">
<xs:enumeration value="registers"/>
<xs:enumeration value="buffer"/>
<xs:enumeration value="reserved"/>
</xs:restriction>
</xs:simpleType>
</xs:element>
<!-- Version 1.3.2: optional access protection for an address block s=secure n=non-secure p=privileged -->
<xs:element name="protection" type="protectionStringType" minOccurs="0"/>
</xs:sequence>
</xs:complexType>
<!-- interruptType specifies how to describe an interrupt associated with a peripheral -->
<xs:complexType name="interruptType">
<xs:sequence>
<xs:element name="name" type="stringType"/>
<xs:element name="description" type="xs:string" minOccurs="0"/>
<xs:element name="value" type="xs:integer"/>
</xs:sequence>
</xs:complexType>
<!-- register properties group specifies register size, access permission and reset value
this is used in multiple locations. Settings are inherited downstream. -->
<xs:group name="registerPropertiesGroup">
<xs:sequence>
<xs:element name="size" type="scaledNonNegativeInteger" minOccurs="0"/>
<xs:element name="access" type="accessType" minOccurs="0"/>
<!-- V 1.3: extended register access protection -->
<xs:element name="protection" type="protectionStringType" minOccurs="0"/>
<xs:element name="resetValue" type="scaledNonNegativeInteger" minOccurs="0"/>
<xs:element name="resetMask" type="scaledNonNegativeInteger" minOccurs="0"/>
</xs:sequence>
</xs:group>
<!-- bitRangeLsbMsbStyle specifies the bit position of a field within a register
by specifying the least significant and the most significant bit position -->
<xs:group name="bitRangeLsbMsbStyle">
<xs:sequence>
<xs:element name="lsb" type="scaledNonNegativeInteger"/>
<xs:element name="msb" type="scaledNonNegativeInteger"/>
</xs:sequence>
</xs:group>
<!-- bitRangeOffsetWidthStyle specifies the bit position of a field within a register
by specifying the least significant bit position and the bitWidth of the field -->
<xs:group name="bitRangeOffsetWidthStyle">
<xs:sequence>
<xs:element name="bitOffset" type="scaledNonNegativeInteger"/>
<xs:element name="bitWidth" type="scaledNonNegativeInteger" minOccurs="0"/>
</xs:sequence>
</xs:group>
<!-- dimElementGroup specifies the number of array elements (dim), the address offset
between to consecutive array elements and an a comma seperated list of strings
being used for identifying each element in the array -->
<xs:group name="dimElementGroup">
<xs:sequence>
<xs:element name="dim" type="scaledNonNegativeInteger"/>
<xs:element name="dimIncrement" type="scaledNonNegativeInteger"/>
<xs:element name="dimIndex" type="dimIndexType" minOccurs="0"/>
<xs:element name="dimName" type="identifierType" minOccurs="0"/>
<xs:element name="dimArrayIndex" type="dimArrayIndexType" minOccurs="0"/>
</xs:sequence>
</xs:group>
<xs:complexType name="cpuType">
<xs:sequence>
<!-- V1.1: ARM processor name: Cortex-Mx / SCxxx -->
<xs:element name="name" type="cpuNameType"/>
<!-- V1.1: ARM defined revision of the cpu -->
<xs:element name="revision" type="revisionType"/>
<!-- V1.1: Endian specifies the endianess of the processor/device -->
<xs:element name="endian" type="endianType"/>
<!-- V1.1: mpuPresent specifies whether or not a memory protection unit is physically present -->
<xs:element name="mpuPresent" type="xs:boolean" minOccurs="0"/>
<!-- V1.1: fpuPresent specifies whether or not a floating point hardware unit is physically present -->
<xs:element name="fpuPresent" type="xs:boolean" minOccurs="0"/>
<!-- V1.2: fpuDP specifies a double precision floating point hardware unit is physically present-->
<xs:element name="fpuDP" type="xs:boolean" minOccurs="0"/>
<!-- V1.3: dspPresent specifies whether the optional SIMD instructions are supported by processor -->
<xs:element name="dspPresent" type="xs:boolean" minOccurs="0"/>
<!-- V1.2: icachePresent specifies that an instruction cache is physically present-->
<xs:element name="icachePresent" type="xs:boolean" minOccurs="0"/>
<!-- V1.2: dcachePresent specifies that a data cache is physically present-->
<xs:element name="dcachePresent" type="xs:boolean" minOccurs="0"/>
<!-- V1.2: itcmPresent specifies that an instruction tightly coupled memory is physically present-->
<xs:element name="itcmPresent" type="xs:boolean" minOccurs="0"/>
<!-- V1.2: dtcmPresent specifies that an data tightly coupled memory is physically present-->
<xs:element name="dtcmPresent" type="xs:boolean" minOccurs="0"/>
<!-- V1.1: vtorPresent is used for Cortex-M0+ based devices only. It indicates whether the Vector -->
<!-- Table Offset Register is implemented in the device or not -->
<xs:element name="vtorPresent" type="xs:boolean" minOccurs="0"/>
<!-- V1.1: nvicPrioBits specifies the number of bits used by the Nested Vectored Interrupt Controller -->
<!-- for defining the priority level = # priority levels -->
<xs:element name="nvicPrioBits" type="scaledNonNegativeInteger"/>
<!-- V1.1: vendorSystickConfig is set true if a custom system timer is implemented in the device -->
<!-- instead of the ARM specified SysTickTimer -->
<xs:element name="vendorSystickConfig" type="xs:boolean"/>
<!-- V1.3: reports the total number of interrupts implemented by the device (optional) -->
<xs:element name="deviceNumInterrupts" type="scaledNonNegativeInteger" minOccurs="0"/>
<!-- V1.3: sauRegions specifies the available number of address regions -->
<!-- if not specified a value of zero is assumed -->
<xs:element name="sauNumRegions" type="scaledNonNegativeInteger" minOccurs="0"/>
<!-- V1.3: SAU Regions Configuration (if fully or partially predefined) -->
<xs:element name="sauRegionsConfig" minOccurs="0">
<xs:complexType>
<xs:sequence>
<xs:element name="region" minOccurs="0" maxOccurs="unbounded">
<!-- addressBlockType specifies the elements to describe an address block -->
<xs:complexType>
<xs:sequence minOccurs="1" maxOccurs="unbounded">
<xs:element name="base" type="scaledNonNegativeInteger"/>
<xs:element name="limit" type="scaledNonNegativeInteger"/>
<xs:element name="access" type="sauAccessType"/>
</xs:sequence>
<xs:attribute name="enabled" type="xs:boolean" use="optional" default="true"/>
<xs:attribute name="name" type="xs:string" use="optional"/>
</xs:complexType>
</xs:element>
</xs:sequence>
<xs:attribute name="enabled" type="xs:boolean" use="optional" default="true"/>
<xs:attribute name="protectionWhenDisabled" type="protectionStringType" use="optional" default="s"/>
</xs:complexType>
</xs:element>
</xs:sequence>
</xs:complexType>
<xs:complexType name="enumeratedValueType">
<xs:sequence>
<!-- name is a ANSI C indentifier representing the value (C Enumeration) -->
<xs:element name="name" type="identifierType"/>
<!-- description contains the details about the semantics/behavior specified by this value -->
<xs:element name="description" type="stringType" minOccurs="0"/>
<xs:choice>
<xs:element name="value" type="enumeratedValueDataType"/>
<!-- isDefault specifies the name and description for all values that are not
specifically described individually -->
<xs:element name="isDefault" type="xs:boolean"/>
</xs:choice>
</xs:sequence>
</xs:complexType>
<xs:complexType name="enumerationType">
<xs:sequence>
<!-- name specfies a reference to this enumeratedValues section for reuse purposes
this name does not appear in the System Viewer nor the Header File. -->
<xs:element name="name" type="identifierType" minOccurs="0"/>
<!-- overrides the hierarchical enumeration type in the device header file. User is responsible for uniqueness across description -->
<xs:element name="headerEnumName" type="identifierType" minOccurs="0"/>
<!-- usage specifies whether this enumeration is to be used for read or write or
(read and write) accesses -->
<xs:element name="usage" type="enumUsageType" minOccurs="0"/>
<!-- enumeratedValue derivedFrom=<identifierType> -->
<xs:element name="enumeratedValue" type="enumeratedValueType" minOccurs="1" maxOccurs="unbounded"/>
</xs:sequence>
<xs:attribute name="derivedFrom" type="identifierType" use="optional"/>
</xs:complexType>
<xs:complexType name="dimArrayIndexType">
<xs:sequence>
<xs:element name="headerEnumName" type="identifierType" minOccurs="0"/>
<xs:element name="enumeratedValue" type="enumeratedValueType" minOccurs="1" maxOccurs="unbounded"/>
</xs:sequence>
</xs:complexType>
<xs:complexType name="fieldType">
<xs:sequence>
<xs:group ref="dimElementGroup" minOccurs="0"/>
<!-- name specifies a field's name. The System Viewer and the device header file will
use the name of the field as identifier -->
<xs:element name="name" type="dimableIdentifierType"/>
<!-- description contains reference manual level information about the function and
options of a field -->
<xs:element name="description" type="stringType" minOccurs="0"/>
<!-- alternative specifications of the bit position of the field within the register -->
<xs:choice minOccurs="1" maxOccurs="1">
<!-- bit field described by lsb followed by msb tag -->
<xs:group ref="bitRangeLsbMsbStyle"/>
<!-- bit field described by bit offset relative to Bit0 + bit width of field -->
<xs:group ref="bitRangeOffsetWidthStyle"/>
<!-- bit field described by [<msb>:<lsb>] -->
<xs:element name="bitRange" type="bitRangeType"/>
</xs:choice>
<!-- access describes the predefined permissions for the field. -->
<xs:element name="access" type="accessType" minOccurs="0"/>
<!-- predefined description of write side effects -->
<xs:element name="modifiedWriteValues" type="modifiedWriteValuesType" minOccurs="0"/>
<!-- writeContstraint specifies the subrange of allowed values -->
<xs:element name="writeConstraint" type="writeConstraintType" minOccurs="0"/>
<!-- readAction specifies the read side effects. -->
<xs:element name="readAction" type="readActionType" minOccurs="0"/>
<!-- enumeratedValues derivedFrom=<identifierType> -->
<xs:element name="enumeratedValues" type="enumerationType" minOccurs="0" maxOccurs="2">
</xs:element>
</xs:sequence>
<xs:attribute name="derivedFrom" type="dimableIdentifierType" use="optional"/>
</xs:complexType>
<xs:complexType name="fieldsType">
<xs:sequence>
<!-- field derivedFrom=<identifierType> -->
<xs:element name="field" type="fieldType" minOccurs="1" maxOccurs="unbounded"/>
</xs:sequence>
</xs:complexType>
<xs:complexType name="registerType">
<xs:sequence>
<xs:group ref="dimElementGroup" minOccurs="0"/>
<!-- name specifies the name of the register. The register name is used by System Viewer and
device header file generator to represent a register -->
<xs:element name="name" type="dimableIdentifierType"/>
<!-- display name specifies a register name without the restritions of an ANSIS C identifier.
The use of this tag is discouraged because it does not allow consistency between
the System View and the device header file. -->
<xs:element name="displayName" type="stringType" minOccurs="0"/>
<!-- description contains a reference manual level description about the register and it's purpose -->
<xs:element name="description" type="stringType" minOccurs="0"/>
<xs:choice>
<!-- alternateGroup specifies the identifier of the subgroup a register belongs to.
This is useful if a register has a different description per mode but a single name -->
<xs:element name="alternateGroup" type="identifierType" minOccurs="0"/>
<!-- V1.1: alternateRegister specifies an alternate register description for an address that is
already fully described. In this case the register name must be unique within the peripheral -->
<xs:element name="alternateRegister" type="dimableIdentifierType" minOccurs="0"/>
</xs:choice>
<!-- addressOffset describes the address of the register relative to the baseOffset of the peripheral -->
<xs:element name="addressOffset" type="scaledNonNegativeInteger"/>
<!-- registerPropertiesGroup elements specify the default values for register size, access permission and
reset value. These default values are inherited to all fields contained in this register -->
<xs:group ref="registerPropertiesGroup" minOccurs="0"/>
<!-- V1.1: dataType specifies a CMSIS compliant native dataType for a register (i.e. signed, unsigned, pointer) -->
<xs:element name="dataType" type="dataTypeType" minOccurs="0"/>
<!-- modifiedWriteValues specifies the write side effects -->
<xs:element name="modifiedWriteValues" type="modifiedWriteValuesType" minOccurs="0"/>
<!-- writeConstraint specifies the subset of allowed write values -->
<xs:element name="writeConstraint" type="writeConstraintType" minOccurs="0"/>
<!-- readAcction specifies the read side effects -->
<xs:element name="readAction" type="readActionType" minOccurs="0"/>
<!-- fields section contains all fields that belong to this register -->
<xs:element name="fields" type="fieldsType" minOccurs="0" maxOccurs="1"/>
</xs:sequence>
<xs:attribute name="derivedFrom" type="dimableIdentifierType" use="optional"/>
</xs:complexType>
<!-- V1.1: A cluster is a set of registers that are composed into a C data structure in the device header file -->
<xs:complexType name="clusterType">
<xs:sequence>
<xs:group ref="dimElementGroup" minOccurs="0"/>
<xs:element name="name" type="dimableIdentifierType"/>
<xs:element name="description" type="xs:string"/>
<!-- V1.1: alternateCluster specifies an alternative description for a cluster address range that is
already fully described. In this case the cluster name must be unique within the peripheral -->
<xs:element name="alternateCluster" type="dimableIdentifierType" minOccurs="0"/>
<!-- V1.1: headerStructName specifies the name for the cluster structure typedef
used in the device header generation instead of the cluster name -->
<xs:element name="headerStructName" type="identifierType" minOccurs="0"/>
<xs:element name="addressOffset" type="scaledNonNegativeInteger"/>
<!-- registerPropertiesGroup elements specify the default values for register size, access permission and
reset value. These default values are inherited to all registers contained in this peripheral -->
<xs:group ref="registerPropertiesGroup" minOccurs="0"/>
<xs:sequence>
<xs:choice minOccurs="1" maxOccurs="unbounded">
<xs:element name="register" type="registerType" minOccurs="0" maxOccurs="unbounded"/>
<!-- 1.3: nesting of cluster is supported -->
<xs:element name="cluster" type="clusterType" minOccurs="0" maxOccurs="unbounded"/>
</xs:choice>
</xs:sequence>
</xs:sequence>
<xs:attribute name="derivedFrom" type="dimableIdentifierType" use="optional"/>
</xs:complexType>
<!-- the registers section can have an arbitrary list of cluster and register sections -->
<xs:complexType name="registersType">
<xs:choice minOccurs="1" maxOccurs="unbounded">
<xs:element name="cluster" type="clusterType"/>
<xs:element name="register" type="registerType"/>
</xs:choice>
</xs:complexType>
<xs:complexType name="peripheralType">
<xs:sequence>
<!-- 1.3: specify uni-dimensional array of peripheral - requires name="<name>[%s]" -->
<xs:group ref="dimElementGroup" minOccurs="0"/>
<!-- name specifies the name of a peripheral. This name is used for the System View and device header file -->
<xs:element name="name" type="dimableIdentifierType"/>
<!-- version specifies the version of the peripheral descriptions -->
<xs:element name="version" type="stringType" minOccurs="0"/>
<!-- description provides a high level functional description of the peripheral -->
<xs:element name="description" type="stringType" minOccurs="0"/>
<!-- V1.1: alternatePeripheral specifies an alternative description for an address range that is
already fully by a peripheral described. In this case the peripheral name must be unique within the device description -->
<xs:element name="alternatePeripheral" type="dimableIdentifierType" minOccurs="0"/>
<!-- groupName assigns this peripheral to a group of peripherals. This is only used bye the System View -->
<xs:element name="groupName" type="xs:Name" minOccurs="0"/>
<!-- prependToName specifies a prefix that is placed in front of each register name of this peripheral.
The device header file will show the registers in a C-Struct of the peripheral without the prefix. -->
<xs:element name="prependToName" type="identifierType" minOccurs="0"/>
<!-- appendToName is a postfix that is appended to each register name of this peripheral. The device header
file will sho the registers in a C-Struct of the peripheral without the postfix -->
<xs:element name="appendToName" type="identifierType" minOccurs="0"/>
<!-- V1.1: headerStructName specifies the name for the peripheral structure typedef
used in the device header generation instead of the peripheral name -->
<xs:element name="headerStructName" type="dimableIdentifierType" minOccurs="0"/>
<!-- disableCondition contains a logical expression based on constants and register or bit-field values
if the condition is evaluated to true, the peripheral display will be disabled -->
<xs:element name="disableCondition" type="stringType" minOccurs="0"/>
<!-- baseAddress specifies the absolute base address of a peripheral. For derived peripherals it is mandatory
to specify a baseAddress. -->
<xs:element name="baseAddress" type="scaledNonNegativeInteger"/>
<!-- registerPropertiesGroup elements specify the default values for register size, access permission and
reset value. These default values are inherited to all registers contained in this peripheral -->
<xs:group ref="registerPropertiesGroup" minOccurs="0"/>
<!-- addressBlock specifies one or more address ranges that are assigned exclusively to this peripheral.
derived peripherals may have no addressBlock, however none-derived peripherals are required to specify
at least one address block -->
<xs:element name="addressBlock" type="addressBlockType" minOccurs="0" maxOccurs="unbounded"/>
<!-- interrupt specifies can specify one or more interrtupts by name, description and value -->
<xs:element name="interrupt" type="interruptType" minOccurs="0" maxOccurs="unbounded"/>
<!-- registers section contains all registers owned by the peripheral. In case a peripheral gets derived it does
not have its own registers section, hence this section is optional. A unique peripheral without a
registers section is not allowed -->
<xs:element name="registers" type="registersType" minOccurs="0" maxOccurs="1">
</xs:element>
</xs:sequence>
<xs:attribute name="derivedFrom" type="dimableIdentifierType" use="optional"/>
</xs:complexType>
<!-- ==================================================== -->
<!-- The top level element of a description is the device -->
<!-- ==================================================== -->
<xs:element name="device" nillable="true">
<xs:complexType>
<xs:sequence>
<!-- V1.1: Vendor Name -->
<xs:element name="vendor" type="stringType" minOccurs="0"/>
<!-- V1.1: Vendor ID - a short name for referring to the vendor (e.g. Texas Instruments = TI) -->
<xs:element name="vendorID" type="identifierType" minOccurs="0"/>
<!-- name specifies the device name being described -->
<xs:element name="name" type="identifierType"/>
<!-- V1.1: series specifies the device series or family name -->
<xs:element name="series" type="stringType" minOccurs="0"/>
<!-- version specifies the version of the device description -->
<xs:element name="version" type="stringType"/>
<!-- description is a string describing the device features (e.g. memory size, peripherals, etc.) -->
<xs:element name="description" type="stringType"/>
<!-- V1.1: licenseText specifies the file header section to be included in any derived file -->
<xs:element name="licenseText" type="stringType" minOccurs="0"/>
<!-- V1.1: cpu specifies the details of the processor included in the device -->
<xs:element name="cpu" type="cpuType" minOccurs="0"/>
<!-- V1.1: the tag specifies the filename without extension of the CMSIS System Device include file.
This tag is used by the header file generator for customizing the include statement referencing the
CMSIS system file within the CMSIS device header file. By default the filename is "system_<device.name>"
In cases a device series shares a single system header file, the name of the series shall be used
instead of the individual device name. -->
<xs:element name="headerSystemFilename" type="identifierType" minOccurs="0"/>
<!-- V1.1: headerDefinitionPrefix specifies the string being prepended to all names of types defined in
generated device header file -->
<xs:element name="headerDefinitionsPrefix" type="identifierType" minOccurs="0"/>
<!-- addressUnitBits specifies the size of the minimal addressable unit in bits -->
<xs:element name="addressUnitBits" type="scaledNonNegativeInteger"/>
<!-- width specifies the number of bits for the maximum single transfer size allowed by the bus interface.
This sets the maximum size of a single register that can be defined for an address space -->
<xs:element name="width" type="scaledNonNegativeInteger"/>
<!-- registerPropertiesGroup elements specify the default values for register size, access permission and
reset value -->
<xs:group ref="registerPropertiesGroup" minOccurs="0"/>
<!-- peripherals is containing all peripherals -->
<xs:element name="peripherals">
<xs:complexType>
<xs:sequence>
<xs:element name="peripheral" type="peripheralType" minOccurs="1" maxOccurs="unbounded"/>
</xs:sequence>
</xs:complexType>
</xs:element>
<!-- Vendor Extensions: this section captures custom extensions. This section will be ignored by default -->
<xs:element name="vendorExtensions" minOccurs="0" maxOccurs="1">
<xs:complexType>
<xs:sequence>
<xs:any namespace="##any" processContents="lax" minOccurs="0" maxOccurs="unbounded">
</xs:any>
</xs:sequence>
</xs:complexType>
</xs:element>
</xs:sequence>
<xs:attribute name="schemaVersion" type="xs:decimal" use="required"/>
</xs:complexType>
</xs:element>
</xs:schema>
<!-- END OF FILE -->

24
ch32v003-pac/Cargo.toml
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[package]
name = "ch32v003-pac"
version = "0.1.0"
authors = ["Andelf <andelf@gmail.com>", "ch32-rs Contributors", "The RISC-V Team <risc-v@teams.rust-embedded.org>", "kekcheburec <hi@kekcheburec.com>"]
description = "PAC for CH32V003 device"
readme = "README.md"
keywords = ["riscv", "wch", "ch32v003", "svd2rust", "no_std", "embedded", "register", "peripheral"]
categories = ["embedded", "no-std", "hardware-support"]
license = "MIT/Apache-2.0"
edition = "2021"
[dependencies]
critical-section = { version = "1.0", optional = true }
riscv = "0.10.1"
vcell = "0.1.0"
[package.metadata.docs.rs]
features = ['rt', 'critical-section']
default-target = "riscv32i-unknown-none-elf"
targets = []
[features]
default = []
rt = []

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ch32v003-pac/README.md
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# `ch32v003-pac`
> Peripheral Access Crate for `CH32V003xx`. Made just to check the code generation, work on real hardware is not verified.
# License
Licensed under either of
- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
http://www.apache.org/licenses/LICENSE-2.0)
- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
at your option.
## Contribution
Unless you explicitly state otherwise, any contribution intentionally submitted
for inclusion in the work by you, as defined in the Apache-2.0 license, shall be
dual licensed as above, without any additional terms or conditions.

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ch32v003-pac/build.rs
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use std::env;
use std::fs::File;
use std::io::Write;
use std::path::PathBuf;
fn main() {
if env::var_os("CARGO_FEATURE_RT").is_some() {
let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
File::create(out.join("device.x"))
.unwrap()
.write_all(include_bytes!("device.x"))
.unwrap();
println!("cargo:rustc-link-search={}", out.display());
println!("cargo:rerun-if-changed=device.x");
}
println!("cargo:rerun-if-changed=build.rs");
}

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ch32v003-pac/device.x
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PROVIDE(POWER_CLOCK = DefaultHandler);
PROVIDE(RADIO = DefaultHandler);
PROVIDE(UARTE0_UART0 = DefaultHandler);
PROVIDE(TWIM0_TWIS0_TWI0 = DefaultHandler);
PROVIDE(SPIM0_SPIS0_SPI0 = DefaultHandler);
PROVIDE(GPIOTE = DefaultHandler);
PROVIDE(SAADC = DefaultHandler);
PROVIDE(TIMER0 = DefaultHandler);
PROVIDE(TIMER1 = DefaultHandler);
PROVIDE(TIMER2 = DefaultHandler);
PROVIDE(RTC0 = DefaultHandler);
PROVIDE(TEMP = DefaultHandler);
PROVIDE(RNG = DefaultHandler);
PROVIDE(ECB = DefaultHandler);
PROVIDE(CCM_AAR = DefaultHandler);
PROVIDE(WDT = DefaultHandler);
PROVIDE(RTC1 = DefaultHandler);
PROVIDE(QDEC = DefaultHandler);
PROVIDE(COMP = DefaultHandler);
PROVIDE(SWI0_EGU0 = DefaultHandler);
PROVIDE(SWI1_EGU1 = DefaultHandler);
PROVIDE(SWI2 = DefaultHandler);
PROVIDE(SWI3 = DefaultHandler);
PROVIDE(SWI4 = DefaultHandler);
PROVIDE(SWI5 = DefaultHandler);
PROVIDE(PWM0 = DefaultHandler);
PROVIDE(PDM = DefaultHandler);

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ch32v003-pac/patched-ch32v003.svd
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ch32v003-pac/src/adc1.rs
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#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - status register"]
pub statr: STATR,
#[doc = "0x04 - control register 1/TKEY_V_CTLR"]
pub ctlr1: CTLR1,
#[doc = "0x08 - control register 2"]
pub ctlr2: CTLR2,
#[doc = "0x0c - sample time register 1"]
pub samptr1_charge1: SAMPTR1_CHARGE1,
#[doc = "0x10 - sample time register 2"]
pub samptr2_charge2: SAMPTR2_CHARGE2,
#[doc = "0x14 - injected channel data offset register x"]
pub iofr1: IOFR1,
#[doc = "0x18 - injected channel data offset register x"]
pub iofr2: IOFR2,
#[doc = "0x1c - injected channel data offset register x"]
pub iofr3: IOFR3,
#[doc = "0x20 - injected channel data offset register x"]
pub iofr4: IOFR4,
#[doc = "0x24 - watchdog higher threshold register"]
pub wdhtr: WDHTR,
#[doc = "0x28 - watchdog lower threshold register"]
pub wdltr: WDLTR,
#[doc = "0x2c - regular sequence register 1"]
pub rsqr1: RSQR1,
#[doc = "0x30 - regular sequence register 2"]
pub rsqr2: RSQR2,
#[doc = "0x34 - regular sequence register 3"]
pub rsqr3: RSQR3,
#[doc = "0x38 - injected sequence register"]
pub isqr: ISQR,
#[doc = "0x3c - injected data register 1"]
pub idatar1: IDATAR1,
#[doc = "0x40 - injected data register 2"]
pub idatar2: IDATAR2,
#[doc = "0x44 - injected data register 3"]
pub idatar3: IDATAR3,
#[doc = "0x48 - injected data register 4"]
pub idatar4: IDATAR4,
#[doc = "0x4c - regular data register"]
pub rdatar: RDATAR,
#[doc = "0x50 - delay data register"]
pub dlyr: DLYR,
}
#[doc = "STATR (rw) register accessor: an alias for `Reg<STATR_SPEC>`"]
pub type STATR = crate::Reg<statr::STATR_SPEC>;
#[doc = "status register"]
pub mod statr;
#[doc = "CTLR1 (rw) register accessor: an alias for `Reg<CTLR1_SPEC>`"]
pub type CTLR1 = crate::Reg<ctlr1::CTLR1_SPEC>;
#[doc = "control register 1/TKEY_V_CTLR"]
pub mod ctlr1;
#[doc = "CTLR2 (rw) register accessor: an alias for `Reg<CTLR2_SPEC>`"]
pub type CTLR2 = crate::Reg<ctlr2::CTLR2_SPEC>;
#[doc = "control register 2"]
pub mod ctlr2;
#[doc = "SAMPTR1_CHARGE1 (rw) register accessor: an alias for `Reg<SAMPTR1_CHARGE1_SPEC>`"]
pub type SAMPTR1_CHARGE1 = crate::Reg<samptr1_charge1::SAMPTR1_CHARGE1_SPEC>;
#[doc = "sample time register 1"]
pub mod samptr1_charge1;
#[doc = "SAMPTR2_CHARGE2 (rw) register accessor: an alias for `Reg<SAMPTR2_CHARGE2_SPEC>`"]
pub type SAMPTR2_CHARGE2 = crate::Reg<samptr2_charge2::SAMPTR2_CHARGE2_SPEC>;
#[doc = "sample time register 2"]
pub mod samptr2_charge2;
#[doc = "IOFR1 (rw) register accessor: an alias for `Reg<IOFR1_SPEC>`"]
pub type IOFR1 = crate::Reg<iofr1::IOFR1_SPEC>;
#[doc = "injected channel data offset register x"]
pub mod iofr1;
#[doc = "IOFR2 (rw) register accessor: an alias for `Reg<IOFR2_SPEC>`"]
pub type IOFR2 = crate::Reg<iofr2::IOFR2_SPEC>;
#[doc = "injected channel data offset register x"]
pub mod iofr2;
#[doc = "IOFR3 (rw) register accessor: an alias for `Reg<IOFR3_SPEC>`"]
pub type IOFR3 = crate::Reg<iofr3::IOFR3_SPEC>;
#[doc = "injected channel data offset register x"]
pub mod iofr3;
#[doc = "IOFR4 (rw) register accessor: an alias for `Reg<IOFR4_SPEC>`"]
pub type IOFR4 = crate::Reg<iofr4::IOFR4_SPEC>;
#[doc = "injected channel data offset register x"]
pub mod iofr4;
#[doc = "WDHTR (rw) register accessor: an alias for `Reg<WDHTR_SPEC>`"]
pub type WDHTR = crate::Reg<wdhtr::WDHTR_SPEC>;
#[doc = "watchdog higher threshold register"]
pub mod wdhtr;
#[doc = "WDLTR (rw) register accessor: an alias for `Reg<WDLTR_SPEC>`"]
pub type WDLTR = crate::Reg<wdltr::WDLTR_SPEC>;
#[doc = "watchdog lower threshold register"]
pub mod wdltr;
#[doc = "RSQR1 (rw) register accessor: an alias for `Reg<RSQR1_SPEC>`"]
pub type RSQR1 = crate::Reg<rsqr1::RSQR1_SPEC>;
#[doc = "regular sequence register 1"]
pub mod rsqr1;
#[doc = "RSQR2 (rw) register accessor: an alias for `Reg<RSQR2_SPEC>`"]
pub type RSQR2 = crate::Reg<rsqr2::RSQR2_SPEC>;
#[doc = "regular sequence register 2"]
pub mod rsqr2;
#[doc = "RSQR3 (rw) register accessor: an alias for `Reg<RSQR3_SPEC>`"]
pub type RSQR3 = crate::Reg<rsqr3::RSQR3_SPEC>;
#[doc = "regular sequence register 3"]
pub mod rsqr3;
#[doc = "ISQR (rw) register accessor: an alias for `Reg<ISQR_SPEC>`"]
pub type ISQR = crate::Reg<isqr::ISQR_SPEC>;
#[doc = "injected sequence register"]
pub mod isqr;
#[doc = "IDATAR1 (r) register accessor: an alias for `Reg<IDATAR1_SPEC>`"]
pub type IDATAR1 = crate::Reg<idatar1::IDATAR1_SPEC>;
#[doc = "injected data register 1"]
pub mod idatar1;
#[doc = "IDATAR2 (r) register accessor: an alias for `Reg<IDATAR2_SPEC>`"]
pub type IDATAR2 = crate::Reg<idatar2::IDATAR2_SPEC>;
#[doc = "injected data register 2"]
pub mod idatar2;
#[doc = "IDATAR3 (r) register accessor: an alias for `Reg<IDATAR3_SPEC>`"]
pub type IDATAR3 = crate::Reg<idatar3::IDATAR3_SPEC>;
#[doc = "injected data register 3"]
pub mod idatar3;
#[doc = "IDATAR4 (r) register accessor: an alias for `Reg<IDATAR4_SPEC>`"]
pub type IDATAR4 = crate::Reg<idatar4::IDATAR4_SPEC>;
#[doc = "injected data register 4"]
pub mod idatar4;
#[doc = "RDATAR (r) register accessor: an alias for `Reg<RDATAR_SPEC>`"]
pub type RDATAR = crate::Reg<rdatar::RDATAR_SPEC>;
#[doc = "regular data register"]
pub mod rdatar;
#[doc = "DLYR (rw) register accessor: an alias for `Reg<DLYR_SPEC>`"]
pub type DLYR = crate::Reg<dlyr::DLYR_SPEC>;
#[doc = "delay data register"]
pub mod dlyr;

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#[doc = "Register `CTLR1` reader"]
pub struct R(crate::R<CTLR1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CTLR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CTLR1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CTLR1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CTLR1` writer"]
pub struct W(crate::W<CTLR1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CTLR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CTLR1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CTLR1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `AWDCH` reader - Analog watchdog channel select bits"]
pub type AWDCH_R = crate::FieldReader<u8, u8>;
#[doc = "Field `AWDCH` writer - Analog watchdog channel select bits"]
pub type AWDCH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTLR1_SPEC, u8, u8, 5, O>;
#[doc = "Field `EOCIE` reader - Interrupt enable for EOC"]
pub type EOCIE_R = crate::BitReader<bool>;
#[doc = "Field `EOCIE` writer - Interrupt enable for EOC"]
pub type EOCIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR1_SPEC, bool, O>;
#[doc = "Field `AWDIE` reader - Analog watchdog interrupt enable"]
pub type AWDIE_R = crate::BitReader<bool>;
#[doc = "Field `AWDIE` writer - Analog watchdog interrupt enable"]
pub type AWDIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR1_SPEC, bool, O>;
#[doc = "Field `JEOCIE` reader - Interrupt enable for injected channels"]
pub type JEOCIE_R = crate::BitReader<bool>;
#[doc = "Field `JEOCIE` writer - Interrupt enable for injected channels"]
pub type JEOCIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR1_SPEC, bool, O>;
#[doc = "Field `SCAN` reader - Scan mode enable"]
pub type SCAN_R = crate::BitReader<bool>;
#[doc = "Field `SCAN` writer - Scan mode enable"]
pub type SCAN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR1_SPEC, bool, O>;
#[doc = "Field `AWDSGL` reader - Enable the watchdog on a single channel in scan mode"]
pub type AWDSGL_R = crate::BitReader<bool>;
#[doc = "Field `AWDSGL` writer - Enable the watchdog on a single channel in scan mode"]
pub type AWDSGL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR1_SPEC, bool, O>;
#[doc = "Field `JAUTO` reader - Automatic injected group conversion"]
pub type JAUTO_R = crate::BitReader<bool>;
#[doc = "Field `JAUTO` writer - Automatic injected group conversion"]
pub type JAUTO_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR1_SPEC, bool, O>;
#[doc = "Field `DISCEN` reader - Discontinuous mode on regular channels"]
pub type DISCEN_R = crate::BitReader<bool>;
#[doc = "Field `DISCEN` writer - Discontinuous mode on regular channels"]
pub type DISCEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR1_SPEC, bool, O>;
#[doc = "Field `JDISCEN` reader - Discontinuous mode on injected channels"]
pub type JDISCEN_R = crate::BitReader<bool>;
#[doc = "Field `JDISCEN` writer - Discontinuous mode on injected channels"]
pub type JDISCEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR1_SPEC, bool, O>;
#[doc = "Field `DISCNUM` reader - Discontinuous mode channel count"]
pub type DISCNUM_R = crate::FieldReader<u8, u8>;
#[doc = "Field `DISCNUM` writer - Discontinuous mode channel count"]
pub type DISCNUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTLR1_SPEC, u8, u8, 3, O>;
#[doc = "Field `JAWDEN` reader - Analog watchdog enable on injected channels"]
pub type JAWDEN_R = crate::BitReader<bool>;
#[doc = "Field `JAWDEN` writer - Analog watchdog enable on injected channels"]
pub type JAWDEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR1_SPEC, bool, O>;
#[doc = "Field `AWDEN` reader - Analog watchdog enable on regular channels"]
pub type AWDEN_R = crate::BitReader<bool>;
#[doc = "Field `AWDEN` writer - Analog watchdog enable on regular channels"]
pub type AWDEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR1_SPEC, bool, O>;
#[doc = "Field `ADC_CAL_VOL` reader - ADC Calibration voltage selection"]
pub type ADC_CAL_VOL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `ADC_CAL_VOL` writer - ADC Calibration voltage selection"]
pub type ADC_CAL_VOL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTLR1_SPEC, u8, u8, 2, O>;
impl R {
#[doc = "Bits 0:4 - Analog watchdog channel select bits"]
#[inline(always)]
pub fn awdch(&self) -> AWDCH_R {
AWDCH_R::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 5 - Interrupt enable for EOC"]
#[inline(always)]
pub fn eocie(&self) -> EOCIE_R {
EOCIE_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Analog watchdog interrupt enable"]
#[inline(always)]
pub fn awdie(&self) -> AWDIE_R {
AWDIE_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Interrupt enable for injected channels"]
#[inline(always)]
pub fn jeocie(&self) -> JEOCIE_R {
JEOCIE_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Scan mode enable"]
#[inline(always)]
pub fn scan(&self) -> SCAN_R {
SCAN_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Enable the watchdog on a single channel in scan mode"]
#[inline(always)]
pub fn awdsgl(&self) -> AWDSGL_R {
AWDSGL_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Automatic injected group conversion"]
#[inline(always)]
pub fn jauto(&self) -> JAUTO_R {
JAUTO_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Discontinuous mode on regular channels"]
#[inline(always)]
pub fn discen(&self) -> DISCEN_R {
DISCEN_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Discontinuous mode on injected channels"]
#[inline(always)]
pub fn jdiscen(&self) -> JDISCEN_R {
JDISCEN_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bits 13:15 - Discontinuous mode channel count"]
#[inline(always)]
pub fn discnum(&self) -> DISCNUM_R {
DISCNUM_R::new(((self.bits >> 13) & 7) as u8)
}
#[doc = "Bit 22 - Analog watchdog enable on injected channels"]
#[inline(always)]
pub fn jawden(&self) -> JAWDEN_R {
JAWDEN_R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - Analog watchdog enable on regular channels"]
#[inline(always)]
pub fn awden(&self) -> AWDEN_R {
AWDEN_R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bits 25:26 - ADC Calibration voltage selection"]
#[inline(always)]
pub fn adc_cal_vol(&self) -> ADC_CAL_VOL_R {
ADC_CAL_VOL_R::new(((self.bits >> 25) & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:4 - Analog watchdog channel select bits"]
#[inline(always)]
#[must_use]
pub fn awdch(&mut self) -> AWDCH_W<0> {
AWDCH_W::new(self)
}
#[doc = "Bit 5 - Interrupt enable for EOC"]
#[inline(always)]
#[must_use]
pub fn eocie(&mut self) -> EOCIE_W<5> {
EOCIE_W::new(self)
}
#[doc = "Bit 6 - Analog watchdog interrupt enable"]
#[inline(always)]
#[must_use]
pub fn awdie(&mut self) -> AWDIE_W<6> {
AWDIE_W::new(self)
}
#[doc = "Bit 7 - Interrupt enable for injected channels"]
#[inline(always)]
#[must_use]
pub fn jeocie(&mut self) -> JEOCIE_W<7> {
JEOCIE_W::new(self)
}
#[doc = "Bit 8 - Scan mode enable"]
#[inline(always)]
#[must_use]
pub fn scan(&mut self) -> SCAN_W<8> {
SCAN_W::new(self)
}
#[doc = "Bit 9 - Enable the watchdog on a single channel in scan mode"]
#[inline(always)]
#[must_use]
pub fn awdsgl(&mut self) -> AWDSGL_W<9> {
AWDSGL_W::new(self)
}
#[doc = "Bit 10 - Automatic injected group conversion"]
#[inline(always)]
#[must_use]
pub fn jauto(&mut self) -> JAUTO_W<10> {
JAUTO_W::new(self)
}
#[doc = "Bit 11 - Discontinuous mode on regular channels"]
#[inline(always)]
#[must_use]
pub fn discen(&mut self) -> DISCEN_W<11> {
DISCEN_W::new(self)
}
#[doc = "Bit 12 - Discontinuous mode on injected channels"]
#[inline(always)]
#[must_use]
pub fn jdiscen(&mut self) -> JDISCEN_W<12> {
JDISCEN_W::new(self)
}
#[doc = "Bits 13:15 - Discontinuous mode channel count"]
#[inline(always)]
#[must_use]
pub fn discnum(&mut self) -> DISCNUM_W<13> {
DISCNUM_W::new(self)
}
#[doc = "Bit 22 - Analog watchdog enable on injected channels"]
#[inline(always)]
#[must_use]
pub fn jawden(&mut self) -> JAWDEN_W<22> {
JAWDEN_W::new(self)
}
#[doc = "Bit 23 - Analog watchdog enable on regular channels"]
#[inline(always)]
#[must_use]
pub fn awden(&mut self) -> AWDEN_W<23> {
AWDEN_W::new(self)
}
#[doc = "Bits 25:26 - ADC Calibration voltage selection"]
#[inline(always)]
#[must_use]
pub fn adc_cal_vol(&mut self) -> ADC_CAL_VOL_W<25> {
ADC_CAL_VOL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "control register 1/TKEY_V_CTLR\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctlr1](index.html) module"]
pub struct CTLR1_SPEC;
impl crate::RegisterSpec for CTLR1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ctlr1::R](R) reader structure"]
impl crate::Readable for CTLR1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ctlr1::W](W) writer structure"]
impl crate::Writable for CTLR1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CTLR1 to value 0"]
impl crate::Resettable for CTLR1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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#[doc = "Register `CTLR2` reader"]
pub struct R(crate::R<CTLR2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CTLR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CTLR2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CTLR2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CTLR2` writer"]
pub struct W(crate::W<CTLR2_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CTLR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CTLR2_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CTLR2_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `ADON` reader - A/D converter ON / OFF"]
pub type ADON_R = crate::BitReader<bool>;
#[doc = "Field `ADON` writer - A/D converter ON / OFF"]
pub type ADON_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR2_SPEC, bool, O>;
#[doc = "Field `CONT` reader - Continuous conversion"]
pub type CONT_R = crate::BitReader<bool>;
#[doc = "Field `CONT` writer - Continuous conversion"]
pub type CONT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR2_SPEC, bool, O>;
#[doc = "Field `CAL` reader - A/D calibration"]
pub type CAL_R = crate::BitReader<bool>;
#[doc = "Field `CAL` writer - A/D calibration"]
pub type CAL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR2_SPEC, bool, O>;
#[doc = "Field `RSTCAL` reader - Reset calibration"]
pub type RSTCAL_R = crate::BitReader<bool>;
#[doc = "Field `RSTCAL` writer - Reset calibration"]
pub type RSTCAL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR2_SPEC, bool, O>;
#[doc = "Field `DMA` reader - Direct memory access mode"]
pub type DMA_R = crate::BitReader<bool>;
#[doc = "Field `DMA` writer - Direct memory access mode"]
pub type DMA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR2_SPEC, bool, O>;
#[doc = "Field `ALIGN` reader - Data alignment"]
pub type ALIGN_R = crate::BitReader<bool>;
#[doc = "Field `ALIGN` writer - Data alignment"]
pub type ALIGN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR2_SPEC, bool, O>;
#[doc = "Field `JEXTSEL` reader - External event select for injected group"]
pub type JEXTSEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `JEXTSEL` writer - External event select for injected group"]
pub type JEXTSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTLR2_SPEC, u8, u8, 3, O>;
#[doc = "Field `JEXTTRIG` reader - External trigger conversion mode for injected channels"]
pub type JEXTTRIG_R = crate::BitReader<bool>;
#[doc = "Field `JEXTTRIG` writer - External trigger conversion mode for injected channels"]
pub type JEXTTRIG_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR2_SPEC, bool, O>;
#[doc = "Field `EXTSEL` reader - External event select for regular group"]
pub type EXTSEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `EXTSEL` writer - External event select for regular group"]
pub type EXTSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTLR2_SPEC, u8, u8, 3, O>;
#[doc = "Field `EXTTRIG` reader - External trigger conversion mode for regular channels"]
pub type EXTTRIG_R = crate::BitReader<bool>;
#[doc = "Field `EXTTRIG` writer - External trigger conversion mode for regular channels"]
pub type EXTTRIG_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR2_SPEC, bool, O>;
#[doc = "Field `JSWSTART` reader - Start conversion of injected channels"]
pub type JSWSTART_R = crate::BitReader<bool>;
#[doc = "Field `JSWSTART` writer - Start conversion of injected channels"]
pub type JSWSTART_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR2_SPEC, bool, O>;
#[doc = "Field `SWSTART` reader - Start conversion of regular channels"]
pub type SWSTART_R = crate::BitReader<bool>;
#[doc = "Field `SWSTART` writer - Start conversion of regular channels"]
pub type SWSTART_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR2_SPEC, bool, O>;
impl R {
#[doc = "Bit 0 - A/D converter ON / OFF"]
#[inline(always)]
pub fn adon(&self) -> ADON_R {
ADON_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Continuous conversion"]
#[inline(always)]
pub fn cont(&self) -> CONT_R {
CONT_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - A/D calibration"]
#[inline(always)]
pub fn cal(&self) -> CAL_R {
CAL_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Reset calibration"]
#[inline(always)]
pub fn rstcal(&self) -> RSTCAL_R {
RSTCAL_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 8 - Direct memory access mode"]
#[inline(always)]
pub fn dma(&self) -> DMA_R {
DMA_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 11 - Data alignment"]
#[inline(always)]
pub fn align(&self) -> ALIGN_R {
ALIGN_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:14 - External event select for injected group"]
#[inline(always)]
pub fn jextsel(&self) -> JEXTSEL_R {
JEXTSEL_R::new(((self.bits >> 12) & 7) as u8)
}
#[doc = "Bit 15 - External trigger conversion mode for injected channels"]
#[inline(always)]
pub fn jexttrig(&self) -> JEXTTRIG_R {
JEXTTRIG_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bits 17:19 - External event select for regular group"]
#[inline(always)]
pub fn extsel(&self) -> EXTSEL_R {
EXTSEL_R::new(((self.bits >> 17) & 7) as u8)
}
#[doc = "Bit 20 - External trigger conversion mode for regular channels"]
#[inline(always)]
pub fn exttrig(&self) -> EXTTRIG_R {
EXTTRIG_R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21 - Start conversion of injected channels"]
#[inline(always)]
pub fn jswstart(&self) -> JSWSTART_R {
JSWSTART_R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22 - Start conversion of regular channels"]
#[inline(always)]
pub fn swstart(&self) -> SWSTART_R {
SWSTART_R::new(((self.bits >> 22) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - A/D converter ON / OFF"]
#[inline(always)]
#[must_use]
pub fn adon(&mut self) -> ADON_W<0> {
ADON_W::new(self)
}
#[doc = "Bit 1 - Continuous conversion"]
#[inline(always)]
#[must_use]
pub fn cont(&mut self) -> CONT_W<1> {
CONT_W::new(self)
}
#[doc = "Bit 2 - A/D calibration"]
#[inline(always)]
#[must_use]
pub fn cal(&mut self) -> CAL_W<2> {
CAL_W::new(self)
}
#[doc = "Bit 3 - Reset calibration"]
#[inline(always)]
#[must_use]
pub fn rstcal(&mut self) -> RSTCAL_W<3> {
RSTCAL_W::new(self)
}
#[doc = "Bit 8 - Direct memory access mode"]
#[inline(always)]
#[must_use]
pub fn dma(&mut self) -> DMA_W<8> {
DMA_W::new(self)
}
#[doc = "Bit 11 - Data alignment"]
#[inline(always)]
#[must_use]
pub fn align(&mut self) -> ALIGN_W<11> {
ALIGN_W::new(self)
}
#[doc = "Bits 12:14 - External event select for injected group"]
#[inline(always)]
#[must_use]
pub fn jextsel(&mut self) -> JEXTSEL_W<12> {
JEXTSEL_W::new(self)
}
#[doc = "Bit 15 - External trigger conversion mode for injected channels"]
#[inline(always)]
#[must_use]
pub fn jexttrig(&mut self) -> JEXTTRIG_W<15> {
JEXTTRIG_W::new(self)
}
#[doc = "Bits 17:19 - External event select for regular group"]
#[inline(always)]
#[must_use]
pub fn extsel(&mut self) -> EXTSEL_W<17> {
EXTSEL_W::new(self)
}
#[doc = "Bit 20 - External trigger conversion mode for regular channels"]
#[inline(always)]
#[must_use]
pub fn exttrig(&mut self) -> EXTTRIG_W<20> {
EXTTRIG_W::new(self)
}
#[doc = "Bit 21 - Start conversion of injected channels"]
#[inline(always)]
#[must_use]
pub fn jswstart(&mut self) -> JSWSTART_W<21> {
JSWSTART_W::new(self)
}
#[doc = "Bit 22 - Start conversion of regular channels"]
#[inline(always)]
#[must_use]
pub fn swstart(&mut self) -> SWSTART_W<22> {
SWSTART_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "control register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctlr2](index.html) module"]
pub struct CTLR2_SPEC;
impl crate::RegisterSpec for CTLR2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ctlr2::R](R) reader structure"]
impl crate::Readable for CTLR2_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ctlr2::W](W) writer structure"]
impl crate::Writable for CTLR2_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CTLR2 to value 0"]
impl crate::Resettable for CTLR2_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

95
ch32v003-pac/src/adc1/dlyr.rs
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#[doc = "Register `DLYR` reader"]
pub struct R(crate::R<DLYR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DLYR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DLYR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DLYR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DLYR` writer"]
pub struct W(crate::W<DLYR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DLYR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DLYR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DLYR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DLYVLU` reader - External trigger data delay time configuration"]
pub type DLYVLU_R = crate::FieldReader<u16, u16>;
#[doc = "Field `DLYVLU` writer - External trigger data delay time configuration"]
pub type DLYVLU_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DLYR_SPEC, u16, u16, 9, O>;
#[doc = "Field `DLYSRC` reader - External trigger source delay selection"]
pub type DLYSRC_R = crate::BitReader<bool>;
#[doc = "Field `DLYSRC` writer - External trigger source delay selection"]
pub type DLYSRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, DLYR_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:8 - External trigger data delay time configuration"]
#[inline(always)]
pub fn dlyvlu(&self) -> DLYVLU_R {
DLYVLU_R::new((self.bits & 0x01ff) as u16)
}
#[doc = "Bit 9 - External trigger source delay selection"]
#[inline(always)]
pub fn dlysrc(&self) -> DLYSRC_R {
DLYSRC_R::new(((self.bits >> 9) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:8 - External trigger data delay time configuration"]
#[inline(always)]
#[must_use]
pub fn dlyvlu(&mut self) -> DLYVLU_W<0> {
DLYVLU_W::new(self)
}
#[doc = "Bit 9 - External trigger source delay selection"]
#[inline(always)]
#[must_use]
pub fn dlysrc(&mut self) -> DLYSRC_W<9> {
DLYSRC_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "delay data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dlyr](index.html) module"]
pub struct DLYR_SPEC;
impl crate::RegisterSpec for DLYR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dlyr::R](R) reader structure"]
impl crate::Readable for DLYR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dlyr::W](W) writer structure"]
impl crate::Writable for DLYR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DLYR to value 0"]
impl crate::Resettable for DLYR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/adc1/idatar1.rs
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#[doc = "Register `IDATAR1` reader"]
pub struct R(crate::R<IDATAR1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IDATAR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IDATAR1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IDATAR1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `IDATA` reader - Injected data"]
pub type IDATA_R = crate::FieldReader<u16, u16>;
impl R {
#[doc = "Bits 0:15 - Injected data"]
#[inline(always)]
pub fn idata(&self) -> IDATA_R {
IDATA_R::new((self.bits & 0xffff) as u16)
}
}
#[doc = "injected data register 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idatar1](index.html) module"]
pub struct IDATAR1_SPEC;
impl crate::RegisterSpec for IDATAR1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [idatar1::R](R) reader structure"]
impl crate::Readable for IDATAR1_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets IDATAR1 to value 0"]
impl crate::Resettable for IDATAR1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/adc1/idatar2.rs
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#[doc = "Register `IDATAR2` reader"]
pub struct R(crate::R<IDATAR2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IDATAR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IDATAR2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IDATAR2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `IDATA` reader - Injected data"]
pub type IDATA_R = crate::FieldReader<u16, u16>;
impl R {
#[doc = "Bits 0:15 - Injected data"]
#[inline(always)]
pub fn idata(&self) -> IDATA_R {
IDATA_R::new((self.bits & 0xffff) as u16)
}
}
#[doc = "injected data register 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idatar2](index.html) module"]
pub struct IDATAR2_SPEC;
impl crate::RegisterSpec for IDATAR2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [idatar2::R](R) reader structure"]
impl crate::Readable for IDATAR2_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets IDATAR2 to value 0"]
impl crate::Resettable for IDATAR2_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/adc1/idatar3.rs
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#[doc = "Register `IDATAR3` reader"]
pub struct R(crate::R<IDATAR3_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IDATAR3_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IDATAR3_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IDATAR3_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `IDATA` reader - Injected data"]
pub type IDATA_R = crate::FieldReader<u16, u16>;
impl R {
#[doc = "Bits 0:15 - Injected data"]
#[inline(always)]
pub fn idata(&self) -> IDATA_R {
IDATA_R::new((self.bits & 0xffff) as u16)
}
}
#[doc = "injected data register 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idatar3](index.html) module"]
pub struct IDATAR3_SPEC;
impl crate::RegisterSpec for IDATAR3_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [idatar3::R](R) reader structure"]
impl crate::Readable for IDATAR3_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets IDATAR3 to value 0"]
impl crate::Resettable for IDATAR3_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/adc1/idatar4.rs
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#[doc = "Register `IDATAR4` reader"]
pub struct R(crate::R<IDATAR4_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IDATAR4_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IDATAR4_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IDATAR4_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `IDATA` reader - Injected data"]
pub type IDATA_R = crate::FieldReader<u16, u16>;
impl R {
#[doc = "Bits 0:15 - Injected data"]
#[inline(always)]
pub fn idata(&self) -> IDATA_R {
IDATA_R::new((self.bits & 0xffff) as u16)
}
}
#[doc = "injected data register 4\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idatar4](index.html) module"]
pub struct IDATAR4_SPEC;
impl crate::RegisterSpec for IDATAR4_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [idatar4::R](R) reader structure"]
impl crate::Readable for IDATAR4_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets IDATAR4 to value 0"]
impl crate::Resettable for IDATAR4_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/adc1/iofr1.rs
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#[doc = "Register `IOFR1` reader"]
pub struct R(crate::R<IOFR1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IOFR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IOFR1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IOFR1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `IOFR1` writer"]
pub struct W(crate::W<IOFR1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<IOFR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<IOFR1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<IOFR1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `JOFFSET1` reader - Data offset for injected channel x"]
pub type JOFFSET1_R = crate::FieldReader<u16, u16>;
#[doc = "Field `JOFFSET1` writer - Data offset for injected channel x"]
pub type JOFFSET1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IOFR1_SPEC, u16, u16, 10, O>;
impl R {
#[doc = "Bits 0:9 - Data offset for injected channel x"]
#[inline(always)]
pub fn joffset1(&self) -> JOFFSET1_R {
JOFFSET1_R::new((self.bits & 0x03ff) as u16)
}
}
impl W {
#[doc = "Bits 0:9 - Data offset for injected channel x"]
#[inline(always)]
#[must_use]
pub fn joffset1(&mut self) -> JOFFSET1_W<0> {
JOFFSET1_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "injected channel data offset register x\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [iofr1](index.html) module"]
pub struct IOFR1_SPEC;
impl crate::RegisterSpec for IOFR1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [iofr1::R](R) reader structure"]
impl crate::Readable for IOFR1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [iofr1::W](W) writer structure"]
impl crate::Writable for IOFR1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets IOFR1 to value 0"]
impl crate::Resettable for IOFR1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/adc1/iofr2.rs
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#[doc = "Register `IOFR2` reader"]
pub struct R(crate::R<IOFR2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IOFR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IOFR2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IOFR2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `IOFR2` writer"]
pub struct W(crate::W<IOFR2_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<IOFR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<IOFR2_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<IOFR2_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `JOFFSET2` reader - Data offset for injected channel x"]
pub type JOFFSET2_R = crate::FieldReader<u16, u16>;
#[doc = "Field `JOFFSET2` writer - Data offset for injected channel x"]
pub type JOFFSET2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IOFR2_SPEC, u16, u16, 10, O>;
impl R {
#[doc = "Bits 0:9 - Data offset for injected channel x"]
#[inline(always)]
pub fn joffset2(&self) -> JOFFSET2_R {
JOFFSET2_R::new((self.bits & 0x03ff) as u16)
}
}
impl W {
#[doc = "Bits 0:9 - Data offset for injected channel x"]
#[inline(always)]
#[must_use]
pub fn joffset2(&mut self) -> JOFFSET2_W<0> {
JOFFSET2_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "injected channel data offset register x\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [iofr2](index.html) module"]
pub struct IOFR2_SPEC;
impl crate::RegisterSpec for IOFR2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [iofr2::R](R) reader structure"]
impl crate::Readable for IOFR2_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [iofr2::W](W) writer structure"]
impl crate::Writable for IOFR2_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets IOFR2 to value 0"]
impl crate::Resettable for IOFR2_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/adc1/iofr3.rs
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#[doc = "Register `IOFR3` reader"]
pub struct R(crate::R<IOFR3_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IOFR3_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IOFR3_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IOFR3_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `IOFR3` writer"]
pub struct W(crate::W<IOFR3_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<IOFR3_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<IOFR3_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<IOFR3_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `JOFFSET3` reader - Data offset for injected channel x"]
pub type JOFFSET3_R = crate::FieldReader<u16, u16>;
#[doc = "Field `JOFFSET3` writer - Data offset for injected channel x"]
pub type JOFFSET3_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IOFR3_SPEC, u16, u16, 10, O>;
impl R {
#[doc = "Bits 0:9 - Data offset for injected channel x"]
#[inline(always)]
pub fn joffset3(&self) -> JOFFSET3_R {
JOFFSET3_R::new((self.bits & 0x03ff) as u16)
}
}
impl W {
#[doc = "Bits 0:9 - Data offset for injected channel x"]
#[inline(always)]
#[must_use]
pub fn joffset3(&mut self) -> JOFFSET3_W<0> {
JOFFSET3_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "injected channel data offset register x\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [iofr3](index.html) module"]
pub struct IOFR3_SPEC;
impl crate::RegisterSpec for IOFR3_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [iofr3::R](R) reader structure"]
impl crate::Readable for IOFR3_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [iofr3::W](W) writer structure"]
impl crate::Writable for IOFR3_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets IOFR3 to value 0"]
impl crate::Resettable for IOFR3_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/adc1/iofr4.rs
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#[doc = "Register `IOFR4` reader"]
pub struct R(crate::R<IOFR4_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IOFR4_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IOFR4_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IOFR4_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `IOFR4` writer"]
pub struct W(crate::W<IOFR4_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<IOFR4_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<IOFR4_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<IOFR4_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `JOFFSET4` reader - Data offset for injected channel x"]
pub type JOFFSET4_R = crate::FieldReader<u16, u16>;
#[doc = "Field `JOFFSET4` writer - Data offset for injected channel x"]
pub type JOFFSET4_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IOFR4_SPEC, u16, u16, 10, O>;
impl R {
#[doc = "Bits 0:9 - Data offset for injected channel x"]
#[inline(always)]
pub fn joffset4(&self) -> JOFFSET4_R {
JOFFSET4_R::new((self.bits & 0x03ff) as u16)
}
}
impl W {
#[doc = "Bits 0:9 - Data offset for injected channel x"]
#[inline(always)]
#[must_use]
pub fn joffset4(&mut self) -> JOFFSET4_W<0> {
JOFFSET4_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "injected channel data offset register x\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [iofr4](index.html) module"]
pub struct IOFR4_SPEC;
impl crate::RegisterSpec for IOFR4_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [iofr4::R](R) reader structure"]
impl crate::Readable for IOFR4_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [iofr4::W](W) writer structure"]
impl crate::Writable for IOFR4_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets IOFR4 to value 0"]
impl crate::Resettable for IOFR4_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/adc1/isqr.rs
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#[doc = "Register `ISQR` reader"]
pub struct R(crate::R<ISQR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ISQR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ISQR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ISQR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `ISQR` writer"]
pub struct W(crate::W<ISQR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<ISQR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<ISQR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<ISQR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `JSQ1` reader - 1st conversion in injected sequence"]
pub type JSQ1_R = crate::FieldReader<u8, u8>;
#[doc = "Field `JSQ1` writer - 1st conversion in injected sequence"]
pub type JSQ1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ISQR_SPEC, u8, u8, 5, O>;
#[doc = "Field `JSQ2` reader - 2nd conversion in injected sequence"]
pub type JSQ2_R = crate::FieldReader<u8, u8>;
#[doc = "Field `JSQ2` writer - 2nd conversion in injected sequence"]
pub type JSQ2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ISQR_SPEC, u8, u8, 5, O>;
#[doc = "Field `JSQ3` reader - 3rd conversion in injected sequence"]
pub type JSQ3_R = crate::FieldReader<u8, u8>;
#[doc = "Field `JSQ3` writer - 3rd conversion in injected sequence"]
pub type JSQ3_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ISQR_SPEC, u8, u8, 5, O>;
#[doc = "Field `JSQ4` reader - 4th conversion in injected sequence"]
pub type JSQ4_R = crate::FieldReader<u8, u8>;
#[doc = "Field `JSQ4` writer - 4th conversion in injected sequence"]
pub type JSQ4_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ISQR_SPEC, u8, u8, 5, O>;
#[doc = "Field `JL` reader - Injected sequence length"]
pub type JL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `JL` writer - Injected sequence length"]
pub type JL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ISQR_SPEC, u8, u8, 2, O>;
impl R {
#[doc = "Bits 0:4 - 1st conversion in injected sequence"]
#[inline(always)]
pub fn jsq1(&self) -> JSQ1_R {
JSQ1_R::new((self.bits & 0x1f) as u8)
}
#[doc = "Bits 5:9 - 2nd conversion in injected sequence"]
#[inline(always)]
pub fn jsq2(&self) -> JSQ2_R {
JSQ2_R::new(((self.bits >> 5) & 0x1f) as u8)
}
#[doc = "Bits 10:14 - 3rd conversion in injected sequence"]
#[inline(always)]
pub fn jsq3(&self) -> JSQ3_R {
JSQ3_R::new(((self.bits >> 10) & 0x1f) as u8)
}
#[doc = "Bits 15:19 - 4th conversion in injected sequence"]
#[inline(always)]
pub fn jsq4(&self) -> JSQ4_R {
JSQ4_R::new(((self.bits >> 15) & 0x1f) as u8)
}
#[doc = "Bits 20:21 - Injected sequence length"]
#[inline(always)]
pub fn jl(&self) -> JL_R {
JL_R::new(((self.bits >> 20) & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:4 - 1st conversion in injected sequence"]
#[inline(always)]
#[must_use]
pub fn jsq1(&mut self) -> JSQ1_W<0> {
JSQ1_W::new(self)
}
#[doc = "Bits 5:9 - 2nd conversion in injected sequence"]
#[inline(always)]
#[must_use]
pub fn jsq2(&mut self) -> JSQ2_W<5> {
JSQ2_W::new(self)
}
#[doc = "Bits 10:14 - 3rd conversion in injected sequence"]
#[inline(always)]
#[must_use]
pub fn jsq3(&mut self) -> JSQ3_W<10> {
JSQ3_W::new(self)
}
#[doc = "Bits 15:19 - 4th conversion in injected sequence"]
#[inline(always)]
#[must_use]
pub fn jsq4(&mut self) -> JSQ4_W<15> {
JSQ4_W::new(self)
}
#[doc = "Bits 20:21 - Injected sequence length"]
#[inline(always)]
#[must_use]
pub fn jl(&mut self) -> JL_W<20> {
JL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "injected sequence register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [isqr](index.html) module"]
pub struct ISQR_SPEC;
impl crate::RegisterSpec for ISQR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [isqr::R](R) reader structure"]
impl crate::Readable for ISQR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [isqr::W](W) writer structure"]
impl crate::Writable for ISQR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets ISQR to value 0"]
impl crate::Resettable for ISQR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/adc1/rdatar.rs
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#[doc = "Register `RDATAR` reader"]
pub struct R(crate::R<RDATAR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<RDATAR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<RDATAR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<RDATAR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `DATA` reader - Regular data"]
pub type DATA_R = crate::FieldReader<u32, u32>;
impl R {
#[doc = "Bits 0:31 - Regular data"]
#[inline(always)]
pub fn data(&self) -> DATA_R {
DATA_R::new(self.bits)
}
}
#[doc = "regular data register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rdatar](index.html) module"]
pub struct RDATAR_SPEC;
impl crate::RegisterSpec for RDATAR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [rdatar::R](R) reader structure"]
impl crate::Readable for RDATAR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets RDATAR to value 0"]
impl crate::Resettable for RDATAR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/adc1/rsqr1.rs
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#[doc = "Register `RSQR1` reader"]
pub struct R(crate::R<RSQR1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<RSQR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<RSQR1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<RSQR1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `RSQR1` writer"]
pub struct W(crate::W<RSQR1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<RSQR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<RSQR1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<RSQR1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SQ13` reader - 13th conversion in regular sequence"]
pub type SQ13_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SQ13` writer - 13th conversion in regular sequence"]
pub type SQ13_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RSQR1_SPEC, u8, u8, 5, O>;
#[doc = "Field `SQ14` reader - 14th conversion in regular sequence"]
pub type SQ14_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SQ14` writer - 14th conversion in regular sequence"]
pub type SQ14_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RSQR1_SPEC, u8, u8, 5, O>;
#[doc = "Field `SQ15` reader - 15th conversion in regular sequence"]
pub type SQ15_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SQ15` writer - 15th conversion in regular sequence"]
pub type SQ15_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RSQR1_SPEC, u8, u8, 5, O>;
#[doc = "Field `SQ16` reader - 16th conversion in regular sequence"]
pub type SQ16_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SQ16` writer - 16th conversion in regular sequence"]
pub type SQ16_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RSQR1_SPEC, u8, u8, 5, O>;
#[doc = "Field `L` reader - Regular channel sequence length"]
pub type L_R = crate::FieldReader<u8, u8>;
#[doc = "Field `L` writer - Regular channel sequence length"]
pub type L_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RSQR1_SPEC, u8, u8, 4, O>;
impl R {
#[doc = "Bits 0:4 - 13th conversion in regular sequence"]
#[inline(always)]
pub fn sq13(&self) -> SQ13_R {
SQ13_R::new((self.bits & 0x1f) as u8)
}
#[doc = "Bits 5:9 - 14th conversion in regular sequence"]
#[inline(always)]
pub fn sq14(&self) -> SQ14_R {
SQ14_R::new(((self.bits >> 5) & 0x1f) as u8)
}
#[doc = "Bits 10:14 - 15th conversion in regular sequence"]
#[inline(always)]
pub fn sq15(&self) -> SQ15_R {
SQ15_R::new(((self.bits >> 10) & 0x1f) as u8)
}
#[doc = "Bits 15:19 - 16th conversion in regular sequence"]
#[inline(always)]
pub fn sq16(&self) -> SQ16_R {
SQ16_R::new(((self.bits >> 15) & 0x1f) as u8)
}
#[doc = "Bits 20:23 - Regular channel sequence length"]
#[inline(always)]
pub fn l(&self) -> L_R {
L_R::new(((self.bits >> 20) & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:4 - 13th conversion in regular sequence"]
#[inline(always)]
#[must_use]
pub fn sq13(&mut self) -> SQ13_W<0> {
SQ13_W::new(self)
}
#[doc = "Bits 5:9 - 14th conversion in regular sequence"]
#[inline(always)]
#[must_use]
pub fn sq14(&mut self) -> SQ14_W<5> {
SQ14_W::new(self)
}
#[doc = "Bits 10:14 - 15th conversion in regular sequence"]
#[inline(always)]
#[must_use]
pub fn sq15(&mut self) -> SQ15_W<10> {
SQ15_W::new(self)
}
#[doc = "Bits 15:19 - 16th conversion in regular sequence"]
#[inline(always)]
#[must_use]
pub fn sq16(&mut self) -> SQ16_W<15> {
SQ16_W::new(self)
}
#[doc = "Bits 20:23 - Regular channel sequence length"]
#[inline(always)]
#[must_use]
pub fn l(&mut self) -> L_W<20> {
L_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "regular sequence register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rsqr1](index.html) module"]
pub struct RSQR1_SPEC;
impl crate::RegisterSpec for RSQR1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [rsqr1::R](R) reader structure"]
impl crate::Readable for RSQR1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [rsqr1::W](W) writer structure"]
impl crate::Writable for RSQR1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets RSQR1 to value 0"]
impl crate::Resettable for RSQR1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/adc1/rsqr2.rs
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#[doc = "Register `RSQR2` reader"]
pub struct R(crate::R<RSQR2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<RSQR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<RSQR2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<RSQR2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `RSQR2` writer"]
pub struct W(crate::W<RSQR2_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<RSQR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<RSQR2_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<RSQR2_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SQ7` reader - 7th conversion in regular sequence"]
pub type SQ7_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SQ7` writer - 7th conversion in regular sequence"]
pub type SQ7_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RSQR2_SPEC, u8, u8, 5, O>;
#[doc = "Field `SQ8` reader - 8th conversion in regular sequence"]
pub type SQ8_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SQ8` writer - 8th conversion in regular sequence"]
pub type SQ8_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RSQR2_SPEC, u8, u8, 5, O>;
#[doc = "Field `SQ9` reader - 9th conversion in regular sequence"]
pub type SQ9_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SQ9` writer - 9th conversion in regular sequence"]
pub type SQ9_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RSQR2_SPEC, u8, u8, 5, O>;
#[doc = "Field `SQ10` reader - 10th conversion in regular sequence"]
pub type SQ10_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SQ10` writer - 10th conversion in regular sequence"]
pub type SQ10_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RSQR2_SPEC, u8, u8, 5, O>;
#[doc = "Field `SQ11` reader - 11th conversion in regular sequence"]
pub type SQ11_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SQ11` writer - 11th conversion in regular sequence"]
pub type SQ11_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RSQR2_SPEC, u8, u8, 5, O>;
#[doc = "Field `SQ12` reader - 12th conversion in regular sequence"]
pub type SQ12_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SQ12` writer - 12th conversion in regular sequence"]
pub type SQ12_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RSQR2_SPEC, u8, u8, 5, O>;
impl R {
#[doc = "Bits 0:4 - 7th conversion in regular sequence"]
#[inline(always)]
pub fn sq7(&self) -> SQ7_R {
SQ7_R::new((self.bits & 0x1f) as u8)
}
#[doc = "Bits 5:9 - 8th conversion in regular sequence"]
#[inline(always)]
pub fn sq8(&self) -> SQ8_R {
SQ8_R::new(((self.bits >> 5) & 0x1f) as u8)
}
#[doc = "Bits 10:14 - 9th conversion in regular sequence"]
#[inline(always)]
pub fn sq9(&self) -> SQ9_R {
SQ9_R::new(((self.bits >> 10) & 0x1f) as u8)
}
#[doc = "Bits 15:19 - 10th conversion in regular sequence"]
#[inline(always)]
pub fn sq10(&self) -> SQ10_R {
SQ10_R::new(((self.bits >> 15) & 0x1f) as u8)
}
#[doc = "Bits 20:24 - 11th conversion in regular sequence"]
#[inline(always)]
pub fn sq11(&self) -> SQ11_R {
SQ11_R::new(((self.bits >> 20) & 0x1f) as u8)
}
#[doc = "Bits 25:29 - 12th conversion in regular sequence"]
#[inline(always)]
pub fn sq12(&self) -> SQ12_R {
SQ12_R::new(((self.bits >> 25) & 0x1f) as u8)
}
}
impl W {
#[doc = "Bits 0:4 - 7th conversion in regular sequence"]
#[inline(always)]
#[must_use]
pub fn sq7(&mut self) -> SQ7_W<0> {
SQ7_W::new(self)
}
#[doc = "Bits 5:9 - 8th conversion in regular sequence"]
#[inline(always)]
#[must_use]
pub fn sq8(&mut self) -> SQ8_W<5> {
SQ8_W::new(self)
}
#[doc = "Bits 10:14 - 9th conversion in regular sequence"]
#[inline(always)]
#[must_use]
pub fn sq9(&mut self) -> SQ9_W<10> {
SQ9_W::new(self)
}
#[doc = "Bits 15:19 - 10th conversion in regular sequence"]
#[inline(always)]
#[must_use]
pub fn sq10(&mut self) -> SQ10_W<15> {
SQ10_W::new(self)
}
#[doc = "Bits 20:24 - 11th conversion in regular sequence"]
#[inline(always)]
#[must_use]
pub fn sq11(&mut self) -> SQ11_W<20> {
SQ11_W::new(self)
}
#[doc = "Bits 25:29 - 12th conversion in regular sequence"]
#[inline(always)]
#[must_use]
pub fn sq12(&mut self) -> SQ12_W<25> {
SQ12_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "regular sequence register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rsqr2](index.html) module"]
pub struct RSQR2_SPEC;
impl crate::RegisterSpec for RSQR2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [rsqr2::R](R) reader structure"]
impl crate::Readable for RSQR2_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [rsqr2::W](W) writer structure"]
impl crate::Writable for RSQR2_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets RSQR2 to value 0"]
impl crate::Resettable for RSQR2_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/adc1/rsqr3.rs
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#[doc = "Register `RSQR3` reader"]
pub struct R(crate::R<RSQR3_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<RSQR3_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<RSQR3_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<RSQR3_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `RSQR3` writer"]
pub struct W(crate::W<RSQR3_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<RSQR3_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<RSQR3_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<RSQR3_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SQ1` reader - 1st conversion in regular sequence"]
pub type SQ1_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SQ1` writer - 1st conversion in regular sequence"]
pub type SQ1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RSQR3_SPEC, u8, u8, 5, O>;
#[doc = "Field `SQ2` reader - 2nd conversion in regular sequence"]
pub type SQ2_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SQ2` writer - 2nd conversion in regular sequence"]
pub type SQ2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RSQR3_SPEC, u8, u8, 5, O>;
#[doc = "Field `SQ3` reader - 3rd conversion in regular sequence"]
pub type SQ3_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SQ3` writer - 3rd conversion in regular sequence"]
pub type SQ3_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RSQR3_SPEC, u8, u8, 5, O>;
#[doc = "Field `SQ4` reader - 4th conversion in regular sequence"]
pub type SQ4_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SQ4` writer - 4th conversion in regular sequence"]
pub type SQ4_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RSQR3_SPEC, u8, u8, 5, O>;
#[doc = "Field `SQ5` reader - 5th conversion in regular sequence"]
pub type SQ5_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SQ5` writer - 5th conversion in regular sequence"]
pub type SQ5_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RSQR3_SPEC, u8, u8, 5, O>;
#[doc = "Field `SQ6` reader - 6th conversion in regular sequence"]
pub type SQ6_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SQ6` writer - 6th conversion in regular sequence"]
pub type SQ6_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RSQR3_SPEC, u8, u8, 5, O>;
impl R {
#[doc = "Bits 0:4 - 1st conversion in regular sequence"]
#[inline(always)]
pub fn sq1(&self) -> SQ1_R {
SQ1_R::new((self.bits & 0x1f) as u8)
}
#[doc = "Bits 5:9 - 2nd conversion in regular sequence"]
#[inline(always)]
pub fn sq2(&self) -> SQ2_R {
SQ2_R::new(((self.bits >> 5) & 0x1f) as u8)
}
#[doc = "Bits 10:14 - 3rd conversion in regular sequence"]
#[inline(always)]
pub fn sq3(&self) -> SQ3_R {
SQ3_R::new(((self.bits >> 10) & 0x1f) as u8)
}
#[doc = "Bits 15:19 - 4th conversion in regular sequence"]
#[inline(always)]
pub fn sq4(&self) -> SQ4_R {
SQ4_R::new(((self.bits >> 15) & 0x1f) as u8)
}
#[doc = "Bits 20:24 - 5th conversion in regular sequence"]
#[inline(always)]
pub fn sq5(&self) -> SQ5_R {
SQ5_R::new(((self.bits >> 20) & 0x1f) as u8)
}
#[doc = "Bits 25:29 - 6th conversion in regular sequence"]
#[inline(always)]
pub fn sq6(&self) -> SQ6_R {
SQ6_R::new(((self.bits >> 25) & 0x1f) as u8)
}
}
impl W {
#[doc = "Bits 0:4 - 1st conversion in regular sequence"]
#[inline(always)]
#[must_use]
pub fn sq1(&mut self) -> SQ1_W<0> {
SQ1_W::new(self)
}
#[doc = "Bits 5:9 - 2nd conversion in regular sequence"]
#[inline(always)]
#[must_use]
pub fn sq2(&mut self) -> SQ2_W<5> {
SQ2_W::new(self)
}
#[doc = "Bits 10:14 - 3rd conversion in regular sequence"]
#[inline(always)]
#[must_use]
pub fn sq3(&mut self) -> SQ3_W<10> {
SQ3_W::new(self)
}
#[doc = "Bits 15:19 - 4th conversion in regular sequence"]
#[inline(always)]
#[must_use]
pub fn sq4(&mut self) -> SQ4_W<15> {
SQ4_W::new(self)
}
#[doc = "Bits 20:24 - 5th conversion in regular sequence"]
#[inline(always)]
#[must_use]
pub fn sq5(&mut self) -> SQ5_W<20> {
SQ5_W::new(self)
}
#[doc = "Bits 25:29 - 6th conversion in regular sequence"]
#[inline(always)]
#[must_use]
pub fn sq6(&mut self) -> SQ6_W<25> {
SQ6_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "regular sequence register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rsqr3](index.html) module"]
pub struct RSQR3_SPEC;
impl crate::RegisterSpec for RSQR3_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [rsqr3::R](R) reader structure"]
impl crate::Readable for RSQR3_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [rsqr3::W](W) writer structure"]
impl crate::Writable for RSQR3_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets RSQR3 to value 0"]
impl crate::Resettable for RSQR3_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

161
ch32v003-pac/src/adc1/samptr1_charge1.rs
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#[doc = "Register `SAMPTR1_CHARGE1` reader"]
pub struct R(crate::R<SAMPTR1_CHARGE1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SAMPTR1_CHARGE1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SAMPTR1_CHARGE1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SAMPTR1_CHARGE1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SAMPTR1_CHARGE1` writer"]
pub struct W(crate::W<SAMPTR1_CHARGE1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SAMPTR1_CHARGE1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SAMPTR1_CHARGE1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SAMPTR1_CHARGE1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SMP10_TKCG10` reader - Channel 10 sample time selection"]
pub type SMP10_TKCG10_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SMP10_TKCG10` writer - Channel 10 sample time selection"]
pub type SMP10_TKCG10_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SAMPTR1_CHARGE1_SPEC, u8, u8, 3, O>;
#[doc = "Field `SMP11_TKCG11` reader - Channel 11 sample time selection"]
pub type SMP11_TKCG11_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SMP11_TKCG11` writer - Channel 11 sample time selection"]
pub type SMP11_TKCG11_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SAMPTR1_CHARGE1_SPEC, u8, u8, 3, O>;
#[doc = "Field `SMP12_TKCG12` reader - Channel 12 sample time selection"]
pub type SMP12_TKCG12_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SMP12_TKCG12` writer - Channel 12 sample time selection"]
pub type SMP12_TKCG12_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SAMPTR1_CHARGE1_SPEC, u8, u8, 3, O>;
#[doc = "Field `SMP13_TKCG13` reader - Channel 13 sample time selection"]
pub type SMP13_TKCG13_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SMP13_TKCG13` writer - Channel 13 sample time selection"]
pub type SMP13_TKCG13_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SAMPTR1_CHARGE1_SPEC, u8, u8, 3, O>;
#[doc = "Field `SMP14_TKCG14` reader - Channel 14 sample time selection"]
pub type SMP14_TKCG14_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SMP14_TKCG14` writer - Channel 14 sample time selection"]
pub type SMP14_TKCG14_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SAMPTR1_CHARGE1_SPEC, u8, u8, 3, O>;
#[doc = "Field `SMP15_TKCG15` reader - Channel 15 sample time selection"]
pub type SMP15_TKCG15_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SMP15_TKCG15` writer - Channel 15 sample time selection"]
pub type SMP15_TKCG15_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SAMPTR1_CHARGE1_SPEC, u8, u8, 3, O>;
impl R {
#[doc = "Bits 0:2 - Channel 10 sample time selection"]
#[inline(always)]
pub fn smp10_tkcg10(&self) -> SMP10_TKCG10_R {
SMP10_TKCG10_R::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:5 - Channel 11 sample time selection"]
#[inline(always)]
pub fn smp11_tkcg11(&self) -> SMP11_TKCG11_R {
SMP11_TKCG11_R::new(((self.bits >> 3) & 7) as u8)
}
#[doc = "Bits 6:8 - Channel 12 sample time selection"]
#[inline(always)]
pub fn smp12_tkcg12(&self) -> SMP12_TKCG12_R {
SMP12_TKCG12_R::new(((self.bits >> 6) & 7) as u8)
}
#[doc = "Bits 9:11 - Channel 13 sample time selection"]
#[inline(always)]
pub fn smp13_tkcg13(&self) -> SMP13_TKCG13_R {
SMP13_TKCG13_R::new(((self.bits >> 9) & 7) as u8)
}
#[doc = "Bits 12:14 - Channel 14 sample time selection"]
#[inline(always)]
pub fn smp14_tkcg14(&self) -> SMP14_TKCG14_R {
SMP14_TKCG14_R::new(((self.bits >> 12) & 7) as u8)
}
#[doc = "Bits 15:17 - Channel 15 sample time selection"]
#[inline(always)]
pub fn smp15_tkcg15(&self) -> SMP15_TKCG15_R {
SMP15_TKCG15_R::new(((self.bits >> 15) & 7) as u8)
}
}
impl W {
#[doc = "Bits 0:2 - Channel 10 sample time selection"]
#[inline(always)]
#[must_use]
pub fn smp10_tkcg10(&mut self) -> SMP10_TKCG10_W<0> {
SMP10_TKCG10_W::new(self)
}
#[doc = "Bits 3:5 - Channel 11 sample time selection"]
#[inline(always)]
#[must_use]
pub fn smp11_tkcg11(&mut self) -> SMP11_TKCG11_W<3> {
SMP11_TKCG11_W::new(self)
}
#[doc = "Bits 6:8 - Channel 12 sample time selection"]
#[inline(always)]
#[must_use]
pub fn smp12_tkcg12(&mut self) -> SMP12_TKCG12_W<6> {
SMP12_TKCG12_W::new(self)
}
#[doc = "Bits 9:11 - Channel 13 sample time selection"]
#[inline(always)]
#[must_use]
pub fn smp13_tkcg13(&mut self) -> SMP13_TKCG13_W<9> {
SMP13_TKCG13_W::new(self)
}
#[doc = "Bits 12:14 - Channel 14 sample time selection"]
#[inline(always)]
#[must_use]
pub fn smp14_tkcg14(&mut self) -> SMP14_TKCG14_W<12> {
SMP14_TKCG14_W::new(self)
}
#[doc = "Bits 15:17 - Channel 15 sample time selection"]
#[inline(always)]
#[must_use]
pub fn smp15_tkcg15(&mut self) -> SMP15_TKCG15_W<15> {
SMP15_TKCG15_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "sample time register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [samptr1_charge1](index.html) module"]
pub struct SAMPTR1_CHARGE1_SPEC;
impl crate::RegisterSpec for SAMPTR1_CHARGE1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [samptr1_charge1::R](R) reader structure"]
impl crate::Readable for SAMPTR1_CHARGE1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [samptr1_charge1::W](W) writer structure"]
impl crate::Writable for SAMPTR1_CHARGE1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SAMPTR1_CHARGE1 to value 0"]
impl crate::Resettable for SAMPTR1_CHARGE1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/adc1/samptr2_charge2.rs
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#[doc = "Register `SAMPTR2_CHARGE2` reader"]
pub struct R(crate::R<SAMPTR2_CHARGE2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SAMPTR2_CHARGE2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SAMPTR2_CHARGE2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SAMPTR2_CHARGE2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SAMPTR2_CHARGE2` writer"]
pub struct W(crate::W<SAMPTR2_CHARGE2_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SAMPTR2_CHARGE2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SAMPTR2_CHARGE2_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SAMPTR2_CHARGE2_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SMP0_TKCG0` reader - Channel 0 sample time selection"]
pub type SMP0_TKCG0_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SMP0_TKCG0` writer - Channel 0 sample time selection"]
pub type SMP0_TKCG0_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SAMPTR2_CHARGE2_SPEC, u8, u8, 3, O>;
#[doc = "Field `SMP1_TKCG1` reader - Channel 1 sample time selection"]
pub type SMP1_TKCG1_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SMP1_TKCG1` writer - Channel 1 sample time selection"]
pub type SMP1_TKCG1_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SAMPTR2_CHARGE2_SPEC, u8, u8, 3, O>;
#[doc = "Field `SMP2_TKCG2` reader - Channel 2 sample time selection"]
pub type SMP2_TKCG2_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SMP2_TKCG2` writer - Channel 2 sample time selection"]
pub type SMP2_TKCG2_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SAMPTR2_CHARGE2_SPEC, u8, u8, 3, O>;
#[doc = "Field `SMP3_TKCG3` reader - Channel 3 sample time selection"]
pub type SMP3_TKCG3_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SMP3_TKCG3` writer - Channel 3 sample time selection"]
pub type SMP3_TKCG3_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SAMPTR2_CHARGE2_SPEC, u8, u8, 3, O>;
#[doc = "Field `SMP4_TKCG4` reader - Channel 4 sample time selection"]
pub type SMP4_TKCG4_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SMP4_TKCG4` writer - Channel 4 sample time selection"]
pub type SMP4_TKCG4_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SAMPTR2_CHARGE2_SPEC, u8, u8, 3, O>;
#[doc = "Field `SMP5_TKCG5` reader - Channel 5 sample time selection"]
pub type SMP5_TKCG5_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SMP5_TKCG5` writer - Channel 5 sample time selection"]
pub type SMP5_TKCG5_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SAMPTR2_CHARGE2_SPEC, u8, u8, 3, O>;
#[doc = "Field `SMP6_TKCG6` reader - Channel 6 sample time selection"]
pub type SMP6_TKCG6_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SMP6_TKCG6` writer - Channel 6 sample time selection"]
pub type SMP6_TKCG6_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SAMPTR2_CHARGE2_SPEC, u8, u8, 3, O>;
#[doc = "Field `SMP7_TKCG7` reader - Channel 7 sample time selection"]
pub type SMP7_TKCG7_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SMP7_TKCG7` writer - Channel 7 sample time selection"]
pub type SMP7_TKCG7_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SAMPTR2_CHARGE2_SPEC, u8, u8, 3, O>;
#[doc = "Field `SMP8_TKCG8` reader - Channel 8 sample time selection"]
pub type SMP8_TKCG8_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SMP8_TKCG8` writer - Channel 8 sample time selection"]
pub type SMP8_TKCG8_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SAMPTR2_CHARGE2_SPEC, u8, u8, 3, O>;
#[doc = "Field `SMP9_TKCG9` reader - Channel 9 sample time selection"]
pub type SMP9_TKCG9_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SMP9_TKCG9` writer - Channel 9 sample time selection"]
pub type SMP9_TKCG9_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SAMPTR2_CHARGE2_SPEC, u8, u8, 3, O>;
impl R {
#[doc = "Bits 0:2 - Channel 0 sample time selection"]
#[inline(always)]
pub fn smp0_tkcg0(&self) -> SMP0_TKCG0_R {
SMP0_TKCG0_R::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:5 - Channel 1 sample time selection"]
#[inline(always)]
pub fn smp1_tkcg1(&self) -> SMP1_TKCG1_R {
SMP1_TKCG1_R::new(((self.bits >> 3) & 7) as u8)
}
#[doc = "Bits 6:8 - Channel 2 sample time selection"]
#[inline(always)]
pub fn smp2_tkcg2(&self) -> SMP2_TKCG2_R {
SMP2_TKCG2_R::new(((self.bits >> 6) & 7) as u8)
}
#[doc = "Bits 9:11 - Channel 3 sample time selection"]
#[inline(always)]
pub fn smp3_tkcg3(&self) -> SMP3_TKCG3_R {
SMP3_TKCG3_R::new(((self.bits >> 9) & 7) as u8)
}
#[doc = "Bits 12:14 - Channel 4 sample time selection"]
#[inline(always)]
pub fn smp4_tkcg4(&self) -> SMP4_TKCG4_R {
SMP4_TKCG4_R::new(((self.bits >> 12) & 7) as u8)
}
#[doc = "Bits 15:17 - Channel 5 sample time selection"]
#[inline(always)]
pub fn smp5_tkcg5(&self) -> SMP5_TKCG5_R {
SMP5_TKCG5_R::new(((self.bits >> 15) & 7) as u8)
}
#[doc = "Bits 18:20 - Channel 6 sample time selection"]
#[inline(always)]
pub fn smp6_tkcg6(&self) -> SMP6_TKCG6_R {
SMP6_TKCG6_R::new(((self.bits >> 18) & 7) as u8)
}
#[doc = "Bits 21:23 - Channel 7 sample time selection"]
#[inline(always)]
pub fn smp7_tkcg7(&self) -> SMP7_TKCG7_R {
SMP7_TKCG7_R::new(((self.bits >> 21) & 7) as u8)
}
#[doc = "Bits 24:26 - Channel 8 sample time selection"]
#[inline(always)]
pub fn smp8_tkcg8(&self) -> SMP8_TKCG8_R {
SMP8_TKCG8_R::new(((self.bits >> 24) & 7) as u8)
}
#[doc = "Bits 27:29 - Channel 9 sample time selection"]
#[inline(always)]
pub fn smp9_tkcg9(&self) -> SMP9_TKCG9_R {
SMP9_TKCG9_R::new(((self.bits >> 27) & 7) as u8)
}
}
impl W {
#[doc = "Bits 0:2 - Channel 0 sample time selection"]
#[inline(always)]
#[must_use]
pub fn smp0_tkcg0(&mut self) -> SMP0_TKCG0_W<0> {
SMP0_TKCG0_W::new(self)
}
#[doc = "Bits 3:5 - Channel 1 sample time selection"]
#[inline(always)]
#[must_use]
pub fn smp1_tkcg1(&mut self) -> SMP1_TKCG1_W<3> {
SMP1_TKCG1_W::new(self)
}
#[doc = "Bits 6:8 - Channel 2 sample time selection"]
#[inline(always)]
#[must_use]
pub fn smp2_tkcg2(&mut self) -> SMP2_TKCG2_W<6> {
SMP2_TKCG2_W::new(self)
}
#[doc = "Bits 9:11 - Channel 3 sample time selection"]
#[inline(always)]
#[must_use]
pub fn smp3_tkcg3(&mut self) -> SMP3_TKCG3_W<9> {
SMP3_TKCG3_W::new(self)
}
#[doc = "Bits 12:14 - Channel 4 sample time selection"]
#[inline(always)]
#[must_use]
pub fn smp4_tkcg4(&mut self) -> SMP4_TKCG4_W<12> {
SMP4_TKCG4_W::new(self)
}
#[doc = "Bits 15:17 - Channel 5 sample time selection"]
#[inline(always)]
#[must_use]
pub fn smp5_tkcg5(&mut self) -> SMP5_TKCG5_W<15> {
SMP5_TKCG5_W::new(self)
}
#[doc = "Bits 18:20 - Channel 6 sample time selection"]
#[inline(always)]
#[must_use]
pub fn smp6_tkcg6(&mut self) -> SMP6_TKCG6_W<18> {
SMP6_TKCG6_W::new(self)
}
#[doc = "Bits 21:23 - Channel 7 sample time selection"]
#[inline(always)]
#[must_use]
pub fn smp7_tkcg7(&mut self) -> SMP7_TKCG7_W<21> {
SMP7_TKCG7_W::new(self)
}
#[doc = "Bits 24:26 - Channel 8 sample time selection"]
#[inline(always)]
#[must_use]
pub fn smp8_tkcg8(&mut self) -> SMP8_TKCG8_W<24> {
SMP8_TKCG8_W::new(self)
}
#[doc = "Bits 27:29 - Channel 9 sample time selection"]
#[inline(always)]
#[must_use]
pub fn smp9_tkcg9(&mut self) -> SMP9_TKCG9_W<27> {
SMP9_TKCG9_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "sample time register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [samptr2_charge2](index.html) module"]
pub struct SAMPTR2_CHARGE2_SPEC;
impl crate::RegisterSpec for SAMPTR2_CHARGE2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [samptr2_charge2::R](R) reader structure"]
impl crate::Readable for SAMPTR2_CHARGE2_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [samptr2_charge2::W](W) writer structure"]
impl crate::Writable for SAMPTR2_CHARGE2_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SAMPTR2_CHARGE2 to value 0"]
impl crate::Resettable for SAMPTR2_CHARGE2_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/adc1/statr.rs
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#[doc = "Register `STATR` reader"]
pub struct R(crate::R<STATR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<STATR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<STATR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<STATR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `STATR` writer"]
pub struct W(crate::W<STATR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<STATR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<STATR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<STATR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `AWD` reader - Analog watchdog flag"]
pub type AWD_R = crate::BitReader<bool>;
#[doc = "Field `AWD` writer - Analog watchdog flag"]
pub type AWD_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATR_SPEC, bool, O>;
#[doc = "Field `EOC` reader - Regular channel end of conversion"]
pub type EOC_R = crate::BitReader<bool>;
#[doc = "Field `EOC` writer - Regular channel end of conversion"]
pub type EOC_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATR_SPEC, bool, O>;
#[doc = "Field `JEOC` reader - Injected channel end of conversion"]
pub type JEOC_R = crate::BitReader<bool>;
#[doc = "Field `JEOC` writer - Injected channel end of conversion"]
pub type JEOC_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATR_SPEC, bool, O>;
#[doc = "Field `JSTRT` reader - Injected channel start flag"]
pub type JSTRT_R = crate::BitReader<bool>;
#[doc = "Field `JSTRT` writer - Injected channel start flag"]
pub type JSTRT_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATR_SPEC, bool, O>;
#[doc = "Field `STRT` reader - Regular channel start flag"]
pub type STRT_R = crate::BitReader<bool>;
#[doc = "Field `STRT` writer - Regular channel start flag"]
pub type STRT_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0 - Analog watchdog flag"]
#[inline(always)]
pub fn awd(&self) -> AWD_R {
AWD_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Regular channel end of conversion"]
#[inline(always)]
pub fn eoc(&self) -> EOC_R {
EOC_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Injected channel end of conversion"]
#[inline(always)]
pub fn jeoc(&self) -> JEOC_R {
JEOC_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Injected channel start flag"]
#[inline(always)]
pub fn jstrt(&self) -> JSTRT_R {
JSTRT_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Regular channel start flag"]
#[inline(always)]
pub fn strt(&self) -> STRT_R {
STRT_R::new(((self.bits >> 4) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Analog watchdog flag"]
#[inline(always)]
#[must_use]
pub fn awd(&mut self) -> AWD_W<0> {
AWD_W::new(self)
}
#[doc = "Bit 1 - Regular channel end of conversion"]
#[inline(always)]
#[must_use]
pub fn eoc(&mut self) -> EOC_W<1> {
EOC_W::new(self)
}
#[doc = "Bit 2 - Injected channel end of conversion"]
#[inline(always)]
#[must_use]
pub fn jeoc(&mut self) -> JEOC_W<2> {
JEOC_W::new(self)
}
#[doc = "Bit 3 - Injected channel start flag"]
#[inline(always)]
#[must_use]
pub fn jstrt(&mut self) -> JSTRT_W<3> {
JSTRT_W::new(self)
}
#[doc = "Bit 4 - Regular channel start flag"]
#[inline(always)]
#[must_use]
pub fn strt(&mut self) -> STRT_W<4> {
STRT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statr](index.html) module"]
pub struct STATR_SPEC;
impl crate::RegisterSpec for STATR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [statr::R](R) reader structure"]
impl crate::Readable for STATR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [statr::W](W) writer structure"]
impl crate::Writable for STATR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets STATR to value 0"]
impl crate::Resettable for STATR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/adc1/wdhtr.rs
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#[doc = "Register `WDHTR` reader"]
pub struct R(crate::R<WDHTR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<WDHTR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<WDHTR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<WDHTR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `WDHTR` writer"]
pub struct W(crate::W<WDHTR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<WDHTR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<WDHTR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<WDHTR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `HT` reader - Analog watchdog higher threshold"]
pub type HT_R = crate::FieldReader<u16, u16>;
#[doc = "Field `HT` writer - Analog watchdog higher threshold"]
pub type HT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, WDHTR_SPEC, u16, u16, 10, O>;
impl R {
#[doc = "Bits 0:9 - Analog watchdog higher threshold"]
#[inline(always)]
pub fn ht(&self) -> HT_R {
HT_R::new((self.bits & 0x03ff) as u16)
}
}
impl W {
#[doc = "Bits 0:9 - Analog watchdog higher threshold"]
#[inline(always)]
#[must_use]
pub fn ht(&mut self) -> HT_W<0> {
HT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "watchdog higher threshold register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wdhtr](index.html) module"]
pub struct WDHTR_SPEC;
impl crate::RegisterSpec for WDHTR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [wdhtr::R](R) reader structure"]
impl crate::Readable for WDHTR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [wdhtr::W](W) writer structure"]
impl crate::Writable for WDHTR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets WDHTR to value 0"]
impl crate::Resettable for WDHTR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/adc1/wdltr.rs
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#[doc = "Register `WDLTR` reader"]
pub struct R(crate::R<WDLTR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<WDLTR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<WDLTR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<WDLTR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `WDLTR` writer"]
pub struct W(crate::W<WDLTR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<WDLTR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<WDLTR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<WDLTR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `LT` reader - Analog watchdog lower threshold"]
pub type LT_R = crate::FieldReader<u16, u16>;
#[doc = "Field `LT` writer - Analog watchdog lower threshold"]
pub type LT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, WDLTR_SPEC, u16, u16, 10, O>;
impl R {
#[doc = "Bits 0:9 - Analog watchdog lower threshold"]
#[inline(always)]
pub fn lt(&self) -> LT_R {
LT_R::new((self.bits & 0x03ff) as u16)
}
}
impl W {
#[doc = "Bits 0:9 - Analog watchdog lower threshold"]
#[inline(always)]
#[must_use]
pub fn lt(&mut self) -> LT_W<0> {
LT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "watchdog lower threshold register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wdltr](index.html) module"]
pub struct WDLTR_SPEC;
impl crate::RegisterSpec for WDLTR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [wdltr::R](R) reader structure"]
impl crate::Readable for WDLTR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [wdltr::W](W) writer structure"]
impl crate::Writable for WDLTR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets WDLTR to value 0"]
impl crate::Resettable for WDLTR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/afio.rs
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#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
_reserved0: [u8; 0x04],
#[doc = "0x04 - AF remap and debug I/O configuration register (AFIO_PCFR)"]
pub pcfr: PCFR,
#[doc = "0x08 - External interrupt configuration register (AFIO_EXTICR)"]
pub exticr: EXTICR,
}
#[doc = "PCFR (rw) register accessor: an alias for `Reg<PCFR_SPEC>`"]
pub type PCFR = crate::Reg<pcfr::PCFR_SPEC>;
#[doc = "AF remap and debug I/O configuration register (AFIO_PCFR)"]
pub mod pcfr;
#[doc = "EXTICR (rw) register accessor: an alias for `Reg<EXTICR_SPEC>`"]
pub type EXTICR = crate::Reg<exticr::EXTICR_SPEC>;
#[doc = "External interrupt configuration register (AFIO_EXTICR)"]
pub mod exticr;

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ch32v003-pac/src/afio/exticr.rs
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#[doc = "Register `EXTICR` reader"]
pub struct R(crate::R<EXTICR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<EXTICR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<EXTICR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<EXTICR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `EXTICR` writer"]
pub struct W(crate::W<EXTICR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<EXTICR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<EXTICR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<EXTICR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `EXTI0` reader - EXTI0 configuration"]
pub type EXTI0_R = crate::FieldReader<u8, u8>;
#[doc = "Field `EXTI0` writer - EXTI0 configuration"]
pub type EXTI0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EXTICR_SPEC, u8, u8, 2, O>;
#[doc = "Field `EXTI1` reader - EXTI1 configuration"]
pub type EXTI1_R = crate::FieldReader<u8, u8>;
#[doc = "Field `EXTI1` writer - EXTI1 configuration"]
pub type EXTI1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EXTICR_SPEC, u8, u8, 2, O>;
#[doc = "Field `EXTI2` reader - EXTI2 configuration"]
pub type EXTI2_R = crate::FieldReader<u8, u8>;
#[doc = "Field `EXTI2` writer - EXTI2 configuration"]
pub type EXTI2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EXTICR_SPEC, u8, u8, 2, O>;
#[doc = "Field `EXTI3` reader - EXTI3 configuration"]
pub type EXTI3_R = crate::FieldReader<u8, u8>;
#[doc = "Field `EXTI3` writer - EXTI3 configuration"]
pub type EXTI3_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EXTICR_SPEC, u8, u8, 2, O>;
#[doc = "Field `EXTI4` reader - EXTI4 configuration"]
pub type EXTI4_R = crate::FieldReader<u8, u8>;
#[doc = "Field `EXTI4` writer - EXTI4 configuration"]
pub type EXTI4_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EXTICR_SPEC, u8, u8, 2, O>;
#[doc = "Field `EXTI5` reader - EXTI5 configuration"]
pub type EXTI5_R = crate::FieldReader<u8, u8>;
#[doc = "Field `EXTI5` writer - EXTI5 configuration"]
pub type EXTI5_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EXTICR_SPEC, u8, u8, 2, O>;
#[doc = "Field `EXTI6` reader - EXTI6 configuration"]
pub type EXTI6_R = crate::FieldReader<u8, u8>;
#[doc = "Field `EXTI6` writer - EXTI6 configuration"]
pub type EXTI6_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EXTICR_SPEC, u8, u8, 2, O>;
#[doc = "Field `EXTI7` reader - EXTI7 configuration"]
pub type EXTI7_R = crate::FieldReader<u8, u8>;
#[doc = "Field `EXTI7` writer - EXTI7 configuration"]
pub type EXTI7_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EXTICR_SPEC, u8, u8, 2, O>;
impl R {
#[doc = "Bits 0:1 - EXTI0 configuration"]
#[inline(always)]
pub fn exti0(&self) -> EXTI0_R {
EXTI0_R::new((self.bits & 3) as u8)
}
#[doc = "Bits 2:3 - EXTI1 configuration"]
#[inline(always)]
pub fn exti1(&self) -> EXTI1_R {
EXTI1_R::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bits 4:5 - EXTI2 configuration"]
#[inline(always)]
pub fn exti2(&self) -> EXTI2_R {
EXTI2_R::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 6:7 - EXTI3 configuration"]
#[inline(always)]
pub fn exti3(&self) -> EXTI3_R {
EXTI3_R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:9 - EXTI4 configuration"]
#[inline(always)]
pub fn exti4(&self) -> EXTI4_R {
EXTI4_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - EXTI5 configuration"]
#[inline(always)]
pub fn exti5(&self) -> EXTI5_R {
EXTI5_R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13 - EXTI6 configuration"]
#[inline(always)]
pub fn exti6(&self) -> EXTI6_R {
EXTI6_R::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:15 - EXTI7 configuration"]
#[inline(always)]
pub fn exti7(&self) -> EXTI7_R {
EXTI7_R::new(((self.bits >> 14) & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:1 - EXTI0 configuration"]
#[inline(always)]
#[must_use]
pub fn exti0(&mut self) -> EXTI0_W<0> {
EXTI0_W::new(self)
}
#[doc = "Bits 2:3 - EXTI1 configuration"]
#[inline(always)]
#[must_use]
pub fn exti1(&mut self) -> EXTI1_W<2> {
EXTI1_W::new(self)
}
#[doc = "Bits 4:5 - EXTI2 configuration"]
#[inline(always)]
#[must_use]
pub fn exti2(&mut self) -> EXTI2_W<4> {
EXTI2_W::new(self)
}
#[doc = "Bits 6:7 - EXTI3 configuration"]
#[inline(always)]
#[must_use]
pub fn exti3(&mut self) -> EXTI3_W<6> {
EXTI3_W::new(self)
}
#[doc = "Bits 8:9 - EXTI4 configuration"]
#[inline(always)]
#[must_use]
pub fn exti4(&mut self) -> EXTI4_W<8> {
EXTI4_W::new(self)
}
#[doc = "Bits 10:11 - EXTI5 configuration"]
#[inline(always)]
#[must_use]
pub fn exti5(&mut self) -> EXTI5_W<10> {
EXTI5_W::new(self)
}
#[doc = "Bits 12:13 - EXTI6 configuration"]
#[inline(always)]
#[must_use]
pub fn exti6(&mut self) -> EXTI6_W<12> {
EXTI6_W::new(self)
}
#[doc = "Bits 14:15 - EXTI7 configuration"]
#[inline(always)]
#[must_use]
pub fn exti7(&mut self) -> EXTI7_W<14> {
EXTI7_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "External interrupt configuration register (AFIO_EXTICR)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [exticr](index.html) module"]
pub struct EXTICR_SPEC;
impl crate::RegisterSpec for EXTICR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [exticr::R](R) reader structure"]
impl crate::Readable for EXTICR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [exticr::W](W) writer structure"]
impl crate::Writable for EXTICR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets EXTICR to value 0"]
impl crate::Resettable for EXTICR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/afio/pcfr.rs
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#[doc = "Register `PCFR` reader"]
pub struct R(crate::R<PCFR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PCFR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PCFR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PCFR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PCFR` writer"]
pub struct W(crate::W<PCFR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PCFR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PCFR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PCFR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SPI1RM` reader - SPI1 remapping"]
pub type SPI1RM_R = crate::BitReader<bool>;
#[doc = "Field `SPI1RM` writer - SPI1 remapping"]
pub type SPI1RM_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCFR_SPEC, bool, O>;
#[doc = "Field `I2C1RM` reader - I2C1 remapping"]
pub type I2C1RM_R = crate::BitReader<bool>;
#[doc = "Field `I2C1RM` writer - I2C1 remapping"]
pub type I2C1RM_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCFR_SPEC, bool, O>;
#[doc = "Field `USART1RM` reader - USART1 remapping"]
pub type USART1RM_R = crate::BitReader<bool>;
#[doc = "Field `USART1RM` writer - USART1 remapping"]
pub type USART1RM_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCFR_SPEC, bool, O>;
#[doc = "Field `TIM1RM` reader - TIM1 remapping"]
pub type TIM1RM_R = crate::FieldReader<u8, u8>;
#[doc = "Field `TIM1RM` writer - TIM1 remapping"]
pub type TIM1RM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PCFR_SPEC, u8, u8, 2, O>;
#[doc = "Field `TIM2RM` reader - TIM2 remapping"]
pub type TIM2RM_R = crate::FieldReader<u8, u8>;
#[doc = "Field `TIM2RM` writer - TIM2 remapping"]
pub type TIM2RM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PCFR_SPEC, u8, u8, 2, O>;
#[doc = "Field `PA12RM` reader - Port A1/Port A2 mapping on OSCIN/OSCOUT"]
pub type PA12RM_R = crate::BitReader<bool>;
#[doc = "Field `PA12RM` writer - Port A1/Port A2 mapping on OSCIN/OSCOUT"]
pub type PA12RM_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCFR_SPEC, bool, O>;
#[doc = "Field `ADC1_ETRGINJ_RM` reader - ADC 1 External trigger injected conversion remapping"]
pub type ADC1_ETRGINJ_RM_R = crate::BitReader<bool>;
#[doc = "Field `ADC1_ETRGINJ_RM` writer - ADC 1 External trigger injected conversion remapping"]
pub type ADC1_ETRGINJ_RM_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCFR_SPEC, bool, O>;
#[doc = "Field `ADC1_ETRGREG_RM` reader - ADC 1 external trigger regular conversion remapping"]
pub type ADC1_ETRGREG_RM_R = crate::BitReader<bool>;
#[doc = "Field `ADC1_ETRGREG_RM` writer - ADC 1 external trigger regular conversion remapping"]
pub type ADC1_ETRGREG_RM_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCFR_SPEC, bool, O>;
#[doc = "Field `USART1REMAP1` reader - USART1 remapping"]
pub type USART1REMAP1_R = crate::BitReader<bool>;
#[doc = "Field `USART1REMAP1` writer - USART1 remapping"]
pub type USART1REMAP1_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCFR_SPEC, bool, O>;
#[doc = "Field `I2C1REMAP1` reader - I2C1 remapping"]
pub type I2C1REMAP1_R = crate::BitReader<bool>;
#[doc = "Field `I2C1REMAP1` writer - I2C1 remapping"]
pub type I2C1REMAP1_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCFR_SPEC, bool, O>;
#[doc = "Field `TIM1_IREMAP` reader - TIM1_CH1 channel selection"]
pub type TIM1_IREMAP_R = crate::BitReader<bool>;
#[doc = "Field `TIM1_IREMAP` writer - TIM1_CH1 channel selection"]
pub type TIM1_IREMAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCFR_SPEC, bool, O>;
#[doc = "Field `SWCFG` writer - Serial wire JTAG configuration"]
pub type SWCFG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PCFR_SPEC, u8, u8, 3, O>;
impl R {
#[doc = "Bit 0 - SPI1 remapping"]
#[inline(always)]
pub fn spi1rm(&self) -> SPI1RM_R {
SPI1RM_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - I2C1 remapping"]
#[inline(always)]
pub fn i2c1rm(&self) -> I2C1RM_R {
I2C1RM_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - USART1 remapping"]
#[inline(always)]
pub fn usart1rm(&self) -> USART1RM_R {
USART1RM_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 6:7 - TIM1 remapping"]
#[inline(always)]
pub fn tim1rm(&self) -> TIM1RM_R {
TIM1RM_R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:9 - TIM2 remapping"]
#[inline(always)]
pub fn tim2rm(&self) -> TIM2RM_R {
TIM2RM_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bit 15 - Port A1/Port A2 mapping on OSCIN/OSCOUT"]
#[inline(always)]
pub fn pa12rm(&self) -> PA12RM_R {
PA12RM_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 17 - ADC 1 External trigger injected conversion remapping"]
#[inline(always)]
pub fn adc1_etrginj_rm(&self) -> ADC1_ETRGINJ_RM_R {
ADC1_ETRGINJ_RM_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - ADC 1 external trigger regular conversion remapping"]
#[inline(always)]
pub fn adc1_etrgreg_rm(&self) -> ADC1_ETRGREG_RM_R {
ADC1_ETRGREG_RM_R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 21 - USART1 remapping"]
#[inline(always)]
pub fn usart1remap1(&self) -> USART1REMAP1_R {
USART1REMAP1_R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22 - I2C1 remapping"]
#[inline(always)]
pub fn i2c1remap1(&self) -> I2C1REMAP1_R {
I2C1REMAP1_R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - TIM1_CH1 channel selection"]
#[inline(always)]
pub fn tim1_iremap(&self) -> TIM1_IREMAP_R {
TIM1_IREMAP_R::new(((self.bits >> 23) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - SPI1 remapping"]
#[inline(always)]
#[must_use]
pub fn spi1rm(&mut self) -> SPI1RM_W<0> {
SPI1RM_W::new(self)
}
#[doc = "Bit 1 - I2C1 remapping"]
#[inline(always)]
#[must_use]
pub fn i2c1rm(&mut self) -> I2C1RM_W<1> {
I2C1RM_W::new(self)
}
#[doc = "Bit 2 - USART1 remapping"]
#[inline(always)]
#[must_use]
pub fn usart1rm(&mut self) -> USART1RM_W<2> {
USART1RM_W::new(self)
}
#[doc = "Bits 6:7 - TIM1 remapping"]
#[inline(always)]
#[must_use]
pub fn tim1rm(&mut self) -> TIM1RM_W<6> {
TIM1RM_W::new(self)
}
#[doc = "Bits 8:9 - TIM2 remapping"]
#[inline(always)]
#[must_use]
pub fn tim2rm(&mut self) -> TIM2RM_W<8> {
TIM2RM_W::new(self)
}
#[doc = "Bit 15 - Port A1/Port A2 mapping on OSCIN/OSCOUT"]
#[inline(always)]
#[must_use]
pub fn pa12rm(&mut self) -> PA12RM_W<15> {
PA12RM_W::new(self)
}
#[doc = "Bit 17 - ADC 1 External trigger injected conversion remapping"]
#[inline(always)]
#[must_use]
pub fn adc1_etrginj_rm(&mut self) -> ADC1_ETRGINJ_RM_W<17> {
ADC1_ETRGINJ_RM_W::new(self)
}
#[doc = "Bit 18 - ADC 1 external trigger regular conversion remapping"]
#[inline(always)]
#[must_use]
pub fn adc1_etrgreg_rm(&mut self) -> ADC1_ETRGREG_RM_W<18> {
ADC1_ETRGREG_RM_W::new(self)
}
#[doc = "Bit 21 - USART1 remapping"]
#[inline(always)]
#[must_use]
pub fn usart1remap1(&mut self) -> USART1REMAP1_W<21> {
USART1REMAP1_W::new(self)
}
#[doc = "Bit 22 - I2C1 remapping"]
#[inline(always)]
#[must_use]
pub fn i2c1remap1(&mut self) -> I2C1REMAP1_W<22> {
I2C1REMAP1_W::new(self)
}
#[doc = "Bit 23 - TIM1_CH1 channel selection"]
#[inline(always)]
#[must_use]
pub fn tim1_iremap(&mut self) -> TIM1_IREMAP_W<23> {
TIM1_IREMAP_W::new(self)
}
#[doc = "Bits 24:26 - Serial wire JTAG configuration"]
#[inline(always)]
#[must_use]
pub fn swcfg(&mut self) -> SWCFG_W<24> {
SWCFG_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "AF remap and debug I/O configuration register (AFIO_PCFR)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pcfr](index.html) module"]
pub struct PCFR_SPEC;
impl crate::RegisterSpec for PCFR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [pcfr::R](R) reader structure"]
impl crate::Readable for PCFR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [pcfr::W](W) writer structure"]
impl crate::Writable for PCFR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PCFR to value 0"]
impl crate::Resettable for PCFR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

16
ch32v003-pac/src/dbg.rs
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#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - DBGMCU_CFGR1"]
pub cfgr1: CFGR1,
#[doc = "0x04 - DBGMCU_CFGR2"]
pub cfgr2: CFGR2,
}
#[doc = "CFGR1 (rw) register accessor: an alias for `Reg<CFGR1_SPEC>`"]
pub type CFGR1 = crate::Reg<cfgr1::CFGR1_SPEC>;
#[doc = "DBGMCU_CFGR1"]
pub mod cfgr1;
#[doc = "CFGR2 (rw) register accessor: an alias for `Reg<CFGR2_SPEC>`"]
pub type CFGR2 = crate::Reg<cfgr2::CFGR2_SPEC>;
#[doc = "DBGMCU_CFGR2"]
pub mod cfgr2;

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ch32v003-pac/src/dbg/cfgr1.rs
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#[doc = "Register `CFGR1` reader"]
pub struct R(crate::R<CFGR1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CFGR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CFGR1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CFGR1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CFGR1` writer"]
pub struct W(crate::W<CFGR1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CFGR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CFGR1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CFGR1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DEG_IWDG` reader - DEG_IWDG"]
pub type DEG_IWDG_R = crate::BitReader<bool>;
#[doc = "Field `DEG_IWDG` writer - DEG_IWDG"]
pub type DEG_IWDG_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR1_SPEC, bool, O>;
#[doc = "Field `DEG_WWDG` reader - DEG_WWDG"]
pub type DEG_WWDG_R = crate::BitReader<bool>;
#[doc = "Field `DEG_WWDG` writer - DEG_WWDG"]
pub type DEG_WWDG_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR1_SPEC, bool, O>;
#[doc = "Field `DEG_I2C1` reader - DEG_I2C1"]
pub type DEG_I2C1_R = crate::BitReader<bool>;
#[doc = "Field `DEG_I2C1` writer - DEG_I2C1"]
pub type DEG_I2C1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR1_SPEC, bool, O>;
#[doc = "Field `DEG_TIM1` reader - DEG_TIM1"]
pub type DEG_TIM1_R = crate::BitReader<bool>;
#[doc = "Field `DEG_TIM1` writer - DEG_TIM1"]
pub type DEG_TIM1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR1_SPEC, bool, O>;
#[doc = "Field `DEG_TIM2` reader - DEG_TIM2"]
pub type DEG_TIM2_R = crate::BitReader<bool>;
#[doc = "Field `DEG_TIM2` writer - DEG_TIM2"]
pub type DEG_TIM2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR1_SPEC, bool, O>;
impl R {
#[doc = "Bit 0 - DEG_IWDG"]
#[inline(always)]
pub fn deg_iwdg(&self) -> DEG_IWDG_R {
DEG_IWDG_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - DEG_WWDG"]
#[inline(always)]
pub fn deg_wwdg(&self) -> DEG_WWDG_R {
DEG_WWDG_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - DEG_I2C1"]
#[inline(always)]
pub fn deg_i2c1(&self) -> DEG_I2C1_R {
DEG_I2C1_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 4 - DEG_TIM1"]
#[inline(always)]
pub fn deg_tim1(&self) -> DEG_TIM1_R {
DEG_TIM1_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - DEG_TIM2"]
#[inline(always)]
pub fn deg_tim2(&self) -> DEG_TIM2_R {
DEG_TIM2_R::new(((self.bits >> 5) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - DEG_IWDG"]
#[inline(always)]
#[must_use]
pub fn deg_iwdg(&mut self) -> DEG_IWDG_W<0> {
DEG_IWDG_W::new(self)
}
#[doc = "Bit 1 - DEG_WWDG"]
#[inline(always)]
#[must_use]
pub fn deg_wwdg(&mut self) -> DEG_WWDG_W<1> {
DEG_WWDG_W::new(self)
}
#[doc = "Bit 2 - DEG_I2C1"]
#[inline(always)]
#[must_use]
pub fn deg_i2c1(&mut self) -> DEG_I2C1_W<2> {
DEG_I2C1_W::new(self)
}
#[doc = "Bit 4 - DEG_TIM1"]
#[inline(always)]
#[must_use]
pub fn deg_tim1(&mut self) -> DEG_TIM1_W<4> {
DEG_TIM1_W::new(self)
}
#[doc = "Bit 5 - DEG_TIM2"]
#[inline(always)]
#[must_use]
pub fn deg_tim2(&mut self) -> DEG_TIM2_W<5> {
DEG_TIM2_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DBGMCU_CFGR1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfgr1](index.html) module"]
pub struct CFGR1_SPEC;
impl crate::RegisterSpec for CFGR1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cfgr1::R](R) reader structure"]
impl crate::Readable for CFGR1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cfgr1::W](W) writer structure"]
impl crate::Writable for CFGR1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CFGR1 to value 0"]
impl crate::Resettable for CFGR1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dbg/cfgr2.rs
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#[doc = "Register `CFGR2` reader"]
pub struct R(crate::R<CFGR2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CFGR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CFGR2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CFGR2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CFGR2` writer"]
pub struct W(crate::W<CFGR2_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CFGR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CFGR2_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CFGR2_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DBG_SLEEP` reader - DBG_SLEEP"]
pub type DBG_SLEEP_R = crate::BitReader<bool>;
#[doc = "Field `DBG_SLEEP` writer - DBG_SLEEP"]
pub type DBG_SLEEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR2_SPEC, bool, O>;
#[doc = "Field `DBG_STOP` reader - DBG_STOP"]
pub type DBG_STOP_R = crate::BitReader<bool>;
#[doc = "Field `DBG_STOP` writer - DBG_STOP"]
pub type DBG_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR2_SPEC, bool, O>;
#[doc = "Field `DBG_STANDBY` reader - DBG_STANDBY"]
pub type DBG_STANDBY_R = crate::BitReader<bool>;
#[doc = "Field `DBG_STANDBY` writer - DBG_STANDBY"]
pub type DBG_STANDBY_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR2_SPEC, bool, O>;
impl R {
#[doc = "Bit 0 - DBG_SLEEP"]
#[inline(always)]
pub fn dbg_sleep(&self) -> DBG_SLEEP_R {
DBG_SLEEP_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - DBG_STOP"]
#[inline(always)]
pub fn dbg_stop(&self) -> DBG_STOP_R {
DBG_STOP_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - DBG_STANDBY"]
#[inline(always)]
pub fn dbg_standby(&self) -> DBG_STANDBY_R {
DBG_STANDBY_R::new(((self.bits >> 2) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - DBG_SLEEP"]
#[inline(always)]
#[must_use]
pub fn dbg_sleep(&mut self) -> DBG_SLEEP_W<0> {
DBG_SLEEP_W::new(self)
}
#[doc = "Bit 1 - DBG_STOP"]
#[inline(always)]
#[must_use]
pub fn dbg_stop(&mut self) -> DBG_STOP_W<1> {
DBG_STOP_W::new(self)
}
#[doc = "Bit 2 - DBG_STANDBY"]
#[inline(always)]
#[must_use]
pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<2> {
DBG_STANDBY_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DBGMCU_CFGR2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfgr2](index.html) module"]
pub struct CFGR2_SPEC;
impl crate::RegisterSpec for CFGR2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cfgr2::R](R) reader structure"]
impl crate::Readable for CFGR2_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cfgr2::W](W) writer structure"]
impl crate::Writable for CFGR2_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CFGR2 to value 0"]
impl crate::Resettable for CFGR2_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1.rs
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#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - DMA interrupt status register (DMA_INTFR)"]
pub intfr: INTFR,
#[doc = "0x04 - DMA interrupt flag clear register (DMA_INTFCR)"]
pub intfcr: INTFCR,
#[doc = "0x08 - DMA channel configuration register (DMA_CFGR)"]
pub cfgr1: CFGR1,
#[doc = "0x0c - DMA channel 1 number of data register"]
pub cntr1: CNTR1,
#[doc = "0x10 - DMA channel 1 peripheral address register"]
pub paddr1: PADDR1,
#[doc = "0x14 - DMA channel 1 memory address register"]
pub maddr1: MADDR1,
_reserved6: [u8; 0x04],
#[doc = "0x1c - DMA channel configuration register (DMA_CFGR)"]
pub cfgr2: CFGR2,
#[doc = "0x20 - DMA channel 2 number of data register"]
pub cntr2: CNTR2,
#[doc = "0x24 - DMA channel 2 peripheral address register"]
pub paddr2: PADDR2,
#[doc = "0x28 - DMA channel 2 memory address register"]
pub maddr2: MADDR2,
_reserved10: [u8; 0x04],
#[doc = "0x30 - DMA channel configuration register (DMA_CFGR)"]
pub cfgr3: CFGR3,
#[doc = "0x34 - DMA channel 3 number of data register"]
pub cntr3: CNTR3,
#[doc = "0x38 - DMA channel 3 peripheral address register"]
pub paddr3: PADDR3,
#[doc = "0x3c - DMA channel 3 memory address register"]
pub maddr3: MADDR3,
_reserved14: [u8; 0x04],
#[doc = "0x44 - DMA channel configuration register (DMA_CFGR)"]
pub cfgr4: CFGR4,
#[doc = "0x48 - DMA channel 4 number of data register"]
pub cntr4: CNTR4,
#[doc = "0x4c - DMA channel 4 peripheral address register"]
pub paddr4: PADDR4,
#[doc = "0x50 - DMA channel 4 memory address register"]
pub maddr4: MADDR4,
_reserved18: [u8; 0x04],
#[doc = "0x58 - DMA channel configuration register (DMA_CFGR)"]
pub cfgr5: CFGR5,
#[doc = "0x5c - DMA channel 5 number of data register"]
pub cntr5: CNTR5,
#[doc = "0x60 - DMA channel 5 peripheral address register"]
pub paddr5: PADDR5,
#[doc = "0x64 - DMA channel 5 memory address register"]
pub maddr5: MADDR5,
_reserved22: [u8; 0x04],
#[doc = "0x6c - DMA channel configuration register (DMA_CFGR)"]
pub cfgr6: CFGR6,
#[doc = "0x70 - DMA channel 6 number of data register"]
pub cntr6: CNTR6,
#[doc = "0x74 - DMA channel 6 peripheral address register"]
pub paddr6: PADDR6,
#[doc = "0x78 - DMA channel 6 memory address register"]
pub maddr6: MADDR6,
_reserved26: [u8; 0x04],
#[doc = "0x80 - DMA channel configuration register (DMA_CFGR)"]
pub cfgr7: CFGR7,
#[doc = "0x84 - DMA channel 7 number of data register"]
pub cntr7: CNTR7,
#[doc = "0x88 - DMA channel 7 peripheral address register"]
pub paddr7: PADDR7,
#[doc = "0x8c - DMA channel 7 memory address register"]
pub maddr7: MADDR7,
}
#[doc = "INTFR (r) register accessor: an alias for `Reg<INTFR_SPEC>`"]
pub type INTFR = crate::Reg<intfr::INTFR_SPEC>;
#[doc = "DMA interrupt status register (DMA_INTFR)"]
pub mod intfr;
#[doc = "INTFCR (w) register accessor: an alias for `Reg<INTFCR_SPEC>`"]
pub type INTFCR = crate::Reg<intfcr::INTFCR_SPEC>;
#[doc = "DMA interrupt flag clear register (DMA_INTFCR)"]
pub mod intfcr;
#[doc = "CFGR1 (rw) register accessor: an alias for `Reg<CFGR1_SPEC>`"]
pub type CFGR1 = crate::Reg<cfgr1::CFGR1_SPEC>;
#[doc = "DMA channel configuration register (DMA_CFGR)"]
pub mod cfgr1;
#[doc = "CNTR1 (rw) register accessor: an alias for `Reg<CNTR1_SPEC>`"]
pub type CNTR1 = crate::Reg<cntr1::CNTR1_SPEC>;
#[doc = "DMA channel 1 number of data register"]
pub mod cntr1;
#[doc = "PADDR1 (rw) register accessor: an alias for `Reg<PADDR1_SPEC>`"]
pub type PADDR1 = crate::Reg<paddr1::PADDR1_SPEC>;
#[doc = "DMA channel 1 peripheral address register"]
pub mod paddr1;
#[doc = "MADDR1 (rw) register accessor: an alias for `Reg<MADDR1_SPEC>`"]
pub type MADDR1 = crate::Reg<maddr1::MADDR1_SPEC>;
#[doc = "DMA channel 1 memory address register"]
pub mod maddr1;
#[doc = "CFGR2 (rw) register accessor: an alias for `Reg<CFGR2_SPEC>`"]
pub type CFGR2 = crate::Reg<cfgr2::CFGR2_SPEC>;
#[doc = "DMA channel configuration register (DMA_CFGR)"]
pub mod cfgr2;
#[doc = "CNTR2 (rw) register accessor: an alias for `Reg<CNTR2_SPEC>`"]
pub type CNTR2 = crate::Reg<cntr2::CNTR2_SPEC>;
#[doc = "DMA channel 2 number of data register"]
pub mod cntr2;
#[doc = "PADDR2 (rw) register accessor: an alias for `Reg<PADDR2_SPEC>`"]
pub type PADDR2 = crate::Reg<paddr2::PADDR2_SPEC>;
#[doc = "DMA channel 2 peripheral address register"]
pub mod paddr2;
#[doc = "MADDR2 (rw) register accessor: an alias for `Reg<MADDR2_SPEC>`"]
pub type MADDR2 = crate::Reg<maddr2::MADDR2_SPEC>;
#[doc = "DMA channel 2 memory address register"]
pub mod maddr2;
#[doc = "CFGR3 (rw) register accessor: an alias for `Reg<CFGR3_SPEC>`"]
pub type CFGR3 = crate::Reg<cfgr3::CFGR3_SPEC>;
#[doc = "DMA channel configuration register (DMA_CFGR)"]
pub mod cfgr3;
#[doc = "CNTR3 (rw) register accessor: an alias for `Reg<CNTR3_SPEC>`"]
pub type CNTR3 = crate::Reg<cntr3::CNTR3_SPEC>;
#[doc = "DMA channel 3 number of data register"]
pub mod cntr3;
#[doc = "PADDR3 (rw) register accessor: an alias for `Reg<PADDR3_SPEC>`"]
pub type PADDR3 = crate::Reg<paddr3::PADDR3_SPEC>;
#[doc = "DMA channel 3 peripheral address register"]
pub mod paddr3;
#[doc = "MADDR3 (rw) register accessor: an alias for `Reg<MADDR3_SPEC>`"]
pub type MADDR3 = crate::Reg<maddr3::MADDR3_SPEC>;
#[doc = "DMA channel 3 memory address register"]
pub mod maddr3;
#[doc = "CFGR4 (rw) register accessor: an alias for `Reg<CFGR4_SPEC>`"]
pub type CFGR4 = crate::Reg<cfgr4::CFGR4_SPEC>;
#[doc = "DMA channel configuration register (DMA_CFGR)"]
pub mod cfgr4;
#[doc = "CNTR4 (rw) register accessor: an alias for `Reg<CNTR4_SPEC>`"]
pub type CNTR4 = crate::Reg<cntr4::CNTR4_SPEC>;
#[doc = "DMA channel 4 number of data register"]
pub mod cntr4;
#[doc = "PADDR4 (rw) register accessor: an alias for `Reg<PADDR4_SPEC>`"]
pub type PADDR4 = crate::Reg<paddr4::PADDR4_SPEC>;
#[doc = "DMA channel 4 peripheral address register"]
pub mod paddr4;
#[doc = "MADDR4 (rw) register accessor: an alias for `Reg<MADDR4_SPEC>`"]
pub type MADDR4 = crate::Reg<maddr4::MADDR4_SPEC>;
#[doc = "DMA channel 4 memory address register"]
pub mod maddr4;
#[doc = "CFGR5 (rw) register accessor: an alias for `Reg<CFGR5_SPEC>`"]
pub type CFGR5 = crate::Reg<cfgr5::CFGR5_SPEC>;
#[doc = "DMA channel configuration register (DMA_CFGR)"]
pub mod cfgr5;
#[doc = "CNTR5 (rw) register accessor: an alias for `Reg<CNTR5_SPEC>`"]
pub type CNTR5 = crate::Reg<cntr5::CNTR5_SPEC>;
#[doc = "DMA channel 5 number of data register"]
pub mod cntr5;
#[doc = "PADDR5 (rw) register accessor: an alias for `Reg<PADDR5_SPEC>`"]
pub type PADDR5 = crate::Reg<paddr5::PADDR5_SPEC>;
#[doc = "DMA channel 5 peripheral address register"]
pub mod paddr5;
#[doc = "MADDR5 (rw) register accessor: an alias for `Reg<MADDR5_SPEC>`"]
pub type MADDR5 = crate::Reg<maddr5::MADDR5_SPEC>;
#[doc = "DMA channel 5 memory address register"]
pub mod maddr5;
#[doc = "CFGR6 (rw) register accessor: an alias for `Reg<CFGR6_SPEC>`"]
pub type CFGR6 = crate::Reg<cfgr6::CFGR6_SPEC>;
#[doc = "DMA channel configuration register (DMA_CFGR)"]
pub mod cfgr6;
#[doc = "CNTR6 (rw) register accessor: an alias for `Reg<CNTR6_SPEC>`"]
pub type CNTR6 = crate::Reg<cntr6::CNTR6_SPEC>;
#[doc = "DMA channel 6 number of data register"]
pub mod cntr6;
#[doc = "PADDR6 (rw) register accessor: an alias for `Reg<PADDR6_SPEC>`"]
pub type PADDR6 = crate::Reg<paddr6::PADDR6_SPEC>;
#[doc = "DMA channel 6 peripheral address register"]
pub mod paddr6;
#[doc = "MADDR6 (rw) register accessor: an alias for `Reg<MADDR6_SPEC>`"]
pub type MADDR6 = crate::Reg<maddr6::MADDR6_SPEC>;
#[doc = "DMA channel 6 memory address register"]
pub mod maddr6;
#[doc = "CFGR7 (rw) register accessor: an alias for `Reg<CFGR7_SPEC>`"]
pub type CFGR7 = crate::Reg<cfgr7::CFGR7_SPEC>;
#[doc = "DMA channel configuration register (DMA_CFGR)"]
pub mod cfgr7;
#[doc = "CNTR7 (rw) register accessor: an alias for `Reg<CNTR7_SPEC>`"]
pub type CNTR7 = crate::Reg<cntr7::CNTR7_SPEC>;
#[doc = "DMA channel 7 number of data register"]
pub mod cntr7;
#[doc = "PADDR7 (rw) register accessor: an alias for `Reg<PADDR7_SPEC>`"]
pub type PADDR7 = crate::Reg<paddr7::PADDR7_SPEC>;
#[doc = "DMA channel 7 peripheral address register"]
pub mod paddr7;
#[doc = "MADDR7 (rw) register accessor: an alias for `Reg<MADDR7_SPEC>`"]
pub type MADDR7 = crate::Reg<maddr7::MADDR7_SPEC>;
#[doc = "DMA channel 7 memory address register"]
pub mod maddr7;

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ch32v003-pac/src/dma1/cfgr1.rs
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#[doc = "Register `CFGR1` reader"]
pub struct R(crate::R<CFGR1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CFGR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CFGR1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CFGR1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CFGR1` writer"]
pub struct W(crate::W<CFGR1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CFGR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CFGR1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CFGR1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `EN` reader - Channel enable"]
pub type EN_R = crate::BitReader<bool>;
#[doc = "Field `EN` writer - Channel enable"]
pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR1_SPEC, bool, O>;
#[doc = "Field `TCIE` reader - Transfer complete interrupt enable"]
pub type TCIE_R = crate::BitReader<bool>;
#[doc = "Field `TCIE` writer - Transfer complete interrupt enable"]
pub type TCIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR1_SPEC, bool, O>;
#[doc = "Field `HTIE` reader - Half Transfer interrupt enable"]
pub type HTIE_R = crate::BitReader<bool>;
#[doc = "Field `HTIE` writer - Half Transfer interrupt enable"]
pub type HTIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR1_SPEC, bool, O>;
#[doc = "Field `TEIE` reader - Transfer error interrupt enable"]
pub type TEIE_R = crate::BitReader<bool>;
#[doc = "Field `TEIE` writer - Transfer error interrupt enable"]
pub type TEIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR1_SPEC, bool, O>;
#[doc = "Field `DIR` reader - Data transfer direction"]
pub type DIR_R = crate::BitReader<bool>;
#[doc = "Field `DIR` writer - Data transfer direction"]
pub type DIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR1_SPEC, bool, O>;
#[doc = "Field `CIRC` reader - Circular mode"]
pub type CIRC_R = crate::BitReader<bool>;
#[doc = "Field `CIRC` writer - Circular mode"]
pub type CIRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR1_SPEC, bool, O>;
#[doc = "Field `PINC` reader - Peripheral increment mode"]
pub type PINC_R = crate::BitReader<bool>;
#[doc = "Field `PINC` writer - Peripheral increment mode"]
pub type PINC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR1_SPEC, bool, O>;
#[doc = "Field `MINC` reader - Memory increment mode"]
pub type MINC_R = crate::BitReader<bool>;
#[doc = "Field `MINC` writer - Memory increment mode"]
pub type MINC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR1_SPEC, bool, O>;
#[doc = "Field `PSIZE` reader - Peripheral size"]
pub type PSIZE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PSIZE` writer - Peripheral size"]
pub type PSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR1_SPEC, u8, u8, 2, O>;
#[doc = "Field `MSIZE` reader - Memory size"]
pub type MSIZE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MSIZE` writer - Memory size"]
pub type MSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR1_SPEC, u8, u8, 2, O>;
#[doc = "Field `PL` reader - Channel Priority level"]
pub type PL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PL` writer - Channel Priority level"]
pub type PL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR1_SPEC, u8, u8, 2, O>;
#[doc = "Field `MEM2MEM` reader - Memory to memory mode"]
pub type MEM2MEM_R = crate::BitReader<bool>;
#[doc = "Field `MEM2MEM` writer - Memory to memory mode"]
pub type MEM2MEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR1_SPEC, bool, O>;
impl R {
#[doc = "Bit 0 - Channel enable"]
#[inline(always)]
pub fn en(&self) -> EN_R {
EN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Transfer complete interrupt enable"]
#[inline(always)]
pub fn tcie(&self) -> TCIE_R {
TCIE_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Half Transfer interrupt enable"]
#[inline(always)]
pub fn htie(&self) -> HTIE_R {
HTIE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Transfer error interrupt enable"]
#[inline(always)]
pub fn teie(&self) -> TEIE_R {
TEIE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Data transfer direction"]
#[inline(always)]
pub fn dir(&self) -> DIR_R {
DIR_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Circular mode"]
#[inline(always)]
pub fn circ(&self) -> CIRC_R {
CIRC_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Peripheral increment mode"]
#[inline(always)]
pub fn pinc(&self) -> PINC_R {
PINC_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Memory increment mode"]
#[inline(always)]
pub fn minc(&self) -> MINC_R {
MINC_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - Peripheral size"]
#[inline(always)]
pub fn psize(&self) -> PSIZE_R {
PSIZE_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - Memory size"]
#[inline(always)]
pub fn msize(&self) -> MSIZE_R {
MSIZE_R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13 - Channel Priority level"]
#[inline(always)]
pub fn pl(&self) -> PL_R {
PL_R::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14 - Memory to memory mode"]
#[inline(always)]
pub fn mem2mem(&self) -> MEM2MEM_R {
MEM2MEM_R::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Channel enable"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EN_W<0> {
EN_W::new(self)
}
#[doc = "Bit 1 - Transfer complete interrupt enable"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TCIE_W<1> {
TCIE_W::new(self)
}
#[doc = "Bit 2 - Half Transfer interrupt enable"]
#[inline(always)]
#[must_use]
pub fn htie(&mut self) -> HTIE_W<2> {
HTIE_W::new(self)
}
#[doc = "Bit 3 - Transfer error interrupt enable"]
#[inline(always)]
#[must_use]
pub fn teie(&mut self) -> TEIE_W<3> {
TEIE_W::new(self)
}
#[doc = "Bit 4 - Data transfer direction"]
#[inline(always)]
#[must_use]
pub fn dir(&mut self) -> DIR_W<4> {
DIR_W::new(self)
}
#[doc = "Bit 5 - Circular mode"]
#[inline(always)]
#[must_use]
pub fn circ(&mut self) -> CIRC_W<5> {
CIRC_W::new(self)
}
#[doc = "Bit 6 - Peripheral increment mode"]
#[inline(always)]
#[must_use]
pub fn pinc(&mut self) -> PINC_W<6> {
PINC_W::new(self)
}
#[doc = "Bit 7 - Memory increment mode"]
#[inline(always)]
#[must_use]
pub fn minc(&mut self) -> MINC_W<7> {
MINC_W::new(self)
}
#[doc = "Bits 8:9 - Peripheral size"]
#[inline(always)]
#[must_use]
pub fn psize(&mut self) -> PSIZE_W<8> {
PSIZE_W::new(self)
}
#[doc = "Bits 10:11 - Memory size"]
#[inline(always)]
#[must_use]
pub fn msize(&mut self) -> MSIZE_W<10> {
MSIZE_W::new(self)
}
#[doc = "Bits 12:13 - Channel Priority level"]
#[inline(always)]
#[must_use]
pub fn pl(&mut self) -> PL_W<12> {
PL_W::new(self)
}
#[doc = "Bit 14 - Memory to memory mode"]
#[inline(always)]
#[must_use]
pub fn mem2mem(&mut self) -> MEM2MEM_W<14> {
MEM2MEM_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA channel configuration register (DMA_CFGR)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfgr1](index.html) module"]
pub struct CFGR1_SPEC;
impl crate::RegisterSpec for CFGR1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cfgr1::R](R) reader structure"]
impl crate::Readable for CFGR1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cfgr1::W](W) writer structure"]
impl crate::Writable for CFGR1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CFGR1 to value 0"]
impl crate::Resettable for CFGR1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1/cfgr2.rs
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#[doc = "Register `CFGR2` reader"]
pub struct R(crate::R<CFGR2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CFGR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CFGR2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CFGR2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CFGR2` writer"]
pub struct W(crate::W<CFGR2_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CFGR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CFGR2_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CFGR2_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `EN` reader - Channel enable"]
pub type EN_R = crate::BitReader<bool>;
#[doc = "Field `EN` writer - Channel enable"]
pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR2_SPEC, bool, O>;
#[doc = "Field `TCIE` reader - Transfer complete interrupt enable"]
pub type TCIE_R = crate::BitReader<bool>;
#[doc = "Field `TCIE` writer - Transfer complete interrupt enable"]
pub type TCIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR2_SPEC, bool, O>;
#[doc = "Field `HTIE` reader - Half Transfer interrupt enable"]
pub type HTIE_R = crate::BitReader<bool>;
#[doc = "Field `HTIE` writer - Half Transfer interrupt enable"]
pub type HTIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR2_SPEC, bool, O>;
#[doc = "Field `TEIE` reader - Transfer error interrupt enable"]
pub type TEIE_R = crate::BitReader<bool>;
#[doc = "Field `TEIE` writer - Transfer error interrupt enable"]
pub type TEIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR2_SPEC, bool, O>;
#[doc = "Field `DIR` reader - Data transfer direction"]
pub type DIR_R = crate::BitReader<bool>;
#[doc = "Field `DIR` writer - Data transfer direction"]
pub type DIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR2_SPEC, bool, O>;
#[doc = "Field `CIRC` reader - Circular mode"]
pub type CIRC_R = crate::BitReader<bool>;
#[doc = "Field `CIRC` writer - Circular mode"]
pub type CIRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR2_SPEC, bool, O>;
#[doc = "Field `PINC` reader - Peripheral increment mode"]
pub type PINC_R = crate::BitReader<bool>;
#[doc = "Field `PINC` writer - Peripheral increment mode"]
pub type PINC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR2_SPEC, bool, O>;
#[doc = "Field `MINC` reader - Memory increment mode"]
pub type MINC_R = crate::BitReader<bool>;
#[doc = "Field `MINC` writer - Memory increment mode"]
pub type MINC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR2_SPEC, bool, O>;
#[doc = "Field `PSIZE` reader - Peripheral size"]
pub type PSIZE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PSIZE` writer - Peripheral size"]
pub type PSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR2_SPEC, u8, u8, 2, O>;
#[doc = "Field `MSIZE` reader - Memory size"]
pub type MSIZE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MSIZE` writer - Memory size"]
pub type MSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR2_SPEC, u8, u8, 2, O>;
#[doc = "Field `PL` reader - Channel Priority level"]
pub type PL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PL` writer - Channel Priority level"]
pub type PL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR2_SPEC, u8, u8, 2, O>;
#[doc = "Field `MEM2MEM` reader - Memory to memory mode"]
pub type MEM2MEM_R = crate::BitReader<bool>;
#[doc = "Field `MEM2MEM` writer - Memory to memory mode"]
pub type MEM2MEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR2_SPEC, bool, O>;
impl R {
#[doc = "Bit 0 - Channel enable"]
#[inline(always)]
pub fn en(&self) -> EN_R {
EN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Transfer complete interrupt enable"]
#[inline(always)]
pub fn tcie(&self) -> TCIE_R {
TCIE_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Half Transfer interrupt enable"]
#[inline(always)]
pub fn htie(&self) -> HTIE_R {
HTIE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Transfer error interrupt enable"]
#[inline(always)]
pub fn teie(&self) -> TEIE_R {
TEIE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Data transfer direction"]
#[inline(always)]
pub fn dir(&self) -> DIR_R {
DIR_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Circular mode"]
#[inline(always)]
pub fn circ(&self) -> CIRC_R {
CIRC_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Peripheral increment mode"]
#[inline(always)]
pub fn pinc(&self) -> PINC_R {
PINC_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Memory increment mode"]
#[inline(always)]
pub fn minc(&self) -> MINC_R {
MINC_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - Peripheral size"]
#[inline(always)]
pub fn psize(&self) -> PSIZE_R {
PSIZE_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - Memory size"]
#[inline(always)]
pub fn msize(&self) -> MSIZE_R {
MSIZE_R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13 - Channel Priority level"]
#[inline(always)]
pub fn pl(&self) -> PL_R {
PL_R::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14 - Memory to memory mode"]
#[inline(always)]
pub fn mem2mem(&self) -> MEM2MEM_R {
MEM2MEM_R::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Channel enable"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EN_W<0> {
EN_W::new(self)
}
#[doc = "Bit 1 - Transfer complete interrupt enable"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TCIE_W<1> {
TCIE_W::new(self)
}
#[doc = "Bit 2 - Half Transfer interrupt enable"]
#[inline(always)]
#[must_use]
pub fn htie(&mut self) -> HTIE_W<2> {
HTIE_W::new(self)
}
#[doc = "Bit 3 - Transfer error interrupt enable"]
#[inline(always)]
#[must_use]
pub fn teie(&mut self) -> TEIE_W<3> {
TEIE_W::new(self)
}
#[doc = "Bit 4 - Data transfer direction"]
#[inline(always)]
#[must_use]
pub fn dir(&mut self) -> DIR_W<4> {
DIR_W::new(self)
}
#[doc = "Bit 5 - Circular mode"]
#[inline(always)]
#[must_use]
pub fn circ(&mut self) -> CIRC_W<5> {
CIRC_W::new(self)
}
#[doc = "Bit 6 - Peripheral increment mode"]
#[inline(always)]
#[must_use]
pub fn pinc(&mut self) -> PINC_W<6> {
PINC_W::new(self)
}
#[doc = "Bit 7 - Memory increment mode"]
#[inline(always)]
#[must_use]
pub fn minc(&mut self) -> MINC_W<7> {
MINC_W::new(self)
}
#[doc = "Bits 8:9 - Peripheral size"]
#[inline(always)]
#[must_use]
pub fn psize(&mut self) -> PSIZE_W<8> {
PSIZE_W::new(self)
}
#[doc = "Bits 10:11 - Memory size"]
#[inline(always)]
#[must_use]
pub fn msize(&mut self) -> MSIZE_W<10> {
MSIZE_W::new(self)
}
#[doc = "Bits 12:13 - Channel Priority level"]
#[inline(always)]
#[must_use]
pub fn pl(&mut self) -> PL_W<12> {
PL_W::new(self)
}
#[doc = "Bit 14 - Memory to memory mode"]
#[inline(always)]
#[must_use]
pub fn mem2mem(&mut self) -> MEM2MEM_W<14> {
MEM2MEM_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA channel configuration register (DMA_CFGR)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfgr2](index.html) module"]
pub struct CFGR2_SPEC;
impl crate::RegisterSpec for CFGR2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cfgr2::R](R) reader structure"]
impl crate::Readable for CFGR2_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cfgr2::W](W) writer structure"]
impl crate::Writable for CFGR2_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CFGR2 to value 0"]
impl crate::Resettable for CFGR2_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1/cfgr3.rs
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#[doc = "Register `CFGR3` reader"]
pub struct R(crate::R<CFGR3_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CFGR3_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CFGR3_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CFGR3_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CFGR3` writer"]
pub struct W(crate::W<CFGR3_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CFGR3_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CFGR3_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CFGR3_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `EN` reader - Channel enable"]
pub type EN_R = crate::BitReader<bool>;
#[doc = "Field `EN` writer - Channel enable"]
pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR3_SPEC, bool, O>;
#[doc = "Field `TCIE` reader - Transfer complete interrupt enable"]
pub type TCIE_R = crate::BitReader<bool>;
#[doc = "Field `TCIE` writer - Transfer complete interrupt enable"]
pub type TCIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR3_SPEC, bool, O>;
#[doc = "Field `HTIE` reader - Half Transfer interrupt enable"]
pub type HTIE_R = crate::BitReader<bool>;
#[doc = "Field `HTIE` writer - Half Transfer interrupt enable"]
pub type HTIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR3_SPEC, bool, O>;
#[doc = "Field `TEIE` reader - Transfer error interrupt enable"]
pub type TEIE_R = crate::BitReader<bool>;
#[doc = "Field `TEIE` writer - Transfer error interrupt enable"]
pub type TEIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR3_SPEC, bool, O>;
#[doc = "Field `DIR` reader - Data transfer direction"]
pub type DIR_R = crate::BitReader<bool>;
#[doc = "Field `DIR` writer - Data transfer direction"]
pub type DIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR3_SPEC, bool, O>;
#[doc = "Field `CIRC` reader - Circular mode"]
pub type CIRC_R = crate::BitReader<bool>;
#[doc = "Field `CIRC` writer - Circular mode"]
pub type CIRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR3_SPEC, bool, O>;
#[doc = "Field `PINC` reader - Peripheral increment mode"]
pub type PINC_R = crate::BitReader<bool>;
#[doc = "Field `PINC` writer - Peripheral increment mode"]
pub type PINC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR3_SPEC, bool, O>;
#[doc = "Field `MINC` reader - Memory increment mode"]
pub type MINC_R = crate::BitReader<bool>;
#[doc = "Field `MINC` writer - Memory increment mode"]
pub type MINC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR3_SPEC, bool, O>;
#[doc = "Field `PSIZE` reader - Peripheral size"]
pub type PSIZE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PSIZE` writer - Peripheral size"]
pub type PSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR3_SPEC, u8, u8, 2, O>;
#[doc = "Field `MSIZE` reader - Memory size"]
pub type MSIZE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MSIZE` writer - Memory size"]
pub type MSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR3_SPEC, u8, u8, 2, O>;
#[doc = "Field `PL` reader - Channel Priority level"]
pub type PL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PL` writer - Channel Priority level"]
pub type PL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR3_SPEC, u8, u8, 2, O>;
#[doc = "Field `MEM2MEM` reader - Memory to memory mode"]
pub type MEM2MEM_R = crate::BitReader<bool>;
#[doc = "Field `MEM2MEM` writer - Memory to memory mode"]
pub type MEM2MEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR3_SPEC, bool, O>;
impl R {
#[doc = "Bit 0 - Channel enable"]
#[inline(always)]
pub fn en(&self) -> EN_R {
EN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Transfer complete interrupt enable"]
#[inline(always)]
pub fn tcie(&self) -> TCIE_R {
TCIE_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Half Transfer interrupt enable"]
#[inline(always)]
pub fn htie(&self) -> HTIE_R {
HTIE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Transfer error interrupt enable"]
#[inline(always)]
pub fn teie(&self) -> TEIE_R {
TEIE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Data transfer direction"]
#[inline(always)]
pub fn dir(&self) -> DIR_R {
DIR_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Circular mode"]
#[inline(always)]
pub fn circ(&self) -> CIRC_R {
CIRC_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Peripheral increment mode"]
#[inline(always)]
pub fn pinc(&self) -> PINC_R {
PINC_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Memory increment mode"]
#[inline(always)]
pub fn minc(&self) -> MINC_R {
MINC_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - Peripheral size"]
#[inline(always)]
pub fn psize(&self) -> PSIZE_R {
PSIZE_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - Memory size"]
#[inline(always)]
pub fn msize(&self) -> MSIZE_R {
MSIZE_R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13 - Channel Priority level"]
#[inline(always)]
pub fn pl(&self) -> PL_R {
PL_R::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14 - Memory to memory mode"]
#[inline(always)]
pub fn mem2mem(&self) -> MEM2MEM_R {
MEM2MEM_R::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Channel enable"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EN_W<0> {
EN_W::new(self)
}
#[doc = "Bit 1 - Transfer complete interrupt enable"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TCIE_W<1> {
TCIE_W::new(self)
}
#[doc = "Bit 2 - Half Transfer interrupt enable"]
#[inline(always)]
#[must_use]
pub fn htie(&mut self) -> HTIE_W<2> {
HTIE_W::new(self)
}
#[doc = "Bit 3 - Transfer error interrupt enable"]
#[inline(always)]
#[must_use]
pub fn teie(&mut self) -> TEIE_W<3> {
TEIE_W::new(self)
}
#[doc = "Bit 4 - Data transfer direction"]
#[inline(always)]
#[must_use]
pub fn dir(&mut self) -> DIR_W<4> {
DIR_W::new(self)
}
#[doc = "Bit 5 - Circular mode"]
#[inline(always)]
#[must_use]
pub fn circ(&mut self) -> CIRC_W<5> {
CIRC_W::new(self)
}
#[doc = "Bit 6 - Peripheral increment mode"]
#[inline(always)]
#[must_use]
pub fn pinc(&mut self) -> PINC_W<6> {
PINC_W::new(self)
}
#[doc = "Bit 7 - Memory increment mode"]
#[inline(always)]
#[must_use]
pub fn minc(&mut self) -> MINC_W<7> {
MINC_W::new(self)
}
#[doc = "Bits 8:9 - Peripheral size"]
#[inline(always)]
#[must_use]
pub fn psize(&mut self) -> PSIZE_W<8> {
PSIZE_W::new(self)
}
#[doc = "Bits 10:11 - Memory size"]
#[inline(always)]
#[must_use]
pub fn msize(&mut self) -> MSIZE_W<10> {
MSIZE_W::new(self)
}
#[doc = "Bits 12:13 - Channel Priority level"]
#[inline(always)]
#[must_use]
pub fn pl(&mut self) -> PL_W<12> {
PL_W::new(self)
}
#[doc = "Bit 14 - Memory to memory mode"]
#[inline(always)]
#[must_use]
pub fn mem2mem(&mut self) -> MEM2MEM_W<14> {
MEM2MEM_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA channel configuration register (DMA_CFGR)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfgr3](index.html) module"]
pub struct CFGR3_SPEC;
impl crate::RegisterSpec for CFGR3_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cfgr3::R](R) reader structure"]
impl crate::Readable for CFGR3_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cfgr3::W](W) writer structure"]
impl crate::Writable for CFGR3_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CFGR3 to value 0"]
impl crate::Resettable for CFGR3_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1/cfgr4.rs
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#[doc = "Register `CFGR4` reader"]
pub struct R(crate::R<CFGR4_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CFGR4_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CFGR4_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CFGR4_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CFGR4` writer"]
pub struct W(crate::W<CFGR4_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CFGR4_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CFGR4_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CFGR4_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `EN` reader - Channel enable"]
pub type EN_R = crate::BitReader<bool>;
#[doc = "Field `EN` writer - Channel enable"]
pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR4_SPEC, bool, O>;
#[doc = "Field `TCIE` reader - Transfer complete interrupt enable"]
pub type TCIE_R = crate::BitReader<bool>;
#[doc = "Field `TCIE` writer - Transfer complete interrupt enable"]
pub type TCIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR4_SPEC, bool, O>;
#[doc = "Field `HTIE` reader - Half Transfer interrupt enable"]
pub type HTIE_R = crate::BitReader<bool>;
#[doc = "Field `HTIE` writer - Half Transfer interrupt enable"]
pub type HTIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR4_SPEC, bool, O>;
#[doc = "Field `TEIE` reader - Transfer error interrupt enable"]
pub type TEIE_R = crate::BitReader<bool>;
#[doc = "Field `TEIE` writer - Transfer error interrupt enable"]
pub type TEIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR4_SPEC, bool, O>;
#[doc = "Field `DIR` reader - Data transfer direction"]
pub type DIR_R = crate::BitReader<bool>;
#[doc = "Field `DIR` writer - Data transfer direction"]
pub type DIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR4_SPEC, bool, O>;
#[doc = "Field `CIRC` reader - Circular mode"]
pub type CIRC_R = crate::BitReader<bool>;
#[doc = "Field `CIRC` writer - Circular mode"]
pub type CIRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR4_SPEC, bool, O>;
#[doc = "Field `PINC` reader - Peripheral increment mode"]
pub type PINC_R = crate::BitReader<bool>;
#[doc = "Field `PINC` writer - Peripheral increment mode"]
pub type PINC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR4_SPEC, bool, O>;
#[doc = "Field `MINC` reader - Memory increment mode"]
pub type MINC_R = crate::BitReader<bool>;
#[doc = "Field `MINC` writer - Memory increment mode"]
pub type MINC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR4_SPEC, bool, O>;
#[doc = "Field `PSIZE` reader - Peripheral size"]
pub type PSIZE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PSIZE` writer - Peripheral size"]
pub type PSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR4_SPEC, u8, u8, 2, O>;
#[doc = "Field `MSIZE` reader - Memory size"]
pub type MSIZE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MSIZE` writer - Memory size"]
pub type MSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR4_SPEC, u8, u8, 2, O>;
#[doc = "Field `PL` reader - Channel Priority level"]
pub type PL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PL` writer - Channel Priority level"]
pub type PL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR4_SPEC, u8, u8, 2, O>;
#[doc = "Field `MEM2MEM` reader - Memory to memory mode"]
pub type MEM2MEM_R = crate::BitReader<bool>;
#[doc = "Field `MEM2MEM` writer - Memory to memory mode"]
pub type MEM2MEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR4_SPEC, bool, O>;
impl R {
#[doc = "Bit 0 - Channel enable"]
#[inline(always)]
pub fn en(&self) -> EN_R {
EN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Transfer complete interrupt enable"]
#[inline(always)]
pub fn tcie(&self) -> TCIE_R {
TCIE_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Half Transfer interrupt enable"]
#[inline(always)]
pub fn htie(&self) -> HTIE_R {
HTIE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Transfer error interrupt enable"]
#[inline(always)]
pub fn teie(&self) -> TEIE_R {
TEIE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Data transfer direction"]
#[inline(always)]
pub fn dir(&self) -> DIR_R {
DIR_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Circular mode"]
#[inline(always)]
pub fn circ(&self) -> CIRC_R {
CIRC_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Peripheral increment mode"]
#[inline(always)]
pub fn pinc(&self) -> PINC_R {
PINC_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Memory increment mode"]
#[inline(always)]
pub fn minc(&self) -> MINC_R {
MINC_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - Peripheral size"]
#[inline(always)]
pub fn psize(&self) -> PSIZE_R {
PSIZE_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - Memory size"]
#[inline(always)]
pub fn msize(&self) -> MSIZE_R {
MSIZE_R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13 - Channel Priority level"]
#[inline(always)]
pub fn pl(&self) -> PL_R {
PL_R::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14 - Memory to memory mode"]
#[inline(always)]
pub fn mem2mem(&self) -> MEM2MEM_R {
MEM2MEM_R::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Channel enable"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EN_W<0> {
EN_W::new(self)
}
#[doc = "Bit 1 - Transfer complete interrupt enable"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TCIE_W<1> {
TCIE_W::new(self)
}
#[doc = "Bit 2 - Half Transfer interrupt enable"]
#[inline(always)]
#[must_use]
pub fn htie(&mut self) -> HTIE_W<2> {
HTIE_W::new(self)
}
#[doc = "Bit 3 - Transfer error interrupt enable"]
#[inline(always)]
#[must_use]
pub fn teie(&mut self) -> TEIE_W<3> {
TEIE_W::new(self)
}
#[doc = "Bit 4 - Data transfer direction"]
#[inline(always)]
#[must_use]
pub fn dir(&mut self) -> DIR_W<4> {
DIR_W::new(self)
}
#[doc = "Bit 5 - Circular mode"]
#[inline(always)]
#[must_use]
pub fn circ(&mut self) -> CIRC_W<5> {
CIRC_W::new(self)
}
#[doc = "Bit 6 - Peripheral increment mode"]
#[inline(always)]
#[must_use]
pub fn pinc(&mut self) -> PINC_W<6> {
PINC_W::new(self)
}
#[doc = "Bit 7 - Memory increment mode"]
#[inline(always)]
#[must_use]
pub fn minc(&mut self) -> MINC_W<7> {
MINC_W::new(self)
}
#[doc = "Bits 8:9 - Peripheral size"]
#[inline(always)]
#[must_use]
pub fn psize(&mut self) -> PSIZE_W<8> {
PSIZE_W::new(self)
}
#[doc = "Bits 10:11 - Memory size"]
#[inline(always)]
#[must_use]
pub fn msize(&mut self) -> MSIZE_W<10> {
MSIZE_W::new(self)
}
#[doc = "Bits 12:13 - Channel Priority level"]
#[inline(always)]
#[must_use]
pub fn pl(&mut self) -> PL_W<12> {
PL_W::new(self)
}
#[doc = "Bit 14 - Memory to memory mode"]
#[inline(always)]
#[must_use]
pub fn mem2mem(&mut self) -> MEM2MEM_W<14> {
MEM2MEM_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA channel configuration register (DMA_CFGR)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfgr4](index.html) module"]
pub struct CFGR4_SPEC;
impl crate::RegisterSpec for CFGR4_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cfgr4::R](R) reader structure"]
impl crate::Readable for CFGR4_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cfgr4::W](W) writer structure"]
impl crate::Writable for CFGR4_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CFGR4 to value 0"]
impl crate::Resettable for CFGR4_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1/cfgr5.rs
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#[doc = "Register `CFGR5` reader"]
pub struct R(crate::R<CFGR5_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CFGR5_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CFGR5_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CFGR5_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CFGR5` writer"]
pub struct W(crate::W<CFGR5_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CFGR5_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CFGR5_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CFGR5_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `EN` reader - Channel enable"]
pub type EN_R = crate::BitReader<bool>;
#[doc = "Field `EN` writer - Channel enable"]
pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR5_SPEC, bool, O>;
#[doc = "Field `TCIE` reader - Transfer complete interrupt enable"]
pub type TCIE_R = crate::BitReader<bool>;
#[doc = "Field `TCIE` writer - Transfer complete interrupt enable"]
pub type TCIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR5_SPEC, bool, O>;
#[doc = "Field `HTIE` reader - Half Transfer interrupt enable"]
pub type HTIE_R = crate::BitReader<bool>;
#[doc = "Field `HTIE` writer - Half Transfer interrupt enable"]
pub type HTIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR5_SPEC, bool, O>;
#[doc = "Field `TEIE` reader - Transfer error interrupt enable"]
pub type TEIE_R = crate::BitReader<bool>;
#[doc = "Field `TEIE` writer - Transfer error interrupt enable"]
pub type TEIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR5_SPEC, bool, O>;
#[doc = "Field `DIR` reader - Data transfer direction"]
pub type DIR_R = crate::BitReader<bool>;
#[doc = "Field `DIR` writer - Data transfer direction"]
pub type DIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR5_SPEC, bool, O>;
#[doc = "Field `CIRC` reader - Circular mode"]
pub type CIRC_R = crate::BitReader<bool>;
#[doc = "Field `CIRC` writer - Circular mode"]
pub type CIRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR5_SPEC, bool, O>;
#[doc = "Field `PINC` reader - Peripheral increment mode"]
pub type PINC_R = crate::BitReader<bool>;
#[doc = "Field `PINC` writer - Peripheral increment mode"]
pub type PINC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR5_SPEC, bool, O>;
#[doc = "Field `MINC` reader - Memory increment mode"]
pub type MINC_R = crate::BitReader<bool>;
#[doc = "Field `MINC` writer - Memory increment mode"]
pub type MINC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR5_SPEC, bool, O>;
#[doc = "Field `PSIZE` reader - Peripheral size"]
pub type PSIZE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PSIZE` writer - Peripheral size"]
pub type PSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR5_SPEC, u8, u8, 2, O>;
#[doc = "Field `MSIZE` reader - Memory size"]
pub type MSIZE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MSIZE` writer - Memory size"]
pub type MSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR5_SPEC, u8, u8, 2, O>;
#[doc = "Field `PL` reader - Channel Priority level"]
pub type PL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PL` writer - Channel Priority level"]
pub type PL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR5_SPEC, u8, u8, 2, O>;
#[doc = "Field `MEM2MEM` reader - Memory to memory mode"]
pub type MEM2MEM_R = crate::BitReader<bool>;
#[doc = "Field `MEM2MEM` writer - Memory to memory mode"]
pub type MEM2MEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR5_SPEC, bool, O>;
impl R {
#[doc = "Bit 0 - Channel enable"]
#[inline(always)]
pub fn en(&self) -> EN_R {
EN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Transfer complete interrupt enable"]
#[inline(always)]
pub fn tcie(&self) -> TCIE_R {
TCIE_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Half Transfer interrupt enable"]
#[inline(always)]
pub fn htie(&self) -> HTIE_R {
HTIE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Transfer error interrupt enable"]
#[inline(always)]
pub fn teie(&self) -> TEIE_R {
TEIE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Data transfer direction"]
#[inline(always)]
pub fn dir(&self) -> DIR_R {
DIR_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Circular mode"]
#[inline(always)]
pub fn circ(&self) -> CIRC_R {
CIRC_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Peripheral increment mode"]
#[inline(always)]
pub fn pinc(&self) -> PINC_R {
PINC_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Memory increment mode"]
#[inline(always)]
pub fn minc(&self) -> MINC_R {
MINC_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - Peripheral size"]
#[inline(always)]
pub fn psize(&self) -> PSIZE_R {
PSIZE_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - Memory size"]
#[inline(always)]
pub fn msize(&self) -> MSIZE_R {
MSIZE_R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13 - Channel Priority level"]
#[inline(always)]
pub fn pl(&self) -> PL_R {
PL_R::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14 - Memory to memory mode"]
#[inline(always)]
pub fn mem2mem(&self) -> MEM2MEM_R {
MEM2MEM_R::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Channel enable"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EN_W<0> {
EN_W::new(self)
}
#[doc = "Bit 1 - Transfer complete interrupt enable"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TCIE_W<1> {
TCIE_W::new(self)
}
#[doc = "Bit 2 - Half Transfer interrupt enable"]
#[inline(always)]
#[must_use]
pub fn htie(&mut self) -> HTIE_W<2> {
HTIE_W::new(self)
}
#[doc = "Bit 3 - Transfer error interrupt enable"]
#[inline(always)]
#[must_use]
pub fn teie(&mut self) -> TEIE_W<3> {
TEIE_W::new(self)
}
#[doc = "Bit 4 - Data transfer direction"]
#[inline(always)]
#[must_use]
pub fn dir(&mut self) -> DIR_W<4> {
DIR_W::new(self)
}
#[doc = "Bit 5 - Circular mode"]
#[inline(always)]
#[must_use]
pub fn circ(&mut self) -> CIRC_W<5> {
CIRC_W::new(self)
}
#[doc = "Bit 6 - Peripheral increment mode"]
#[inline(always)]
#[must_use]
pub fn pinc(&mut self) -> PINC_W<6> {
PINC_W::new(self)
}
#[doc = "Bit 7 - Memory increment mode"]
#[inline(always)]
#[must_use]
pub fn minc(&mut self) -> MINC_W<7> {
MINC_W::new(self)
}
#[doc = "Bits 8:9 - Peripheral size"]
#[inline(always)]
#[must_use]
pub fn psize(&mut self) -> PSIZE_W<8> {
PSIZE_W::new(self)
}
#[doc = "Bits 10:11 - Memory size"]
#[inline(always)]
#[must_use]
pub fn msize(&mut self) -> MSIZE_W<10> {
MSIZE_W::new(self)
}
#[doc = "Bits 12:13 - Channel Priority level"]
#[inline(always)]
#[must_use]
pub fn pl(&mut self) -> PL_W<12> {
PL_W::new(self)
}
#[doc = "Bit 14 - Memory to memory mode"]
#[inline(always)]
#[must_use]
pub fn mem2mem(&mut self) -> MEM2MEM_W<14> {
MEM2MEM_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA channel configuration register (DMA_CFGR)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfgr5](index.html) module"]
pub struct CFGR5_SPEC;
impl crate::RegisterSpec for CFGR5_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cfgr5::R](R) reader structure"]
impl crate::Readable for CFGR5_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cfgr5::W](W) writer structure"]
impl crate::Writable for CFGR5_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CFGR5 to value 0"]
impl crate::Resettable for CFGR5_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1/cfgr6.rs
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#[doc = "Register `CFGR6` reader"]
pub struct R(crate::R<CFGR6_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CFGR6_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CFGR6_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CFGR6_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CFGR6` writer"]
pub struct W(crate::W<CFGR6_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CFGR6_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CFGR6_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CFGR6_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `EN` reader - Channel enable"]
pub type EN_R = crate::BitReader<bool>;
#[doc = "Field `EN` writer - Channel enable"]
pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR6_SPEC, bool, O>;
#[doc = "Field `TCIE` reader - Transfer complete interrupt enable"]
pub type TCIE_R = crate::BitReader<bool>;
#[doc = "Field `TCIE` writer - Transfer complete interrupt enable"]
pub type TCIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR6_SPEC, bool, O>;
#[doc = "Field `HTIE` reader - Half Transfer interrupt enable"]
pub type HTIE_R = crate::BitReader<bool>;
#[doc = "Field `HTIE` writer - Half Transfer interrupt enable"]
pub type HTIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR6_SPEC, bool, O>;
#[doc = "Field `TEIE` reader - Transfer error interrupt enable"]
pub type TEIE_R = crate::BitReader<bool>;
#[doc = "Field `TEIE` writer - Transfer error interrupt enable"]
pub type TEIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR6_SPEC, bool, O>;
#[doc = "Field `DIR` reader - Data transfer direction"]
pub type DIR_R = crate::BitReader<bool>;
#[doc = "Field `DIR` writer - Data transfer direction"]
pub type DIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR6_SPEC, bool, O>;
#[doc = "Field `CIRC` reader - Circular mode"]
pub type CIRC_R = crate::BitReader<bool>;
#[doc = "Field `CIRC` writer - Circular mode"]
pub type CIRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR6_SPEC, bool, O>;
#[doc = "Field `PINC` reader - Peripheral increment mode"]
pub type PINC_R = crate::BitReader<bool>;
#[doc = "Field `PINC` writer - Peripheral increment mode"]
pub type PINC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR6_SPEC, bool, O>;
#[doc = "Field `MINC` reader - Memory increment mode"]
pub type MINC_R = crate::BitReader<bool>;
#[doc = "Field `MINC` writer - Memory increment mode"]
pub type MINC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR6_SPEC, bool, O>;
#[doc = "Field `PSIZE` reader - Peripheral size"]
pub type PSIZE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PSIZE` writer - Peripheral size"]
pub type PSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR6_SPEC, u8, u8, 2, O>;
#[doc = "Field `MSIZE` reader - Memory size"]
pub type MSIZE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MSIZE` writer - Memory size"]
pub type MSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR6_SPEC, u8, u8, 2, O>;
#[doc = "Field `PL` reader - Channel Priority level"]
pub type PL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PL` writer - Channel Priority level"]
pub type PL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR6_SPEC, u8, u8, 2, O>;
#[doc = "Field `MEM2MEM` reader - Memory to memory mode"]
pub type MEM2MEM_R = crate::BitReader<bool>;
#[doc = "Field `MEM2MEM` writer - Memory to memory mode"]
pub type MEM2MEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR6_SPEC, bool, O>;
impl R {
#[doc = "Bit 0 - Channel enable"]
#[inline(always)]
pub fn en(&self) -> EN_R {
EN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Transfer complete interrupt enable"]
#[inline(always)]
pub fn tcie(&self) -> TCIE_R {
TCIE_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Half Transfer interrupt enable"]
#[inline(always)]
pub fn htie(&self) -> HTIE_R {
HTIE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Transfer error interrupt enable"]
#[inline(always)]
pub fn teie(&self) -> TEIE_R {
TEIE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Data transfer direction"]
#[inline(always)]
pub fn dir(&self) -> DIR_R {
DIR_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Circular mode"]
#[inline(always)]
pub fn circ(&self) -> CIRC_R {
CIRC_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Peripheral increment mode"]
#[inline(always)]
pub fn pinc(&self) -> PINC_R {
PINC_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Memory increment mode"]
#[inline(always)]
pub fn minc(&self) -> MINC_R {
MINC_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - Peripheral size"]
#[inline(always)]
pub fn psize(&self) -> PSIZE_R {
PSIZE_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - Memory size"]
#[inline(always)]
pub fn msize(&self) -> MSIZE_R {
MSIZE_R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13 - Channel Priority level"]
#[inline(always)]
pub fn pl(&self) -> PL_R {
PL_R::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14 - Memory to memory mode"]
#[inline(always)]
pub fn mem2mem(&self) -> MEM2MEM_R {
MEM2MEM_R::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Channel enable"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EN_W<0> {
EN_W::new(self)
}
#[doc = "Bit 1 - Transfer complete interrupt enable"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TCIE_W<1> {
TCIE_W::new(self)
}
#[doc = "Bit 2 - Half Transfer interrupt enable"]
#[inline(always)]
#[must_use]
pub fn htie(&mut self) -> HTIE_W<2> {
HTIE_W::new(self)
}
#[doc = "Bit 3 - Transfer error interrupt enable"]
#[inline(always)]
#[must_use]
pub fn teie(&mut self) -> TEIE_W<3> {
TEIE_W::new(self)
}
#[doc = "Bit 4 - Data transfer direction"]
#[inline(always)]
#[must_use]
pub fn dir(&mut self) -> DIR_W<4> {
DIR_W::new(self)
}
#[doc = "Bit 5 - Circular mode"]
#[inline(always)]
#[must_use]
pub fn circ(&mut self) -> CIRC_W<5> {
CIRC_W::new(self)
}
#[doc = "Bit 6 - Peripheral increment mode"]
#[inline(always)]
#[must_use]
pub fn pinc(&mut self) -> PINC_W<6> {
PINC_W::new(self)
}
#[doc = "Bit 7 - Memory increment mode"]
#[inline(always)]
#[must_use]
pub fn minc(&mut self) -> MINC_W<7> {
MINC_W::new(self)
}
#[doc = "Bits 8:9 - Peripheral size"]
#[inline(always)]
#[must_use]
pub fn psize(&mut self) -> PSIZE_W<8> {
PSIZE_W::new(self)
}
#[doc = "Bits 10:11 - Memory size"]
#[inline(always)]
#[must_use]
pub fn msize(&mut self) -> MSIZE_W<10> {
MSIZE_W::new(self)
}
#[doc = "Bits 12:13 - Channel Priority level"]
#[inline(always)]
#[must_use]
pub fn pl(&mut self) -> PL_W<12> {
PL_W::new(self)
}
#[doc = "Bit 14 - Memory to memory mode"]
#[inline(always)]
#[must_use]
pub fn mem2mem(&mut self) -> MEM2MEM_W<14> {
MEM2MEM_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA channel configuration register (DMA_CFGR)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfgr6](index.html) module"]
pub struct CFGR6_SPEC;
impl crate::RegisterSpec for CFGR6_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cfgr6::R](R) reader structure"]
impl crate::Readable for CFGR6_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cfgr6::W](W) writer structure"]
impl crate::Writable for CFGR6_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CFGR6 to value 0"]
impl crate::Resettable for CFGR6_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1/cfgr7.rs
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#[doc = "Register `CFGR7` reader"]
pub struct R(crate::R<CFGR7_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CFGR7_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CFGR7_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CFGR7_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CFGR7` writer"]
pub struct W(crate::W<CFGR7_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CFGR7_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CFGR7_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CFGR7_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `EN` reader - Channel enable"]
pub type EN_R = crate::BitReader<bool>;
#[doc = "Field `EN` writer - Channel enable"]
pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR7_SPEC, bool, O>;
#[doc = "Field `TCIE` reader - Transfer complete interrupt enable"]
pub type TCIE_R = crate::BitReader<bool>;
#[doc = "Field `TCIE` writer - Transfer complete interrupt enable"]
pub type TCIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR7_SPEC, bool, O>;
#[doc = "Field `HTIE` reader - Half Transfer interrupt enable"]
pub type HTIE_R = crate::BitReader<bool>;
#[doc = "Field `HTIE` writer - Half Transfer interrupt enable"]
pub type HTIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR7_SPEC, bool, O>;
#[doc = "Field `TEIE` reader - Transfer error interrupt enable"]
pub type TEIE_R = crate::BitReader<bool>;
#[doc = "Field `TEIE` writer - Transfer error interrupt enable"]
pub type TEIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR7_SPEC, bool, O>;
#[doc = "Field `DIR` reader - Data transfer direction"]
pub type DIR_R = crate::BitReader<bool>;
#[doc = "Field `DIR` writer - Data transfer direction"]
pub type DIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR7_SPEC, bool, O>;
#[doc = "Field `CIRC` reader - Circular mode"]
pub type CIRC_R = crate::BitReader<bool>;
#[doc = "Field `CIRC` writer - Circular mode"]
pub type CIRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR7_SPEC, bool, O>;
#[doc = "Field `PINC` reader - Peripheral increment mode"]
pub type PINC_R = crate::BitReader<bool>;
#[doc = "Field `PINC` writer - Peripheral increment mode"]
pub type PINC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR7_SPEC, bool, O>;
#[doc = "Field `MINC` reader - Memory increment mode"]
pub type MINC_R = crate::BitReader<bool>;
#[doc = "Field `MINC` writer - Memory increment mode"]
pub type MINC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR7_SPEC, bool, O>;
#[doc = "Field `PSIZE` reader - Peripheral size"]
pub type PSIZE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PSIZE` writer - Peripheral size"]
pub type PSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR7_SPEC, u8, u8, 2, O>;
#[doc = "Field `MSIZE` reader - Memory size"]
pub type MSIZE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MSIZE` writer - Memory size"]
pub type MSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR7_SPEC, u8, u8, 2, O>;
#[doc = "Field `PL` reader - Channel Priority level"]
pub type PL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PL` writer - Channel Priority level"]
pub type PL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR7_SPEC, u8, u8, 2, O>;
#[doc = "Field `MEM2MEM` reader - Memory to memory mode"]
pub type MEM2MEM_R = crate::BitReader<bool>;
#[doc = "Field `MEM2MEM` writer - Memory to memory mode"]
pub type MEM2MEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR7_SPEC, bool, O>;
impl R {
#[doc = "Bit 0 - Channel enable"]
#[inline(always)]
pub fn en(&self) -> EN_R {
EN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Transfer complete interrupt enable"]
#[inline(always)]
pub fn tcie(&self) -> TCIE_R {
TCIE_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Half Transfer interrupt enable"]
#[inline(always)]
pub fn htie(&self) -> HTIE_R {
HTIE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Transfer error interrupt enable"]
#[inline(always)]
pub fn teie(&self) -> TEIE_R {
TEIE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Data transfer direction"]
#[inline(always)]
pub fn dir(&self) -> DIR_R {
DIR_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Circular mode"]
#[inline(always)]
pub fn circ(&self) -> CIRC_R {
CIRC_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Peripheral increment mode"]
#[inline(always)]
pub fn pinc(&self) -> PINC_R {
PINC_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Memory increment mode"]
#[inline(always)]
pub fn minc(&self) -> MINC_R {
MINC_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - Peripheral size"]
#[inline(always)]
pub fn psize(&self) -> PSIZE_R {
PSIZE_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - Memory size"]
#[inline(always)]
pub fn msize(&self) -> MSIZE_R {
MSIZE_R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13 - Channel Priority level"]
#[inline(always)]
pub fn pl(&self) -> PL_R {
PL_R::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14 - Memory to memory mode"]
#[inline(always)]
pub fn mem2mem(&self) -> MEM2MEM_R {
MEM2MEM_R::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Channel enable"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EN_W<0> {
EN_W::new(self)
}
#[doc = "Bit 1 - Transfer complete interrupt enable"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TCIE_W<1> {
TCIE_W::new(self)
}
#[doc = "Bit 2 - Half Transfer interrupt enable"]
#[inline(always)]
#[must_use]
pub fn htie(&mut self) -> HTIE_W<2> {
HTIE_W::new(self)
}
#[doc = "Bit 3 - Transfer error interrupt enable"]
#[inline(always)]
#[must_use]
pub fn teie(&mut self) -> TEIE_W<3> {
TEIE_W::new(self)
}
#[doc = "Bit 4 - Data transfer direction"]
#[inline(always)]
#[must_use]
pub fn dir(&mut self) -> DIR_W<4> {
DIR_W::new(self)
}
#[doc = "Bit 5 - Circular mode"]
#[inline(always)]
#[must_use]
pub fn circ(&mut self) -> CIRC_W<5> {
CIRC_W::new(self)
}
#[doc = "Bit 6 - Peripheral increment mode"]
#[inline(always)]
#[must_use]
pub fn pinc(&mut self) -> PINC_W<6> {
PINC_W::new(self)
}
#[doc = "Bit 7 - Memory increment mode"]
#[inline(always)]
#[must_use]
pub fn minc(&mut self) -> MINC_W<7> {
MINC_W::new(self)
}
#[doc = "Bits 8:9 - Peripheral size"]
#[inline(always)]
#[must_use]
pub fn psize(&mut self) -> PSIZE_W<8> {
PSIZE_W::new(self)
}
#[doc = "Bits 10:11 - Memory size"]
#[inline(always)]
#[must_use]
pub fn msize(&mut self) -> MSIZE_W<10> {
MSIZE_W::new(self)
}
#[doc = "Bits 12:13 - Channel Priority level"]
#[inline(always)]
#[must_use]
pub fn pl(&mut self) -> PL_W<12> {
PL_W::new(self)
}
#[doc = "Bit 14 - Memory to memory mode"]
#[inline(always)]
#[must_use]
pub fn mem2mem(&mut self) -> MEM2MEM_W<14> {
MEM2MEM_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA channel configuration register (DMA_CFGR)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfgr7](index.html) module"]
pub struct CFGR7_SPEC;
impl crate::RegisterSpec for CFGR7_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cfgr7::R](R) reader structure"]
impl crate::Readable for CFGR7_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cfgr7::W](W) writer structure"]
impl crate::Writable for CFGR7_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CFGR7 to value 0"]
impl crate::Resettable for CFGR7_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1/cntr1.rs
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#[doc = "Register `CNTR1` reader"]
pub struct R(crate::R<CNTR1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CNTR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CNTR1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CNTR1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CNTR1` writer"]
pub struct W(crate::W<CNTR1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CNTR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CNTR1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CNTR1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `NDT` reader - Number of data to transfer"]
pub type NDT_R = crate::FieldReader<u16, u16>;
#[doc = "Field `NDT` writer - Number of data to transfer"]
pub type NDT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTR1_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15 - Number of data to transfer"]
#[inline(always)]
pub fn ndt(&self) -> NDT_R {
NDT_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Number of data to transfer"]
#[inline(always)]
#[must_use]
pub fn ndt(&mut self) -> NDT_W<0> {
NDT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA channel 1 number of data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cntr1](index.html) module"]
pub struct CNTR1_SPEC;
impl crate::RegisterSpec for CNTR1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cntr1::R](R) reader structure"]
impl crate::Readable for CNTR1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cntr1::W](W) writer structure"]
impl crate::Writable for CNTR1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CNTR1 to value 0"]
impl crate::Resettable for CNTR1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1/cntr2.rs
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#[doc = "Register `CNTR2` reader"]
pub struct R(crate::R<CNTR2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CNTR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CNTR2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CNTR2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CNTR2` writer"]
pub struct W(crate::W<CNTR2_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CNTR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CNTR2_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CNTR2_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `NDT` reader - Number of data to transfer"]
pub type NDT_R = crate::FieldReader<u16, u16>;
#[doc = "Field `NDT` writer - Number of data to transfer"]
pub type NDT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTR2_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15 - Number of data to transfer"]
#[inline(always)]
pub fn ndt(&self) -> NDT_R {
NDT_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Number of data to transfer"]
#[inline(always)]
#[must_use]
pub fn ndt(&mut self) -> NDT_W<0> {
NDT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA channel 2 number of data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cntr2](index.html) module"]
pub struct CNTR2_SPEC;
impl crate::RegisterSpec for CNTR2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cntr2::R](R) reader structure"]
impl crate::Readable for CNTR2_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cntr2::W](W) writer structure"]
impl crate::Writable for CNTR2_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CNTR2 to value 0"]
impl crate::Resettable for CNTR2_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1/cntr3.rs
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#[doc = "Register `CNTR3` reader"]
pub struct R(crate::R<CNTR3_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CNTR3_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CNTR3_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CNTR3_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CNTR3` writer"]
pub struct W(crate::W<CNTR3_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CNTR3_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CNTR3_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CNTR3_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `NDT` reader - Number of data to transfer"]
pub type NDT_R = crate::FieldReader<u16, u16>;
#[doc = "Field `NDT` writer - Number of data to transfer"]
pub type NDT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTR3_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15 - Number of data to transfer"]
#[inline(always)]
pub fn ndt(&self) -> NDT_R {
NDT_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Number of data to transfer"]
#[inline(always)]
#[must_use]
pub fn ndt(&mut self) -> NDT_W<0> {
NDT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA channel 3 number of data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cntr3](index.html) module"]
pub struct CNTR3_SPEC;
impl crate::RegisterSpec for CNTR3_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cntr3::R](R) reader structure"]
impl crate::Readable for CNTR3_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cntr3::W](W) writer structure"]
impl crate::Writable for CNTR3_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CNTR3 to value 0"]
impl crate::Resettable for CNTR3_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1/cntr4.rs
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#[doc = "Register `CNTR4` reader"]
pub struct R(crate::R<CNTR4_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CNTR4_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CNTR4_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CNTR4_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CNTR4` writer"]
pub struct W(crate::W<CNTR4_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CNTR4_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CNTR4_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CNTR4_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `NDT` reader - Number of data to transfer"]
pub type NDT_R = crate::FieldReader<u16, u16>;
#[doc = "Field `NDT` writer - Number of data to transfer"]
pub type NDT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTR4_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15 - Number of data to transfer"]
#[inline(always)]
pub fn ndt(&self) -> NDT_R {
NDT_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Number of data to transfer"]
#[inline(always)]
#[must_use]
pub fn ndt(&mut self) -> NDT_W<0> {
NDT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA channel 4 number of data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cntr4](index.html) module"]
pub struct CNTR4_SPEC;
impl crate::RegisterSpec for CNTR4_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cntr4::R](R) reader structure"]
impl crate::Readable for CNTR4_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cntr4::W](W) writer structure"]
impl crate::Writable for CNTR4_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CNTR4 to value 0"]
impl crate::Resettable for CNTR4_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1/cntr5.rs
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#[doc = "Register `CNTR5` reader"]
pub struct R(crate::R<CNTR5_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CNTR5_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CNTR5_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CNTR5_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CNTR5` writer"]
pub struct W(crate::W<CNTR5_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CNTR5_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CNTR5_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CNTR5_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `NDT` reader - Number of data to transfer"]
pub type NDT_R = crate::FieldReader<u16, u16>;
#[doc = "Field `NDT` writer - Number of data to transfer"]
pub type NDT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTR5_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15 - Number of data to transfer"]
#[inline(always)]
pub fn ndt(&self) -> NDT_R {
NDT_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Number of data to transfer"]
#[inline(always)]
#[must_use]
pub fn ndt(&mut self) -> NDT_W<0> {
NDT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA channel 5 number of data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cntr5](index.html) module"]
pub struct CNTR5_SPEC;
impl crate::RegisterSpec for CNTR5_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cntr5::R](R) reader structure"]
impl crate::Readable for CNTR5_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cntr5::W](W) writer structure"]
impl crate::Writable for CNTR5_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CNTR5 to value 0"]
impl crate::Resettable for CNTR5_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1/cntr6.rs
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#[doc = "Register `CNTR6` reader"]
pub struct R(crate::R<CNTR6_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CNTR6_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CNTR6_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CNTR6_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CNTR6` writer"]
pub struct W(crate::W<CNTR6_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CNTR6_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CNTR6_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CNTR6_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `NDT` reader - Number of data to transfer"]
pub type NDT_R = crate::FieldReader<u16, u16>;
#[doc = "Field `NDT` writer - Number of data to transfer"]
pub type NDT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTR6_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15 - Number of data to transfer"]
#[inline(always)]
pub fn ndt(&self) -> NDT_R {
NDT_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Number of data to transfer"]
#[inline(always)]
#[must_use]
pub fn ndt(&mut self) -> NDT_W<0> {
NDT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA channel 6 number of data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cntr6](index.html) module"]
pub struct CNTR6_SPEC;
impl crate::RegisterSpec for CNTR6_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cntr6::R](R) reader structure"]
impl crate::Readable for CNTR6_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cntr6::W](W) writer structure"]
impl crate::Writable for CNTR6_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CNTR6 to value 0"]
impl crate::Resettable for CNTR6_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1/cntr7.rs
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#[doc = "Register `CNTR7` reader"]
pub struct R(crate::R<CNTR7_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CNTR7_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CNTR7_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CNTR7_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CNTR7` writer"]
pub struct W(crate::W<CNTR7_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CNTR7_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CNTR7_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CNTR7_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `NDT` reader - Number of data to transfer"]
pub type NDT_R = crate::FieldReader<u16, u16>;
#[doc = "Field `NDT` writer - Number of data to transfer"]
pub type NDT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTR7_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15 - Number of data to transfer"]
#[inline(always)]
pub fn ndt(&self) -> NDT_R {
NDT_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Number of data to transfer"]
#[inline(always)]
#[must_use]
pub fn ndt(&mut self) -> NDT_W<0> {
NDT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA channel 7 number of data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cntr7](index.html) module"]
pub struct CNTR7_SPEC;
impl crate::RegisterSpec for CNTR7_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cntr7::R](R) reader structure"]
impl crate::Readable for CNTR7_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cntr7::W](W) writer structure"]
impl crate::Writable for CNTR7_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CNTR7 to value 0"]
impl crate::Resettable for CNTR7_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1/intfcr.rs
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#[doc = "Register `INTFCR` writer"]
pub struct W(crate::W<INTFCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<INTFCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<INTFCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<INTFCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CGIF1` writer - Channel 1 Global interrupt clear"]
pub type CGIF1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFCR_SPEC, bool, O>;
#[doc = "Field `CTCIF1` writer - Channel 1 Transfer Complete clear"]
pub type CTCIF1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFCR_SPEC, bool, O>;
#[doc = "Field `CHTIF1` writer - Channel 1 Half Transfer clear"]
pub type CHTIF1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFCR_SPEC, bool, O>;
#[doc = "Field `CTEIF1` writer - Channel 1 Transfer Error clear"]
pub type CTEIF1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFCR_SPEC, bool, O>;
#[doc = "Field `CGIF2` writer - Channel 2 Global interrupt clear"]
pub type CGIF2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFCR_SPEC, bool, O>;
#[doc = "Field `CTCIF2` writer - Channel 2 Transfer Complete clear"]
pub type CTCIF2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFCR_SPEC, bool, O>;
#[doc = "Field `CHTIF2` writer - Channel 2 Half Transfer clear"]
pub type CHTIF2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFCR_SPEC, bool, O>;
#[doc = "Field `CTEIF2` writer - Channel 2 Transfer Error clear"]
pub type CTEIF2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFCR_SPEC, bool, O>;
#[doc = "Field `CGIF3` writer - Channel 3 Global interrupt clear"]
pub type CGIF3_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFCR_SPEC, bool, O>;
#[doc = "Field `CTCIF3` writer - Channel 3 Transfer Complete clear"]
pub type CTCIF3_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFCR_SPEC, bool, O>;
#[doc = "Field `CHTIF3` writer - Channel 3 Half Transfer clear"]
pub type CHTIF3_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFCR_SPEC, bool, O>;
#[doc = "Field `CTEIF3` writer - Channel 3 Transfer Error clear"]
pub type CTEIF3_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFCR_SPEC, bool, O>;
#[doc = "Field `CGIF4` writer - Channel 4 Global interrupt clear"]
pub type CGIF4_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFCR_SPEC, bool, O>;
#[doc = "Field `CTCIF4` writer - Channel 4 Transfer Complete clear"]
pub type CTCIF4_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFCR_SPEC, bool, O>;
#[doc = "Field `CHTIF4` writer - Channel 4 Half Transfer clear"]
pub type CHTIF4_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFCR_SPEC, bool, O>;
#[doc = "Field `CTEIF4` writer - Channel 4 Transfer Error clear"]
pub type CTEIF4_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFCR_SPEC, bool, O>;
#[doc = "Field `CGIF5` writer - Channel 5 Global interrupt clear"]
pub type CGIF5_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFCR_SPEC, bool, O>;
#[doc = "Field `CTCIF5` writer - Channel 5 Transfer Complete clear"]
pub type CTCIF5_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFCR_SPEC, bool, O>;
#[doc = "Field `CHTIF5` writer - Channel 5 Half Transfer clear"]
pub type CHTIF5_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFCR_SPEC, bool, O>;
#[doc = "Field `CTEIF5` writer - Channel 5 Transfer Error clear"]
pub type CTEIF5_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFCR_SPEC, bool, O>;
#[doc = "Field `CGIF6` writer - Channel 6 Global interrupt clear"]
pub type CGIF6_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFCR_SPEC, bool, O>;
#[doc = "Field `CTCIF6` writer - Channel 6 Transfer Complete clear"]
pub type CTCIF6_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFCR_SPEC, bool, O>;
#[doc = "Field `CHTIF6` writer - Channel 6 Half Transfer clear"]
pub type CHTIF6_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFCR_SPEC, bool, O>;
#[doc = "Field `CTEIF6` writer - Channel 6 Transfer Error clear"]
pub type CTEIF6_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFCR_SPEC, bool, O>;
#[doc = "Field `CGIF7` writer - Channel 7 Global interrupt clear"]
pub type CGIF7_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFCR_SPEC, bool, O>;
#[doc = "Field `CTCIF7` writer - Channel 7 Transfer Complete clear"]
pub type CTCIF7_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFCR_SPEC, bool, O>;
#[doc = "Field `CHTIF7` writer - Channel 7 Half Transfer clear"]
pub type CHTIF7_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFCR_SPEC, bool, O>;
#[doc = "Field `CTEIF7` writer - Channel 7 Transfer Error clear"]
pub type CTEIF7_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFCR_SPEC, bool, O>;
impl W {
#[doc = "Bit 0 - Channel 1 Global interrupt clear"]
#[inline(always)]
#[must_use]
pub fn cgif1(&mut self) -> CGIF1_W<0> {
CGIF1_W::new(self)
}
#[doc = "Bit 1 - Channel 1 Transfer Complete clear"]
#[inline(always)]
#[must_use]
pub fn ctcif1(&mut self) -> CTCIF1_W<1> {
CTCIF1_W::new(self)
}
#[doc = "Bit 2 - Channel 1 Half Transfer clear"]
#[inline(always)]
#[must_use]
pub fn chtif1(&mut self) -> CHTIF1_W<2> {
CHTIF1_W::new(self)
}
#[doc = "Bit 3 - Channel 1 Transfer Error clear"]
#[inline(always)]
#[must_use]
pub fn cteif1(&mut self) -> CTEIF1_W<3> {
CTEIF1_W::new(self)
}
#[doc = "Bit 4 - Channel 2 Global interrupt clear"]
#[inline(always)]
#[must_use]
pub fn cgif2(&mut self) -> CGIF2_W<4> {
CGIF2_W::new(self)
}
#[doc = "Bit 5 - Channel 2 Transfer Complete clear"]
#[inline(always)]
#[must_use]
pub fn ctcif2(&mut self) -> CTCIF2_W<5> {
CTCIF2_W::new(self)
}
#[doc = "Bit 6 - Channel 2 Half Transfer clear"]
#[inline(always)]
#[must_use]
pub fn chtif2(&mut self) -> CHTIF2_W<6> {
CHTIF2_W::new(self)
}
#[doc = "Bit 7 - Channel 2 Transfer Error clear"]
#[inline(always)]
#[must_use]
pub fn cteif2(&mut self) -> CTEIF2_W<7> {
CTEIF2_W::new(self)
}
#[doc = "Bit 8 - Channel 3 Global interrupt clear"]
#[inline(always)]
#[must_use]
pub fn cgif3(&mut self) -> CGIF3_W<8> {
CGIF3_W::new(self)
}
#[doc = "Bit 9 - Channel 3 Transfer Complete clear"]
#[inline(always)]
#[must_use]
pub fn ctcif3(&mut self) -> CTCIF3_W<9> {
CTCIF3_W::new(self)
}
#[doc = "Bit 10 - Channel 3 Half Transfer clear"]
#[inline(always)]
#[must_use]
pub fn chtif3(&mut self) -> CHTIF3_W<10> {
CHTIF3_W::new(self)
}
#[doc = "Bit 11 - Channel 3 Transfer Error clear"]
#[inline(always)]
#[must_use]
pub fn cteif3(&mut self) -> CTEIF3_W<11> {
CTEIF3_W::new(self)
}
#[doc = "Bit 12 - Channel 4 Global interrupt clear"]
#[inline(always)]
#[must_use]
pub fn cgif4(&mut self) -> CGIF4_W<12> {
CGIF4_W::new(self)
}
#[doc = "Bit 13 - Channel 4 Transfer Complete clear"]
#[inline(always)]
#[must_use]
pub fn ctcif4(&mut self) -> CTCIF4_W<13> {
CTCIF4_W::new(self)
}
#[doc = "Bit 14 - Channel 4 Half Transfer clear"]
#[inline(always)]
#[must_use]
pub fn chtif4(&mut self) -> CHTIF4_W<14> {
CHTIF4_W::new(self)
}
#[doc = "Bit 15 - Channel 4 Transfer Error clear"]
#[inline(always)]
#[must_use]
pub fn cteif4(&mut self) -> CTEIF4_W<15> {
CTEIF4_W::new(self)
}
#[doc = "Bit 16 - Channel 5 Global interrupt clear"]
#[inline(always)]
#[must_use]
pub fn cgif5(&mut self) -> CGIF5_W<16> {
CGIF5_W::new(self)
}
#[doc = "Bit 17 - Channel 5 Transfer Complete clear"]
#[inline(always)]
#[must_use]
pub fn ctcif5(&mut self) -> CTCIF5_W<17> {
CTCIF5_W::new(self)
}
#[doc = "Bit 18 - Channel 5 Half Transfer clear"]
#[inline(always)]
#[must_use]
pub fn chtif5(&mut self) -> CHTIF5_W<18> {
CHTIF5_W::new(self)
}
#[doc = "Bit 19 - Channel 5 Transfer Error clear"]
#[inline(always)]
#[must_use]
pub fn cteif5(&mut self) -> CTEIF5_W<19> {
CTEIF5_W::new(self)
}
#[doc = "Bit 20 - Channel 6 Global interrupt clear"]
#[inline(always)]
#[must_use]
pub fn cgif6(&mut self) -> CGIF6_W<20> {
CGIF6_W::new(self)
}
#[doc = "Bit 21 - Channel 6 Transfer Complete clear"]
#[inline(always)]
#[must_use]
pub fn ctcif6(&mut self) -> CTCIF6_W<21> {
CTCIF6_W::new(self)
}
#[doc = "Bit 22 - Channel 6 Half Transfer clear"]
#[inline(always)]
#[must_use]
pub fn chtif6(&mut self) -> CHTIF6_W<22> {
CHTIF6_W::new(self)
}
#[doc = "Bit 23 - Channel 6 Transfer Error clear"]
#[inline(always)]
#[must_use]
pub fn cteif6(&mut self) -> CTEIF6_W<23> {
CTEIF6_W::new(self)
}
#[doc = "Bit 24 - Channel 7 Global interrupt clear"]
#[inline(always)]
#[must_use]
pub fn cgif7(&mut self) -> CGIF7_W<24> {
CGIF7_W::new(self)
}
#[doc = "Bit 25 - Channel 7 Transfer Complete clear"]
#[inline(always)]
#[must_use]
pub fn ctcif7(&mut self) -> CTCIF7_W<25> {
CTCIF7_W::new(self)
}
#[doc = "Bit 26 - Channel 7 Half Transfer clear"]
#[inline(always)]
#[must_use]
pub fn chtif7(&mut self) -> CHTIF7_W<26> {
CHTIF7_W::new(self)
}
#[doc = "Bit 27 - Channel 7 Transfer Error clear"]
#[inline(always)]
#[must_use]
pub fn cteif7(&mut self) -> CTEIF7_W<27> {
CTEIF7_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA interrupt flag clear register (DMA_INTFCR)\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intfcr](index.html) module"]
pub struct INTFCR_SPEC;
impl crate::RegisterSpec for INTFCR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [intfcr::W](W) writer structure"]
impl crate::Writable for INTFCR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets INTFCR to value 0"]
impl crate::Resettable for INTFCR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1/intfr.rs
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#[doc = "Register `INTFR` reader"]
pub struct R(crate::R<INTFR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<INTFR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<INTFR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<INTFR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `GIF1` reader - Channel 1 Global interrupt flag"]
pub type GIF1_R = crate::BitReader<bool>;
#[doc = "Field `TCIF1` reader - Channel 1 Transfer Complete flag"]
pub type TCIF1_R = crate::BitReader<bool>;
#[doc = "Field `HTIF1` reader - Channel 1 Half Transfer Complete flag"]
pub type HTIF1_R = crate::BitReader<bool>;
#[doc = "Field `TEIF1` reader - Channel 1 Transfer Error flag"]
pub type TEIF1_R = crate::BitReader<bool>;
#[doc = "Field `GIF2` reader - Channel 2 Global interrupt flag"]
pub type GIF2_R = crate::BitReader<bool>;
#[doc = "Field `TCIF2` reader - Channel 2 Transfer Complete flag"]
pub type TCIF2_R = crate::BitReader<bool>;
#[doc = "Field `HTIF2` reader - Channel 2 Half Transfer Complete flag"]
pub type HTIF2_R = crate::BitReader<bool>;
#[doc = "Field `TEIF2` reader - Channel 2 Transfer Error flag"]
pub type TEIF2_R = crate::BitReader<bool>;
#[doc = "Field `GIF3` reader - Channel 3 Global interrupt flag"]
pub type GIF3_R = crate::BitReader<bool>;
#[doc = "Field `TCIF3` reader - Channel 3 Transfer Complete flag"]
pub type TCIF3_R = crate::BitReader<bool>;
#[doc = "Field `HTIF3` reader - Channel 3 Half Transfer Complete flag"]
pub type HTIF3_R = crate::BitReader<bool>;
#[doc = "Field `TEIF3` reader - Channel 3 Transfer Error flag"]
pub type TEIF3_R = crate::BitReader<bool>;
#[doc = "Field `GIF4` reader - Channel 4 Global interrupt flag"]
pub type GIF4_R = crate::BitReader<bool>;
#[doc = "Field `TCIF4` reader - Channel 4 Transfer Complete flag"]
pub type TCIF4_R = crate::BitReader<bool>;
#[doc = "Field `HTIF4` reader - Channel 4 Half Transfer Complete flag"]
pub type HTIF4_R = crate::BitReader<bool>;
#[doc = "Field `TEIF4` reader - Channel 4 Transfer Error flag"]
pub type TEIF4_R = crate::BitReader<bool>;
#[doc = "Field `GIF5` reader - Channel 5 Global interrupt flag"]
pub type GIF5_R = crate::BitReader<bool>;
#[doc = "Field `TCIF5` reader - Channel 5 Transfer Complete flag"]
pub type TCIF5_R = crate::BitReader<bool>;
#[doc = "Field `HTIF5` reader - Channel 5 Half Transfer Complete flag"]
pub type HTIF5_R = crate::BitReader<bool>;
#[doc = "Field `TEIF5` reader - Channel 5 Transfer Error flag"]
pub type TEIF5_R = crate::BitReader<bool>;
#[doc = "Field `GIF6` reader - Channel 6 Global interrupt flag"]
pub type GIF6_R = crate::BitReader<bool>;
#[doc = "Field `TCIF6` reader - Channel 6 Transfer Complete flag"]
pub type TCIF6_R = crate::BitReader<bool>;
#[doc = "Field `HTIF6` reader - Channel 6 Half Transfer Complete flag"]
pub type HTIF6_R = crate::BitReader<bool>;
#[doc = "Field `TEIF6` reader - Channel 6 Transfer Error flag"]
pub type TEIF6_R = crate::BitReader<bool>;
#[doc = "Field `GIF7` reader - Channel 7 Global interrupt flag"]
pub type GIF7_R = crate::BitReader<bool>;
#[doc = "Field `TCIF7` reader - Channel 7 Transfer Complete flag"]
pub type TCIF7_R = crate::BitReader<bool>;
#[doc = "Field `HTIF7` reader - Channel 7 Half Transfer Complete flag"]
pub type HTIF7_R = crate::BitReader<bool>;
#[doc = "Field `TEIF7` reader - Channel 7 Transfer Error flag"]
pub type TEIF7_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0 - Channel 1 Global interrupt flag"]
#[inline(always)]
pub fn gif1(&self) -> GIF1_R {
GIF1_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Channel 1 Transfer Complete flag"]
#[inline(always)]
pub fn tcif1(&self) -> TCIF1_R {
TCIF1_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Channel 1 Half Transfer Complete flag"]
#[inline(always)]
pub fn htif1(&self) -> HTIF1_R {
HTIF1_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Channel 1 Transfer Error flag"]
#[inline(always)]
pub fn teif1(&self) -> TEIF1_R {
TEIF1_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Channel 2 Global interrupt flag"]
#[inline(always)]
pub fn gif2(&self) -> GIF2_R {
GIF2_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Channel 2 Transfer Complete flag"]
#[inline(always)]
pub fn tcif2(&self) -> TCIF2_R {
TCIF2_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Channel 2 Half Transfer Complete flag"]
#[inline(always)]
pub fn htif2(&self) -> HTIF2_R {
HTIF2_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Channel 2 Transfer Error flag"]
#[inline(always)]
pub fn teif2(&self) -> TEIF2_R {
TEIF2_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Channel 3 Global interrupt flag"]
#[inline(always)]
pub fn gif3(&self) -> GIF3_R {
GIF3_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Channel 3 Transfer Complete flag"]
#[inline(always)]
pub fn tcif3(&self) -> TCIF3_R {
TCIF3_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Channel 3 Half Transfer Complete flag"]
#[inline(always)]
pub fn htif3(&self) -> HTIF3_R {
HTIF3_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Channel 3 Transfer Error flag"]
#[inline(always)]
pub fn teif3(&self) -> TEIF3_R {
TEIF3_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Channel 4 Global interrupt flag"]
#[inline(always)]
pub fn gif4(&self) -> GIF4_R {
GIF4_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - Channel 4 Transfer Complete flag"]
#[inline(always)]
pub fn tcif4(&self) -> TCIF4_R {
TCIF4_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - Channel 4 Half Transfer Complete flag"]
#[inline(always)]
pub fn htif4(&self) -> HTIF4_R {
HTIF4_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - Channel 4 Transfer Error flag"]
#[inline(always)]
pub fn teif4(&self) -> TEIF4_R {
TEIF4_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - Channel 5 Global interrupt flag"]
#[inline(always)]
pub fn gif5(&self) -> GIF5_R {
GIF5_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - Channel 5 Transfer Complete flag"]
#[inline(always)]
pub fn tcif5(&self) -> TCIF5_R {
TCIF5_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - Channel 5 Half Transfer Complete flag"]
#[inline(always)]
pub fn htif5(&self) -> HTIF5_R {
HTIF5_R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - Channel 5 Transfer Error flag"]
#[inline(always)]
pub fn teif5(&self) -> TEIF5_R {
TEIF5_R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20 - Channel 6 Global interrupt flag"]
#[inline(always)]
pub fn gif6(&self) -> GIF6_R {
GIF6_R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21 - Channel 6 Transfer Complete flag"]
#[inline(always)]
pub fn tcif6(&self) -> TCIF6_R {
TCIF6_R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22 - Channel 6 Half Transfer Complete flag"]
#[inline(always)]
pub fn htif6(&self) -> HTIF6_R {
HTIF6_R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - Channel 6 Transfer Error flag"]
#[inline(always)]
pub fn teif6(&self) -> TEIF6_R {
TEIF6_R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24 - Channel 7 Global interrupt flag"]
#[inline(always)]
pub fn gif7(&self) -> GIF7_R {
GIF7_R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25 - Channel 7 Transfer Complete flag"]
#[inline(always)]
pub fn tcif7(&self) -> TCIF7_R {
TCIF7_R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26 - Channel 7 Half Transfer Complete flag"]
#[inline(always)]
pub fn htif7(&self) -> HTIF7_R {
HTIF7_R::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27 - Channel 7 Transfer Error flag"]
#[inline(always)]
pub fn teif7(&self) -> TEIF7_R {
TEIF7_R::new(((self.bits >> 27) & 1) != 0)
}
}
#[doc = "DMA interrupt status register (DMA_INTFR)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intfr](index.html) module"]
pub struct INTFR_SPEC;
impl crate::RegisterSpec for INTFR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [intfr::R](R) reader structure"]
impl crate::Readable for INTFR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets INTFR to value 0"]
impl crate::Resettable for INTFR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1/maddr1.rs
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#[doc = "Register `MADDR1` reader"]
pub struct R(crate::R<MADDR1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MADDR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MADDR1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MADDR1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `MADDR1` writer"]
pub struct W(crate::W<MADDR1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MADDR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MADDR1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MADDR1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `MA` reader - Memory address"]
pub type MA_R = crate::FieldReader<u32, u32>;
#[doc = "Field `MA` writer - Memory address"]
pub type MA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MADDR1_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31 - Memory address"]
#[inline(always)]
pub fn ma(&self) -> MA_R {
MA_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Memory address"]
#[inline(always)]
#[must_use]
pub fn ma(&mut self) -> MA_W<0> {
MA_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA channel 1 memory address register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [maddr1](index.html) module"]
pub struct MADDR1_SPEC;
impl crate::RegisterSpec for MADDR1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [maddr1::R](R) reader structure"]
impl crate::Readable for MADDR1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [maddr1::W](W) writer structure"]
impl crate::Writable for MADDR1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets MADDR1 to value 0"]
impl crate::Resettable for MADDR1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1/maddr2.rs
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#[doc = "Register `MADDR2` reader"]
pub struct R(crate::R<MADDR2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MADDR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MADDR2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MADDR2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `MADDR2` writer"]
pub struct W(crate::W<MADDR2_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MADDR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MADDR2_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MADDR2_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `MA` reader - Memory address"]
pub type MA_R = crate::FieldReader<u32, u32>;
#[doc = "Field `MA` writer - Memory address"]
pub type MA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MADDR2_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31 - Memory address"]
#[inline(always)]
pub fn ma(&self) -> MA_R {
MA_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Memory address"]
#[inline(always)]
#[must_use]
pub fn ma(&mut self) -> MA_W<0> {
MA_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA channel 2 memory address register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [maddr2](index.html) module"]
pub struct MADDR2_SPEC;
impl crate::RegisterSpec for MADDR2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [maddr2::R](R) reader structure"]
impl crate::Readable for MADDR2_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [maddr2::W](W) writer structure"]
impl crate::Writable for MADDR2_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets MADDR2 to value 0"]
impl crate::Resettable for MADDR2_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1/maddr3.rs
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#[doc = "Register `MADDR3` reader"]
pub struct R(crate::R<MADDR3_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MADDR3_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MADDR3_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MADDR3_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `MADDR3` writer"]
pub struct W(crate::W<MADDR3_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MADDR3_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MADDR3_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MADDR3_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `MA` reader - Memory address"]
pub type MA_R = crate::FieldReader<u32, u32>;
#[doc = "Field `MA` writer - Memory address"]
pub type MA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MADDR3_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31 - Memory address"]
#[inline(always)]
pub fn ma(&self) -> MA_R {
MA_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Memory address"]
#[inline(always)]
#[must_use]
pub fn ma(&mut self) -> MA_W<0> {
MA_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA channel 3 memory address register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [maddr3](index.html) module"]
pub struct MADDR3_SPEC;
impl crate::RegisterSpec for MADDR3_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [maddr3::R](R) reader structure"]
impl crate::Readable for MADDR3_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [maddr3::W](W) writer structure"]
impl crate::Writable for MADDR3_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets MADDR3 to value 0"]
impl crate::Resettable for MADDR3_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1/maddr4.rs
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#[doc = "Register `MADDR4` reader"]
pub struct R(crate::R<MADDR4_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MADDR4_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MADDR4_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MADDR4_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `MADDR4` writer"]
pub struct W(crate::W<MADDR4_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MADDR4_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MADDR4_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MADDR4_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `MA` reader - Memory address"]
pub type MA_R = crate::FieldReader<u32, u32>;
#[doc = "Field `MA` writer - Memory address"]
pub type MA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MADDR4_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31 - Memory address"]
#[inline(always)]
pub fn ma(&self) -> MA_R {
MA_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Memory address"]
#[inline(always)]
#[must_use]
pub fn ma(&mut self) -> MA_W<0> {
MA_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA channel 4 memory address register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [maddr4](index.html) module"]
pub struct MADDR4_SPEC;
impl crate::RegisterSpec for MADDR4_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [maddr4::R](R) reader structure"]
impl crate::Readable for MADDR4_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [maddr4::W](W) writer structure"]
impl crate::Writable for MADDR4_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets MADDR4 to value 0"]
impl crate::Resettable for MADDR4_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1/maddr5.rs
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#[doc = "Register `MADDR5` reader"]
pub struct R(crate::R<MADDR5_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MADDR5_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MADDR5_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MADDR5_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `MADDR5` writer"]
pub struct W(crate::W<MADDR5_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MADDR5_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MADDR5_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MADDR5_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `MA` reader - Memory address"]
pub type MA_R = crate::FieldReader<u32, u32>;
#[doc = "Field `MA` writer - Memory address"]
pub type MA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MADDR5_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31 - Memory address"]
#[inline(always)]
pub fn ma(&self) -> MA_R {
MA_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Memory address"]
#[inline(always)]
#[must_use]
pub fn ma(&mut self) -> MA_W<0> {
MA_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA channel 5 memory address register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [maddr5](index.html) module"]
pub struct MADDR5_SPEC;
impl crate::RegisterSpec for MADDR5_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [maddr5::R](R) reader structure"]
impl crate::Readable for MADDR5_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [maddr5::W](W) writer structure"]
impl crate::Writable for MADDR5_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets MADDR5 to value 0"]
impl crate::Resettable for MADDR5_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1/maddr6.rs
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#[doc = "Register `MADDR6` reader"]
pub struct R(crate::R<MADDR6_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MADDR6_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MADDR6_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MADDR6_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `MADDR6` writer"]
pub struct W(crate::W<MADDR6_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MADDR6_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MADDR6_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MADDR6_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `MA` reader - Memory address"]
pub type MA_R = crate::FieldReader<u32, u32>;
#[doc = "Field `MA` writer - Memory address"]
pub type MA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MADDR6_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31 - Memory address"]
#[inline(always)]
pub fn ma(&self) -> MA_R {
MA_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Memory address"]
#[inline(always)]
#[must_use]
pub fn ma(&mut self) -> MA_W<0> {
MA_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA channel 6 memory address register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [maddr6](index.html) module"]
pub struct MADDR6_SPEC;
impl crate::RegisterSpec for MADDR6_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [maddr6::R](R) reader structure"]
impl crate::Readable for MADDR6_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [maddr6::W](W) writer structure"]
impl crate::Writable for MADDR6_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets MADDR6 to value 0"]
impl crate::Resettable for MADDR6_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1/maddr7.rs
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#[doc = "Register `MADDR7` reader"]
pub struct R(crate::R<MADDR7_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MADDR7_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MADDR7_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MADDR7_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `MADDR7` writer"]
pub struct W(crate::W<MADDR7_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MADDR7_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MADDR7_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MADDR7_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `MA` reader - Memory address"]
pub type MA_R = crate::FieldReader<u32, u32>;
#[doc = "Field `MA` writer - Memory address"]
pub type MA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MADDR7_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31 - Memory address"]
#[inline(always)]
pub fn ma(&self) -> MA_R {
MA_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Memory address"]
#[inline(always)]
#[must_use]
pub fn ma(&mut self) -> MA_W<0> {
MA_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA channel 7 memory address register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [maddr7](index.html) module"]
pub struct MADDR7_SPEC;
impl crate::RegisterSpec for MADDR7_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [maddr7::R](R) reader structure"]
impl crate::Readable for MADDR7_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [maddr7::W](W) writer structure"]
impl crate::Writable for MADDR7_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets MADDR7 to value 0"]
impl crate::Resettable for MADDR7_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1/paddr1.rs
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#[doc = "Register `PADDR1` reader"]
pub struct R(crate::R<PADDR1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PADDR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PADDR1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PADDR1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PADDR1` writer"]
pub struct W(crate::W<PADDR1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PADDR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PADDR1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PADDR1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PA` reader - Peripheral address"]
pub type PA_R = crate::FieldReader<u32, u32>;
#[doc = "Field `PA` writer - Peripheral address"]
pub type PA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PADDR1_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31 - Peripheral address"]
#[inline(always)]
pub fn pa(&self) -> PA_R {
PA_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Peripheral address"]
#[inline(always)]
#[must_use]
pub fn pa(&mut self) -> PA_W<0> {
PA_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA channel 1 peripheral address register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [paddr1](index.html) module"]
pub struct PADDR1_SPEC;
impl crate::RegisterSpec for PADDR1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [paddr1::R](R) reader structure"]
impl crate::Readable for PADDR1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [paddr1::W](W) writer structure"]
impl crate::Writable for PADDR1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PADDR1 to value 0"]
impl crate::Resettable for PADDR1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1/paddr2.rs
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#[doc = "Register `PADDR2` reader"]
pub struct R(crate::R<PADDR2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PADDR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PADDR2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PADDR2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PADDR2` writer"]
pub struct W(crate::W<PADDR2_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PADDR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PADDR2_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PADDR2_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PA` reader - Peripheral address"]
pub type PA_R = crate::FieldReader<u32, u32>;
#[doc = "Field `PA` writer - Peripheral address"]
pub type PA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PADDR2_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31 - Peripheral address"]
#[inline(always)]
pub fn pa(&self) -> PA_R {
PA_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Peripheral address"]
#[inline(always)]
#[must_use]
pub fn pa(&mut self) -> PA_W<0> {
PA_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA channel 2 peripheral address register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [paddr2](index.html) module"]
pub struct PADDR2_SPEC;
impl crate::RegisterSpec for PADDR2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [paddr2::R](R) reader structure"]
impl crate::Readable for PADDR2_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [paddr2::W](W) writer structure"]
impl crate::Writable for PADDR2_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PADDR2 to value 0"]
impl crate::Resettable for PADDR2_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1/paddr3.rs
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#[doc = "Register `PADDR3` reader"]
pub struct R(crate::R<PADDR3_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PADDR3_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PADDR3_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PADDR3_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PADDR3` writer"]
pub struct W(crate::W<PADDR3_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PADDR3_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PADDR3_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PADDR3_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PA` reader - Peripheral address"]
pub type PA_R = crate::FieldReader<u32, u32>;
#[doc = "Field `PA` writer - Peripheral address"]
pub type PA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PADDR3_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31 - Peripheral address"]
#[inline(always)]
pub fn pa(&self) -> PA_R {
PA_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Peripheral address"]
#[inline(always)]
#[must_use]
pub fn pa(&mut self) -> PA_W<0> {
PA_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA channel 3 peripheral address register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [paddr3](index.html) module"]
pub struct PADDR3_SPEC;
impl crate::RegisterSpec for PADDR3_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [paddr3::R](R) reader structure"]
impl crate::Readable for PADDR3_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [paddr3::W](W) writer structure"]
impl crate::Writable for PADDR3_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PADDR3 to value 0"]
impl crate::Resettable for PADDR3_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1/paddr4.rs
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#[doc = "Register `PADDR4` reader"]
pub struct R(crate::R<PADDR4_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PADDR4_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PADDR4_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PADDR4_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PADDR4` writer"]
pub struct W(crate::W<PADDR4_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PADDR4_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PADDR4_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PADDR4_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PA` reader - Peripheral address"]
pub type PA_R = crate::FieldReader<u32, u32>;
#[doc = "Field `PA` writer - Peripheral address"]
pub type PA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PADDR4_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31 - Peripheral address"]
#[inline(always)]
pub fn pa(&self) -> PA_R {
PA_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Peripheral address"]
#[inline(always)]
#[must_use]
pub fn pa(&mut self) -> PA_W<0> {
PA_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA channel 4 peripheral address register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [paddr4](index.html) module"]
pub struct PADDR4_SPEC;
impl crate::RegisterSpec for PADDR4_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [paddr4::R](R) reader structure"]
impl crate::Readable for PADDR4_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [paddr4::W](W) writer structure"]
impl crate::Writable for PADDR4_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PADDR4 to value 0"]
impl crate::Resettable for PADDR4_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1/paddr5.rs
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#[doc = "Register `PADDR5` reader"]
pub struct R(crate::R<PADDR5_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PADDR5_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PADDR5_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PADDR5_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PADDR5` writer"]
pub struct W(crate::W<PADDR5_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PADDR5_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PADDR5_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PADDR5_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PA` reader - Peripheral address"]
pub type PA_R = crate::FieldReader<u32, u32>;
#[doc = "Field `PA` writer - Peripheral address"]
pub type PA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PADDR5_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31 - Peripheral address"]
#[inline(always)]
pub fn pa(&self) -> PA_R {
PA_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Peripheral address"]
#[inline(always)]
#[must_use]
pub fn pa(&mut self) -> PA_W<0> {
PA_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA channel 5 peripheral address register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [paddr5](index.html) module"]
pub struct PADDR5_SPEC;
impl crate::RegisterSpec for PADDR5_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [paddr5::R](R) reader structure"]
impl crate::Readable for PADDR5_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [paddr5::W](W) writer structure"]
impl crate::Writable for PADDR5_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PADDR5 to value 0"]
impl crate::Resettable for PADDR5_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1/paddr6.rs
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#[doc = "Register `PADDR6` reader"]
pub struct R(crate::R<PADDR6_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PADDR6_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PADDR6_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PADDR6_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PADDR6` writer"]
pub struct W(crate::W<PADDR6_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PADDR6_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PADDR6_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PADDR6_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PA` reader - Peripheral address"]
pub type PA_R = crate::FieldReader<u32, u32>;
#[doc = "Field `PA` writer - Peripheral address"]
pub type PA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PADDR6_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31 - Peripheral address"]
#[inline(always)]
pub fn pa(&self) -> PA_R {
PA_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Peripheral address"]
#[inline(always)]
#[must_use]
pub fn pa(&mut self) -> PA_W<0> {
PA_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA channel 6 peripheral address register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [paddr6](index.html) module"]
pub struct PADDR6_SPEC;
impl crate::RegisterSpec for PADDR6_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [paddr6::R](R) reader structure"]
impl crate::Readable for PADDR6_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [paddr6::W](W) writer structure"]
impl crate::Writable for PADDR6_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PADDR6 to value 0"]
impl crate::Resettable for PADDR6_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/dma1/paddr7.rs
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#[doc = "Register `PADDR7` reader"]
pub struct R(crate::R<PADDR7_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PADDR7_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PADDR7_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PADDR7_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PADDR7` writer"]
pub struct W(crate::W<PADDR7_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PADDR7_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PADDR7_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PADDR7_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PA` reader - Peripheral address"]
pub type PA_R = crate::FieldReader<u32, u32>;
#[doc = "Field `PA` writer - Peripheral address"]
pub type PA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PADDR7_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31 - Peripheral address"]
#[inline(always)]
pub fn pa(&self) -> PA_R {
PA_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Peripheral address"]
#[inline(always)]
#[must_use]
pub fn pa(&mut self) -> PA_W<0> {
PA_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA channel 7 peripheral address register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [paddr7](index.html) module"]
pub struct PADDR7_SPEC;
impl crate::RegisterSpec for PADDR7_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [paddr7::R](R) reader structure"]
impl crate::Readable for PADDR7_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [paddr7::W](W) writer structure"]
impl crate::Writable for PADDR7_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PADDR7 to value 0"]
impl crate::Resettable for PADDR7_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/esig.rs
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#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Flash capacity register"]
pub flacap: FLACAP,
_reserved1: [u8; 0x06],
#[doc = "0x08 - Unique identity 1"]
pub uniid1: UNIID1,
#[doc = "0x0c - Unique identity 2"]
pub uniid2: UNIID2,
#[doc = "0x10 - Unique identity 3"]
pub uniid3: UNIID3,
}
#[doc = "FLACAP (r) register accessor: an alias for `Reg<FLACAP_SPEC>`"]
pub type FLACAP = crate::Reg<flacap::FLACAP_SPEC>;
#[doc = "Flash capacity register"]
pub mod flacap;
#[doc = "UNIID1 (r) register accessor: an alias for `Reg<UNIID1_SPEC>`"]
pub type UNIID1 = crate::Reg<uniid1::UNIID1_SPEC>;
#[doc = "Unique identity 1"]
pub mod uniid1;
#[doc = "UNIID2 (r) register accessor: an alias for `Reg<UNIID2_SPEC>`"]
pub type UNIID2 = crate::Reg<uniid2::UNIID2_SPEC>;
#[doc = "Unique identity 2"]
pub mod uniid2;
#[doc = "UNIID3 (r) register accessor: an alias for `Reg<UNIID3_SPEC>`"]
pub type UNIID3 = crate::Reg<uniid3::UNIID3_SPEC>;
#[doc = "Unique identity 3"]
pub mod uniid3;

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ch32v003-pac/src/esig/flacap.rs
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#[doc = "Register `FLACAP` reader"]
pub struct R(crate::R<FLACAP_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<FLACAP_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<FLACAP_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<FLACAP_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `FLASHSIZE` reader - Flash size"]
pub type FLASHSIZE_R = crate::FieldReader<u16, u16>;
impl R {
#[doc = "Bits 0:15 - Flash size"]
#[inline(always)]
pub fn flashsize(&self) -> FLASHSIZE_R {
FLASHSIZE_R::new(self.bits)
}
}
#[doc = "Flash capacity register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flacap](index.html) module"]
pub struct FLACAP_SPEC;
impl crate::RegisterSpec for FLACAP_SPEC {
type Ux = u16;
}
#[doc = "`read()` method returns [flacap::R](R) reader structure"]
impl crate::Readable for FLACAP_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets FLACAP to value 0"]
impl crate::Resettable for FLACAP_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/esig/uniid1.rs
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#[doc = "Register `UNIID1` reader"]
pub struct R(crate::R<UNIID1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<UNIID1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<UNIID1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<UNIID1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `U_ID` reader - Unique identity\\[31:0\\]"]
pub type U_ID_R = crate::FieldReader<u32, u32>;
impl R {
#[doc = "Bits 0:31 - Unique identity\\[31:0\\]"]
#[inline(always)]
pub fn u_id(&self) -> U_ID_R {
U_ID_R::new(self.bits)
}
}
#[doc = "Unique identity 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uniid1](index.html) module"]
pub struct UNIID1_SPEC;
impl crate::RegisterSpec for UNIID1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [uniid1::R](R) reader structure"]
impl crate::Readable for UNIID1_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets UNIID1 to value 0"]
impl crate::Resettable for UNIID1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/esig/uniid2.rs
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#[doc = "Register `UNIID2` reader"]
pub struct R(crate::R<UNIID2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<UNIID2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<UNIID2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<UNIID2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `U_ID` reader - Unique identity\\[63:32\\]"]
pub type U_ID_R = crate::FieldReader<u32, u32>;
impl R {
#[doc = "Bits 0:31 - Unique identity\\[63:32\\]"]
#[inline(always)]
pub fn u_id(&self) -> U_ID_R {
U_ID_R::new(self.bits)
}
}
#[doc = "Unique identity 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uniid2](index.html) module"]
pub struct UNIID2_SPEC;
impl crate::RegisterSpec for UNIID2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [uniid2::R](R) reader structure"]
impl crate::Readable for UNIID2_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets UNIID2 to value 0"]
impl crate::Resettable for UNIID2_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/esig/uniid3.rs
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#[doc = "Register `UNIID3` reader"]
pub struct R(crate::R<UNIID3_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<UNIID3_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<UNIID3_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<UNIID3_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `U_ID` reader - Unique identity\\[95:64\\]"]
pub type U_ID_R = crate::FieldReader<u32, u32>;
impl R {
#[doc = "Bits 0:31 - Unique identity\\[95:64\\]"]
#[inline(always)]
pub fn u_id(&self) -> U_ID_R {
U_ID_R::new(self.bits)
}
}
#[doc = "Unique identity 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uniid3](index.html) module"]
pub struct UNIID3_SPEC;
impl crate::RegisterSpec for UNIID3_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [uniid3::R](R) reader structure"]
impl crate::Readable for UNIID3_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets UNIID3 to value 0"]
impl crate::Resettable for UNIID3_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

16
ch32v003-pac/src/extend.rs
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#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Configure the extended control register"]
pub extend_ctr: EXTEND_CTR,
#[doc = "0x04 - Configure the extended key register"]
pub extend_kr: EXTEND_KR,
}
#[doc = "EXTEND_CTR (rw) register accessor: an alias for `Reg<EXTEND_CTR_SPEC>`"]
pub type EXTEND_CTR = crate::Reg<extend_ctr::EXTEND_CTR_SPEC>;
#[doc = "Configure the extended control register"]
pub mod extend_ctr;
#[doc = "EXTEND_KR (w) register accessor: an alias for `Reg<EXTEND_KR_SPEC>`"]
pub type EXTEND_KR = crate::Reg<extend_kr::EXTEND_KR_SPEC>;
#[doc = "Configure the extended key register"]
pub mod extend_kr;

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ch32v003-pac/src/extend/extend_ctr.rs
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#[doc = "Register `EXTEND_CTR` reader"]
pub struct R(crate::R<EXTEND_CTR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<EXTEND_CTR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<EXTEND_CTR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<EXTEND_CTR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `EXTEND_CTR` writer"]
pub struct W(crate::W<EXTEND_CTR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<EXTEND_CTR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<EXTEND_CTR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<EXTEND_CTR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PLL_CFG` reader - Configure the PLL clock delay time"]
pub type PLL_CFG_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PLL_CFG` writer - Configure the PLL clock delay time"]
pub type PLL_CFG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EXTEND_CTR_SPEC, u8, u8, 4, O>;
#[doc = "Field `LOCKUP_EN` reader - LOCKUP_Enable"]
pub type LOCKUP_EN_R = crate::BitReader<bool>;
#[doc = "Field `LOCKUP_EN` writer - LOCKUP_Enable"]
pub type LOCKUP_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, EXTEND_CTR_SPEC, bool, O>;
#[doc = "Field `LOCKUP_RESET` reader - LOCKUP RESET"]
pub type LOCKUP_RESET_R = crate::BitReader<bool>;
#[doc = "Field `LOCKUP_RESET` writer - LOCKUP RESET"]
pub type LOCKUP_RESET_W<'a, const O: u8> = crate::BitWriter<'a, u32, EXTEND_CTR_SPEC, bool, O>;
#[doc = "Field `LDO_TRIM` reader - LDO_TRIM"]
pub type LDO_TRIM_R = crate::BitReader<bool>;
#[doc = "Field `LDO_TRIM` writer - LDO_TRIM"]
pub type LDO_TRIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, EXTEND_CTR_SPEC, bool, O>;
#[doc = "Field `FLASH_CLK_TRIM` reader - FLASH clock trimming"]
pub type FLASH_CLK_TRIM_R = crate::FieldReader<u8, u8>;
#[doc = "Field `FLASH_CLK_TRIM` writer - FLASH clock trimming"]
pub type FLASH_CLK_TRIM_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, EXTEND_CTR_SPEC, u8, u8, 3, O>;
#[doc = "Field `WR_EN` reader - Control Register write enable"]
pub type WR_EN_R = crate::BitReader<bool>;
#[doc = "Field `WR_EN` writer - Control Register write enable"]
pub type WR_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, EXTEND_CTR_SPEC, bool, O>;
#[doc = "Field `WR_LOCK` reader - Control Register write lock"]
pub type WR_LOCK_R = crate::BitReader<bool>;
#[doc = "Field `WR_LOCK` writer - Control Register write lock"]
pub type WR_LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, EXTEND_CTR_SPEC, bool, O>;
#[doc = "Field `OPA_EN` reader - OPA Enalbe"]
pub type OPA_EN_R = crate::BitReader<bool>;
#[doc = "Field `OPA_EN` writer - OPA Enalbe"]
pub type OPA_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, EXTEND_CTR_SPEC, bool, O>;
#[doc = "Field `OPA_NSEL` reader - OPA negative end channel selection"]
pub type OPA_NSEL_R = crate::BitReader<bool>;
#[doc = "Field `OPA_NSEL` writer - OPA negative end channel selection"]
pub type OPA_NSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, EXTEND_CTR_SPEC, bool, O>;
#[doc = "Field `OPA_PSEL` reader - OPA positive end channel selection"]
pub type OPA_PSEL_R = crate::BitReader<bool>;
#[doc = "Field `OPA_PSEL` writer - OPA positive end channel selection"]
pub type OPA_PSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, EXTEND_CTR_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:3 - Configure the PLL clock delay time"]
#[inline(always)]
pub fn pll_cfg(&self) -> PLL_CFG_R {
PLL_CFG_R::new((self.bits & 0x0f) as u8)
}
#[doc = "Bit 6 - LOCKUP_Enable"]
#[inline(always)]
pub fn lockup_en(&self) -> LOCKUP_EN_R {
LOCKUP_EN_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - LOCKUP RESET"]
#[inline(always)]
pub fn lockup_reset(&self) -> LOCKUP_RESET_R {
LOCKUP_RESET_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 10 - LDO_TRIM"]
#[inline(always)]
pub fn ldo_trim(&self) -> LDO_TRIM_R {
LDO_TRIM_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bits 11:13 - FLASH clock trimming"]
#[inline(always)]
pub fn flash_clk_trim(&self) -> FLASH_CLK_TRIM_R {
FLASH_CLK_TRIM_R::new(((self.bits >> 11) & 7) as u8)
}
#[doc = "Bit 14 - Control Register write enable"]
#[inline(always)]
pub fn wr_en(&self) -> WR_EN_R {
WR_EN_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - Control Register write lock"]
#[inline(always)]
pub fn wr_lock(&self) -> WR_LOCK_R {
WR_LOCK_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - OPA Enalbe"]
#[inline(always)]
pub fn opa_en(&self) -> OPA_EN_R {
OPA_EN_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - OPA negative end channel selection"]
#[inline(always)]
pub fn opa_nsel(&self) -> OPA_NSEL_R {
OPA_NSEL_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - OPA positive end channel selection"]
#[inline(always)]
pub fn opa_psel(&self) -> OPA_PSEL_R {
OPA_PSEL_R::new(((self.bits >> 18) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:3 - Configure the PLL clock delay time"]
#[inline(always)]
#[must_use]
pub fn pll_cfg(&mut self) -> PLL_CFG_W<0> {
PLL_CFG_W::new(self)
}
#[doc = "Bit 6 - LOCKUP_Enable"]
#[inline(always)]
#[must_use]
pub fn lockup_en(&mut self) -> LOCKUP_EN_W<6> {
LOCKUP_EN_W::new(self)
}
#[doc = "Bit 7 - LOCKUP RESET"]
#[inline(always)]
#[must_use]
pub fn lockup_reset(&mut self) -> LOCKUP_RESET_W<7> {
LOCKUP_RESET_W::new(self)
}
#[doc = "Bit 10 - LDO_TRIM"]
#[inline(always)]
#[must_use]
pub fn ldo_trim(&mut self) -> LDO_TRIM_W<10> {
LDO_TRIM_W::new(self)
}
#[doc = "Bits 11:13 - FLASH clock trimming"]
#[inline(always)]
#[must_use]
pub fn flash_clk_trim(&mut self) -> FLASH_CLK_TRIM_W<11> {
FLASH_CLK_TRIM_W::new(self)
}
#[doc = "Bit 14 - Control Register write enable"]
#[inline(always)]
#[must_use]
pub fn wr_en(&mut self) -> WR_EN_W<14> {
WR_EN_W::new(self)
}
#[doc = "Bit 15 - Control Register write lock"]
#[inline(always)]
#[must_use]
pub fn wr_lock(&mut self) -> WR_LOCK_W<15> {
WR_LOCK_W::new(self)
}
#[doc = "Bit 16 - OPA Enalbe"]
#[inline(always)]
#[must_use]
pub fn opa_en(&mut self) -> OPA_EN_W<16> {
OPA_EN_W::new(self)
}
#[doc = "Bit 17 - OPA negative end channel selection"]
#[inline(always)]
#[must_use]
pub fn opa_nsel(&mut self) -> OPA_NSEL_W<17> {
OPA_NSEL_W::new(self)
}
#[doc = "Bit 18 - OPA positive end channel selection"]
#[inline(always)]
#[must_use]
pub fn opa_psel(&mut self) -> OPA_PSEL_W<18> {
OPA_PSEL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Configure the extended control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [extend_ctr](index.html) module"]
pub struct EXTEND_CTR_SPEC;
impl crate::RegisterSpec for EXTEND_CTR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [extend_ctr::R](R) reader structure"]
impl crate::Readable for EXTEND_CTR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [extend_ctr::W](W) writer structure"]
impl crate::Writable for EXTEND_CTR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets EXTEND_CTR to value 0x40"]
impl crate::Resettable for EXTEND_CTR_SPEC {
const RESET_VALUE: Self::Ux = 0x40;
}

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ch32v003-pac/src/extend/extend_kr.rs
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#[doc = "Register `EXTEND_KR` writer"]
pub struct W(crate::W<EXTEND_KR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<EXTEND_KR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<EXTEND_KR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<EXTEND_KR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `KEY` writer - Write key value"]
pub type KEY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EXTEND_KR_SPEC, u32, u32, 32, O>;
impl W {
#[doc = "Bits 0:31 - Write key value"]
#[inline(always)]
#[must_use]
pub fn key(&mut self) -> KEY_W<0> {
KEY_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Configure the extended key register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [extend_kr](index.html) module"]
pub struct EXTEND_KR_SPEC;
impl crate::RegisterSpec for EXTEND_KR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [extend_kr::W](W) writer structure"]
impl crate::Writable for EXTEND_KR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets EXTEND_KR to value 0"]
impl crate::Resettable for EXTEND_KR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/exti.rs
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#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Interrupt mask register (EXTI_INTENR)"]
pub intenr: INTENR,
#[doc = "0x04 - Event mask register (EXTI_EVENR)"]
pub evenr: EVENR,
#[doc = "0x08 - Rising Trigger selection register (EXTI_RTENR)"]
pub rtenr: RTENR,
#[doc = "0x0c - Falling Trigger selection register (EXTI_FTENR)"]
pub ftenr: FTENR,
#[doc = "0x10 - Software interrupt event register (EXTI_SWIEVR)"]
pub swievr: SWIEVR,
#[doc = "0x14 - Pending register (EXTI_INTFR)"]
pub intfr: INTFR,
}
#[doc = "INTENR (rw) register accessor: an alias for `Reg<INTENR_SPEC>`"]
pub type INTENR = crate::Reg<intenr::INTENR_SPEC>;
#[doc = "Interrupt mask register (EXTI_INTENR)"]
pub mod intenr;
#[doc = "EVENR (rw) register accessor: an alias for `Reg<EVENR_SPEC>`"]
pub type EVENR = crate::Reg<evenr::EVENR_SPEC>;
#[doc = "Event mask register (EXTI_EVENR)"]
pub mod evenr;
#[doc = "RTENR (rw) register accessor: an alias for `Reg<RTENR_SPEC>`"]
pub type RTENR = crate::Reg<rtenr::RTENR_SPEC>;
#[doc = "Rising Trigger selection register (EXTI_RTENR)"]
pub mod rtenr;
#[doc = "FTENR (rw) register accessor: an alias for `Reg<FTENR_SPEC>`"]
pub type FTENR = crate::Reg<ftenr::FTENR_SPEC>;
#[doc = "Falling Trigger selection register (EXTI_FTENR)"]
pub mod ftenr;
#[doc = "SWIEVR (rw) register accessor: an alias for `Reg<SWIEVR_SPEC>`"]
pub type SWIEVR = crate::Reg<swievr::SWIEVR_SPEC>;
#[doc = "Software interrupt event register (EXTI_SWIEVR)"]
pub mod swievr;
#[doc = "INTFR (rw) register accessor: an alias for `Reg<INTFR_SPEC>`"]
pub type INTFR = crate::Reg<intfr::INTFR_SPEC>;
#[doc = "Pending register (EXTI_INTFR)"]
pub mod intfr;

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ch32v003-pac/src/exti/evenr.rs
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#[doc = "Register `EVENR` reader"]
pub struct R(crate::R<EVENR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<EVENR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<EVENR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<EVENR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `EVENR` writer"]
pub struct W(crate::W<EVENR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<EVENR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<EVENR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<EVENR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `MR0` reader - Event Mask on line 0"]
pub type MR0_R = crate::BitReader<bool>;
#[doc = "Field `MR0` writer - Event Mask on line 0"]
pub type MR0_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVENR_SPEC, bool, O>;
#[doc = "Field `MR1` reader - Event Mask on line 1"]
pub type MR1_R = crate::BitReader<bool>;
#[doc = "Field `MR1` writer - Event Mask on line 1"]
pub type MR1_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVENR_SPEC, bool, O>;
#[doc = "Field `MR2` reader - Event Mask on line 2"]
pub type MR2_R = crate::BitReader<bool>;
#[doc = "Field `MR2` writer - Event Mask on line 2"]
pub type MR2_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVENR_SPEC, bool, O>;
#[doc = "Field `MR3` reader - Event Mask on line 3"]
pub type MR3_R = crate::BitReader<bool>;
#[doc = "Field `MR3` writer - Event Mask on line 3"]
pub type MR3_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVENR_SPEC, bool, O>;
#[doc = "Field `MR4` reader - Event Mask on line 4"]
pub type MR4_R = crate::BitReader<bool>;
#[doc = "Field `MR4` writer - Event Mask on line 4"]
pub type MR4_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVENR_SPEC, bool, O>;
#[doc = "Field `MR5` reader - Event Mask on line 5"]
pub type MR5_R = crate::BitReader<bool>;
#[doc = "Field `MR5` writer - Event Mask on line 5"]
pub type MR5_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVENR_SPEC, bool, O>;
#[doc = "Field `MR6` reader - Event Mask on line 6"]
pub type MR6_R = crate::BitReader<bool>;
#[doc = "Field `MR6` writer - Event Mask on line 6"]
pub type MR6_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVENR_SPEC, bool, O>;
#[doc = "Field `MR7` reader - Event Mask on line 7"]
pub type MR7_R = crate::BitReader<bool>;
#[doc = "Field `MR7` writer - Event Mask on line 7"]
pub type MR7_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVENR_SPEC, bool, O>;
#[doc = "Field `MR8` reader - Event Mask on line 8"]
pub type MR8_R = crate::BitReader<bool>;
#[doc = "Field `MR8` writer - Event Mask on line 8"]
pub type MR8_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVENR_SPEC, bool, O>;
#[doc = "Field `MR9` reader - Event Mask on line 9"]
pub type MR9_R = crate::BitReader<bool>;
#[doc = "Field `MR9` writer - Event Mask on line 9"]
pub type MR9_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVENR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0 - Event Mask on line 0"]
#[inline(always)]
pub fn mr0(&self) -> MR0_R {
MR0_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Event Mask on line 1"]
#[inline(always)]
pub fn mr1(&self) -> MR1_R {
MR1_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Event Mask on line 2"]
#[inline(always)]
pub fn mr2(&self) -> MR2_R {
MR2_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Event Mask on line 3"]
#[inline(always)]
pub fn mr3(&self) -> MR3_R {
MR3_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Event Mask on line 4"]
#[inline(always)]
pub fn mr4(&self) -> MR4_R {
MR4_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Event Mask on line 5"]
#[inline(always)]
pub fn mr5(&self) -> MR5_R {
MR5_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Event Mask on line 6"]
#[inline(always)]
pub fn mr6(&self) -> MR6_R {
MR6_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Event Mask on line 7"]
#[inline(always)]
pub fn mr7(&self) -> MR7_R {
MR7_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Event Mask on line 8"]
#[inline(always)]
pub fn mr8(&self) -> MR8_R {
MR8_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Event Mask on line 9"]
#[inline(always)]
pub fn mr9(&self) -> MR9_R {
MR9_R::new(((self.bits >> 9) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Event Mask on line 0"]
#[inline(always)]
#[must_use]
pub fn mr0(&mut self) -> MR0_W<0> {
MR0_W::new(self)
}
#[doc = "Bit 1 - Event Mask on line 1"]
#[inline(always)]
#[must_use]
pub fn mr1(&mut self) -> MR1_W<1> {
MR1_W::new(self)
}
#[doc = "Bit 2 - Event Mask on line 2"]
#[inline(always)]
#[must_use]
pub fn mr2(&mut self) -> MR2_W<2> {
MR2_W::new(self)
}
#[doc = "Bit 3 - Event Mask on line 3"]
#[inline(always)]
#[must_use]
pub fn mr3(&mut self) -> MR3_W<3> {
MR3_W::new(self)
}
#[doc = "Bit 4 - Event Mask on line 4"]
#[inline(always)]
#[must_use]
pub fn mr4(&mut self) -> MR4_W<4> {
MR4_W::new(self)
}
#[doc = "Bit 5 - Event Mask on line 5"]
#[inline(always)]
#[must_use]
pub fn mr5(&mut self) -> MR5_W<5> {
MR5_W::new(self)
}
#[doc = "Bit 6 - Event Mask on line 6"]
#[inline(always)]
#[must_use]
pub fn mr6(&mut self) -> MR6_W<6> {
MR6_W::new(self)
}
#[doc = "Bit 7 - Event Mask on line 7"]
#[inline(always)]
#[must_use]
pub fn mr7(&mut self) -> MR7_W<7> {
MR7_W::new(self)
}
#[doc = "Bit 8 - Event Mask on line 8"]
#[inline(always)]
#[must_use]
pub fn mr8(&mut self) -> MR8_W<8> {
MR8_W::new(self)
}
#[doc = "Bit 9 - Event Mask on line 9"]
#[inline(always)]
#[must_use]
pub fn mr9(&mut self) -> MR9_W<9> {
MR9_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Event mask register (EXTI_EVENR)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evenr](index.html) module"]
pub struct EVENR_SPEC;
impl crate::RegisterSpec for EVENR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [evenr::R](R) reader structure"]
impl crate::Readable for EVENR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [evenr::W](W) writer structure"]
impl crate::Writable for EVENR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets EVENR to value 0"]
impl crate::Resettable for EVENR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/exti/ftenr.rs
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#[doc = "Register `FTENR` reader"]
pub struct R(crate::R<FTENR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<FTENR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<FTENR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<FTENR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `FTENR` writer"]
pub struct W(crate::W<FTENR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<FTENR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<FTENR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<FTENR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TR0` reader - Falling trigger event configuration of line 0"]
pub type TR0_R = crate::BitReader<bool>;
#[doc = "Field `TR0` writer - Falling trigger event configuration of line 0"]
pub type TR0_W<'a, const O: u8> = crate::BitWriter<'a, u32, FTENR_SPEC, bool, O>;
#[doc = "Field `TR1` reader - Falling trigger event configuration of line 1"]
pub type TR1_R = crate::BitReader<bool>;
#[doc = "Field `TR1` writer - Falling trigger event configuration of line 1"]
pub type TR1_W<'a, const O: u8> = crate::BitWriter<'a, u32, FTENR_SPEC, bool, O>;
#[doc = "Field `TR2` reader - Falling trigger event configuration of line 2"]
pub type TR2_R = crate::BitReader<bool>;
#[doc = "Field `TR2` writer - Falling trigger event configuration of line 2"]
pub type TR2_W<'a, const O: u8> = crate::BitWriter<'a, u32, FTENR_SPEC, bool, O>;
#[doc = "Field `TR3` reader - Falling trigger event configuration of line 3"]
pub type TR3_R = crate::BitReader<bool>;
#[doc = "Field `TR3` writer - Falling trigger event configuration of line 3"]
pub type TR3_W<'a, const O: u8> = crate::BitWriter<'a, u32, FTENR_SPEC, bool, O>;
#[doc = "Field `TR4` reader - Falling trigger event configuration of line 4"]
pub type TR4_R = crate::BitReader<bool>;
#[doc = "Field `TR4` writer - Falling trigger event configuration of line 4"]
pub type TR4_W<'a, const O: u8> = crate::BitWriter<'a, u32, FTENR_SPEC, bool, O>;
#[doc = "Field `TR5` reader - Falling trigger event configuration of line 5"]
pub type TR5_R = crate::BitReader<bool>;
#[doc = "Field `TR5` writer - Falling trigger event configuration of line 5"]
pub type TR5_W<'a, const O: u8> = crate::BitWriter<'a, u32, FTENR_SPEC, bool, O>;
#[doc = "Field `TR6` reader - Falling trigger event configuration of line 6"]
pub type TR6_R = crate::BitReader<bool>;
#[doc = "Field `TR6` writer - Falling trigger event configuration of line 6"]
pub type TR6_W<'a, const O: u8> = crate::BitWriter<'a, u32, FTENR_SPEC, bool, O>;
#[doc = "Field `TR7` reader - Falling trigger event configuration of line 7"]
pub type TR7_R = crate::BitReader<bool>;
#[doc = "Field `TR7` writer - Falling trigger event configuration of line 7"]
pub type TR7_W<'a, const O: u8> = crate::BitWriter<'a, u32, FTENR_SPEC, bool, O>;
#[doc = "Field `TR8` reader - Falling trigger event configuration of line 8"]
pub type TR8_R = crate::BitReader<bool>;
#[doc = "Field `TR8` writer - Falling trigger event configuration of line 8"]
pub type TR8_W<'a, const O: u8> = crate::BitWriter<'a, u32, FTENR_SPEC, bool, O>;
#[doc = "Field `TR9` reader - Falling trigger event configuration of line 9"]
pub type TR9_R = crate::BitReader<bool>;
#[doc = "Field `TR9` writer - Falling trigger event configuration of line 9"]
pub type TR9_W<'a, const O: u8> = crate::BitWriter<'a, u32, FTENR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0 - Falling trigger event configuration of line 0"]
#[inline(always)]
pub fn tr0(&self) -> TR0_R {
TR0_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Falling trigger event configuration of line 1"]
#[inline(always)]
pub fn tr1(&self) -> TR1_R {
TR1_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Falling trigger event configuration of line 2"]
#[inline(always)]
pub fn tr2(&self) -> TR2_R {
TR2_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Falling trigger event configuration of line 3"]
#[inline(always)]
pub fn tr3(&self) -> TR3_R {
TR3_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Falling trigger event configuration of line 4"]
#[inline(always)]
pub fn tr4(&self) -> TR4_R {
TR4_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Falling trigger event configuration of line 5"]
#[inline(always)]
pub fn tr5(&self) -> TR5_R {
TR5_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Falling trigger event configuration of line 6"]
#[inline(always)]
pub fn tr6(&self) -> TR6_R {
TR6_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Falling trigger event configuration of line 7"]
#[inline(always)]
pub fn tr7(&self) -> TR7_R {
TR7_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Falling trigger event configuration of line 8"]
#[inline(always)]
pub fn tr8(&self) -> TR8_R {
TR8_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Falling trigger event configuration of line 9"]
#[inline(always)]
pub fn tr9(&self) -> TR9_R {
TR9_R::new(((self.bits >> 9) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Falling trigger event configuration of line 0"]
#[inline(always)]
#[must_use]
pub fn tr0(&mut self) -> TR0_W<0> {
TR0_W::new(self)
}
#[doc = "Bit 1 - Falling trigger event configuration of line 1"]
#[inline(always)]
#[must_use]
pub fn tr1(&mut self) -> TR1_W<1> {
TR1_W::new(self)
}
#[doc = "Bit 2 - Falling trigger event configuration of line 2"]
#[inline(always)]
#[must_use]
pub fn tr2(&mut self) -> TR2_W<2> {
TR2_W::new(self)
}
#[doc = "Bit 3 - Falling trigger event configuration of line 3"]
#[inline(always)]
#[must_use]
pub fn tr3(&mut self) -> TR3_W<3> {
TR3_W::new(self)
}
#[doc = "Bit 4 - Falling trigger event configuration of line 4"]
#[inline(always)]
#[must_use]
pub fn tr4(&mut self) -> TR4_W<4> {
TR4_W::new(self)
}
#[doc = "Bit 5 - Falling trigger event configuration of line 5"]
#[inline(always)]
#[must_use]
pub fn tr5(&mut self) -> TR5_W<5> {
TR5_W::new(self)
}
#[doc = "Bit 6 - Falling trigger event configuration of line 6"]
#[inline(always)]
#[must_use]
pub fn tr6(&mut self) -> TR6_W<6> {
TR6_W::new(self)
}
#[doc = "Bit 7 - Falling trigger event configuration of line 7"]
#[inline(always)]
#[must_use]
pub fn tr7(&mut self) -> TR7_W<7> {
TR7_W::new(self)
}
#[doc = "Bit 8 - Falling trigger event configuration of line 8"]
#[inline(always)]
#[must_use]
pub fn tr8(&mut self) -> TR8_W<8> {
TR8_W::new(self)
}
#[doc = "Bit 9 - Falling trigger event configuration of line 9"]
#[inline(always)]
#[must_use]
pub fn tr9(&mut self) -> TR9_W<9> {
TR9_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Falling Trigger selection register (EXTI_FTENR)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ftenr](index.html) module"]
pub struct FTENR_SPEC;
impl crate::RegisterSpec for FTENR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ftenr::R](R) reader structure"]
impl crate::Readable for FTENR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ftenr::W](W) writer structure"]
impl crate::Writable for FTENR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets FTENR to value 0"]
impl crate::Resettable for FTENR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/exti/intenr.rs
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#[doc = "Register `INTENR` reader"]
pub struct R(crate::R<INTENR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<INTENR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<INTENR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<INTENR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `INTENR` writer"]
pub struct W(crate::W<INTENR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<INTENR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<INTENR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<INTENR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `MR0` reader - Interrupt Mask on line 0"]
pub type MR0_R = crate::BitReader<bool>;
#[doc = "Field `MR0` writer - Interrupt Mask on line 0"]
pub type MR0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENR_SPEC, bool, O>;
#[doc = "Field `MR1` reader - Interrupt Mask on line 1"]
pub type MR1_R = crate::BitReader<bool>;
#[doc = "Field `MR1` writer - Interrupt Mask on line 1"]
pub type MR1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENR_SPEC, bool, O>;
#[doc = "Field `MR2` reader - Interrupt Mask on line 2"]
pub type MR2_R = crate::BitReader<bool>;
#[doc = "Field `MR2` writer - Interrupt Mask on line 2"]
pub type MR2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENR_SPEC, bool, O>;
#[doc = "Field `MR3` reader - Interrupt Mask on line 3"]
pub type MR3_R = crate::BitReader<bool>;
#[doc = "Field `MR3` writer - Interrupt Mask on line 3"]
pub type MR3_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENR_SPEC, bool, O>;
#[doc = "Field `MR4` reader - Interrupt Mask on line 4"]
pub type MR4_R = crate::BitReader<bool>;
#[doc = "Field `MR4` writer - Interrupt Mask on line 4"]
pub type MR4_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENR_SPEC, bool, O>;
#[doc = "Field `MR5` reader - Interrupt Mask on line 5"]
pub type MR5_R = crate::BitReader<bool>;
#[doc = "Field `MR5` writer - Interrupt Mask on line 5"]
pub type MR5_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENR_SPEC, bool, O>;
#[doc = "Field `MR6` reader - Interrupt Mask on line 6"]
pub type MR6_R = crate::BitReader<bool>;
#[doc = "Field `MR6` writer - Interrupt Mask on line 6"]
pub type MR6_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENR_SPEC, bool, O>;
#[doc = "Field `MR7` reader - Interrupt Mask on line 7"]
pub type MR7_R = crate::BitReader<bool>;
#[doc = "Field `MR7` writer - Interrupt Mask on line 7"]
pub type MR7_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENR_SPEC, bool, O>;
#[doc = "Field `MR8` reader - Interrupt Mask on line 8"]
pub type MR8_R = crate::BitReader<bool>;
#[doc = "Field `MR8` writer - Interrupt Mask on line 8"]
pub type MR8_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENR_SPEC, bool, O>;
#[doc = "Field `MR9` reader - Interrupt Mask on line 9"]
pub type MR9_R = crate::BitReader<bool>;
#[doc = "Field `MR9` writer - Interrupt Mask on line 9"]
pub type MR9_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0 - Interrupt Mask on line 0"]
#[inline(always)]
pub fn mr0(&self) -> MR0_R {
MR0_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Interrupt Mask on line 1"]
#[inline(always)]
pub fn mr1(&self) -> MR1_R {
MR1_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Interrupt Mask on line 2"]
#[inline(always)]
pub fn mr2(&self) -> MR2_R {
MR2_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Interrupt Mask on line 3"]
#[inline(always)]
pub fn mr3(&self) -> MR3_R {
MR3_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Interrupt Mask on line 4"]
#[inline(always)]
pub fn mr4(&self) -> MR4_R {
MR4_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Interrupt Mask on line 5"]
#[inline(always)]
pub fn mr5(&self) -> MR5_R {
MR5_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Interrupt Mask on line 6"]
#[inline(always)]
pub fn mr6(&self) -> MR6_R {
MR6_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Interrupt Mask on line 7"]
#[inline(always)]
pub fn mr7(&self) -> MR7_R {
MR7_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Interrupt Mask on line 8"]
#[inline(always)]
pub fn mr8(&self) -> MR8_R {
MR8_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Interrupt Mask on line 9"]
#[inline(always)]
pub fn mr9(&self) -> MR9_R {
MR9_R::new(((self.bits >> 9) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Interrupt Mask on line 0"]
#[inline(always)]
#[must_use]
pub fn mr0(&mut self) -> MR0_W<0> {
MR0_W::new(self)
}
#[doc = "Bit 1 - Interrupt Mask on line 1"]
#[inline(always)]
#[must_use]
pub fn mr1(&mut self) -> MR1_W<1> {
MR1_W::new(self)
}
#[doc = "Bit 2 - Interrupt Mask on line 2"]
#[inline(always)]
#[must_use]
pub fn mr2(&mut self) -> MR2_W<2> {
MR2_W::new(self)
}
#[doc = "Bit 3 - Interrupt Mask on line 3"]
#[inline(always)]
#[must_use]
pub fn mr3(&mut self) -> MR3_W<3> {
MR3_W::new(self)
}
#[doc = "Bit 4 - Interrupt Mask on line 4"]
#[inline(always)]
#[must_use]
pub fn mr4(&mut self) -> MR4_W<4> {
MR4_W::new(self)
}
#[doc = "Bit 5 - Interrupt Mask on line 5"]
#[inline(always)]
#[must_use]
pub fn mr5(&mut self) -> MR5_W<5> {
MR5_W::new(self)
}
#[doc = "Bit 6 - Interrupt Mask on line 6"]
#[inline(always)]
#[must_use]
pub fn mr6(&mut self) -> MR6_W<6> {
MR6_W::new(self)
}
#[doc = "Bit 7 - Interrupt Mask on line 7"]
#[inline(always)]
#[must_use]
pub fn mr7(&mut self) -> MR7_W<7> {
MR7_W::new(self)
}
#[doc = "Bit 8 - Interrupt Mask on line 8"]
#[inline(always)]
#[must_use]
pub fn mr8(&mut self) -> MR8_W<8> {
MR8_W::new(self)
}
#[doc = "Bit 9 - Interrupt Mask on line 9"]
#[inline(always)]
#[must_use]
pub fn mr9(&mut self) -> MR9_W<9> {
MR9_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Interrupt mask register (EXTI_INTENR)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenr](index.html) module"]
pub struct INTENR_SPEC;
impl crate::RegisterSpec for INTENR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [intenr::R](R) reader structure"]
impl crate::Readable for INTENR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [intenr::W](W) writer structure"]
impl crate::Writable for INTENR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets INTENR to value 0"]
impl crate::Resettable for INTENR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/exti/intfr.rs
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#[doc = "Register `INTFR` reader"]
pub struct R(crate::R<INTFR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<INTFR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<INTFR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<INTFR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `INTFR` writer"]
pub struct W(crate::W<INTFR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<INTFR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<INTFR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<INTFR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PR0` reader - Pending bit 0"]
pub type PR0_R = crate::BitReader<bool>;
#[doc = "Field `PR0` writer - Pending bit 0"]
pub type PR0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFR_SPEC, bool, O>;
#[doc = "Field `PR1` reader - Pending bit 1"]
pub type PR1_R = crate::BitReader<bool>;
#[doc = "Field `PR1` writer - Pending bit 1"]
pub type PR1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFR_SPEC, bool, O>;
#[doc = "Field `PR2` reader - Pending bit 2"]
pub type PR2_R = crate::BitReader<bool>;
#[doc = "Field `PR2` writer - Pending bit 2"]
pub type PR2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFR_SPEC, bool, O>;
#[doc = "Field `PR3` reader - Pending bit 3"]
pub type PR3_R = crate::BitReader<bool>;
#[doc = "Field `PR3` writer - Pending bit 3"]
pub type PR3_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFR_SPEC, bool, O>;
#[doc = "Field `PR4` reader - Pending bit 4"]
pub type PR4_R = crate::BitReader<bool>;
#[doc = "Field `PR4` writer - Pending bit 4"]
pub type PR4_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFR_SPEC, bool, O>;
#[doc = "Field `PR5` reader - Pending bit 5"]
pub type PR5_R = crate::BitReader<bool>;
#[doc = "Field `PR5` writer - Pending bit 5"]
pub type PR5_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFR_SPEC, bool, O>;
#[doc = "Field `PR6` reader - Pending bit 6"]
pub type PR6_R = crate::BitReader<bool>;
#[doc = "Field `PR6` writer - Pending bit 6"]
pub type PR6_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFR_SPEC, bool, O>;
#[doc = "Field `PR7` reader - Pending bit 7"]
pub type PR7_R = crate::BitReader<bool>;
#[doc = "Field `PR7` writer - Pending bit 7"]
pub type PR7_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFR_SPEC, bool, O>;
#[doc = "Field `PR8` reader - Pending bit 8"]
pub type PR8_R = crate::BitReader<bool>;
#[doc = "Field `PR8` writer - Pending bit 8"]
pub type PR8_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFR_SPEC, bool, O>;
#[doc = "Field `PR9` reader - Pending bit 9"]
pub type PR9_R = crate::BitReader<bool>;
#[doc = "Field `PR9` writer - Pending bit 9"]
pub type PR9_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0 - Pending bit 0"]
#[inline(always)]
pub fn pr0(&self) -> PR0_R {
PR0_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Pending bit 1"]
#[inline(always)]
pub fn pr1(&self) -> PR1_R {
PR1_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Pending bit 2"]
#[inline(always)]
pub fn pr2(&self) -> PR2_R {
PR2_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Pending bit 3"]
#[inline(always)]
pub fn pr3(&self) -> PR3_R {
PR3_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Pending bit 4"]
#[inline(always)]
pub fn pr4(&self) -> PR4_R {
PR4_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Pending bit 5"]
#[inline(always)]
pub fn pr5(&self) -> PR5_R {
PR5_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Pending bit 6"]
#[inline(always)]
pub fn pr6(&self) -> PR6_R {
PR6_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Pending bit 7"]
#[inline(always)]
pub fn pr7(&self) -> PR7_R {
PR7_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Pending bit 8"]
#[inline(always)]
pub fn pr8(&self) -> PR8_R {
PR8_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Pending bit 9"]
#[inline(always)]
pub fn pr9(&self) -> PR9_R {
PR9_R::new(((self.bits >> 9) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Pending bit 0"]
#[inline(always)]
#[must_use]
pub fn pr0(&mut self) -> PR0_W<0> {
PR0_W::new(self)
}
#[doc = "Bit 1 - Pending bit 1"]
#[inline(always)]
#[must_use]
pub fn pr1(&mut self) -> PR1_W<1> {
PR1_W::new(self)
}
#[doc = "Bit 2 - Pending bit 2"]
#[inline(always)]
#[must_use]
pub fn pr2(&mut self) -> PR2_W<2> {
PR2_W::new(self)
}
#[doc = "Bit 3 - Pending bit 3"]
#[inline(always)]
#[must_use]
pub fn pr3(&mut self) -> PR3_W<3> {
PR3_W::new(self)
}
#[doc = "Bit 4 - Pending bit 4"]
#[inline(always)]
#[must_use]
pub fn pr4(&mut self) -> PR4_W<4> {
PR4_W::new(self)
}
#[doc = "Bit 5 - Pending bit 5"]
#[inline(always)]
#[must_use]
pub fn pr5(&mut self) -> PR5_W<5> {
PR5_W::new(self)
}
#[doc = "Bit 6 - Pending bit 6"]
#[inline(always)]
#[must_use]
pub fn pr6(&mut self) -> PR6_W<6> {
PR6_W::new(self)
}
#[doc = "Bit 7 - Pending bit 7"]
#[inline(always)]
#[must_use]
pub fn pr7(&mut self) -> PR7_W<7> {
PR7_W::new(self)
}
#[doc = "Bit 8 - Pending bit 8"]
#[inline(always)]
#[must_use]
pub fn pr8(&mut self) -> PR8_W<8> {
PR8_W::new(self)
}
#[doc = "Bit 9 - Pending bit 9"]
#[inline(always)]
#[must_use]
pub fn pr9(&mut self) -> PR9_W<9> {
PR9_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Pending register (EXTI_INTFR)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intfr](index.html) module"]
pub struct INTFR_SPEC;
impl crate::RegisterSpec for INTFR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [intfr::R](R) reader structure"]
impl crate::Readable for INTFR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [intfr::W](W) writer structure"]
impl crate::Writable for INTFR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets INTFR to value 0"]
impl crate::Resettable for INTFR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/exti/rtenr.rs
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#[doc = "Register `RTENR` reader"]
pub struct R(crate::R<RTENR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<RTENR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<RTENR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<RTENR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `RTENR` writer"]
pub struct W(crate::W<RTENR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<RTENR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<RTENR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<RTENR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TR0` reader - Rising trigger event configuration of line 0"]
pub type TR0_R = crate::BitReader<bool>;
#[doc = "Field `TR0` writer - Rising trigger event configuration of line 0"]
pub type TR0_W<'a, const O: u8> = crate::BitWriter<'a, u32, RTENR_SPEC, bool, O>;
#[doc = "Field `TR1` reader - Rising trigger event configuration of line 1"]
pub type TR1_R = crate::BitReader<bool>;
#[doc = "Field `TR1` writer - Rising trigger event configuration of line 1"]
pub type TR1_W<'a, const O: u8> = crate::BitWriter<'a, u32, RTENR_SPEC, bool, O>;
#[doc = "Field `TR2` reader - Rising trigger event configuration of line 2"]
pub type TR2_R = crate::BitReader<bool>;
#[doc = "Field `TR2` writer - Rising trigger event configuration of line 2"]
pub type TR2_W<'a, const O: u8> = crate::BitWriter<'a, u32, RTENR_SPEC, bool, O>;
#[doc = "Field `TR3` reader - Rising trigger event configuration of line 3"]
pub type TR3_R = crate::BitReader<bool>;
#[doc = "Field `TR3` writer - Rising trigger event configuration of line 3"]
pub type TR3_W<'a, const O: u8> = crate::BitWriter<'a, u32, RTENR_SPEC, bool, O>;
#[doc = "Field `TR4` reader - Rising trigger event configuration of line 4"]
pub type TR4_R = crate::BitReader<bool>;
#[doc = "Field `TR4` writer - Rising trigger event configuration of line 4"]
pub type TR4_W<'a, const O: u8> = crate::BitWriter<'a, u32, RTENR_SPEC, bool, O>;
#[doc = "Field `TR5` reader - Rising trigger event configuration of line 5"]
pub type TR5_R = crate::BitReader<bool>;
#[doc = "Field `TR5` writer - Rising trigger event configuration of line 5"]
pub type TR5_W<'a, const O: u8> = crate::BitWriter<'a, u32, RTENR_SPEC, bool, O>;
#[doc = "Field `TR6` reader - Rising trigger event configuration of line 6"]
pub type TR6_R = crate::BitReader<bool>;
#[doc = "Field `TR6` writer - Rising trigger event configuration of line 6"]
pub type TR6_W<'a, const O: u8> = crate::BitWriter<'a, u32, RTENR_SPEC, bool, O>;
#[doc = "Field `TR7` reader - Rising trigger event configuration of line 7"]
pub type TR7_R = crate::BitReader<bool>;
#[doc = "Field `TR7` writer - Rising trigger event configuration of line 7"]
pub type TR7_W<'a, const O: u8> = crate::BitWriter<'a, u32, RTENR_SPEC, bool, O>;
#[doc = "Field `TR8` reader - Rising trigger event configuration of line 8"]
pub type TR8_R = crate::BitReader<bool>;
#[doc = "Field `TR8` writer - Rising trigger event configuration of line 8"]
pub type TR8_W<'a, const O: u8> = crate::BitWriter<'a, u32, RTENR_SPEC, bool, O>;
#[doc = "Field `TR9` reader - Rising trigger event configuration of line 9"]
pub type TR9_R = crate::BitReader<bool>;
#[doc = "Field `TR9` writer - Rising trigger event configuration of line 9"]
pub type TR9_W<'a, const O: u8> = crate::BitWriter<'a, u32, RTENR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0 - Rising trigger event configuration of line 0"]
#[inline(always)]
pub fn tr0(&self) -> TR0_R {
TR0_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Rising trigger event configuration of line 1"]
#[inline(always)]
pub fn tr1(&self) -> TR1_R {
TR1_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Rising trigger event configuration of line 2"]
#[inline(always)]
pub fn tr2(&self) -> TR2_R {
TR2_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Rising trigger event configuration of line 3"]
#[inline(always)]
pub fn tr3(&self) -> TR3_R {
TR3_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Rising trigger event configuration of line 4"]
#[inline(always)]
pub fn tr4(&self) -> TR4_R {
TR4_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Rising trigger event configuration of line 5"]
#[inline(always)]
pub fn tr5(&self) -> TR5_R {
TR5_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Rising trigger event configuration of line 6"]
#[inline(always)]
pub fn tr6(&self) -> TR6_R {
TR6_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Rising trigger event configuration of line 7"]
#[inline(always)]
pub fn tr7(&self) -> TR7_R {
TR7_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Rising trigger event configuration of line 8"]
#[inline(always)]
pub fn tr8(&self) -> TR8_R {
TR8_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Rising trigger event configuration of line 9"]
#[inline(always)]
pub fn tr9(&self) -> TR9_R {
TR9_R::new(((self.bits >> 9) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Rising trigger event configuration of line 0"]
#[inline(always)]
#[must_use]
pub fn tr0(&mut self) -> TR0_W<0> {
TR0_W::new(self)
}
#[doc = "Bit 1 - Rising trigger event configuration of line 1"]
#[inline(always)]
#[must_use]
pub fn tr1(&mut self) -> TR1_W<1> {
TR1_W::new(self)
}
#[doc = "Bit 2 - Rising trigger event configuration of line 2"]
#[inline(always)]
#[must_use]
pub fn tr2(&mut self) -> TR2_W<2> {
TR2_W::new(self)
}
#[doc = "Bit 3 - Rising trigger event configuration of line 3"]
#[inline(always)]
#[must_use]
pub fn tr3(&mut self) -> TR3_W<3> {
TR3_W::new(self)
}
#[doc = "Bit 4 - Rising trigger event configuration of line 4"]
#[inline(always)]
#[must_use]
pub fn tr4(&mut self) -> TR4_W<4> {
TR4_W::new(self)
}
#[doc = "Bit 5 - Rising trigger event configuration of line 5"]
#[inline(always)]
#[must_use]
pub fn tr5(&mut self) -> TR5_W<5> {
TR5_W::new(self)
}
#[doc = "Bit 6 - Rising trigger event configuration of line 6"]
#[inline(always)]
#[must_use]
pub fn tr6(&mut self) -> TR6_W<6> {
TR6_W::new(self)
}
#[doc = "Bit 7 - Rising trigger event configuration of line 7"]
#[inline(always)]
#[must_use]
pub fn tr7(&mut self) -> TR7_W<7> {
TR7_W::new(self)
}
#[doc = "Bit 8 - Rising trigger event configuration of line 8"]
#[inline(always)]
#[must_use]
pub fn tr8(&mut self) -> TR8_W<8> {
TR8_W::new(self)
}
#[doc = "Bit 9 - Rising trigger event configuration of line 9"]
#[inline(always)]
#[must_use]
pub fn tr9(&mut self) -> TR9_W<9> {
TR9_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Rising Trigger selection register (EXTI_RTENR)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rtenr](index.html) module"]
pub struct RTENR_SPEC;
impl crate::RegisterSpec for RTENR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [rtenr::R](R) reader structure"]
impl crate::Readable for RTENR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [rtenr::W](W) writer structure"]
impl crate::Writable for RTENR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets RTENR to value 0"]
impl crate::Resettable for RTENR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/exti/swievr.rs
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#[doc = "Register `SWIEVR` reader"]
pub struct R(crate::R<SWIEVR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SWIEVR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SWIEVR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SWIEVR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SWIEVR` writer"]
pub struct W(crate::W<SWIEVR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SWIEVR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SWIEVR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SWIEVR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SWIER0` reader - Software Interrupt on line 0"]
pub type SWIER0_R = crate::BitReader<bool>;
#[doc = "Field `SWIER0` writer - Software Interrupt on line 0"]
pub type SWIER0_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWIEVR_SPEC, bool, O>;
#[doc = "Field `SWIER1` reader - Software Interrupt on line 1"]
pub type SWIER1_R = crate::BitReader<bool>;
#[doc = "Field `SWIER1` writer - Software Interrupt on line 1"]
pub type SWIER1_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWIEVR_SPEC, bool, O>;
#[doc = "Field `SWIER2` reader - Software Interrupt on line 2"]
pub type SWIER2_R = crate::BitReader<bool>;
#[doc = "Field `SWIER2` writer - Software Interrupt on line 2"]
pub type SWIER2_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWIEVR_SPEC, bool, O>;
#[doc = "Field `SWIER3` reader - Software Interrupt on line 3"]
pub type SWIER3_R = crate::BitReader<bool>;
#[doc = "Field `SWIER3` writer - Software Interrupt on line 3"]
pub type SWIER3_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWIEVR_SPEC, bool, O>;
#[doc = "Field `SWIER4` reader - Software Interrupt on line 4"]
pub type SWIER4_R = crate::BitReader<bool>;
#[doc = "Field `SWIER4` writer - Software Interrupt on line 4"]
pub type SWIER4_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWIEVR_SPEC, bool, O>;
#[doc = "Field `SWIER5` reader - Software Interrupt on line 5"]
pub type SWIER5_R = crate::BitReader<bool>;
#[doc = "Field `SWIER5` writer - Software Interrupt on line 5"]
pub type SWIER5_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWIEVR_SPEC, bool, O>;
#[doc = "Field `SWIER6` reader - Software Interrupt on line 6"]
pub type SWIER6_R = crate::BitReader<bool>;
#[doc = "Field `SWIER6` writer - Software Interrupt on line 6"]
pub type SWIER6_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWIEVR_SPEC, bool, O>;
#[doc = "Field `SWIER7` reader - Software Interrupt on line 7"]
pub type SWIER7_R = crate::BitReader<bool>;
#[doc = "Field `SWIER7` writer - Software Interrupt on line 7"]
pub type SWIER7_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWIEVR_SPEC, bool, O>;
#[doc = "Field `SWIER8` reader - Software Interrupt on line 8"]
pub type SWIER8_R = crate::BitReader<bool>;
#[doc = "Field `SWIER8` writer - Software Interrupt on line 8"]
pub type SWIER8_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWIEVR_SPEC, bool, O>;
#[doc = "Field `SWIER9` reader - Software Interrupt on line 9"]
pub type SWIER9_R = crate::BitReader<bool>;
#[doc = "Field `SWIER9` writer - Software Interrupt on line 9"]
pub type SWIER9_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWIEVR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0 - Software Interrupt on line 0"]
#[inline(always)]
pub fn swier0(&self) -> SWIER0_R {
SWIER0_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Software Interrupt on line 1"]
#[inline(always)]
pub fn swier1(&self) -> SWIER1_R {
SWIER1_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Software Interrupt on line 2"]
#[inline(always)]
pub fn swier2(&self) -> SWIER2_R {
SWIER2_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Software Interrupt on line 3"]
#[inline(always)]
pub fn swier3(&self) -> SWIER3_R {
SWIER3_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Software Interrupt on line 4"]
#[inline(always)]
pub fn swier4(&self) -> SWIER4_R {
SWIER4_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Software Interrupt on line 5"]
#[inline(always)]
pub fn swier5(&self) -> SWIER5_R {
SWIER5_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Software Interrupt on line 6"]
#[inline(always)]
pub fn swier6(&self) -> SWIER6_R {
SWIER6_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Software Interrupt on line 7"]
#[inline(always)]
pub fn swier7(&self) -> SWIER7_R {
SWIER7_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Software Interrupt on line 8"]
#[inline(always)]
pub fn swier8(&self) -> SWIER8_R {
SWIER8_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Software Interrupt on line 9"]
#[inline(always)]
pub fn swier9(&self) -> SWIER9_R {
SWIER9_R::new(((self.bits >> 9) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Software Interrupt on line 0"]
#[inline(always)]
#[must_use]
pub fn swier0(&mut self) -> SWIER0_W<0> {
SWIER0_W::new(self)
}
#[doc = "Bit 1 - Software Interrupt on line 1"]
#[inline(always)]
#[must_use]
pub fn swier1(&mut self) -> SWIER1_W<1> {
SWIER1_W::new(self)
}
#[doc = "Bit 2 - Software Interrupt on line 2"]
#[inline(always)]
#[must_use]
pub fn swier2(&mut self) -> SWIER2_W<2> {
SWIER2_W::new(self)
}
#[doc = "Bit 3 - Software Interrupt on line 3"]
#[inline(always)]
#[must_use]
pub fn swier3(&mut self) -> SWIER3_W<3> {
SWIER3_W::new(self)
}
#[doc = "Bit 4 - Software Interrupt on line 4"]
#[inline(always)]
#[must_use]
pub fn swier4(&mut self) -> SWIER4_W<4> {
SWIER4_W::new(self)
}
#[doc = "Bit 5 - Software Interrupt on line 5"]
#[inline(always)]
#[must_use]
pub fn swier5(&mut self) -> SWIER5_W<5> {
SWIER5_W::new(self)
}
#[doc = "Bit 6 - Software Interrupt on line 6"]
#[inline(always)]
#[must_use]
pub fn swier6(&mut self) -> SWIER6_W<6> {
SWIER6_W::new(self)
}
#[doc = "Bit 7 - Software Interrupt on line 7"]
#[inline(always)]
#[must_use]
pub fn swier7(&mut self) -> SWIER7_W<7> {
SWIER7_W::new(self)
}
#[doc = "Bit 8 - Software Interrupt on line 8"]
#[inline(always)]
#[must_use]
pub fn swier8(&mut self) -> SWIER8_W<8> {
SWIER8_W::new(self)
}
#[doc = "Bit 9 - Software Interrupt on line 9"]
#[inline(always)]
#[must_use]
pub fn swier9(&mut self) -> SWIER9_W<9> {
SWIER9_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Software interrupt event register (EXTI_SWIEVR)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swievr](index.html) module"]
pub struct SWIEVR_SPEC;
impl crate::RegisterSpec for SWIEVR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [swievr::R](R) reader structure"]
impl crate::Readable for SWIEVR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [swievr::W](W) writer structure"]
impl crate::Writable for SWIEVR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SWIEVR to value 0"]
impl crate::Resettable for SWIEVR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/flash.rs
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#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Flash key register"]
pub actlr: ACTLR,
#[doc = "0x04 - Flash key register"]
pub keyr: KEYR,
#[doc = "0x08 - Flash option key register"]
pub obkeyr: OBKEYR,
#[doc = "0x0c - Status register"]
pub statr: STATR,
#[doc = "0x10 - Control register"]
pub ctlr: CTLR,
#[doc = "0x14 - Flash address register"]
pub addr: ADDR,
_reserved6: [u8; 0x04],
#[doc = "0x1c - Option byte register"]
pub obr: OBR,
#[doc = "0x20 - Write protection register"]
pub wpr: WPR,
#[doc = "0x24 - Mode select register"]
pub modekeyr: MODEKEYR,
#[doc = "0x28 - Boot mode key register"]
pub boot_modekeyp: BOOT_MODEKEYP,
}
#[doc = "ACTLR (rw) register accessor: an alias for `Reg<ACTLR_SPEC>`"]
pub type ACTLR = crate::Reg<actlr::ACTLR_SPEC>;
#[doc = "Flash key register"]
pub mod actlr;
#[doc = "KEYR (w) register accessor: an alias for `Reg<KEYR_SPEC>`"]
pub type KEYR = crate::Reg<keyr::KEYR_SPEC>;
#[doc = "Flash key register"]
pub mod keyr;
#[doc = "OBKEYR (w) register accessor: an alias for `Reg<OBKEYR_SPEC>`"]
pub type OBKEYR = crate::Reg<obkeyr::OBKEYR_SPEC>;
#[doc = "Flash option key register"]
pub mod obkeyr;
#[doc = "STATR (rw) register accessor: an alias for `Reg<STATR_SPEC>`"]
pub type STATR = crate::Reg<statr::STATR_SPEC>;
#[doc = "Status register"]
pub mod statr;
#[doc = "CTLR (rw) register accessor: an alias for `Reg<CTLR_SPEC>`"]
pub type CTLR = crate::Reg<ctlr::CTLR_SPEC>;
#[doc = "Control register"]
pub mod ctlr;
#[doc = "ADDR (w) register accessor: an alias for `Reg<ADDR_SPEC>`"]
pub type ADDR = crate::Reg<addr::ADDR_SPEC>;
#[doc = "Flash address register"]
pub mod addr;
#[doc = "OBR (r) register accessor: an alias for `Reg<OBR_SPEC>`"]
pub type OBR = crate::Reg<obr::OBR_SPEC>;
#[doc = "Option byte register"]
pub mod obr;
#[doc = "WPR (r) register accessor: an alias for `Reg<WPR_SPEC>`"]
pub type WPR = crate::Reg<wpr::WPR_SPEC>;
#[doc = "Write protection register"]
pub mod wpr;
#[doc = "MODEKEYR (w) register accessor: an alias for `Reg<MODEKEYR_SPEC>`"]
pub type MODEKEYR = crate::Reg<modekeyr::MODEKEYR_SPEC>;
#[doc = "Mode select register"]
pub mod modekeyr;
#[doc = "BOOT_MODEKEYP (w) register accessor: an alias for `Reg<BOOT_MODEKEYP_SPEC>`"]
pub type BOOT_MODEKEYP = crate::Reg<boot_modekeyp::BOOT_MODEKEYP_SPEC>;
#[doc = "Boot mode key register"]
pub mod boot_modekeyp;

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ch32v003-pac/src/flash/actlr.rs
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#[doc = "Register `ACTLR` reader"]
pub struct R(crate::R<ACTLR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ACTLR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ACTLR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ACTLR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `ACTLR` writer"]
pub struct W(crate::W<ACTLR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<ACTLR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<ACTLR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<ACTLR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `LATENCY` reader - Number of FLASH wait states"]
pub type LATENCY_R = crate::BitReader<bool>;
#[doc = "Field `LATENCY` writer - Number of FLASH wait states"]
pub type LATENCY_W<'a, const O: u8> = crate::BitWriter<'a, u32, ACTLR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0 - Number of FLASH wait states"]
#[inline(always)]
pub fn latency(&self) -> LATENCY_R {
LATENCY_R::new((self.bits & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Number of FLASH wait states"]
#[inline(always)]
#[must_use]
pub fn latency(&mut self) -> LATENCY_W<0> {
LATENCY_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Flash key register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [actlr](index.html) module"]
pub struct ACTLR_SPEC;
impl crate::RegisterSpec for ACTLR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [actlr::R](R) reader structure"]
impl crate::Readable for ACTLR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [actlr::W](W) writer structure"]
impl crate::Writable for ACTLR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets ACTLR to value 0"]
impl crate::Resettable for ACTLR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/flash/addr.rs
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#[doc = "Register `ADDR` writer"]
pub struct W(crate::W<ADDR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<ADDR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<ADDR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<ADDR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `ADDR` writer - Flash Address"]
pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADDR_SPEC, u32, u32, 32, O>;
impl W {
#[doc = "Bits 0:31 - Flash Address"]
#[inline(always)]
#[must_use]
pub fn addr(&mut self) -> ADDR_W<0> {
ADDR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Flash address register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"]
pub struct ADDR_SPEC;
impl crate::RegisterSpec for ADDR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"]
impl crate::Writable for ADDR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets ADDR to value 0"]
impl crate::Resettable for ADDR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/flash/boot_modekeyp.rs
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#[doc = "Register `BOOT_MODEKEYP` writer"]
pub struct W(crate::W<BOOT_MODEKEYP_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<BOOT_MODEKEYP_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<BOOT_MODEKEYP_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<BOOT_MODEKEYP_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `MODEKEYR` writer - Boot mode key"]
pub type MODEKEYR_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, BOOT_MODEKEYP_SPEC, u32, u32, 32, O>;
impl W {
#[doc = "Bits 0:31 - Boot mode key"]
#[inline(always)]
#[must_use]
pub fn modekeyr(&mut self) -> MODEKEYR_W<0> {
MODEKEYR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Boot mode key register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [boot_modekeyp](index.html) module"]
pub struct BOOT_MODEKEYP_SPEC;
impl crate::RegisterSpec for BOOT_MODEKEYP_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [boot_modekeyp::W](W) writer structure"]
impl crate::Writable for BOOT_MODEKEYP_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets BOOT_MODEKEYP to value 0"]
impl crate::Resettable for BOOT_MODEKEYP_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

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ch32v003-pac/src/flash/ctlr.rs
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#[doc = "Register `CTLR` reader"]
pub struct R(crate::R<CTLR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CTLR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CTLR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CTLR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CTLR` writer"]
pub struct W(crate::W<CTLR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CTLR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CTLR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CTLR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PG` reader - Programming"]
pub type PG_R = crate::BitReader<bool>;
#[doc = "Field `PG` writer - Programming"]
pub type PG_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR_SPEC, bool, O>;
#[doc = "Field `PER` reader - Page Erase"]
pub type PER_R = crate::BitReader<bool>;
#[doc = "Field `PER` writer - Page Erase"]
pub type PER_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR_SPEC, bool, O>;
#[doc = "Field `MER` reader - Mass Erase"]
pub type MER_R = crate::BitReader<bool>;
#[doc = "Field `MER` writer - Mass Erase"]
pub type MER_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR_SPEC, bool, O>;
#[doc = "Field `OBPG` reader - Option byte programming"]
pub type OBPG_R = crate::BitReader<bool>;
#[doc = "Field `OBPG` writer - Option byte programming"]
pub type OBPG_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR_SPEC, bool, O>;
#[doc = "Field `OBER` reader - Option byte erase"]
pub type OBER_R = crate::BitReader<bool>;
#[doc = "Field `OBER` writer - Option byte erase"]
pub type OBER_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR_SPEC, bool, O>;
#[doc = "Field `STRT` reader - Start"]
pub type STRT_R = crate::BitReader<bool>;
#[doc = "Field `STRT` writer - Start"]
pub type STRT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR_SPEC, bool, O>;
#[doc = "Field `LOCK` reader - Lock"]
pub type LOCK_R = crate::BitReader<bool>;
#[doc = "Field `LOCK` writer - Lock"]
pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR_SPEC, bool, O>;
#[doc = "Field `OBWRE` reader - Option bytes write enable"]
pub type OBWRE_R = crate::BitReader<bool>;
#[doc = "Field `OBWRE` writer - Option bytes write enable"]
pub type OBWRE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR_SPEC, bool, O>;
#[doc = "Field `ERRIE` reader - Error interrupt enable"]
pub type ERRIE_R = crate::BitReader<bool>;
#[doc = "Field `ERRIE` writer - Error interrupt enable"]
pub type ERRIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR_SPEC, bool, O>;
#[doc = "Field `EOPIE` reader - End of operation interrupt enable"]
pub type EOPIE_R = crate::BitReader<bool>;
#[doc = "Field `EOPIE` writer - End of operation interrupt enable"]
pub type EOPIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR_SPEC, bool, O>;
#[doc = "Field `FLOCK` reader - Fast programmable lock"]
pub type FLOCK_R = crate::BitReader<bool>;
#[doc = "Field `FLOCK` writer - Fast programmable lock"]
pub type FLOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR_SPEC, bool, O>;
#[doc = "Field `PAGE_PG` reader - Fast programming"]
pub type PAGE_PG_R = crate::BitReader<bool>;
#[doc = "Field `PAGE_PG` writer - Fast programming"]
pub type PAGE_PG_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR_SPEC, bool, O>;
#[doc = "Field `PAGE_ER` reader - Fast erase"]
pub type PAGE_ER_R = crate::BitReader<bool>;
#[doc = "Field `PAGE_ER` writer - Fast erase"]
pub type PAGE_ER_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR_SPEC, bool, O>;
#[doc = "Field `BUFLOAD` reader - Buffer load"]
pub type BUFLOAD_R = crate::BitReader<bool>;
#[doc = "Field `BUFLOAD` writer - Buffer load"]
pub type BUFLOAD_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR_SPEC, bool, O>;
#[doc = "Field `BUFRST` reader - Buffer reset"]
pub type BUFRST_R = crate::BitReader<bool>;
#[doc = "Field `BUFRST` writer - Buffer reset"]
pub type BUFRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTLR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0 - Programming"]
#[inline(always)]
pub fn pg(&self) -> PG_R {
PG_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Page Erase"]
#[inline(always)]
pub fn per(&self) -> PER_R {
PER_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Mass Erase"]
#[inline(always)]
pub fn mer(&self) -> MER_R {
MER_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 4 - Option byte programming"]
#[inline(always)]
pub fn obpg(&self) -> OBPG_R {
OBPG_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Option byte erase"]
#[inline(always)]
pub fn ober(&self) -> OBER_R {
OBER_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Start"]
#[inline(always)]
pub fn strt(&self) -> STRT_R {
STRT_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Lock"]
#[inline(always)]
pub fn lock(&self) -> LOCK_R {
LOCK_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 9 - Option bytes write enable"]
#[inline(always)]
pub fn obwre(&self) -> OBWRE_R {
OBWRE_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Error interrupt enable"]
#[inline(always)]
pub fn errie(&self) -> ERRIE_R {
ERRIE_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 12 - End of operation interrupt enable"]
#[inline(always)]
pub fn eopie(&self) -> EOPIE_R {
EOPIE_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 15 - Fast programmable lock"]
#[inline(always)]
pub fn flock(&self) -> FLOCK_R {
FLOCK_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - Fast programming"]
#[inline(always)]
pub fn page_pg(&self) -> PAGE_PG_R {
PAGE_PG_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - Fast erase"]
#[inline(always)]
pub fn page_er(&self) -> PAGE_ER_R {
PAGE_ER_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - Buffer load"]
#[inline(always)]
pub fn bufload(&self) -> BUFLOAD_R {
BUFLOAD_R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - Buffer reset"]
#[inline(always)]
pub fn bufrst(&self) -> BUFRST_R {
BUFRST_R::new(((self.bits >> 19) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Programming"]
#[inline(always)]
#[must_use]
pub fn pg(&mut self) -> PG_W<0> {
PG_W::new(self)
}
#[doc = "Bit 1 - Page Erase"]
#[inline(always)]
#[must_use]
pub fn per(&mut self) -> PER_W<1> {
PER_W::new(self)
}
#[doc = "Bit 2 - Mass Erase"]
#[inline(always)]
#[must_use]
pub fn mer(&mut self) -> MER_W<2> {
MER_W::new(self)
}
#[doc = "Bit 4 - Option byte programming"]
#[inline(always)]
#[must_use]
pub fn obpg(&mut self) -> OBPG_W<4> {
OBPG_W::new(self)
}
#[doc = "Bit 5 - Option byte erase"]
#[inline(always)]
#[must_use]
pub fn ober(&mut self) -> OBER_W<5> {
OBER_W::new(self)
}
#[doc = "Bit 6 - Start"]
#[inline(always)]
#[must_use]
pub fn strt(&mut self) -> STRT_W<6> {
STRT_W::new(self)
}
#[doc = "Bit 7 - Lock"]
#[inline(always)]
#[must_use]
pub fn lock(&mut self) -> LOCK_W<7> {
LOCK_W::new(self)
}
#[doc = "Bit 9 - Option bytes write enable"]
#[inline(always)]
#[must_use]
pub fn obwre(&mut self) -> OBWRE_W<9> {
OBWRE_W::new(self)
}
#[doc = "Bit 10 - Error interrupt enable"]
#[inline(always)]
#[must_use]
pub fn errie(&mut self) -> ERRIE_W<10> {
ERRIE_W::new(self)
}
#[doc = "Bit 12 - End of operation interrupt enable"]
#[inline(always)]
#[must_use]
pub fn eopie(&mut self) -> EOPIE_W<12> {
EOPIE_W::new(self)
}
#[doc = "Bit 15 - Fast programmable lock"]
#[inline(always)]
#[must_use]
pub fn flock(&mut self) -> FLOCK_W<15> {
FLOCK_W::new(self)
}
#[doc = "Bit 16 - Fast programming"]
#[inline(always)]
#[must_use]
pub fn page_pg(&mut self) -> PAGE_PG_W<16> {
PAGE_PG_W::new(self)
}
#[doc = "Bit 17 - Fast erase"]
#[inline(always)]
#[must_use]
pub fn page_er(&mut self) -> PAGE_ER_W<17> {
PAGE_ER_W::new(self)
}
#[doc = "Bit 18 - Buffer load"]
#[inline(always)]
#[must_use]
pub fn bufload(&mut self) -> BUFLOAD_W<18> {
BUFLOAD_W::new(self)
}
#[doc = "Bit 19 - Buffer reset"]
#[inline(always)]
#[must_use]
pub fn bufrst(&mut self) -> BUFRST_W<19> {
BUFRST_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctlr](index.html) module"]
pub struct CTLR_SPEC;
impl crate::RegisterSpec for CTLR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ctlr::R](R) reader structure"]
impl crate::Readable for CTLR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ctlr::W](W) writer structure"]
impl crate::Writable for CTLR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CTLR to value 0x8080"]
impl crate::Resettable for CTLR_SPEC {
const RESET_VALUE: Self::Ux = 0x8080;
}

52
ch32v003-pac/src/flash/keyr.rs
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#[doc = "Register `KEYR` writer"]
pub struct W(crate::W<KEYR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<KEYR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<KEYR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<KEYR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `KEYR` writer - FPEC key"]
pub type KEYR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, KEYR_SPEC, u32, u32, 32, O>;
impl W {
#[doc = "Bits 0:31 - FPEC key"]
#[inline(always)]
#[must_use]
pub fn keyr(&mut self) -> KEYR_W<0> {
KEYR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Flash key register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [keyr](index.html) module"]
pub struct KEYR_SPEC;
impl crate::RegisterSpec for KEYR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [keyr::W](W) writer structure"]
impl crate::Writable for KEYR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets KEYR to value 0"]
impl crate::Resettable for KEYR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

52
ch32v003-pac/src/flash/modekeyr.rs
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#[doc = "Register `MODEKEYR` writer"]
pub struct W(crate::W<MODEKEYR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MODEKEYR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MODEKEYR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MODEKEYR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `MODEKEYR` writer - Mode select"]
pub type MODEKEYR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MODEKEYR_SPEC, u32, u32, 32, O>;
impl W {
#[doc = "Bits 0:31 - Mode select"]
#[inline(always)]
#[must_use]
pub fn modekeyr(&mut self) -> MODEKEYR_W<0> {
MODEKEYR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Mode select register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [modekeyr](index.html) module"]
pub struct MODEKEYR_SPEC;
impl crate::RegisterSpec for MODEKEYR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [modekeyr::W](W) writer structure"]
impl crate::Writable for MODEKEYR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets MODEKEYR to value 0"]
impl crate::Resettable for MODEKEYR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

52
ch32v003-pac/src/flash/obkeyr.rs
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#[doc = "Register `OBKEYR` writer"]
pub struct W(crate::W<OBKEYR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<OBKEYR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<OBKEYR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<OBKEYR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `OPTKEY` writer - Option byte key"]
pub type OPTKEY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OBKEYR_SPEC, u32, u32, 32, O>;
impl W {
#[doc = "Bits 0:31 - Option byte key"]
#[inline(always)]
#[must_use]
pub fn optkey(&mut self) -> OPTKEY_W<0> {
OPTKEY_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Flash option key register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [obkeyr](index.html) module"]
pub struct OBKEYR_SPEC;
impl crate::RegisterSpec for OBKEYR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [obkeyr::W](W) writer structure"]
impl crate::Writable for OBKEYR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets OBKEYR to value 0"]
impl crate::Resettable for OBKEYR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}

86
ch32v003-pac/src/flash/obr.rs
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#[doc = "Register `OBR` reader"]
pub struct R(crate::R<OBR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<OBR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<OBR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<OBR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `OBERR` reader - Option byte error"]
pub type OBERR_R = crate::BitReader<bool>;
#[doc = "Field `RDPRT` reader - Read protection"]
pub type RDPRT_R = crate::BitReader<bool>;
#[doc = "Field `IWDG_SW` reader - IWDG_SW"]
pub type IWDG_SW_R = crate::BitReader<bool>;
#[doc = "Field `STOP_RST` reader - STOP_RST"]
pub type STOP_RST_R = crate::BitReader<bool>;
#[doc = "Field `STANDY_RST` reader - STANDY_RST"]
pub type STANDY_RST_R = crate::BitReader<bool>;
#[doc = "Field `CFG_RST_MODE` reader - CFG_RST_MODE"]
pub type CFG_RST_MODE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `DATA0` reader - DATA0"]
pub type DATA0_R = crate::FieldReader<u8, u8>;
#[doc = "Field `DATA1` reader - DATA1"]
pub type DATA1_R = crate::FieldReader<u8, u8>;
impl R {
#[doc = "Bit 0 - Option byte error"]
#[inline(always)]
pub fn oberr(&self) -> OBERR_R {
OBERR_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Read protection"]
#[inline(always)]
pub fn rdprt(&self) -> RDPRT_R {
RDPRT_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - IWDG_SW"]
#[inline(always)]
pub fn iwdg_sw(&self) -> IWDG_SW_R {
IWDG_SW_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - STOP_RST"]
#[inline(always)]
pub fn stop_rst(&self) -> STOP_RST_R {
STOP_RST_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - STANDY_RST"]
#[inline(always)]
pub fn standy_rst(&self) -> STANDY_RST_R {
STANDY_RST_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:6 - CFG_RST_MODE"]
#[inline(always)]
pub fn cfg_rst_mode(&self) -> CFG_RST_MODE_R {
CFG_RST_MODE_R::new(((self.bits >> 5) & 3) as u8)
}
#[doc = "Bits 10:17 - DATA0"]
#[inline(always)]
pub fn data0(&self) -> DATA0_R {
DATA0_R::new(((self.bits >> 10) & 0xff) as u8)
}
#[doc = "Bits 18:25 - DATA1"]
#[inline(always)]
pub fn data1(&self) -> DATA1_R {
DATA1_R::new(((self.bits >> 18) & 0xff) as u8)
}
}
#[doc = "Option byte register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [obr](index.html) module"]
pub struct OBR_SPEC;
impl crate::RegisterSpec for OBR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [obr::R](R) reader structure"]
impl crate::Readable for OBR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets OBR to value 0x03ff_fffe"]
impl crate::Resettable for OBR_SPEC {
const RESET_VALUE: Self::Ux = 0x03ff_fffe;
}

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