{ "version": "0.1.0", "types": { "peripherals": { "GPIOA": { "description": "General-purpose I/Os", "children": { "registers": { "MODER": { "description": "GPIO port mode register", "offset": 0, "size": 32, "reset_value": 671088640, "reset_mask": 4294967295, "children": { "fields": { "MODER15": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 30, "size": 2 }, "MODER14": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 28, "size": 2 }, "MODER13": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 26, "size": 2 }, "MODER12": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 24, "size": 2 }, "MODER11": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 22, "size": 2 }, "MODER10": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 20, "size": 2 }, "MODER9": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 18, "size": 2 }, "MODER8": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 16, "size": 2 }, "MODER7": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 14, "size": 2 }, "MODER6": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 12, "size": 2 }, "MODER5": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 10, "size": 2 }, "MODER4": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 8, "size": 2 }, "MODER3": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 6, "size": 2 }, "MODER2": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 4, "size": 2 }, "MODER1": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 2, "size": 2 }, "MODER0": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 0, "size": 2 } } } }, "OTYPER": { "description": "GPIO port output type register", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "OT15": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 15, "size": 1 }, "OT14": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 14, "size": 1 }, "OT13": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 13, "size": 1 }, "OT12": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 12, "size": 1 }, "OT11": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 11, "size": 1 }, "OT10": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 10, "size": 1 }, "OT9": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 9, "size": 1 }, "OT8": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 8, "size": 1 }, "OT7": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 7, "size": 1 }, "OT6": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 6, "size": 1 }, "OT5": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 5, "size": 1 }, "OT4": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 4, "size": 1 }, "OT3": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 3, "size": 1 }, "OT2": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 2, "size": 1 }, "OT1": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 1, "size": 1 }, "OT0": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 0, "size": 1 } } } }, "OSPEEDR": { "description": "GPIO port output speed\n register", "offset": 8, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "OSPEEDR15": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 30, "size": 2 }, "OSPEEDR14": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 28, "size": 2 }, "OSPEEDR13": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 26, "size": 2 }, "OSPEEDR12": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 24, "size": 2 }, "OSPEEDR11": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 22, "size": 2 }, "OSPEEDR10": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 20, "size": 2 }, "OSPEEDR9": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 18, "size": 2 }, "OSPEEDR8": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 16, "size": 2 }, "OSPEEDR7": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 14, "size": 2 }, "OSPEEDR6": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 12, "size": 2 }, "OSPEEDR5": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 10, "size": 2 }, "OSPEEDR4": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 8, "size": 2 }, "OSPEEDR3": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 6, "size": 2 }, "OSPEEDR2": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 4, "size": 2 }, "OSPEEDR1": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 2, "size": 2 }, "OSPEEDR0": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 0, "size": 2 } } } }, "PUPDR": { "description": "GPIO port pull-up/pull-down\n register", "offset": 12, "size": 32, "reset_value": 603979776, "reset_mask": 4294967295, "children": { "fields": { "PUPDR15": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 30, "size": 2 }, "PUPDR14": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 28, "size": 2 }, "PUPDR13": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 26, "size": 2 }, "PUPDR12": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 24, "size": 2 }, "PUPDR11": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 22, "size": 2 }, "PUPDR10": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 20, "size": 2 }, "PUPDR9": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 18, "size": 2 }, "PUPDR8": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 16, "size": 2 }, "PUPDR7": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 14, "size": 2 }, "PUPDR6": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 12, "size": 2 }, "PUPDR5": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 10, "size": 2 }, "PUPDR4": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 8, "size": 2 }, "PUPDR3": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 6, "size": 2 }, "PUPDR2": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 4, "size": 2 }, "PUPDR1": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 2, "size": 2 }, "PUPDR0": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 0, "size": 2 } } } }, "IDR": { "description": "GPIO port input data register", "offset": 16, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "IDR15": { "description": "Port input data (y =\n 0..15)", "offset": 15, "size": 1 }, "IDR14": { "description": "Port input data (y =\n 0..15)", "offset": 14, "size": 1 }, "IDR13": { "description": "Port input data (y =\n 0..15)", "offset": 13, "size": 1 }, "IDR12": { "description": "Port input data (y =\n 0..15)", "offset": 12, "size": 1 }, "IDR11": { "description": "Port input data (y =\n 0..15)", "offset": 11, "size": 1 }, "IDR10": { "description": "Port input data (y =\n 0..15)", "offset": 10, "size": 1 }, "IDR9": { "description": "Port input data (y =\n 0..15)", "offset": 9, "size": 1 }, "IDR8": { "description": "Port input data (y =\n 0..15)", "offset": 8, "size": 1 }, "IDR7": { "description": "Port input data (y =\n 0..15)", "offset": 7, "size": 1 }, "IDR6": { "description": "Port input data (y =\n 0..15)", "offset": 6, "size": 1 }, "IDR5": { "description": "Port input data (y =\n 0..15)", "offset": 5, "size": 1 }, "IDR4": { "description": "Port input data (y =\n 0..15)", "offset": 4, "size": 1 }, "IDR3": { "description": "Port input data (y =\n 0..15)", "offset": 3, "size": 1 }, "IDR2": { "description": "Port input data (y =\n 0..15)", "offset": 2, "size": 1 }, "IDR1": { "description": "Port input data (y =\n 0..15)", "offset": 1, "size": 1 }, "IDR0": { "description": "Port input data (y =\n 0..15)", "offset": 0, "size": 1 } } } }, "ODR": { "description": "GPIO port output data register", "offset": 20, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "ODR15": { "description": "Port output data (y =\n 0..15)", "offset": 15, "size": 1 }, "ODR14": { "description": "Port output data (y =\n 0..15)", "offset": 14, "size": 1 }, "ODR13": { "description": "Port output data (y =\n 0..15)", "offset": 13, "size": 1 }, "ODR12": { "description": "Port output data (y =\n 0..15)", "offset": 12, "size": 1 }, "ODR11": { "description": "Port output data (y =\n 0..15)", "offset": 11, "size": 1 }, "ODR10": { "description": "Port output data (y =\n 0..15)", "offset": 10, "size": 1 }, "ODR9": { "description": "Port output data (y =\n 0..15)", "offset": 9, "size": 1 }, "ODR8": { "description": "Port output data (y =\n 0..15)", "offset": 8, "size": 1 }, "ODR7": { "description": "Port output data (y =\n 0..15)", "offset": 7, "size": 1 }, "ODR6": { "description": "Port output data (y =\n 0..15)", "offset": 6, "size": 1 }, "ODR5": { "description": "Port output data (y =\n 0..15)", "offset": 5, "size": 1 }, "ODR4": { "description": "Port output data (y =\n 0..15)", "offset": 4, "size": 1 }, "ODR3": { "description": "Port output data (y =\n 0..15)", "offset": 3, "size": 1 }, "ODR2": { "description": "Port output data (y =\n 0..15)", "offset": 2, "size": 1 }, "ODR1": { "description": "Port output data (y =\n 0..15)", "offset": 1, "size": 1 }, "ODR0": { "description": "Port output data (y =\n 0..15)", "offset": 0, "size": 1 } } } }, "BSRR": { "description": "GPIO port bit set/reset\n register", "offset": 24, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "write-only", "children": { "fields": { "BR15": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 31, "size": 1 }, "BR14": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 30, "size": 1 }, "BR13": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 29, "size": 1 }, "BR12": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 28, "size": 1 }, "BR11": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 27, "size": 1 }, "BR10": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 26, "size": 1 }, "BR9": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 25, "size": 1 }, "BR8": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 24, "size": 1 }, "BR7": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 23, "size": 1 }, "BR6": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 22, "size": 1 }, "BR5": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 21, "size": 1 }, "BR4": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 20, "size": 1 }, "BR3": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 19, "size": 1 }, "BR2": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 18, "size": 1 }, "BR1": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 17, "size": 1 }, "BR0": { "description": "Port x set bit y (y=\n 0..15)", "offset": 16, "size": 1 }, "BS15": { "description": "Port x set bit y (y=\n 0..15)", "offset": 15, "size": 1 }, "BS14": { "description": "Port x set bit y (y=\n 0..15)", "offset": 14, "size": 1 }, "BS13": { "description": "Port x set bit y (y=\n 0..15)", "offset": 13, "size": 1 }, "BS12": { "description": "Port x set bit y (y=\n 0..15)", "offset": 12, "size": 1 }, "BS11": { "description": "Port x set bit y (y=\n 0..15)", "offset": 11, "size": 1 }, "BS10": { "description": "Port x set bit y (y=\n 0..15)", "offset": 10, "size": 1 }, "BS9": { "description": "Port x set bit y (y=\n 0..15)", "offset": 9, "size": 1 }, "BS8": { "description": "Port x set bit y (y=\n 0..15)", "offset": 8, "size": 1 }, "BS7": { "description": "Port x set bit y (y=\n 0..15)", "offset": 7, "size": 1 }, "BS6": { "description": "Port x set bit y (y=\n 0..15)", "offset": 6, "size": 1 }, "BS5": { "description": "Port x set bit y (y=\n 0..15)", "offset": 5, "size": 1 }, "BS4": { "description": "Port x set bit y (y=\n 0..15)", "offset": 4, "size": 1 }, "BS3": { "description": "Port x set bit y (y=\n 0..15)", "offset": 3, "size": 1 }, "BS2": { "description": "Port x set bit y (y=\n 0..15)", "offset": 2, "size": 1 }, "BS1": { "description": "Port x set bit y (y=\n 0..15)", "offset": 1, "size": 1 }, "BS0": { "description": "Port x set bit y (y=\n 0..15)", "offset": 0, "size": 1 } } } }, "LCKR": { "description": "GPIO port configuration lock\n register", "offset": 28, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "LCKK": { "description": "Lok Key", "offset": 16, "size": 1 }, "LCK15": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 15, "size": 1 }, "LCK14": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 14, "size": 1 }, "LCK13": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 13, "size": 1 }, "LCK12": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 12, "size": 1 }, "LCK11": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 11, "size": 1 }, "LCK10": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 10, "size": 1 }, "LCK9": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 9, "size": 1 }, "LCK8": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 8, "size": 1 }, "LCK7": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 7, "size": 1 }, "LCK6": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 6, "size": 1 }, "LCK5": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 5, "size": 1 }, "LCK4": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 4, "size": 1 }, "LCK3": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 3, "size": 1 }, "LCK2": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 2, "size": 1 }, "LCK1": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 1, "size": 1 }, "LCK0": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 0, "size": 1 } } } }, "AFRL": { "description": "GPIO alternate function low\n register", "offset": 32, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "AFRL7": { "description": "Alternate function selection for port x\n bit y (y = 0..7)", "offset": 28, "size": 4 }, "AFRL6": { "description": "Alternate function selection for port x\n bit y (y = 0..7)", "offset": 24, "size": 4 }, "AFRL5": { "description": "Alternate function selection for port x\n bit y (y = 0..7)", "offset": 20, "size": 4 }, "AFRL4": { "description": "Alternate function selection for port x\n bit y (y = 0..7)", "offset": 16, "size": 4 }, "AFRL3": { "description": "Alternate function selection for port x\n bit y (y = 0..7)", "offset": 12, "size": 4 }, "AFRL2": { "description": "Alternate function selection for port x\n bit y (y = 0..7)", "offset": 8, "size": 4 }, "AFRL1": { "description": "Alternate function selection for port x\n bit y (y = 0..7)", "offset": 4, "size": 4 }, "AFRL0": { "description": "Alternate function selection for port x\n bit y (y = 0..7)", "offset": 0, "size": 4 } } } }, "AFRH": { "description": "GPIO alternate function high\n register", "offset": 36, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "AFRH15": { "description": "Alternate function selection for port x\n bit y (y = 8..15)", "offset": 28, "size": 4 }, "AFRH14": { "description": "Alternate function selection for port x\n bit y (y = 8..15)", "offset": 24, "size": 4 }, "AFRH13": { "description": "Alternate function selection for port x\n bit y (y = 8..15)", "offset": 20, "size": 4 }, "AFRH12": { "description": "Alternate function selection for port x\n bit y (y = 8..15)", "offset": 16, "size": 4 }, "AFRH11": { "description": "Alternate function selection for port x\n bit y (y = 8..15)", "offset": 12, "size": 4 }, "AFRH10": { "description": "Alternate function selection for port x\n bit y (y = 8..15)", "offset": 8, "size": 4 }, "AFRH9": { "description": "Alternate function selection for port x\n bit y (y = 8..15)", "offset": 4, "size": 4 }, "AFRH8": { "description": "Alternate function selection for port x\n bit y (y = 8..15)", "offset": 0, "size": 4 } } } }, "BRR": { "description": "Port bit reset register", "offset": 40, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "write-only", "children": { "fields": { "BR0": { "description": "Port x Reset bit y", "offset": 0, "size": 1 }, "BR1": { "description": "Port x Reset bit y", "offset": 1, "size": 1 }, "BR2": { "description": "Port x Reset bit y", "offset": 2, "size": 1 }, "BR3": { "description": "Port x Reset bit y", "offset": 3, "size": 1 }, "BR4": { "description": "Port x Reset bit y", "offset": 4, "size": 1 }, "BR5": { "description": "Port x Reset bit y", "offset": 5, "size": 1 }, "BR6": { "description": "Port x Reset bit y", "offset": 6, "size": 1 }, "BR7": { "description": "Port x Reset bit y", "offset": 7, "size": 1 }, "BR8": { "description": "Port x Reset bit y", "offset": 8, "size": 1 }, "BR9": { "description": "Port x Reset bit y", "offset": 9, "size": 1 }, "BR10": { "description": "Port x Reset bit y", "offset": 10, "size": 1 }, "BR11": { "description": "Port x Reset bit y", "offset": 11, "size": 1 }, "BR12": { "description": "Port x Reset bit y", "offset": 12, "size": 1 }, "BR13": { "description": "Port x Reset bit y", "offset": 13, "size": 1 }, "BR14": { "description": "Port x Reset bit y", "offset": 14, "size": 1 }, "BR15": { "description": "Port x Reset bit y", "offset": 15, "size": 1 } } } } } } }, "GPIOB": { "description": "General-purpose I/Os", "children": { "registers": { "MODER": { "description": "GPIO port mode register", "offset": 0, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "MODER15": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 30, "size": 2 }, "MODER14": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 28, "size": 2 }, "MODER13": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 26, "size": 2 }, "MODER12": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 24, "size": 2 }, "MODER11": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 22, "size": 2 }, "MODER10": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 20, "size": 2 }, "MODER9": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 18, "size": 2 }, "MODER8": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 16, "size": 2 }, "MODER7": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 14, "size": 2 }, "MODER6": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 12, "size": 2 }, "MODER5": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 10, "size": 2 }, "MODER4": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 8, "size": 2 }, "MODER3": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 6, "size": 2 }, "MODER2": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 4, "size": 2 }, "MODER1": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 2, "size": 2 }, "MODER0": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 0, "size": 2 } } } }, "OTYPER": { "description": "GPIO port output type register", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "OT15": { "description": "Port x configuration bit\n 15", "offset": 15, "size": 1 }, "OT14": { "description": "Port x configuration bit\n 14", "offset": 14, "size": 1 }, "OT13": { "description": "Port x configuration bit\n 13", "offset": 13, "size": 1 }, "OT12": { "description": "Port x configuration bit\n 12", "offset": 12, "size": 1 }, "OT11": { "description": "Port x configuration bit\n 11", "offset": 11, "size": 1 }, "OT10": { "description": "Port x configuration bit\n 10", "offset": 10, "size": 1 }, "OT9": { "description": "Port x configuration bit 9", "offset": 9, "size": 1 }, "OT8": { "description": "Port x configuration bit 8", "offset": 8, "size": 1 }, "OT7": { "description": "Port x configuration bit 7", "offset": 7, "size": 1 }, "OT6": { "description": "Port x configuration bit 6", "offset": 6, "size": 1 }, "OT5": { "description": "Port x configuration bit 5", "offset": 5, "size": 1 }, "OT4": { "description": "Port x configuration bit 4", "offset": 4, "size": 1 }, "OT3": { "description": "Port x configuration bit 3", "offset": 3, "size": 1 }, "OT2": { "description": "Port x configuration bit 2", "offset": 2, "size": 1 }, "OT1": { "description": "Port x configuration bit 1", "offset": 1, "size": 1 }, "OT0": { "description": "Port x configuration bit 0", "offset": 0, "size": 1 } } } }, "OSPEEDR": { "description": "GPIO port output speed\n register", "offset": 8, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "OSPEEDR15": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 30, "size": 2 }, "OSPEEDR14": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 28, "size": 2 }, "OSPEEDR13": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 26, "size": 2 }, "OSPEEDR12": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 24, "size": 2 }, "OSPEEDR11": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 22, "size": 2 }, "OSPEEDR10": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 20, "size": 2 }, "OSPEEDR9": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 18, "size": 2 }, "OSPEEDR8": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 16, "size": 2 }, "OSPEEDR7": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 14, "size": 2 }, "OSPEEDR6": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 12, "size": 2 }, "OSPEEDR5": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 10, "size": 2 }, "OSPEEDR4": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 8, "size": 2 }, "OSPEEDR3": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 6, "size": 2 }, "OSPEEDR2": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 4, "size": 2 }, "OSPEEDR1": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 2, "size": 2 }, "OSPEEDR0": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 0, "size": 2 } } } }, "PUPDR": { "description": "GPIO port pull-up/pull-down\n register", "offset": 12, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "PUPDR15": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 30, "size": 2 }, "PUPDR14": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 28, "size": 2 }, "PUPDR13": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 26, "size": 2 }, "PUPDR12": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 24, "size": 2 }, "PUPDR11": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 22, "size": 2 }, "PUPDR10": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 20, "size": 2 }, "PUPDR9": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 18, "size": 2 }, "PUPDR8": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 16, "size": 2 }, "PUPDR7": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 14, "size": 2 }, "PUPDR6": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 12, "size": 2 }, "PUPDR5": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 10, "size": 2 }, "PUPDR4": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 8, "size": 2 }, "PUPDR3": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 6, "size": 2 }, "PUPDR2": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 4, "size": 2 }, "PUPDR1": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 2, "size": 2 }, "PUPDR0": { "description": "Port x configuration bits (y =\n 0..15)", "offset": 0, "size": 2 } } } }, "IDR": { "description": "GPIO port input data register", "offset": 16, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "IDR15": { "description": "Port input data (y =\n 0..15)", "offset": 15, "size": 1 }, "IDR14": { "description": "Port input data (y =\n 0..15)", "offset": 14, "size": 1 }, "IDR13": { "description": "Port input data (y =\n 0..15)", "offset": 13, "size": 1 }, "IDR12": { "description": "Port input data (y =\n 0..15)", "offset": 12, "size": 1 }, "IDR11": { "description": "Port input data (y =\n 0..15)", "offset": 11, "size": 1 }, "IDR10": { "description": "Port input data (y =\n 0..15)", "offset": 10, "size": 1 }, "IDR9": { "description": "Port input data (y =\n 0..15)", "offset": 9, "size": 1 }, "IDR8": { "description": "Port input data (y =\n 0..15)", "offset": 8, "size": 1 }, "IDR7": { "description": "Port input data (y =\n 0..15)", "offset": 7, "size": 1 }, "IDR6": { "description": "Port input data (y =\n 0..15)", "offset": 6, "size": 1 }, "IDR5": { "description": "Port input data (y =\n 0..15)", "offset": 5, "size": 1 }, "IDR4": { "description": "Port input data (y =\n 0..15)", "offset": 4, "size": 1 }, "IDR3": { "description": "Port input data (y =\n 0..15)", "offset": 3, "size": 1 }, "IDR2": { "description": "Port input data (y =\n 0..15)", "offset": 2, "size": 1 }, "IDR1": { "description": "Port input data (y =\n 0..15)", "offset": 1, "size": 1 }, "IDR0": { "description": "Port input data (y =\n 0..15)", "offset": 0, "size": 1 } } } }, "ODR": { "description": "GPIO port output data register", "offset": 20, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "ODR15": { "description": "Port output data (y =\n 0..15)", "offset": 15, "size": 1 }, "ODR14": { "description": "Port output data (y =\n 0..15)", "offset": 14, "size": 1 }, "ODR13": { "description": "Port output data (y =\n 0..15)", "offset": 13, "size": 1 }, "ODR12": { "description": "Port output data (y =\n 0..15)", "offset": 12, "size": 1 }, "ODR11": { "description": "Port output data (y =\n 0..15)", "offset": 11, "size": 1 }, "ODR10": { "description": "Port output data (y =\n 0..15)", "offset": 10, "size": 1 }, "ODR9": { "description": "Port output data (y =\n 0..15)", "offset": 9, "size": 1 }, "ODR8": { "description": "Port output data (y =\n 0..15)", "offset": 8, "size": 1 }, "ODR7": { "description": "Port output data (y =\n 0..15)", "offset": 7, "size": 1 }, "ODR6": { "description": "Port output data (y =\n 0..15)", "offset": 6, "size": 1 }, "ODR5": { "description": "Port output data (y =\n 0..15)", "offset": 5, "size": 1 }, "ODR4": { "description": "Port output data (y =\n 0..15)", "offset": 4, "size": 1 }, "ODR3": { "description": "Port output data (y =\n 0..15)", "offset": 3, "size": 1 }, "ODR2": { "description": "Port output data (y =\n 0..15)", "offset": 2, "size": 1 }, "ODR1": { "description": "Port output data (y =\n 0..15)", "offset": 1, "size": 1 }, "ODR0": { "description": "Port output data (y =\n 0..15)", "offset": 0, "size": 1 } } } }, "BSRR": { "description": "GPIO port bit set/reset\n register", "offset": 24, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "write-only", "children": { "fields": { "BR15": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 31, "size": 1 }, "BR14": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 30, "size": 1 }, "BR13": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 29, "size": 1 }, "BR12": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 28, "size": 1 }, "BR11": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 27, "size": 1 }, "BR10": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 26, "size": 1 }, "BR9": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 25, "size": 1 }, "BR8": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 24, "size": 1 }, "BR7": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 23, "size": 1 }, "BR6": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 22, "size": 1 }, "BR5": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 21, "size": 1 }, "BR4": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 20, "size": 1 }, "BR3": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 19, "size": 1 }, "BR2": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 18, "size": 1 }, "BR1": { "description": "Port x reset bit y (y =\n 0..15)", "offset": 17, "size": 1 }, "BR0": { "description": "Port x set bit y (y=\n 0..15)", "offset": 16, "size": 1 }, "BS15": { "description": "Port x set bit y (y=\n 0..15)", "offset": 15, "size": 1 }, "BS14": { "description": "Port x set bit y (y=\n 0..15)", "offset": 14, "size": 1 }, "BS13": { "description": "Port x set bit y (y=\n 0..15)", "offset": 13, "size": 1 }, "BS12": { "description": "Port x set bit y (y=\n 0..15)", "offset": 12, "size": 1 }, "BS11": { "description": "Port x set bit y (y=\n 0..15)", "offset": 11, "size": 1 }, "BS10": { "description": "Port x set bit y (y=\n 0..15)", "offset": 10, "size": 1 }, "BS9": { "description": "Port x set bit y (y=\n 0..15)", "offset": 9, "size": 1 }, "BS8": { "description": "Port x set bit y (y=\n 0..15)", "offset": 8, "size": 1 }, "BS7": { "description": "Port x set bit y (y=\n 0..15)", "offset": 7, "size": 1 }, "BS6": { "description": "Port x set bit y (y=\n 0..15)", "offset": 6, "size": 1 }, "BS5": { "description": "Port x set bit y (y=\n 0..15)", "offset": 5, "size": 1 }, "BS4": { "description": "Port x set bit y (y=\n 0..15)", "offset": 4, "size": 1 }, "BS3": { "description": "Port x set bit y (y=\n 0..15)", "offset": 3, "size": 1 }, "BS2": { "description": "Port x set bit y (y=\n 0..15)", "offset": 2, "size": 1 }, "BS1": { "description": "Port x set bit y (y=\n 0..15)", "offset": 1, "size": 1 }, "BS0": { "description": "Port x set bit y (y=\n 0..15)", "offset": 0, "size": 1 } } } }, "LCKR": { "description": "GPIO port configuration lock\n register", "offset": 28, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "LCKK": { "description": "Lok Key", "offset": 16, "size": 1 }, "LCK15": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 15, "size": 1 }, "LCK14": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 14, "size": 1 }, "LCK13": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 13, "size": 1 }, "LCK12": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 12, "size": 1 }, "LCK11": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 11, "size": 1 }, "LCK10": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 10, "size": 1 }, "LCK9": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 9, "size": 1 }, "LCK8": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 8, "size": 1 }, "LCK7": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 7, "size": 1 }, "LCK6": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 6, "size": 1 }, "LCK5": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 5, "size": 1 }, "LCK4": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 4, "size": 1 }, "LCK3": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 3, "size": 1 }, "LCK2": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 2, "size": 1 }, "LCK1": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 1, "size": 1 }, "LCK0": { "description": "Port x lock bit y (y=\n 0..15)", "offset": 0, "size": 1 } } } }, "AFRL": { "description": "GPIO alternate function low\n register", "offset": 32, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "AFRL7": { "description": "Alternate function selection for port x\n bit y (y = 0..7)", "offset": 28, "size": 4 }, "AFRL6": { "description": "Alternate function selection for port x\n bit y (y = 0..7)", "offset": 24, "size": 4 }, "AFRL5": { "description": "Alternate function selection for port x\n bit y (y = 0..7)", "offset": 20, "size": 4 }, "AFRL4": { "description": "Alternate function selection for port x\n bit y (y = 0..7)", "offset": 16, "size": 4 }, "AFRL3": { "description": "Alternate function selection for port x\n bit y (y = 0..7)", "offset": 12, "size": 4 }, "AFRL2": { "description": "Alternate function selection for port x\n bit y (y = 0..7)", "offset": 8, "size": 4 }, "AFRL1": { "description": "Alternate function selection for port x\n bit y (y = 0..7)", "offset": 4, "size": 4 }, "AFRL0": { "description": "Alternate function selection for port x\n bit y (y = 0..7)", "offset": 0, "size": 4 } } } }, "AFRH": { "description": "GPIO alternate function high\n register", "offset": 36, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "AFRH15": { "description": "Alternate function selection for port x\n bit y (y = 8..15)", "offset": 28, "size": 4 }, "AFRH14": { "description": "Alternate function selection for port x\n bit y (y = 8..15)", "offset": 24, "size": 4 }, "AFRH13": { "description": "Alternate function selection for port x\n bit y (y = 8..15)", "offset": 20, "size": 4 }, "AFRH12": { "description": "Alternate function selection for port x\n bit y (y = 8..15)", "offset": 16, "size": 4 }, "AFRH11": { "description": "Alternate function selection for port x\n bit y (y = 8..15)", "offset": 12, "size": 4 }, "AFRH10": { "description": "Alternate function selection for port x\n bit y (y = 8..15)", "offset": 8, "size": 4 }, "AFRH9": { "description": "Alternate function selection for port x\n bit y (y = 8..15)", "offset": 4, "size": 4 }, "AFRH8": { "description": "Alternate function selection for port x\n bit y (y = 8..15)", "offset": 0, "size": 4 } } } }, "BRR": { "description": "Port bit reset register", "offset": 40, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "write-only", "children": { "fields": { "BR0": { "description": "Port x Reset bit y", "offset": 0, "size": 1 }, "BR1": { "description": "Port x Reset bit y", "offset": 1, "size": 1 }, "BR2": { "description": "Port x Reset bit y", "offset": 2, "size": 1 }, "BR3": { "description": "Port x Reset bit y", "offset": 3, "size": 1 }, "BR4": { "description": "Port x Reset bit y", "offset": 4, "size": 1 }, "BR5": { "description": "Port x Reset bit y", "offset": 5, "size": 1 }, "BR6": { "description": "Port x Reset bit y", "offset": 6, "size": 1 }, "BR7": { "description": "Port x Reset bit y", "offset": 7, "size": 1 }, "BR8": { "description": "Port x Reset bit y", "offset": 8, "size": 1 }, "BR9": { "description": "Port x Reset bit y", "offset": 9, "size": 1 }, "BR10": { "description": "Port x Reset bit y", "offset": 10, "size": 1 }, "BR11": { "description": "Port x Reset bit y", "offset": 11, "size": 1 }, "BR12": { "description": "Port x Reset bit y", "offset": 12, "size": 1 }, "BR13": { "description": "Port x Reset bit y", "offset": 13, "size": 1 }, "BR14": { "description": "Port x Reset bit y", "offset": 14, "size": 1 }, "BR15": { "description": "Port x Reset bit y", "offset": 15, "size": 1 } } } } } } }, "SCB_ACTRL": { "description": "System control block ACTLR", "children": { "registers": { "ACTRL": { "description": "Auxiliary control register", "offset": 0, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DISMCYCINT": { "description": "DISMCYCINT", "offset": 0, "size": 1 }, "DISDEFWBUF": { "description": "DISDEFWBUF", "offset": 1, "size": 1 }, "DISFOLD": { "description": "DISFOLD", "offset": 2, "size": 1 }, "DISFPCA": { "description": "DISFPCA", "offset": 8, "size": 1 }, "DISOOFP": { "description": "DISOOFP", "offset": 9, "size": 1 } } } } } } }, "FPU_CPACR": { "description": "Floating point unit CPACR", "children": { "registers": { "CPACR": { "description": "Coprocessor access control\n register", "offset": 0, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CP": { "description": "CP", "offset": 20, "size": 4 } } } } } } }, "NVIC_STIR": { "description": "Nested vectored interrupt\n controller", "children": { "registers": { "STIR": { "description": "Software trigger interrupt\n register", "offset": 0, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "INTID": { "description": "Software generated interrupt\n ID", "offset": 0, "size": 9 } } } } } } }, "SCB": { "description": "System control block", "children": { "registers": { "CPUID": { "description": "CPUID base register", "offset": 0, "size": 32, "reset_value": 1091551809, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "Revision": { "description": "Revision number", "offset": 0, "size": 4 }, "PartNo": { "description": "Part number of the\n processor", "offset": 4, "size": 12 }, "Constant": { "description": "Reads as 0xF", "offset": 16, "size": 4 }, "Variant": { "description": "Variant number", "offset": 20, "size": 4 }, "Implementer": { "description": "Implementer code", "offset": 24, "size": 8 } } } }, "ICSR": { "description": "Interrupt control and state\n register", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "VECTACTIVE": { "description": "Active vector", "offset": 0, "size": 9 }, "RETTOBASE": { "description": "Return to base level", "offset": 11, "size": 1 }, "VECTPENDING": { "description": "Pending vector", "offset": 12, "size": 7 }, "ISRPENDING": { "description": "Interrupt pending flag", "offset": 22, "size": 1 }, "PENDSTCLR": { "description": "SysTick exception clear-pending\n bit", "offset": 25, "size": 1 }, "PENDSTSET": { "description": "SysTick exception set-pending\n bit", "offset": 26, "size": 1 }, "PENDSVCLR": { "description": "PendSV clear-pending bit", "offset": 27, "size": 1 }, "PENDSVSET": { "description": "PendSV set-pending bit", "offset": 28, "size": 1 }, "NMIPENDSET": { "description": "NMI set-pending bit.", "offset": 31, "size": 1 } } } }, "VTOR": { "description": "Vector table offset register", "offset": 8, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "TBLOFF": { "description": "Vector table base offset\n field", "offset": 9, "size": 21 } } } }, "AIRCR": { "description": "Application interrupt and reset control\n register", "offset": 12, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "VECTRESET": { "description": "VECTRESET", "offset": 0, "size": 1 }, "VECTCLRACTIVE": { "description": "VECTCLRACTIVE", "offset": 1, "size": 1 }, "SYSRESETREQ": { "description": "SYSRESETREQ", "offset": 2, "size": 1 }, "PRIGROUP": { "description": "PRIGROUP", "offset": 8, "size": 3 }, "ENDIANESS": { "description": "ENDIANESS", "offset": 15, "size": 1 }, "VECTKEYSTAT": { "description": "Register key", "offset": 16, "size": 16 } } } }, "SCR": { "description": "System control register", "offset": 16, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "SLEEPONEXIT": { "description": "SLEEPONEXIT", "offset": 1, "size": 1 }, "SLEEPDEEP": { "description": "SLEEPDEEP", "offset": 2, "size": 1 }, "SEVEONPEND": { "description": "Send Event on Pending bit", "offset": 4, "size": 1 } } } }, "CCR": { "description": "Configuration and control\n register", "offset": 20, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "NONBASETHRDENA": { "description": "Configures how the processor enters\n Thread mode", "offset": 0, "size": 1 }, "USERSETMPEND": { "description": "USERSETMPEND", "offset": 1, "size": 1 }, "UNALIGN__TRP": { "description": "UNALIGN_ TRP", "offset": 3, "size": 1 }, "DIV_0_TRP": { "description": "DIV_0_TRP", "offset": 4, "size": 1 }, "BFHFNMIGN": { "description": "BFHFNMIGN", "offset": 8, "size": 1 }, "STKALIGN": { "description": "STKALIGN", "offset": 9, "size": 1 } } } }, "SHPR1": { "description": "System handler priority\n registers", "offset": 24, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "PRI_4": { "description": "Priority of system handler\n 4", "offset": 0, "size": 8 }, "PRI_5": { "description": "Priority of system handler\n 5", "offset": 8, "size": 8 }, "PRI_6": { "description": "Priority of system handler\n 6", "offset": 16, "size": 8 } } } }, "SHPR2": { "description": "System handler priority\n registers", "offset": 28, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "PRI_11": { "description": "Priority of system handler\n 11", "offset": 24, "size": 8 } } } }, "SHPR3": { "description": "System handler priority\n registers", "offset": 32, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "PRI_14": { "description": "Priority of system handler\n 14", "offset": 16, "size": 8 }, "PRI_15": { "description": "Priority of system handler\n 15", "offset": 24, "size": 8 } } } }, "SHCRS": { "description": "System handler control and state\n register", "offset": 36, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "MEMFAULTACT": { "description": "Memory management fault exception active\n bit", "offset": 0, "size": 1 }, "BUSFAULTACT": { "description": "Bus fault exception active\n bit", "offset": 1, "size": 1 }, "USGFAULTACT": { "description": "Usage fault exception active\n bit", "offset": 3, "size": 1 }, "SVCALLACT": { "description": "SVC call active bit", "offset": 7, "size": 1 }, "MONITORACT": { "description": "Debug monitor active bit", "offset": 8, "size": 1 }, "PENDSVACT": { "description": "PendSV exception active\n bit", "offset": 10, "size": 1 }, "SYSTICKACT": { "description": "SysTick exception active\n bit", "offset": 11, "size": 1 }, "USGFAULTPENDED": { "description": "Usage fault exception pending\n bit", "offset": 12, "size": 1 }, "MEMFAULTPENDED": { "description": "Memory management fault exception\n pending bit", "offset": 13, "size": 1 }, "BUSFAULTPENDED": { "description": "Bus fault exception pending\n bit", "offset": 14, "size": 1 }, "SVCALLPENDED": { "description": "SVC call pending bit", "offset": 15, "size": 1 }, "MEMFAULTENA": { "description": "Memory management fault enable\n bit", "offset": 16, "size": 1 }, "BUSFAULTENA": { "description": "Bus fault enable bit", "offset": 17, "size": 1 }, "USGFAULTENA": { "description": "Usage fault enable bit", "offset": 18, "size": 1 } } } }, "CFSR_UFSR_BFSR_MMFSR": { "description": "Configurable fault status\n register", "offset": 40, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IACCVIOL": { "description": "Instruction access violation\n flag", "offset": 1, "size": 1 }, "MUNSTKERR": { "description": "Memory manager fault on unstacking for a\n return from exception", "offset": 3, "size": 1 }, "MSTKERR": { "description": "Memory manager fault on stacking for\n exception entry.", "offset": 4, "size": 1 }, "MLSPERR": { "description": "MLSPERR", "offset": 5, "size": 1 }, "MMARVALID": { "description": "Memory Management Fault Address Register\n (MMAR) valid flag", "offset": 7, "size": 1 }, "IBUSERR": { "description": "Instruction bus error", "offset": 8, "size": 1 }, "PRECISERR": { "description": "Precise data bus error", "offset": 9, "size": 1 }, "IMPRECISERR": { "description": "Imprecise data bus error", "offset": 10, "size": 1 }, "UNSTKERR": { "description": "Bus fault on unstacking for a return\n from exception", "offset": 11, "size": 1 }, "STKERR": { "description": "Bus fault on stacking for exception\n entry", "offset": 12, "size": 1 }, "LSPERR": { "description": "Bus fault on floating-point lazy state\n preservation", "offset": 13, "size": 1 }, "BFARVALID": { "description": "Bus Fault Address Register (BFAR) valid\n flag", "offset": 15, "size": 1 }, "UNDEFINSTR": { "description": "Undefined instruction usage\n fault", "offset": 16, "size": 1 }, "INVSTATE": { "description": "Invalid state usage fault", "offset": 17, "size": 1 }, "INVPC": { "description": "Invalid PC load usage\n fault", "offset": 18, "size": 1 }, "NOCP": { "description": "No coprocessor usage\n fault.", "offset": 19, "size": 1 }, "UNALIGNED": { "description": "Unaligned access usage\n fault", "offset": 24, "size": 1 }, "DIVBYZERO": { "description": "Divide by zero usage fault", "offset": 25, "size": 1 } } } }, "HFSR": { "description": "Hard fault status register", "offset": 44, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "VECTTBL": { "description": "Vector table hard fault", "offset": 1, "size": 1 }, "FORCED": { "description": "Forced hard fault", "offset": 30, "size": 1 }, "DEBUG_VT": { "description": "Reserved for Debug use", "offset": 31, "size": 1 } } } }, "MMFAR": { "description": "Memory management fault address\n register", "offset": 52, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "MMFAR": { "description": "Memory management fault\n address", "offset": 0, "size": 32 } } } }, "BFAR": { "description": "Bus fault address register", "offset": 56, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BFAR": { "description": "Bus fault address", "offset": 0, "size": 32 } } } }, "AFSR": { "description": "Auxiliary fault status\n register", "offset": 60, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IMPDEF": { "description": "Implementation defined", "offset": 0, "size": 32 } } } } } } }, "STK": { "description": "SysTick timer", "children": { "registers": { "CTRL": { "description": "SysTick control and status\n register", "offset": 0, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "ENABLE": { "description": "Counter enable", "offset": 0, "size": 1 }, "TICKINT": { "description": "SysTick exception request\n enable", "offset": 1, "size": 1 }, "CLKSOURCE": { "description": "Clock source selection", "offset": 2, "size": 1 }, "COUNTFLAG": { "description": "COUNTFLAG", "offset": 16, "size": 1 } } } }, "LOAD": { "description": "SysTick reload value register", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "RELOAD": { "description": "RELOAD value", "offset": 0, "size": 24 } } } }, "VAL": { "description": "SysTick current value register", "offset": 8, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CURRENT": { "description": "Current counter value", "offset": 0, "size": 24 } } } }, "CALIB": { "description": "SysTick calibration value\n register", "offset": 12, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "TENMS": { "description": "Calibration value", "offset": 0, "size": 24 }, "SKEW": { "description": "SKEW flag: Indicates whether the TENMS\n value is exact", "offset": 30, "size": 1 }, "NOREF": { "description": "NOREF flag. Reads as zero", "offset": 31, "size": 1 } } } } } } }, "MPU": { "description": "Memory protection unit", "children": { "registers": { "MPU_TYPER": { "description": "MPU type register", "offset": 0, "size": 32, "reset_value": 2048, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "SEPARATE": { "description": "Separate flag", "offset": 0, "size": 1 }, "DREGION": { "description": "Number of MPU data regions", "offset": 8, "size": 8 }, "IREGION": { "description": "Number of MPU instruction\n regions", "offset": 16, "size": 8 } } } }, "MPU_CTRL": { "description": "MPU control register", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "ENABLE": { "description": "Enables the MPU", "offset": 0, "size": 1 }, "HFNMIENA": { "description": "Enables the operation of MPU during hard\n fault", "offset": 1, "size": 1 }, "PRIVDEFENA": { "description": "Enable priviliged software access to\n default memory map", "offset": 2, "size": 1 } } } }, "MPU_RNR": { "description": "MPU region number register", "offset": 8, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "REGION": { "description": "MPU region", "offset": 0, "size": 8 } } } }, "MPU_RBAR": { "description": "MPU region base address\n register", "offset": 12, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "REGION": { "description": "MPU region field", "offset": 0, "size": 4 }, "VALID": { "description": "MPU region number valid", "offset": 4, "size": 1 }, "ADDR": { "description": "Region base address field", "offset": 5, "size": 27 } } } }, "MPU_RASR": { "description": "MPU region attribute and size\n register", "offset": 16, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "ENABLE": { "description": "Region enable bit.", "offset": 0, "size": 1 }, "SIZE": { "description": "Size of the MPU protection\n region", "offset": 1, "size": 5 }, "SRD": { "description": "Subregion disable bits", "offset": 8, "size": 8 }, "B": { "description": "memory attribute", "offset": 16, "size": 1 }, "C": { "description": "memory attribute", "offset": 17, "size": 1 }, "S": { "description": "Shareable memory attribute", "offset": 18, "size": 1 }, "TEX": { "description": "memory attribute", "offset": 19, "size": 3 }, "AP": { "description": "Access permission", "offset": 24, "size": 3 }, "XN": { "description": "Instruction access disable\n bit", "offset": 28, "size": 1 } } } } } } }, "TSC": { "description": "Touch sensing controller", "children": { "registers": { "CR": { "description": "control register", "offset": 0, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CTPH": { "description": "Charge transfer pulse high", "offset": 28, "size": 4 }, "CTPL": { "description": "Charge transfer pulse low", "offset": 24, "size": 4 }, "SSD": { "description": "Spread spectrum deviation", "offset": 17, "size": 7 }, "SSE": { "description": "Spread spectrum enable", "offset": 16, "size": 1 }, "SSPSC": { "description": "Spread spectrum prescaler", "offset": 15, "size": 1 }, "PGPSC": { "description": "pulse generator prescaler", "offset": 12, "size": 3 }, "MCV": { "description": "Max count value", "offset": 5, "size": 3 }, "IODEF": { "description": "I/O Default mode", "offset": 4, "size": 1 }, "SYNCPOL": { "description": "Synchronization pin\n polarity", "offset": 3, "size": 1 }, "AM": { "description": "Acquisition mode", "offset": 2, "size": 1 }, "START": { "description": "Start a new acquisition", "offset": 1, "size": 1 }, "TSCE": { "description": "Touch sensing controller\n enable", "offset": 0, "size": 1 } } } }, "IER": { "description": "interrupt enable register", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "MCEIE": { "description": "Max count error interrupt\n enable", "offset": 1, "size": 1 }, "EOAIE": { "description": "End of acquisition interrupt\n enable", "offset": 0, "size": 1 } } } }, "ICR": { "description": "interrupt clear register", "offset": 8, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "MCEIC": { "description": "Max count error interrupt\n clear", "offset": 1, "size": 1 }, "EOAIC": { "description": "End of acquisition interrupt\n clear", "offset": 0, "size": 1 } } } }, "ISR": { "description": "interrupt status register", "offset": 12, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "MCEF": { "description": "Max count error flag", "offset": 1, "size": 1 }, "EOAF": { "description": "End of acquisition flag", "offset": 0, "size": 1 } } } }, "IOHCR": { "description": "I/O hysteresis control\n register", "offset": 16, "size": 32, "reset_value": 4294967295, "reset_mask": 4294967295, "children": { "fields": { "G1_IO1": { "description": "G1_IO1 Schmitt trigger hysteresis\n mode", "offset": 0, "size": 1 }, "G1_IO2": { "description": "G1_IO2 Schmitt trigger hysteresis\n mode", "offset": 1, "size": 1 }, "G1_IO3": { "description": "G1_IO3 Schmitt trigger hysteresis\n mode", "offset": 2, "size": 1 }, "G1_IO4": { "description": "G1_IO4 Schmitt trigger hysteresis\n mode", "offset": 3, "size": 1 }, "G2_IO1": { "description": "G2_IO1 Schmitt trigger hysteresis\n mode", "offset": 4, "size": 1 }, "G2_IO2": { "description": "G2_IO2 Schmitt trigger hysteresis\n mode", "offset": 5, "size": 1 }, "G2_IO3": { "description": "G2_IO3 Schmitt trigger hysteresis\n mode", "offset": 6, "size": 1 }, "G2_IO4": { "description": "G2_IO4 Schmitt trigger hysteresis\n mode", "offset": 7, "size": 1 }, "G3_IO1": { "description": "G3_IO1 Schmitt trigger hysteresis\n mode", "offset": 8, "size": 1 }, "G3_IO2": { "description": "G3_IO2 Schmitt trigger hysteresis\n mode", "offset": 9, "size": 1 }, "G3_IO3": { "description": "G3_IO3 Schmitt trigger hysteresis\n mode", "offset": 10, "size": 1 }, "G3_IO4": { "description": "G3_IO4 Schmitt trigger hysteresis\n mode", "offset": 11, "size": 1 }, "G4_IO1": { "description": "G4_IO1 Schmitt trigger hysteresis\n mode", "offset": 12, "size": 1 }, "G4_IO2": { "description": "G4_IO2 Schmitt trigger hysteresis\n mode", "offset": 13, "size": 1 }, "G4_IO3": { "description": "G4_IO3 Schmitt trigger hysteresis\n mode", "offset": 14, "size": 1 }, "G4_IO4": { "description": "G4_IO4 Schmitt trigger hysteresis\n mode", "offset": 15, "size": 1 }, "G5_IO1": { "description": "G5_IO1 Schmitt trigger hysteresis\n mode", "offset": 16, "size": 1 }, "G5_IO2": { "description": "G5_IO2 Schmitt trigger hysteresis\n mode", "offset": 17, "size": 1 }, "G5_IO3": { "description": "G5_IO3 Schmitt trigger hysteresis\n mode", "offset": 18, "size": 1 }, "G5_IO4": { "description": "G5_IO4 Schmitt trigger hysteresis\n mode", "offset": 19, "size": 1 }, "G6_IO1": { "description": "G6_IO1 Schmitt trigger hysteresis\n mode", "offset": 20, "size": 1 }, "G6_IO2": { "description": "G6_IO2 Schmitt trigger hysteresis\n mode", "offset": 21, "size": 1 }, "G6_IO3": { "description": "G6_IO3 Schmitt trigger hysteresis\n mode", "offset": 22, "size": 1 }, "G6_IO4": { "description": "G6_IO4 Schmitt trigger hysteresis\n mode", "offset": 23, "size": 1 }, "G7_IO1": { "description": "G7_IO1 Schmitt trigger hysteresis\n mode", "offset": 24, "size": 1 }, "G7_IO2": { "description": "G7_IO2 Schmitt trigger hysteresis\n mode", "offset": 25, "size": 1 }, "G7_IO3": { "description": "G7_IO3 Schmitt trigger hysteresis\n mode", "offset": 26, "size": 1 }, "G7_IO4": { "description": "G7_IO4 Schmitt trigger hysteresis\n mode", "offset": 27, "size": 1 }, "G8_IO1": { "description": "G8_IO1 Schmitt trigger hysteresis\n mode", "offset": 28, "size": 1 }, "G8_IO2": { "description": "G8_IO2 Schmitt trigger hysteresis\n mode", "offset": 29, "size": 1 }, "G8_IO3": { "description": "G8_IO3 Schmitt trigger hysteresis\n mode", "offset": 30, "size": 1 }, "G8_IO4": { "description": "G8_IO4 Schmitt trigger hysteresis\n mode", "offset": 31, "size": 1 } } } }, "IOASCR": { "description": "I/O analog switch control\n register", "offset": 24, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "G1_IO1": { "description": "G1_IO1 analog switch\n enable", "offset": 0, "size": 1 }, "G1_IO2": { "description": "G1_IO2 analog switch\n enable", "offset": 1, "size": 1 }, "G1_IO3": { "description": "G1_IO3 analog switch\n enable", "offset": 2, "size": 1 }, "G1_IO4": { "description": "G1_IO4 analog switch\n enable", "offset": 3, "size": 1 }, "G2_IO1": { "description": "G2_IO1 analog switch\n enable", "offset": 4, "size": 1 }, "G2_IO2": { "description": "G2_IO2 analog switch\n enable", "offset": 5, "size": 1 }, "G2_IO3": { "description": "G2_IO3 analog switch\n enable", "offset": 6, "size": 1 }, "G2_IO4": { "description": "G2_IO4 analog switch\n enable", "offset": 7, "size": 1 }, "G3_IO1": { "description": "G3_IO1 analog switch\n enable", "offset": 8, "size": 1 }, "G3_IO2": { "description": "G3_IO2 analog switch\n enable", "offset": 9, "size": 1 }, "G3_IO3": { "description": "G3_IO3 analog switch\n enable", "offset": 10, "size": 1 }, "G3_IO4": { "description": "G3_IO4 analog switch\n enable", "offset": 11, "size": 1 }, "G4_IO1": { "description": "G4_IO1 analog switch\n enable", "offset": 12, "size": 1 }, "G4_IO2": { "description": "G4_IO2 analog switch\n enable", "offset": 13, "size": 1 }, "G4_IO3": { "description": "G4_IO3 analog switch\n enable", "offset": 14, "size": 1 }, "G4_IO4": { "description": "G4_IO4 analog switch\n enable", "offset": 15, "size": 1 }, "G5_IO1": { "description": "G5_IO1 analog switch\n enable", "offset": 16, "size": 1 }, "G5_IO2": { "description": "G5_IO2 analog switch\n enable", "offset": 17, "size": 1 }, "G5_IO3": { "description": "G5_IO3 analog switch\n enable", "offset": 18, "size": 1 }, "G5_IO4": { "description": "G5_IO4 analog switch\n enable", "offset": 19, "size": 1 }, "G6_IO1": { "description": "G6_IO1 analog switch\n enable", "offset": 20, "size": 1 }, "G6_IO2": { "description": "G6_IO2 analog switch\n enable", "offset": 21, "size": 1 }, "G6_IO3": { "description": "G6_IO3 analog switch\n enable", "offset": 22, "size": 1 }, "G6_IO4": { "description": "G6_IO4 analog switch\n enable", "offset": 23, "size": 1 }, "G7_IO1": { "description": "G7_IO1 analog switch\n enable", "offset": 24, "size": 1 }, "G7_IO2": { "description": "G7_IO2 analog switch\n enable", "offset": 25, "size": 1 }, "G7_IO3": { "description": "G7_IO3 analog switch\n enable", "offset": 26, "size": 1 }, "G7_IO4": { "description": "G7_IO4 analog switch\n enable", "offset": 27, "size": 1 }, "G8_IO1": { "description": "G8_IO1 analog switch\n enable", "offset": 28, "size": 1 }, "G8_IO2": { "description": "G8_IO2 analog switch\n enable", "offset": 29, "size": 1 }, "G8_IO3": { "description": "G8_IO3 analog switch\n enable", "offset": 30, "size": 1 }, "G8_IO4": { "description": "G8_IO4 analog switch\n enable", "offset": 31, "size": 1 } } } }, "IOSCR": { "description": "I/O sampling control register", "offset": 32, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "G1_IO1": { "description": "G1_IO1 sampling mode", "offset": 0, "size": 1 }, "G1_IO2": { "description": "G1_IO2 sampling mode", "offset": 1, "size": 1 }, "G1_IO3": { "description": "G1_IO3 sampling mode", "offset": 2, "size": 1 }, "G1_IO4": { "description": "G1_IO4 sampling mode", "offset": 3, "size": 1 }, "G2_IO1": { "description": "G2_IO1 sampling mode", "offset": 4, "size": 1 }, "G2_IO2": { "description": "G2_IO2 sampling mode", "offset": 5, "size": 1 }, "G2_IO3": { "description": "G2_IO3 sampling mode", "offset": 6, "size": 1 }, "G2_IO4": { "description": "G2_IO4 sampling mode", "offset": 7, "size": 1 }, "G3_IO1": { "description": "G3_IO1 sampling mode", "offset": 8, "size": 1 }, "G3_IO2": { "description": "G3_IO2 sampling mode", "offset": 9, "size": 1 }, "G3_IO3": { "description": "G3_IO3 sampling mode", "offset": 10, "size": 1 }, "G3_IO4": { "description": "G3_IO4 sampling mode", "offset": 11, "size": 1 }, "G4_IO1": { "description": "G4_IO1 sampling mode", "offset": 12, "size": 1 }, "G4_IO2": { "description": "G4_IO2 sampling mode", "offset": 13, "size": 1 }, "G4_IO3": { "description": "G4_IO3 sampling mode", "offset": 14, "size": 1 }, "G4_IO4": { "description": "G4_IO4 sampling mode", "offset": 15, "size": 1 }, "G5_IO1": { "description": "G5_IO1 sampling mode", "offset": 16, "size": 1 }, "G5_IO2": { "description": "G5_IO2 sampling mode", "offset": 17, "size": 1 }, "G5_IO3": { "description": "G5_IO3 sampling mode", "offset": 18, "size": 1 }, "G5_IO4": { "description": "G5_IO4 sampling mode", "offset": 19, "size": 1 }, "G6_IO1": { "description": "G6_IO1 sampling mode", "offset": 20, "size": 1 }, "G6_IO2": { "description": "G6_IO2 sampling mode", "offset": 21, "size": 1 }, "G6_IO3": { "description": "G6_IO3 sampling mode", "offset": 22, "size": 1 }, "G6_IO4": { "description": "G6_IO4 sampling mode", "offset": 23, "size": 1 }, "G7_IO1": { "description": "G7_IO1 sampling mode", "offset": 24, "size": 1 }, "G7_IO2": { "description": "G7_IO2 sampling mode", "offset": 25, "size": 1 }, "G7_IO3": { "description": "G7_IO3 sampling mode", "offset": 26, "size": 1 }, "G7_IO4": { "description": "G7_IO4 sampling mode", "offset": 27, "size": 1 }, "G8_IO1": { "description": "G8_IO1 sampling mode", "offset": 28, "size": 1 }, "G8_IO2": { "description": "G8_IO2 sampling mode", "offset": 29, "size": 1 }, "G8_IO3": { "description": "G8_IO3 sampling mode", "offset": 30, "size": 1 }, "G8_IO4": { "description": "G8_IO4 sampling mode", "offset": 31, "size": 1 } } } }, "IOCCR": { "description": "I/O channel control register", "offset": 40, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "G1_IO1": { "description": "G1_IO1 channel mode", "offset": 0, "size": 1 }, "G1_IO2": { "description": "G1_IO2 channel mode", "offset": 1, "size": 1 }, "G1_IO3": { "description": "G1_IO3 channel mode", "offset": 2, "size": 1 }, "G1_IO4": { "description": "G1_IO4 channel mode", "offset": 3, "size": 1 }, "G2_IO1": { "description": "G2_IO1 channel mode", "offset": 4, "size": 1 }, "G2_IO2": { "description": "G2_IO2 channel mode", "offset": 5, "size": 1 }, "G2_IO3": { "description": "G2_IO3 channel mode", "offset": 6, "size": 1 }, "G2_IO4": { "description": "G2_IO4 channel mode", "offset": 7, "size": 1 }, "G3_IO1": { "description": "G3_IO1 channel mode", "offset": 8, "size": 1 }, "G3_IO2": { "description": "G3_IO2 channel mode", "offset": 9, "size": 1 }, "G3_IO3": { "description": "G3_IO3 channel mode", "offset": 10, "size": 1 }, "G3_IO4": { "description": "G3_IO4 channel mode", "offset": 11, "size": 1 }, "G4_IO1": { "description": "G4_IO1 channel mode", "offset": 12, "size": 1 }, "G4_IO2": { "description": "G4_IO2 channel mode", "offset": 13, "size": 1 }, "G4_IO3": { "description": "G4_IO3 channel mode", "offset": 14, "size": 1 }, "G4_IO4": { "description": "G4_IO4 channel mode", "offset": 15, "size": 1 }, "G5_IO1": { "description": "G5_IO1 channel mode", "offset": 16, "size": 1 }, "G5_IO2": { "description": "G5_IO2 channel mode", "offset": 17, "size": 1 }, "G5_IO3": { "description": "G5_IO3 channel mode", "offset": 18, "size": 1 }, "G5_IO4": { "description": "G5_IO4 channel mode", "offset": 19, "size": 1 }, "G6_IO1": { "description": "G6_IO1 channel mode", "offset": 20, "size": 1 }, "G6_IO2": { "description": "G6_IO2 channel mode", "offset": 21, "size": 1 }, "G6_IO3": { "description": "G6_IO3 channel mode", "offset": 22, "size": 1 }, "G6_IO4": { "description": "G6_IO4 channel mode", "offset": 23, "size": 1 }, "G7_IO1": { "description": "G7_IO1 channel mode", "offset": 24, "size": 1 }, "G7_IO2": { "description": "G7_IO2 channel mode", "offset": 25, "size": 1 }, "G7_IO3": { "description": "G7_IO3 channel mode", "offset": 26, "size": 1 }, "G7_IO4": { "description": "G7_IO4 channel mode", "offset": 27, "size": 1 }, "G8_IO1": { "description": "G8_IO1 channel mode", "offset": 28, "size": 1 }, "G8_IO2": { "description": "G8_IO2 channel mode", "offset": 29, "size": 1 }, "G8_IO3": { "description": "G8_IO3 channel mode", "offset": 30, "size": 1 }, "G8_IO4": { "description": "G8_IO4 channel mode", "offset": 31, "size": 1 } } } }, "IOGCSR": { "description": "I/O group control status\n register", "offset": 48, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "G8S": { "description": "Analog I/O group x status", "offset": 23, "size": 1 }, "G7S": { "description": "Analog I/O group x status", "offset": 22, "size": 1 }, "G6S": { "description": "Analog I/O group x status", "offset": 21, "size": 1, "access": "read-only" }, "G5S": { "description": "Analog I/O group x status", "offset": 20, "size": 1, "access": "read-only" }, "G4S": { "description": "Analog I/O group x status", "offset": 19, "size": 1, "access": "read-only" }, "G3S": { "description": "Analog I/O group x status", "offset": 18, "size": 1, "access": "read-only" }, "G2S": { "description": "Analog I/O group x status", "offset": 17, "size": 1, "access": "read-only" }, "G1S": { "description": "Analog I/O group x status", "offset": 16, "size": 1, "access": "read-only" }, "G8E": { "description": "Analog I/O group x enable", "offset": 7, "size": 1 }, "G7E": { "description": "Analog I/O group x enable", "offset": 6, "size": 1 }, "G6E": { "description": "Analog I/O group x enable", "offset": 5, "size": 1 }, "G5E": { "description": "Analog I/O group x enable", "offset": 4, "size": 1 }, "G4E": { "description": "Analog I/O group x enable", "offset": 3, "size": 1 }, "G3E": { "description": "Analog I/O group x enable", "offset": 2, "size": 1 }, "G2E": { "description": "Analog I/O group x enable", "offset": 1, "size": 1 }, "G1E": { "description": "Analog I/O group x enable", "offset": 0, "size": 1 } } } }, "IOG1CR": { "description": "I/O group x counter register", "offset": 52, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "CNT": { "description": "Counter value", "offset": 0, "size": 14 } } } }, "IOG2CR": { "description": "I/O group x counter register", "offset": 56, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "CNT": { "description": "Counter value", "offset": 0, "size": 14 } } } }, "IOG3CR": { "description": "I/O group x counter register", "offset": 60, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "CNT": { "description": "Counter value", "offset": 0, "size": 14 } } } }, "IOG4CR": { "description": "I/O group x counter register", "offset": 64, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "CNT": { "description": "Counter value", "offset": 0, "size": 14 } } } }, "IOG5CR": { "description": "I/O group x counter register", "offset": 68, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "CNT": { "description": "Counter value", "offset": 0, "size": 14 } } } }, "IOG6CR": { "description": "I/O group x counter register", "offset": 72, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "CNT": { "description": "Counter value", "offset": 0, "size": 14 } } } }, "IOG7CR": { "description": "I/O group x counter register", "offset": 76, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "CNT": { "description": "Counter value", "offset": 0, "size": 14 } } } }, "IOG8CR": { "description": "I/O group x counter register", "offset": 80, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "CNT": { "description": "Counter value", "offset": 0, "size": 14 } } } } } } }, "CRC": { "description": "cyclic redundancy check calculation\n unit", "children": { "registers": { "DR": { "description": "Data register", "offset": 0, "size": 32, "reset_value": 4294967295, "reset_mask": 4294967295, "children": { "fields": { "DR": { "description": "Data register bits", "offset": 0, "size": 32 } } } }, "IDR": { "description": "Independent data register", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IDR": { "description": "General-purpose 8-bit data register\n bits", "offset": 0, "size": 8 } } } }, "CR": { "description": "Control register", "offset": 8, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "RESET": { "description": "reset bit", "offset": 0, "size": 1 }, "POLYSIZE": { "description": "Polynomial size", "offset": 3, "size": 2 }, "REV_IN": { "description": "Reverse input data", "offset": 5, "size": 2 }, "REV_OUT": { "description": "Reverse output data", "offset": 7, "size": 1 } } } }, "INIT": { "description": "Initial CRC value", "offset": 16, "size": 32, "reset_value": 4294967295, "reset_mask": 4294967295, "children": { "fields": { "INIT": { "description": "Programmable initial CRC\n value", "offset": 0, "size": 32 } } } }, "POL": { "description": "CRC polynomial", "offset": 20, "size": 32, "reset_value": 79764919, "reset_mask": 4294967295, "children": { "fields": { "POL": { "description": "Programmable polynomial", "offset": 0, "size": 32 } } } } } } }, "Flash": { "description": "Flash", "children": { "registers": { "ACR": { "description": "Flash access control register", "offset": 0, "size": 32, "reset_value": 48, "reset_mask": 4294967295, "children": { "fields": { "LATENCY": { "description": "LATENCY", "offset": 0, "size": 3 }, "PRFTBE": { "description": "PRFTBE", "offset": 4, "size": 1 }, "PRFTBS": { "description": "PRFTBS", "offset": 5, "size": 1, "access": "read-only" } } } }, "KEYR": { "description": "Flash key register", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "write-only", "children": { "fields": { "FKEYR": { "description": "Flash Key", "offset": 0, "size": 32 } } } }, "OPTKEYR": { "description": "Flash option key register", "offset": 8, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "write-only", "children": { "fields": { "OPTKEYR": { "description": "Option byte key", "offset": 0, "size": 32 } } } }, "SR": { "description": "Flash status register", "offset": 12, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "EOP": { "description": "End of operation", "offset": 5, "size": 1 }, "WRPRT": { "description": "Write protection error", "offset": 4, "size": 1 }, "PGERR": { "description": "Programming error", "offset": 2, "size": 1 }, "BSY": { "description": "Busy", "offset": 0, "size": 1, "access": "read-only" } } } }, "CR": { "description": "Flash control register", "offset": 16, "size": 32, "reset_value": 128, "reset_mask": 4294967295, "children": { "fields": { "FORCE_OPTLOAD": { "description": "Force option byte loading", "offset": 13, "size": 1 }, "EOPIE": { "description": "End of operation interrupt\n enable", "offset": 12, "size": 1 }, "ERRIE": { "description": "Error interrupt enable", "offset": 10, "size": 1 }, "OPTWRE": { "description": "Option bytes write enable", "offset": 9, "size": 1 }, "LOCK": { "description": "Lock", "offset": 7, "size": 1 }, "STRT": { "description": "Start", "offset": 6, "size": 1 }, "OPTER": { "description": "Option byte erase", "offset": 5, "size": 1 }, "OPTPG": { "description": "Option byte programming", "offset": 4, "size": 1 }, "MER": { "description": "Mass erase", "offset": 2, "size": 1 }, "PER": { "description": "Page erase", "offset": 1, "size": 1 }, "PG": { "description": "Programming", "offset": 0, "size": 1 } } } }, "AR": { "description": "Flash address register", "offset": 20, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "write-only", "children": { "fields": { "FAR": { "description": "Flash address", "offset": 0, "size": 32 } } } }, "OBR": { "description": "Option byte register", "offset": 28, "size": 32, "reset_value": 4294967042, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "OPTERR": { "description": "Option byte error", "offset": 0, "size": 1 }, "LEVEL1_PROT": { "description": "Level 1 protection status", "offset": 1, "size": 1 }, "LEVEL2_PROT": { "description": "Level 2 protection status", "offset": 2, "size": 1 }, "WDG_SW": { "description": "WDG_SW", "offset": 8, "size": 1 }, "nRST_STOP": { "description": "nRST_STOP", "offset": 9, "size": 1 }, "nRST_STDBY": { "description": "nRST_STDBY", "offset": 10, "size": 1 }, "BOOT1": { "description": "BOOT1", "offset": 12, "size": 1 }, "VDDA_MONITOR": { "description": "VDDA_MONITOR", "offset": 13, "size": 1 }, "SRAM_PARITY_CHECK": { "description": "SRAM_PARITY_CHECK", "offset": 14, "size": 1 }, "Data0": { "description": "Data0", "offset": 16, "size": 8 }, "Data1": { "description": "Data1", "offset": 24, "size": 8 } } } }, "WRPR": { "description": "Write protection register", "offset": 32, "size": 32, "reset_value": 4294967295, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "WRP": { "description": "Write protect", "offset": 0, "size": 32 } } } } } } }, "RCC": { "description": "Reset and clock control", "children": { "registers": { "CR": { "description": "Clock control register", "offset": 0, "size": 32, "reset_value": 131, "reset_mask": 4294967295, "children": { "fields": { "HSION": { "description": "Internal High Speed clock\n enable", "offset": 0, "size": 1 }, "HSIRDY": { "description": "Internal High Speed clock ready\n flag", "offset": 1, "size": 1, "access": "read-only" }, "HSITRIM": { "description": "Internal High Speed clock\n trimming", "offset": 3, "size": 5 }, "HSICAL": { "description": "Internal High Speed clock\n Calibration", "offset": 8, "size": 8, "access": "read-only" }, "HSEON": { "description": "External High Speed clock\n enable", "offset": 16, "size": 1 }, "HSERDY": { "description": "External High Speed clock ready\n flag", "offset": 17, "size": 1, "access": "read-only" }, "HSEBYP": { "description": "External High Speed clock\n Bypass", "offset": 18, "size": 1 }, "CSSON": { "description": "Clock Security System\n enable", "offset": 19, "size": 1 }, "PLLON": { "description": "PLL enable", "offset": 24, "size": 1 }, "PLLRDY": { "description": "PLL clock ready flag", "offset": 25, "size": 1, "access": "read-only" } } } }, "CFGR": { "description": "Clock configuration register\n (RCC_CFGR)", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "SW": { "description": "System clock Switch", "offset": 0, "size": 2 }, "SWS": { "description": "System Clock Switch Status", "offset": 2, "size": 2, "access": "read-only" }, "HPRE": { "description": "AHB prescaler", "offset": 4, "size": 4 }, "PPRE1": { "description": "APB Low speed prescaler\n (APB1)", "offset": 8, "size": 3 }, "PPRE2": { "description": "APB high speed prescaler\n (APB2)", "offset": 11, "size": 3 }, "PLLSRC": { "description": "PLL entry clock source", "offset": 15, "size": 2 }, "PLLXTPRE": { "description": "HSE divider for PLL entry", "offset": 17, "size": 1 }, "PLLMUL": { "description": "PLL Multiplication Factor", "offset": 18, "size": 4 }, "USBPRES": { "description": "USB prescaler", "offset": 22, "size": 1 }, "MCO": { "description": "Microcontroller clock\n output", "offset": 24, "size": 3 }, "MCOF": { "description": "Microcontroller Clock Output\n Flag", "offset": 28, "size": 1, "access": "read-only" }, "I2SSRC": { "description": "I2S external clock source\n selection", "offset": 23, "size": 1 } } } }, "CIR": { "description": "Clock interrupt register\n (RCC_CIR)", "offset": 8, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "LSIRDYF": { "description": "LSI Ready Interrupt flag", "offset": 0, "size": 1, "access": "read-only" }, "LSERDYF": { "description": "LSE Ready Interrupt flag", "offset": 1, "size": 1, "access": "read-only" }, "HSIRDYF": { "description": "HSI Ready Interrupt flag", "offset": 2, "size": 1, "access": "read-only" }, "HSERDYF": { "description": "HSE Ready Interrupt flag", "offset": 3, "size": 1, "access": "read-only" }, "PLLRDYF": { "description": "PLL Ready Interrupt flag", "offset": 4, "size": 1, "access": "read-only" }, "CSSF": { "description": "Clock Security System Interrupt\n flag", "offset": 7, "size": 1, "access": "read-only" }, "LSIRDYIE": { "description": "LSI Ready Interrupt Enable", "offset": 8, "size": 1 }, "LSERDYIE": { "description": "LSE Ready Interrupt Enable", "offset": 9, "size": 1 }, "HSIRDYIE": { "description": "HSI Ready Interrupt Enable", "offset": 10, "size": 1 }, "HSERDYIE": { "description": "HSE Ready Interrupt Enable", "offset": 11, "size": 1 }, "PLLRDYIE": { "description": "PLL Ready Interrupt Enable", "offset": 12, "size": 1 }, "LSIRDYC": { "description": "LSI Ready Interrupt Clear", "offset": 16, "size": 1, "access": "write-only" }, "LSERDYC": { "description": "LSE Ready Interrupt Clear", "offset": 17, "size": 1, "access": "write-only" }, "HSIRDYC": { "description": "HSI Ready Interrupt Clear", "offset": 18, "size": 1, "access": "write-only" }, "HSERDYC": { "description": "HSE Ready Interrupt Clear", "offset": 19, "size": 1, "access": "write-only" }, "PLLRDYC": { "description": "PLL Ready Interrupt Clear", "offset": 20, "size": 1, "access": "write-only" }, "CSSC": { "description": "Clock security system interrupt\n clear", "offset": 23, "size": 1, "access": "write-only" } } } }, "APB2RSTR": { "description": "APB2 peripheral reset register\n (RCC_APB2RSTR)", "offset": 12, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "SYSCFGRST": { "description": "SYSCFG and COMP reset", "offset": 0, "size": 1 }, "TIM1RST": { "description": "TIM1 timer reset", "offset": 11, "size": 1 }, "SPI1RST": { "description": "SPI 1 reset", "offset": 12, "size": 1 }, "TIM8RST": { "description": "TIM8 timer reset", "offset": 13, "size": 1 }, "USART1RST": { "description": "USART1 reset", "offset": 14, "size": 1 }, "TIM15RST": { "description": "TIM15 timer reset", "offset": 16, "size": 1 }, "TIM16RST": { "description": "TIM16 timer reset", "offset": 17, "size": 1 }, "TIM17RST": { "description": "TIM17 timer reset", "offset": 18, "size": 1 } } } }, "APB1RSTR": { "description": "APB1 peripheral reset register\n (RCC_APB1RSTR)", "offset": 16, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "TIM2RST": { "description": "Timer 2 reset", "offset": 0, "size": 1 }, "TIM3RST": { "description": "Timer 3 reset", "offset": 1, "size": 1 }, "TIM4RST": { "description": "Timer 14 reset", "offset": 2, "size": 1 }, "TIM6RST": { "description": "Timer 6 reset", "offset": 4, "size": 1 }, "TIM7RST": { "description": "Timer 7 reset", "offset": 5, "size": 1 }, "WWDGRST": { "description": "Window watchdog reset", "offset": 11, "size": 1 }, "SPI2RST": { "description": "SPI2 reset", "offset": 14, "size": 1 }, "SPI3RST": { "description": "SPI3 reset", "offset": 15, "size": 1 }, "USART2RST": { "description": "USART 2 reset", "offset": 17, "size": 1 }, "USART3RST": { "description": "USART3 reset", "offset": 18, "size": 1 }, "UART4RST": { "description": "UART 4 reset", "offset": 19, "size": 1 }, "UART5RST": { "description": "UART 5 reset", "offset": 20, "size": 1 }, "I2C1RST": { "description": "I2C1 reset", "offset": 21, "size": 1 }, "I2C2RST": { "description": "I2C2 reset", "offset": 22, "size": 1 }, "USBRST": { "description": "USB reset", "offset": 23, "size": 1 }, "CANRST": { "description": "CAN reset", "offset": 25, "size": 1 }, "PWRRST": { "description": "Power interface reset", "offset": 28, "size": 1 }, "DACRST": { "description": "DAC interface reset", "offset": 29, "size": 1 }, "I2C3RST": { "description": "I2C3 reset", "offset": 30, "size": 1 } } } }, "AHBENR": { "description": "AHB Peripheral Clock enable register\n (RCC_AHBENR)", "offset": 20, "size": 32, "reset_value": 20, "reset_mask": 4294967295, "children": { "fields": { "DMAEN": { "description": "DMA1 clock enable", "offset": 0, "size": 1 }, "DMA2EN": { "description": "DMA2 clock enable", "offset": 1, "size": 1 }, "SRAMEN": { "description": "SRAM interface clock\n enable", "offset": 2, "size": 1 }, "FLITFEN": { "description": "FLITF clock enable", "offset": 4, "size": 1 }, "FMCEN": { "description": "FMC clock enable", "offset": 5, "size": 1 }, "CRCEN": { "description": "CRC clock enable", "offset": 6, "size": 1 }, "IOPHEN": { "description": "IO port H clock enable", "offset": 16, "size": 1 }, "IOPAEN": { "description": "I/O port A clock enable", "offset": 17, "size": 1 }, "IOPBEN": { "description": "I/O port B clock enable", "offset": 18, "size": 1 }, "IOPCEN": { "description": "I/O port C clock enable", "offset": 19, "size": 1 }, "IOPDEN": { "description": "I/O port D clock enable", "offset": 20, "size": 1 }, "IOPEEN": { "description": "I/O port E clock enable", "offset": 21, "size": 1 }, "IOPFEN": { "description": "I/O port F clock enable", "offset": 22, "size": 1 }, "IOPGEN": { "description": "I/O port G clock enable", "offset": 23, "size": 1 }, "TSCEN": { "description": "Touch sensing controller clock\n enable", "offset": 24, "size": 1 }, "ADC12EN": { "description": "ADC1 and ADC2 clock enable", "offset": 28, "size": 1 }, "ADC34EN": { "description": "ADC3 and ADC4 clock enable", "offset": 29, "size": 1 } } } }, "APB2ENR": { "description": "APB2 peripheral clock enable register\n (RCC_APB2ENR)", "offset": 24, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "SYSCFGEN": { "description": "SYSCFG clock enable", "offset": 0, "size": 1 }, "TIM1EN": { "description": "TIM1 Timer clock enable", "offset": 11, "size": 1 }, "SPI1EN": { "description": "SPI 1 clock enable", "offset": 12, "size": 1 }, "TIM8EN": { "description": "TIM8 Timer clock enable", "offset": 13, "size": 1 }, "USART1EN": { "description": "USART1 clock enable", "offset": 14, "size": 1 }, "TIM15EN": { "description": "TIM15 timer clock enable", "offset": 16, "size": 1 }, "TIM16EN": { "description": "TIM16 timer clock enable", "offset": 17, "size": 1 }, "TIM17EN": { "description": "TIM17 timer clock enable", "offset": 18, "size": 1 } } } }, "APB1ENR": { "description": "APB1 peripheral clock enable register\n (RCC_APB1ENR)", "offset": 28, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "TIM2EN": { "description": "Timer 2 clock enable", "offset": 0, "size": 1 }, "TIM3EN": { "description": "Timer 3 clock enable", "offset": 1, "size": 1 }, "TIM4EN": { "description": "Timer 4 clock enable", "offset": 2, "size": 1 }, "TIM6EN": { "description": "Timer 6 clock enable", "offset": 4, "size": 1 }, "TIM7EN": { "description": "Timer 7 clock enable", "offset": 5, "size": 1 }, "WWDGEN": { "description": "Window watchdog clock\n enable", "offset": 11, "size": 1 }, "SPI2EN": { "description": "SPI 2 clock enable", "offset": 14, "size": 1 }, "SPI3EN": { "description": "SPI 3 clock enable", "offset": 15, "size": 1 }, "USART2EN": { "description": "USART 2 clock enable", "offset": 17, "size": 1 }, "USART3EN": { "description": "USART 3 clock enable", "offset": 18, "size": 1 }, "USART4EN": { "description": "USART 4 clock enable", "offset": 19, "size": 1 }, "USART5EN": { "description": "USART 5 clock enable", "offset": 20, "size": 1 }, "I2C1EN": { "description": "I2C 1 clock enable", "offset": 21, "size": 1 }, "I2C2EN": { "description": "I2C 2 clock enable", "offset": 22, "size": 1 }, "USBEN": { "description": "USB clock enable", "offset": 23, "size": 1 }, "CANEN": { "description": "CAN clock enable", "offset": 25, "size": 1 }, "DAC2EN": { "description": "DAC2 interface clock\n enable", "offset": 26, "size": 1 }, "PWREN": { "description": "Power interface clock\n enable", "offset": 28, "size": 1 }, "DACEN": { "description": "DAC interface clock enable", "offset": 29, "size": 1 }, "I2C3EN": { "description": "I2C3 clock enable", "offset": 30, "size": 1 } } } }, "BDCR": { "description": "Backup domain control register\n (RCC_BDCR)", "offset": 32, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "LSEON": { "description": "External Low Speed oscillator\n enable", "offset": 0, "size": 1 }, "LSERDY": { "description": "External Low Speed oscillator\n ready", "offset": 1, "size": 1, "access": "read-only" }, "LSEBYP": { "description": "External Low Speed oscillator\n bypass", "offset": 2, "size": 1 }, "LSEDRV": { "description": "LSE oscillator drive\n capability", "offset": 3, "size": 2 }, "RTCSEL": { "description": "RTC clock source selection", "offset": 8, "size": 2 }, "RTCEN": { "description": "RTC clock enable", "offset": 15, "size": 1 }, "BDRST": { "description": "Backup domain software\n reset", "offset": 16, "size": 1 } } } }, "CSR": { "description": "Control/status register\n (RCC_CSR)", "offset": 36, "size": 32, "reset_value": 201326592, "reset_mask": 4294967295, "children": { "fields": { "LSION": { "description": "Internal low speed oscillator\n enable", "offset": 0, "size": 1 }, "LSIRDY": { "description": "Internal low speed oscillator\n ready", "offset": 1, "size": 1, "access": "read-only" }, "RMVF": { "description": "Remove reset flag", "offset": 24, "size": 1 }, "OBLRSTF": { "description": "Option byte loader reset\n flag", "offset": 25, "size": 1 }, "PINRSTF": { "description": "PIN reset flag", "offset": 26, "size": 1 }, "PORRSTF": { "description": "POR/PDR reset flag", "offset": 27, "size": 1 }, "SFTRSTF": { "description": "Software reset flag", "offset": 28, "size": 1 }, "IWDGRSTF": { "description": "Independent watchdog reset\n flag", "offset": 29, "size": 1 }, "WWDGRSTF": { "description": "Window watchdog reset flag", "offset": 30, "size": 1 }, "LPWRRSTF": { "description": "Low-power reset flag", "offset": 31, "size": 1 } } } }, "AHBRSTR": { "description": "AHB peripheral reset register", "offset": 40, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FMCRST": { "description": "FMC reset", "offset": 5, "size": 1 }, "IOPHRST": { "description": "I/O port H reset", "offset": 16, "size": 1 }, "IOPARST": { "description": "I/O port A reset", "offset": 17, "size": 1 }, "IOPBRST": { "description": "I/O port B reset", "offset": 18, "size": 1 }, "IOPCRST": { "description": "I/O port C reset", "offset": 19, "size": 1 }, "IOPDRST": { "description": "I/O port D reset", "offset": 20, "size": 1 }, "IOPERST": { "description": "I/O port E reset", "offset": 21, "size": 1 }, "IOPFRST": { "description": "I/O port F reset", "offset": 22, "size": 1 }, "IOPGRST": { "description": "Touch sensing controller\n reset", "offset": 23, "size": 1 }, "TSCRST": { "description": "Touch sensing controller\n reset", "offset": 24, "size": 1 }, "ADC12RST": { "description": "ADC1 and ADC2 reset", "offset": 28, "size": 1 }, "ADC34RST": { "description": "ADC3 and ADC4 reset", "offset": 29, "size": 1 } } } }, "CFGR2": { "description": "Clock configuration register 2", "offset": 44, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "PREDIV": { "description": "PREDIV division factor", "offset": 0, "size": 4 }, "ADC12PRES": { "description": "ADC1 and ADC2 prescaler", "offset": 4, "size": 5 }, "ADC34PRES": { "description": "ADC3 and ADC4 prescaler", "offset": 9, "size": 5 } } } }, "CFGR3": { "description": "Clock configuration register 3", "offset": 48, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "USART1SW": { "description": "USART1 clock source\n selection", "offset": 0, "size": 2 }, "I2C1SW": { "description": "I2C1 clock source\n selection", "offset": 4, "size": 1 }, "I2C2SW": { "description": "I2C2 clock source\n selection", "offset": 5, "size": 1 }, "I2C3SW": { "description": "I2C3 clock source\n selection", "offset": 6, "size": 1 }, "USART2SW": { "description": "USART2 clock source\n selection", "offset": 16, "size": 2 }, "USART3SW": { "description": "USART3 clock source\n selection", "offset": 18, "size": 2 }, "TIM1SW": { "description": "Timer1 clock source\n selection", "offset": 8, "size": 1 }, "TIM8SW": { "description": "Timer8 clock source\n selection", "offset": 9, "size": 1 }, "UART4SW": { "description": "UART4 clock source\n selection", "offset": 20, "size": 2 }, "UART5SW": { "description": "UART5 clock source\n selection", "offset": 22, "size": 2 } } } } } } }, "DMA1": { "description": "DMA controller 1", "children": { "registers": { "ISR": { "description": "DMA interrupt status register\n (DMA_ISR)", "offset": 0, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "GIF1": { "description": "Channel 1 Global interrupt\n flag", "offset": 0, "size": 1 }, "TCIF1": { "description": "Channel 1 Transfer Complete\n flag", "offset": 1, "size": 1 }, "HTIF1": { "description": "Channel 1 Half Transfer Complete\n flag", "offset": 2, "size": 1 }, "TEIF1": { "description": "Channel 1 Transfer Error\n flag", "offset": 3, "size": 1 }, "GIF2": { "description": "Channel 2 Global interrupt\n flag", "offset": 4, "size": 1 }, "TCIF2": { "description": "Channel 2 Transfer Complete\n flag", "offset": 5, "size": 1 }, "HTIF2": { "description": "Channel 2 Half Transfer Complete\n flag", "offset": 6, "size": 1 }, "TEIF2": { "description": "Channel 2 Transfer Error\n flag", "offset": 7, "size": 1 }, "GIF3": { "description": "Channel 3 Global interrupt\n flag", "offset": 8, "size": 1 }, "TCIF3": { "description": "Channel 3 Transfer Complete\n flag", "offset": 9, "size": 1 }, "HTIF3": { "description": "Channel 3 Half Transfer Complete\n flag", "offset": 10, "size": 1 }, "TEIF3": { "description": "Channel 3 Transfer Error\n flag", "offset": 11, "size": 1 }, "GIF4": { "description": "Channel 4 Global interrupt\n flag", "offset": 12, "size": 1 }, "TCIF4": { "description": "Channel 4 Transfer Complete\n flag", "offset": 13, "size": 1 }, "HTIF4": { "description": "Channel 4 Half Transfer Complete\n flag", "offset": 14, "size": 1 }, "TEIF4": { "description": "Channel 4 Transfer Error\n flag", "offset": 15, "size": 1 }, "GIF5": { "description": "Channel 5 Global interrupt\n flag", "offset": 16, "size": 1 }, "TCIF5": { "description": "Channel 5 Transfer Complete\n flag", "offset": 17, "size": 1 }, "HTIF5": { "description": "Channel 5 Half Transfer Complete\n flag", "offset": 18, "size": 1 }, "TEIF5": { "description": "Channel 5 Transfer Error\n flag", "offset": 19, "size": 1 }, "GIF6": { "description": "Channel 6 Global interrupt\n flag", "offset": 20, "size": 1 }, "TCIF6": { "description": "Channel 6 Transfer Complete\n flag", "offset": 21, "size": 1 }, "HTIF6": { "description": "Channel 6 Half Transfer Complete\n flag", "offset": 22, "size": 1 }, "TEIF6": { "description": "Channel 6 Transfer Error\n flag", "offset": 23, "size": 1 }, "GIF7": { "description": "Channel 7 Global interrupt\n flag", "offset": 24, "size": 1 }, "TCIF7": { "description": "Channel 7 Transfer Complete\n flag", "offset": 25, "size": 1 }, "HTIF7": { "description": "Channel 7 Half Transfer Complete\n flag", "offset": 26, "size": 1 }, "TEIF7": { "description": "Channel 7 Transfer Error\n flag", "offset": 27, "size": 1 } } } }, "IFCR": { "description": "DMA interrupt flag clear register\n (DMA_IFCR)", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "write-only", "children": { "fields": { "CGIF1": { "description": "Channel 1 Global interrupt\n clear", "offset": 0, "size": 1 }, "CTCIF1": { "description": "Channel 1 Transfer Complete\n clear", "offset": 1, "size": 1 }, "CHTIF1": { "description": "Channel 1 Half Transfer\n clear", "offset": 2, "size": 1 }, "CTEIF1": { "description": "Channel 1 Transfer Error\n clear", "offset": 3, "size": 1 }, "CGIF2": { "description": "Channel 2 Global interrupt\n clear", "offset": 4, "size": 1 }, "CTCIF2": { "description": "Channel 2 Transfer Complete\n clear", "offset": 5, "size": 1 }, "CHTIF2": { "description": "Channel 2 Half Transfer\n clear", "offset": 6, "size": 1 }, "CTEIF2": { "description": "Channel 2 Transfer Error\n clear", "offset": 7, "size": 1 }, "CGIF3": { "description": "Channel 3 Global interrupt\n clear", "offset": 8, "size": 1 }, "CTCIF3": { "description": "Channel 3 Transfer Complete\n clear", "offset": 9, "size": 1 }, "CHTIF3": { "description": "Channel 3 Half Transfer\n clear", "offset": 10, "size": 1 }, "CTEIF3": { "description": "Channel 3 Transfer Error\n clear", "offset": 11, "size": 1 }, "CGIF4": { "description": "Channel 4 Global interrupt\n clear", "offset": 12, "size": 1 }, "CTCIF4": { "description": "Channel 4 Transfer Complete\n clear", "offset": 13, "size": 1 }, "CHTIF4": { "description": "Channel 4 Half Transfer\n clear", "offset": 14, "size": 1 }, "CTEIF4": { "description": "Channel 4 Transfer Error\n clear", "offset": 15, "size": 1 }, "CGIF5": { "description": "Channel 5 Global interrupt\n clear", "offset": 16, "size": 1 }, "CTCIF5": { "description": "Channel 5 Transfer Complete\n clear", "offset": 17, "size": 1 }, "CHTIF5": { "description": "Channel 5 Half Transfer\n clear", "offset": 18, "size": 1 }, "CTEIF5": { "description": "Channel 5 Transfer Error\n clear", "offset": 19, "size": 1 }, "CGIF6": { "description": "Channel 6 Global interrupt\n clear", "offset": 20, "size": 1 }, "CTCIF6": { "description": "Channel 6 Transfer Complete\n clear", "offset": 21, "size": 1 }, "CHTIF6": { "description": "Channel 6 Half Transfer\n clear", "offset": 22, "size": 1 }, "CTEIF6": { "description": "Channel 6 Transfer Error\n clear", "offset": 23, "size": 1 }, "CGIF7": { "description": "Channel 7 Global interrupt\n clear", "offset": 24, "size": 1 }, "CTCIF7": { "description": "Channel 7 Transfer Complete\n clear", "offset": 25, "size": 1 }, "CHTIF7": { "description": "Channel 7 Half Transfer\n clear", "offset": 26, "size": 1 }, "CTEIF7": { "description": "Channel 7 Transfer Error\n clear", "offset": 27, "size": 1 } } } }, "CCR1": { "description": "DMA channel configuration register\n (DMA_CCR)", "offset": 8, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "EN": { "description": "Channel enable", "offset": 0, "size": 1 }, "TCIE": { "description": "Transfer complete interrupt\n enable", "offset": 1, "size": 1 }, "HTIE": { "description": "Half Transfer interrupt\n enable", "offset": 2, "size": 1 }, "TEIE": { "description": "Transfer error interrupt\n enable", "offset": 3, "size": 1 }, "DIR": { "description": "Data transfer direction", "offset": 4, "size": 1 }, "CIRC": { "description": "Circular mode", "offset": 5, "size": 1 }, "PINC": { "description": "Peripheral increment mode", "offset": 6, "size": 1 }, "MINC": { "description": "Memory increment mode", "offset": 7, "size": 1 }, "PSIZE": { "description": "Peripheral size", "offset": 8, "size": 2 }, "MSIZE": { "description": "Memory size", "offset": 10, "size": 2 }, "PL": { "description": "Channel Priority level", "offset": 12, "size": 2 }, "MEM2MEM": { "description": "Memory to memory mode", "offset": 14, "size": 1 } } } }, "CNDTR1": { "description": "DMA channel 1 number of data\n register", "offset": 12, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "NDT": { "description": "Number of data to transfer", "offset": 0, "size": 16 } } } }, "CPAR1": { "description": "DMA channel 1 peripheral address\n register", "offset": 16, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "PA": { "description": "Peripheral address", "offset": 0, "size": 32 } } } }, "CMAR1": { "description": "DMA channel 1 memory address\n register", "offset": 20, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "MA": { "description": "Memory address", "offset": 0, "size": 32 } } } }, "CCR2": { "description": "DMA channel configuration register\n (DMA_CCR)", "offset": 28, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "EN": { "description": "Channel enable", "offset": 0, "size": 1 }, "TCIE": { "description": "Transfer complete interrupt\n enable", "offset": 1, "size": 1 }, "HTIE": { "description": "Half Transfer interrupt\n enable", "offset": 2, "size": 1 }, "TEIE": { "description": "Transfer error interrupt\n enable", "offset": 3, "size": 1 }, "DIR": { "description": "Data transfer direction", "offset": 4, "size": 1 }, "CIRC": { "description": "Circular mode", "offset": 5, "size": 1 }, "PINC": { "description": "Peripheral increment mode", "offset": 6, "size": 1 }, "MINC": { "description": "Memory increment mode", "offset": 7, "size": 1 }, "PSIZE": { "description": "Peripheral size", "offset": 8, "size": 2 }, "MSIZE": { "description": "Memory size", "offset": 10, "size": 2 }, "PL": { "description": "Channel Priority level", "offset": 12, "size": 2 }, "MEM2MEM": { "description": "Memory to memory mode", "offset": 14, "size": 1 } } } }, "CNDTR2": { "description": "DMA channel 2 number of data\n register", "offset": 32, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "NDT": { "description": "Number of data to transfer", "offset": 0, "size": 16 } } } }, "CPAR2": { "description": "DMA channel 2 peripheral address\n register", "offset": 36, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "PA": { "description": "Peripheral address", "offset": 0, "size": 32 } } } }, "CMAR2": { "description": "DMA channel 2 memory address\n register", "offset": 40, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "MA": { "description": "Memory address", "offset": 0, "size": 32 } } } }, "CCR3": { "description": "DMA channel configuration register\n (DMA_CCR)", "offset": 48, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "EN": { "description": "Channel enable", "offset": 0, "size": 1 }, "TCIE": { "description": "Transfer complete interrupt\n enable", "offset": 1, "size": 1 }, "HTIE": { "description": "Half Transfer interrupt\n enable", "offset": 2, "size": 1 }, "TEIE": { "description": "Transfer error interrupt\n enable", "offset": 3, "size": 1 }, "DIR": { "description": "Data transfer direction", "offset": 4, "size": 1 }, "CIRC": { "description": "Circular mode", "offset": 5, "size": 1 }, "PINC": { "description": "Peripheral increment mode", "offset": 6, "size": 1 }, "MINC": { "description": "Memory increment mode", "offset": 7, "size": 1 }, "PSIZE": { "description": "Peripheral size", "offset": 8, "size": 2 }, "MSIZE": { "description": "Memory size", "offset": 10, "size": 2 }, "PL": { "description": "Channel Priority level", "offset": 12, "size": 2 }, "MEM2MEM": { "description": "Memory to memory mode", "offset": 14, "size": 1 } } } }, "CNDTR3": { "description": "DMA channel 3 number of data\n register", "offset": 52, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "NDT": { "description": "Number of data to transfer", "offset": 0, "size": 16 } } } }, "CPAR3": { "description": "DMA channel 3 peripheral address\n register", "offset": 56, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "PA": { "description": "Peripheral address", "offset": 0, "size": 32 } } } }, "CMAR3": { "description": "DMA channel 3 memory address\n register", "offset": 60, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "MA": { "description": "Memory address", "offset": 0, "size": 32 } } } }, "CCR4": { "description": "DMA channel configuration register\n (DMA_CCR)", "offset": 68, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "EN": { "description": "Channel enable", "offset": 0, "size": 1 }, "TCIE": { "description": "Transfer complete interrupt\n enable", "offset": 1, "size": 1 }, "HTIE": { "description": "Half Transfer interrupt\n enable", "offset": 2, "size": 1 }, "TEIE": { "description": "Transfer error interrupt\n enable", "offset": 3, "size": 1 }, "DIR": { "description": "Data transfer direction", "offset": 4, "size": 1 }, "CIRC": { "description": "Circular mode", "offset": 5, "size": 1 }, "PINC": { "description": "Peripheral increment mode", "offset": 6, "size": 1 }, "MINC": { "description": "Memory increment mode", "offset": 7, "size": 1 }, "PSIZE": { "description": "Peripheral size", "offset": 8, "size": 2 }, "MSIZE": { "description": "Memory size", "offset": 10, "size": 2 }, "PL": { "description": "Channel Priority level", "offset": 12, "size": 2 }, "MEM2MEM": { "description": "Memory to memory mode", "offset": 14, "size": 1 } } } }, "CNDTR4": { "description": "DMA channel 4 number of data\n register", "offset": 72, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "NDT": { "description": "Number of data to transfer", "offset": 0, "size": 16 } } } }, "CPAR4": { "description": "DMA channel 4 peripheral address\n register", "offset": 76, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "PA": { "description": "Peripheral address", "offset": 0, "size": 32 } } } }, "CMAR4": { "description": "DMA channel 4 memory address\n register", "offset": 80, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "MA": { "description": "Memory address", "offset": 0, "size": 32 } } } }, "CCR5": { "description": "DMA channel configuration register\n (DMA_CCR)", "offset": 88, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "EN": { "description": "Channel enable", "offset": 0, "size": 1 }, "TCIE": { "description": "Transfer complete interrupt\n enable", "offset": 1, "size": 1 }, "HTIE": { "description": "Half Transfer interrupt\n enable", "offset": 2, "size": 1 }, "TEIE": { "description": "Transfer error interrupt\n enable", "offset": 3, "size": 1 }, "DIR": { "description": "Data transfer direction", "offset": 4, "size": 1 }, "CIRC": { "description": "Circular mode", "offset": 5, "size": 1 }, "PINC": { "description": "Peripheral increment mode", "offset": 6, "size": 1 }, "MINC": { "description": "Memory increment mode", "offset": 7, "size": 1 }, "PSIZE": { "description": "Peripheral size", "offset": 8, "size": 2 }, "MSIZE": { "description": "Memory size", "offset": 10, "size": 2 }, "PL": { "description": "Channel Priority level", "offset": 12, "size": 2 }, "MEM2MEM": { "description": "Memory to memory mode", "offset": 14, "size": 1 } } } }, "CNDTR5": { "description": "DMA channel 5 number of data\n register", "offset": 92, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "NDT": { "description": "Number of data to transfer", "offset": 0, "size": 16 } } } }, "CPAR5": { "description": "DMA channel 5 peripheral address\n register", "offset": 96, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "PA": { "description": "Peripheral address", "offset": 0, "size": 32 } } } }, "CMAR5": { "description": "DMA channel 5 memory address\n register", "offset": 100, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "MA": { "description": "Memory address", "offset": 0, "size": 32 } } } }, "CCR6": { "description": "DMA channel configuration register\n (DMA_CCR)", "offset": 108, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "EN": { "description": "Channel enable", "offset": 0, "size": 1 }, "TCIE": { "description": "Transfer complete interrupt\n enable", "offset": 1, "size": 1 }, "HTIE": { "description": "Half Transfer interrupt\n enable", "offset": 2, "size": 1 }, "TEIE": { "description": "Transfer error interrupt\n enable", "offset": 3, "size": 1 }, "DIR": { "description": "Data transfer direction", "offset": 4, "size": 1 }, "CIRC": { "description": "Circular mode", "offset": 5, "size": 1 }, "PINC": { "description": "Peripheral increment mode", "offset": 6, "size": 1 }, "MINC": { "description": "Memory increment mode", "offset": 7, "size": 1 }, "PSIZE": { "description": "Peripheral size", "offset": 8, "size": 2 }, "MSIZE": { "description": "Memory size", "offset": 10, "size": 2 }, "PL": { "description": "Channel Priority level", "offset": 12, "size": 2 }, "MEM2MEM": { "description": "Memory to memory mode", "offset": 14, "size": 1 } } } }, "CNDTR6": { "description": "DMA channel 6 number of data\n register", "offset": 112, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "NDT": { "description": "Number of data to transfer", "offset": 0, "size": 16 } } } }, "CPAR6": { "description": "DMA channel 6 peripheral address\n register", "offset": 116, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "PA": { "description": "Peripheral address", "offset": 0, "size": 32 } } } }, "CMAR6": { "description": "DMA channel 6 memory address\n register", "offset": 120, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "MA": { "description": "Memory address", "offset": 0, "size": 32 } } } }, "CCR7": { "description": "DMA channel configuration register\n (DMA_CCR)", "offset": 128, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "EN": { "description": "Channel enable", "offset": 0, "size": 1 }, "TCIE": { "description": "Transfer complete interrupt\n enable", "offset": 1, "size": 1 }, "HTIE": { "description": "Half Transfer interrupt\n enable", "offset": 2, "size": 1 }, "TEIE": { "description": "Transfer error interrupt\n enable", "offset": 3, "size": 1 }, "DIR": { "description": "Data transfer direction", "offset": 4, "size": 1 }, "CIRC": { "description": "Circular mode", "offset": 5, "size": 1 }, "PINC": { "description": "Peripheral increment mode", "offset": 6, "size": 1 }, "MINC": { "description": "Memory increment mode", "offset": 7, "size": 1 }, "PSIZE": { "description": "Peripheral size", "offset": 8, "size": 2 }, "MSIZE": { "description": "Memory size", "offset": 10, "size": 2 }, "PL": { "description": "Channel Priority level", "offset": 12, "size": 2 }, "MEM2MEM": { "description": "Memory to memory mode", "offset": 14, "size": 1 } } } }, "CNDTR7": { "description": "DMA channel 7 number of data\n register", "offset": 132, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "NDT": { "description": "Number of data to transfer", "offset": 0, "size": 16 } } } }, "CPAR7": { "description": "DMA channel 7 peripheral address\n register", "offset": 136, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "PA": { "description": "Peripheral address", "offset": 0, "size": 32 } } } }, "CMAR7": { "description": "DMA channel 7 memory address\n register", "offset": 140, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "MA": { "description": "Memory address", "offset": 0, "size": 32 } } } } } } }, "FPU": { "description": "Floting point unit", "children": { "registers": { "FPCCR": { "description": "Floating-point context control\n register", "offset": 0, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "LSPACT": { "description": "LSPACT", "offset": 0, "size": 1 }, "USER": { "description": "USER", "offset": 1, "size": 1 }, "THREAD": { "description": "THREAD", "offset": 3, "size": 1 }, "HFRDY": { "description": "HFRDY", "offset": 4, "size": 1 }, "MMRDY": { "description": "MMRDY", "offset": 5, "size": 1 }, "BFRDY": { "description": "BFRDY", "offset": 6, "size": 1 }, "MONRDY": { "description": "MONRDY", "offset": 8, "size": 1 }, "LSPEN": { "description": "LSPEN", "offset": 30, "size": 1 }, "ASPEN": { "description": "ASPEN", "offset": 31, "size": 1 } } } }, "FPCAR": { "description": "Floating-point context address\n register", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "ADDRESS": { "description": "Location of unpopulated\n floating-point", "offset": 3, "size": 29 } } } }, "FPSCR": { "description": "Floating-point status control\n register", "offset": 8, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IOC": { "description": "Invalid operation cumulative exception\n bit", "offset": 0, "size": 1 }, "DZC": { "description": "Division by zero cumulative exception\n bit.", "offset": 1, "size": 1 }, "OFC": { "description": "Overflow cumulative exception\n bit", "offset": 2, "size": 1 }, "UFC": { "description": "Underflow cumulative exception\n bit", "offset": 3, "size": 1 }, "IXC": { "description": "Inexact cumulative exception\n bit", "offset": 4, "size": 1 }, "IDC": { "description": "Input denormal cumulative exception\n bit.", "offset": 7, "size": 1 }, "RMode": { "description": "Rounding Mode control\n field", "offset": 22, "size": 2 }, "FZ": { "description": "Flush-to-zero mode control\n bit:", "offset": 24, "size": 1 }, "DN": { "description": "Default NaN mode control\n bit", "offset": 25, "size": 1 }, "AHP": { "description": "Alternative half-precision control\n bit", "offset": 26, "size": 1 }, "V": { "description": "Overflow condition code\n flag", "offset": 28, "size": 1 }, "C": { "description": "Carry condition code flag", "offset": 29, "size": 1 }, "Z": { "description": "Zero condition code flag", "offset": 30, "size": 1 }, "N": { "description": "Negative condition code\n flag", "offset": 31, "size": 1 } } } } } } }, "TIM2": { "description": "General purpose timer", "children": { "registers": { "CR1": { "description": "control register 1", "offset": 0, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CEN": { "description": "Counter enable", "offset": 0, "size": 1 }, "UDIS": { "description": "Update disable", "offset": 1, "size": 1 }, "URS": { "description": "Update request source", "offset": 2, "size": 1 }, "OPM": { "description": "One-pulse mode", "offset": 3, "size": 1 }, "DIR": { "description": "Direction", "offset": 4, "size": 1 }, "CMS": { "description": "Center-aligned mode\n selection", "offset": 5, "size": 2 }, "ARPE": { "description": "Auto-reload preload enable", "offset": 7, "size": 1 }, "CKD": { "description": "Clock division", "offset": 8, "size": 2 }, "UIFREMAP": { "description": "UIF status bit remapping", "offset": 11, "size": 1 } } } }, "CR2": { "description": "control register 2", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "TI1S": { "description": "TI1 selection", "offset": 7, "size": 1 }, "MMS": { "description": "Master mode selection", "offset": 4, "size": 3 }, "CCDS": { "description": "Capture/compare DMA\n selection", "offset": 3, "size": 1 } } } }, "SMCR": { "description": "slave mode control register", "offset": 8, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "SMS": { "description": "Slave mode selection", "offset": 0, "size": 3 }, "OCCS": { "description": "OCREF clear selection", "offset": 3, "size": 1 }, "TS": { "description": "Trigger selection", "offset": 4, "size": 3 }, "MSM": { "description": "Master/Slave mode", "offset": 7, "size": 1 }, "ETF": { "description": "External trigger filter", "offset": 8, "size": 4 }, "ETPS": { "description": "External trigger prescaler", "offset": 12, "size": 2 }, "ECE": { "description": "External clock enable", "offset": 14, "size": 1 }, "ETP": { "description": "External trigger polarity", "offset": 15, "size": 1 }, "SMS_3": { "description": "Slave mode selection bit3", "offset": 16, "size": 1 } } } }, "DIER": { "description": "DMA/Interrupt enable register", "offset": 12, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "TDE": { "description": "Trigger DMA request enable", "offset": 14, "size": 1 }, "CC4DE": { "description": "Capture/Compare 4 DMA request\n enable", "offset": 12, "size": 1 }, "CC3DE": { "description": "Capture/Compare 3 DMA request\n enable", "offset": 11, "size": 1 }, "CC2DE": { "description": "Capture/Compare 2 DMA request\n enable", "offset": 10, "size": 1 }, "CC1DE": { "description": "Capture/Compare 1 DMA request\n enable", "offset": 9, "size": 1 }, "UDE": { "description": "Update DMA request enable", "offset": 8, "size": 1 }, "TIE": { "description": "Trigger interrupt enable", "offset": 6, "size": 1 }, "CC4IE": { "description": "Capture/Compare 4 interrupt\n enable", "offset": 4, "size": 1 }, "CC3IE": { "description": "Capture/Compare 3 interrupt\n enable", "offset": 3, "size": 1 }, "CC2IE": { "description": "Capture/Compare 2 interrupt\n enable", "offset": 2, "size": 1 }, "CC1IE": { "description": "Capture/Compare 1 interrupt\n enable", "offset": 1, "size": 1 }, "UIE": { "description": "Update interrupt enable", "offset": 0, "size": 1 } } } }, "SR": { "description": "status register", "offset": 16, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CC4OF": { "description": "Capture/Compare 4 overcapture\n flag", "offset": 12, "size": 1 }, "CC3OF": { "description": "Capture/Compare 3 overcapture\n flag", "offset": 11, "size": 1 }, "CC2OF": { "description": "Capture/compare 2 overcapture\n flag", "offset": 10, "size": 1 }, "CC1OF": { "description": "Capture/Compare 1 overcapture\n flag", "offset": 9, "size": 1 }, "TIF": { "description": "Trigger interrupt flag", "offset": 6, "size": 1 }, "CC4IF": { "description": "Capture/Compare 4 interrupt\n flag", "offset": 4, "size": 1 }, "CC3IF": { "description": "Capture/Compare 3 interrupt\n flag", "offset": 3, "size": 1 }, "CC2IF": { "description": "Capture/Compare 2 interrupt\n flag", "offset": 2, "size": 1 }, "CC1IF": { "description": "Capture/compare 1 interrupt\n flag", "offset": 1, "size": 1 }, "UIF": { "description": "Update interrupt flag", "offset": 0, "size": 1 } } } }, "EGR": { "description": "event generation register", "offset": 20, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "write-only", "children": { "fields": { "TG": { "description": "Trigger generation", "offset": 6, "size": 1 }, "CC4G": { "description": "Capture/compare 4\n generation", "offset": 4, "size": 1 }, "CC3G": { "description": "Capture/compare 3\n generation", "offset": 3, "size": 1 }, "CC2G": { "description": "Capture/compare 2\n generation", "offset": 2, "size": 1 }, "CC1G": { "description": "Capture/compare 1\n generation", "offset": 1, "size": 1 }, "UG": { "description": "Update generation", "offset": 0, "size": 1 } } } }, "CCMR1_Output": { "description": "capture/compare mode register 1 (output\n mode)", "offset": 24, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CC1S": { "description": "Capture/Compare 1\n selection", "offset": 0, "size": 2 }, "OC1FE": { "description": "Output compare 1 fast\n enable", "offset": 2, "size": 1 }, "OC1PE": { "description": "Output compare 1 preload\n enable", "offset": 3, "size": 1 }, "OC1M": { "description": "Output compare 1 mode", "offset": 4, "size": 3 }, "OC1CE": { "description": "Output compare 1 clear\n enable", "offset": 7, "size": 1 }, "CC2S": { "description": "Capture/Compare 2\n selection", "offset": 8, "size": 2 }, "OC2FE": { "description": "Output compare 2 fast\n enable", "offset": 10, "size": 1 }, "OC2PE": { "description": "Output compare 2 preload\n enable", "offset": 11, "size": 1 }, "OC2M": { "description": "Output compare 2 mode", "offset": 12, "size": 3 }, "OC2CE": { "description": "Output compare 2 clear\n enable", "offset": 15, "size": 1 }, "OC1M_3": { "description": "Output compare 1 mode bit\n 3", "offset": 16, "size": 1 }, "OC2M_3": { "description": "Output compare 2 mode bit\n 3", "offset": 24, "size": 1 } } } }, "CCMR1_Input": { "description": "capture/compare mode register 1 (input\n mode)", "offset": 24, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IC2F": { "description": "Input capture 2 filter", "offset": 12, "size": 4 }, "IC2PSC": { "description": "Input capture 2 prescaler", "offset": 10, "size": 2 }, "CC2S": { "description": "Capture/compare 2\n selection", "offset": 8, "size": 2 }, "IC1F": { "description": "Input capture 1 filter", "offset": 4, "size": 4 }, "IC1PSC": { "description": "Input capture 1 prescaler", "offset": 2, "size": 2 }, "CC1S": { "description": "Capture/Compare 1\n selection", "offset": 0, "size": 2 } } } }, "CCMR2_Output": { "description": "capture/compare mode register 2 (output\n mode)", "offset": 28, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CC3S": { "description": "Capture/Compare 3\n selection", "offset": 0, "size": 2 }, "OC3FE": { "description": "Output compare 3 fast\n enable", "offset": 2, "size": 1 }, "OC3PE": { "description": "Output compare 3 preload\n enable", "offset": 3, "size": 1 }, "OC3M": { "description": "Output compare 3 mode", "offset": 4, "size": 3 }, "OC3CE": { "description": "Output compare 3 clear\n enable", "offset": 7, "size": 1 }, "CC4S": { "description": "Capture/Compare 4\n selection", "offset": 8, "size": 2 }, "OC4FE": { "description": "Output compare 4 fast\n enable", "offset": 10, "size": 1 }, "OC4PE": { "description": "Output compare 4 preload\n enable", "offset": 11, "size": 1 }, "OC4M": { "description": "Output compare 4 mode", "offset": 12, "size": 3 }, "O24CE": { "description": "Output compare 4 clear\n enable", "offset": 15, "size": 1 }, "OC3M_3": { "description": "Output compare 3 mode bit3", "offset": 16, "size": 1 }, "OC4M_3": { "description": "Output compare 4 mode bit3", "offset": 24, "size": 1 } } } }, "CCMR2_Input": { "description": "capture/compare mode register 2 (input\n mode)", "offset": 28, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IC4F": { "description": "Input capture 4 filter", "offset": 12, "size": 4 }, "IC4PSC": { "description": "Input capture 4 prescaler", "offset": 10, "size": 2 }, "CC4S": { "description": "Capture/Compare 4\n selection", "offset": 8, "size": 2 }, "IC3F": { "description": "Input capture 3 filter", "offset": 4, "size": 4 }, "IC3PSC": { "description": "Input capture 3 prescaler", "offset": 2, "size": 2 }, "CC3S": { "description": "Capture/Compare 3\n selection", "offset": 0, "size": 2 } } } }, "CCER": { "description": "capture/compare enable\n register", "offset": 32, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CC1E": { "description": "Capture/Compare 1 output\n enable", "offset": 0, "size": 1 }, "CC1P": { "description": "Capture/Compare 1 output\n Polarity", "offset": 1, "size": 1 }, "CC1NP": { "description": "Capture/Compare 1 output\n Polarity", "offset": 3, "size": 1 }, "CC2E": { "description": "Capture/Compare 2 output\n enable", "offset": 4, "size": 1 }, "CC2P": { "description": "Capture/Compare 2 output\n Polarity", "offset": 5, "size": 1 }, "CC2NP": { "description": "Capture/Compare 2 output\n Polarity", "offset": 7, "size": 1 }, "CC3E": { "description": "Capture/Compare 3 output\n enable", "offset": 8, "size": 1 }, "CC3P": { "description": "Capture/Compare 3 output\n Polarity", "offset": 9, "size": 1 }, "CC3NP": { "description": "Capture/Compare 3 output\n Polarity", "offset": 11, "size": 1 }, "CC4E": { "description": "Capture/Compare 4 output\n enable", "offset": 12, "size": 1 }, "CC4P": { "description": "Capture/Compare 3 output\n Polarity", "offset": 13, "size": 1 }, "CC4NP": { "description": "Capture/Compare 3 output\n Polarity", "offset": 15, "size": 1 } } } }, "CNT": { "description": "counter", "offset": 36, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CNTL": { "description": "Low counter value", "offset": 0, "size": 16 }, "CNTH": { "description": "High counter value", "offset": 16, "size": 15 }, "CNT_or_UIFCPY": { "description": "if IUFREMAP=0 than CNT with read write\n access else UIFCPY with read only\n access", "offset": 31, "size": 1 } } } }, "PSC": { "description": "prescaler", "offset": 40, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "PSC": { "description": "Prescaler value", "offset": 0, "size": 16 } } } }, "ARR": { "description": "auto-reload register", "offset": 44, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "ARRL": { "description": "Low Auto-reload value", "offset": 0, "size": 16 }, "ARRH": { "description": "High Auto-reload value", "offset": 16, "size": 16 } } } }, "CCR1": { "description": "capture/compare register 1", "offset": 52, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CCR1L": { "description": "Low Capture/Compare 1\n value", "offset": 0, "size": 16 }, "CCR1H": { "description": "High Capture/Compare 1 value (on\n TIM2)", "offset": 16, "size": 16 } } } }, "CCR2": { "description": "capture/compare register 2", "offset": 56, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CCR2L": { "description": "Low Capture/Compare 2\n value", "offset": 0, "size": 16 }, "CCR2H": { "description": "High Capture/Compare 2 value (on\n TIM2)", "offset": 16, "size": 16 } } } }, "CCR3": { "description": "capture/compare register 3", "offset": 60, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CCR3L": { "description": "Low Capture/Compare value", "offset": 0, "size": 16 }, "CCR3H": { "description": "High Capture/Compare value (on\n TIM2)", "offset": 16, "size": 16 } } } }, "CCR4": { "description": "capture/compare register 4", "offset": 64, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CCR4L": { "description": "Low Capture/Compare value", "offset": 0, "size": 16 }, "CCR4H": { "description": "High Capture/Compare value (on\n TIM2)", "offset": 16, "size": 16 } } } }, "DCR": { "description": "DMA control register", "offset": 72, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DBL": { "description": "DMA burst length", "offset": 8, "size": 5 }, "DBA": { "description": "DMA base address", "offset": 0, "size": 5 } } } }, "DMAR": { "description": "DMA address for full transfer", "offset": 76, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DMAB": { "description": "DMA register for burst\n accesses", "offset": 0, "size": 16 } } } } } } }, "NVIC": { "description": "Nested Vectored Interrupt\n Controller", "children": { "registers": { "ISER0": { "description": "Interrupt Set-Enable Register", "offset": 0, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "SETENA": { "description": "SETENA", "offset": 0, "size": 32 } } } }, "ISER1": { "description": "Interrupt Set-Enable Register", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "SETENA": { "description": "SETENA", "offset": 0, "size": 32 } } } }, "ISER2": { "description": "Interrupt Set-Enable Register", "offset": 8, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "SETENA": { "description": "SETENA", "offset": 0, "size": 32 } } } }, "ICER0": { "description": "Interrupt Clear-Enable\n Register", "offset": 128, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CLRENA": { "description": "CLRENA", "offset": 0, "size": 32 } } } }, "ICER1": { "description": "Interrupt Clear-Enable\n Register", "offset": 132, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CLRENA": { "description": "CLRENA", "offset": 0, "size": 32 } } } }, "ICER2": { "description": "Interrupt Clear-Enable\n Register", "offset": 136, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CLRENA": { "description": "CLRENA", "offset": 0, "size": 32 } } } }, "ISPR0": { "description": "Interrupt Set-Pending Register", "offset": 256, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "SETPEND": { "description": "SETPEND", "offset": 0, "size": 32 } } } }, "ISPR1": { "description": "Interrupt Set-Pending Register", "offset": 260, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "SETPEND": { "description": "SETPEND", "offset": 0, "size": 32 } } } }, "ISPR2": { "description": "Interrupt Set-Pending Register", "offset": 264, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "SETPEND": { "description": "SETPEND", "offset": 0, "size": 32 } } } }, "ICPR0": { "description": "Interrupt Clear-Pending\n Register", "offset": 384, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CLRPEND": { "description": "CLRPEND", "offset": 0, "size": 32 } } } }, "ICPR1": { "description": "Interrupt Clear-Pending\n Register", "offset": 388, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CLRPEND": { "description": "CLRPEND", "offset": 0, "size": 32 } } } }, "ICPR2": { "description": "Interrupt Clear-Pending\n Register", "offset": 392, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CLRPEND": { "description": "CLRPEND", "offset": 0, "size": 32 } } } }, "IABR0": { "description": "Interrupt Active Bit Register", "offset": 512, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "ACTIVE": { "description": "ACTIVE", "offset": 0, "size": 32 } } } }, "IABR1": { "description": "Interrupt Active Bit Register", "offset": 516, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "ACTIVE": { "description": "ACTIVE", "offset": 0, "size": 32 } } } }, "IABR2": { "description": "Interrupt Active Bit Register", "offset": 520, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "ACTIVE": { "description": "ACTIVE", "offset": 0, "size": 32 } } } }, "IPR0": { "description": "Interrupt Priority Register", "offset": 768, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IPR_N0": { "description": "IPR_N0", "offset": 0, "size": 8 }, "IPR_N1": { "description": "IPR_N1", "offset": 8, "size": 8 }, "IPR_N2": { "description": "IPR_N2", "offset": 16, "size": 8 }, "IPR_N3": { "description": "IPR_N3", "offset": 24, "size": 8 } } } }, "IPR1": { "description": "Interrupt Priority Register", "offset": 772, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IPR_N0": { "description": "IPR_N0", "offset": 0, "size": 8 }, "IPR_N1": { "description": "IPR_N1", "offset": 8, "size": 8 }, "IPR_N2": { "description": "IPR_N2", "offset": 16, "size": 8 }, "IPR_N3": { "description": "IPR_N3", "offset": 24, "size": 8 } } } }, "IPR2": { "description": "Interrupt Priority Register", "offset": 776, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IPR_N0": { "description": "IPR_N0", "offset": 0, "size": 8 }, "IPR_N1": { "description": "IPR_N1", "offset": 8, "size": 8 }, "IPR_N2": { "description": "IPR_N2", "offset": 16, "size": 8 }, "IPR_N3": { "description": "IPR_N3", "offset": 24, "size": 8 } } } }, "IPR3": { "description": "Interrupt Priority Register", "offset": 780, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IPR_N0": { "description": "IPR_N0", "offset": 0, "size": 8 }, "IPR_N1": { "description": "IPR_N1", "offset": 8, "size": 8 }, "IPR_N2": { "description": "IPR_N2", "offset": 16, "size": 8 }, "IPR_N3": { "description": "IPR_N3", "offset": 24, "size": 8 } } } }, "IPR4": { "description": "Interrupt Priority Register", "offset": 784, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IPR_N0": { "description": "IPR_N0", "offset": 0, "size": 8 }, "IPR_N1": { "description": "IPR_N1", "offset": 8, "size": 8 }, "IPR_N2": { "description": "IPR_N2", "offset": 16, "size": 8 }, "IPR_N3": { "description": "IPR_N3", "offset": 24, "size": 8 } } } }, "IPR5": { "description": "Interrupt Priority Register", "offset": 788, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IPR_N0": { "description": "IPR_N0", "offset": 0, "size": 8 }, "IPR_N1": { "description": "IPR_N1", "offset": 8, "size": 8 }, "IPR_N2": { "description": "IPR_N2", "offset": 16, "size": 8 }, "IPR_N3": { "description": "IPR_N3", "offset": 24, "size": 8 } } } }, "IPR6": { "description": "Interrupt Priority Register", "offset": 792, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IPR_N0": { "description": "IPR_N0", "offset": 0, "size": 8 }, "IPR_N1": { "description": "IPR_N1", "offset": 8, "size": 8 }, "IPR_N2": { "description": "IPR_N2", "offset": 16, "size": 8 }, "IPR_N3": { "description": "IPR_N3", "offset": 24, "size": 8 } } } }, "IPR7": { "description": "Interrupt Priority Register", "offset": 796, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IPR_N0": { "description": "IPR_N0", "offset": 0, "size": 8 }, "IPR_N1": { "description": "IPR_N1", "offset": 8, "size": 8 }, "IPR_N2": { "description": "IPR_N2", "offset": 16, "size": 8 }, "IPR_N3": { "description": "IPR_N3", "offset": 24, "size": 8 } } } }, "IPR8": { "description": "Interrupt Priority Register", "offset": 800, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IPR_N0": { "description": "IPR_N0", "offset": 0, "size": 8 }, "IPR_N1": { "description": "IPR_N1", "offset": 8, "size": 8 }, "IPR_N2": { "description": "IPR_N2", "offset": 16, "size": 8 }, "IPR_N3": { "description": "IPR_N3", "offset": 24, "size": 8 } } } }, "IPR9": { "description": "Interrupt Priority Register", "offset": 804, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IPR_N0": { "description": "IPR_N0", "offset": 0, "size": 8 }, "IPR_N1": { "description": "IPR_N1", "offset": 8, "size": 8 }, "IPR_N2": { "description": "IPR_N2", "offset": 16, "size": 8 }, "IPR_N3": { "description": "IPR_N3", "offset": 24, "size": 8 } } } }, "IPR10": { "description": "Interrupt Priority Register", "offset": 808, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IPR_N0": { "description": "IPR_N0", "offset": 0, "size": 8 }, "IPR_N1": { "description": "IPR_N1", "offset": 8, "size": 8 }, "IPR_N2": { "description": "IPR_N2", "offset": 16, "size": 8 }, "IPR_N3": { "description": "IPR_N3", "offset": 24, "size": 8 } } } }, "IPR11": { "description": "Interrupt Priority Register", "offset": 812, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IPR_N0": { "description": "IPR_N0", "offset": 0, "size": 8 }, "IPR_N1": { "description": "IPR_N1", "offset": 8, "size": 8 }, "IPR_N2": { "description": "IPR_N2", "offset": 16, "size": 8 }, "IPR_N3": { "description": "IPR_N3", "offset": 24, "size": 8 } } } }, "IPR12": { "description": "Interrupt Priority Register", "offset": 816, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IPR_N0": { "description": "IPR_N0", "offset": 0, "size": 8 }, "IPR_N1": { "description": "IPR_N1", "offset": 8, "size": 8 }, "IPR_N2": { "description": "IPR_N2", "offset": 16, "size": 8 }, "IPR_N3": { "description": "IPR_N3", "offset": 24, "size": 8 } } } }, "IPR13": { "description": "Interrupt Priority Register", "offset": 820, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IPR_N0": { "description": "IPR_N0", "offset": 0, "size": 8 }, "IPR_N1": { "description": "IPR_N1", "offset": 8, "size": 8 }, "IPR_N2": { "description": "IPR_N2", "offset": 16, "size": 8 }, "IPR_N3": { "description": "IPR_N3", "offset": 24, "size": 8 } } } }, "IPR14": { "description": "Interrupt Priority Register", "offset": 824, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IPR_N0": { "description": "IPR_N0", "offset": 0, "size": 8 }, "IPR_N1": { "description": "IPR_N1", "offset": 8, "size": 8 }, "IPR_N2": { "description": "IPR_N2", "offset": 16, "size": 8 }, "IPR_N3": { "description": "IPR_N3", "offset": 24, "size": 8 } } } }, "IPR15": { "description": "Interrupt Priority Register", "offset": 828, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IPR_N0": { "description": "IPR_N0", "offset": 0, "size": 8 }, "IPR_N1": { "description": "IPR_N1", "offset": 8, "size": 8 }, "IPR_N2": { "description": "IPR_N2", "offset": 16, "size": 8 }, "IPR_N3": { "description": "IPR_N3", "offset": 24, "size": 8 } } } }, "IPR16": { "description": "Interrupt Priority Register", "offset": 832, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IPR_N0": { "description": "IPR_N0", "offset": 0, "size": 8 }, "IPR_N1": { "description": "IPR_N1", "offset": 8, "size": 8 }, "IPR_N2": { "description": "IPR_N2", "offset": 16, "size": 8 }, "IPR_N3": { "description": "IPR_N3", "offset": 24, "size": 8 } } } }, "IPR17": { "description": "Interrupt Priority Register", "offset": 836, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IPR_N0": { "description": "IPR_N0", "offset": 0, "size": 8 }, "IPR_N1": { "description": "IPR_N1", "offset": 8, "size": 8 }, "IPR_N2": { "description": "IPR_N2", "offset": 16, "size": 8 }, "IPR_N3": { "description": "IPR_N3", "offset": 24, "size": 8 } } } }, "IPR18": { "description": "Interrupt Priority Register", "offset": 840, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IPR_N0": { "description": "IPR_N0", "offset": 0, "size": 8 }, "IPR_N1": { "description": "IPR_N1", "offset": 8, "size": 8 }, "IPR_N2": { "description": "IPR_N2", "offset": 16, "size": 8 }, "IPR_N3": { "description": "IPR_N3", "offset": 24, "size": 8 } } } }, "IPR19": { "description": "Interrupt Priority Register", "offset": 844, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IPR_N0": { "description": "IPR_N0", "offset": 0, "size": 8 }, "IPR_N1": { "description": "IPR_N1", "offset": 8, "size": 8 }, "IPR_N2": { "description": "IPR_N2", "offset": 16, "size": 8 }, "IPR_N3": { "description": "IPR_N3", "offset": 24, "size": 8 } } } }, "IPR20": { "description": "Interrupt Priority Register", "offset": 848, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IPR_N0": { "description": "IPR_N0", "offset": 0, "size": 8 }, "IPR_N1": { "description": "IPR_N1", "offset": 8, "size": 8 }, "IPR_N2": { "description": "IPR_N2", "offset": 16, "size": 8 }, "IPR_N3": { "description": "IPR_N3", "offset": 24, "size": 8 } } } } } } }, "FMC": { "description": "Flexible memory controller", "children": { "registers": { "BCR1": { "description": "SRAM/NOR-Flash chip-select control register\n 1", "offset": 0, "size": 32, "reset_value": 12496, "reset_mask": 4294967295, "children": { "fields": { "CCLKEN": { "description": "CCLKEN", "offset": 20, "size": 1 }, "CBURSTRW": { "description": "CBURSTRW", "offset": 19, "size": 1 }, "ASYNCWAIT": { "description": "ASYNCWAIT", "offset": 15, "size": 1 }, "EXTMOD": { "description": "EXTMOD", "offset": 14, "size": 1 }, "WAITEN": { "description": "WAITEN", "offset": 13, "size": 1 }, "WREN": { "description": "WREN", "offset": 12, "size": 1 }, "WAITCFG": { "description": "WAITCFG", "offset": 11, "size": 1 }, "WAITPOL": { "description": "WAITPOL", "offset": 9, "size": 1 }, "BURSTEN": { "description": "BURSTEN", "offset": 8, "size": 1 }, "FACCEN": { "description": "FACCEN", "offset": 6, "size": 1 }, "MWID": { "description": "MWID", "offset": 4, "size": 2 }, "MTYP": { "description": "MTYP", "offset": 2, "size": 2 }, "MUXEN": { "description": "MUXEN", "offset": 1, "size": 1 }, "MBKEN": { "description": "MBKEN", "offset": 0, "size": 1 } } } }, "BTR1": { "description": "SRAM/NOR-Flash chip-select timing register\n 1", "offset": 4, "size": 32, "reset_value": 4294967295, "reset_mask": 4294967295, "children": { "fields": { "ACCMOD": { "description": "ACCMOD", "offset": 28, "size": 2 }, "DATLAT": { "description": "DATLAT", "offset": 24, "size": 4 }, "CLKDIV": { "description": "CLKDIV", "offset": 20, "size": 4 }, "BUSTURN": { "description": "BUSTURN", "offset": 16, "size": 4 }, "DATAST": { "description": "DATAST", "offset": 8, "size": 8 }, "ADDHLD": { "description": "ADDHLD", "offset": 4, "size": 4 }, "ADDSET": { "description": "ADDSET", "offset": 0, "size": 4 } } } }, "BCR2": { "description": "SRAM/NOR-Flash chip-select control register\n 2", "offset": 8, "size": 32, "reset_value": 12496, "reset_mask": 4294967295, "children": { "fields": { "CBURSTRW": { "description": "CBURSTRW", "offset": 19, "size": 1 }, "ASYNCWAIT": { "description": "ASYNCWAIT", "offset": 15, "size": 1 }, "EXTMOD": { "description": "EXTMOD", "offset": 14, "size": 1 }, "WAITEN": { "description": "WAITEN", "offset": 13, "size": 1 }, "WREN": { "description": "WREN", "offset": 12, "size": 1 }, "WAITCFG": { "description": "WAITCFG", "offset": 11, "size": 1 }, "WRAPMOD": { "description": "WRAPMOD", "offset": 10, "size": 1 }, "WAITPOL": { "description": "WAITPOL", "offset": 9, "size": 1 }, "BURSTEN": { "description": "BURSTEN", "offset": 8, "size": 1 }, "FACCEN": { "description": "FACCEN", "offset": 6, "size": 1 }, "MWID": { "description": "MWID", "offset": 4, "size": 2 }, "MTYP": { "description": "MTYP", "offset": 2, "size": 2 }, "MUXEN": { "description": "MUXEN", "offset": 1, "size": 1 }, "MBKEN": { "description": "MBKEN", "offset": 0, "size": 1 } } } }, "BTR2": { "description": "SRAM/NOR-Flash chip-select timing register\n 2", "offset": 12, "size": 32, "reset_value": 4294967295, "reset_mask": 4294967295, "children": { "fields": { "ACCMOD": { "description": "ACCMOD", "offset": 28, "size": 2 }, "DATLAT": { "description": "DATLAT", "offset": 24, "size": 4 }, "CLKDIV": { "description": "CLKDIV", "offset": 20, "size": 4 }, "BUSTURN": { "description": "BUSTURN", "offset": 16, "size": 4 }, "DATAST": { "description": "DATAST", "offset": 8, "size": 8 }, "ADDHLD": { "description": "ADDHLD", "offset": 4, "size": 4 }, "ADDSET": { "description": "ADDSET", "offset": 0, "size": 4 } } } }, "BCR3": { "description": "SRAM/NOR-Flash chip-select control register\n 3", "offset": 16, "size": 32, "reset_value": 12496, "reset_mask": 4294967295, "children": { "fields": { "CBURSTRW": { "description": "CBURSTRW", "offset": 19, "size": 1 }, "ASYNCWAIT": { "description": "ASYNCWAIT", "offset": 15, "size": 1 }, "EXTMOD": { "description": "EXTMOD", "offset": 14, "size": 1 }, "WAITEN": { "description": "WAITEN", "offset": 13, "size": 1 }, "WREN": { "description": "WREN", "offset": 12, "size": 1 }, "WAITCFG": { "description": "WAITCFG", "offset": 11, "size": 1 }, "WRAPMOD": { "description": "WRAPMOD", "offset": 10, "size": 1 }, "WAITPOL": { "description": "WAITPOL", "offset": 9, "size": 1 }, "BURSTEN": { "description": "BURSTEN", "offset": 8, "size": 1 }, "FACCEN": { "description": "FACCEN", "offset": 6, "size": 1 }, "MWID": { "description": "MWID", "offset": 4, "size": 2 }, "MTYP": { "description": "MTYP", "offset": 2, "size": 2 }, "MUXEN": { "description": "MUXEN", "offset": 1, "size": 1 }, "MBKEN": { "description": "MBKEN", "offset": 0, "size": 1 } } } }, "BTR3": { "description": "SRAM/NOR-Flash chip-select timing register\n 3", "offset": 20, "size": 32, "reset_value": 4294967295, "reset_mask": 4294967295, "children": { "fields": { "ACCMOD": { "description": "ACCMOD", "offset": 28, "size": 2 }, "DATLAT": { "description": "DATLAT", "offset": 24, "size": 4 }, "CLKDIV": { "description": "CLKDIV", "offset": 20, "size": 4 }, "BUSTURN": { "description": "BUSTURN", "offset": 16, "size": 4 }, "DATAST": { "description": "DATAST", "offset": 8, "size": 8 }, "ADDHLD": { "description": "ADDHLD", "offset": 4, "size": 4 }, "ADDSET": { "description": "ADDSET", "offset": 0, "size": 4 } } } }, "BCR4": { "description": "SRAM/NOR-Flash chip-select control register\n 4", "offset": 24, "size": 32, "reset_value": 12496, "reset_mask": 4294967295, "children": { "fields": { "CBURSTRW": { "description": "CBURSTRW", "offset": 19, "size": 1 }, "ASYNCWAIT": { "description": "ASYNCWAIT", "offset": 15, "size": 1 }, "EXTMOD": { "description": "EXTMOD", "offset": 14, "size": 1 }, "WAITEN": { "description": "WAITEN", "offset": 13, "size": 1 }, "WREN": { "description": "WREN", "offset": 12, "size": 1 }, "WAITCFG": { "description": "WAITCFG", "offset": 11, "size": 1 }, "WRAPMOD": { "description": "WRAPMOD", "offset": 10, "size": 1 }, "WAITPOL": { "description": "WAITPOL", "offset": 9, "size": 1 }, "BURSTEN": { "description": "BURSTEN", "offset": 8, "size": 1 }, "FACCEN": { "description": "FACCEN", "offset": 6, "size": 1 }, "MWID": { "description": "MWID", "offset": 4, "size": 2 }, "MTYP": { "description": "MTYP", "offset": 2, "size": 2 }, "MUXEN": { "description": "MUXEN", "offset": 1, "size": 1 }, "MBKEN": { "description": "MBKEN", "offset": 0, "size": 1 } } } }, "BTR4": { "description": "SRAM/NOR-Flash chip-select timing register\n 4", "offset": 28, "size": 32, "reset_value": 4294967295, "reset_mask": 4294967295, "children": { "fields": { "ACCMOD": { "description": "ACCMOD", "offset": 28, "size": 2 }, "DATLAT": { "description": "DATLAT", "offset": 24, "size": 4 }, "CLKDIV": { "description": "CLKDIV", "offset": 20, "size": 4 }, "BUSTURN": { "description": "BUSTURN", "offset": 16, "size": 4 }, "DATAST": { "description": "DATAST", "offset": 8, "size": 8 }, "ADDHLD": { "description": "ADDHLD", "offset": 4, "size": 4 }, "ADDSET": { "description": "ADDSET", "offset": 0, "size": 4 } } } }, "PCR2": { "description": "PC Card/NAND Flash control register\n 2", "offset": 96, "size": 32, "reset_value": 24, "reset_mask": 4294967295, "children": { "fields": { "ECCPS": { "description": "ECCPS", "offset": 17, "size": 3 }, "TAR": { "description": "TAR", "offset": 13, "size": 4 }, "TCLR": { "description": "TCLR", "offset": 9, "size": 4 }, "ECCEN": { "description": "ECCEN", "offset": 6, "size": 1 }, "PWID": { "description": "PWID", "offset": 4, "size": 2 }, "PTYP": { "description": "PTYP", "offset": 3, "size": 1 }, "PBKEN": { "description": "PBKEN", "offset": 2, "size": 1 }, "PWAITEN": { "description": "PWAITEN", "offset": 1, "size": 1 } } } }, "SR2": { "description": "FIFO status and interrupt register\n 2", "offset": 100, "size": 32, "reset_value": 64, "reset_mask": 4294967295, "children": { "fields": { "FEMPT": { "description": "FEMPT", "offset": 6, "size": 1, "access": "read-only" }, "IFEN": { "description": "IFEN", "offset": 5, "size": 1 }, "ILEN": { "description": "ILEN", "offset": 4, "size": 1 }, "IREN": { "description": "IREN", "offset": 3, "size": 1 }, "IFS": { "description": "IFS", "offset": 2, "size": 1 }, "ILS": { "description": "ILS", "offset": 1, "size": 1 }, "IRS": { "description": "IRS", "offset": 0, "size": 1 } } } }, "PMEM2": { "description": "Common memory space timing register\n 2", "offset": 104, "size": 32, "reset_value": 4244438268, "reset_mask": 4294967295, "children": { "fields": { "MEMHIZx": { "description": "MEMHIZx", "offset": 24, "size": 8 }, "MEMHOLDx": { "description": "MEMHOLDx", "offset": 16, "size": 8 }, "MEMWAITx": { "description": "MEMWAITx", "offset": 8, "size": 8 }, "MEMSETx": { "description": "MEMSETx", "offset": 0, "size": 8 } } } }, "PATT2": { "description": "Attribute memory space timing register\n 2", "offset": 108, "size": 32, "reset_value": 4244438268, "reset_mask": 4294967295, "children": { "fields": { "ATTHIZx": { "description": "ATTHIZx", "offset": 24, "size": 8 }, "ATTHOLDx": { "description": "ATTHOLDx", "offset": 16, "size": 8 }, "ATTWAITx": { "description": "ATTWAITx", "offset": 8, "size": 8 }, "ATTSETx": { "description": "ATTSETx", "offset": 0, "size": 8 } } } }, "ECCR2": { "description": "ECC result register 2", "offset": 116, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "ECCx": { "description": "ECCx", "offset": 0, "size": 32 } } } }, "PCR3": { "description": "PC Card/NAND Flash control register\n 3", "offset": 128, "size": 32, "reset_value": 24, "reset_mask": 4294967295, "children": { "fields": { "ECCPS": { "description": "ECCPS", "offset": 17, "size": 3 }, "TAR": { "description": "TAR", "offset": 13, "size": 4 }, "TCLR": { "description": "TCLR", "offset": 9, "size": 4 }, "ECCEN": { "description": "ECCEN", "offset": 6, "size": 1 }, "PWID": { "description": "PWID", "offset": 4, "size": 2 }, "PTYP": { "description": "PTYP", "offset": 3, "size": 1 }, "PBKEN": { "description": "PBKEN", "offset": 2, "size": 1 }, "PWAITEN": { "description": "PWAITEN", "offset": 1, "size": 1 } } } }, "SR3": { "description": "FIFO status and interrupt register\n 3", "offset": 132, "size": 32, "reset_value": 64, "reset_mask": 4294967295, "children": { "fields": { "FEMPT": { "description": "FEMPT", "offset": 6, "size": 1, "access": "read-only" }, "IFEN": { "description": "IFEN", "offset": 5, "size": 1 }, "ILEN": { "description": "ILEN", "offset": 4, "size": 1 }, "IREN": { "description": "IREN", "offset": 3, "size": 1 }, "IFS": { "description": "IFS", "offset": 2, "size": 1 }, "ILS": { "description": "ILS", "offset": 1, "size": 1 }, "IRS": { "description": "IRS", "offset": 0, "size": 1 } } } }, "PMEM3": { "description": "Common memory space timing register\n 3", "offset": 136, "size": 32, "reset_value": 4244438268, "reset_mask": 4294967295, "children": { "fields": { "MEMHIZx": { "description": "MEMHIZx", "offset": 24, "size": 8 }, "MEMHOLDx": { "description": "MEMHOLDx", "offset": 16, "size": 8 }, "MEMWAITx": { "description": "MEMWAITx", "offset": 8, "size": 8 }, "MEMSETx": { "description": "MEMSETx", "offset": 0, "size": 8 } } } }, "PATT3": { "description": "Attribute memory space timing register\n 3", "offset": 140, "size": 32, "reset_value": 4244438268, "reset_mask": 4294967295, "children": { "fields": { "ATTHIZx": { "description": "ATTHIZx", "offset": 24, "size": 8 }, "ATTHOLDx": { "description": "ATTHOLDx", "offset": 16, "size": 8 }, "ATTWAITx": { "description": "ATTWAITx", "offset": 8, "size": 8 }, "ATTSETx": { "description": "ATTSETx", "offset": 0, "size": 8 } } } }, "ECCR3": { "description": "ECC result register 3", "offset": 148, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "ECCx": { "description": "ECCx", "offset": 0, "size": 32 } } } }, "PCR4": { "description": "PC Card/NAND Flash control register\n 4", "offset": 160, "size": 32, "reset_value": 24, "reset_mask": 4294967295, "children": { "fields": { "ECCPS": { "description": "ECCPS", "offset": 17, "size": 3 }, "TAR": { "description": "TAR", "offset": 13, "size": 4 }, "TCLR": { "description": "TCLR", "offset": 9, "size": 4 }, "ECCEN": { "description": "ECCEN", "offset": 6, "size": 1 }, "PWID": { "description": "PWID", "offset": 4, "size": 2 }, "PTYP": { "description": "PTYP", "offset": 3, "size": 1 }, "PBKEN": { "description": "PBKEN", "offset": 2, "size": 1 }, "PWAITEN": { "description": "PWAITEN", "offset": 1, "size": 1 } } } }, "SR4": { "description": "FIFO status and interrupt register\n 4", "offset": 164, "size": 32, "reset_value": 64, "reset_mask": 4294967295, "children": { "fields": { "FEMPT": { "description": "FEMPT", "offset": 6, "size": 1, "access": "read-only" }, "IFEN": { "description": "IFEN", "offset": 5, "size": 1 }, "ILEN": { "description": "ILEN", "offset": 4, "size": 1 }, "IREN": { "description": "IREN", "offset": 3, "size": 1 }, "IFS": { "description": "IFS", "offset": 2, "size": 1 }, "ILS": { "description": "ILS", "offset": 1, "size": 1 }, "IRS": { "description": "IRS", "offset": 0, "size": 1 } } } }, "PMEM4": { "description": "Common memory space timing register\n 4", "offset": 168, "size": 32, "reset_value": 4244438268, "reset_mask": 4294967295, "children": { "fields": { "MEMHIZx": { "description": "MEMHIZx", "offset": 24, "size": 8 }, "MEMHOLDx": { "description": "MEMHOLDx", "offset": 16, "size": 8 }, "MEMWAITx": { "description": "MEMWAITx", "offset": 8, "size": 8 }, "MEMSETx": { "description": "MEMSETx", "offset": 0, "size": 8 } } } }, "PATT4": { "description": "Attribute memory space timing register\n 4", "offset": 172, "size": 32, "reset_value": 4244438268, "reset_mask": 4294967295, "children": { "fields": { "ATTHIZx": { "description": "ATTHIZx", "offset": 24, "size": 8 }, "ATTHOLDx": { "description": "ATTHOLDx", "offset": 16, "size": 8 }, "ATTWAITx": { "description": "ATTWAITx", "offset": 8, "size": 8 }, "ATTSETx": { "description": "ATTSETx", "offset": 0, "size": 8 } } } }, "PIO4": { "description": "I/O space timing register 4", "offset": 176, "size": 32, "reset_value": 4244438268, "reset_mask": 4294967295, "children": { "fields": { "IOHIZx": { "description": "IOHIZx", "offset": 24, "size": 8 }, "IOHOLDx": { "description": "IOHOLDx", "offset": 16, "size": 8 }, "IOWAITx": { "description": "IOWAITx", "offset": 8, "size": 8 }, "IOSETx": { "description": "IOSETx", "offset": 0, "size": 8 } } } }, "BWTR1": { "description": "SRAM/NOR-Flash write timing registers\n 1", "offset": 260, "size": 32, "reset_value": 268435455, "reset_mask": 4294967295, "children": { "fields": { "ACCMOD": { "description": "ACCMOD", "offset": 28, "size": 2 }, "DATLAT": { "description": "DATLAT", "offset": 24, "size": 4 }, "CLKDIV": { "description": "CLKDIV", "offset": 20, "size": 4 }, "BUSTURN": { "description": "Bus turnaround phase\n duration", "offset": 16, "size": 4 }, "DATAST": { "description": "DATAST", "offset": 8, "size": 8 }, "ADDHLD": { "description": "ADDHLD", "offset": 4, "size": 4 }, "ADDSET": { "description": "ADDSET", "offset": 0, "size": 4 } } } }, "BWTR2": { "description": "SRAM/NOR-Flash write timing registers\n 2", "offset": 268, "size": 32, "reset_value": 268435455, "reset_mask": 4294967295, "children": { "fields": { "ACCMOD": { "description": "ACCMOD", "offset": 28, "size": 2 }, "DATLAT": { "description": "DATLAT", "offset": 24, "size": 4 }, "CLKDIV": { "description": "CLKDIV", "offset": 20, "size": 4 }, "BUSTURN": { "description": "Bus turnaround phase\n duration", "offset": 16, "size": 4 }, "DATAST": { "description": "DATAST", "offset": 8, "size": 8 }, "ADDHLD": { "description": "ADDHLD", "offset": 4, "size": 4 }, "ADDSET": { "description": "ADDSET", "offset": 0, "size": 4 } } } }, "BWTR3": { "description": "SRAM/NOR-Flash write timing registers\n 3", "offset": 276, "size": 32, "reset_value": 268435455, "reset_mask": 4294967295, "children": { "fields": { "ACCMOD": { "description": "ACCMOD", "offset": 28, "size": 2 }, "DATLAT": { "description": "DATLAT", "offset": 24, "size": 4 }, "CLKDIV": { "description": "CLKDIV", "offset": 20, "size": 4 }, "BUSTURN": { "description": "Bus turnaround phase\n duration", "offset": 16, "size": 4 }, "DATAST": { "description": "DATAST", "offset": 8, "size": 8 }, "ADDHLD": { "description": "ADDHLD", "offset": 4, "size": 4 }, "ADDSET": { "description": "ADDSET", "offset": 0, "size": 4 } } } }, "BWTR4": { "description": "SRAM/NOR-Flash write timing registers\n 4", "offset": 284, "size": 32, "reset_value": 268435455, "reset_mask": 4294967295, "children": { "fields": { "ACCMOD": { "description": "ACCMOD", "offset": 28, "size": 2 }, "DATLAT": { "description": "DATLAT", "offset": 24, "size": 4 }, "CLKDIV": { "description": "CLKDIV", "offset": 20, "size": 4 }, "BUSTURN": { "description": "Bus turnaround phase\n duration", "offset": 16, "size": 4 }, "DATAST": { "description": "DATAST", "offset": 8, "size": 8 }, "ADDHLD": { "description": "ADDHLD", "offset": 4, "size": 4 }, "ADDSET": { "description": "ADDSET", "offset": 0, "size": 4 } } } } } } }, "TIM15": { "description": "General purpose timers", "children": { "registers": { "CR1": { "description": "control register 1", "offset": 0, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CEN": { "description": "Counter enable", "offset": 0, "size": 1 }, "UDIS": { "description": "Update disable", "offset": 1, "size": 1 }, "URS": { "description": "Update request source", "offset": 2, "size": 1 }, "OPM": { "description": "One-pulse mode", "offset": 3, "size": 1 }, "ARPE": { "description": "Auto-reload preload enable", "offset": 7, "size": 1 }, "CKD": { "description": "Clock division", "offset": 8, "size": 2 }, "UIFREMAP": { "description": "UIF status bit remapping", "offset": 11, "size": 1 } } } }, "CR2": { "description": "control register 2", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CCPC": { "description": "Capture/compare preloaded\n control", "offset": 0, "size": 1 }, "CCUS": { "description": "Capture/compare control update\n selection", "offset": 2, "size": 1 }, "CCDS": { "description": "Capture/compare DMA\n selection", "offset": 3, "size": 1 }, "MMS": { "description": "Master mode selection", "offset": 4, "size": 3 }, "TI1S": { "description": "TI1 selection", "offset": 7, "size": 1 }, "OIS1": { "description": "Output Idle state 1", "offset": 8, "size": 1 }, "OIS1N": { "description": "Output Idle state 1", "offset": 9, "size": 1 }, "OIS2": { "description": "Output Idle state 2", "offset": 10, "size": 1 } } } }, "SMCR": { "description": "slave mode control register", "offset": 8, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "SMS": { "description": "Slave mode selection", "offset": 0, "size": 3 }, "TS": { "description": "Trigger selection", "offset": 4, "size": 3 }, "MSM": { "description": "Master/Slave mode", "offset": 7, "size": 1 }, "SMS_3": { "description": "Slave mode selection bit 3", "offset": 16, "size": 1 } } } }, "DIER": { "description": "DMA/Interrupt enable register", "offset": 12, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "UIE": { "description": "Update interrupt enable", "offset": 0, "size": 1 }, "CC1IE": { "description": "Capture/Compare 1 interrupt\n enable", "offset": 1, "size": 1 }, "CC2IE": { "description": "Capture/Compare 2 interrupt\n enable", "offset": 2, "size": 1 }, "COMIE": { "description": "COM interrupt enable", "offset": 5, "size": 1 }, "TIE": { "description": "Trigger interrupt enable", "offset": 6, "size": 1 }, "BIE": { "description": "Break interrupt enable", "offset": 7, "size": 1 }, "UDE": { "description": "Update DMA request enable", "offset": 8, "size": 1 }, "CC1DE": { "description": "Capture/Compare 1 DMA request\n enable", "offset": 9, "size": 1 }, "CC2DE": { "description": "Capture/Compare 2 DMA request\n enable", "offset": 10, "size": 1 }, "COMDE": { "description": "COM DMA request enable", "offset": 13, "size": 1 }, "TDE": { "description": "Trigger DMA request enable", "offset": 14, "size": 1 } } } }, "SR": { "description": "status register", "offset": 16, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CC2OF": { "description": "Capture/compare 2 overcapture\n flag", "offset": 10, "size": 1 }, "CC1OF": { "description": "Capture/Compare 1 overcapture\n flag", "offset": 9, "size": 1 }, "BIF": { "description": "Break interrupt flag", "offset": 7, "size": 1 }, "TIF": { "description": "Trigger interrupt flag", "offset": 6, "size": 1 }, "COMIF": { "description": "COM interrupt flag", "offset": 5, "size": 1 }, "CC2IF": { "description": "Capture/Compare 2 interrupt\n flag", "offset": 2, "size": 1 }, "CC1IF": { "description": "Capture/compare 1 interrupt\n flag", "offset": 1, "size": 1 }, "UIF": { "description": "Update interrupt flag", "offset": 0, "size": 1 } } } }, "EGR": { "description": "event generation register", "offset": 20, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "write-only", "children": { "fields": { "BG": { "description": "Break generation", "offset": 7, "size": 1 }, "TG": { "description": "Trigger generation", "offset": 6, "size": 1 }, "COMG": { "description": "Capture/Compare control update\n generation", "offset": 5, "size": 1 }, "CC2G": { "description": "Capture/compare 2\n generation", "offset": 2, "size": 1 }, "CC1G": { "description": "Capture/compare 1\n generation", "offset": 1, "size": 1 }, "UG": { "description": "Update generation", "offset": 0, "size": 1 } } } }, "CCMR1_Output": { "description": "capture/compare mode register (output\n mode)", "offset": 24, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CC1S": { "description": "Capture/Compare 1\n selection", "offset": 0, "size": 2 }, "OC1FE": { "description": "Output Compare 1 fast\n enable", "offset": 2, "size": 1 }, "OC1PE": { "description": "Output Compare 1 preload\n enable", "offset": 3, "size": 1 }, "OC1M": { "description": "Output Compare 1 mode", "offset": 4, "size": 3 }, "CC2S": { "description": "Capture/Compare 2\n selection", "offset": 8, "size": 2 }, "OC2FE": { "description": "Output Compare 2 fast\n enable", "offset": 10, "size": 1 }, "OC2PE": { "description": "Output Compare 2 preload\n enable", "offset": 11, "size": 1 }, "OC2M": { "description": "Output Compare 2 mode", "offset": 12, "size": 3 }, "OC1M_3": { "description": "Output Compare 1 mode bit\n 3", "offset": 16, "size": 1 }, "OC2M_3": { "description": "Output Compare 2 mode bit\n 3", "offset": 24, "size": 1 } } } }, "CCMR1_Input": { "description": "capture/compare mode register 1 (input\n mode)", "offset": 24, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IC2F": { "description": "Input capture 2 filter", "offset": 12, "size": 4 }, "IC2PSC": { "description": "Input capture 2 prescaler", "offset": 10, "size": 2 }, "CC2S": { "description": "Capture/Compare 2\n selection", "offset": 8, "size": 2 }, "IC1F": { "description": "Input capture 1 filter", "offset": 4, "size": 4 }, "IC1PSC": { "description": "Input capture 1 prescaler", "offset": 2, "size": 2 }, "CC1S": { "description": "Capture/Compare 1\n selection", "offset": 0, "size": 2 } } } }, "CCER": { "description": "capture/compare enable\n register", "offset": 32, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CC2NP": { "description": "Capture/Compare 2 output\n Polarity", "offset": 7, "size": 1 }, "CC2P": { "description": "Capture/Compare 2 output\n Polarity", "offset": 5, "size": 1 }, "CC2E": { "description": "Capture/Compare 2 output\n enable", "offset": 4, "size": 1 }, "CC1NP": { "description": "Capture/Compare 1 output\n Polarity", "offset": 3, "size": 1 }, "CC1NE": { "description": "Capture/Compare 1 complementary output\n enable", "offset": 2, "size": 1 }, "CC1P": { "description": "Capture/Compare 1 output\n Polarity", "offset": 1, "size": 1 }, "CC1E": { "description": "Capture/Compare 1 output\n enable", "offset": 0, "size": 1 } } } }, "CNT": { "description": "counter", "offset": 36, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CNT": { "description": "counter value", "offset": 0, "size": 16 }, "UIFCPY": { "description": "UIF copy", "offset": 31, "size": 1, "access": "read-only" } } } }, "PSC": { "description": "prescaler", "offset": 40, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "PSC": { "description": "Prescaler value", "offset": 0, "size": 16 } } } }, "ARR": { "description": "auto-reload register", "offset": 44, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "ARR": { "description": "Auto-reload value", "offset": 0, "size": 16 } } } }, "RCR": { "description": "repetition counter register", "offset": 48, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "REP": { "description": "Repetition counter value", "offset": 0, "size": 8 } } } }, "CCR1": { "description": "capture/compare register 1", "offset": 52, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CCR1": { "description": "Capture/Compare 1 value", "offset": 0, "size": 16 } } } }, "CCR2": { "description": "capture/compare register 2", "offset": 56, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CCR2": { "description": "Capture/Compare 2 value", "offset": 0, "size": 16 } } } }, "BDTR": { "description": "break and dead-time register", "offset": 68, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "MOE": { "description": "Main output enable", "offset": 15, "size": 1 }, "AOE": { "description": "Automatic output enable", "offset": 14, "size": 1 }, "BKP": { "description": "Break polarity", "offset": 13, "size": 1 }, "BKE": { "description": "Break enable", "offset": 12, "size": 1 }, "OSSR": { "description": "Off-state selection for Run\n mode", "offset": 11, "size": 1 }, "OSSI": { "description": "Off-state selection for Idle\n mode", "offset": 10, "size": 1 }, "LOCK": { "description": "Lock configuration", "offset": 8, "size": 2 }, "DTG": { "description": "Dead-time generator setup", "offset": 0, "size": 8 }, "BKF": { "description": "Break filter", "offset": 16, "size": 4 } } } }, "DCR": { "description": "DMA control register", "offset": 72, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DBL": { "description": "DMA burst length", "offset": 8, "size": 5 }, "DBA": { "description": "DMA base address", "offset": 0, "size": 5 } } } }, "DMAR": { "description": "DMA address for full transfer", "offset": 76, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DMAB": { "description": "DMA register for burst\n accesses", "offset": 0, "size": 16 } } } } } } }, "TIM16": { "description": "General-purpose-timers", "children": { "registers": { "CR1": { "description": "control register 1", "offset": 0, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CEN": { "description": "Counter enable", "offset": 0, "size": 1 }, "UDIS": { "description": "Update disable", "offset": 1, "size": 1 }, "URS": { "description": "Update request source", "offset": 2, "size": 1 }, "OPM": { "description": "One-pulse mode", "offset": 3, "size": 1 }, "ARPE": { "description": "Auto-reload preload enable", "offset": 7, "size": 1 }, "CKD": { "description": "Clock division", "offset": 8, "size": 2 }, "UIFREMAP": { "description": "UIF status bit remapping", "offset": 11, "size": 1 } } } }, "CR2": { "description": "control register 2", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "OIS1N": { "description": "Output Idle state 1", "offset": 9, "size": 1 }, "OIS1": { "description": "Output Idle state 1", "offset": 8, "size": 1 }, "CCDS": { "description": "Capture/compare DMA\n selection", "offset": 3, "size": 1 }, "CCUS": { "description": "Capture/compare control update\n selection", "offset": 2, "size": 1 }, "CCPC": { "description": "Capture/compare preloaded\n control", "offset": 0, "size": 1 } } } }, "DIER": { "description": "DMA/Interrupt enable register", "offset": 12, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "UIE": { "description": "Update interrupt enable", "offset": 0, "size": 1 }, "CC1IE": { "description": "Capture/Compare 1 interrupt\n enable", "offset": 1, "size": 1 }, "COMIE": { "description": "COM interrupt enable", "offset": 5, "size": 1 }, "TIE": { "description": "Trigger interrupt enable", "offset": 6, "size": 1 }, "BIE": { "description": "Break interrupt enable", "offset": 7, "size": 1 }, "UDE": { "description": "Update DMA request enable", "offset": 8, "size": 1 }, "CC1DE": { "description": "Capture/Compare 1 DMA request\n enable", "offset": 9, "size": 1 }, "COMDE": { "description": "COM DMA request enable", "offset": 13, "size": 1 }, "TDE": { "description": "Trigger DMA request enable", "offset": 14, "size": 1 } } } }, "SR": { "description": "status register", "offset": 16, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CC1OF": { "description": "Capture/Compare 1 overcapture\n flag", "offset": 9, "size": 1 }, "BIF": { "description": "Break interrupt flag", "offset": 7, "size": 1 }, "TIF": { "description": "Trigger interrupt flag", "offset": 6, "size": 1 }, "COMIF": { "description": "COM interrupt flag", "offset": 5, "size": 1 }, "CC1IF": { "description": "Capture/compare 1 interrupt\n flag", "offset": 1, "size": 1 }, "UIF": { "description": "Update interrupt flag", "offset": 0, "size": 1 } } } }, "EGR": { "description": "event generation register", "offset": 20, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "write-only", "children": { "fields": { "BG": { "description": "Break generation", "offset": 7, "size": 1 }, "TG": { "description": "Trigger generation", "offset": 6, "size": 1 }, "COMG": { "description": "Capture/Compare control update\n generation", "offset": 5, "size": 1 }, "CC1G": { "description": "Capture/compare 1\n generation", "offset": 1, "size": 1 }, "UG": { "description": "Update generation", "offset": 0, "size": 1 } } } }, "CCMR1_Output": { "description": "capture/compare mode register (output\n mode)", "offset": 24, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CC1S": { "description": "Capture/Compare 1\n selection", "offset": 0, "size": 2 }, "OC1FE": { "description": "Output Compare 1 fast\n enable", "offset": 2, "size": 1 }, "OC1PE": { "description": "Output Compare 1 preload\n enable", "offset": 3, "size": 1 }, "OC1M": { "description": "Output Compare 1 mode", "offset": 4, "size": 3 }, "OC1M_3": { "description": "Output Compare 1 mode", "offset": 16, "size": 1 } } } }, "CCMR1_Input": { "description": "capture/compare mode register 1 (input\n mode)", "offset": 24, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IC1F": { "description": "Input capture 1 filter", "offset": 4, "size": 4 }, "IC1PSC": { "description": "Input capture 1 prescaler", "offset": 2, "size": 2 }, "CC1S": { "description": "Capture/Compare 1\n selection", "offset": 0, "size": 2 } } } }, "CCER": { "description": "capture/compare enable\n register", "offset": 32, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CC1NP": { "description": "Capture/Compare 1 output\n Polarity", "offset": 3, "size": 1 }, "CC1NE": { "description": "Capture/Compare 1 complementary output\n enable", "offset": 2, "size": 1 }, "CC1P": { "description": "Capture/Compare 1 output\n Polarity", "offset": 1, "size": 1 }, "CC1E": { "description": "Capture/Compare 1 output\n enable", "offset": 0, "size": 1 } } } }, "CNT": { "description": "counter", "offset": 36, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CNT": { "description": "counter value", "offset": 0, "size": 16 }, "UIFCPY": { "description": "UIF Copy", "offset": 31, "size": 1, "access": "read-only" } } } }, "PSC": { "description": "prescaler", "offset": 40, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "PSC": { "description": "Prescaler value", "offset": 0, "size": 16 } } } }, "ARR": { "description": "auto-reload register", "offset": 44, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "ARR": { "description": "Auto-reload value", "offset": 0, "size": 16 } } } }, "RCR": { "description": "repetition counter register", "offset": 48, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "REP": { "description": "Repetition counter value", "offset": 0, "size": 8 } } } }, "CCR1": { "description": "capture/compare register 1", "offset": 52, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CCR1": { "description": "Capture/Compare 1 value", "offset": 0, "size": 16 } } } }, "BDTR": { "description": "break and dead-time register", "offset": 68, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DTG": { "description": "Dead-time generator setup", "offset": 0, "size": 8 }, "LOCK": { "description": "Lock configuration", "offset": 8, "size": 2 }, "OSSI": { "description": "Off-state selection for Idle\n mode", "offset": 10, "size": 1 }, "OSSR": { "description": "Off-state selection for Run\n mode", "offset": 11, "size": 1 }, "BKE": { "description": "Break enable", "offset": 12, "size": 1 }, "BKP": { "description": "Break polarity", "offset": 13, "size": 1 }, "AOE": { "description": "Automatic output enable", "offset": 14, "size": 1 }, "MOE": { "description": "Main output enable", "offset": 15, "size": 1 }, "BKF": { "description": "Break filter", "offset": 16, "size": 4 } } } }, "DCR": { "description": "DMA control register", "offset": 72, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DBL": { "description": "DMA burst length", "offset": 8, "size": 5 }, "DBA": { "description": "DMA base address", "offset": 0, "size": 5 } } } }, "DMAR": { "description": "DMA address for full transfer", "offset": 76, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DMAB": { "description": "DMA register for burst\n accesses", "offset": 0, "size": 16 } } } }, "OR": { "description": "option register", "offset": 80, "size": 32, "reset_value": 0, "reset_mask": 4294967295 } } } }, "TIM17": { "description": "General purpose timer", "children": { "registers": { "CR1": { "description": "control register 1", "offset": 0, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CEN": { "description": "Counter enable", "offset": 0, "size": 1 }, "UDIS": { "description": "Update disable", "offset": 1, "size": 1 }, "URS": { "description": "Update request source", "offset": 2, "size": 1 }, "OPM": { "description": "One-pulse mode", "offset": 3, "size": 1 }, "ARPE": { "description": "Auto-reload preload enable", "offset": 7, "size": 1 }, "CKD": { "description": "Clock division", "offset": 8, "size": 2 }, "UIFREMAP": { "description": "UIF status bit remapping", "offset": 11, "size": 1 } } } }, "CR2": { "description": "control register 2", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "OIS1N": { "description": "Output Idle state 1", "offset": 9, "size": 1 }, "OIS1": { "description": "Output Idle state 1", "offset": 8, "size": 1 }, "CCDS": { "description": "Capture/compare DMA\n selection", "offset": 3, "size": 1 }, "CCUS": { "description": "Capture/compare control update\n selection", "offset": 2, "size": 1 }, "CCPC": { "description": "Capture/compare preloaded\n control", "offset": 0, "size": 1 } } } }, "DIER": { "description": "DMA/Interrupt enable register", "offset": 12, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "UIE": { "description": "Update interrupt enable", "offset": 0, "size": 1 }, "CC1IE": { "description": "Capture/Compare 1 interrupt\n enable", "offset": 1, "size": 1 }, "COMIE": { "description": "COM interrupt enable", "offset": 5, "size": 1 }, "TIE": { "description": "Trigger interrupt enable", "offset": 6, "size": 1 }, "BIE": { "description": "Break interrupt enable", "offset": 7, "size": 1 }, "UDE": { "description": "Update DMA request enable", "offset": 8, "size": 1 }, "CC1DE": { "description": "Capture/Compare 1 DMA request\n enable", "offset": 9, "size": 1 }, "COMDE": { "description": "COM DMA request enable", "offset": 13, "size": 1 }, "TDE": { "description": "Trigger DMA request enable", "offset": 14, "size": 1 } } } }, "SR": { "description": "status register", "offset": 16, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CC1OF": { "description": "Capture/Compare 1 overcapture\n flag", "offset": 9, "size": 1 }, "BIF": { "description": "Break interrupt flag", "offset": 7, "size": 1 }, "TIF": { "description": "Trigger interrupt flag", "offset": 6, "size": 1 }, "COMIF": { "description": "COM interrupt flag", "offset": 5, "size": 1 }, "CC1IF": { "description": "Capture/compare 1 interrupt\n flag", "offset": 1, "size": 1 }, "UIF": { "description": "Update interrupt flag", "offset": 0, "size": 1 } } } }, "EGR": { "description": "event generation register", "offset": 20, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "write-only", "children": { "fields": { "BG": { "description": "Break generation", "offset": 7, "size": 1 }, "TG": { "description": "Trigger generation", "offset": 6, "size": 1 }, "COMG": { "description": "Capture/Compare control update\n generation", "offset": 5, "size": 1 }, "CC1G": { "description": "Capture/compare 1\n generation", "offset": 1, "size": 1 }, "UG": { "description": "Update generation", "offset": 0, "size": 1 } } } }, "CCMR1_Output": { "description": "capture/compare mode register (output\n mode)", "offset": 24, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CC1S": { "description": "Capture/Compare 1\n selection", "offset": 0, "size": 2 }, "OC1FE": { "description": "Output Compare 1 fast\n enable", "offset": 2, "size": 1 }, "OC1PE": { "description": "Output Compare 1 preload\n enable", "offset": 3, "size": 1 }, "OC1M": { "description": "Output Compare 1 mode", "offset": 4, "size": 3 }, "OC1M_3": { "description": "Output Compare 1 mode", "offset": 16, "size": 1 } } } }, "CCMR1_Input": { "description": "capture/compare mode register 1 (input\n mode)", "offset": 24, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IC1F": { "description": "Input capture 1 filter", "offset": 4, "size": 4 }, "IC1PSC": { "description": "Input capture 1 prescaler", "offset": 2, "size": 2 }, "CC1S": { "description": "Capture/Compare 1\n selection", "offset": 0, "size": 2 } } } }, "CCER": { "description": "capture/compare enable\n register", "offset": 32, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CC1NP": { "description": "Capture/Compare 1 output\n Polarity", "offset": 3, "size": 1 }, "CC1NE": { "description": "Capture/Compare 1 complementary output\n enable", "offset": 2, "size": 1 }, "CC1P": { "description": "Capture/Compare 1 output\n Polarity", "offset": 1, "size": 1 }, "CC1E": { "description": "Capture/Compare 1 output\n enable", "offset": 0, "size": 1 } } } }, "CNT": { "description": "counter", "offset": 36, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CNT": { "description": "counter value", "offset": 0, "size": 16 }, "UIFCPY": { "description": "UIF Copy", "offset": 31, "size": 1, "access": "read-only" } } } }, "PSC": { "description": "prescaler", "offset": 40, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "PSC": { "description": "Prescaler value", "offset": 0, "size": 16 } } } }, "ARR": { "description": "auto-reload register", "offset": 44, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "ARR": { "description": "Auto-reload value", "offset": 0, "size": 16 } } } }, "RCR": { "description": "repetition counter register", "offset": 48, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "REP": { "description": "Repetition counter value", "offset": 0, "size": 8 } } } }, "CCR1": { "description": "capture/compare register 1", "offset": 52, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CCR1": { "description": "Capture/Compare 1 value", "offset": 0, "size": 16 } } } }, "BDTR": { "description": "break and dead-time register", "offset": 68, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DTG": { "description": "Dead-time generator setup", "offset": 0, "size": 8 }, "LOCK": { "description": "Lock configuration", "offset": 8, "size": 2 }, "OSSI": { "description": "Off-state selection for Idle\n mode", "offset": 10, "size": 1 }, "OSSR": { "description": "Off-state selection for Run\n mode", "offset": 11, "size": 1 }, "BKE": { "description": "Break enable", "offset": 12, "size": 1 }, "BKP": { "description": "Break polarity", "offset": 13, "size": 1 }, "AOE": { "description": "Automatic output enable", "offset": 14, "size": 1 }, "MOE": { "description": "Main output enable", "offset": 15, "size": 1 }, "BKF": { "description": "Break filter", "offset": 16, "size": 4 } } } }, "DCR": { "description": "DMA control register", "offset": 72, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DBL": { "description": "DMA burst length", "offset": 8, "size": 5 }, "DBA": { "description": "DMA base address", "offset": 0, "size": 5 } } } }, "DMAR": { "description": "DMA address for full transfer", "offset": 76, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DMAB": { "description": "DMA register for burst\n accesses", "offset": 0, "size": 16 } } } } } } }, "USART1": { "description": "Universal synchronous asynchronous receiver\n transmitter", "children": { "registers": { "CR1": { "description": "Control register 1", "offset": 0, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "EOBIE": { "description": "End of Block interrupt\n enable", "offset": 27, "size": 1 }, "RTOIE": { "description": "Receiver timeout interrupt\n enable", "offset": 26, "size": 1 }, "DEAT": { "description": "Driver Enable assertion\n time", "offset": 21, "size": 5 }, "DEDT": { "description": "Driver Enable deassertion\n time", "offset": 16, "size": 5 }, "OVER8": { "description": "Oversampling mode", "offset": 15, "size": 1 }, "CMIE": { "description": "Character match interrupt\n enable", "offset": 14, "size": 1 }, "MME": { "description": "Mute mode enable", "offset": 13, "size": 1 }, "M": { "description": "Word length", "offset": 12, "size": 1 }, "WAKE": { "description": "Receiver wakeup method", "offset": 11, "size": 1 }, "PCE": { "description": "Parity control enable", "offset": 10, "size": 1 }, "PS": { "description": "Parity selection", "offset": 9, "size": 1 }, "PEIE": { "description": "PE interrupt enable", "offset": 8, "size": 1 }, "TXEIE": { "description": "interrupt enable", "offset": 7, "size": 1 }, "TCIE": { "description": "Transmission complete interrupt\n enable", "offset": 6, "size": 1 }, "RXNEIE": { "description": "RXNE interrupt enable", "offset": 5, "size": 1 }, "IDLEIE": { "description": "IDLE interrupt enable", "offset": 4, "size": 1 }, "TE": { "description": "Transmitter enable", "offset": 3, "size": 1 }, "RE": { "description": "Receiver enable", "offset": 2, "size": 1 }, "UESM": { "description": "USART enable in Stop mode", "offset": 1, "size": 1 }, "UE": { "description": "USART enable", "offset": 0, "size": 1 } } } }, "CR2": { "description": "Control register 2", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "ADD4": { "description": "Address of the USART node", "offset": 28, "size": 4 }, "ADD0": { "description": "Address of the USART node", "offset": 24, "size": 4 }, "RTOEN": { "description": "Receiver timeout enable", "offset": 23, "size": 1 }, "ABRMOD": { "description": "Auto baud rate mode", "offset": 21, "size": 2 }, "ABREN": { "description": "Auto baud rate enable", "offset": 20, "size": 1 }, "MSBFIRST": { "description": "Most significant bit first", "offset": 19, "size": 1 }, "DATAINV": { "description": "Binary data inversion", "offset": 18, "size": 1 }, "TXINV": { "description": "TX pin active level\n inversion", "offset": 17, "size": 1 }, "RXINV": { "description": "RX pin active level\n inversion", "offset": 16, "size": 1 }, "SWAP": { "description": "Swap TX/RX pins", "offset": 15, "size": 1 }, "LINEN": { "description": "LIN mode enable", "offset": 14, "size": 1 }, "STOP": { "description": "STOP bits", "offset": 12, "size": 2 }, "CLKEN": { "description": "Clock enable", "offset": 11, "size": 1 }, "CPOL": { "description": "Clock polarity", "offset": 10, "size": 1 }, "CPHA": { "description": "Clock phase", "offset": 9, "size": 1 }, "LBCL": { "description": "Last bit clock pulse", "offset": 8, "size": 1 }, "LBDIE": { "description": "LIN break detection interrupt\n enable", "offset": 6, "size": 1 }, "LBDL": { "description": "LIN break detection length", "offset": 5, "size": 1 }, "ADDM7": { "description": "7-bit Address Detection/4-bit Address\n Detection", "offset": 4, "size": 1 } } } }, "CR3": { "description": "Control register 3", "offset": 8, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "WUFIE": { "description": "Wakeup from Stop mode interrupt\n enable", "offset": 22, "size": 1 }, "WUS": { "description": "Wakeup from Stop mode interrupt flag\n selection", "offset": 20, "size": 2 }, "SCARCNT": { "description": "Smartcard auto-retry count", "offset": 17, "size": 3 }, "DEP": { "description": "Driver enable polarity\n selection", "offset": 15, "size": 1 }, "DEM": { "description": "Driver enable mode", "offset": 14, "size": 1 }, "DDRE": { "description": "DMA Disable on Reception\n Error", "offset": 13, "size": 1 }, "OVRDIS": { "description": "Overrun Disable", "offset": 12, "size": 1 }, "ONEBIT": { "description": "One sample bit method\n enable", "offset": 11, "size": 1 }, "CTSIE": { "description": "CTS interrupt enable", "offset": 10, "size": 1 }, "CTSE": { "description": "CTS enable", "offset": 9, "size": 1 }, "RTSE": { "description": "RTS enable", "offset": 8, "size": 1 }, "DMAT": { "description": "DMA enable transmitter", "offset": 7, "size": 1 }, "DMAR": { "description": "DMA enable receiver", "offset": 6, "size": 1 }, "SCEN": { "description": "Smartcard mode enable", "offset": 5, "size": 1 }, "NACK": { "description": "Smartcard NACK enable", "offset": 4, "size": 1 }, "HDSEL": { "description": "Half-duplex selection", "offset": 3, "size": 1 }, "IRLP": { "description": "IrDA low-power", "offset": 2, "size": 1 }, "IREN": { "description": "IrDA mode enable", "offset": 1, "size": 1 }, "EIE": { "description": "Error interrupt enable", "offset": 0, "size": 1 } } } }, "BRR": { "description": "Baud rate register", "offset": 12, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DIV_Mantissa": { "description": "mantissa of USARTDIV", "offset": 4, "size": 12 }, "DIV_Fraction": { "description": "fraction of USARTDIV", "offset": 0, "size": 4 } } } }, "GTPR": { "description": "Guard time and prescaler\n register", "offset": 16, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "GT": { "description": "Guard time value", "offset": 8, "size": 8 }, "PSC": { "description": "Prescaler value", "offset": 0, "size": 8 } } } }, "RTOR": { "description": "Receiver timeout register", "offset": 20, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BLEN": { "description": "Block Length", "offset": 24, "size": 8 }, "RTO": { "description": "Receiver timeout value", "offset": 0, "size": 24 } } } }, "RQR": { "description": "Request register", "offset": 24, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "TXFRQ": { "description": "Transmit data flush\n request", "offset": 4, "size": 1 }, "RXFRQ": { "description": "Receive data flush request", "offset": 3, "size": 1 }, "MMRQ": { "description": "Mute mode request", "offset": 2, "size": 1 }, "SBKRQ": { "description": "Send break request", "offset": 1, "size": 1 }, "ABRRQ": { "description": "Auto baud rate request", "offset": 0, "size": 1 } } } }, "ISR": { "description": "Interrupt & status\n register", "offset": 28, "size": 32, "reset_value": 192, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "REACK": { "description": "Receive enable acknowledge\n flag", "offset": 22, "size": 1 }, "TEACK": { "description": "Transmit enable acknowledge\n flag", "offset": 21, "size": 1 }, "WUF": { "description": "Wakeup from Stop mode flag", "offset": 20, "size": 1 }, "RWU": { "description": "Receiver wakeup from Mute\n mode", "offset": 19, "size": 1 }, "SBKF": { "description": "Send break flag", "offset": 18, "size": 1 }, "CMF": { "description": "character match flag", "offset": 17, "size": 1 }, "BUSY": { "description": "Busy flag", "offset": 16, "size": 1 }, "ABRF": { "description": "Auto baud rate flag", "offset": 15, "size": 1 }, "ABRE": { "description": "Auto baud rate error", "offset": 14, "size": 1 }, "EOBF": { "description": "End of block flag", "offset": 12, "size": 1 }, "RTOF": { "description": "Receiver timeout", "offset": 11, "size": 1 }, "CTS": { "description": "CTS flag", "offset": 10, "size": 1 }, "CTSIF": { "description": "CTS interrupt flag", "offset": 9, "size": 1 }, "LBDF": { "description": "LIN break detection flag", "offset": 8, "size": 1 }, "TXE": { "description": "Transmit data register\n empty", "offset": 7, "size": 1 }, "TC": { "description": "Transmission complete", "offset": 6, "size": 1 }, "RXNE": { "description": "Read data register not\n empty", "offset": 5, "size": 1 }, "IDLE": { "description": "Idle line detected", "offset": 4, "size": 1 }, "ORE": { "description": "Overrun error", "offset": 3, "size": 1 }, "NF": { "description": "Noise detected flag", "offset": 2, "size": 1 }, "FE": { "description": "Framing error", "offset": 1, "size": 1 }, "PE": { "description": "Parity error", "offset": 0, "size": 1 } } } }, "ICR": { "description": "Interrupt flag clear register", "offset": 32, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "WUCF": { "description": "Wakeup from Stop mode clear\n flag", "offset": 20, "size": 1 }, "CMCF": { "description": "Character match clear flag", "offset": 17, "size": 1 }, "EOBCF": { "description": "End of timeout clear flag", "offset": 12, "size": 1 }, "RTOCF": { "description": "Receiver timeout clear\n flag", "offset": 11, "size": 1 }, "CTSCF": { "description": "CTS clear flag", "offset": 9, "size": 1 }, "LBDCF": { "description": "LIN break detection clear\n flag", "offset": 8, "size": 1 }, "TCCF": { "description": "Transmission complete clear\n flag", "offset": 6, "size": 1 }, "IDLECF": { "description": "Idle line detected clear\n flag", "offset": 4, "size": 1 }, "ORECF": { "description": "Overrun error clear flag", "offset": 3, "size": 1 }, "NCF": { "description": "Noise detected clear flag", "offset": 2, "size": 1 }, "FECF": { "description": "Framing error clear flag", "offset": 1, "size": 1 }, "PECF": { "description": "Parity error clear flag", "offset": 0, "size": 1 } } } }, "RDR": { "description": "Receive data register", "offset": 36, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "RDR": { "description": "Receive data value", "offset": 0, "size": 9 } } } }, "TDR": { "description": "Transmit data register", "offset": 40, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "TDR": { "description": "Transmit data value", "offset": 0, "size": 9 } } } } } } }, "SYSCFG_COMP_OPAMP": { "description": "System configuration controller _Comparator and\n Operational amplifier", "children": { "registers": { "SYSCFG_CFGR1": { "description": "configuration register 1", "offset": 0, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "MEM_MODE": { "description": "Memory mapping selection\n bits", "offset": 0, "size": 2 }, "USB_IT_RMP": { "description": "USB interrupt remap", "offset": 5, "size": 1 }, "TIM1_ITR_RMP": { "description": "Timer 1 ITR3 selection", "offset": 6, "size": 1 }, "DAC_TRIG_RMP": { "description": "DAC trigger remap (when TSEL =\n 001)", "offset": 7, "size": 1 }, "ADC24_DMA_RMP": { "description": "ADC24 DMA remapping bit", "offset": 8, "size": 1 }, "TIM16_DMA_RMP": { "description": "TIM16 DMA request remapping\n bit", "offset": 11, "size": 1 }, "TIM17_DMA_RMP": { "description": "TIM17 DMA request remapping\n bit", "offset": 12, "size": 1 }, "TIM6_DAC1_DMA_RMP": { "description": "TIM6 and DAC1 DMA request remapping\n bit", "offset": 13, "size": 1 }, "TIM7_DAC2_DMA_RMP": { "description": "TIM7 and DAC2 DMA request remapping\n bit", "offset": 14, "size": 1 }, "I2C_PB6_FM": { "description": "Fast Mode Plus (FM+) driving capability\n activation bits.", "offset": 16, "size": 1 }, "I2C_PB7_FM": { "description": "Fast Mode Plus (FM+) driving capability\n activation bits.", "offset": 17, "size": 1 }, "I2C_PB8_FM": { "description": "Fast Mode Plus (FM+) driving capability\n activation bits.", "offset": 18, "size": 1 }, "I2C_PB9_FM": { "description": "Fast Mode Plus (FM+) driving capability\n activation bits.", "offset": 19, "size": 1 }, "I2C1_FM": { "description": "I2C1 Fast Mode Plus", "offset": 20, "size": 1 }, "I2C2_FM": { "description": "I2C2 Fast Mode Plus", "offset": 21, "size": 1 }, "ENCODER_MODE": { "description": "Encoder mode", "offset": 22, "size": 2 }, "FPU_IT": { "description": "Interrupt enable bits from\n FPU", "offset": 26, "size": 6 } } } }, "SYSCFG_EXTICR1": { "description": "external interrupt configuration register\n 1", "offset": 8, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "EXTI3": { "description": "EXTI 3 configuration bits", "offset": 12, "size": 4 }, "EXTI2": { "description": "EXTI 2 configuration bits", "offset": 8, "size": 4 }, "EXTI1": { "description": "EXTI 1 configuration bits", "offset": 4, "size": 4 }, "EXTI0": { "description": "EXTI 0 configuration bits", "offset": 0, "size": 4 } } } }, "SYSCFG_EXTICR2": { "description": "external interrupt configuration register\n 2", "offset": 12, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "EXTI7": { "description": "EXTI 7 configuration bits", "offset": 12, "size": 4 }, "EXTI6": { "description": "EXTI 6 configuration bits", "offset": 8, "size": 4 }, "EXTI5": { "description": "EXTI 5 configuration bits", "offset": 4, "size": 4 }, "EXTI4": { "description": "EXTI 4 configuration bits", "offset": 0, "size": 4 } } } }, "SYSCFG_EXTICR3": { "description": "external interrupt configuration register\n 3", "offset": 16, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "EXTI11": { "description": "EXTI 11 configuration bits", "offset": 12, "size": 4 }, "EXTI10": { "description": "EXTI 10 configuration bits", "offset": 8, "size": 4 }, "EXTI9": { "description": "EXTI 9 configuration bits", "offset": 4, "size": 4 }, "EXTI8": { "description": "EXTI 8 configuration bits", "offset": 0, "size": 4 } } } }, "SYSCFG_EXTICR4": { "description": "external interrupt configuration register\n 4", "offset": 20, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "EXTI15": { "description": "EXTI 15 configuration bits", "offset": 12, "size": 4 }, "EXTI14": { "description": "EXTI 14 configuration bits", "offset": 8, "size": 4 }, "EXTI13": { "description": "EXTI 13 configuration bits", "offset": 4, "size": 4 }, "EXTI12": { "description": "EXTI 12 configuration bits", "offset": 0, "size": 4 } } } }, "SYSCFG_CFGR2": { "description": "configuration register 2", "offset": 24, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "LOCUP_LOCK": { "description": "Cortex-M0 LOCKUP bit enable\n bit", "offset": 0, "size": 1 }, "SRAM_PARITY_LOCK": { "description": "SRAM parity lock bit", "offset": 1, "size": 1 }, "PVD_LOCK": { "description": "PVD lock enable bit", "offset": 2, "size": 1 }, "BYP_ADD_PAR": { "description": "Bypass address bit 29 in parity\n calculation", "offset": 4, "size": 1 }, "SRAM_PEF": { "description": "SRAM parity flag", "offset": 8, "size": 1 } } } }, "SYSCFG_RCR": { "description": "CCM SRAM protection register", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "PAGE0_WP": { "description": "CCM SRAM page write protection\n bit", "offset": 0, "size": 1 }, "PAGE1_WP": { "description": "CCM SRAM page write protection\n bit", "offset": 1, "size": 1 }, "PAGE2_WP": { "description": "CCM SRAM page write protection\n bit", "offset": 2, "size": 1 }, "PAGE3_WP": { "description": "CCM SRAM page write protection\n bit", "offset": 3, "size": 1 }, "PAGE4_WP": { "description": "CCM SRAM page write protection\n bit", "offset": 4, "size": 1 }, "PAGE5_WP": { "description": "CCM SRAM page write protection\n bit", "offset": 5, "size": 1 }, "PAGE6_WP": { "description": "CCM SRAM page write protection\n bit", "offset": 6, "size": 1 }, "PAGE7_WP": { "description": "CCM SRAM page write protection\n bit", "offset": 7, "size": 1 } } } }, "COMP1_CSR": { "description": "control and status register", "offset": 28, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "COMP1EN": { "description": "Comparator 1 enable", "offset": 0, "size": 1 }, "COMP1_INP_DAC": { "description": "COMP1_INP_DAC", "offset": 1, "size": 1 }, "COMP1MODE": { "description": "Comparator 1 mode", "offset": 2, "size": 2 }, "COMP1INSEL": { "description": "Comparator 1 inverting input\n selection", "offset": 4, "size": 3 }, "COMP1_OUT_SEL": { "description": "Comparator 1 output\n selection", "offset": 10, "size": 4 }, "COMP1POL": { "description": "Comparator 1 output\n polarity", "offset": 15, "size": 1 }, "COMP1HYST": { "description": "Comparator 1 hysteresis", "offset": 16, "size": 2 }, "COMP1_BLANKING": { "description": "Comparator 1 blanking\n source", "offset": 18, "size": 3 }, "COMP1OUT": { "description": "Comparator 1 output", "offset": 30, "size": 1, "access": "read-only" }, "COMP1LOCK": { "description": "Comparator 1 lock", "offset": 31, "size": 1 } } } }, "COMP2_CSR": { "description": "control and status register", "offset": 32, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "COMP2EN": { "description": "Comparator 2 enable", "offset": 0, "size": 1 }, "COMP2MODE": { "description": "Comparator 2 mode", "offset": 2, "size": 2 }, "COMP2INSEL": { "description": "Comparator 2 inverting input\n selection", "offset": 4, "size": 3 }, "COMP2INPSEL": { "description": "Comparator 2 non inverted input\n selection", "offset": 7, "size": 1 }, "COMP2INMSEL": { "description": "Comparator 1inverting input\n selection", "offset": 9, "size": 1 }, "COMP2_OUT_SEL": { "description": "Comparator 2 output\n selection", "offset": 10, "size": 4 }, "COMP2POL": { "description": "Comparator 2 output\n polarity", "offset": 15, "size": 1 }, "COMP2HYST": { "description": "Comparator 2 hysteresis", "offset": 16, "size": 2 }, "COMP2_BLANKING": { "description": "Comparator 2 blanking\n source", "offset": 18, "size": 3 }, "COMP2LOCK": { "description": "Comparator 2 lock", "offset": 31, "size": 1 } } } }, "COMP3_CSR": { "description": "control and status register", "offset": 36, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "COMP3EN": { "description": "Comparator 3 enable", "offset": 0, "size": 1 }, "COMP3MODE": { "description": "Comparator 3 mode", "offset": 2, "size": 2 }, "COMP3INSEL": { "description": "Comparator 3 inverting input\n selection", "offset": 4, "size": 3 }, "COMP3INPSEL": { "description": "Comparator 3 non inverted input\n selection", "offset": 7, "size": 1 }, "COMP3_OUT_SEL": { "description": "Comparator 3 output\n selection", "offset": 10, "size": 4 }, "COMP3POL": { "description": "Comparator 3 output\n polarity", "offset": 15, "size": 1 }, "COMP3HYST": { "description": "Comparator 3 hysteresis", "offset": 16, "size": 2 }, "COMP3_BLANKING": { "description": "Comparator 3 blanking\n source", "offset": 18, "size": 3 }, "COMP3OUT": { "description": "Comparator 3 output", "offset": 30, "size": 1, "access": "read-only" }, "COMP3LOCK": { "description": "Comparator 3 lock", "offset": 31, "size": 1 } } } }, "COMP4_CSR": { "description": "control and status register", "offset": 40, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "COMP4EN": { "description": "Comparator 4 enable", "offset": 0, "size": 1 }, "COMP4MODE": { "description": "Comparator 4 mode", "offset": 2, "size": 2 }, "COMP4INSEL": { "description": "Comparator 4 inverting input\n selection", "offset": 4, "size": 3 }, "COMP4INPSEL": { "description": "Comparator 4 non inverted input\n selection", "offset": 7, "size": 1 }, "COM4WINMODE": { "description": "Comparator 4 window mode", "offset": 9, "size": 1 }, "COMP4_OUT_SEL": { "description": "Comparator 4 output\n selection", "offset": 10, "size": 4 }, "COMP4POL": { "description": "Comparator 4 output\n polarity", "offset": 15, "size": 1 }, "COMP4HYST": { "description": "Comparator 4 hysteresis", "offset": 16, "size": 2 }, "COMP4_BLANKING": { "description": "Comparator 4 blanking\n source", "offset": 18, "size": 3 }, "COMP4OUT": { "description": "Comparator 4 output", "offset": 30, "size": 1, "access": "read-only" }, "COMP4LOCK": { "description": "Comparator 4 lock", "offset": 31, "size": 1 } } } }, "COMP5_CSR": { "description": "control and status register", "offset": 44, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "COMP5EN": { "description": "Comparator 5 enable", "offset": 0, "size": 1 }, "COMP5MODE": { "description": "Comparator 5 mode", "offset": 2, "size": 2 }, "COMP5INSEL": { "description": "Comparator 5 inverting input\n selection", "offset": 4, "size": 3 }, "COMP5INPSEL": { "description": "Comparator 5 non inverted input\n selection", "offset": 7, "size": 1 }, "COMP5_OUT_SEL": { "description": "Comparator 5 output\n selection", "offset": 10, "size": 4 }, "COMP5POL": { "description": "Comparator 5 output\n polarity", "offset": 15, "size": 1 }, "COMP5HYST": { "description": "Comparator 5 hysteresis", "offset": 16, "size": 2 }, "COMP5_BLANKING": { "description": "Comparator 5 blanking\n source", "offset": 18, "size": 3 }, "COMP5OUT": { "description": "Comparator51 output", "offset": 30, "size": 1, "access": "read-only" }, "COMP5LOCK": { "description": "Comparator 5 lock", "offset": 31, "size": 1 } } } }, "COMP6_CSR": { "description": "control and status register", "offset": 48, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "COMP6EN": { "description": "Comparator 6 enable", "offset": 0, "size": 1 }, "COMP6MODE": { "description": "Comparator 6 mode", "offset": 2, "size": 2 }, "COMP6INSEL": { "description": "Comparator 6 inverting input\n selection", "offset": 4, "size": 3 }, "COMP6INPSEL": { "description": "Comparator 6 non inverted input\n selection", "offset": 7, "size": 1 }, "COM6WINMODE": { "description": "Comparator 6 window mode", "offset": 9, "size": 1 }, "COMP6_OUT_SEL": { "description": "Comparator 6 output\n selection", "offset": 10, "size": 4 }, "COMP6POL": { "description": "Comparator 6 output\n polarity", "offset": 15, "size": 1 }, "COMP6HYST": { "description": "Comparator 6 hysteresis", "offset": 16, "size": 2 }, "COMP6_BLANKING": { "description": "Comparator 6 blanking\n source", "offset": 18, "size": 3 }, "COMP6OUT": { "description": "Comparator 6 output", "offset": 30, "size": 1, "access": "read-only" }, "COMP6LOCK": { "description": "Comparator 6 lock", "offset": 31, "size": 1 } } } }, "COMP7_CSR": { "description": "control and status register", "offset": 52, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "COMP7EN": { "description": "Comparator 7 enable", "offset": 0, "size": 1 }, "COMP7MODE": { "description": "Comparator 7 mode", "offset": 2, "size": 2 }, "COMP7INSEL": { "description": "Comparator 7 inverting input\n selection", "offset": 4, "size": 3 }, "COMP7INPSEL": { "description": "Comparator 7 non inverted input\n selection", "offset": 7, "size": 1 }, "COMP7_OUT_SEL": { "description": "Comparator 7 output\n selection", "offset": 10, "size": 4 }, "COMP7POL": { "description": "Comparator 7 output\n polarity", "offset": 15, "size": 1 }, "COMP7HYST": { "description": "Comparator 7 hysteresis", "offset": 16, "size": 2 }, "COMP7_BLANKING": { "description": "Comparator 7 blanking\n source", "offset": 18, "size": 3 }, "COMP7OUT": { "description": "Comparator 7 output", "offset": 30, "size": 1, "access": "read-only" }, "COMP7LOCK": { "description": "Comparator 7 lock", "offset": 31, "size": 1 } } } }, "OPAMP1_CSR": { "description": "control register", "offset": 56, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "OPAMP1_EN": { "description": "OPAMP1 enable", "offset": 0, "size": 1 }, "FORCE_VP": { "description": "FORCE_VP", "offset": 1, "size": 1 }, "VP_SEL": { "description": "OPAMP1 Non inverting input\n selection", "offset": 2, "size": 2 }, "VM_SEL": { "description": "OPAMP1 inverting input\n selection", "offset": 5, "size": 2 }, "TCM_EN": { "description": "Timer controlled Mux mode\n enable", "offset": 7, "size": 1 }, "VMS_SEL": { "description": "OPAMP1 inverting input secondary\n selection", "offset": 8, "size": 1 }, "VPS_SEL": { "description": "OPAMP1 Non inverting input secondary\n selection", "offset": 9, "size": 2 }, "CALON": { "description": "Calibration mode enable", "offset": 11, "size": 1 }, "CALSEL": { "description": "Calibration selection", "offset": 12, "size": 2 }, "PGA_GAIN": { "description": "Gain in PGA mode", "offset": 14, "size": 4 }, "USER_TRIM": { "description": "User trimming enable", "offset": 18, "size": 1 }, "TRIMOFFSETP": { "description": "Offset trimming value\n (PMOS)", "offset": 19, "size": 5 }, "TRIMOFFSETN": { "description": "Offset trimming value\n (NMOS)", "offset": 24, "size": 5 }, "TSTREF": { "description": "TSTREF", "offset": 29, "size": 1 }, "OUTCAL": { "description": "OPAMP 1 ouput status flag", "offset": 30, "size": 1, "access": "read-only" }, "LOCK": { "description": "OPAMP 1 lock", "offset": 31, "size": 1 } } } }, "OPAMP2_CSR": { "description": "control register", "offset": 60, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "OPAMP2EN": { "description": "OPAMP2 enable", "offset": 0, "size": 1 }, "FORCE_VP": { "description": "FORCE_VP", "offset": 1, "size": 1 }, "VP_SEL": { "description": "OPAMP2 Non inverting input\n selection", "offset": 2, "size": 2 }, "VM_SEL": { "description": "OPAMP2 inverting input\n selection", "offset": 5, "size": 2 }, "TCM_EN": { "description": "Timer controlled Mux mode\n enable", "offset": 7, "size": 1 }, "VMS_SEL": { "description": "OPAMP2 inverting input secondary\n selection", "offset": 8, "size": 1 }, "VPS_SEL": { "description": "OPAMP2 Non inverting input secondary\n selection", "offset": 9, "size": 2 }, "CALON": { "description": "Calibration mode enable", "offset": 11, "size": 1 }, "CAL_SEL": { "description": "Calibration selection", "offset": 12, "size": 2 }, "PGA_GAIN": { "description": "Gain in PGA mode", "offset": 14, "size": 4 }, "USER_TRIM": { "description": "User trimming enable", "offset": 18, "size": 1 }, "TRIMOFFSETP": { "description": "Offset trimming value\n (PMOS)", "offset": 19, "size": 5 }, "TRIMOFFSETN": { "description": "Offset trimming value\n (NMOS)", "offset": 24, "size": 5 }, "TSTREF": { "description": "TSTREF", "offset": 29, "size": 1 }, "OUTCAL": { "description": "OPAMP 2 ouput status flag", "offset": 30, "size": 1, "access": "read-only" }, "LOCK": { "description": "OPAMP 2 lock", "offset": 31, "size": 1 } } } }, "OPAMP3_CSR": { "description": "control register", "offset": 64, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "OPAMP3EN": { "description": "OPAMP3 enable", "offset": 0, "size": 1 }, "FORCE_VP": { "description": "FORCE_VP", "offset": 1, "size": 1 }, "VP_SEL": { "description": "OPAMP3 Non inverting input\n selection", "offset": 2, "size": 2 }, "VM_SEL": { "description": "OPAMP3 inverting input\n selection", "offset": 5, "size": 2 }, "TCM_EN": { "description": "Timer controlled Mux mode\n enable", "offset": 7, "size": 1 }, "VMS_SEL": { "description": "OPAMP3 inverting input secondary\n selection", "offset": 8, "size": 1 }, "VPS_SEL": { "description": "OPAMP3 Non inverting input secondary\n selection", "offset": 9, "size": 2 }, "CALON": { "description": "Calibration mode enable", "offset": 11, "size": 1 }, "CALSEL": { "description": "Calibration selection", "offset": 12, "size": 2 }, "PGA_GAIN": { "description": "Gain in PGA mode", "offset": 14, "size": 4 }, "USER_TRIM": { "description": "User trimming enable", "offset": 18, "size": 1 }, "TRIMOFFSETP": { "description": "Offset trimming value\n (PMOS)", "offset": 19, "size": 5 }, "TRIMOFFSETN": { "description": "Offset trimming value\n (NMOS)", "offset": 24, "size": 5 }, "TSTREF": { "description": "TSTREF", "offset": 29, "size": 1 }, "OUTCAL": { "description": "OPAMP 3 ouput status flag", "offset": 30, "size": 1, "access": "read-only" }, "LOCK": { "description": "OPAMP 3 lock", "offset": 31, "size": 1 } } } }, "OPAMP4_CSR": { "description": "control register", "offset": 68, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "OPAMP4EN": { "description": "OPAMP4 enable", "offset": 0, "size": 1 }, "FORCE_VP": { "description": "FORCE_VP", "offset": 1, "size": 1 }, "VP_SEL": { "description": "OPAMP4 Non inverting input\n selection", "offset": 2, "size": 2 }, "VM_SEL": { "description": "OPAMP4 inverting input\n selection", "offset": 5, "size": 2 }, "TCM_EN": { "description": "Timer controlled Mux mode\n enable", "offset": 7, "size": 1 }, "VMS_SEL": { "description": "OPAMP4 inverting input secondary\n selection", "offset": 8, "size": 1 }, "VPS_SEL": { "description": "OPAMP4 Non inverting input secondary\n selection", "offset": 9, "size": 2 }, "CALON": { "description": "Calibration mode enable", "offset": 11, "size": 1 }, "CALSEL": { "description": "Calibration selection", "offset": 12, "size": 2 }, "PGA_GAIN": { "description": "Gain in PGA mode", "offset": 14, "size": 4 }, "USER_TRIM": { "description": "User trimming enable", "offset": 18, "size": 1 }, "TRIMOFFSETP": { "description": "Offset trimming value\n (PMOS)", "offset": 19, "size": 5 }, "TRIMOFFSETN": { "description": "Offset trimming value\n (NMOS)", "offset": 24, "size": 5 }, "TSTREF": { "description": "TSTREF", "offset": 29, "size": 1 }, "OUTCAL": { "description": "OPAMP 4 ouput status flag", "offset": 30, "size": 1, "access": "read-only" }, "LOCK": { "description": "OPAMP 4 lock", "offset": 31, "size": 1 } } } } } } }, "IWDG": { "description": "Independent watchdog", "children": { "registers": { "KR": { "description": "Key register", "offset": 0, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "write-only", "children": { "fields": { "KEY": { "description": "Key value", "offset": 0, "size": 16 } } } }, "PR": { "description": "Prescaler register", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "PR": { "description": "Prescaler divider", "offset": 0, "size": 3 } } } }, "RLR": { "description": "Reload register", "offset": 8, "size": 32, "reset_value": 4095, "reset_mask": 4294967295, "children": { "fields": { "RL": { "description": "Watchdog counter reload\n value", "offset": 0, "size": 12 } } } }, "SR": { "description": "Status register", "offset": 12, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "PVU": { "description": "Watchdog prescaler value\n update", "offset": 0, "size": 1 }, "RVU": { "description": "Watchdog counter reload value\n update", "offset": 1, "size": 1 }, "WVU": { "description": "Watchdog counter window value\n update", "offset": 2, "size": 1 } } } }, "WINR": { "description": "Window register", "offset": 16, "size": 32, "reset_value": 4095, "reset_mask": 4294967295, "children": { "fields": { "WIN": { "description": "Watchdog counter window\n value", "offset": 0, "size": 12 } } } } } } }, "ADC1_2": { "description": "Analog-to-Digital Converter", "children": { "registers": { "CSR": { "description": "ADC Common status register", "offset": 0, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "ADDRDY_MST": { "description": "ADDRDY_MST", "offset": 0, "size": 1 }, "EOSMP_MST": { "description": "EOSMP_MST", "offset": 1, "size": 1 }, "EOC_MST": { "description": "EOC_MST", "offset": 2, "size": 1 }, "EOS_MST": { "description": "EOS_MST", "offset": 3, "size": 1 }, "OVR_MST": { "description": "OVR_MST", "offset": 4, "size": 1 }, "JEOC_MST": { "description": "JEOC_MST", "offset": 5, "size": 1 }, "JEOS_MST": { "description": "JEOS_MST", "offset": 6, "size": 1 }, "AWD1_MST": { "description": "AWD1_MST", "offset": 7, "size": 1 }, "AWD2_MST": { "description": "AWD2_MST", "offset": 8, "size": 1 }, "AWD3_MST": { "description": "AWD3_MST", "offset": 9, "size": 1 }, "JQOVF_MST": { "description": "JQOVF_MST", "offset": 10, "size": 1 }, "ADRDY_SLV": { "description": "ADRDY_SLV", "offset": 16, "size": 1 }, "EOSMP_SLV": { "description": "EOSMP_SLV", "offset": 17, "size": 1 }, "EOC_SLV": { "description": "End of regular conversion of the slave\n ADC", "offset": 18, "size": 1 }, "EOS_SLV": { "description": "End of regular sequence flag of the\n slave ADC", "offset": 19, "size": 1 }, "OVR_SLV": { "description": "Overrun flag of the slave\n ADC", "offset": 20, "size": 1 }, "JEOC_SLV": { "description": "End of injected conversion flag of the\n slave ADC", "offset": 21, "size": 1 }, "JEOS_SLV": { "description": "End of injected sequence flag of the\n slave ADC", "offset": 22, "size": 1 }, "AWD1_SLV": { "description": "Analog watchdog 1 flag of the slave\n ADC", "offset": 23, "size": 1 }, "AWD2_SLV": { "description": "Analog watchdog 2 flag of the slave\n ADC", "offset": 24, "size": 1 }, "AWD3_SLV": { "description": "Analog watchdog 3 flag of the slave\n ADC", "offset": 25, "size": 1 }, "JQOVF_SLV": { "description": "Injected Context Queue Overflow flag of\n the slave ADC", "offset": 26, "size": 1 } } } }, "CCR": { "description": "ADC common control register", "offset": 8, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "MULT": { "description": "Multi ADC mode selection", "offset": 0, "size": 5 }, "DELAY": { "description": "Delay between 2 sampling\n phases", "offset": 8, "size": 4 }, "DMACFG": { "description": "DMA configuration (for multi-ADC\n mode)", "offset": 13, "size": 1 }, "MDMA": { "description": "Direct memory access mode for multi ADC\n mode", "offset": 14, "size": 2 }, "CKMODE": { "description": "ADC clock mode", "offset": 16, "size": 2 }, "VREFEN": { "description": "VREFINT enable", "offset": 22, "size": 1 }, "TSEN": { "description": "Temperature sensor enable", "offset": 23, "size": 1 }, "VBATEN": { "description": "VBAT enable", "offset": 24, "size": 1 } } } }, "CDR": { "description": "ADC common regular data register for dual\n and triple modes", "offset": 12, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "RDATA_SLV": { "description": "Regular data of the slave\n ADC", "offset": 16, "size": 16 }, "RDATA_MST": { "description": "Regular data of the master\n ADC", "offset": 0, "size": 16 } } } } } } }, "WWDG": { "description": "Window watchdog", "children": { "registers": { "CR": { "description": "Control register", "offset": 0, "size": 32, "reset_value": 127, "reset_mask": 4294967295, "children": { "fields": { "T": { "description": "7-bit counter", "offset": 0, "size": 7 }, "WDGA": { "description": "Activation bit", "offset": 7, "size": 1 } } } }, "CFR": { "description": "Configuration register", "offset": 4, "size": 32, "reset_value": 127, "reset_mask": 4294967295, "children": { "fields": { "EWI": { "description": "Early wakeup interrupt", "offset": 9, "size": 1 }, "WDGTB": { "description": "Timer base", "offset": 7, "size": 2 }, "W": { "description": "7-bit window value", "offset": 0, "size": 7 } } } }, "SR": { "description": "Status register", "offset": 8, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "EWIF": { "description": "Early wakeup interrupt\n flag", "offset": 0, "size": 1 } } } } } } }, "SPI1": { "description": "Serial peripheral interface/Inter-IC\n sound", "children": { "registers": { "CR1": { "description": "control register 1", "offset": 0, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BIDIMODE": { "description": "Bidirectional data mode\n enable", "offset": 15, "size": 1 }, "BIDIOE": { "description": "Output enable in bidirectional\n mode", "offset": 14, "size": 1 }, "CRCEN": { "description": "Hardware CRC calculation\n enable", "offset": 13, "size": 1 }, "CRCNEXT": { "description": "CRC transfer next", "offset": 12, "size": 1 }, "CRCL": { "description": "CRC length", "offset": 11, "size": 1 }, "RXONLY": { "description": "Receive only", "offset": 10, "size": 1 }, "SSM": { "description": "Software slave management", "offset": 9, "size": 1 }, "SSI": { "description": "Internal slave select", "offset": 8, "size": 1 }, "LSBFIRST": { "description": "Frame format", "offset": 7, "size": 1 }, "SPE": { "description": "SPI enable", "offset": 6, "size": 1 }, "BR": { "description": "Baud rate control", "offset": 3, "size": 3 }, "MSTR": { "description": "Master selection", "offset": 2, "size": 1 }, "CPOL": { "description": "Clock polarity", "offset": 1, "size": 1 }, "CPHA": { "description": "Clock phase", "offset": 0, "size": 1 } } } }, "CR2": { "description": "control register 2", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "RXDMAEN": { "description": "Rx buffer DMA enable", "offset": 0, "size": 1 }, "TXDMAEN": { "description": "Tx buffer DMA enable", "offset": 1, "size": 1 }, "SSOE": { "description": "SS output enable", "offset": 2, "size": 1 }, "NSSP": { "description": "NSS pulse management", "offset": 3, "size": 1 }, "FRF": { "description": "Frame format", "offset": 4, "size": 1 }, "ERRIE": { "description": "Error interrupt enable", "offset": 5, "size": 1 }, "RXNEIE": { "description": "RX buffer not empty interrupt\n enable", "offset": 6, "size": 1 }, "TXEIE": { "description": "Tx buffer empty interrupt\n enable", "offset": 7, "size": 1 }, "DS": { "description": "Data size", "offset": 8, "size": 4 }, "FRXTH": { "description": "FIFO reception threshold", "offset": 12, "size": 1 }, "LDMA_RX": { "description": "Last DMA transfer for\n reception", "offset": 13, "size": 1 }, "LDMA_TX": { "description": "Last DMA transfer for\n transmission", "offset": 14, "size": 1 } } } }, "SR": { "description": "status register", "offset": 8, "size": 32, "reset_value": 2, "reset_mask": 4294967295, "children": { "fields": { "RXNE": { "description": "Receive buffer not empty", "offset": 0, "size": 1, "access": "read-only" }, "TXE": { "description": "Transmit buffer empty", "offset": 1, "size": 1, "access": "read-only" }, "CHSIDE": { "description": "Channel side", "offset": 2, "size": 1, "access": "read-only" }, "UDR": { "description": "Underrun flag", "offset": 3, "size": 1, "access": "read-only" }, "CRCERR": { "description": "CRC error flag", "offset": 4, "size": 1 }, "MODF": { "description": "Mode fault", "offset": 5, "size": 1, "access": "read-only" }, "OVR": { "description": "Overrun flag", "offset": 6, "size": 1, "access": "read-only" }, "BSY": { "description": "Busy flag", "offset": 7, "size": 1, "access": "read-only" }, "TIFRFE": { "description": "TI frame format error", "offset": 8, "size": 1, "access": "read-only" }, "FRLVL": { "description": "FIFO reception level", "offset": 9, "size": 2, "access": "read-only" }, "FTLVL": { "description": "FIFO transmission level", "offset": 11, "size": 2, "access": "read-only" } } } }, "DR": { "description": "data register", "offset": 12, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DR": { "description": "Data register", "offset": 0, "size": 16 } } } }, "CRCPR": { "description": "CRC polynomial register", "offset": 16, "size": 32, "reset_value": 7, "reset_mask": 4294967295, "children": { "fields": { "CRCPOLY": { "description": "CRC polynomial register", "offset": 0, "size": 16 } } } }, "RXCRCR": { "description": "RX CRC register", "offset": 20, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "RxCRC": { "description": "Rx CRC register", "offset": 0, "size": 16 } } } }, "TXCRCR": { "description": "TX CRC register", "offset": 24, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "TxCRC": { "description": "Tx CRC register", "offset": 0, "size": 16 } } } }, "I2SCFGR": { "description": "I2S configuration register", "offset": 28, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "I2SMOD": { "description": "I2S mode selection", "offset": 11, "size": 1 }, "I2SE": { "description": "I2S Enable", "offset": 10, "size": 1 }, "I2SCFG": { "description": "I2S configuration mode", "offset": 8, "size": 2 }, "PCMSYNC": { "description": "PCM frame synchronization", "offset": 7, "size": 1 }, "I2SSTD": { "description": "I2S standard selection", "offset": 4, "size": 2 }, "CKPOL": { "description": "Steady state clock\n polarity", "offset": 3, "size": 1 }, "DATLEN": { "description": "Data length to be\n transferred", "offset": 1, "size": 2 }, "CHLEN": { "description": "Channel length (number of bits per audio\n channel)", "offset": 0, "size": 1 } } } }, "I2SPR": { "description": "I2S prescaler register", "offset": 32, "size": 32, "reset_value": 16, "reset_mask": 4294967295, "children": { "fields": { "MCKOE": { "description": "Master clock output enable", "offset": 9, "size": 1 }, "ODD": { "description": "Odd factor for the\n prescaler", "offset": 8, "size": 1 }, "I2SDIV": { "description": "I2S Linear prescaler", "offset": 0, "size": 8 } } } } } } }, "RTC": { "description": "Real-time clock", "children": { "registers": { "TR": { "description": "time register", "offset": 0, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "PM": { "description": "AM/PM notation", "offset": 22, "size": 1 }, "HT": { "description": "Hour tens in BCD format", "offset": 20, "size": 2 }, "HU": { "description": "Hour units in BCD format", "offset": 16, "size": 4 }, "MNT": { "description": "Minute tens in BCD format", "offset": 12, "size": 3 }, "MNU": { "description": "Minute units in BCD format", "offset": 8, "size": 4 }, "ST": { "description": "Second tens in BCD format", "offset": 4, "size": 3 }, "SU": { "description": "Second units in BCD format", "offset": 0, "size": 4 } } } }, "DR": { "description": "date register", "offset": 4, "size": 32, "reset_value": 8449, "reset_mask": 4294967295, "children": { "fields": { "YT": { "description": "Year tens in BCD format", "offset": 20, "size": 4 }, "YU": { "description": "Year units in BCD format", "offset": 16, "size": 4 }, "WDU": { "description": "Week day units", "offset": 13, "size": 3 }, "MT": { "description": "Month tens in BCD format", "offset": 12, "size": 1 }, "MU": { "description": "Month units in BCD format", "offset": 8, "size": 4 }, "DT": { "description": "Date tens in BCD format", "offset": 4, "size": 2 }, "DU": { "description": "Date units in BCD format", "offset": 0, "size": 4 } } } }, "CR": { "description": "control register", "offset": 8, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "WCKSEL": { "description": "Wakeup clock selection", "offset": 0, "size": 3 }, "TSEDGE": { "description": "Time-stamp event active\n edge", "offset": 3, "size": 1 }, "REFCKON": { "description": "Reference clock detection enable (50 or\n 60 Hz)", "offset": 4, "size": 1 }, "BYPSHAD": { "description": "Bypass the shadow\n registers", "offset": 5, "size": 1 }, "FMT": { "description": "Hour format", "offset": 6, "size": 1 }, "ALRAE": { "description": "Alarm A enable", "offset": 8, "size": 1 }, "ALRBE": { "description": "Alarm B enable", "offset": 9, "size": 1 }, "WUTE": { "description": "Wakeup timer enable", "offset": 10, "size": 1 }, "TSE": { "description": "Time stamp enable", "offset": 11, "size": 1 }, "ALRAIE": { "description": "Alarm A interrupt enable", "offset": 12, "size": 1 }, "ALRBIE": { "description": "Alarm B interrupt enable", "offset": 13, "size": 1 }, "WUTIE": { "description": "Wakeup timer interrupt\n enable", "offset": 14, "size": 1 }, "TSIE": { "description": "Time-stamp interrupt\n enable", "offset": 15, "size": 1 }, "ADD1H": { "description": "Add 1 hour (summer time\n change)", "offset": 16, "size": 1 }, "SUB1H": { "description": "Subtract 1 hour (winter time\n change)", "offset": 17, "size": 1 }, "BKP": { "description": "Backup", "offset": 18, "size": 1 }, "COSEL": { "description": "Calibration output\n selection", "offset": 19, "size": 1 }, "POL": { "description": "Output polarity", "offset": 20, "size": 1 }, "OSEL": { "description": "Output selection", "offset": 21, "size": 2 }, "COE": { "description": "Calibration output enable", "offset": 23, "size": 1 } } } }, "ISR": { "description": "initialization and status\n register", "offset": 12, "size": 32, "reset_value": 7, "reset_mask": 4294967295, "children": { "fields": { "ALRAWF": { "description": "Alarm A write flag", "offset": 0, "size": 1, "access": "read-only" }, "ALRBWF": { "description": "Alarm B write flag", "offset": 1, "size": 1, "access": "read-only" }, "WUTWF": { "description": "Wakeup timer write flag", "offset": 2, "size": 1, "access": "read-only" }, "SHPF": { "description": "Shift operation pending", "offset": 3, "size": 1 }, "INITS": { "description": "Initialization status flag", "offset": 4, "size": 1, "access": "read-only" }, "RSF": { "description": "Registers synchronization\n flag", "offset": 5, "size": 1 }, "INITF": { "description": "Initialization flag", "offset": 6, "size": 1, "access": "read-only" }, "INIT": { "description": "Initialization mode", "offset": 7, "size": 1 }, "ALRAF": { "description": "Alarm A flag", "offset": 8, "size": 1 }, "ALRBF": { "description": "Alarm B flag", "offset": 9, "size": 1 }, "WUTF": { "description": "Wakeup timer flag", "offset": 10, "size": 1 }, "TSF": { "description": "Time-stamp flag", "offset": 11, "size": 1 }, "TSOVF": { "description": "Time-stamp overflow flag", "offset": 12, "size": 1 }, "TAMP1F": { "description": "Tamper detection flag", "offset": 13, "size": 1 }, "TAMP2F": { "description": "RTC_TAMP2 detection flag", "offset": 14, "size": 1 }, "TAMP3F": { "description": "RTC_TAMP3 detection flag", "offset": 15, "size": 1 }, "RECALPF": { "description": "Recalibration pending Flag", "offset": 16, "size": 1, "access": "read-only" } } } }, "PRER": { "description": "prescaler register", "offset": 16, "size": 32, "reset_value": 8323327, "reset_mask": 4294967295, "children": { "fields": { "PREDIV_A": { "description": "Asynchronous prescaler\n factor", "offset": 16, "size": 7 }, "PREDIV_S": { "description": "Synchronous prescaler\n factor", "offset": 0, "size": 15 } } } }, "WUTR": { "description": "wakeup timer register", "offset": 20, "size": 32, "reset_value": 65535, "reset_mask": 4294967295, "children": { "fields": { "WUT": { "description": "Wakeup auto-reload value\n bits", "offset": 0, "size": 16 } } } }, "ALRMAR": { "description": "alarm A register", "offset": 28, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "MSK4": { "description": "Alarm A date mask", "offset": 31, "size": 1 }, "WDSEL": { "description": "Week day selection", "offset": 30, "size": 1 }, "DT": { "description": "Date tens in BCD format", "offset": 28, "size": 2 }, "DU": { "description": "Date units or day in BCD\n format", "offset": 24, "size": 4 }, "MSK3": { "description": "Alarm A hours mask", "offset": 23, "size": 1 }, "PM": { "description": "AM/PM notation", "offset": 22, "size": 1 }, "HT": { "description": "Hour tens in BCD format", "offset": 20, "size": 2 }, "HU": { "description": "Hour units in BCD format", "offset": 16, "size": 4 }, "MSK2": { "description": "Alarm A minutes mask", "offset": 15, "size": 1 }, "MNT": { "description": "Minute tens in BCD format", "offset": 12, "size": 3 }, "MNU": { "description": "Minute units in BCD format", "offset": 8, "size": 4 }, "MSK1": { "description": "Alarm A seconds mask", "offset": 7, "size": 1 }, "ST": { "description": "Second tens in BCD format", "offset": 4, "size": 3 }, "SU": { "description": "Second units in BCD format", "offset": 0, "size": 4 } } } }, "ALRMBR": { "description": "alarm B register", "offset": 32, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "MSK4": { "description": "Alarm B date mask", "offset": 31, "size": 1 }, "WDSEL": { "description": "Week day selection", "offset": 30, "size": 1 }, "DT": { "description": "Date tens in BCD format", "offset": 28, "size": 2 }, "DU": { "description": "Date units or day in BCD\n format", "offset": 24, "size": 4 }, "MSK3": { "description": "Alarm B hours mask", "offset": 23, "size": 1 }, "PM": { "description": "AM/PM notation", "offset": 22, "size": 1 }, "HT": { "description": "Hour tens in BCD format", "offset": 20, "size": 2 }, "HU": { "description": "Hour units in BCD format", "offset": 16, "size": 4 }, "MSK2": { "description": "Alarm B minutes mask", "offset": 15, "size": 1 }, "MNT": { "description": "Minute tens in BCD format", "offset": 12, "size": 3 }, "MNU": { "description": "Minute units in BCD format", "offset": 8, "size": 4 }, "MSK1": { "description": "Alarm B seconds mask", "offset": 7, "size": 1 }, "ST": { "description": "Second tens in BCD format", "offset": 4, "size": 3 }, "SU": { "description": "Second units in BCD format", "offset": 0, "size": 4 } } } }, "WPR": { "description": "write protection register", "offset": 36, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "write-only", "children": { "fields": { "KEY": { "description": "Write protection key", "offset": 0, "size": 8 } } } }, "SSR": { "description": "sub second register", "offset": 40, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "SS": { "description": "Sub second value", "offset": 0, "size": 16 } } } }, "SHIFTR": { "description": "shift control register", "offset": 44, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "write-only", "children": { "fields": { "ADD1S": { "description": "Add one second", "offset": 31, "size": 1 }, "SUBFS": { "description": "Subtract a fraction of a\n second", "offset": 0, "size": 15 } } } }, "TSTR": { "description": "time stamp time register", "offset": 48, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "SU": { "description": "Second units in BCD format", "offset": 0, "size": 4 }, "ST": { "description": "Second tens in BCD format", "offset": 4, "size": 3 }, "MNU": { "description": "Minute units in BCD format", "offset": 8, "size": 4 }, "MNT": { "description": "Minute tens in BCD format", "offset": 12, "size": 3 }, "HU": { "description": "Hour units in BCD format", "offset": 16, "size": 4 }, "HT": { "description": "Hour tens in BCD format", "offset": 20, "size": 2 }, "PM": { "description": "AM/PM notation", "offset": 22, "size": 1 } } } }, "TSDR": { "description": "time stamp date register", "offset": 52, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "WDU": { "description": "Week day units", "offset": 13, "size": 3 }, "MT": { "description": "Month tens in BCD format", "offset": 12, "size": 1 }, "MU": { "description": "Month units in BCD format", "offset": 8, "size": 4 }, "DT": { "description": "Date tens in BCD format", "offset": 4, "size": 2 }, "DU": { "description": "Date units in BCD format", "offset": 0, "size": 4 } } } }, "TSSSR": { "description": "timestamp sub second register", "offset": 56, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "SS": { "description": "Sub second value", "offset": 0, "size": 16 } } } }, "CALR": { "description": "calibration register", "offset": 60, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CALP": { "description": "Increase frequency of RTC by 488.5\n ppm", "offset": 15, "size": 1 }, "CALW8": { "description": "Use an 8-second calibration cycle\n period", "offset": 14, "size": 1 }, "CALW16": { "description": "Use a 16-second calibration cycle\n period", "offset": 13, "size": 1 }, "CALM": { "description": "Calibration minus", "offset": 0, "size": 9 } } } }, "TAFCR": { "description": "tamper and alternate function configuration\n register", "offset": 64, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "TAMP1E": { "description": "Tamper 1 detection enable", "offset": 0, "size": 1 }, "TAMP1TRG": { "description": "Active level for tamper 1", "offset": 1, "size": 1 }, "TAMPIE": { "description": "Tamper interrupt enable", "offset": 2, "size": 1 }, "TAMP2E": { "description": "Tamper 2 detection enable", "offset": 3, "size": 1 }, "TAMP2TRG": { "description": "Active level for tamper 2", "offset": 4, "size": 1 }, "TAMP3E": { "description": "Tamper 3 detection enable", "offset": 5, "size": 1 }, "TAMP3TRG": { "description": "Active level for tamper 3", "offset": 6, "size": 1 }, "TAMPTS": { "description": "Activate timestamp on tamper detection\n event", "offset": 7, "size": 1 }, "TAMPFREQ": { "description": "Tamper sampling frequency", "offset": 8, "size": 3 }, "TAMPFLT": { "description": "Tamper filter count", "offset": 11, "size": 2 }, "TAMPPRCH": { "description": "Tamper precharge duration", "offset": 13, "size": 2 }, "TAMPPUDIS": { "description": "TAMPER pull-up disable", "offset": 15, "size": 1 }, "PC13VALUE": { "description": "PC13 value", "offset": 18, "size": 1 }, "PC13MODE": { "description": "PC13 mode", "offset": 19, "size": 1 }, "PC14VALUE": { "description": "PC14 value", "offset": 20, "size": 1 }, "PC14MODE": { "description": "PC 14 mode", "offset": 21, "size": 1 }, "PC15VALUE": { "description": "PC15 value", "offset": 22, "size": 1 }, "PC15MODE": { "description": "PC15 mode", "offset": 23, "size": 1 } } } }, "ALRMASSR": { "description": "alarm A sub second register", "offset": 68, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "MASKSS": { "description": "Mask the most-significant bits starting\n at this bit", "offset": 24, "size": 4 }, "SS": { "description": "Sub seconds value", "offset": 0, "size": 15 } } } }, "ALRMBSSR": { "description": "alarm B sub second register", "offset": 72, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "MASKSS": { "description": "Mask the most-significant bits starting\n at this bit", "offset": 24, "size": 4 }, "SS": { "description": "Sub seconds value", "offset": 0, "size": 15 } } } }, "BKP0R": { "description": "backup register", "offset": 80, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP1R": { "description": "backup register", "offset": 84, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP2R": { "description": "backup register", "offset": 88, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP3R": { "description": "backup register", "offset": 92, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP4R": { "description": "backup register", "offset": 96, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP5R": { "description": "backup register", "offset": 100, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP6R": { "description": "backup register", "offset": 104, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP7R": { "description": "backup register", "offset": 108, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP8R": { "description": "backup register", "offset": 112, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP9R": { "description": "backup register", "offset": 116, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP10R": { "description": "backup register", "offset": 120, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP11R": { "description": "backup register", "offset": 124, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP12R": { "description": "backup register", "offset": 128, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP13R": { "description": "backup register", "offset": 132, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP14R": { "description": "backup register", "offset": 136, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP15R": { "description": "backup register", "offset": 140, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP16R": { "description": "backup register", "offset": 144, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP17R": { "description": "backup register", "offset": 148, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP18R": { "description": "backup register", "offset": 152, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP19R": { "description": "backup register", "offset": 156, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP20R": { "description": "backup register", "offset": 160, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP21R": { "description": "backup register", "offset": 164, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP22R": { "description": "backup register", "offset": 168, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP23R": { "description": "backup register", "offset": 172, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP24R": { "description": "backup register", "offset": 176, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP25R": { "description": "backup register", "offset": 180, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP26R": { "description": "backup register", "offset": 184, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP27R": { "description": "backup register", "offset": 188, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP28R": { "description": "backup register", "offset": 192, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP29R": { "description": "backup register", "offset": 196, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP30R": { "description": "backup register", "offset": 200, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } }, "BKP31R": { "description": "backup register", "offset": 204, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BKP": { "description": "BKP", "offset": 0, "size": 32 } } } } } } }, "TIM6": { "description": "Basic timers", "children": { "registers": { "CR1": { "description": "control register 1", "offset": 0, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CEN": { "description": "Counter enable", "offset": 0, "size": 1 }, "UDIS": { "description": "Update disable", "offset": 1, "size": 1 }, "URS": { "description": "Update request source", "offset": 2, "size": 1 }, "OPM": { "description": "One-pulse mode", "offset": 3, "size": 1 }, "ARPE": { "description": "Auto-reload preload enable", "offset": 7, "size": 1 }, "UIFREMAP": { "description": "UIF status bit remapping", "offset": 11, "size": 1 } } } }, "CR2": { "description": "control register 2", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "MMS": { "description": "Master mode selection", "offset": 4, "size": 3 } } } }, "DIER": { "description": "DMA/Interrupt enable register", "offset": 12, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "UDE": { "description": "Update DMA request enable", "offset": 8, "size": 1 }, "UIE": { "description": "Update interrupt enable", "offset": 0, "size": 1 } } } }, "SR": { "description": "status register", "offset": 16, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "UIF": { "description": "Update interrupt flag", "offset": 0, "size": 1 } } } }, "EGR": { "description": "event generation register", "offset": 20, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "write-only", "children": { "fields": { "UG": { "description": "Update generation", "offset": 0, "size": 1 } } } }, "CNT": { "description": "counter", "offset": 36, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CNT": { "description": "Low counter value", "offset": 0, "size": 16 }, "UIFCPY": { "description": "UIF Copy", "offset": 31, "size": 1, "access": "read-only" } } } }, "PSC": { "description": "prescaler", "offset": 40, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "PSC": { "description": "Prescaler value", "offset": 0, "size": 16 } } } }, "ARR": { "description": "auto-reload register", "offset": 44, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "ARR": { "description": "Low Auto-reload value", "offset": 0, "size": 16 } } } } } } }, "ADC1": { "description": "Analog-to-Digital Converter", "children": { "registers": { "ISR": { "description": "interrupt and status register", "offset": 0, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "JQOVF": { "description": "JQOVF", "offset": 10, "size": 1 }, "AWD3": { "description": "AWD3", "offset": 9, "size": 1 }, "AWD2": { "description": "AWD2", "offset": 8, "size": 1 }, "AWD1": { "description": "AWD1", "offset": 7, "size": 1 }, "JEOS": { "description": "JEOS", "offset": 6, "size": 1 }, "JEOC": { "description": "JEOC", "offset": 5, "size": 1 }, "OVR": { "description": "OVR", "offset": 4, "size": 1 }, "EOS": { "description": "EOS", "offset": 3, "size": 1 }, "EOC": { "description": "EOC", "offset": 2, "size": 1 }, "EOSMP": { "description": "EOSMP", "offset": 1, "size": 1 }, "ADRDY": { "description": "ADRDY", "offset": 0, "size": 1 } } } }, "IER": { "description": "interrupt enable register", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "JQOVFIE": { "description": "JQOVFIE", "offset": 10, "size": 1 }, "AWD3IE": { "description": "AWD3IE", "offset": 9, "size": 1 }, "AWD2IE": { "description": "AWD2IE", "offset": 8, "size": 1 }, "AWD1IE": { "description": "AWD1IE", "offset": 7, "size": 1 }, "JEOSIE": { "description": "JEOSIE", "offset": 6, "size": 1 }, "JEOCIE": { "description": "JEOCIE", "offset": 5, "size": 1 }, "OVRIE": { "description": "OVRIE", "offset": 4, "size": 1 }, "EOSIE": { "description": "EOSIE", "offset": 3, "size": 1 }, "EOCIE": { "description": "EOCIE", "offset": 2, "size": 1 }, "EOSMPIE": { "description": "EOSMPIE", "offset": 1, "size": 1 }, "ADRDYIE": { "description": "ADRDYIE", "offset": 0, "size": 1 } } } }, "CR": { "description": "control register", "offset": 8, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "ADCAL": { "description": "ADCAL", "offset": 31, "size": 1 }, "ADCALDIF": { "description": "ADCALDIF", "offset": 30, "size": 1 }, "DEEPPWD": { "description": "DEEPPWD", "offset": 29, "size": 1 }, "ADVREGEN": { "description": "ADVREGEN", "offset": 28, "size": 1 }, "JADSTP": { "description": "JADSTP", "offset": 5, "size": 1 }, "ADSTP": { "description": "ADSTP", "offset": 4, "size": 1 }, "JADSTART": { "description": "JADSTART", "offset": 3, "size": 1 }, "ADSTART": { "description": "ADSTART", "offset": 2, "size": 1 }, "ADDIS": { "description": "ADDIS", "offset": 1, "size": 1 }, "ADEN": { "description": "ADEN", "offset": 0, "size": 1 } } } }, "CFGR": { "description": "configuration register", "offset": 12, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "AWDCH1CH": { "description": "AWDCH1CH", "offset": 26, "size": 5 }, "JAUTO": { "description": "JAUTO", "offset": 25, "size": 1 }, "JAWD1EN": { "description": "JAWD1EN", "offset": 24, "size": 1 }, "AWD1EN": { "description": "AWD1EN", "offset": 23, "size": 1 }, "AWD1SGL": { "description": "AWD1SGL", "offset": 22, "size": 1 }, "JQM": { "description": "JQM", "offset": 21, "size": 1 }, "JDISCEN": { "description": "JDISCEN", "offset": 20, "size": 1 }, "DISCNUM": { "description": "DISCNUM", "offset": 17, "size": 3 }, "DISCEN": { "description": "DISCEN", "offset": 16, "size": 1 }, "AUTOFF": { "description": "AUTOFF", "offset": 15, "size": 1 }, "AUTDLY": { "description": "AUTDLY", "offset": 14, "size": 1 }, "CONT": { "description": "CONT", "offset": 13, "size": 1 }, "OVRMOD": { "description": "OVRMOD", "offset": 12, "size": 1 }, "EXTEN": { "description": "EXTEN", "offset": 10, "size": 2 }, "EXTSEL": { "description": "EXTSEL", "offset": 6, "size": 4 }, "ALIGN": { "description": "ALIGN", "offset": 5, "size": 1 }, "RES": { "description": "RES", "offset": 3, "size": 2 }, "DMACFG": { "description": "DMACFG", "offset": 1, "size": 1 }, "DMAEN": { "description": "DMAEN", "offset": 0, "size": 1 } } } }, "SMPR1": { "description": "sample time register 1", "offset": 20, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "SMP9": { "description": "SMP9", "offset": 27, "size": 3 }, "SMP8": { "description": "SMP8", "offset": 24, "size": 3 }, "SMP7": { "description": "SMP7", "offset": 21, "size": 3 }, "SMP6": { "description": "SMP6", "offset": 18, "size": 3 }, "SMP5": { "description": "SMP5", "offset": 15, "size": 3 }, "SMP4": { "description": "SMP4", "offset": 12, "size": 3 }, "SMP3": { "description": "SMP3", "offset": 9, "size": 3 }, "SMP2": { "description": "SMP2", "offset": 6, "size": 3 }, "SMP1": { "description": "SMP1", "offset": 3, "size": 3 } } } }, "SMPR2": { "description": "sample time register 2", "offset": 24, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "SMP18": { "description": "SMP18", "offset": 24, "size": 3 }, "SMP17": { "description": "SMP17", "offset": 21, "size": 3 }, "SMP16": { "description": "SMP16", "offset": 18, "size": 3 }, "SMP15": { "description": "SMP15", "offset": 15, "size": 3 }, "SMP14": { "description": "SMP14", "offset": 12, "size": 3 }, "SMP13": { "description": "SMP13", "offset": 9, "size": 3 }, "SMP12": { "description": "SMP12", "offset": 6, "size": 3 }, "SMP11": { "description": "SMP11", "offset": 3, "size": 3 }, "SMP10": { "description": "SMP10", "offset": 0, "size": 3 } } } }, "TR1": { "description": "watchdog threshold register 1", "offset": 32, "size": 32, "reset_value": 268369920, "reset_mask": 4294967295, "children": { "fields": { "HT1": { "description": "HT1", "offset": 16, "size": 12 }, "LT1": { "description": "LT1", "offset": 0, "size": 12 } } } }, "TR2": { "description": "watchdog threshold register", "offset": 36, "size": 32, "reset_value": 268369920, "reset_mask": 4294967295, "children": { "fields": { "HT2": { "description": "HT2", "offset": 16, "size": 8 }, "LT2": { "description": "LT2", "offset": 0, "size": 8 } } } }, "TR3": { "description": "watchdog threshold register 3", "offset": 40, "size": 32, "reset_value": 268369920, "reset_mask": 4294967295, "children": { "fields": { "HT3": { "description": "HT3", "offset": 16, "size": 8 }, "LT3": { "description": "LT3", "offset": 0, "size": 8 } } } }, "SQR1": { "description": "regular sequence register 1", "offset": 48, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "SQ4": { "description": "SQ4", "offset": 24, "size": 5 }, "SQ3": { "description": "SQ3", "offset": 18, "size": 5 }, "SQ2": { "description": "SQ2", "offset": 12, "size": 5 }, "SQ1": { "description": "SQ1", "offset": 6, "size": 5 }, "L3": { "description": "L3", "offset": 0, "size": 4 } } } }, "SQR2": { "description": "regular sequence register 2", "offset": 52, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "SQ9": { "description": "SQ9", "offset": 24, "size": 5 }, "SQ8": { "description": "SQ8", "offset": 18, "size": 5 }, "SQ7": { "description": "SQ7", "offset": 12, "size": 5 }, "SQ6": { "description": "SQ6", "offset": 6, "size": 5 }, "SQ5": { "description": "SQ5", "offset": 0, "size": 5 } } } }, "SQR3": { "description": "regular sequence register 3", "offset": 56, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "SQ14": { "description": "SQ14", "offset": 24, "size": 5 }, "SQ13": { "description": "SQ13", "offset": 18, "size": 5 }, "SQ12": { "description": "SQ12", "offset": 12, "size": 5 }, "SQ11": { "description": "SQ11", "offset": 6, "size": 5 }, "SQ10": { "description": "SQ10", "offset": 0, "size": 5 } } } }, "SQR4": { "description": "regular sequence register 4", "offset": 60, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "SQ16": { "description": "SQ16", "offset": 6, "size": 5 }, "SQ15": { "description": "SQ15", "offset": 0, "size": 5 } } } }, "DR": { "description": "regular Data Register", "offset": 64, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "regularDATA": { "description": "regularDATA", "offset": 0, "size": 16 } } } }, "JSQR": { "description": "injected sequence register", "offset": 76, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "JSQ4": { "description": "JSQ4", "offset": 26, "size": 5 }, "JSQ3": { "description": "JSQ3", "offset": 20, "size": 5 }, "JSQ2": { "description": "JSQ2", "offset": 14, "size": 5 }, "JSQ1": { "description": "JSQ1", "offset": 8, "size": 5 }, "JEXTEN": { "description": "JEXTEN", "offset": 6, "size": 2 }, "JEXTSEL": { "description": "JEXTSEL", "offset": 2, "size": 4 }, "JL": { "description": "JL", "offset": 0, "size": 2 } } } }, "OFR1": { "description": "offset register 1", "offset": 96, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "OFFSET1_EN": { "description": "OFFSET1_EN", "offset": 31, "size": 1 }, "OFFSET1_CH": { "description": "OFFSET1_CH", "offset": 26, "size": 5 }, "OFFSET1": { "description": "OFFSET1", "offset": 0, "size": 12 } } } }, "OFR2": { "description": "offset register 2", "offset": 100, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "OFFSET2_EN": { "description": "OFFSET2_EN", "offset": 31, "size": 1 }, "OFFSET2_CH": { "description": "OFFSET2_CH", "offset": 26, "size": 5 }, "OFFSET2": { "description": "OFFSET2", "offset": 0, "size": 12 } } } }, "OFR3": { "description": "offset register 3", "offset": 104, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "OFFSET3_EN": { "description": "OFFSET3_EN", "offset": 31, "size": 1 }, "OFFSET3_CH": { "description": "OFFSET3_CH", "offset": 26, "size": 5 }, "OFFSET3": { "description": "OFFSET3", "offset": 0, "size": 12 } } } }, "OFR4": { "description": "offset register 4", "offset": 108, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "OFFSET4_EN": { "description": "OFFSET4_EN", "offset": 31, "size": 1 }, "OFFSET4_CH": { "description": "OFFSET4_CH", "offset": 26, "size": 5 }, "OFFSET4": { "description": "OFFSET4", "offset": 0, "size": 12 } } } }, "JDR1": { "description": "injected data register 1", "offset": 128, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "JDATA1": { "description": "JDATA1", "offset": 0, "size": 16 } } } }, "JDR2": { "description": "injected data register 2", "offset": 132, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "JDATA2": { "description": "JDATA2", "offset": 0, "size": 16 } } } }, "JDR3": { "description": "injected data register 3", "offset": 136, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "JDATA3": { "description": "JDATA3", "offset": 0, "size": 16 } } } }, "JDR4": { "description": "injected data register 4", "offset": 140, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "JDATA4": { "description": "JDATA4", "offset": 0, "size": 16 } } } }, "AWD2CR": { "description": "Analog Watchdog 2 Configuration\n Register", "offset": 160, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "AWD2CH": { "description": "AWD2CH", "offset": 1, "size": 18 } } } }, "AWD3CR": { "description": "Analog Watchdog 3 Configuration\n Register", "offset": 164, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "AWD3CH": { "description": "AWD3CH", "offset": 1, "size": 18 } } } }, "DIFSEL": { "description": "Differential Mode Selection Register\n 2", "offset": 176, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DIFSEL_1_15": { "description": "Differential mode for channels 15 to\n 1", "offset": 1, "size": 15 }, "DIFSEL_16_18": { "description": "Differential mode for channels 18 to\n 16", "offset": 16, "size": 3, "access": "read-only" } } } }, "CALFACT": { "description": "Calibration Factors", "offset": 180, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CALFACT_D": { "description": "CALFACT_D", "offset": 16, "size": 7 }, "CALFACT_S": { "description": "CALFACT_S", "offset": 0, "size": 7 } } } } } } }, "TIM8": { "description": "Advanced-timers", "children": { "registers": { "CR1": { "description": "control register 1", "offset": 0, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CEN": { "description": "Counter enable", "offset": 0, "size": 1 }, "UDIS": { "description": "Update disable", "offset": 1, "size": 1 }, "URS": { "description": "Update request source", "offset": 2, "size": 1 }, "OPM": { "description": "One-pulse mode", "offset": 3, "size": 1 }, "DIR": { "description": "Direction", "offset": 4, "size": 1 }, "CMS": { "description": "Center-aligned mode\n selection", "offset": 5, "size": 2 }, "ARPE": { "description": "Auto-reload preload enable", "offset": 7, "size": 1 }, "CKD": { "description": "Clock division", "offset": 8, "size": 2 }, "UIFREMAP": { "description": "UIF status bit remapping", "offset": 11, "size": 1 } } } }, "CR2": { "description": "control register 2", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CCPC": { "description": "Capture/compare preloaded\n control", "offset": 0, "size": 1 }, "CCUS": { "description": "Capture/compare control update\n selection", "offset": 2, "size": 1 }, "CCDS": { "description": "Capture/compare DMA\n selection", "offset": 3, "size": 1 }, "MMS": { "description": "Master mode selection", "offset": 4, "size": 3 }, "TI1S": { "description": "TI1 selection", "offset": 7, "size": 1 }, "OIS1": { "description": "Output Idle state 1", "offset": 8, "size": 1 }, "OIS1N": { "description": "Output Idle state 1", "offset": 9, "size": 1 }, "OIS2": { "description": "Output Idle state 2", "offset": 10, "size": 1 }, "OIS2N": { "description": "Output Idle state 2", "offset": 11, "size": 1 }, "OIS3": { "description": "Output Idle state 3", "offset": 12, "size": 1 }, "OIS3N": { "description": "Output Idle state 3", "offset": 13, "size": 1 }, "OIS4": { "description": "Output Idle state 4", "offset": 14, "size": 1 }, "OIS5": { "description": "Output Idle state 5", "offset": 16, "size": 1 }, "OIS6": { "description": "Output Idle state 6", "offset": 18, "size": 1 }, "MMS2": { "description": "Master mode selection 2", "offset": 20, "size": 4 } } } }, "SMCR": { "description": "slave mode control register", "offset": 8, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "SMS": { "description": "Slave mode selection", "offset": 0, "size": 3 }, "OCCS": { "description": "OCREF clear selection", "offset": 3, "size": 1 }, "TS": { "description": "Trigger selection", "offset": 4, "size": 3 }, "MSM": { "description": "Master/Slave mode", "offset": 7, "size": 1 }, "ETF": { "description": "External trigger filter", "offset": 8, "size": 4 }, "ETPS": { "description": "External trigger prescaler", "offset": 12, "size": 2 }, "ECE": { "description": "External clock enable", "offset": 14, "size": 1 }, "ETP": { "description": "External trigger polarity", "offset": 15, "size": 1 }, "SMS3": { "description": "Slave mode selection bit 3", "offset": 16, "size": 1 } } } }, "DIER": { "description": "DMA/Interrupt enable register", "offset": 12, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "TDE": { "description": "Trigger DMA request enable", "offset": 14, "size": 1 }, "COMDE": { "description": "COM DMA request enable", "offset": 13, "size": 1 }, "CC4DE": { "description": "Capture/Compare 4 DMA request\n enable", "offset": 12, "size": 1 }, "CC3DE": { "description": "Capture/Compare 3 DMA request\n enable", "offset": 11, "size": 1 }, "CC2DE": { "description": "Capture/Compare 2 DMA request\n enable", "offset": 10, "size": 1 }, "CC1DE": { "description": "Capture/Compare 1 DMA request\n enable", "offset": 9, "size": 1 }, "UDE": { "description": "Update DMA request enable", "offset": 8, "size": 1 }, "BIE": { "description": "Break interrupt enable", "offset": 7, "size": 1 }, "TIE": { "description": "Trigger interrupt enable", "offset": 6, "size": 1 }, "COMIE": { "description": "COM interrupt enable", "offset": 5, "size": 1 }, "CC4IE": { "description": "Capture/Compare 4 interrupt\n enable", "offset": 4, "size": 1 }, "CC3IE": { "description": "Capture/Compare 3 interrupt\n enable", "offset": 3, "size": 1 }, "CC2IE": { "description": "Capture/Compare 2 interrupt\n enable", "offset": 2, "size": 1 }, "CC1IE": { "description": "Capture/Compare 1 interrupt\n enable", "offset": 1, "size": 1 }, "UIE": { "description": "Update interrupt enable", "offset": 0, "size": 1 } } } }, "SR": { "description": "status register", "offset": 16, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "UIF": { "description": "Update interrupt flag", "offset": 0, "size": 1 }, "CC1IF": { "description": "Capture/compare 1 interrupt\n flag", "offset": 1, "size": 1 }, "CC2IF": { "description": "Capture/Compare 2 interrupt\n flag", "offset": 2, "size": 1 }, "CC3IF": { "description": "Capture/Compare 3 interrupt\n flag", "offset": 3, "size": 1 }, "CC4IF": { "description": "Capture/Compare 4 interrupt\n flag", "offset": 4, "size": 1 }, "COMIF": { "description": "COM interrupt flag", "offset": 5, "size": 1 }, "TIF": { "description": "Trigger interrupt flag", "offset": 6, "size": 1 }, "BIF": { "description": "Break interrupt flag", "offset": 7, "size": 1 }, "B2IF": { "description": "Break 2 interrupt flag", "offset": 8, "size": 1 }, "CC1OF": { "description": "Capture/Compare 1 overcapture\n flag", "offset": 9, "size": 1 }, "CC2OF": { "description": "Capture/compare 2 overcapture\n flag", "offset": 10, "size": 1 }, "CC3OF": { "description": "Capture/Compare 3 overcapture\n flag", "offset": 11, "size": 1 }, "CC4OF": { "description": "Capture/Compare 4 overcapture\n flag", "offset": 12, "size": 1 }, "C5IF": { "description": "Capture/Compare 5 interrupt\n flag", "offset": 16, "size": 1 }, "C6IF": { "description": "Capture/Compare 6 interrupt\n flag", "offset": 17, "size": 1 } } } }, "EGR": { "description": "event generation register", "offset": 20, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "write-only", "children": { "fields": { "UG": { "description": "Update generation", "offset": 0, "size": 1 }, "CC1G": { "description": "Capture/compare 1\n generation", "offset": 1, "size": 1 }, "CC2G": { "description": "Capture/compare 2\n generation", "offset": 2, "size": 1 }, "CC3G": { "description": "Capture/compare 3\n generation", "offset": 3, "size": 1 }, "CC4G": { "description": "Capture/compare 4\n generation", "offset": 4, "size": 1 }, "COMG": { "description": "Capture/Compare control update\n generation", "offset": 5, "size": 1 }, "TG": { "description": "Trigger generation", "offset": 6, "size": 1 }, "BG": { "description": "Break generation", "offset": 7, "size": 1 }, "B2G": { "description": "Break 2 generation", "offset": 8, "size": 1 } } } }, "CCMR1_Output": { "description": "capture/compare mode register (output\n mode)", "offset": 24, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "OC2CE": { "description": "Output Compare 2 clear\n enable", "offset": 15, "size": 1 }, "OC2M": { "description": "Output Compare 2 mode", "offset": 12, "size": 3 }, "OC2PE": { "description": "Output Compare 2 preload\n enable", "offset": 11, "size": 1 }, "OC2FE": { "description": "Output Compare 2 fast\n enable", "offset": 10, "size": 1 }, "CC2S": { "description": "Capture/Compare 2\n selection", "offset": 8, "size": 2 }, "OC1CE": { "description": "Output Compare 1 clear\n enable", "offset": 7, "size": 1 }, "OC1M": { "description": "Output Compare 1 mode", "offset": 4, "size": 3 }, "OC1PE": { "description": "Output Compare 1 preload\n enable", "offset": 3, "size": 1 }, "OC1FE": { "description": "Output Compare 1 fast\n enable", "offset": 2, "size": 1 }, "CC1S": { "description": "Capture/Compare 1\n selection", "offset": 0, "size": 2 }, "OC1M_3": { "description": "Output Compare 1 mode bit\n 3", "offset": 16, "size": 1 }, "OC2M_3": { "description": "Output Compare 2 mode bit\n 3", "offset": 24, "size": 1 } } } }, "CCMR1_Input": { "description": "capture/compare mode register 1 (input\n mode)", "offset": 24, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IC2F": { "description": "Input capture 2 filter", "offset": 12, "size": 4 }, "IC2PCS": { "description": "Input capture 2 prescaler", "offset": 10, "size": 2 }, "CC2S": { "description": "Capture/Compare 2\n selection", "offset": 8, "size": 2 }, "IC1F": { "description": "Input capture 1 filter", "offset": 4, "size": 4 }, "IC1PCS": { "description": "Input capture 1 prescaler", "offset": 2, "size": 2 }, "CC1S": { "description": "Capture/Compare 1\n selection", "offset": 0, "size": 2 } } } }, "CCMR2_Output": { "description": "capture/compare mode register (output\n mode)", "offset": 28, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "OC4CE": { "description": "Output compare 4 clear\n enable", "offset": 15, "size": 1 }, "OC4M": { "description": "Output compare 4 mode", "offset": 12, "size": 3 }, "OC4PE": { "description": "Output compare 4 preload\n enable", "offset": 11, "size": 1 }, "OC4FE": { "description": "Output compare 4 fast\n enable", "offset": 10, "size": 1 }, "CC4S": { "description": "Capture/Compare 4\n selection", "offset": 8, "size": 2 }, "OC3CE": { "description": "Output compare 3 clear\n enable", "offset": 7, "size": 1 }, "OC3M": { "description": "Output compare 3 mode", "offset": 4, "size": 3 }, "OC3PE": { "description": "Output compare 3 preload\n enable", "offset": 3, "size": 1 }, "OC3FE": { "description": "Output compare 3 fast\n enable", "offset": 2, "size": 1 }, "CC3S": { "description": "Capture/Compare 3\n selection", "offset": 0, "size": 2 }, "OC3M_3": { "description": "Output Compare 3 mode bit\n 3", "offset": 16, "size": 1 }, "OC4M_3": { "description": "Output Compare 4 mode bit\n 3", "offset": 24, "size": 1 } } } }, "CCMR2_Input": { "description": "capture/compare mode register 2 (input\n mode)", "offset": 28, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IC4F": { "description": "Input capture 4 filter", "offset": 12, "size": 4 }, "IC4PSC": { "description": "Input capture 4 prescaler", "offset": 10, "size": 2 }, "CC4S": { "description": "Capture/Compare 4\n selection", "offset": 8, "size": 2 }, "IC3F": { "description": "Input capture 3 filter", "offset": 4, "size": 4 }, "IC3PSC": { "description": "Input capture 3 prescaler", "offset": 2, "size": 2 }, "CC3S": { "description": "Capture/compare 3\n selection", "offset": 0, "size": 2 } } } }, "CCER": { "description": "capture/compare enable\n register", "offset": 32, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CC1E": { "description": "Capture/Compare 1 output\n enable", "offset": 0, "size": 1 }, "CC1P": { "description": "Capture/Compare 1 output\n Polarity", "offset": 1, "size": 1 }, "CC1NE": { "description": "Capture/Compare 1 complementary output\n enable", "offset": 2, "size": 1 }, "CC1NP": { "description": "Capture/Compare 1 output\n Polarity", "offset": 3, "size": 1 }, "CC2E": { "description": "Capture/Compare 2 output\n enable", "offset": 4, "size": 1 }, "CC2P": { "description": "Capture/Compare 2 output\n Polarity", "offset": 5, "size": 1 }, "CC2NE": { "description": "Capture/Compare 2 complementary output\n enable", "offset": 6, "size": 1 }, "CC2NP": { "description": "Capture/Compare 2 output\n Polarity", "offset": 7, "size": 1 }, "CC3E": { "description": "Capture/Compare 3 output\n enable", "offset": 8, "size": 1 }, "CC3P": { "description": "Capture/Compare 3 output\n Polarity", "offset": 9, "size": 1 }, "CC3NE": { "description": "Capture/Compare 3 complementary output\n enable", "offset": 10, "size": 1 }, "CC3NP": { "description": "Capture/Compare 3 output\n Polarity", "offset": 11, "size": 1 }, "CC4E": { "description": "Capture/Compare 4 output\n enable", "offset": 12, "size": 1 }, "CC4P": { "description": "Capture/Compare 3 output\n Polarity", "offset": 13, "size": 1 }, "CC4NP": { "description": "Capture/Compare 4 output\n Polarity", "offset": 15, "size": 1 }, "CC5E": { "description": "Capture/Compare 5 output\n enable", "offset": 16, "size": 1 }, "CC5P": { "description": "Capture/Compare 5 output\n Polarity", "offset": 17, "size": 1 }, "CC6E": { "description": "Capture/Compare 6 output\n enable", "offset": 20, "size": 1 }, "CC6P": { "description": "Capture/Compare 6 output\n Polarity", "offset": 21, "size": 1 } } } }, "CNT": { "description": "counter", "offset": 36, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CNT": { "description": "counter value", "offset": 0, "size": 16 }, "UIFCPY": { "description": "UIF copy", "offset": 31, "size": 1, "access": "read-only" } } } }, "PSC": { "description": "prescaler", "offset": 40, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "PSC": { "description": "Prescaler value", "offset": 0, "size": 16 } } } }, "ARR": { "description": "auto-reload register", "offset": 44, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "ARR": { "description": "Auto-reload value", "offset": 0, "size": 16 } } } }, "RCR": { "description": "repetition counter register", "offset": 48, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "REP": { "description": "Repetition counter value", "offset": 0, "size": 16 } } } }, "CCR1": { "description": "capture/compare register 1", "offset": 52, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CCR1": { "description": "Capture/Compare 1 value", "offset": 0, "size": 16 } } } }, "CCR2": { "description": "capture/compare register 2", "offset": 56, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CCR2": { "description": "Capture/Compare 2 value", "offset": 0, "size": 16 } } } }, "CCR3": { "description": "capture/compare register 3", "offset": 60, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CCR3": { "description": "Capture/Compare 3 value", "offset": 0, "size": 16 } } } }, "CCR4": { "description": "capture/compare register 4", "offset": 64, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CCR4": { "description": "Capture/Compare 3 value", "offset": 0, "size": 16 } } } }, "BDTR": { "description": "break and dead-time register", "offset": 68, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DTG": { "description": "Dead-time generator setup", "offset": 0, "size": 8 }, "LOCK": { "description": "Lock configuration", "offset": 8, "size": 2 }, "OSSI": { "description": "Off-state selection for Idle\n mode", "offset": 10, "size": 1 }, "OSSR": { "description": "Off-state selection for Run\n mode", "offset": 11, "size": 1 }, "BKE": { "description": "Break enable", "offset": 12, "size": 1 }, "BKP": { "description": "Break polarity", "offset": 13, "size": 1 }, "AOE": { "description": "Automatic output enable", "offset": 14, "size": 1 }, "MOE": { "description": "Main output enable", "offset": 15, "size": 1 }, "BKF": { "description": "Break filter", "offset": 16, "size": 4 }, "BK2F": { "description": "Break 2 filter", "offset": 20, "size": 4 }, "BK2E": { "description": "Break 2 enable", "offset": 24, "size": 1 }, "BK2P": { "description": "Break 2 polarity", "offset": 25, "size": 1 } } } }, "DCR": { "description": "DMA control register", "offset": 72, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DBL": { "description": "DMA burst length", "offset": 8, "size": 5 }, "DBA": { "description": "DMA base address", "offset": 0, "size": 5 } } } }, "DMAR": { "description": "DMA address for full transfer", "offset": 76, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DMAB": { "description": "DMA register for burst\n accesses", "offset": 0, "size": 16 } } } }, "CCMR3_Output": { "description": "capture/compare mode register 3 (output\n mode)", "offset": 84, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "OC5FE": { "description": "Output compare 5 fast\n enable", "offset": 2, "size": 1 }, "OC5PE": { "description": "Output compare 5 preload\n enable", "offset": 3, "size": 1 }, "OC5M": { "description": "Output compare 5 mode", "offset": 4, "size": 3 }, "OC5CE": { "description": "Output compare 5 clear\n enable", "offset": 7, "size": 1 }, "OC6FE": { "description": "Output compare 6 fast\n enable", "offset": 10, "size": 1 }, "OC6PE": { "description": "Output compare 6 preload\n enable", "offset": 11, "size": 1 }, "OC6M": { "description": "Output compare 6 mode", "offset": 12, "size": 3 }, "OC6CE": { "description": "Output compare 6 clear\n enable", "offset": 15, "size": 1 }, "OC5M_3": { "description": "Outout Compare 5 mode bit\n 3", "offset": 16, "size": 1 }, "OC6M_3": { "description": "Outout Compare 6 mode bit\n 3", "offset": 24, "size": 1 } } } }, "CCR5": { "description": "capture/compare register 5", "offset": 88, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CCR5": { "description": "Capture/Compare 5 value", "offset": 0, "size": 16 }, "GC5C1": { "description": "Group Channel 5 and Channel\n 1", "offset": 29, "size": 1 }, "GC5C2": { "description": "Group Channel 5 and Channel\n 2", "offset": 30, "size": 1 }, "GC5C3": { "description": "Group Channel 5 and Channel\n 3", "offset": 31, "size": 1 } } } }, "CCR6": { "description": "capture/compare register 6", "offset": 92, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CCR6": { "description": "Capture/Compare 6 value", "offset": 0, "size": 16 } } } }, "OR": { "description": "option registers", "offset": 96, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "TIM8_ETR_ADC2_RMP": { "description": "TIM8_ETR_ADC2 remapping\n capability", "offset": 0, "size": 2 }, "TIM8_ETR_ADC3_RMP": { "description": "TIM8_ETR_ADC3 remapping\n capability", "offset": 2, "size": 2 } } } } } } }, "DAC": { "description": "Digital-to-analog converter", "children": { "registers": { "CR": { "description": "control register", "offset": 0, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DMAUDRIE2": { "description": "DAC channel2 DMA underrun interrupt\n enable", "offset": 29, "size": 1 }, "DMAEN2": { "description": "DAC channel2 DMA enable", "offset": 28, "size": 1 }, "MAMP2": { "description": "DAC channel2 mask/amplitude\n selector", "offset": 24, "size": 4 }, "WAVE2": { "description": "DAC channel2 noise/triangle wave\n generation enable", "offset": 22, "size": 2 }, "TSEL2": { "description": "DAC channel2 trigger\n selection", "offset": 19, "size": 3 }, "TEN2": { "description": "DAC channel2 trigger\n enable", "offset": 18, "size": 1 }, "BOFF2": { "description": "DAC channel2 output buffer\n disable", "offset": 17, "size": 1 }, "EN2": { "description": "DAC channel2 enable", "offset": 16, "size": 1 }, "DMAUDRIE1": { "description": "DAC channel1 DMA Underrun Interrupt\n enable", "offset": 13, "size": 1 }, "DMAEN1": { "description": "DAC channel1 DMA enable", "offset": 12, "size": 1 }, "MAMP1": { "description": "DAC channel1 mask/amplitude\n selector", "offset": 8, "size": 4 }, "WAVE1": { "description": "DAC channel1 noise/triangle wave\n generation enable", "offset": 6, "size": 2 }, "TSEL1": { "description": "DAC channel1 trigger\n selection", "offset": 3, "size": 3 }, "TEN1": { "description": "DAC channel1 trigger\n enable", "offset": 2, "size": 1 }, "BOFF1": { "description": "DAC channel1 output buffer\n disable", "offset": 1, "size": 1 }, "EN1": { "description": "DAC channel1 enable", "offset": 0, "size": 1 } } } }, "SWTRIGR": { "description": "software trigger register", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "write-only", "children": { "fields": { "SWTRIG2": { "description": "DAC channel2 software\n trigger", "offset": 1, "size": 1 }, "SWTRIG1": { "description": "DAC channel1 software\n trigger", "offset": 0, "size": 1 } } } }, "DHR12R1": { "description": "channel1 12-bit right-aligned data holding\n register", "offset": 8, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DACC1DHR": { "description": "DAC channel1 12-bit right-aligned\n data", "offset": 0, "size": 12 } } } }, "DHR12L1": { "description": "channel1 12-bit left aligned data holding\n register", "offset": 12, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DACC1DHR": { "description": "DAC channel1 12-bit left-aligned\n data", "offset": 4, "size": 12 } } } }, "DHR8R1": { "description": "channel1 8-bit right aligned data holding\n register", "offset": 16, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DACC1DHR": { "description": "DAC channel1 8-bit right-aligned\n data", "offset": 0, "size": 8 } } } }, "DHR12R2": { "description": "channel2 12-bit right aligned data holding\n register", "offset": 20, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DACC2DHR": { "description": "DAC channel2 12-bit right-aligned\n data", "offset": 0, "size": 12 } } } }, "DHR12L2": { "description": "channel2 12-bit left aligned data holding\n register", "offset": 24, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DACC2DHR": { "description": "DAC channel2 12-bit left-aligned\n data", "offset": 4, "size": 12 } } } }, "DHR8R2": { "description": "channel2 8-bit right-aligned data holding\n register", "offset": 28, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DACC2DHR": { "description": "DAC channel2 8-bit right-aligned\n data", "offset": 0, "size": 8 } } } }, "DHR12RD": { "description": "Dual DAC 12-bit right-aligned data holding\n register", "offset": 32, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DACC2DHR": { "description": "DAC channel2 12-bit right-aligned\n data", "offset": 16, "size": 12 }, "DACC1DHR": { "description": "DAC channel1 12-bit right-aligned\n data", "offset": 0, "size": 12 } } } }, "DHR12LD": { "description": "DUAL DAC 12-bit left aligned data holding\n register", "offset": 36, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DACC2DHR": { "description": "DAC channel2 12-bit left-aligned\n data", "offset": 20, "size": 12 }, "DACC1DHR": { "description": "DAC channel1 12-bit left-aligned\n data", "offset": 4, "size": 12 } } } }, "DHR8RD": { "description": "DUAL DAC 8-bit right aligned data holding\n register", "offset": 40, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DACC2DHR": { "description": "DAC channel2 8-bit right-aligned\n data", "offset": 8, "size": 8 }, "DACC1DHR": { "description": "DAC channel1 8-bit right-aligned\n data", "offset": 0, "size": 8 } } } }, "DOR1": { "description": "channel1 data output register", "offset": 44, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "DACC1DOR": { "description": "DAC channel1 data output", "offset": 0, "size": 12 } } } }, "DOR2": { "description": "channel2 data output register", "offset": 48, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "DACC2DOR": { "description": "DAC channel2 data output", "offset": 0, "size": 12 } } } }, "SR": { "description": "status register", "offset": 52, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DMAUDR2": { "description": "DAC channel2 DMA underrun\n flag", "offset": 29, "size": 1 }, "DMAUDR1": { "description": "DAC channel1 DMA underrun\n flag", "offset": 13, "size": 1 } } } } } } }, "EXTI": { "description": "External interrupt/event\n controller", "children": { "registers": { "IMR1": { "description": "Interrupt mask register", "offset": 0, "size": 32, "reset_value": 528482304, "reset_mask": 4294967295, "children": { "fields": { "MR0": { "description": "Interrupt Mask on line 0", "offset": 0, "size": 1 }, "MR1": { "description": "Interrupt Mask on line 1", "offset": 1, "size": 1 }, "MR2": { "description": "Interrupt Mask on line 2", "offset": 2, "size": 1 }, "MR3": { "description": "Interrupt Mask on line 3", "offset": 3, "size": 1 }, "MR4": { "description": "Interrupt Mask on line 4", "offset": 4, "size": 1 }, "MR5": { "description": "Interrupt Mask on line 5", "offset": 5, "size": 1 }, "MR6": { "description": "Interrupt Mask on line 6", "offset": 6, "size": 1 }, "MR7": { "description": "Interrupt Mask on line 7", "offset": 7, "size": 1 }, "MR8": { "description": "Interrupt Mask on line 8", "offset": 8, "size": 1 }, "MR9": { "description": "Interrupt Mask on line 9", "offset": 9, "size": 1 }, "MR10": { "description": "Interrupt Mask on line 10", "offset": 10, "size": 1 }, "MR11": { "description": "Interrupt Mask on line 11", "offset": 11, "size": 1 }, "MR12": { "description": "Interrupt Mask on line 12", "offset": 12, "size": 1 }, "MR13": { "description": "Interrupt Mask on line 13", "offset": 13, "size": 1 }, "MR14": { "description": "Interrupt Mask on line 14", "offset": 14, "size": 1 }, "MR15": { "description": "Interrupt Mask on line 15", "offset": 15, "size": 1 }, "MR16": { "description": "Interrupt Mask on line 16", "offset": 16, "size": 1 }, "MR17": { "description": "Interrupt Mask on line 17", "offset": 17, "size": 1 }, "MR18": { "description": "Interrupt Mask on line 18", "offset": 18, "size": 1 }, "MR19": { "description": "Interrupt Mask on line 19", "offset": 19, "size": 1 }, "MR20": { "description": "Interrupt Mask on line 20", "offset": 20, "size": 1 }, "MR21": { "description": "Interrupt Mask on line 21", "offset": 21, "size": 1 }, "MR22": { "description": "Interrupt Mask on line 22", "offset": 22, "size": 1 }, "MR23": { "description": "Interrupt Mask on line 23", "offset": 23, "size": 1 }, "MR24": { "description": "Interrupt Mask on line 24", "offset": 24, "size": 1 }, "MR25": { "description": "Interrupt Mask on line 25", "offset": 25, "size": 1 }, "MR26": { "description": "Interrupt Mask on line 26", "offset": 26, "size": 1 }, "MR27": { "description": "Interrupt Mask on line 27", "offset": 27, "size": 1 }, "MR28": { "description": "Interrupt Mask on line 28", "offset": 28, "size": 1 }, "MR29": { "description": "Interrupt Mask on line 29", "offset": 29, "size": 1 }, "MR30": { "description": "Interrupt Mask on line 30", "offset": 30, "size": 1 }, "MR31": { "description": "Interrupt Mask on line 31", "offset": 31, "size": 1 } } } }, "EMR1": { "description": "Event mask register", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "MR0": { "description": "Event Mask on line 0", "offset": 0, "size": 1 }, "MR1": { "description": "Event Mask on line 1", "offset": 1, "size": 1 }, "MR2": { "description": "Event Mask on line 2", "offset": 2, "size": 1 }, "MR3": { "description": "Event Mask on line 3", "offset": 3, "size": 1 }, "MR4": { "description": "Event Mask on line 4", "offset": 4, "size": 1 }, "MR5": { "description": "Event Mask on line 5", "offset": 5, "size": 1 }, "MR6": { "description": "Event Mask on line 6", "offset": 6, "size": 1 }, "MR7": { "description": "Event Mask on line 7", "offset": 7, "size": 1 }, "MR8": { "description": "Event Mask on line 8", "offset": 8, "size": 1 }, "MR9": { "description": "Event Mask on line 9", "offset": 9, "size": 1 }, "MR10": { "description": "Event Mask on line 10", "offset": 10, "size": 1 }, "MR11": { "description": "Event Mask on line 11", "offset": 11, "size": 1 }, "MR12": { "description": "Event Mask on line 12", "offset": 12, "size": 1 }, "MR13": { "description": "Event Mask on line 13", "offset": 13, "size": 1 }, "MR14": { "description": "Event Mask on line 14", "offset": 14, "size": 1 }, "MR15": { "description": "Event Mask on line 15", "offset": 15, "size": 1 }, "MR16": { "description": "Event Mask on line 16", "offset": 16, "size": 1 }, "MR17": { "description": "Event Mask on line 17", "offset": 17, "size": 1 }, "MR18": { "description": "Event Mask on line 18", "offset": 18, "size": 1 }, "MR19": { "description": "Event Mask on line 19", "offset": 19, "size": 1 }, "MR20": { "description": "Event Mask on line 20", "offset": 20, "size": 1 }, "MR21": { "description": "Event Mask on line 21", "offset": 21, "size": 1 }, "MR22": { "description": "Event Mask on line 22", "offset": 22, "size": 1 }, "MR23": { "description": "Event Mask on line 23", "offset": 23, "size": 1 }, "MR24": { "description": "Event Mask on line 24", "offset": 24, "size": 1 }, "MR25": { "description": "Event Mask on line 25", "offset": 25, "size": 1 }, "MR26": { "description": "Event Mask on line 26", "offset": 26, "size": 1 }, "MR27": { "description": "Event Mask on line 27", "offset": 27, "size": 1 }, "MR28": { "description": "Event Mask on line 28", "offset": 28, "size": 1 }, "MR29": { "description": "Event Mask on line 29", "offset": 29, "size": 1 }, "MR30": { "description": "Event Mask on line 30", "offset": 30, "size": 1 }, "MR31": { "description": "Event Mask on line 31", "offset": 31, "size": 1 } } } }, "RTSR1": { "description": "Rising Trigger selection\n register", "offset": 8, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "TR0": { "description": "Rising trigger event configuration of\n line 0", "offset": 0, "size": 1 }, "TR1": { "description": "Rising trigger event configuration of\n line 1", "offset": 1, "size": 1 }, "TR2": { "description": "Rising trigger event configuration of\n line 2", "offset": 2, "size": 1 }, "TR3": { "description": "Rising trigger event configuration of\n line 3", "offset": 3, "size": 1 }, "TR4": { "description": "Rising trigger event configuration of\n line 4", "offset": 4, "size": 1 }, "TR5": { "description": "Rising trigger event configuration of\n line 5", "offset": 5, "size": 1 }, "TR6": { "description": "Rising trigger event configuration of\n line 6", "offset": 6, "size": 1 }, "TR7": { "description": "Rising trigger event configuration of\n line 7", "offset": 7, "size": 1 }, "TR8": { "description": "Rising trigger event configuration of\n line 8", "offset": 8, "size": 1 }, "TR9": { "description": "Rising trigger event configuration of\n line 9", "offset": 9, "size": 1 }, "TR10": { "description": "Rising trigger event configuration of\n line 10", "offset": 10, "size": 1 }, "TR11": { "description": "Rising trigger event configuration of\n line 11", "offset": 11, "size": 1 }, "TR12": { "description": "Rising trigger event configuration of\n line 12", "offset": 12, "size": 1 }, "TR13": { "description": "Rising trigger event configuration of\n line 13", "offset": 13, "size": 1 }, "TR14": { "description": "Rising trigger event configuration of\n line 14", "offset": 14, "size": 1 }, "TR15": { "description": "Rising trigger event configuration of\n line 15", "offset": 15, "size": 1 }, "TR16": { "description": "Rising trigger event configuration of\n line 16", "offset": 16, "size": 1 }, "TR17": { "description": "Rising trigger event configuration of\n line 17", "offset": 17, "size": 1 }, "TR18": { "description": "Rising trigger event configuration of\n line 18", "offset": 18, "size": 1 }, "TR19": { "description": "Rising trigger event configuration of\n line 19", "offset": 19, "size": 1 }, "TR20": { "description": "Rising trigger event configuration of\n line 20", "offset": 20, "size": 1 }, "TR21": { "description": "Rising trigger event configuration of\n line 21", "offset": 21, "size": 1 }, "TR22": { "description": "Rising trigger event configuration of\n line 22", "offset": 22, "size": 1 }, "TR29": { "description": "Rising trigger event configuration of\n line 29", "offset": 29, "size": 1 }, "TR30": { "description": "Rising trigger event configuration of\n line 30", "offset": 30, "size": 1 }, "TR31": { "description": "Rising trigger event configuration of\n line 31", "offset": 31, "size": 1 } } } }, "FTSR1": { "description": "Falling Trigger selection\n register", "offset": 12, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "TR0": { "description": "Falling trigger event configuration of\n line 0", "offset": 0, "size": 1 }, "TR1": { "description": "Falling trigger event configuration of\n line 1", "offset": 1, "size": 1 }, "TR2": { "description": "Falling trigger event configuration of\n line 2", "offset": 2, "size": 1 }, "TR3": { "description": "Falling trigger event configuration of\n line 3", "offset": 3, "size": 1 }, "TR4": { "description": "Falling trigger event configuration of\n line 4", "offset": 4, "size": 1 }, "TR5": { "description": "Falling trigger event configuration of\n line 5", "offset": 5, "size": 1 }, "TR6": { "description": "Falling trigger event configuration of\n line 6", "offset": 6, "size": 1 }, "TR7": { "description": "Falling trigger event configuration of\n line 7", "offset": 7, "size": 1 }, "TR8": { "description": "Falling trigger event configuration of\n line 8", "offset": 8, "size": 1 }, "TR9": { "description": "Falling trigger event configuration of\n line 9", "offset": 9, "size": 1 }, "TR10": { "description": "Falling trigger event configuration of\n line 10", "offset": 10, "size": 1 }, "TR11": { "description": "Falling trigger event configuration of\n line 11", "offset": 11, "size": 1 }, "TR12": { "description": "Falling trigger event configuration of\n line 12", "offset": 12, "size": 1 }, "TR13": { "description": "Falling trigger event configuration of\n line 13", "offset": 13, "size": 1 }, "TR14": { "description": "Falling trigger event configuration of\n line 14", "offset": 14, "size": 1 }, "TR15": { "description": "Falling trigger event configuration of\n line 15", "offset": 15, "size": 1 }, "TR16": { "description": "Falling trigger event configuration of\n line 16", "offset": 16, "size": 1 }, "TR17": { "description": "Falling trigger event configuration of\n line 17", "offset": 17, "size": 1 }, "TR18": { "description": "Falling trigger event configuration of\n line 18", "offset": 18, "size": 1 }, "TR19": { "description": "Falling trigger event configuration of\n line 19", "offset": 19, "size": 1 }, "TR20": { "description": "Falling trigger event configuration of\n line 20", "offset": 20, "size": 1 }, "TR21": { "description": "Falling trigger event configuration of\n line 21", "offset": 21, "size": 1 }, "TR22": { "description": "Falling trigger event configuration of\n line 22", "offset": 22, "size": 1 }, "TR29": { "description": "Falling trigger event configuration of\n line 29", "offset": 29, "size": 1 }, "TR30": { "description": "Falling trigger event configuration of\n line 30.", "offset": 30, "size": 1 }, "TR31": { "description": "Falling trigger event configuration of\n line 31", "offset": 31, "size": 1 } } } }, "SWIER1": { "description": "Software interrupt event\n register", "offset": 16, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "SWIER0": { "description": "Software Interrupt on line\n 0", "offset": 0, "size": 1 }, "SWIER1": { "description": "Software Interrupt on line\n 1", "offset": 1, "size": 1 }, "SWIER2": { "description": "Software Interrupt on line\n 2", "offset": 2, "size": 1 }, "SWIER3": { "description": "Software Interrupt on line\n 3", "offset": 3, "size": 1 }, "SWIER4": { "description": "Software Interrupt on line\n 4", "offset": 4, "size": 1 }, "SWIER5": { "description": "Software Interrupt on line\n 5", "offset": 5, "size": 1 }, "SWIER6": { "description": "Software Interrupt on line\n 6", "offset": 6, "size": 1 }, "SWIER7": { "description": "Software Interrupt on line\n 7", "offset": 7, "size": 1 }, "SWIER8": { "description": "Software Interrupt on line\n 8", "offset": 8, "size": 1 }, "SWIER9": { "description": "Software Interrupt on line\n 9", "offset": 9, "size": 1 }, "SWIER10": { "description": "Software Interrupt on line\n 10", "offset": 10, "size": 1 }, "SWIER11": { "description": "Software Interrupt on line\n 11", "offset": 11, "size": 1 }, "SWIER12": { "description": "Software Interrupt on line\n 12", "offset": 12, "size": 1 }, "SWIER13": { "description": "Software Interrupt on line\n 13", "offset": 13, "size": 1 }, "SWIER14": { "description": "Software Interrupt on line\n 14", "offset": 14, "size": 1 }, "SWIER15": { "description": "Software Interrupt on line\n 15", "offset": 15, "size": 1 }, "SWIER16": { "description": "Software Interrupt on line\n 16", "offset": 16, "size": 1 }, "SWIER17": { "description": "Software Interrupt on line\n 17", "offset": 17, "size": 1 }, "SWIER18": { "description": "Software Interrupt on line\n 18", "offset": 18, "size": 1 }, "SWIER19": { "description": "Software Interrupt on line\n 19", "offset": 19, "size": 1 }, "SWIER20": { "description": "Software Interrupt on line\n 20", "offset": 20, "size": 1 }, "SWIER21": { "description": "Software Interrupt on line\n 21", "offset": 21, "size": 1 }, "SWIER22": { "description": "Software Interrupt on line\n 22", "offset": 22, "size": 1 }, "SWIER29": { "description": "Software Interrupt on line\n 29", "offset": 29, "size": 1 }, "SWIER30": { "description": "Software Interrupt on line\n 309", "offset": 30, "size": 1 }, "SWIER31": { "description": "Software Interrupt on line\n 319", "offset": 31, "size": 1 } } } }, "PR1": { "description": "Pending register", "offset": 20, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "PR0": { "description": "Pending bit 0", "offset": 0, "size": 1 }, "PR1": { "description": "Pending bit 1", "offset": 1, "size": 1 }, "PR2": { "description": "Pending bit 2", "offset": 2, "size": 1 }, "PR3": { "description": "Pending bit 3", "offset": 3, "size": 1 }, "PR4": { "description": "Pending bit 4", "offset": 4, "size": 1 }, "PR5": { "description": "Pending bit 5", "offset": 5, "size": 1 }, "PR6": { "description": "Pending bit 6", "offset": 6, "size": 1 }, "PR7": { "description": "Pending bit 7", "offset": 7, "size": 1 }, "PR8": { "description": "Pending bit 8", "offset": 8, "size": 1 }, "PR9": { "description": "Pending bit 9", "offset": 9, "size": 1 }, "PR10": { "description": "Pending bit 10", "offset": 10, "size": 1 }, "PR11": { "description": "Pending bit 11", "offset": 11, "size": 1 }, "PR12": { "description": "Pending bit 12", "offset": 12, "size": 1 }, "PR13": { "description": "Pending bit 13", "offset": 13, "size": 1 }, "PR14": { "description": "Pending bit 14", "offset": 14, "size": 1 }, "PR15": { "description": "Pending bit 15", "offset": 15, "size": 1 }, "PR16": { "description": "Pending bit 16", "offset": 16, "size": 1 }, "PR17": { "description": "Pending bit 17", "offset": 17, "size": 1 }, "PR18": { "description": "Pending bit 18", "offset": 18, "size": 1 }, "PR19": { "description": "Pending bit 19", "offset": 19, "size": 1 }, "PR20": { "description": "Pending bit 20", "offset": 20, "size": 1 }, "PR21": { "description": "Pending bit 21", "offset": 21, "size": 1 }, "PR22": { "description": "Pending bit 22", "offset": 22, "size": 1 }, "PR29": { "description": "Pending bit 29", "offset": 29, "size": 1 }, "PR30": { "description": "Pending bit 30", "offset": 30, "size": 1 }, "PR31": { "description": "Pending bit 31", "offset": 31, "size": 1 } } } }, "IMR2": { "description": "Interrupt mask register", "offset": 24, "size": 32, "reset_value": 4294967292, "reset_mask": 4294967295, "children": { "fields": { "MR32": { "description": "Interrupt Mask on external/internal line\n 32", "offset": 0, "size": 1 }, "MR33": { "description": "Interrupt Mask on external/internal line\n 33", "offset": 1, "size": 1 }, "MR34": { "description": "Interrupt Mask on external/internal line\n 34", "offset": 2, "size": 1 }, "MR35": { "description": "Interrupt Mask on external/internal line\n 35", "offset": 3, "size": 1 } } } }, "EMR2": { "description": "Event mask register", "offset": 28, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "MR32": { "description": "Event mask on external/internal line\n 32", "offset": 0, "size": 1 }, "MR33": { "description": "Event mask on external/internal line\n 33", "offset": 1, "size": 1 }, "MR34": { "description": "Event mask on external/internal line\n 34", "offset": 2, "size": 1 }, "MR35": { "description": "Event mask on external/internal line\n 35", "offset": 3, "size": 1 } } } }, "RTSR2": { "description": "Rising Trigger selection\n register", "offset": 32, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "TR32": { "description": "Rising trigger event configuration bit\n of line 32", "offset": 0, "size": 1 }, "TR33": { "description": "Rising trigger event configuration bit\n of line 33", "offset": 1, "size": 1 } } } }, "FTSR2": { "description": "Falling Trigger selection\n register", "offset": 36, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "TR32": { "description": "Falling trigger event configuration bit\n of line 32", "offset": 0, "size": 1 }, "TR33": { "description": "Falling trigger event configuration bit\n of line 33", "offset": 1, "size": 1 } } } }, "SWIER2": { "description": "Software interrupt event\n register", "offset": 40, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "SWIER32": { "description": "Software interrupt on line\n 32", "offset": 0, "size": 1 }, "SWIER33": { "description": "Software interrupt on line\n 33", "offset": 1, "size": 1 } } } }, "PR2": { "description": "Pending register", "offset": 44, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "PR32": { "description": "Pending bit on line 32", "offset": 0, "size": 1 }, "PR33": { "description": "Pending bit on line 33", "offset": 1, "size": 1 } } } } } } }, "PWR": { "description": "Power control", "children": { "registers": { "CR": { "description": "power control register", "offset": 0, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "LPDS": { "description": "Low-power deep sleep", "offset": 0, "size": 1 }, "PDDS": { "description": "Power down deepsleep", "offset": 1, "size": 1 }, "CWUF": { "description": "Clear wakeup flag", "offset": 2, "size": 1 }, "CSBF": { "description": "Clear standby flag", "offset": 3, "size": 1 }, "PVDE": { "description": "Power voltage detector\n enable", "offset": 4, "size": 1 }, "PLS": { "description": "PVD level selection", "offset": 5, "size": 3 }, "DBP": { "description": "Disable backup domain write\n protection", "offset": 8, "size": 1 } } } }, "CSR": { "description": "power control/status register", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "WUF": { "description": "Wakeup flag", "offset": 0, "size": 1, "access": "read-only" }, "SBF": { "description": "Standby flag", "offset": 1, "size": 1, "access": "read-only" }, "PVDO": { "description": "PVD output", "offset": 2, "size": 1, "access": "read-only" }, "EWUP1": { "description": "Enable WKUP1 pin", "offset": 8, "size": 1 }, "EWUP2": { "description": "Enable WKUP2 pin", "offset": 9, "size": 1 } } } } } } }, "CAN": { "description": "Controller area network", "children": { "registers": { "MCR": { "description": "master control register", "offset": 0, "size": 32, "reset_value": 65538, "reset_mask": 4294967295, "children": { "fields": { "DBF": { "description": "DBF", "offset": 16, "size": 1 }, "RESET": { "description": "RESET", "offset": 15, "size": 1 }, "TTCM": { "description": "TTCM", "offset": 7, "size": 1 }, "ABOM": { "description": "ABOM", "offset": 6, "size": 1 }, "AWUM": { "description": "AWUM", "offset": 5, "size": 1 }, "NART": { "description": "NART", "offset": 4, "size": 1 }, "RFLM": { "description": "RFLM", "offset": 3, "size": 1 }, "TXFP": { "description": "TXFP", "offset": 2, "size": 1 }, "SLEEP": { "description": "SLEEP", "offset": 1, "size": 1 }, "INRQ": { "description": "INRQ", "offset": 0, "size": 1 } } } }, "MSR": { "description": "master status register", "offset": 4, "size": 32, "reset_value": 3074, "reset_mask": 4294967295, "children": { "fields": { "RX": { "description": "RX", "offset": 11, "size": 1, "access": "read-only" }, "SAMP": { "description": "SAMP", "offset": 10, "size": 1, "access": "read-only" }, "RXM": { "description": "RXM", "offset": 9, "size": 1, "access": "read-only" }, "TXM": { "description": "TXM", "offset": 8, "size": 1, "access": "read-only" }, "SLAKI": { "description": "SLAKI", "offset": 4, "size": 1 }, "WKUI": { "description": "WKUI", "offset": 3, "size": 1 }, "ERRI": { "description": "ERRI", "offset": 2, "size": 1 }, "SLAK": { "description": "SLAK", "offset": 1, "size": 1, "access": "read-only" }, "INAK": { "description": "INAK", "offset": 0, "size": 1, "access": "read-only" } } } }, "TSR": { "description": "transmit status register", "offset": 8, "size": 32, "reset_value": 469762048, "reset_mask": 4294967295, "children": { "fields": { "LOW2": { "description": "Lowest priority flag for mailbox\n 2", "offset": 31, "size": 1, "access": "read-only" }, "LOW1": { "description": "Lowest priority flag for mailbox\n 1", "offset": 30, "size": 1, "access": "read-only" }, "LOW0": { "description": "Lowest priority flag for mailbox\n 0", "offset": 29, "size": 1, "access": "read-only" }, "TME2": { "description": "Lowest priority flag for mailbox\n 2", "offset": 28, "size": 1, "access": "read-only" }, "TME1": { "description": "Lowest priority flag for mailbox\n 1", "offset": 27, "size": 1, "access": "read-only" }, "TME0": { "description": "Lowest priority flag for mailbox\n 0", "offset": 26, "size": 1, "access": "read-only" }, "CODE": { "description": "CODE", "offset": 24, "size": 2, "access": "read-only" }, "ABRQ2": { "description": "ABRQ2", "offset": 23, "size": 1 }, "TERR2": { "description": "TERR2", "offset": 19, "size": 1 }, "ALST2": { "description": "ALST2", "offset": 18, "size": 1 }, "TXOK2": { "description": "TXOK2", "offset": 17, "size": 1 }, "RQCP2": { "description": "RQCP2", "offset": 16, "size": 1 }, "ABRQ1": { "description": "ABRQ1", "offset": 15, "size": 1 }, "TERR1": { "description": "TERR1", "offset": 11, "size": 1 }, "ALST1": { "description": "ALST1", "offset": 10, "size": 1 }, "TXOK1": { "description": "TXOK1", "offset": 9, "size": 1 }, "RQCP1": { "description": "RQCP1", "offset": 8, "size": 1 }, "ABRQ0": { "description": "ABRQ0", "offset": 7, "size": 1 }, "TERR0": { "description": "TERR0", "offset": 3, "size": 1 }, "ALST0": { "description": "ALST0", "offset": 2, "size": 1 }, "TXOK0": { "description": "TXOK0", "offset": 1, "size": 1 }, "RQCP0": { "description": "RQCP0", "offset": 0, "size": 1 } } } }, "RF0R": { "description": "receive FIFO 0 register", "offset": 12, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "RFOM0": { "description": "RFOM0", "offset": 5, "size": 1 }, "FOVR0": { "description": "FOVR0", "offset": 4, "size": 1 }, "FULL0": { "description": "FULL0", "offset": 3, "size": 1 }, "FMP0": { "description": "FMP0", "offset": 0, "size": 2, "access": "read-only" } } } }, "RF1R": { "description": "receive FIFO 1 register", "offset": 16, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "RFOM1": { "description": "RFOM1", "offset": 5, "size": 1 }, "FOVR1": { "description": "FOVR1", "offset": 4, "size": 1 }, "FULL1": { "description": "FULL1", "offset": 3, "size": 1 }, "FMP1": { "description": "FMP1", "offset": 0, "size": 2, "access": "read-only" } } } }, "IER": { "description": "interrupt enable register", "offset": 20, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "SLKIE": { "description": "SLKIE", "offset": 17, "size": 1 }, "WKUIE": { "description": "WKUIE", "offset": 16, "size": 1 }, "ERRIE": { "description": "ERRIE", "offset": 15, "size": 1 }, "LECIE": { "description": "LECIE", "offset": 11, "size": 1 }, "BOFIE": { "description": "BOFIE", "offset": 10, "size": 1 }, "EPVIE": { "description": "EPVIE", "offset": 9, "size": 1 }, "EWGIE": { "description": "EWGIE", "offset": 8, "size": 1 }, "FOVIE1": { "description": "FOVIE1", "offset": 6, "size": 1 }, "FFIE1": { "description": "FFIE1", "offset": 5, "size": 1 }, "FMPIE1": { "description": "FMPIE1", "offset": 4, "size": 1 }, "FOVIE0": { "description": "FOVIE0", "offset": 3, "size": 1 }, "FFIE0": { "description": "FFIE0", "offset": 2, "size": 1 }, "FMPIE0": { "description": "FMPIE0", "offset": 1, "size": 1 }, "TMEIE": { "description": "TMEIE", "offset": 0, "size": 1 } } } }, "ESR": { "description": "error status register", "offset": 24, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "REC": { "description": "REC", "offset": 24, "size": 8, "access": "read-only" }, "TEC": { "description": "TEC", "offset": 16, "size": 8, "access": "read-only" }, "LEC": { "description": "LEC", "offset": 4, "size": 3 }, "BOFF": { "description": "BOFF", "offset": 2, "size": 1, "access": "read-only" }, "EPVF": { "description": "EPVF", "offset": 1, "size": 1, "access": "read-only" }, "EWGF": { "description": "EWGF", "offset": 0, "size": 1, "access": "read-only" } } } }, "BTR": { "description": "bit timing register", "offset": 28, "size": 32, "reset_value": 19070976, "reset_mask": 4294967295, "children": { "fields": { "SILM": { "description": "SILM", "offset": 31, "size": 1 }, "LBKM": { "description": "LBKM", "offset": 30, "size": 1 }, "SJW": { "description": "SJW", "offset": 24, "size": 2 }, "TS2": { "description": "TS2", "offset": 20, "size": 3 }, "TS1": { "description": "TS1", "offset": 16, "size": 4 }, "BRP": { "description": "BRP", "offset": 0, "size": 10 } } } }, "TI0R": { "description": "TX mailbox identifier register", "offset": 384, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "STID": { "description": "STID", "offset": 21, "size": 11 }, "EXID": { "description": "EXID", "offset": 3, "size": 18 }, "IDE": { "description": "IDE", "offset": 2, "size": 1 }, "RTR": { "description": "RTR", "offset": 1, "size": 1 }, "TXRQ": { "description": "TXRQ", "offset": 0, "size": 1 } } } }, "TDT0R": { "description": "mailbox data length control and time stamp\n register", "offset": 388, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "TIME": { "description": "TIME", "offset": 16, "size": 16 }, "TGT": { "description": "TGT", "offset": 8, "size": 1 }, "DLC": { "description": "DLC", "offset": 0, "size": 4 } } } }, "TDL0R": { "description": "mailbox data low register", "offset": 392, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DATA3": { "description": "DATA3", "offset": 24, "size": 8 }, "DATA2": { "description": "DATA2", "offset": 16, "size": 8 }, "DATA1": { "description": "DATA1", "offset": 8, "size": 8 }, "DATA0": { "description": "DATA0", "offset": 0, "size": 8 } } } }, "TDH0R": { "description": "mailbox data high register", "offset": 396, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DATA7": { "description": "DATA7", "offset": 24, "size": 8 }, "DATA6": { "description": "DATA6", "offset": 16, "size": 8 }, "DATA5": { "description": "DATA5", "offset": 8, "size": 8 }, "DATA4": { "description": "DATA4", "offset": 0, "size": 8 } } } }, "TI1R": { "description": "TX mailbox identifier register", "offset": 400, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "STID": { "description": "STID", "offset": 21, "size": 11 }, "EXID": { "description": "EXID", "offset": 3, "size": 18 }, "IDE": { "description": "IDE", "offset": 2, "size": 1 }, "RTR": { "description": "RTR", "offset": 1, "size": 1 }, "TXRQ": { "description": "TXRQ", "offset": 0, "size": 1 } } } }, "TDT1R": { "description": "mailbox data length control and time stamp\n register", "offset": 404, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "TIME": { "description": "TIME", "offset": 16, "size": 16 }, "TGT": { "description": "TGT", "offset": 8, "size": 1 }, "DLC": { "description": "DLC", "offset": 0, "size": 4 } } } }, "TDL1R": { "description": "mailbox data low register", "offset": 408, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DATA3": { "description": "DATA3", "offset": 24, "size": 8 }, "DATA2": { "description": "DATA2", "offset": 16, "size": 8 }, "DATA1": { "description": "DATA1", "offset": 8, "size": 8 }, "DATA0": { "description": "DATA0", "offset": 0, "size": 8 } } } }, "TDH1R": { "description": "mailbox data high register", "offset": 412, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DATA7": { "description": "DATA7", "offset": 24, "size": 8 }, "DATA6": { "description": "DATA6", "offset": 16, "size": 8 }, "DATA5": { "description": "DATA5", "offset": 8, "size": 8 }, "DATA4": { "description": "DATA4", "offset": 0, "size": 8 } } } }, "TI2R": { "description": "TX mailbox identifier register", "offset": 416, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "STID": { "description": "STID", "offset": 21, "size": 11 }, "EXID": { "description": "EXID", "offset": 3, "size": 18 }, "IDE": { "description": "IDE", "offset": 2, "size": 1 }, "RTR": { "description": "RTR", "offset": 1, "size": 1 }, "TXRQ": { "description": "TXRQ", "offset": 0, "size": 1 } } } }, "TDT2R": { "description": "mailbox data length control and time stamp\n register", "offset": 420, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "TIME": { "description": "TIME", "offset": 16, "size": 16 }, "TGT": { "description": "TGT", "offset": 8, "size": 1 }, "DLC": { "description": "DLC", "offset": 0, "size": 4 } } } }, "TDL2R": { "description": "mailbox data low register", "offset": 424, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DATA3": { "description": "DATA3", "offset": 24, "size": 8 }, "DATA2": { "description": "DATA2", "offset": 16, "size": 8 }, "DATA1": { "description": "DATA1", "offset": 8, "size": 8 }, "DATA0": { "description": "DATA0", "offset": 0, "size": 8 } } } }, "TDH2R": { "description": "mailbox data high register", "offset": 428, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DATA7": { "description": "DATA7", "offset": 24, "size": 8 }, "DATA6": { "description": "DATA6", "offset": 16, "size": 8 }, "DATA5": { "description": "DATA5", "offset": 8, "size": 8 }, "DATA4": { "description": "DATA4", "offset": 0, "size": 8 } } } }, "RI0R": { "description": "receive FIFO mailbox identifier\n register", "offset": 432, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "STID": { "description": "STID", "offset": 21, "size": 11 }, "EXID": { "description": "EXID", "offset": 3, "size": 18 }, "IDE": { "description": "IDE", "offset": 2, "size": 1 }, "RTR": { "description": "RTR", "offset": 1, "size": 1 } } } }, "RDT0R": { "description": "receive FIFO mailbox data length control and\n time stamp register", "offset": 436, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "TIME": { "description": "TIME", "offset": 16, "size": 16 }, "FMI": { "description": "FMI", "offset": 8, "size": 8 }, "DLC": { "description": "DLC", "offset": 0, "size": 4 } } } }, "RDL0R": { "description": "receive FIFO mailbox data low\n register", "offset": 440, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "DATA3": { "description": "DATA3", "offset": 24, "size": 8 }, "DATA2": { "description": "DATA2", "offset": 16, "size": 8 }, "DATA1": { "description": "DATA1", "offset": 8, "size": 8 }, "DATA0": { "description": "DATA0", "offset": 0, "size": 8 } } } }, "RDH0R": { "description": "receive FIFO mailbox data high\n register", "offset": 444, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "DATA7": { "description": "DATA7", "offset": 24, "size": 8 }, "DATA6": { "description": "DATA6", "offset": 16, "size": 8 }, "DATA5": { "description": "DATA5", "offset": 8, "size": 8 }, "DATA4": { "description": "DATA4", "offset": 0, "size": 8 } } } }, "RI1R": { "description": "receive FIFO mailbox identifier\n register", "offset": 448, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "STID": { "description": "STID", "offset": 21, "size": 11 }, "EXID": { "description": "EXID", "offset": 3, "size": 18 }, "IDE": { "description": "IDE", "offset": 2, "size": 1 }, "RTR": { "description": "RTR", "offset": 1, "size": 1 } } } }, "RDT1R": { "description": "receive FIFO mailbox data length control and\n time stamp register", "offset": 452, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "TIME": { "description": "TIME", "offset": 16, "size": 16 }, "FMI": { "description": "FMI", "offset": 8, "size": 8 }, "DLC": { "description": "DLC", "offset": 0, "size": 4 } } } }, "RDL1R": { "description": "receive FIFO mailbox data low\n register", "offset": 456, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "DATA3": { "description": "DATA3", "offset": 24, "size": 8 }, "DATA2": { "description": "DATA2", "offset": 16, "size": 8 }, "DATA1": { "description": "DATA1", "offset": 8, "size": 8 }, "DATA0": { "description": "DATA0", "offset": 0, "size": 8 } } } }, "RDH1R": { "description": "receive FIFO mailbox data high\n register", "offset": 460, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "DATA7": { "description": "DATA7", "offset": 24, "size": 8 }, "DATA6": { "description": "DATA6", "offset": 16, "size": 8 }, "DATA5": { "description": "DATA5", "offset": 8, "size": 8 }, "DATA4": { "description": "DATA4", "offset": 0, "size": 8 } } } }, "FMR": { "description": "filter master register", "offset": 512, "size": 32, "reset_value": 706481665, "reset_mask": 4294967295, "children": { "fields": { "CAN2SB": { "description": "CAN2 start bank", "offset": 8, "size": 6 }, "FINIT": { "description": "Filter init mode", "offset": 0, "size": 1 } } } }, "FM1R": { "description": "filter mode register", "offset": 516, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FBM0": { "description": "Filter mode", "offset": 0, "size": 1 }, "FBM1": { "description": "Filter mode", "offset": 1, "size": 1 }, "FBM2": { "description": "Filter mode", "offset": 2, "size": 1 }, "FBM3": { "description": "Filter mode", "offset": 3, "size": 1 }, "FBM4": { "description": "Filter mode", "offset": 4, "size": 1 }, "FBM5": { "description": "Filter mode", "offset": 5, "size": 1 }, "FBM6": { "description": "Filter mode", "offset": 6, "size": 1 }, "FBM7": { "description": "Filter mode", "offset": 7, "size": 1 }, "FBM8": { "description": "Filter mode", "offset": 8, "size": 1 }, "FBM9": { "description": "Filter mode", "offset": 9, "size": 1 }, "FBM10": { "description": "Filter mode", "offset": 10, "size": 1 }, "FBM11": { "description": "Filter mode", "offset": 11, "size": 1 }, "FBM12": { "description": "Filter mode", "offset": 12, "size": 1 }, "FBM13": { "description": "Filter mode", "offset": 13, "size": 1 }, "FBM14": { "description": "Filter mode", "offset": 14, "size": 1 }, "FBM15": { "description": "Filter mode", "offset": 15, "size": 1 }, "FBM16": { "description": "Filter mode", "offset": 16, "size": 1 }, "FBM17": { "description": "Filter mode", "offset": 17, "size": 1 }, "FBM18": { "description": "Filter mode", "offset": 18, "size": 1 }, "FBM19": { "description": "Filter mode", "offset": 19, "size": 1 }, "FBM20": { "description": "Filter mode", "offset": 20, "size": 1 }, "FBM21": { "description": "Filter mode", "offset": 21, "size": 1 }, "FBM22": { "description": "Filter mode", "offset": 22, "size": 1 }, "FBM23": { "description": "Filter mode", "offset": 23, "size": 1 }, "FBM24": { "description": "Filter mode", "offset": 24, "size": 1 }, "FBM25": { "description": "Filter mode", "offset": 25, "size": 1 }, "FBM26": { "description": "Filter mode", "offset": 26, "size": 1 }, "FBM27": { "description": "Filter mode", "offset": 27, "size": 1 } } } }, "FS1R": { "description": "filter scale register", "offset": 524, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FSC0": { "description": "Filter scale configuration", "offset": 0, "size": 1 }, "FSC1": { "description": "Filter scale configuration", "offset": 1, "size": 1 }, "FSC2": { "description": "Filter scale configuration", "offset": 2, "size": 1 }, "FSC3": { "description": "Filter scale configuration", "offset": 3, "size": 1 }, "FSC4": { "description": "Filter scale configuration", "offset": 4, "size": 1 }, "FSC5": { "description": "Filter scale configuration", "offset": 5, "size": 1 }, "FSC6": { "description": "Filter scale configuration", "offset": 6, "size": 1 }, "FSC7": { "description": "Filter scale configuration", "offset": 7, "size": 1 }, "FSC8": { "description": "Filter scale configuration", "offset": 8, "size": 1 }, "FSC9": { "description": "Filter scale configuration", "offset": 9, "size": 1 }, "FSC10": { "description": "Filter scale configuration", "offset": 10, "size": 1 }, "FSC11": { "description": "Filter scale configuration", "offset": 11, "size": 1 }, "FSC12": { "description": "Filter scale configuration", "offset": 12, "size": 1 }, "FSC13": { "description": "Filter scale configuration", "offset": 13, "size": 1 }, "FSC14": { "description": "Filter scale configuration", "offset": 14, "size": 1 }, "FSC15": { "description": "Filter scale configuration", "offset": 15, "size": 1 }, "FSC16": { "description": "Filter scale configuration", "offset": 16, "size": 1 }, "FSC17": { "description": "Filter scale configuration", "offset": 17, "size": 1 }, "FSC18": { "description": "Filter scale configuration", "offset": 18, "size": 1 }, "FSC19": { "description": "Filter scale configuration", "offset": 19, "size": 1 }, "FSC20": { "description": "Filter scale configuration", "offset": 20, "size": 1 }, "FSC21": { "description": "Filter scale configuration", "offset": 21, "size": 1 }, "FSC22": { "description": "Filter scale configuration", "offset": 22, "size": 1 }, "FSC23": { "description": "Filter scale configuration", "offset": 23, "size": 1 }, "FSC24": { "description": "Filter scale configuration", "offset": 24, "size": 1 }, "FSC25": { "description": "Filter scale configuration", "offset": 25, "size": 1 }, "FSC26": { "description": "Filter scale configuration", "offset": 26, "size": 1 }, "FSC27": { "description": "Filter scale configuration", "offset": 27, "size": 1 } } } }, "FFA1R": { "description": "filter FIFO assignment\n register", "offset": 532, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FFA0": { "description": "Filter FIFO assignment for filter\n 0", "offset": 0, "size": 1 }, "FFA1": { "description": "Filter FIFO assignment for filter\n 1", "offset": 1, "size": 1 }, "FFA2": { "description": "Filter FIFO assignment for filter\n 2", "offset": 2, "size": 1 }, "FFA3": { "description": "Filter FIFO assignment for filter\n 3", "offset": 3, "size": 1 }, "FFA4": { "description": "Filter FIFO assignment for filter\n 4", "offset": 4, "size": 1 }, "FFA5": { "description": "Filter FIFO assignment for filter\n 5", "offset": 5, "size": 1 }, "FFA6": { "description": "Filter FIFO assignment for filter\n 6", "offset": 6, "size": 1 }, "FFA7": { "description": "Filter FIFO assignment for filter\n 7", "offset": 7, "size": 1 }, "FFA8": { "description": "Filter FIFO assignment for filter\n 8", "offset": 8, "size": 1 }, "FFA9": { "description": "Filter FIFO assignment for filter\n 9", "offset": 9, "size": 1 }, "FFA10": { "description": "Filter FIFO assignment for filter\n 10", "offset": 10, "size": 1 }, "FFA11": { "description": "Filter FIFO assignment for filter\n 11", "offset": 11, "size": 1 }, "FFA12": { "description": "Filter FIFO assignment for filter\n 12", "offset": 12, "size": 1 }, "FFA13": { "description": "Filter FIFO assignment for filter\n 13", "offset": 13, "size": 1 }, "FFA14": { "description": "Filter FIFO assignment for filter\n 14", "offset": 14, "size": 1 }, "FFA15": { "description": "Filter FIFO assignment for filter\n 15", "offset": 15, "size": 1 }, "FFA16": { "description": "Filter FIFO assignment for filter\n 16", "offset": 16, "size": 1 }, "FFA17": { "description": "Filter FIFO assignment for filter\n 17", "offset": 17, "size": 1 }, "FFA18": { "description": "Filter FIFO assignment for filter\n 18", "offset": 18, "size": 1 }, "FFA19": { "description": "Filter FIFO assignment for filter\n 19", "offset": 19, "size": 1 }, "FFA20": { "description": "Filter FIFO assignment for filter\n 20", "offset": 20, "size": 1 }, "FFA21": { "description": "Filter FIFO assignment for filter\n 21", "offset": 21, "size": 1 }, "FFA22": { "description": "Filter FIFO assignment for filter\n 22", "offset": 22, "size": 1 }, "FFA23": { "description": "Filter FIFO assignment for filter\n 23", "offset": 23, "size": 1 }, "FFA24": { "description": "Filter FIFO assignment for filter\n 24", "offset": 24, "size": 1 }, "FFA25": { "description": "Filter FIFO assignment for filter\n 25", "offset": 25, "size": 1 }, "FFA26": { "description": "Filter FIFO assignment for filter\n 26", "offset": 26, "size": 1 }, "FFA27": { "description": "Filter FIFO assignment for filter\n 27", "offset": 27, "size": 1 } } } }, "FA1R": { "description": "CAN filter activation register", "offset": 540, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FACT0": { "description": "Filter active", "offset": 0, "size": 1 }, "FACT1": { "description": "Filter active", "offset": 1, "size": 1 }, "FACT2": { "description": "Filter active", "offset": 2, "size": 1 }, "FACT3": { "description": "Filter active", "offset": 3, "size": 1 }, "FACT4": { "description": "Filter active", "offset": 4, "size": 1 }, "FACT5": { "description": "Filter active", "offset": 5, "size": 1 }, "FACT6": { "description": "Filter active", "offset": 6, "size": 1 }, "FACT7": { "description": "Filter active", "offset": 7, "size": 1 }, "FACT8": { "description": "Filter active", "offset": 8, "size": 1 }, "FACT9": { "description": "Filter active", "offset": 9, "size": 1 }, "FACT10": { "description": "Filter active", "offset": 10, "size": 1 }, "FACT11": { "description": "Filter active", "offset": 11, "size": 1 }, "FACT12": { "description": "Filter active", "offset": 12, "size": 1 }, "FACT13": { "description": "Filter active", "offset": 13, "size": 1 }, "FACT14": { "description": "Filter active", "offset": 14, "size": 1 }, "FACT15": { "description": "Filter active", "offset": 15, "size": 1 }, "FACT16": { "description": "Filter active", "offset": 16, "size": 1 }, "FACT17": { "description": "Filter active", "offset": 17, "size": 1 }, "FACT18": { "description": "Filter active", "offset": 18, "size": 1 }, "FACT19": { "description": "Filter active", "offset": 19, "size": 1 }, "FACT20": { "description": "Filter active", "offset": 20, "size": 1 }, "FACT21": { "description": "Filter active", "offset": 21, "size": 1 }, "FACT22": { "description": "Filter active", "offset": 22, "size": 1 }, "FACT23": { "description": "Filter active", "offset": 23, "size": 1 }, "FACT24": { "description": "Filter active", "offset": 24, "size": 1 }, "FACT25": { "description": "Filter active", "offset": 25, "size": 1 }, "FACT26": { "description": "Filter active", "offset": 26, "size": 1 }, "FACT27": { "description": "Filter active", "offset": 27, "size": 1 } } } }, "F0R1": { "description": "Filter bank 0 register 1", "offset": 576, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F0R2": { "description": "Filter bank 0 register 2", "offset": 580, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F1R1": { "description": "Filter bank 1 register 1", "offset": 584, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F1R2": { "description": "Filter bank 1 register 2", "offset": 588, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F2R1": { "description": "Filter bank 2 register 1", "offset": 592, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F2R2": { "description": "Filter bank 2 register 2", "offset": 596, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F3R1": { "description": "Filter bank 3 register 1", "offset": 600, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F3R2": { "description": "Filter bank 3 register 2", "offset": 604, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F4R1": { "description": "Filter bank 4 register 1", "offset": 608, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F4R2": { "description": "Filter bank 4 register 2", "offset": 612, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F5R1": { "description": "Filter bank 5 register 1", "offset": 616, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F5R2": { "description": "Filter bank 5 register 2", "offset": 620, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F6R1": { "description": "Filter bank 6 register 1", "offset": 624, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F6R2": { "description": "Filter bank 6 register 2", "offset": 628, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F7R1": { "description": "Filter bank 7 register 1", "offset": 632, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F7R2": { "description": "Filter bank 7 register 2", "offset": 636, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F8R1": { "description": "Filter bank 8 register 1", "offset": 640, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F8R2": { "description": "Filter bank 8 register 2", "offset": 644, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F9R1": { "description": "Filter bank 9 register 1", "offset": 648, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F9R2": { "description": "Filter bank 9 register 2", "offset": 652, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F10R1": { "description": "Filter bank 10 register 1", "offset": 656, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F10R2": { "description": "Filter bank 10 register 2", "offset": 660, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F11R1": { "description": "Filter bank 11 register 1", "offset": 664, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F11R2": { "description": "Filter bank 11 register 2", "offset": 668, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F12R1": { "description": "Filter bank 4 register 1", "offset": 672, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F12R2": { "description": "Filter bank 12 register 2", "offset": 676, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F13R1": { "description": "Filter bank 13 register 1", "offset": 680, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F13R2": { "description": "Filter bank 13 register 2", "offset": 684, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F14R1": { "description": "Filter bank 14 register 1", "offset": 688, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F14R2": { "description": "Filter bank 14 register 2", "offset": 692, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F15R1": { "description": "Filter bank 15 register 1", "offset": 696, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F15R2": { "description": "Filter bank 15 register 2", "offset": 700, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F16R1": { "description": "Filter bank 16 register 1", "offset": 704, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F16R2": { "description": "Filter bank 16 register 2", "offset": 708, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F17R1": { "description": "Filter bank 17 register 1", "offset": 712, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F17R2": { "description": "Filter bank 17 register 2", "offset": 716, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F18R1": { "description": "Filter bank 18 register 1", "offset": 720, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F18R2": { "description": "Filter bank 18 register 2", "offset": 724, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F19R1": { "description": "Filter bank 19 register 1", "offset": 728, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F19R2": { "description": "Filter bank 19 register 2", "offset": 732, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F20R1": { "description": "Filter bank 20 register 1", "offset": 736, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F20R2": { "description": "Filter bank 20 register 2", "offset": 740, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F21R1": { "description": "Filter bank 21 register 1", "offset": 744, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F21R2": { "description": "Filter bank 21 register 2", "offset": 748, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F22R1": { "description": "Filter bank 22 register 1", "offset": 752, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F22R2": { "description": "Filter bank 22 register 2", "offset": 756, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F23R1": { "description": "Filter bank 23 register 1", "offset": 760, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F23R2": { "description": "Filter bank 23 register 2", "offset": 764, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F24R1": { "description": "Filter bank 24 register 1", "offset": 768, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F24R2": { "description": "Filter bank 24 register 2", "offset": 772, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F25R1": { "description": "Filter bank 25 register 1", "offset": 776, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F25R2": { "description": "Filter bank 25 register 2", "offset": 780, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F26R1": { "description": "Filter bank 26 register 1", "offset": 784, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F26R2": { "description": "Filter bank 26 register 2", "offset": 788, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F27R1": { "description": "Filter bank 27 register 1", "offset": 792, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } }, "F27R2": { "description": "Filter bank 27 register 2", "offset": 796, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "FB0": { "description": "Filter bits", "offset": 0, "size": 1 }, "FB1": { "description": "Filter bits", "offset": 1, "size": 1 }, "FB2": { "description": "Filter bits", "offset": 2, "size": 1 }, "FB3": { "description": "Filter bits", "offset": 3, "size": 1 }, "FB4": { "description": "Filter bits", "offset": 4, "size": 1 }, "FB5": { "description": "Filter bits", "offset": 5, "size": 1 }, "FB6": { "description": "Filter bits", "offset": 6, "size": 1 }, "FB7": { "description": "Filter bits", "offset": 7, "size": 1 }, "FB8": { "description": "Filter bits", "offset": 8, "size": 1 }, "FB9": { "description": "Filter bits", "offset": 9, "size": 1 }, "FB10": { "description": "Filter bits", "offset": 10, "size": 1 }, "FB11": { "description": "Filter bits", "offset": 11, "size": 1 }, "FB12": { "description": "Filter bits", "offset": 12, "size": 1 }, "FB13": { "description": "Filter bits", "offset": 13, "size": 1 }, "FB14": { "description": "Filter bits", "offset": 14, "size": 1 }, "FB15": { "description": "Filter bits", "offset": 15, "size": 1 }, "FB16": { "description": "Filter bits", "offset": 16, "size": 1 }, "FB17": { "description": "Filter bits", "offset": 17, "size": 1 }, "FB18": { "description": "Filter bits", "offset": 18, "size": 1 }, "FB19": { "description": "Filter bits", "offset": 19, "size": 1 }, "FB20": { "description": "Filter bits", "offset": 20, "size": 1 }, "FB21": { "description": "Filter bits", "offset": 21, "size": 1 }, "FB22": { "description": "Filter bits", "offset": 22, "size": 1 }, "FB23": { "description": "Filter bits", "offset": 23, "size": 1 }, "FB24": { "description": "Filter bits", "offset": 24, "size": 1 }, "FB25": { "description": "Filter bits", "offset": 25, "size": 1 }, "FB26": { "description": "Filter bits", "offset": 26, "size": 1 }, "FB27": { "description": "Filter bits", "offset": 27, "size": 1 }, "FB28": { "description": "Filter bits", "offset": 28, "size": 1 }, "FB29": { "description": "Filter bits", "offset": 29, "size": 1 }, "FB30": { "description": "Filter bits", "offset": 30, "size": 1 }, "FB31": { "description": "Filter bits", "offset": 31, "size": 1 } } } } } } }, "USB_FS": { "description": "Universal serial bus full-speed device\n interface", "children": { "registers": { "USB_EP0R": { "description": "endpoint 0 register", "offset": 0, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "EA": { "description": "Endpoint address", "offset": 0, "size": 4 }, "STAT_TX": { "description": "Status bits, for transmission\n transfers", "offset": 4, "size": 2 }, "DTOG_TX": { "description": "Data Toggle, for transmission\n transfers", "offset": 6, "size": 1 }, "CTR_TX": { "description": "Correct Transfer for\n transmission", "offset": 7, "size": 1 }, "EP_KIND": { "description": "Endpoint kind", "offset": 8, "size": 1 }, "EP_TYPE": { "description": "Endpoint type", "offset": 9, "size": 2 }, "SETUP": { "description": "Setup transaction\n completed", "offset": 11, "size": 1, "access": "read-only" }, "STAT_RX": { "description": "Status bits, for reception\n transfers", "offset": 12, "size": 2 }, "DTOG_RX": { "description": "Data Toggle, for reception\n transfers", "offset": 14, "size": 1 }, "CTR_RX": { "description": "Correct transfer for\n reception", "offset": 15, "size": 1 } } } }, "USB_EP1R": { "description": "endpoint 1 register", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "EA": { "description": "Endpoint address", "offset": 0, "size": 4 }, "STAT_TX": { "description": "Status bits, for transmission\n transfers", "offset": 4, "size": 2 }, "DTOG_TX": { "description": "Data Toggle, for transmission\n transfers", "offset": 6, "size": 1 }, "CTR_TX": { "description": "Correct Transfer for\n transmission", "offset": 7, "size": 1 }, "EP_KIND": { "description": "Endpoint kind", "offset": 8, "size": 1 }, "EP_TYPE": { "description": "Endpoint type", "offset": 9, "size": 2 }, "SETUP": { "description": "Setup transaction\n completed", "offset": 11, "size": 1, "access": "read-only" }, "STAT_RX": { "description": "Status bits, for reception\n transfers", "offset": 12, "size": 2 }, "DTOG_RX": { "description": "Data Toggle, for reception\n transfers", "offset": 14, "size": 1 }, "CTR_RX": { "description": "Correct transfer for\n reception", "offset": 15, "size": 1 } } } }, "USB_EP2R": { "description": "endpoint 2 register", "offset": 8, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "EA": { "description": "Endpoint address", "offset": 0, "size": 4 }, "STAT_TX": { "description": "Status bits, for transmission\n transfers", "offset": 4, "size": 2 }, "DTOG_TX": { "description": "Data Toggle, for transmission\n transfers", "offset": 6, "size": 1 }, "CTR_TX": { "description": "Correct Transfer for\n transmission", "offset": 7, "size": 1 }, "EP_KIND": { "description": "Endpoint kind", "offset": 8, "size": 1 }, "EP_TYPE": { "description": "Endpoint type", "offset": 9, "size": 2 }, "SETUP": { "description": "Setup transaction\n completed", "offset": 11, "size": 1, "access": "read-only" }, "STAT_RX": { "description": "Status bits, for reception\n transfers", "offset": 12, "size": 2 }, "DTOG_RX": { "description": "Data Toggle, for reception\n transfers", "offset": 14, "size": 1 }, "CTR_RX": { "description": "Correct transfer for\n reception", "offset": 15, "size": 1 } } } }, "USB_EP3R": { "description": "endpoint 3 register", "offset": 12, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "EA": { "description": "Endpoint address", "offset": 0, "size": 4 }, "STAT_TX": { "description": "Status bits, for transmission\n transfers", "offset": 4, "size": 2 }, "DTOG_TX": { "description": "Data Toggle, for transmission\n transfers", "offset": 6, "size": 1 }, "CTR_TX": { "description": "Correct Transfer for\n transmission", "offset": 7, "size": 1 }, "EP_KIND": { "description": "Endpoint kind", "offset": 8, "size": 1 }, "EP_TYPE": { "description": "Endpoint type", "offset": 9, "size": 2 }, "SETUP": { "description": "Setup transaction\n completed", "offset": 11, "size": 1, "access": "read-only" }, "STAT_RX": { "description": "Status bits, for reception\n transfers", "offset": 12, "size": 2 }, "DTOG_RX": { "description": "Data Toggle, for reception\n transfers", "offset": 14, "size": 1 }, "CTR_RX": { "description": "Correct transfer for\n reception", "offset": 15, "size": 1 } } } }, "USB_EP4R": { "description": "endpoint 4 register", "offset": 16, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "EA": { "description": "Endpoint address", "offset": 0, "size": 4 }, "STAT_TX": { "description": "Status bits, for transmission\n transfers", "offset": 4, "size": 2 }, "DTOG_TX": { "description": "Data Toggle, for transmission\n transfers", "offset": 6, "size": 1 }, "CTR_TX": { "description": "Correct Transfer for\n transmission", "offset": 7, "size": 1 }, "EP_KIND": { "description": "Endpoint kind", "offset": 8, "size": 1 }, "EP_TYPE": { "description": "Endpoint type", "offset": 9, "size": 2 }, "SETUP": { "description": "Setup transaction\n completed", "offset": 11, "size": 1, "access": "read-only" }, "STAT_RX": { "description": "Status bits, for reception\n transfers", "offset": 12, "size": 2 }, "DTOG_RX": { "description": "Data Toggle, for reception\n transfers", "offset": 14, "size": 1 }, "CTR_RX": { "description": "Correct transfer for\n reception", "offset": 15, "size": 1 } } } }, "USB_EP5R": { "description": "endpoint 5 register", "offset": 20, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "EA": { "description": "Endpoint address", "offset": 0, "size": 4 }, "STAT_TX": { "description": "Status bits, for transmission\n transfers", "offset": 4, "size": 2 }, "DTOG_TX": { "description": "Data Toggle, for transmission\n transfers", "offset": 6, "size": 1 }, "CTR_TX": { "description": "Correct Transfer for\n transmission", "offset": 7, "size": 1 }, "EP_KIND": { "description": "Endpoint kind", "offset": 8, "size": 1 }, "EP_TYPE": { "description": "Endpoint type", "offset": 9, "size": 2 }, "SETUP": { "description": "Setup transaction\n completed", "offset": 11, "size": 1, "access": "read-only" }, "STAT_RX": { "description": "Status bits, for reception\n transfers", "offset": 12, "size": 2 }, "DTOG_RX": { "description": "Data Toggle, for reception\n transfers", "offset": 14, "size": 1 }, "CTR_RX": { "description": "Correct transfer for\n reception", "offset": 15, "size": 1 } } } }, "USB_EP6R": { "description": "endpoint 6 register", "offset": 24, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "EA": { "description": "Endpoint address", "offset": 0, "size": 4 }, "STAT_TX": { "description": "Status bits, for transmission\n transfers", "offset": 4, "size": 2 }, "DTOG_TX": { "description": "Data Toggle, for transmission\n transfers", "offset": 6, "size": 1 }, "CTR_TX": { "description": "Correct Transfer for\n transmission", "offset": 7, "size": 1 }, "EP_KIND": { "description": "Endpoint kind", "offset": 8, "size": 1 }, "EP_TYPE": { "description": "Endpoint type", "offset": 9, "size": 2 }, "SETUP": { "description": "Setup transaction\n completed", "offset": 11, "size": 1, "access": "read-only" }, "STAT_RX": { "description": "Status bits, for reception\n transfers", "offset": 12, "size": 2 }, "DTOG_RX": { "description": "Data Toggle, for reception\n transfers", "offset": 14, "size": 1 }, "CTR_RX": { "description": "Correct transfer for\n reception", "offset": 15, "size": 1 } } } }, "USB_EP7R": { "description": "endpoint 7 register", "offset": 28, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "EA": { "description": "Endpoint address", "offset": 0, "size": 4 }, "STAT_TX": { "description": "Status bits, for transmission\n transfers", "offset": 4, "size": 2 }, "DTOG_TX": { "description": "Data Toggle, for transmission\n transfers", "offset": 6, "size": 1 }, "CTR_TX": { "description": "Correct Transfer for\n transmission", "offset": 7, "size": 1 }, "EP_KIND": { "description": "Endpoint kind", "offset": 8, "size": 1 }, "EP_TYPE": { "description": "Endpoint type", "offset": 9, "size": 2 }, "SETUP": { "description": "Setup transaction\n completed", "offset": 11, "size": 1, "access": "read-only" }, "STAT_RX": { "description": "Status bits, for reception\n transfers", "offset": 12, "size": 2 }, "DTOG_RX": { "description": "Data Toggle, for reception\n transfers", "offset": 14, "size": 1 }, "CTR_RX": { "description": "Correct transfer for\n reception", "offset": 15, "size": 1 } } } }, "USB_CNTR": { "description": "control register", "offset": 64, "size": 32, "reset_value": 3, "reset_mask": 4294967295, "children": { "fields": { "FRES": { "description": "Force USB Reset", "offset": 0, "size": 1 }, "PDWN": { "description": "Power down", "offset": 1, "size": 1 }, "LPMODE": { "description": "Low-power mode", "offset": 2, "size": 1 }, "FSUSP": { "description": "Force suspend", "offset": 3, "size": 1 }, "RESUME": { "description": "Resume request", "offset": 4, "size": 1 }, "ESOFM": { "description": "Expected start of frame interrupt\n mask", "offset": 8, "size": 1 }, "SOFM": { "description": "Start of frame interrupt\n mask", "offset": 9, "size": 1 }, "RESETM": { "description": "USB reset interrupt mask", "offset": 10, "size": 1 }, "SUSPM": { "description": "Suspend mode interrupt\n mask", "offset": 11, "size": 1 }, "WKUPM": { "description": "Wakeup interrupt mask", "offset": 12, "size": 1 }, "ERRM": { "description": "Error interrupt mask", "offset": 13, "size": 1 }, "PMAOVRM": { "description": "Packet memory area over / underrun\n interrupt mask", "offset": 14, "size": 1 }, "CTRM": { "description": "Correct transfer interrupt\n mask", "offset": 15, "size": 1 } } } }, "ISTR": { "description": "interrupt status register", "offset": 68, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "EP_ID": { "description": "Endpoint Identifier", "offset": 0, "size": 4, "access": "read-only" }, "DIR": { "description": "Direction of transaction", "offset": 4, "size": 1, "access": "read-only" }, "ESOF": { "description": "Expected start frame", "offset": 8, "size": 1 }, "SOF": { "description": "start of frame", "offset": 9, "size": 1 }, "RESET": { "description": "reset request", "offset": 10, "size": 1 }, "SUSP": { "description": "Suspend mode request", "offset": 11, "size": 1 }, "WKUP": { "description": "Wakeup", "offset": 12, "size": 1 }, "ERR": { "description": "Error", "offset": 13, "size": 1 }, "PMAOVR": { "description": "Packet memory area over /\n underrun", "offset": 14, "size": 1 }, "CTR": { "description": "Correct transfer", "offset": 15, "size": 1, "access": "read-only" } } } }, "FNR": { "description": "frame number register", "offset": 72, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "FN": { "description": "Frame number", "offset": 0, "size": 11 }, "LSOF": { "description": "Lost SOF", "offset": 11, "size": 2 }, "LCK": { "description": "Locked", "offset": 13, "size": 1 }, "RXDM": { "description": "Receive data - line status", "offset": 14, "size": 1 }, "RXDP": { "description": "Receive data + line status", "offset": 15, "size": 1 } } } }, "DADDR": { "description": "device address", "offset": 76, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "ADD": { "description": "Device address", "offset": 0, "size": 1 }, "ADD1": { "description": "Device address", "offset": 1, "size": 1 }, "ADD2": { "description": "Device address", "offset": 2, "size": 1 }, "ADD3": { "description": "Device address", "offset": 3, "size": 1 }, "ADD4": { "description": "Device address", "offset": 4, "size": 1 }, "ADD5": { "description": "Device address", "offset": 5, "size": 1 }, "ADD6": { "description": "Device address", "offset": 6, "size": 1 }, "EF": { "description": "Enable function", "offset": 7, "size": 1 } } } }, "BTABLE": { "description": "Buffer table address", "offset": 80, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "BTABLE": { "description": "Buffer table", "offset": 3, "size": 13 } } } } } } }, "I2C1": { "description": "Inter-integrated circuit", "children": { "registers": { "CR1": { "description": "Control register 1", "offset": 0, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "PE": { "description": "Peripheral enable", "offset": 0, "size": 1 }, "TXIE": { "description": "TX Interrupt enable", "offset": 1, "size": 1 }, "RXIE": { "description": "RX Interrupt enable", "offset": 2, "size": 1 }, "ADDRIE": { "description": "Address match interrupt enable (slave\n only)", "offset": 3, "size": 1 }, "NACKIE": { "description": "Not acknowledge received interrupt\n enable", "offset": 4, "size": 1 }, "STOPIE": { "description": "STOP detection Interrupt\n enable", "offset": 5, "size": 1 }, "TCIE": { "description": "Transfer Complete interrupt\n enable", "offset": 6, "size": 1 }, "ERRIE": { "description": "Error interrupts enable", "offset": 7, "size": 1 }, "DNF": { "description": "Digital noise filter", "offset": 8, "size": 4 }, "ANFOFF": { "description": "Analog noise filter OFF", "offset": 12, "size": 1 }, "SWRST": { "description": "Software reset", "offset": 13, "size": 1, "access": "write-only" }, "TXDMAEN": { "description": "DMA transmission requests\n enable", "offset": 14, "size": 1 }, "RXDMAEN": { "description": "DMA reception requests\n enable", "offset": 15, "size": 1 }, "SBC": { "description": "Slave byte control", "offset": 16, "size": 1 }, "NOSTRETCH": { "description": "Clock stretching disable", "offset": 17, "size": 1 }, "WUPEN": { "description": "Wakeup from STOP enable", "offset": 18, "size": 1 }, "GCEN": { "description": "General call enable", "offset": 19, "size": 1 }, "SMBHEN": { "description": "SMBus Host address enable", "offset": 20, "size": 1 }, "SMBDEN": { "description": "SMBus Device Default address\n enable", "offset": 21, "size": 1 }, "ALERTEN": { "description": "SMBUS alert enable", "offset": 22, "size": 1 }, "PECEN": { "description": "PEC enable", "offset": 23, "size": 1 } } } }, "CR2": { "description": "Control register 2", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "PECBYTE": { "description": "Packet error checking byte", "offset": 26, "size": 1 }, "AUTOEND": { "description": "Automatic end mode (master\n mode)", "offset": 25, "size": 1 }, "RELOAD": { "description": "NBYTES reload mode", "offset": 24, "size": 1 }, "NBYTES": { "description": "Number of bytes", "offset": 16, "size": 8 }, "NACK": { "description": "NACK generation (slave\n mode)", "offset": 15, "size": 1 }, "STOP": { "description": "Stop generation (master\n mode)", "offset": 14, "size": 1 }, "START": { "description": "Start generation", "offset": 13, "size": 1 }, "HEAD10R": { "description": "10-bit address header only read\n direction (master receiver mode)", "offset": 12, "size": 1 }, "ADD10": { "description": "10-bit addressing mode (master\n mode)", "offset": 11, "size": 1 }, "RD_WRN": { "description": "Transfer direction (master\n mode)", "offset": 10, "size": 1 }, "SADD8": { "description": "Slave address bit 9:8 (master\n mode)", "offset": 8, "size": 2 }, "SADD1": { "description": "Slave address bit 7:1 (master\n mode)", "offset": 1, "size": 7 }, "SADD0": { "description": "Slave address bit 0 (master\n mode)", "offset": 0, "size": 1 } } } }, "OAR1": { "description": "Own address register 1", "offset": 8, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "OA1_0": { "description": "Interface address", "offset": 0, "size": 1 }, "OA1_1": { "description": "Interface address", "offset": 1, "size": 7 }, "OA1_8": { "description": "Interface address", "offset": 8, "size": 2 }, "OA1MODE": { "description": "Own Address 1 10-bit mode", "offset": 10, "size": 1 }, "OA1EN": { "description": "Own Address 1 enable", "offset": 15, "size": 1 } } } }, "OAR2": { "description": "Own address register 2", "offset": 12, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "OA2": { "description": "Interface address", "offset": 1, "size": 7 }, "OA2MSK": { "description": "Own Address 2 masks", "offset": 8, "size": 3 }, "OA2EN": { "description": "Own Address 2 enable", "offset": 15, "size": 1 } } } }, "TIMINGR": { "description": "Timing register", "offset": 16, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "SCLL": { "description": "SCL low period (master\n mode)", "offset": 0, "size": 8 }, "SCLH": { "description": "SCL high period (master\n mode)", "offset": 8, "size": 8 }, "SDADEL": { "description": "Data hold time", "offset": 16, "size": 4 }, "SCLDEL": { "description": "Data setup time", "offset": 20, "size": 4 }, "PRESC": { "description": "Timing prescaler", "offset": 28, "size": 4 } } } }, "TIMEOUTR": { "description": "Status register 1", "offset": 20, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "TIMEOUTA": { "description": "Bus timeout A", "offset": 0, "size": 12 }, "TIDLE": { "description": "Idle clock timeout\n detection", "offset": 12, "size": 1 }, "TIMOUTEN": { "description": "Clock timeout enable", "offset": 15, "size": 1 }, "TIMEOUTB": { "description": "Bus timeout B", "offset": 16, "size": 12 }, "TEXTEN": { "description": "Extended clock timeout\n enable", "offset": 31, "size": 1 } } } }, "ISR": { "description": "Interrupt and Status register", "offset": 24, "size": 32, "reset_value": 1, "reset_mask": 4294967295, "children": { "fields": { "ADDCODE": { "description": "Address match code (Slave\n mode)", "offset": 17, "size": 7, "access": "read-only" }, "DIR": { "description": "Transfer direction (Slave\n mode)", "offset": 16, "size": 1, "access": "read-only" }, "BUSY": { "description": "Bus busy", "offset": 15, "size": 1, "access": "read-only" }, "ALERT": { "description": "SMBus alert", "offset": 13, "size": 1, "access": "read-only" }, "TIMEOUT": { "description": "Timeout or t_low detection\n flag", "offset": 12, "size": 1, "access": "read-only" }, "PECERR": { "description": "PEC Error in reception", "offset": 11, "size": 1, "access": "read-only" }, "OVR": { "description": "Overrun/Underrun (slave\n mode)", "offset": 10, "size": 1, "access": "read-only" }, "ARLO": { "description": "Arbitration lost", "offset": 9, "size": 1, "access": "read-only" }, "BERR": { "description": "Bus error", "offset": 8, "size": 1, "access": "read-only" }, "TCR": { "description": "Transfer Complete Reload", "offset": 7, "size": 1, "access": "read-only" }, "TC": { "description": "Transfer Complete (master\n mode)", "offset": 6, "size": 1, "access": "read-only" }, "STOPF": { "description": "Stop detection flag", "offset": 5, "size": 1, "access": "read-only" }, "NACKF": { "description": "Not acknowledge received\n flag", "offset": 4, "size": 1, "access": "read-only" }, "ADDR": { "description": "Address matched (slave\n mode)", "offset": 3, "size": 1, "access": "read-only" }, "RXNE": { "description": "Receive data register not empty\n (receivers)", "offset": 2, "size": 1, "access": "read-only" }, "TXIS": { "description": "Transmit interrupt status\n (transmitters)", "offset": 1, "size": 1 }, "TXE": { "description": "Transmit data register empty\n (transmitters)", "offset": 0, "size": 1 } } } }, "ICR": { "description": "Interrupt clear register", "offset": 28, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "write-only", "children": { "fields": { "ALERTCF": { "description": "Alert flag clear", "offset": 13, "size": 1 }, "TIMOUTCF": { "description": "Timeout detection flag\n clear", "offset": 12, "size": 1 }, "PECCF": { "description": "PEC Error flag clear", "offset": 11, "size": 1 }, "OVRCF": { "description": "Overrun/Underrun flag\n clear", "offset": 10, "size": 1 }, "ARLOCF": { "description": "Arbitration lost flag\n clear", "offset": 9, "size": 1 }, "BERRCF": { "description": "Bus error flag clear", "offset": 8, "size": 1 }, "STOPCF": { "description": "Stop detection flag clear", "offset": 5, "size": 1 }, "NACKCF": { "description": "Not Acknowledge flag clear", "offset": 4, "size": 1 }, "ADDRCF": { "description": "Address Matched flag clear", "offset": 3, "size": 1 } } } }, "PECR": { "description": "PEC register", "offset": 32, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "PEC": { "description": "Packet error checking\n register", "offset": 0, "size": 8 } } } }, "RXDR": { "description": "Receive data register", "offset": 36, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "RXDATA": { "description": "8-bit receive data", "offset": 0, "size": 8 } } } }, "TXDR": { "description": "Transmit data register", "offset": 40, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "TXDATA": { "description": "8-bit transmit data", "offset": 0, "size": 8 } } } } } } }, "TIM1": { "description": "Advanced timer", "children": { "registers": { "CR1": { "description": "control register 1", "offset": 0, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CEN": { "description": "Counter enable", "offset": 0, "size": 1 }, "UDIS": { "description": "Update disable", "offset": 1, "size": 1 }, "URS": { "description": "Update request source", "offset": 2, "size": 1 }, "OPM": { "description": "One-pulse mode", "offset": 3, "size": 1 }, "DIR": { "description": "Direction", "offset": 4, "size": 1 }, "CMS": { "description": "Center-aligned mode\n selection", "offset": 5, "size": 2 }, "ARPE": { "description": "Auto-reload preload enable", "offset": 7, "size": 1 }, "CKD": { "description": "Clock division", "offset": 8, "size": 2 }, "UIFREMAP": { "description": "UIF status bit remapping", "offset": 11, "size": 1 } } } }, "CR2": { "description": "control register 2", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CCPC": { "description": "Capture/compare preloaded\n control", "offset": 0, "size": 1 }, "CCUS": { "description": "Capture/compare control update\n selection", "offset": 2, "size": 1 }, "CCDS": { "description": "Capture/compare DMA\n selection", "offset": 3, "size": 1 }, "MMS": { "description": "Master mode selection", "offset": 4, "size": 3 }, "TI1S": { "description": "TI1 selection", "offset": 7, "size": 1 }, "OIS1": { "description": "Output Idle state 1", "offset": 8, "size": 1 }, "OIS1N": { "description": "Output Idle state 1", "offset": 9, "size": 1 }, "OIS2": { "description": "Output Idle state 2", "offset": 10, "size": 1 }, "OIS2N": { "description": "Output Idle state 2", "offset": 11, "size": 1 }, "OIS3": { "description": "Output Idle state 3", "offset": 12, "size": 1 }, "OIS3N": { "description": "Output Idle state 3", "offset": 13, "size": 1 }, "OIS4": { "description": "Output Idle state 4", "offset": 14, "size": 1 }, "OIS5": { "description": "Output Idle state 5", "offset": 16, "size": 1 }, "OIS6": { "description": "Output Idle state 6", "offset": 18, "size": 1 }, "MMS2": { "description": "Master mode selection 2", "offset": 20, "size": 4 } } } }, "SMCR": { "description": "slave mode control register", "offset": 8, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "SMS": { "description": "Slave mode selection", "offset": 0, "size": 3 }, "OCCS": { "description": "OCREF clear selection", "offset": 3, "size": 1 }, "TS": { "description": "Trigger selection", "offset": 4, "size": 3 }, "MSM": { "description": "Master/Slave mode", "offset": 7, "size": 1 }, "ETF": { "description": "External trigger filter", "offset": 8, "size": 4 }, "ETPS": { "description": "External trigger prescaler", "offset": 12, "size": 2 }, "ECE": { "description": "External clock enable", "offset": 14, "size": 1 }, "ETP": { "description": "External trigger polarity", "offset": 15, "size": 1 }, "SMS3": { "description": "Slave mode selection bit 3", "offset": 16, "size": 1 } } } }, "DIER": { "description": "DMA/Interrupt enable register", "offset": 12, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "TDE": { "description": "Trigger DMA request enable", "offset": 14, "size": 1 }, "COMDE": { "description": "COM DMA request enable", "offset": 13, "size": 1 }, "CC4DE": { "description": "Capture/Compare 4 DMA request\n enable", "offset": 12, "size": 1 }, "CC3DE": { "description": "Capture/Compare 3 DMA request\n enable", "offset": 11, "size": 1 }, "CC2DE": { "description": "Capture/Compare 2 DMA request\n enable", "offset": 10, "size": 1 }, "CC1DE": { "description": "Capture/Compare 1 DMA request\n enable", "offset": 9, "size": 1 }, "UDE": { "description": "Update DMA request enable", "offset": 8, "size": 1 }, "BIE": { "description": "Break interrupt enable", "offset": 7, "size": 1 }, "TIE": { "description": "Trigger interrupt enable", "offset": 6, "size": 1 }, "COMIE": { "description": "COM interrupt enable", "offset": 5, "size": 1 }, "CC4IE": { "description": "Capture/Compare 4 interrupt\n enable", "offset": 4, "size": 1 }, "CC3IE": { "description": "Capture/Compare 3 interrupt\n enable", "offset": 3, "size": 1 }, "CC2IE": { "description": "Capture/Compare 2 interrupt\n enable", "offset": 2, "size": 1 }, "CC1IE": { "description": "Capture/Compare 1 interrupt\n enable", "offset": 1, "size": 1 }, "UIE": { "description": "Update interrupt enable", "offset": 0, "size": 1 } } } }, "SR": { "description": "status register", "offset": 16, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "UIF": { "description": "Update interrupt flag", "offset": 0, "size": 1 }, "CC1IF": { "description": "Capture/compare 1 interrupt\n flag", "offset": 1, "size": 1 }, "CC2IF": { "description": "Capture/Compare 2 interrupt\n flag", "offset": 2, "size": 1 }, "CC3IF": { "description": "Capture/Compare 3 interrupt\n flag", "offset": 3, "size": 1 }, "CC4IF": { "description": "Capture/Compare 4 interrupt\n flag", "offset": 4, "size": 1 }, "COMIF": { "description": "COM interrupt flag", "offset": 5, "size": 1 }, "TIF": { "description": "Trigger interrupt flag", "offset": 6, "size": 1 }, "BIF": { "description": "Break interrupt flag", "offset": 7, "size": 1 }, "B2IF": { "description": "Break 2 interrupt flag", "offset": 8, "size": 1 }, "CC1OF": { "description": "Capture/Compare 1 overcapture\n flag", "offset": 9, "size": 1 }, "CC2OF": { "description": "Capture/compare 2 overcapture\n flag", "offset": 10, "size": 1 }, "CC3OF": { "description": "Capture/Compare 3 overcapture\n flag", "offset": 11, "size": 1 }, "CC4OF": { "description": "Capture/Compare 4 overcapture\n flag", "offset": 12, "size": 1 }, "C5IF": { "description": "Capture/Compare 5 interrupt\n flag", "offset": 16, "size": 1 }, "C6IF": { "description": "Capture/Compare 6 interrupt\n flag", "offset": 17, "size": 1 } } } }, "EGR": { "description": "event generation register", "offset": 20, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "write-only", "children": { "fields": { "UG": { "description": "Update generation", "offset": 0, "size": 1 }, "CC1G": { "description": "Capture/compare 1\n generation", "offset": 1, "size": 1 }, "CC2G": { "description": "Capture/compare 2\n generation", "offset": 2, "size": 1 }, "CC3G": { "description": "Capture/compare 3\n generation", "offset": 3, "size": 1 }, "CC4G": { "description": "Capture/compare 4\n generation", "offset": 4, "size": 1 }, "COMG": { "description": "Capture/Compare control update\n generation", "offset": 5, "size": 1 }, "TG": { "description": "Trigger generation", "offset": 6, "size": 1 }, "BG": { "description": "Break generation", "offset": 7, "size": 1 }, "B2G": { "description": "Break 2 generation", "offset": 8, "size": 1 } } } }, "CCMR1_Output": { "description": "capture/compare mode register (output\n mode)", "offset": 24, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "OC2CE": { "description": "Output Compare 2 clear\n enable", "offset": 15, "size": 1 }, "OC2M": { "description": "Output Compare 2 mode", "offset": 12, "size": 3 }, "OC2PE": { "description": "Output Compare 2 preload\n enable", "offset": 11, "size": 1 }, "OC2FE": { "description": "Output Compare 2 fast\n enable", "offset": 10, "size": 1 }, "CC2S": { "description": "Capture/Compare 2\n selection", "offset": 8, "size": 2 }, "OC1CE": { "description": "Output Compare 1 clear\n enable", "offset": 7, "size": 1 }, "OC1M": { "description": "Output Compare 1 mode", "offset": 4, "size": 3 }, "OC1PE": { "description": "Output Compare 1 preload\n enable", "offset": 3, "size": 1 }, "OC1FE": { "description": "Output Compare 1 fast\n enable", "offset": 2, "size": 1 }, "CC1S": { "description": "Capture/Compare 1\n selection", "offset": 0, "size": 2 }, "OC1M_3": { "description": "Output Compare 1 mode bit\n 3", "offset": 16, "size": 1 }, "OC2M_3": { "description": "Output Compare 2 mode bit\n 3", "offset": 24, "size": 1 } } } }, "CCMR1_Input": { "description": "capture/compare mode register 1 (input\n mode)", "offset": 24, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IC2F": { "description": "Input capture 2 filter", "offset": 12, "size": 4 }, "IC2PCS": { "description": "Input capture 2 prescaler", "offset": 10, "size": 2 }, "CC2S": { "description": "Capture/Compare 2\n selection", "offset": 8, "size": 2 }, "IC1F": { "description": "Input capture 1 filter", "offset": 4, "size": 4 }, "IC1PCS": { "description": "Input capture 1 prescaler", "offset": 2, "size": 2 }, "CC1S": { "description": "Capture/Compare 1\n selection", "offset": 0, "size": 2 } } } }, "CCMR2_Output": { "description": "capture/compare mode register (output\n mode)", "offset": 28, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "OC4CE": { "description": "Output compare 4 clear\n enable", "offset": 15, "size": 1 }, "OC4M": { "description": "Output compare 4 mode", "offset": 12, "size": 3 }, "OC4PE": { "description": "Output compare 4 preload\n enable", "offset": 11, "size": 1 }, "OC4FE": { "description": "Output compare 4 fast\n enable", "offset": 10, "size": 1 }, "CC4S": { "description": "Capture/Compare 4\n selection", "offset": 8, "size": 2 }, "OC3CE": { "description": "Output compare 3 clear\n enable", "offset": 7, "size": 1 }, "OC3M": { "description": "Output compare 3 mode", "offset": 4, "size": 3 }, "OC3PE": { "description": "Output compare 3 preload\n enable", "offset": 3, "size": 1 }, "OC3FE": { "description": "Output compare 3 fast\n enable", "offset": 2, "size": 1 }, "CC3S": { "description": "Capture/Compare 3\n selection", "offset": 0, "size": 2 }, "OC3M_3": { "description": "Output Compare 3 mode bit\n 3", "offset": 16, "size": 1 }, "OC4M_3": { "description": "Output Compare 4 mode bit\n 3", "offset": 24, "size": 1 } } } }, "CCMR2_Input": { "description": "capture/compare mode register 2 (input\n mode)", "offset": 28, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "IC4F": { "description": "Input capture 4 filter", "offset": 12, "size": 4 }, "IC4PSC": { "description": "Input capture 4 prescaler", "offset": 10, "size": 2 }, "CC4S": { "description": "Capture/Compare 4\n selection", "offset": 8, "size": 2 }, "IC3F": { "description": "Input capture 3 filter", "offset": 4, "size": 4 }, "IC3PSC": { "description": "Input capture 3 prescaler", "offset": 2, "size": 2 }, "CC3S": { "description": "Capture/compare 3\n selection", "offset": 0, "size": 2 } } } }, "CCER": { "description": "capture/compare enable\n register", "offset": 32, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CC1E": { "description": "Capture/Compare 1 output\n enable", "offset": 0, "size": 1 }, "CC1P": { "description": "Capture/Compare 1 output\n Polarity", "offset": 1, "size": 1 }, "CC1NE": { "description": "Capture/Compare 1 complementary output\n enable", "offset": 2, "size": 1 }, "CC1NP": { "description": "Capture/Compare 1 output\n Polarity", "offset": 3, "size": 1 }, "CC2E": { "description": "Capture/Compare 2 output\n enable", "offset": 4, "size": 1 }, "CC2P": { "description": "Capture/Compare 2 output\n Polarity", "offset": 5, "size": 1 }, "CC2NE": { "description": "Capture/Compare 2 complementary output\n enable", "offset": 6, "size": 1 }, "CC2NP": { "description": "Capture/Compare 2 output\n Polarity", "offset": 7, "size": 1 }, "CC3E": { "description": "Capture/Compare 3 output\n enable", "offset": 8, "size": 1 }, "CC3P": { "description": "Capture/Compare 3 output\n Polarity", "offset": 9, "size": 1 }, "CC3NE": { "description": "Capture/Compare 3 complementary output\n enable", "offset": 10, "size": 1 }, "CC3NP": { "description": "Capture/Compare 3 output\n Polarity", "offset": 11, "size": 1 }, "CC4E": { "description": "Capture/Compare 4 output\n enable", "offset": 12, "size": 1 }, "CC4P": { "description": "Capture/Compare 3 output\n Polarity", "offset": 13, "size": 1 }, "CC4NP": { "description": "Capture/Compare 4 output\n Polarity", "offset": 15, "size": 1 }, "CC5E": { "description": "Capture/Compare 5 output\n enable", "offset": 16, "size": 1 }, "CC5P": { "description": "Capture/Compare 5 output\n Polarity", "offset": 17, "size": 1 }, "CC6E": { "description": "Capture/Compare 6 output\n enable", "offset": 20, "size": 1 }, "CC6P": { "description": "Capture/Compare 6 output\n Polarity", "offset": 21, "size": 1 } } } }, "CNT": { "description": "counter", "offset": 36, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CNT": { "description": "counter value", "offset": 0, "size": 16 }, "UIFCPY": { "description": "UIF copy", "offset": 31, "size": 1, "access": "read-only" } } } }, "PSC": { "description": "prescaler", "offset": 40, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "PSC": { "description": "Prescaler value", "offset": 0, "size": 16 } } } }, "ARR": { "description": "auto-reload register", "offset": 44, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "ARR": { "description": "Auto-reload value", "offset": 0, "size": 16 } } } }, "RCR": { "description": "repetition counter register", "offset": 48, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "REP": { "description": "Repetition counter value", "offset": 0, "size": 16 } } } }, "CCR1": { "description": "capture/compare register 1", "offset": 52, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CCR1": { "description": "Capture/Compare 1 value", "offset": 0, "size": 16 } } } }, "CCR2": { "description": "capture/compare register 2", "offset": 56, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CCR2": { "description": "Capture/Compare 2 value", "offset": 0, "size": 16 } } } }, "CCR3": { "description": "capture/compare register 3", "offset": 60, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CCR3": { "description": "Capture/Compare 3 value", "offset": 0, "size": 16 } } } }, "CCR4": { "description": "capture/compare register 4", "offset": 64, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CCR4": { "description": "Capture/Compare 3 value", "offset": 0, "size": 16 } } } }, "BDTR": { "description": "break and dead-time register", "offset": 68, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DTG": { "description": "Dead-time generator setup", "offset": 0, "size": 8 }, "LOCK": { "description": "Lock configuration", "offset": 8, "size": 2 }, "OSSI": { "description": "Off-state selection for Idle\n mode", "offset": 10, "size": 1 }, "OSSR": { "description": "Off-state selection for Run\n mode", "offset": 11, "size": 1 }, "BKE": { "description": "Break enable", "offset": 12, "size": 1 }, "BKP": { "description": "Break polarity", "offset": 13, "size": 1 }, "AOE": { "description": "Automatic output enable", "offset": 14, "size": 1 }, "MOE": { "description": "Main output enable", "offset": 15, "size": 1 }, "BKF": { "description": "Break filter", "offset": 16, "size": 4 }, "BK2F": { "description": "Break 2 filter", "offset": 20, "size": 4 }, "BK2E": { "description": "Break 2 enable", "offset": 24, "size": 1 }, "BK2P": { "description": "Break 2 polarity", "offset": 25, "size": 1 } } } }, "DCR": { "description": "DMA control register", "offset": 72, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DBL": { "description": "DMA burst length", "offset": 8, "size": 5 }, "DBA": { "description": "DMA base address", "offset": 0, "size": 5 } } } }, "DMAR": { "description": "DMA address for full transfer", "offset": 76, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DMAB": { "description": "DMA register for burst\n accesses", "offset": 0, "size": 16 } } } }, "CCMR3_Output": { "description": "capture/compare mode register 3 (output\n mode)", "offset": 84, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "OC5FE": { "description": "Output compare 5 fast\n enable", "offset": 2, "size": 1 }, "OC5PE": { "description": "Output compare 5 preload\n enable", "offset": 3, "size": 1 }, "OC5M": { "description": "Output compare 5 mode", "offset": 4, "size": 3 }, "OC5CE": { "description": "Output compare 5 clear\n enable", "offset": 7, "size": 1 }, "OC6FE": { "description": "Output compare 6 fast\n enable", "offset": 10, "size": 1 }, "OC6PE": { "description": "Output compare 6 preload\n enable", "offset": 11, "size": 1 }, "OC6M": { "description": "Output compare 6 mode", "offset": 12, "size": 3 }, "OC6CE": { "description": "Output compare 6 clear\n enable", "offset": 15, "size": 1 }, "OC5M_3": { "description": "Outout Compare 5 mode bit\n 3", "offset": 16, "size": 1 }, "OC6M_3": { "description": "Outout Compare 6 mode bit\n 3", "offset": 24, "size": 1 } } } }, "CCR5": { "description": "capture/compare register 5", "offset": 88, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CCR5": { "description": "Capture/Compare 5 value", "offset": 0, "size": 16 }, "GC5C1": { "description": "Group Channel 5 and Channel\n 1", "offset": 29, "size": 1 }, "GC5C2": { "description": "Group Channel 5 and Channel\n 2", "offset": 30, "size": 1 }, "GC5C3": { "description": "Group Channel 5 and Channel\n 3", "offset": 31, "size": 1 } } } }, "CCR6": { "description": "capture/compare register 6", "offset": 92, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "CCR6": { "description": "Capture/Compare 6 value", "offset": 0, "size": 16 } } } }, "OR": { "description": "option registers", "offset": 96, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "TIM1_ETR_ADC1_RMP": { "description": "TIM1_ETR_ADC1 remapping\n capability", "offset": 0, "size": 2 }, "TIM1_ETR_ADC4_RMP": { "description": "TIM1_ETR_ADC4 remapping\n capability", "offset": 2, "size": 2 } } } } } } }, "DBGMCU": { "description": "Debug support", "children": { "registers": { "IDCODE": { "description": "MCU Device ID Code Register", "offset": 0, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "access": "read-only", "children": { "fields": { "DEV_ID": { "description": "Device Identifier", "offset": 0, "size": 12 }, "REV_ID": { "description": "Revision Identifier", "offset": 16, "size": 16 } } } }, "CR": { "description": "Debug MCU Configuration\n Register", "offset": 4, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DBG_SLEEP": { "description": "Debug Sleep mode", "offset": 0, "size": 1 }, "DBG_STOP": { "description": "Debug Stop Mode", "offset": 1, "size": 1 }, "DBG_STANDBY": { "description": "Debug Standby Mode", "offset": 2, "size": 1 }, "TRACE_IOEN": { "description": "Trace pin assignment\n control", "offset": 5, "size": 1 }, "TRACE_MODE": { "description": "Trace pin assignment\n control", "offset": 6, "size": 2 } } } }, "APB1FZ": { "description": "APB Low Freeze Register", "offset": 8, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DBG_TIM2_STOP": { "description": "Debug Timer 2 stopped when Core is\n halted", "offset": 0, "size": 1 }, "DBG_TIM3_STOP": { "description": "Debug Timer 3 stopped when Core is\n halted", "offset": 1, "size": 1 }, "DBG_TIM4_STOP": { "description": "Debug Timer 4 stopped when Core is\n halted", "offset": 2, "size": 1 }, "DBG_TIM5_STOP": { "description": "Debug Timer 5 stopped when Core is\n halted", "offset": 3, "size": 1 }, "DBG_TIM6_STOP": { "description": "Debug Timer 6 stopped when Core is\n halted", "offset": 4, "size": 1 }, "DBG_TIM7_STOP": { "description": "Debug Timer 7 stopped when Core is\n halted", "offset": 5, "size": 1 }, "DBG_TIM12_STOP": { "description": "Debug Timer 12 stopped when Core is\n halted", "offset": 6, "size": 1 }, "DBG_TIM13_STOP": { "description": "Debug Timer 13 stopped when Core is\n halted", "offset": 7, "size": 1 }, "DBG_TIMER14_STOP": { "description": "Debug Timer 14 stopped when Core is\n halted", "offset": 8, "size": 1 }, "DBG_TIM18_STOP": { "description": "Debug Timer 18 stopped when Core is\n halted", "offset": 9, "size": 1 }, "DBG_RTC_STOP": { "description": "Debug RTC stopped when Core is\n halted", "offset": 10, "size": 1 }, "DBG_WWDG_STOP": { "description": "Debug Window Wachdog stopped when Core\n is halted", "offset": 11, "size": 1 }, "DBG_IWDG_STOP": { "description": "Debug Independent Wachdog stopped when\n Core is halted", "offset": 12, "size": 1 }, "I2C1_SMBUS_TIMEOUT": { "description": "SMBUS timeout mode stopped when Core is\n halted", "offset": 21, "size": 1 }, "I2C2_SMBUS_TIMEOUT": { "description": "SMBUS timeout mode stopped when Core is\n halted", "offset": 22, "size": 1 }, "DBG_CAN_STOP": { "description": "Debug CAN stopped when core is\n halted", "offset": 25, "size": 1 } } } }, "APB2FZ": { "description": "APB High Freeze Register", "offset": 12, "size": 32, "reset_value": 0, "reset_mask": 4294967295, "children": { "fields": { "DBG_TIM15_STOP": { "description": "Debug Timer 15 stopped when Core is\n halted", "offset": 2, "size": 1 }, "DBG_TIM16_STOP": { "description": "Debug Timer 16 stopped when Core is\n halted", "offset": 3, "size": 1 }, "DBG_TIM17_STO": { "description": "Debug Timer 17 stopped when Core is\n halted", "offset": 4, "size": 1 }, "DBG_TIM19_STOP": { "description": "Debug Timer 19 stopped when Core is\n halted", "offset": 5, "size": 1 } } } } } } } } }, "devices": { "STM32F303": { "arch": "cortex_m4", "description": "STM32F303", "properties": { "cpu.nvic_prio_bits": "3", "cpu.mpu": "false", "cpu.fpu": "false", "cpu.revision": "r1p0", "cpu.vendor_systick_config": "false", "cpu.endian": "little", "cpu.name": "CM4" }, "children": { "interrupts": { "MemManageFault": { "index": -12 }, "BusFault": { "index": -11 }, "UsageFault": { "index": -10 }, "DebugMonitor": { "index": -4 }, "NMI": { "index": -14 }, "HardFault": { "index": -13 }, "SVCall": { "index": -5 }, "PendSV": { "index": -2 }, "SysTick": { "index": -1 }, "EXTI2_TSC": { "index": 8, "description": "EXTI Line2 and Touch sensing\n interrupts" }, "FLASH": { "index": 4, "description": "Flash global interrupt" }, "RCC": { "index": 5, "description": "RCC global interrupt" }, "DMA1_CH1": { "index": 11, "description": "DMA1 channel 1 interrupt" }, "DMA2_CH1": { "index": 56, "description": "DMA2 channel1 global interrupt" }, "TIM2": { "index": 28, "description": "TIM2 global interrupt" }, "TIM3": { "index": 29, "description": "TIM3 global interrupt" }, "TIM4": { "index": 30, "description": "TIM4 global interrupt" }, "TIM1_BRK_TIM15": { "index": 24, "description": "TIM1 Break/TIM15 global\n interruts" }, "TIM1_UP_TIM16": { "index": 25, "description": "TIM1 Update/TIM16 global\n interrupts" }, "TIM1_TRG_COM_TIM17": { "index": 26, "description": "TIM1 trigger and commutation/TIM17\n interrupts" }, "USART1_EXTI25": { "index": 37, "description": "USART1 global interrupt and EXTI Line 25\n interrupt" }, "USART2_EXTI26": { "index": 38, "description": "USART2 global interrupt and EXTI Line 26\n interrupt" }, "USART3_EXTI28": { "index": 39, "description": "USART3 global interrupt and EXTI Line 28\n interrupt" }, "UART4_EXTI34": { "index": 52, "description": "UART4 global and EXTI Line 34\n interrupts" }, "UART5_EXTI35": { "index": 53, "description": "UART5 global and EXTI Line 35\n interrupts" }, "SPI1": { "index": 35, "description": "SPI1 global interrupt" }, "SPI2": { "index": 36, "description": "SPI2 global interrupt" }, "SPI3": { "index": 51, "description": "SPI3 global interrupt" }, "TAMP_STAMP": { "index": 2, "description": "Tamper and TimeStamp interrupts" }, "PVD": { "index": 1, "description": "PVD through EXTI line detection\n interrupt" }, "USB_HP_CAN_TX": { "index": 19, "description": "USB High Priority/CAN_TX\n interrupts" }, "USB_WKUP": { "index": 42, "description": "USB wakeup from Suspend" }, "I2C1_EV_EXTI23": { "index": 31, "description": "I2C1 event interrupt and EXTI Line23\n interrupt" }, "I2C2_EV_EXTI24": { "index": 33, "description": "I2C2 event interrupt & EXTI Line24\n interrupt" }, "WWDG": { "index": 0, "description": "Window Watchdog interrupt" }, "RTC_WKUP": { "index": 3, "description": "RTC Wakeup interrupt through the EXTI\n line" }, "TIM6_DACUNDER": { "index": 54, "description": "TIM6 global and DAC12 underrun\n interrupts" }, "TIM7": { "index": 55, "description": "TIM7 global interrupt" }, "TIM1_CC": { "index": 27, "description": "TIM1 capture compare interrupt" }, "TIM8_BRK": { "index": 43, "description": "TIM8 break interrupt" }, "ADC1_2": { "index": 18, "description": "ADC1 and ADC2 global interrupt" }, "ADC3": { "index": 47, "description": "ADC3 global interrupt" }, "ADC4": { "index": 61, "description": "ADC4 global interrupt" }, "COMP123": { "index": 64, "description": "COMP1 & COMP2 & COMP3 interrupts\n combined with EXTI Lines 21, 22 and 29\n interrupts" }, "FMC": { "index": 48, "description": "FSMC global interrupt" }, "FPU": { "index": 81, "description": "Floating point unit interrupt" } }, "peripheral_instances": { "GPIOA": { "description": "General-purpose I/Os", "offset": 1207959552, "type": "types.peripherals.GPIOA" }, "GPIOB": { "description": "General-purpose I/Os", "offset": 1207960576, "type": "types.peripherals.GPIOB" }, "GPIOC": { "offset": 1207961600, "type": "types.peripherals.GPIOB" }, "GPIOD": { "offset": 1207962624, "type": "types.peripherals.GPIOB" }, "GPIOE": { "offset": 1207963648, "type": "types.peripherals.GPIOB" }, "GPIOF": { "offset": 1207964672, "type": "types.peripherals.GPIOB" }, "GPIOG": { "offset": 1207965696, "type": "types.peripherals.GPIOB" }, "GPIOH": { "offset": 1207966720, "type": "types.peripherals.GPIOB" }, "TSC": { "description": "Touch sensing controller", "offset": 1073889280, "type": "types.peripherals.TSC" }, "CRC": { "description": "cyclic redundancy check calculation\n unit", "offset": 1073885184, "type": "types.peripherals.CRC" }, "Flash": { "description": "Flash", "offset": 1073881088, "type": "types.peripherals.Flash" }, "RCC": { "description": "Reset and clock control", "offset": 1073876992, "type": "types.peripherals.RCC" }, "DMA1": { "description": "DMA controller 1", "offset": 1073872896, "type": "types.peripherals.DMA1" }, "DMA2": { "offset": 1073873920, "type": "types.peripherals.DMA1" }, "TIM2": { "description": "General purpose timer", "offset": 1073741824, "type": "types.peripherals.TIM2" }, "TIM3": { "offset": 1073742848, "type": "types.peripherals.TIM2" }, "TIM4": { "offset": 1073743872, "type": "types.peripherals.TIM2" }, "TIM15": { "description": "General purpose timers", "offset": 1073823744, "type": "types.peripherals.TIM15" }, "TIM16": { "description": "General-purpose-timers", "offset": 1073824768, "type": "types.peripherals.TIM16" }, "TIM17": { "description": "General purpose timer", "offset": 1073825792, "type": "types.peripherals.TIM17" }, "USART1": { "description": "Universal synchronous asynchronous receiver\n transmitter", "offset": 1073821696, "type": "types.peripherals.USART1" }, "USART2": { "offset": 1073759232, "type": "types.peripherals.USART1" }, "USART3": { "offset": 1073760256, "type": "types.peripherals.USART1" }, "UART4": { "offset": 1073761280, "type": "types.peripherals.USART1" }, "UART5": { "offset": 1073762304, "type": "types.peripherals.USART1" }, "SPI1": { "description": "Serial peripheral interface/Inter-IC\n sound", "offset": 1073819648, "type": "types.peripherals.SPI1" }, "SPI2": { "offset": 1073756160, "type": "types.peripherals.SPI1" }, "SPI3": { "offset": 1073757184, "type": "types.peripherals.SPI1" }, "I2S2ext": { "offset": 1073755136, "type": "types.peripherals.SPI1" }, "I2S3ext": { "offset": 1073758208, "type": "types.peripherals.SPI1" }, "SPI4": { "offset": 1073822720, "type": "types.peripherals.SPI1" }, "EXTI": { "description": "External interrupt/event\n controller", "offset": 1073808384, "type": "types.peripherals.EXTI" }, "PWR": { "description": "Power control", "offset": 1073770496, "type": "types.peripherals.PWR" }, "CAN": { "description": "Controller area network", "offset": 1073767424, "type": "types.peripherals.CAN" }, "USB_FS": { "description": "Universal serial bus full-speed device\n interface", "offset": 1073765376, "type": "types.peripherals.USB_FS" }, "I2C1": { "description": "Inter-integrated circuit", "offset": 1073763328, "type": "types.peripherals.I2C1" }, "I2C2": { "offset": 1073764352, "type": "types.peripherals.I2C1" }, "I2C3": { "offset": 1073772544, "type": "types.peripherals.I2C1" }, "IWDG": { "description": "Independent watchdog", "offset": 1073754112, "type": "types.peripherals.IWDG" }, "WWDG": { "description": "Window watchdog", "offset": 1073753088, "type": "types.peripherals.WWDG" }, "RTC": { "description": "Real-time clock", "offset": 1073752064, "type": "types.peripherals.RTC" }, "TIM6": { "description": "Basic timers", "offset": 1073745920, "type": "types.peripherals.TIM6" }, "TIM7": { "offset": 1073746944, "type": "types.peripherals.TIM6" }, "DAC": { "description": "Digital-to-analog converter", "offset": 1073771520, "type": "types.peripherals.DAC" }, "DBGMCU": { "description": "Debug support", "offset": 3758366720, "type": "types.peripherals.DBGMCU" }, "TIM1": { "description": "Advanced timer", "offset": 1073818624, "type": "types.peripherals.TIM1" }, "TIM20": { "offset": 1073827840, "type": "types.peripherals.TIM1" }, "TIM8": { "description": "Advanced-timers", "offset": 1073820672, "type": "types.peripherals.TIM8" }, "ADC1": { "description": "Analog-to-Digital Converter", "offset": 1342177280, "type": "types.peripherals.ADC1" }, "ADC2": { "offset": 1342177536, "type": "types.peripherals.ADC1" }, "ADC3": { "offset": 1342178304, "type": "types.peripherals.ADC1" }, "ADC4": { "offset": 1342178560, "type": "types.peripherals.ADC1" }, "ADC1_2": { "description": "Analog-to-Digital Converter", "offset": 1342178048, "type": "types.peripherals.ADC1_2" }, "ADC3_4": { "offset": 1342179072, "type": "types.peripherals.ADC1_2" }, "SYSCFG_COMP_OPAMP": { "description": "System configuration controller _Comparator and\n Operational amplifier", "offset": 1073807360, "type": "types.peripherals.SYSCFG_COMP_OPAMP" }, "FMC": { "description": "Flexible memory controller", "offset": 2684355584, "type": "types.peripherals.FMC" }, "NVIC": { "description": "Nested Vectored Interrupt\n Controller", "offset": 3758153984, "type": "types.peripherals.NVIC" }, "FPU": { "description": "Floting point unit", "offset": 3758157620, "type": "types.peripherals.FPU" }, "MPU": { "description": "Memory protection unit", "offset": 3758157200, "type": "types.peripherals.MPU" }, "STK": { "description": "SysTick timer", "offset": 3758153744, "type": "types.peripherals.STK" }, "SCB": { "description": "System control block", "offset": 3758157056, "type": "types.peripherals.SCB" }, "NVIC_STIR": { "description": "Nested vectored interrupt\n controller", "offset": 3758157568, "type": "types.peripherals.NVIC_STIR" }, "FPU_CPACR": { "description": "Floating point unit CPACR", "offset": 3758157192, "type": "types.peripherals.FPU_CPACR" }, "SCB_ACTRL": { "description": "System control block ACTLR", "offset": 3758153736, "type": "types.peripherals.SCB_ACTRL" } } } } } }