158ad9eefa
Fix compilation with latest zig master ( #102 )
7 months ago
f489ac41d9
update libxml2 ( #101 )
7 months ago
d488b381d7
update build api ( #99 )
7 months ago
eb98a1d1ab
handle additional %s case for register names in SVD ( #97 )
7 months ago
7c75bc6297
don't generate system registers ( #96 )
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* don't generate system registers
* handle missing cpu name
7 months ago
c48ca0e86b
use new for loops over iterators ( #95 )
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* use new for loops over iterators
* run github actions on every push
7 months ago
137b50484a
Snake case ( #94 )
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* wip
* converted functions to snake case
7 months ago
fa73a4d164
new for loop syntax ( #93 )
7 months ago
4b38512d67
Update README.md ( #92 )
7 months ago
b81760cd24
getMode() now generated as get_mode() ( #90 )
7 months ago
060b6fbd5a
update json tree api ( #89 )
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* update json tree api
* sneak in namespacing of types into peripherals, registers, etc
* fix cache api usage, later try cache invalidation
7 months ago
f174713fd3
catch up to zig modules ( #88 )
7 months ago
44201d5370
Add core registers for Cortex M0 and M0+ ( #86 )
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* Refactored core register functions
Most of this was just renaming function calls
* More refactoring
* Added calls to the core register functions
* Return error on missing NvicPrioBits
* Added function to check the value of vendor _systick_config
This should work but it is a bit brittle.
If vendorSystickConfig isn't lowercase for false it will return true
* Add extra check for vendor_systick_config
* fix formatting
7 months ago
8c47254c9c
SVD: peripheral derivation ( #84 )
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* SVD: peripheral derivation
7 months ago
f42d279890
Fix build api breaks and morale ( #85 )
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* fix build api breaks
* fix ci
* zig parser api update
7 months ago
0838f5809a
Add all interrupts for a peripheral ( #81 )
7 months ago
3d6cf928b3
initial vector table support for arm ( #80 )
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When parsing ATDF or SVD files, seed the interrupts with known exception handlers for different architectures.
7 months ago
eb24365786
regzon ( #79 )
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regzon is the name for the json output for reg'z data model. This PR includes a number of tests for serialization and deserialization. The intention of this format is to provide an accessible format for tooling, and to provide a medium for schema patching. Rather than errata, patching can be utilized to improve codegen such as type deduplication.
This format is subject to change.
7 months ago
ec84f7eebf
svd field array ( #77 )
7 months ago
71a8e27e8e
omit [%s] suffix for svd ( #76 )
7 months ago
83b4ee2a3d
packed structs can have an explicit backing integer ( #75 )
7 months ago
43ee9c8af0
vector table generation for ATDF ( #74 )
7 months ago
efeba02119
enums in SVD are always children of peripherals ( #71 )
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* enums in SVD are always children of peripherals
* make SVD enums anonymous for now
7 months ago
66ac34e33b
fix mmio array codegen ( #72 )
7 months ago
a34e4ef648
initial support for dimElementsGroup for SVD ( #70 )
7 months ago
293f25e6c3
make distinct types for peripherals always ( #69 )
7 months ago
9627d4196c
Rearchitect Regz ( #63 )
7 months ago
2b985fc898
Characterize ( #60 )
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* rename ndjson, add new tool to characterize sets of xml files
* remove some debug logs
* add characterized register schemas
7 months ago
f204d7f42c
A quick fix for ATDF codegen and register groups ( #59 )
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* A quick fix for ATDF codegen and register groups
The current code was expecting register groups and peripherals to have a
1:1 ratio, however the register groups under `modules` are more like
templates which are used to instantiate peripherals. This does the
minimal amount of refactoring in order for this to work and unblock some
users.
* i386 -> x86 target name update
7 months ago
7a0d75f105
upgrade dependencies ( #57 )
7 months ago
0d0e667c26
removing some used "unused" variables ( #55 )
7 months ago
dea71d5272
add comptime for uses of ++ ( #53 )
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* add comptime for uses of ++
* ptrCast instead of bitCast
* don't build i386 windows for now
7 months ago
43a88c16b3
fix ptrCast to intToPtr ( #50 )
7 months ago
c87a7422fc
update clap, fix logs of optional types ( #48 )
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* update clap, fix logs of optional types
* rename empty test
7 months ago
242b9300b6
update build badge
7 months ago
ba94c404f8
migrate linux builds to build kite ( #47 )
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* see if it works
* add badge
* try grouping and matrix
* poke
* fix typo
* clean up
7 months ago
f160633eb5
add buildkite pipeline file ( #46 )
7 months ago
befb9a2928
make InterruptVector public ( #44 )
7 months ago
708f0a6af6
don't overwrite register set, simplify nvic register generation ( #42 )
7 months ago
48f2c0b051
Nvic codegen ( #41 )
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* add system registers for cortex m0 and m1, nvic register generation for the chip
* make warning log a debug log
* usize to u64
* register size is now max 2^16 - 1
7 months ago
c38ca6403e
Update build.zig: rename path->source ( #39 )
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See ziglang/zig#11557
7 months ago
9af2e274f1
core registers for the m0plus ( #26 )
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* core registers for the m0plus
* do proper optional handling
7 months ago
6f4850dab7
fix mmio int generation ( #25 )
7 months ago
780a75268f
add reset value and reset mask register properties ( #24 )
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* add reset value and reset mask register properties
* usize => u64
7 months ago
3d0c1ece64
use unmanaged datastructures ( #23 )
7 months ago
8ba737656a
Add support for dimensioned register fields ( #20 )
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Signed-off-by: Riccardo Binetti <rbino@gmx.com>
7 months ago
e34f293fec
Update README.md
7 months ago
edf25671b9
add parsing the access type for svd ( #22 )
7 months ago
2eb508c318
Register properties size ( #21 )
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* snapshot
* size from register properties now passes tests
* finish moving to named index types
7 months ago
96bf099d2e
Update README.md
7 months ago
Nicolas Goy
Matt Knight
Matt Knight
Paul
Jacob Peters
Eckhart Köppen
Ethan Frei
Matt Hall
Riccardo Binetti