* Add stm32f429 registers
Generated using regz with:
./regz STM32F429.svd > registers.zig
Using this SVD:
871761af63/data/STMicro/STM32F429.svd
* Add initial support for the stm32f429idiscovery eval board
Blinky example working on the board
* Makes AVR UART work.
* Some comment. This is definitly not padding.
* Exports panic, log and log_level from application.
* Implements generic quadrature decoder driver.
* Fixes `@export` bug in AVR interrupt logic. Now we get distinct interrupt vectors.
Co-authored-by: Felix "xq" Queißner <git@masterq32.de>
* Add stm32f407 registers
Generated using regz with:
./regz STM32F407.svd > registers.zig
Using this SVD:
871761af63/data/STMicro/STM32F407.svd
* Add initial support for the stm32f4discovery eval board
The blinky example is working on the board
* build.zig: Trivial rename around UART test
* mmio: Add writeRaw() to set a full register
* UART: Add TODO for auto baud rate detection
* STM32F30x Initial USART1 output/transmit support
All code assumes default chip clock configuration.
Code assumes STM32F303xB / STM32F3030xC.
Code supports only 8 data bits, 1 stop bit.
* stm32f3discovery @panic() to UART1
This is done by implementing `debugWrite()` for the board,
which only initializes UART1 if that was not yet done,
and flushes afterwards to make sure the host receives all.
* stm32f303: Support UART1 reader
This is done by implementing `rx()` and `canRead()`.
* stm32f303 UART1 correctly support 7 and 8 bits
This includes correctly masking the parity bit
on reads.
* stm32f3 UART1 support 0.5/1.5/2 stop bits
* stm32f303 UART1 simplify parity code
* stm32f303 I2C rough initial code
Allows only writing and reading single bytes.
* stm32f3 i2c: enable debug 'logging'
* Add a few comments
* I2C API changes, STM32F303 I2C multi-byte transfers
Now using controller/device terminology, instead of master/slave.
Now using 'transfer objects' to make STOPs and re-STARTs explicit,
and allow using Writer and Reader APIs.
Added 'register' abstraction.
STM32F303 I2C now supports this new API, and multi-byte transfers.
Now waiting for I2C_ISR.BUSY == 0, after setting I2C_CR2.STOP == 1.
Without this, the sequence write-stop-write caused an additional STOP
to be sent immediately the START and address of the second write.
* Make work with regz-generated registers.zig change
* Updated to match regz-generated update
* After #23 repair Reset on stm32, lpc1768
* Clean-up I2C `readRegisters()`.
* Refactor to separate read/write states
* On STM32F303, make second read call fail
Also doc comments to clarify the new API.
* STM32 I2C: Properly support multiple write calls
* I2C STM32: Fix release mode compile error
...on top of an earlier commit on this branch.
* I2C Add 'write register' shorthand functions
* mostly implemented, need different patch in order to wire it in
* add generated code
* turned interrupts back on
* fix symbol names for avr
* export in cpu file
* Emits a function instead of a `void` symbol.
* add interrupt test to avr
* Removes invalid comment.
Co-authored-by: Felix "xq" Queißner <git@masterq32.de>
* Greatly simplifies the package logic by using a proxy-to-root package.
* Makes startup logic less obscure.
Co-authored-by: Felix "xq" Queißner <git@masterq32.de>
* Makes default panic uses logging facilities to print the panic message.
* Makes MMIO functions inline for better codegen
* Brings LPC1768 up to date.
Co-authored-by: Felix "xq" Queißner <git@masterq32.de>
* build.zig: Trivial rename around UART test
* mmio: Add writeRaw() to set a full register
* UART: Add TODO for auto baud rate detection
* STM32F30x Initial USART1 output/transmit support
All code assumes default chip clock configuration.
Code assumes STM32F303xB / STM32F3030xC.
Code supports only 8 data bits, 1 stop bit.
* stm32f3discovery @panic() to UART1
This is done by implementing `debugWrite()` for the board,
which only initializes UART1 if that was not yet done,
and flushes afterwards to make sure the host receives all.
* stm32f303: Support UART1 reader
This is done by implementing `rx()` and `canRead()`.
* stm32f303 UART1 correctly support 7 and 8 bits
This includes correctly masking the parity bit
on reads.
* stm32f3 UART1 support 0.5/1.5/2 stop bits
* stm32f303 UART1 simplify parity code
* Make work with regz-generated registers.zig change
* After #23 repair Reset on stm32, lpc1768
* Support disabling UART test configs
* `zig build [install]` also builds .bin files
* Support one blinking LD3 on STM32F3DISCOVERY board
These changes were mostly copied from the stm32f103 already there.
But this is far from complete, many shortcuts were taken:
- Most importantly,
only a single LED on the board, and its port/pin, is supported,
viz. the 'north' LD3 on bit 9 of GPIOE.
- Setting RCC_AHBENR bit IOPEEN ("I/O port E clock enable") is done
at the same as setting the mode (input or output) on one of its pins.
No idea if that is the right place to do this.
- In cortex-m4.zig, using 'max ram' as the initial stack pointer.
The rest is completely copied from cortex-m3.zig.
- UART test is disabled.
(It seems to assume mbed-lpc1768 pin numbers.)
* Nicer initial stack pointer: exactly after RAM
* Fix build error
(How was this code working earlier?!?)
* stm32f30x: Allow all 16 pins, all GPIOx registers
* STM32F3DISCOVERY: map all LED pins
* create linkerscript step
* catch up to master, do some cleanup
* remove references to micro_linker
* commas
* remove package
* use root path trick for cpus and chips
* remove duped file
Riccardo Binetti
Felix Queißner
Marnix Klooster
Matt Knight
Vesim
Felix Queißner