diff --git a/src/modules/chips.zig b/src/modules/chips.zig index 1794e12..4419d2d 100644 --- a/src/modules/chips.zig +++ b/src/modules/chips.zig @@ -103,3 +103,14 @@ pub const nrf52832 = Chip{ MemoryRegion{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, }, }; + +pub const atsame51j20a = Chip{ + .name = "ATSAME51J20A", + .path = root_path ++ "chips/atsame51j20a/atsame51j20a.zig", + .cpu = cpus.cortex_m4, + .memory_regions = &.{ + // SAM D5x/E5x Family Data Sheet page 53 + MemoryRegion{ .offset = 0x00000000, .length = 1024 * 1024, .kind = .flash }, + MemoryRegion{ .offset = 0x20000000, .length = 256 * 1024, .kind = .ram }, + }, +}; \ No newline at end of file diff --git a/src/modules/chips/atsame51j20a/ATSAME51J20A.svd b/src/modules/chips/atsame51j20a/ATSAME51J20A.svd new file mode 100644 index 0000000..10353bd --- /dev/null +++ b/src/modules/chips/atsame51j20a/ATSAME51J20A.svd @@ -0,0 +1,45092 @@ + + + + Microchip Technology + MCHP + ATSAME51J20A + SAME51 + 0 + Microchip ATSAME51J20A Microcontroller + + CM4 + r0p1 + selectable + true + true + 3 + false + + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + AC + U25011.0.0 + Analog Comparators + AC + AC_ + 0x42002000 + + 0 + 0x26 + registers + + + AC + 122 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + write-only + 0x00 + + + START0 + Comparator 0 Start Comparison + 0 + 1 + + + START1 + Comparator 1 Start Comparison + 1 + 1 + + + + + EVCTRL + Event Control + 0x2 + 16 + 0x0000 + + + COMPEO0 + Comparator 0 Event Output Enable + 0 + 1 + + + COMPEO1 + Comparator 1 Event Output Enable + 1 + 1 + + + WINEO0 + Window 0 Event Output Enable + 4 + 1 + + + COMPEI0 + Comparator 0 Event Input Enable + 8 + 1 + + + COMPEI1 + Comparator 1 Event Input Enable + 9 + 1 + + + INVEI0 + Comparator 0 Input Event Invert Enable + 12 + 1 + + + INVEI1 + Comparator 1 Input Event Invert Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + COMP0 + Comparator 0 + 0 + 1 + + + COMP1 + Comparator 1 + 1 + 1 + + + WIN0 + Window 0 + 4 + 1 + + + + + STATUSA + Status A + 0x7 + 8 + read-only + 0x00 + + + STATE0 + Comparator 0 Current State + 0 + 1 + + + STATE1 + Comparator 1 Current State + 1 + 1 + + + WSTATE0 + Window 0 Current State + 4 + 2 + + WSTATE0Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + + + STATUSB + Status B + 0x8 + 8 + read-only + 0x00 + + + READY0 + Comparator 0 Ready + 0 + 1 + + + READY1 + Comparator 1 Ready + 1 + 1 + + + + + DBGCTRL + Debug Control + 0x9 + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + WINCTRL + Window Control + 0xA + 8 + 0x00 + + + WEN0 + Window 0 Mode Enable + 0 + 1 + + + WINTSEL0 + Window 0 Interrupt Selection + 1 + 2 + + WINTSEL0Select + + ABOVE + Interrupt on signal above window + 0 + + + INSIDE + Interrupt on signal inside window + 1 + + + BELOW + Interrupt on signal below window + 2 + + + OUTSIDE + Interrupt on signal outside window + 3 + + + + + + + 2 + 1 + SCALER[%s] + Scaler n + 0xC + 8 + 0x00 + + + VALUE + Scaler Value + 0 + 6 + + + + + 2 + 4 + COMPCTRL[%s] + Comparator Control n + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + SINGLE + Single-Shot Mode + 2 + 1 + + + INTSEL + Interrupt Selection + 3 + 2 + + INTSELSelect + + TOGGLE + Interrupt on comparator output toggle + 0 + + + RISING + Interrupt on comparator output rising + 1 + + + FALLING + Interrupt on comparator output falling + 2 + + + EOC + Interrupt on end of comparison (single-shot mode only) + 3 + + + + + RUNSTDBY + Run in Standby + 6 + 1 + + + MUXNEG + Negative Input Mux Selection + 8 + 3 + + MUXNEGSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + GND + Ground + 4 + + + VSCALE + VDD scaler + 5 + + + BANDGAP + Internal bandgap voltage + 6 + + + DAC + DAC output + 7 + + + + + MUXPOS + Positive Input Mux Selection + 12 + 3 + + MUXPOSSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + VSCALE + VDD Scaler + 4 + + + + + SWAP + Swap Inputs and Invert + 15 + 1 + + + SPEED + Speed Selection + 16 + 2 + + SPEEDSelect + + HIGH + High speed + 3 + + + + + HYSTEN + Hysteresis Enable + 19 + 1 + + + HYST + Hysteresis Level + 20 + 2 + + HYSTSelect + + HYST50 + 50mV + 0 + + + HYST100 + 100mV + 1 + + + HYST150 + 150mV + 2 + + + + + FLEN + Filter Length + 24 + 3 + + FLENSelect + + OFF + No filtering + 0 + + + MAJ3 + 3-bit majority function (2 of 3) + 1 + + + MAJ5 + 5-bit majority function (3 of 5) + 2 + + + + + OUT + Output + 28 + 2 + + OUTSelect + + OFF + The output of COMPn is not routed to the COMPn I/O port + 0 + + + ASYNC + The asynchronous output of COMPn is routed to the COMPn I/O port + 1 + + + SYNC + The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port + 2 + + + + + + + SYNCBUSY + Synchronization Busy + 0x20 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + WINCTRL + WINCTRL Synchronization Busy + 2 + 1 + + + COMPCTRL0 + COMPCTRL 0 Synchronization Busy + 3 + 1 + + + COMPCTRL1 + COMPCTRL 1 Synchronization Busy + 4 + 1 + + + + + CALIB + Calibration + 0x24 + 16 + 0x0101 + + + BIAS0 + COMP0/1 Bias Scaling + 0 + 2 + + + + + + + ADC0 + U25001.0.0 + Analog Digital Converter + ADC + ADC_ + 0x43001C00 + + 0 + 0x4A + registers + + + ADC0_OTHER + 118 + + + ADC0_RESRDY + 119 + + + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + DUALSEL + Dual Mode Trigger Selection + 3 + 2 + + DUALSELSelect + + BOTH + Start event or software trigger will start a conversion on both ADCs + 0 + + + INTERLEAVE + START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 + 1 + + + + + SLAVEEN + Slave Enable + 5 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + PRESCALER + Prescaler Configuration + 8 + 3 + + PRESCALERSelect + + DIV2 + Peripheral clock divided by 2 + 0 + + + DIV4 + Peripheral clock divided by 4 + 1 + + + DIV8 + Peripheral clock divided by 8 + 2 + + + DIV16 + Peripheral clock divided by 16 + 3 + + + DIV32 + Peripheral clock divided by 32 + 4 + + + DIV64 + Peripheral clock divided by 64 + 5 + + + DIV128 + Peripheral clock divided by 128 + 6 + + + DIV256 + Peripheral clock divided by 256 + 7 + + + + + R2R + Rail to Rail Operation Enable + 15 + 1 + + + + + EVCTRL + Event Control + 0x2 + 8 + 0x00 + + + FLUSHEI + Flush Event Input Enable + 0 + 1 + + + STARTEI + Start Conversion Event Input Enable + 1 + 1 + + + FLUSHINV + Flush Event Invert Enable + 2 + 1 + + + STARTINV + Start Conversion Event Invert Enable + 3 + 1 + + + RESRDYEO + Result Ready Event Out + 4 + 1 + + + WINMONEO + Window Monitor Event Out + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x3 + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + INPUTCTRL + Input Control + 0x4 + 16 + 0x0000 + + + MUXPOS + Positive Mux Input Selection + 0 + 5 + + MUXPOSSelect + + AIN0 + ADC AIN0 Pin + 0x0 + + + AIN1 + ADC AIN1 Pin + 0x1 + + + AIN2 + ADC AIN2 Pin + 0x2 + + + AIN3 + ADC AIN3 Pin + 0x3 + + + AIN4 + ADC AIN4 Pin + 0x4 + + + AIN5 + ADC AIN5 Pin + 0x5 + + + AIN6 + ADC AIN6 Pin + 0x6 + + + AIN7 + ADC AIN7 Pin + 0x7 + + + AIN8 + ADC AIN8 Pin + 0x8 + + + AIN9 + ADC AIN9 Pin + 0x9 + + + AIN10 + ADC AIN10 Pin + 0xA + + + AIN11 + ADC AIN11 Pin + 0xB + + + AIN12 + ADC AIN12 Pin + 0xC + + + AIN13 + ADC AIN13 Pin + 0xD + + + AIN14 + ADC AIN14 Pin + 0xE + + + AIN15 + ADC AIN15 Pin + 0xF + + + AIN16 + ADC AIN16 Pin + 0x10 + + + AIN17 + ADC AIN17 Pin + 0x11 + + + AIN18 + ADC AIN18 Pin + 0x12 + + + AIN19 + ADC AIN19 Pin + 0x13 + + + AIN20 + ADC AIN20 Pin + 0x14 + + + AIN21 + ADC AIN21 Pin + 0x15 + + + AIN22 + ADC AIN22 Pin + 0x16 + + + AIN23 + ADC AIN23 Pin + 0x17 + + + SCALEDCOREVCC + 1/4 Scaled Core Supply + 0x18 + + + SCALEDVBAT + 1/4 Scaled VBAT Supply + 0x19 + + + SCALEDIOVCC + 1/4 Scaled I/O Supply + 0x1A + + + BANDGAP + Bandgap Voltage + 0x1B + + + PTAT + Temperature Sensor TSENSP + 0x1C + + + CTAT + Temperature Sensor TSENSC + 0x1D + + + DAC + DAC Output + 0x1E + + + PTC + PTC output (only on ADC0) + 0x1F + + + + + DIFFMODE + Differential Mode + 7 + 1 + + + MUXNEG + Negative Mux Input Selection + 8 + 5 + + MUXNEGSelect + + AIN0 + ADC AIN0 Pin + 0x0 + + + AIN1 + ADC AIN1 Pin + 0x1 + + + AIN2 + ADC AIN2 Pin + 0x2 + + + AIN3 + ADC AIN3 Pin + 0x3 + + + AIN4 + ADC AIN4 Pin + 0x4 + + + AIN5 + ADC AIN5 Pin + 0x5 + + + AIN6 + ADC AIN6 Pin + 0x6 + + + AIN7 + ADC AIN7 Pin + 0x7 + + + GND + Internal Ground + 0x18 + + + + + DSEQSTOP + Stop DMA Sequencing + 15 + 1 + + + + + CTRLB + Control B + 0x6 + 16 + 0x0000 + + + LEFTADJ + Left-Adjusted Result + 0 + 1 + + + FREERUN + Free Running Mode + 1 + 1 + + + CORREN + Digital Correction Logic Enable + 2 + 1 + + + RESSEL + Conversion Result Resolution + 3 + 2 + + RESSELSelect + + 12BIT + 12-bit result + 0x0 + + + 16BIT + For averaging mode output + 0x1 + + + 10BIT + 10-bit result + 0x2 + + + 8BIT + 8-bit result + 0x3 + + + + + WINMODE + Window Monitor Mode + 8 + 3 + + WINMODESelect + + DISABLE + No window mode (default) + 0 + + + MODE1 + RESULT > WINLT + 1 + + + MODE2 + RESULT < WINUT + 2 + + + MODE3 + WINLT < RESULT < WINUT + 3 + + + MODE4 + !(WINLT < RESULT < WINUT) + 4 + + + + + WINSS + Window Single Sample + 11 + 1 + + + + + REFCTRL + Reference Control + 0x8 + 8 + 0x00 + + + REFSEL + Reference Selection + 0 + 4 + + REFSELSelect + + INTREF + Internal Bandgap Reference + 0x0 + + + INTVCC0 + 1/2 VDDANA + 0x2 + + + INTVCC1 + VDDANA + 0x3 + + + AREFA + External Reference A + 0x4 + + + AREFB + External Reference B + 0x5 + + + AREFC + External Reference C (only on ADC1) + 0x6 + + + + + REFCOMP + Reference Buffer Offset Compensation Enable + 7 + 1 + + + + + AVGCTRL + Average Control + 0xA + 8 + 0x00 + + + SAMPLENUM + Number of Samples to be Collected + 0 + 4 + + SAMPLENUMSelect + + 1 + 1 sample + 0x0 + + + 2 + 2 samples + 0x1 + + + 4 + 4 samples + 0x2 + + + 8 + 8 samples + 0x3 + + + 16 + 16 samples + 0x4 + + + 32 + 32 samples + 0x5 + + + 64 + 64 samples + 0x6 + + + 128 + 128 samples + 0x7 + + + 256 + 256 samples + 0x8 + + + 512 + 512 samples + 0x9 + + + 1024 + 1024 samples + 0xA + + + + + ADJRES + Adjusting Result / Division Coefficient + 4 + 3 + + + + + SAMPCTRL + Sample Time Control + 0xB + 8 + 0x00 + + + SAMPLEN + Sampling Time Length + 0 + 6 + + + OFFCOMP + Comparator Offset Compensation Enable + 7 + 1 + + + + + WINLT + Window Monitor Lower Threshold + 0xC + 16 + 0x0000 + + + WINLT + Window Lower Threshold + 0 + 16 + + + + + WINUT + Window Monitor Upper Threshold + 0xE + 16 + 0x0000 + + + WINUT + Window Upper Threshold + 0 + 16 + + + + + GAINCORR + Gain Correction + 0x10 + 16 + 0x0000 + + + GAINCORR + Gain Correction Value + 0 + 12 + + + + + OFFSETCORR + Offset Correction + 0x12 + 16 + 0x0000 + + + OFFSETCORR + Offset Correction Value + 0 + 12 + + + + + SWTRIG + Software Trigger + 0x14 + 8 + 0x00 + + + FLUSH + ADC Conversion Flush + 0 + 1 + + + START + Start ADC Conversion + 1 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x2C + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Disable + 0 + 1 + + + OVERRUN + Overrun Interrupt Disable + 1 + 1 + + + WINMON + Window Monitor Interrupt Disable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x2D + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x2E + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Flag + 0 + 1 + + + OVERRUN + Overrun Interrupt Flag + 1 + 1 + + + WINMON + Window Monitor Interrupt Flag + 2 + 1 + + + + + STATUS + Status + 0x2F + 8 + read-only + 0x00 + + + ADCBUSY + ADC Busy Status + 0 + 1 + + + WCC + Window Comparator Counter + 2 + 6 + + + + + SYNCBUSY + Synchronization Busy + 0x30 + 32 + read-only + 0x00000000 + + + SWRST + SWRST Synchronization Busy + 0 + 1 + + + ENABLE + ENABLE Synchronization Busy + 1 + 1 + + + INPUTCTRL + Input Control Synchronization Busy + 2 + 1 + + + CTRLB + Control B Synchronization Busy + 3 + 1 + + + REFCTRL + Reference Control Synchronization Busy + 4 + 1 + + + AVGCTRL + Average Control Synchronization Busy + 5 + 1 + + + SAMPCTRL + Sampling Time Control Synchronization Busy + 6 + 1 + + + WINLT + Window Monitor Lower Threshold Synchronization Busy + 7 + 1 + + + WINUT + Window Monitor Upper Threshold Synchronization Busy + 8 + 1 + + + GAINCORR + Gain Correction Synchronization Busy + 9 + 1 + + + OFFSETCORR + Offset Correction Synchronization Busy + 10 + 1 + + + SWTRIG + Software Trigger Synchronization Busy + 11 + 1 + + + + + DSEQDATA + DMA Sequencial Data + 0x34 + 32 + write-only + 0x00000000 + + + DATA + DMA Sequential Data + 0 + 32 + + + + + DSEQCTRL + DMA Sequential Control + 0x38 + 32 + 0x00000000 + + + INPUTCTRL + Input Control + 0 + 1 + + + CTRLB + Control B + 1 + 1 + + + REFCTRL + Reference Control + 2 + 1 + + + AVGCTRL + Average Control + 3 + 1 + + + SAMPCTRL + Sampling Time Control + 4 + 1 + + + WINLT + Window Monitor Lower Threshold + 5 + 1 + + + WINUT + Window Monitor Upper Threshold + 6 + 1 + + + GAINCORR + Gain Correction + 7 + 1 + + + OFFSETCORR + Offset Correction + 8 + 1 + + + AUTOSTART + ADC Auto-Start Conversion + 31 + 1 + + + + + DSEQSTAT + DMA Sequencial Status + 0x3C + 32 + read-only + 0x00000000 + + + INPUTCTRL + Input Control + 0 + 1 + + + CTRLB + Control B + 1 + 1 + + + REFCTRL + Reference Control + 2 + 1 + + + AVGCTRL + Average Control + 3 + 1 + + + SAMPCTRL + Sampling Time Control + 4 + 1 + + + WINLT + Window Monitor Lower Threshold + 5 + 1 + + + WINUT + Window Monitor Upper Threshold + 6 + 1 + + + GAINCORR + Gain Correction + 7 + 1 + + + OFFSETCORR + Offset Correction + 8 + 1 + + + BUSY + DMA Sequencing Busy + 31 + 1 + + + + + RESULT + Result Conversion Value + 0x40 + 16 + read-only + 0x0000 + + + RESULT + Result Conversion Value + 0 + 16 + + + + + RESS + Last Sample Result + 0x44 + 16 + read-only + 0x0000 + + + RESS + Last ADC conversion result + 0 + 16 + + + + + CALIB + Calibration + 0x48 + 16 + 0x0000 + + + BIASCOMP + Bias Comparator Scaling + 0 + 3 + + + BIASR2R + Bias R2R Ampli scaling + 4 + 3 + + + BIASREFBUF + Bias Reference Buffer Scaling + 8 + 3 + + + + + + + ADC1 + 0x43002000 + + ADC1_OTHER + 120 + + + ADC1_RESRDY + 121 + + + + AES + U22382.2.0 + Advanced Encryption Standard + AES + AES_ + 0x42002400 + + 0 + 0x88 + registers + + + AES + 130 + + + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + AESMODE + AES Modes of operation + 2 + 3 + + AESMODESelect + + ECB + Electronic code book mode + 0x0 + + + CBC + Cipher block chaining mode + 0x1 + + + OFB + Output feedback mode + 0x2 + + + CFB + Cipher feedback mode + 0x3 + + + COUNTER + Counter mode + 0x4 + + + CCM + CCM mode + 0x5 + + + GCM + Galois counter mode + 0x6 + + + + + CFBS + Cipher Feedback Block Size + 5 + 3 + + CFBSSelect + + 128BIT + 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode + 0x0 + + + 64BIT + 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode + 0x1 + + + 32BIT + 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode + 0x2 + + + 16BIT + 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode + 0x3 + + + 8BIT + 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode + 0x4 + + + + + KEYSIZE + Encryption Key Size + 8 + 2 + + KEYSIZESelect + + 128BIT + 128-bit Key for Encryption / Decryption + 0x0 + + + 192BIT + 192-bit Key for Encryption / Decryption + 0x1 + + + 256BIT + 256-bit Key for Encryption / Decryption + 0x2 + + + + + CIPHER + Cipher Mode + 10 + 1 + + CIPHERSelect + + DEC + Decryption + 0x0 + + + ENC + Encryption + 0x1 + + + + + STARTMODE + Start Mode Select + 11 + 1 + + STARTMODESelect + + MANUAL + Start Encryption / Decryption in Manual mode + 0x0 + + + AUTO + Start Encryption / Decryption in Auto mode + 0x1 + + + + + LOD + Last Output Data Mode + 12 + 1 + + LODSelect + + NONE + No effect + 0x0 + + + LAST + Start encryption in Last Output Data mode + 0x1 + + + + + KEYGEN + Last Key Generation + 13 + 1 + + KEYGENSelect + + NONE + No effect + 0x0 + + + LAST + Start Computation of the last NK words of the expanded key + 0x1 + + + + + XORKEY + XOR Key Operation + 14 + 1 + + XORKEYSelect + + NONE + No effect + 0x0 + + + XOR + The user keyword gets XORed with the previous keyword register content. + 0x1 + + + + + CTYPE + Counter Measure Type + 16 + 4 + + + + + CTRLB + Control B + 0x4 + 8 + 0x00 + + + START + Start Encryption/Decryption + 0 + 1 + + + NEWMSG + New message + 1 + 1 + + + EOM + End of message + 2 + 1 + + + GFMUL + GF Multiplication + 3 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x5 + 8 + 0x00 + + + ENCCMP + Encryption Complete Interrupt Enable + 0 + 1 + + + GFMCMP + GF Multiplication Complete Interrupt Enable + 1 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x6 + 8 + 0x00 + + + ENCCMP + Encryption Complete Interrupt Enable + 0 + 1 + + + GFMCMP + GF Multiplication Complete Interrupt Enable + 1 + 1 + + + + + INTFLAG + Interrupt Flag Status + 0x7 + 8 + 0x00 + + + ENCCMP + Encryption Complete + 0 + 1 + + + GFMCMP + GF Multiplication Complete + 1 + 1 + + + + + DATABUFPTR + Data buffer pointer + 0x8 + 8 + 0x00 + + + INDATAPTR + Input Data Pointer + 0 + 2 + + + + + DBGCTRL + Debug control + 0x9 + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + 8 + 4 + KEYWORD[%s] + Keyword n + 0xC + 32 + write-only + 0x00000000 + + + INDATA + Indata + 0x38 + 32 + 0x00000000 + + + 4 + 4 + INTVECTV[%s] + Initialisation Vector n + 0x3C + 32 + write-only + 0x00000000 + + + 4 + 4 + HASHKEY[%s] + Hash key n + 0x5C + 32 + 0x00000000 + + + 4 + 4 + GHASH[%s] + Galois Hash n + 0x6C + 32 + 0x00000000 + + + CIPLEN + Cipher Length + 0x80 + 32 + 0x00000000 + + + RANDSEED + Random Seed + 0x84 + 32 + 0x00000000 + + + + + CAN0 + U20033.2.1 + Control Area Network + CAN + CAN_ + 0x42000000 + + 0 + 0xFC + registers + + + CAN0 + 78 + + + + CREL + Core Release + 0x0 + 32 + read-only + 0x32100000 + + + SUBSTEP + Sub-step of Core Release + 20 + 4 + + + STEP + Step of Core Release + 24 + 4 + + + REL + Core Release + 28 + 4 + + + + + ENDN + Endian + 0x4 + 32 + read-only + 0x87654321 + + + ETV + Endianness Test Value + 0 + 32 + + + + + MRCFG + Message RAM Configuration + 0x8 + 32 + 0x00000002 + + + QOS + Quality of Service + 0 + 2 + + QOSSelect + + DISABLE + Background (no sensitive operation) + 0 + + + LOW + Sensitive Bandwidth + 1 + + + MEDIUM + Sensitive Latency + 2 + + + HIGH + Critical Latency + 3 + + + + + + + DBTP + Fast Bit Timing and Prescaler + 0xC + 32 + 0x00000A33 + + + DSJW + Data (Re)Synchronization Jump Width + 0 + 4 + + + DTSEG2 + Data time segment after sample point + 4 + 4 + + + DTSEG1 + Data time segment before sample point + 8 + 5 + + + DBRP + Data Baud Rate Prescaler + 16 + 5 + + + TDC + Tranceiver Delay Compensation + 23 + 1 + + + + + TEST + Test + 0x10 + 32 + 0x00000000 + + + LBCK + Loop Back Mode + 4 + 1 + + + TX + Control of Transmit Pin + 5 + 2 + + TXSelect + + CORE + TX controlled by CAN core + 0 + + + SAMPLE + TX monitoring sample point + 1 + + + DOMINANT + Dominant (0) level at pin CAN_TX + 2 + + + RECESSIVE + Recessive (1) level at pin CAN_TX + 3 + + + + + RX + Receive Pin + 7 + 1 + + + + + RWD + RAM Watchdog + 0x14 + 32 + 0x00000000 + + + WDC + Watchdog Configuration + 0 + 8 + + + WDV + Watchdog Value + 8 + 8 + + + + + CCCR + CC Control + 0x18 + 32 + 0x00000001 + + + INIT + Initialization + 0 + 1 + + + CCE + Configuration Change Enable + 1 + 1 + + + ASM + ASM Restricted Operation Mode + 2 + 1 + + + CSA + Clock Stop Acknowledge + 3 + 1 + + + CSR + Clock Stop Request + 4 + 1 + + + MON + Bus Monitoring Mode + 5 + 1 + + + DAR + Disable Automatic Retransmission + 6 + 1 + + + TEST + Test Mode Enable + 7 + 1 + + + FDOE + FD Operation Enable + 8 + 1 + + + BRSE + Bit Rate Switch Enable + 9 + 1 + + + PXHD + Protocol Exception Handling Disable + 12 + 1 + + + EFBI + Edge Filtering during Bus Integration + 13 + 1 + + + TXP + Transmit Pause + 14 + 1 + + + NISO + Non ISO Operation + 15 + 1 + + + + + NBTP + Nominal Bit Timing and Prescaler + 0x1C + 32 + 0x06000A03 + + + NTSEG2 + Nominal Time segment after sample point + 0 + 7 + + + NTSEG1 + Nominal Time segment before sample point + 8 + 8 + + + NBRP + Nominal Baud Rate Prescaler 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2 + + + TRANSACTION + One trigger required for each transaction + 3 + + + + + BURSTLEN + Burst Length + 24 + 4 + + BURSTLENSelect + + SINGLE + Single-beat burst length + 0 + + + 2BEAT + 2-beats burst length + 1 + + + 3BEAT + 3-beats burst length + 2 + + + 4BEAT + 4-beats burst length + 3 + + + 5BEAT + 5-beats burst length + 4 + + + 6BEAT + 6-beats burst length + 5 + + + 7BEAT + 7-beats burst length + 6 + + + 8BEAT + 8-beats burst length + 7 + + + 9BEAT + 9-beats burst length + 8 + + + 10BEAT + 10-beats burst length + 9 + + + 11BEAT + 11-beats burst length + 10 + + + 12BEAT + 12-beats burst length + 11 + + + 13BEAT + 13-beats burst length + 12 + + + 14BEAT + 14-beats burst length + 13 + + + 15BEAT + 15-beats burst length + 14 + + + 16BEAT + 16-beats burst length + 15 + + + + + THRESHOLD + FIFO Threshold + 28 + 2 + + THRESHOLDSelect + + 1BEAT + Destination write starts after each beat source address read + 0 + + + 2BEATS + Destination write starts after 2-beats source address read + 1 + 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Channel 17 Software Selection + 17 + 1 + + + CHANNEL18 + Channel 18 Software Selection + 18 + 1 + + + CHANNEL19 + Channel 19 Software Selection + 19 + 1 + + + CHANNEL20 + Channel 20 Software Selection + 20 + 1 + + + CHANNEL21 + Channel 21 Software Selection + 21 + 1 + + + CHANNEL22 + Channel 22 Software Selection + 22 + 1 + + + CHANNEL23 + Channel 23 Software Selection + 23 + 1 + + + CHANNEL24 + Channel 24 Software Selection + 24 + 1 + + + CHANNEL25 + Channel 25 Software Selection + 25 + 1 + + + CHANNEL26 + Channel 26 Software Selection + 26 + 1 + + + CHANNEL27 + Channel 27 Software Selection + 27 + 1 + + + CHANNEL28 + Channel 28 Software Selection + 28 + 1 + + + CHANNEL29 + Channel 29 Software Selection + 29 + 1 + + + CHANNEL30 + Channel 30 Software Selection + 30 + 1 + + + CHANNEL31 + Channel 31 Software Selection + 31 + 1 + + + + + PRICTRL + Priority Control + 0x8 + 8 + 0x00 + + + PRI + Channel Priority Number + 0 + 4 + + + RREN + Round-Robin Scheduling Enable + 7 + 1 + + + + + INTPEND + Channel Pending Interrupt + 0x10 + 16 + 0x4000 + + + ID + Channel ID + 0 + 4 + + + OVR + Channel Overrun + 8 + 1 + + + EVD + Channel Event Detected + 9 + 1 + + + READY + Ready + 14 + 1 + + + BUSY + Busy + 15 + 1 + + + + + INTSTATUS + Interrupt Status + 0x14 + 32 + read-only + 0x00000000 + + + CHINT0 + Channel 0 Pending Interrupt + 0 + 1 + + + CHINT1 + Channel 1 Pending Interrupt + 1 + 1 + + + CHINT2 + Channel 2 Pending Interrupt + 2 + 1 + + + CHINT3 + Channel 3 Pending Interrupt + 3 + 1 + + + CHINT4 + Channel 4 Pending Interrupt + 4 + 1 + + + CHINT5 + Channel 5 Pending Interrupt + 5 + 1 + + + CHINT6 + Channel 6 Pending Interrupt + 6 + 1 + + + CHINT7 + Channel 7 Pending Interrupt + 7 + 1 + + + CHINT8 + Channel 8 Pending Interrupt + 8 + 1 + + + CHINT9 + Channel 9 Pending Interrupt + 9 + 1 + + + CHINT10 + Channel 10 Pending Interrupt + 10 + 1 + + + CHINT11 + Channel 11 Pending Interrupt + 11 + 1 + + + + + BUSYCH + Busy Channels + 0x18 + 32 + read-only + 0x00000000 + + + BUSYCH0 + Busy Channel 0 + 0 + 1 + + + BUSYCH1 + Busy Channel 1 + 1 + 1 + + + BUSYCH2 + Busy Channel 2 + 2 + 1 + + + BUSYCH3 + Busy Channel 3 + 3 + 1 + + + BUSYCH4 + Busy Channel 4 + 4 + 1 + + + BUSYCH5 + Busy Channel 5 + 5 + 1 + + + BUSYCH6 + Busy Channel 6 + 6 + 1 + + + BUSYCH7 + Busy Channel 7 + 7 + 1 + + + BUSYCH8 + Busy Channel 8 + 8 + 1 + + + BUSYCH9 + Busy Channel 9 + 9 + 1 + + + BUSYCH10 + Busy Channel 10 + 10 + 1 + + + BUSYCH11 + Busy Channel 11 + 11 + 1 + + + + + READYUSR + Ready Users + 0x1C + 32 + read-only + 0xFFFFFFFF + + + READYUSR0 + Ready User for Channel 0 + 0 + 1 + + + READYUSR1 + Ready User for Channel 1 + 1 + 1 + + + READYUSR2 + Ready User for Channel 2 + 2 + 1 + + + READYUSR3 + Ready User for Channel 3 + 3 + 1 + + + READYUSR4 + Ready User for Channel 4 + 4 + 1 + + + READYUSR5 + Ready User for Channel 5 + 5 + 1 + + + READYUSR6 + Ready User for Channel 6 + 6 + 1 + + + READYUSR7 + Ready User for Channel 7 + 7 + 1 + + + READYUSR8 + Ready User for Channel 8 + 8 + 1 + + + READYUSR9 + Ready User for Channel 9 + 9 + 1 + + + READYUSR10 + Ready User for Channel 10 + 10 + 1 + + + READYUSR11 + Ready User for Channel 11 + 11 + 1 + + + + + 32 + 0x8 + CHANNEL[%s] + + 0x020 + + CHANNEL + Channel n Control + 0x0 + 32 + 0x00008000 + + + EVGEN + Event Generator Selection + 0 + 7 + + + PATH + Path Selection + 8 + 2 + + PATHSelect + + SYNCHRONOUS + Synchronous path + 0 + + + RESYNCHRONIZED + Resynchronized path + 1 + + + ASYNCHRONOUS + Asynchronous path + 2 + + + + + EDGSEL + Edge Detection Selection + 10 + 2 + + EDGSELSelect + + NO_EVT_OUTPUT + No event output when using the resynchronized or synchronous path + 0 + + + RISING_EDGE + Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path + 1 + + + FALLING_EDGE + Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path + 2 + + + BOTH_EDGES + Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path + 3 + + + + + RUNSTDBY + Run in standby + 14 + 1 + + + ONDEMAND + Generic Clock On Demand + 15 + 1 + + + + + CHINTENCLR + Channel n Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + OVR + Channel Overrun Interrupt Disable + 0 + 1 + + + EVD + Channel Event Detected Interrupt Disable + 1 + 1 + + + + + CHINTENSET + Channel n Interrupt Enable Set + 0x5 + 8 + 0x00 + + + OVR + Channel Overrun Interrupt Enable + 0 + 1 + + + EVD + Channel Event Detected Interrupt Enable + 1 + 1 + + + + + CHINTFLAG + Channel n Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + OVR + Channel Overrun + 0 + 1 + + + EVD + Channel Event Detected + 1 + 1 + + + + + CHSTATUS + Channel n Status + 0x7 + 8 + read-only + 0x01 + + + RDYUSR + Ready User + 0 + 1 + + + BUSYCH + Busy Channel + 1 + 1 + + + + + + 67 + 4 + USER[%s] + User Multiplexer n + 0x120 + 32 + 0x00000000 + + + CHANNEL + Channel Event Selection + 0 + 6 + + + + + + + FREQM + U22571.1.0 + Frequency Meter + FREQM + FREQM_ + 0x40002C00 + + 0 + 0x14 + registers + + + FREQM + 28 + + + + CTRLA + Control A Register + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + CTRLB + Control B Register + 0x1 + 8 + write-only + 0x00 + + + START + Start Measurement + 0 + 1 + + + + + CFGA + Config A register + 0x2 + 16 + 0x0000 + + + REFNUM + Number of Reference Clock Cycles + 0 + 8 + + + + + INTENCLR + Interrupt Enable Clear Register + 0x8 + 8 + 0x00 + + + DONE + Measurement Done Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set Register + 0x9 + 8 + 0x00 + + + DONE + Measurement Done Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Register + 0xA + 8 + 0x00 + + + DONE + Measurement Done + 0 + 1 + + + + + STATUS + Status Register + 0xB + 8 + 0x00 + + + BUSY + FREQM Status + 0 + 1 + + + OVF + Sticky Count Value Overflow + 1 + 1 + + + + + SYNCBUSY + Synchronization Busy Register + 0xC + 32 + read-only + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + VALUE + Count Value Register + 0x10 + 32 + read-only + 0x00000000 + + + VALUE + Measurement Value + 0 + 24 + + + + + + + GCLK + U21221.2.0 + Generic Clock Generator + GCLK + GCLK_ + 0x40001C00 + + 0 + 0x1A0 + registers + + + + CTRLA + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x4 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchroniation Busy bit + 0 + 1 + + + GENCTRL + Generic Clock Generator Control n Synchronization Busy bits + 2 + 12 + + GENCTRLSelect + + GCLK0 + Generic clock generator 0 + 0x0001 + + + GCLK1 + Generic clock generator 1 + 0x0002 + + + GCLK2 + Generic clock generator 2 + 0x0004 + + + GCLK3 + Generic clock generator 3 + 0x0008 + + + GCLK4 + Generic clock generator 4 + 0x0010 + + + GCLK5 + Generic clock generator 5 + 0x0020 + + + GCLK6 + Generic clock generator 6 + 0x0040 + + + GCLK7 + Generic clock generator 7 + 0x0080 + + + GCLK8 + Generic clock generator 8 + 0x0100 + + + GCLK9 + Generic clock generator 9 + 0x0200 + + + GCLK10 + Generic clock generator 10 + 0x0400 + + + GCLK11 + Generic clock generator 11 + 0x0800 + + + + + + + 12 + 4 + GENCTRL[%s] + Generic Clock Generator Control + 0x20 + 32 + 0x00000000 + + + SRC + Source Select + 0 + 4 + + SRCSelect + + XOSC0 + XOSC0 oscillator output + 0 + + + XOSC1 + XOSC1 oscillator output + 1 + + + GCLKIN + Generator input pad + 2 + + + GCLKGEN1 + Generic clock generator 1 output + 3 + + + OSCULP32K + OSCULP32K oscillator output + 4 + + + XOSC32K + XOSC32K oscillator output + 5 + + + DFLL + DFLL output + 6 + + + DPLL0 + DPLL0 output + 7 + + + DPLL1 + DPLL1 output + 8 + + + + + GENEN + Generic Clock Generator Enable + 8 + 1 + + + IDC + Improve Duty Cycle + 9 + 1 + + + OOV + Output Off Value + 10 + 1 + + + OE + Output Enable + 11 + 1 + + + DIVSEL + Divide Selection + 12 + 1 + + DIVSELSelect + + DIV1 + Divide input directly by divider factor + 0x0 + + + DIV2 + Divide input by 2^(divider factor+ 1) + 0x1 + + + + + RUNSTDBY + Run in Standby + 13 + 1 + + + DIV + Division Factor + 16 + 16 + + + + + 48 + 4 + PCHCTRL[%s] + Peripheral Clock Control + 0x80 + 32 + 0x00000000 + + + GEN + Generic Clock Generator + 0 + 4 + + GENSelect + + GCLK0 + Generic clock generator 0 + 0x0 + + + GCLK1 + Generic clock generator 1 + 0x1 + + + GCLK2 + Generic clock generator 2 + 0x2 + + + GCLK3 + Generic clock generator 3 + 0x3 + + + GCLK4 + Generic clock generator 4 + 0x4 + + + GCLK5 + Generic clock generator 5 + 0x5 + + + GCLK6 + Generic clock generator 6 + 0x6 + + + GCLK7 + Generic clock generator 7 + 0x7 + + + GCLK8 + Generic clock generator 8 + 0x8 + + + GCLK9 + Generic clock generator 9 + 0x9 + + + GCLK10 + Generic clock generator 10 + 0xA + + + GCLK11 + Generic clock generator 11 + 0xB + + + + + CHEN + Channel Enable + 6 + 1 + + + WRTLOCK + Write Lock + 7 + 1 + + + + + + + HMATRIX + I76382.1.4 + HSB Matrix + HMATRIXB + HMATRIXB_ + 0x4100C000 + + 0 + 0xB0 + registers + + + + 16 + 0x8 + PRS[%s] + + 0x080 + + PRAS + Priority A for Slave + 0x0 + 32 + 0x00000000 + + + PRBS + Priority B for Slave + 0x4 + 32 + 0x00000000 + + + + + + ICM + U20101.2.0 + Integrity Check Monitor + ICM + ICM_ + 0x42002C00 + + 0 + 0x58 + registers + + + ICM + 132 + + + + CFG + Configuration + 0x0 + 32 + 0x00000000 + + + WBDIS + Write Back Disable + 0 + 1 + + + EOMDIS + End of Monitoring Disable + 1 + 1 + + + SLBDIS + Secondary List Branching Disable + 2 + 1 + + + BBC + Bus Burden Control + 4 + 4 + + + ASCD + Automatic Switch To Compare Digest + 8 + 1 + + + DUALBUFF + Dual Input Buffer + 9 + 1 + + + UIHASH + User Initial Hash Value + 12 + 1 + + + UALGO + User SHA Algorithm + 13 + 3 + + UALGOSelect + + SHA1 + SHA1 Algorithm + 0x0 + + + SHA256 + SHA256 Algorithm + 0x1 + + + SHA224 + SHA224 Algorithm + 0x4 + + + + + HAPROT + Region Hash Area Protection + 16 + 6 + + + DAPROT + Region Descriptor Area Protection + 24 + 6 + + + + + CTRL + Control + 0x4 + 32 + write-only + + + ENABLE + ICM Enable + 0 + 1 + + + DISABLE + ICM Disable Register + 1 + 1 + + + SWRST + Software Reset + 2 + 1 + + + REHASH + Recompute Internal Hash + 4 + 4 + + + RMDIS + Region Monitoring Disable + 8 + 4 + + + RMEN + Region Monitoring Enable + 12 + 4 + + + + + SR + Status + 0x8 + 32 + read-only + 0x00000000 + + + ENABLE + ICM Controller Enable Register + 0 + 1 + + + RAWRMDIS + RAW Region Monitoring Disabled Status + 8 + 4 + + + RMDIS + Region Monitoring Disabled Status + 12 + 4 + + + + + IER + Interrupt Enable + 0x10 + 32 + write-only + + + RHC + Region Hash Completed Interrupt Enable + 0 + 4 + + + RDM + Region Digest Mismatch Interrupt Enable + 4 + 4 + + + RBE + Region Bus Error Interrupt Enable + 8 + 4 + + + RWC + Region Wrap Condition detected Interrupt Enable + 12 + 4 + + + REC + Region End bit Condition Detected Interrupt Enable + 16 + 4 + + + RSU + Region Status Updated Interrupt Disable + 20 + 4 + + + URAD + Undefined Register Access Detection Interrupt Enable + 24 + 1 + + + + + IDR + Interrupt Disable + 0x14 + 32 + write-only + 0x00000000 + + + RHC + Region Hash Completed Interrupt Disable + 0 + 4 + + + RDM + Region Digest Mismatch Interrupt Disable + 4 + 4 + + + RBE + Region Bus Error Interrupt Disable + 8 + 4 + + + RWC + Region Wrap Condition Detected Interrupt Disable + 12 + 4 + + + REC + Region End bit Condition detected Interrupt Disable + 16 + 4 + + + RSU + Region Status Updated Interrupt Disable + 20 + 4 + + + URAD + Undefined Register Access Detection Interrupt Disable + 24 + 1 + + + + + IMR + Interrupt Mask + 0x18 + 32 + read-only + 0x00000000 + + + RHC + Region Hash Completed Interrupt Mask + 0 + 4 + + + RDM + Region Digest Mismatch Interrupt Mask + 4 + 4 + + + RBE + Region Bus Error Interrupt Mask + 8 + 4 + + + RWC + Region Wrap Condition Detected Interrupt Mask + 12 + 4 + + + REC + Region End bit Condition Detected Interrupt Mask + 16 + 4 + + + RSU + Region Status Updated Interrupt Mask + 20 + 4 + + + URAD + Undefined Register Access Detection Interrupt Mask + 24 + 1 + + + + + ISR + Interrupt Status + 0x1C + 32 + read-only + 0x00000000 + + + RHC + Region Hash Completed + 0 + 4 + + + RDM + Region Digest Mismatch + 4 + 4 + + + RBE + Region Bus Error + 8 + 4 + + + RWC + Region Wrap Condition Detected + 12 + 4 + + + REC + Region End bit Condition Detected + 16 + 4 + + + RSU + Region Status Updated Detected + 20 + 4 + + + URAD + Undefined Register Access Detection Status + 24 + 1 + + + + + UASR + Undefined Access Status + 0x20 + 32 + read-only + 0x00000000 + + + URAT + Undefined Register Access Trace + 0 + 3 + + URATSelect + + UNSPEC_STRUCT_MEMBER + Unspecified structure member set to one detected when the descriptor is loaded + 0x0 + + + CFG_MODIFIED + CFG modified during active monitoring + 0x1 + + + DSCR_MODIFIED + DSCR modified during active monitoring + 0x2 + + + HASH_MODIFIED + HASH modified during active monitoring + 0x3 + + + READ_ACCESS + Write-only register read access + 0x4 + + + + + + + DSCR + Region Descriptor Area Start Address + 0x30 + 32 + 0x00000000 + + + DASA + Descriptor Area Start Address + 6 + 26 + + + + + HASH + Region Hash Area Start Address + 0x34 + 32 + 0x00000000 + + + HASA + Hash Area Start Address + 7 + 25 + + + + + 8 + 4 + UIHVAL[%s] + User Initial Hash Value n + 0x38 + 32 + write-only + 0x00000000 + + + VAL + Initial Hash Value + 0 + 32 + + + + + + + I2S + U22242.0.0 + Inter-IC Sound Interface + I2S + I2S_ + 0x43002800 + + 0 + 0x38 + registers + + + I2S + 128 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + CKEN0 + Clock Unit 0 Enable + 2 + 1 + + + CKEN1 + Clock Unit 1 Enable + 3 + 1 + + + TXEN + Tx Serializer Enable + 4 + 1 + + + RXEN + Rx Serializer Enable + 5 + 1 + + + + + 2 + 4 + CLKCTRL[%s] + Clock Unit n Control + 0x4 + 32 + 0x00000000 + + + SLOTSIZE + Slot Size + 0 + 2 + + SLOTSIZESelect + + 8 + 8-bit Slot for Clock Unit n + 0x0 + + + 16 + 16-bit Slot for Clock Unit n + 0x1 + + + 24 + 24-bit Slot for Clock Unit n + 0x2 + + + 32 + 32-bit Slot for Clock Unit n + 0x3 + + + + + NBSLOTS + Number of Slots in Frame + 2 + 3 + + + FSWIDTH + Frame Sync Width + 5 + 2 + + FSWIDTHSelect + + SLOT + Frame Sync Pulse is 1 Slot wide (default for I2S protocol) + 0x0 + + + HALF + Frame Sync Pulse is half a Frame wide + 0x1 + + + BIT + Frame Sync Pulse is 1 Bit wide + 0x2 + + + BURST + Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested + 0x3 + + + + + BITDELAY + Data Delay from Frame Sync + 7 + 1 + + BITDELAYSelect + + LJ + Left Justified (0 Bit Delay) + 0x0 + + + I2S + I2S (1 Bit Delay) + 0x1 + + + + + FSSEL + Frame Sync Select + 8 + 1 + + FSSELSelect + + SCKDIV + Divided Serial Clock n is used as Frame Sync n source + 0x0 + + + FSPIN + FSn input pin is used as Frame Sync n source + 0x1 + + + + + FSINV + Frame Sync Invert + 9 + 1 + + + FSOUTINV + Frame Sync Output Invert + 10 + 1 + + + SCKSEL + Serial Clock Select + 11 + 1 + + SCKSELSelect + + MCKDIV + Divided Master Clock n is used as Serial Clock n source + 0x0 + + + SCKPIN + SCKn input pin is used as Serial Clock n source + 0x1 + + + + + SCKOUTINV + Serial Clock Output Invert + 12 + 1 + + + MCKSEL + Master Clock Select + 13 + 1 + + MCKSELSelect + + GCLK + GCLK_I2S_n is used as Master Clock n source + 0x0 + + + MCKPIN + MCKn input pin is used as Master Clock n source + 0x1 + + + + + MCKEN + Master Clock Enable + 14 + 1 + + + MCKOUTINV + Master Clock Output Invert + 15 + 1 + + + MCKDIV + Master Clock Division Factor + 16 + 6 + + + MCKOUTDIV + Master Clock Output Division Factor + 24 + 6 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 Interrupt Enable + 0 + 1 + + + RXRDY1 + Receive Ready 1 Interrupt Enable + 1 + 1 + + + RXOR0 + Receive Overrun 0 Interrupt Enable + 4 + 1 + + + RXOR1 + Receive Overrun 1 Interrupt Enable + 5 + 1 + + + TXRDY0 + Transmit Ready 0 Interrupt Enable + 8 + 1 + + + TXRDY1 + Transmit Ready 1 Interrupt Enable + 9 + 1 + + + TXUR0 + Transmit Underrun 0 Interrupt Enable + 12 + 1 + + + TXUR1 + Transmit Underrun 1 Interrupt Enable + 13 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 Interrupt Enable + 0 + 1 + + + RXRDY1 + Receive Ready 1 Interrupt Enable + 1 + 1 + + + RXOR0 + Receive Overrun 0 Interrupt Enable + 4 + 1 + + + RXOR1 + Receive Overrun 1 Interrupt Enable + 5 + 1 + + + TXRDY0 + Transmit Ready 0 Interrupt Enable + 8 + 1 + + + TXRDY1 + Transmit Ready 1 Interrupt Enable + 9 + 1 + + + TXUR0 + Transmit Underrun 0 Interrupt Enable + 12 + 1 + + + TXUR1 + Transmit Underrun 1 Interrupt Enable + 13 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 + 0 + 1 + + + RXRDY1 + Receive Ready 1 + 1 + 1 + + + RXOR0 + Receive Overrun 0 + 4 + 1 + + + RXOR1 + Receive Overrun 1 + 5 + 1 + + + TXRDY0 + Transmit Ready 0 + 8 + 1 + + + TXRDY1 + Transmit Ready 1 + 9 + 1 + + + TXUR0 + Transmit Underrun 0 + 12 + 1 + + + TXUR1 + Transmit Underrun 1 + 13 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x18 + 16 + read-only + 0x0000 + + + SWRST + Software Reset Synchronization Status + 0 + 1 + + + ENABLE + Enable Synchronization Status + 1 + 1 + + + CKEN0 + Clock Unit 0 Enable Synchronization Status + 2 + 1 + + + CKEN1 + Clock Unit 1 Enable Synchronization Status + 3 + 1 + + + TXEN + Tx Serializer Enable Synchronization Status + 4 + 1 + + + RXEN + Rx Serializer Enable Synchronization Status + 5 + 1 + + + TXDATA + Tx Data Synchronization Status + 8 + 1 + + + RXDATA + Rx Data Synchronization Status + 9 + 1 + + + + + TXCTRL + Tx Serializer Control + 0x20 + 32 + 0x00000000 + + + SERMODE + Serializer Mode + 0 + 2 + + SERMODESelect + + RX + Receive + 0x0 + + + TX + Transmit + 0x1 + + + PDM2 + Receive one PDM data on each serial clock edge + 0x2 + + + + + TXDEFAULT + Line Default Line when Slot Disabled + 2 + 2 + + TXDEFAULTSelect + + ZERO + Output Default Value is 0 + 0x0 + + + ONE + Output Default Value is 1 + 0x1 + + + HIZ + Output Default Value is high impedance + 0x3 + + + + + TXSAME + Transmit Data when Underrun + 4 + 1 + + TXSAMESelect + + ZERO + Zero data transmitted in case of underrun + 0x0 + + + SAME + Last data transmitted in case of underrun + 0x1 + + + + + CLKSEL + Clock Unit Selection + 5 + 1 + + CLKSELSelect + + CLK0 + Use Clock Unit 0 + 0x0 + + + CLK1 + Use Clock Unit 1 + 0x1 + + + + + SLOTADJ + Data Slot Formatting Adjust + 7 + 1 + + SLOTADJSelect + + RIGHT + Data is right adjusted in slot + 0x0 + + + LEFT + Data is left adjusted in slot + 0x1 + + + + + DATASIZE + Data Word Size + 8 + 3 + + DATASIZESelect + + 32 + 32 bits + 0x0 + + + 24 + 24 bits + 0x1 + + + 20 + 20 bits + 0x2 + + + 18 + 18 bits + 0x3 + + + 16 + 16 bits + 0x4 + + + 16C + 16 bits compact stereo + 0x5 + + + 8 + 8 bits + 0x6 + + + 8C + 8 bits compact stereo + 0x7 + + + + + WORDADJ + Data Word Formatting Adjust + 12 + 1 + + WORDADJSelect + + RIGHT + Data is right adjusted in word + 0x0 + + + LEFT + Data is left adjusted in word + 0x1 + + + + + EXTEND + Data Formatting Bit Extension + 13 + 2 + + EXTENDSelect + + ZERO + Extend with zeroes + 0x0 + + + ONE + Extend with ones + 0x1 + + + MSBIT + Extend with Most Significant Bit + 0x2 + + + LSBIT + Extend with Least Significant Bit + 0x3 + + + + + BITREV + Data Formatting Bit Reverse + 15 + 1 + + BITREVSelect + + MSBIT + Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) + 0x0 + + + LSBIT + Transfer Data Least Significant Bit (LSB) first + 0x1 + + + + + SLOTDIS0 + Slot 0 Disabled for this Serializer + 16 + 1 + + + SLOTDIS1 + Slot 1 Disabled for this Serializer + 17 + 1 + + + SLOTDIS2 + Slot 2 Disabled for this Serializer + 18 + 1 + + + SLOTDIS3 + Slot 3 Disabled for this Serializer + 19 + 1 + + + SLOTDIS4 + Slot 4 Disabled for this Serializer + 20 + 1 + + + SLOTDIS5 + Slot 5 Disabled for this Serializer + 21 + 1 + + + SLOTDIS6 + Slot 6 Disabled for this Serializer + 22 + 1 + + + SLOTDIS7 + Slot 7 Disabled for this Serializer + 23 + 1 + + + MONO + Mono Mode + 24 + 1 + + MONOSelect + + STEREO + Normal mode + 0x0 + + + MONO + Left channel data is duplicated to right channel + 0x1 + + + + + DMA + Single or Multiple DMA Channels + 25 + 1 + + DMASelect + + SINGLE + Single DMA channel + 0x0 + + + MULTIPLE + One DMA channel per data channel + 0x1 + + + + + + + RXCTRL + Rx Serializer Control + 0x24 + 32 + 0x00000000 + + + SERMODE + Serializer Mode + 0 + 2 + + SERMODESelect + + RX + Receive + 0x0 + + + PDM2 + Receive one PDM data on each serial clock edge + 0x2 + + + + + CLKSEL + Clock Unit Selection + 5 + 1 + + CLKSELSelect + + CLK0 + Use Clock Unit 0 + 0x0 + + + CLK1 + Use Clock Unit 1 + 0x1 + + + + + SLOTADJ + Data Slot Formatting Adjust + 7 + 1 + + SLOTADJSelect + + RIGHT + Data is right adjusted in slot + 0x0 + + + LEFT + Data is left adjusted in slot + 0x1 + + + + + DATASIZE + Data Word Size + 8 + 3 + + DATASIZESelect + + 32 + 32 bits + 0x0 + + + 24 + 24 bits + 0x1 + + + 20 + 20 bits + 0x2 + + + 18 + 18 bits + 0x3 + + + 16 + 16 bits + 0x4 + + + 16C + 16 bits compact stereo + 0x5 + + + 8 + 8 bits + 0x6 + + + 8C + 8 bits compact stereo + 0x7 + + + + + WORDADJ + Data Word Formatting Adjust + 12 + 1 + + WORDADJSelect + + RIGHT + Data is right adjusted in word + 0x0 + + + LEFT + Data is left adjusted in word + 0x1 + + + + + EXTEND + Data Formatting Bit Extension + 13 + 2 + + EXTENDSelect + + ZERO + Extend with zeroes + 0x0 + + + ONE + Extend with ones + 0x1 + + + MSBIT + Extend with Most Significant Bit + 0x2 + + + LSBIT + Extend with Least Significant Bit + 0x3 + + + + + BITREV + Data Formatting Bit Reverse + 15 + 1 + + BITREVSelect + + MSBIT + Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) + 0x0 + + + LSBIT + Transfer Data Least Significant Bit (LSB) first + 0x1 + + + + + SLOTDIS0 + Slot 0 Disabled for this Serializer + 16 + 1 + + + SLOTDIS1 + Slot 1 Disabled for this Serializer + 17 + 1 + + + SLOTDIS2 + Slot 2 Disabled for this Serializer + 18 + 1 + + + SLOTDIS3 + Slot 3 Disabled for this Serializer + 19 + 1 + + + SLOTDIS4 + Slot 4 Disabled for this Serializer + 20 + 1 + + + SLOTDIS5 + Slot 5 Disabled for this Serializer + 21 + 1 + + + SLOTDIS6 + Slot 6 Disabled for this Serializer + 22 + 1 + + + SLOTDIS7 + Slot 7 Disabled for this Serializer + 23 + 1 + + + MONO + Mono Mode + 24 + 1 + + MONOSelect + + STEREO + Normal mode + 0x0 + + + MONO + Left channel data is duplicated to right channel + 0x1 + + + + + DMA + Single or Multiple DMA Channels + 25 + 1 + + DMASelect + + SINGLE + Single DMA channel + 0x0 + + + MULTIPLE + One DMA channel per data channel + 0x1 + + + + + RXLOOP + Loop-back Test Mode + 26 + 1 + + + + + TXDATA + Tx Data + 0x30 + 32 + write-only + 0x00000000 + + + DATA + Sample Data + 0 + 32 + + + + + RXDATA + Rx Data + 0x34 + 32 + read-only + 0x00000000 + + + DATA + Sample Data + 0 + 32 + + + + + + + MCLK + U24081.0.0 + Main Clock + MCLK + MCLK_ + 0x40000800 + + 0 + 0x24 + registers + + + MCLK + 1 + + + + INTENCLR + Interrupt Enable Clear + 0x1 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x2 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x3 + 8 + 0x01 + + + CKRDY + Clock Ready + 0 + 1 + + + + + HSDIV + HS Clock Division + 0x4 + 8 + read-only + 0x01 + + + DIV + CPU Clock Division Factor + 0 + 8 + + DIVSelect + + DIV1 + Divide by 1 + 0x01 + + + + + + + CPUDIV + CPU Clock Division + 0x5 + 8 + 0x01 + + + DIV + Low-Power Clock Division Factor + 0 + 8 + + DIVSelect + + DIV1 + Divide by 1 + 0x01 + + + DIV2 + Divide by 2 + 0x02 + + + DIV4 + Divide by 4 + 0x04 + + + DIV8 + Divide by 8 + 0x08 + + + DIV16 + Divide by 16 + 0x10 + + + DIV32 + Divide by 32 + 0x20 + + + DIV64 + Divide by 64 + 0x40 + + + DIV128 + Divide by 128 + 0x80 + + + + + + + AHBMASK + AHB Mask + 0x10 + 32 + 0x00FFFFFF + + + HPB0_ + HPB0 AHB Clock Mask + 0 + 1 + + + HPB1_ + HPB1 AHB Clock Mask + 1 + 1 + + + HPB2_ + HPB2 AHB Clock Mask + 2 + 1 + + + HPB3_ + HPB3 AHB Clock Mask + 3 + 1 + + + DSU_ + DSU AHB Clock Mask + 4 + 1 + + + HMATRIX_ + HMATRIX AHB Clock Mask + 5 + 1 + + + NVMCTRL_ + NVMCTRL AHB Clock Mask + 6 + 1 + + + HSRAM_ + HSRAM AHB Clock Mask + 7 + 1 + + + CMCC_ + CMCC AHB Clock Mask + 8 + 1 + + + DMAC_ + DMAC AHB Clock Mask + 9 + 1 + + + USB_ + USB AHB Clock Mask + 10 + 1 + + + BKUPRAM_ + BKUPRAM AHB Clock Mask + 11 + 1 + + + PAC_ + PAC AHB Clock Mask + 12 + 1 + + + QSPI_ + QSPI AHB Clock Mask + 13 + 1 + + + SDHC0_ + SDHC0 AHB Clock Mask + 15 + 1 + + + CAN0_ + CAN0 AHB Clock Mask + 17 + 1 + + + CAN1_ + CAN1 AHB Clock Mask + 18 + 1 + + + ICM_ + ICM AHB Clock Mask + 19 + 1 + + + PUKCC_ + PUKCC AHB Clock Mask + 20 + 1 + + + QSPI_2X_ + QSPI_2X AHB Clock Mask + 21 + 1 + + + NVMCTRL_SMEEPROM_ + NVMCTRL_SMEEPROM AHB Clock Mask + 22 + 1 + + + NVMCTRL_CACHE_ + NVMCTRL_CACHE AHB Clock Mask + 23 + 1 + + + + + APBAMASK + APBA Mask + 0x14 + 32 + 0x000007FF + + + PAC_ + PAC APB Clock Enable + 0 + 1 + + + PM_ + PM APB Clock Enable + 1 + 1 + + + MCLK_ + MCLK APB Clock Enable + 2 + 1 + + + RSTC_ + RSTC APB Clock Enable + 3 + 1 + + + OSCCTRL_ + OSCCTRL APB Clock Enable + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL APB Clock Enable + 5 + 1 + + + SUPC_ + SUPC APB Clock Enable + 6 + 1 + + + GCLK_ + GCLK APB Clock Enable + 7 + 1 + + + WDT_ + WDT APB Clock Enable + 8 + 1 + + + RTC_ + RTC APB Clock Enable + 9 + 1 + + + EIC_ + EIC APB Clock Enable + 10 + 1 + + + FREQM_ + FREQM APB Clock Enable + 11 + 1 + + + SERCOM0_ + SERCOM0 APB Clock Enable + 12 + 1 + + + SERCOM1_ + SERCOM1 APB Clock Enable + 13 + 1 + + + TC0_ + TC0 APB Clock Enable + 14 + 1 + + + TC1_ + TC1 APB Clock Enable + 15 + 1 + + + + + APBBMASK + APBB Mask + 0x18 + 32 + 0x00018056 + + + USB_ + USB APB Clock Enable + 0 + 1 + + + DSU_ + DSU APB Clock Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Clock Enable + 2 + 1 + + + PORT_ + PORT APB Clock Enable + 4 + 1 + + + HMATRIX_ + HMATRIX APB Clock Enable + 6 + 1 + + + EVSYS_ + EVSYS APB Clock Enable + 7 + 1 + + + SERCOM2_ + SERCOM2 APB Clock Enable + 9 + 1 + + + SERCOM3_ + SERCOM3 APB Clock Enable + 10 + 1 + + + TCC0_ + TCC0 APB Clock Enable + 11 + 1 + + + TCC1_ + TCC1 APB Clock Enable + 12 + 1 + + + TC2_ + TC2 APB Clock Enable + 13 + 1 + + + TC3_ + TC3 APB Clock Enable + 14 + 1 + + + RAMECC_ + RAMECC APB Clock Enable + 16 + 1 + + + + + APBCMASK + APBC Mask + 0x1C + 32 + 0x00002000 + + + TCC2_ + TCC2 APB Clock Enable + 3 + 1 + + + TCC3_ + TCC3 APB Clock Enable + 4 + 1 + + + TC4_ + TC4 APB Clock Enable + 5 + 1 + + + TC5_ + TC5 APB Clock Enable + 6 + 1 + + + PDEC_ + PDEC APB Clock Enable + 7 + 1 + + + AC_ + AC APB Clock Enable + 8 + 1 + + + AES_ + AES APB Clock Enable + 9 + 1 + + + TRNG_ + TRNG APB Clock Enable + 10 + 1 + + + ICM_ + ICM APB Clock Enable + 11 + 1 + + + QSPI_ + QSPI APB Clock Enable + 13 + 1 + + + CCL_ + CCL APB Clock Enable + 14 + 1 + + + + + APBDMASK + APBD Mask + 0x20 + 32 + 0x00000000 + + + SERCOM4_ + SERCOM4 APB Clock Enable + 0 + 1 + + + SERCOM5_ + SERCOM5 APB Clock Enable + 1 + 1 + + + TCC4_ + TCC4 APB Clock Enable + 4 + 1 + + + ADC0_ + ADC0 APB Clock Enable + 7 + 1 + + + ADC1_ + ADC1 APB Clock Enable + 8 + 1 + + + DAC_ + DAC APB Clock Enable + 9 + 1 + + + I2S_ + I2S APB Clock Enable + 10 + 1 + + + PCC_ + PCC APB Clock Enable + 11 + 1 + + + + + + + NVMCTRL + U24091.0.0 + Non-Volatile Memory Controller + NVMCTRL + NVMCTRL_ + 0x41004000 + + 0 + 0x30 + registers + + + NVMCTRL_0 + 29 + + + NVMCTRL_1 + 30 + + + + CTRLA + Control A + 0x0 + 16 + 0x0004 + + + AUTOWS + Auto Wait State Enable + 2 + 1 + + + SUSPEN + Suspend Enable + 3 + 1 + + + WMODE + Write Mode + 4 + 2 + + WMODESelect + + MAN + Manual Write + 0 + + + ADW + Automatic Double Word Write + 1 + + + AQW + Automatic Quad Word + 2 + + + AP + Automatic Page Write + 3 + + + + + PRM + Power Reduction Mode during Sleep + 6 + 2 + + PRMSelect + + SEMIAUTO + NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. + 0 + + + FULLAUTO + NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode when system is not in standby mode. + 1 + + + MANUAL + NVM block does not enter low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. + 3 + + + + + RWS + NVM Read Wait States + 8 + 4 + + + AHBNS0 + Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated + 12 + 1 + + + AHBNS1 + Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated + 13 + 1 + + + CACHEDIS0 + AHB0 Cache Disable + 14 + 1 + + + CACHEDIS1 + AHB1 Cache Disable + 15 + 1 + + + + + CTRLB + Control B + 0x4 + 16 + write-only + 0x0000 + + + CMD + Command + 0 + 7 + + CMDSelect + + EP + Erase Page - Only supported in the USER and AUX pages. + 0x0 + + + EB + Erase Block - Erases the block addressed by the ADDR register, not supported in the user page + 0x1 + + + WP + Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register, not supported in the user page + 0x3 + + + WQW + Write Quad Word - Writes a 128-bit word at the location addressed by the ADDR register. + 0x4 + + + SWRST + Software Reset - Power-Cycle the NVM memory and replay the device automatic calibration procedure and resets the module configuration registers + 0x10 + + + LR + Lock Region - Locks the region containing the address location in the ADDR register. + 0x11 + + + UR + Unlock Region - Unlocks the region containing the address location in the ADDR register. + 0x12 + + + SPRM + Sets the power reduction mode. + 0x13 + + + CPRM + Clears the power reduction mode. + 0x14 + + + PBC + Page Buffer Clear - Clears the page buffer. + 0x15 + + + SSB + Set Security Bit + 0x16 + + + BKSWRST + Bank swap and system reset, if SMEE is used also reallocate SMEE data into the opposite BANK + 0x17 + + + CELCK + Chip Erase Lock - DSU.CE command is not available + 0x18 + + + CEULCK + Chip Erase Unlock - DSU.CE command is available + 0x19 + + + SBPDIS + Sets STATUS.BPDIS, Boot loader protection is discarded until CBPDIS is issued or next start-up sequence + 0x1A + + + CBPDIS + Clears STATUS.BPDIS, Boot loader protection is not discarded + 0x1B + + + ASEES0 + Activate SmartEEPROM Sector 0, deactivate Sector 1 + 0x30 + + + ASEES1 + Activate SmartEEPROM Sector 1, deactivate Sector 0 + 0x31 + + + SEERALOC + Starts SmartEEPROM sector reallocation algorithm + 0x32 + + + SEEFLUSH + Flush SMEE data when in buffered mode + 0x33 + + + LSEE + Lock access to SmartEEPROM data from any mean + 0x34 + + + USEE + Unlock access to SmartEEPROM data + 0x35 + + + LSEER + Lock access to the SmartEEPROM Register Address Space (above 64KB) + 0x36 + + + USEER + Unlock access to the SmartEEPROM Register Address Space (above 64KB) + 0x37 + + + + + CMDEX + Command Execution + 8 + 8 + + CMDEXSelect + + KEY + Execution Key + 0xA5 + + + + + + + PARAM + NVM Parameter + 0x8 + 32 + read-only + 0x00060000 + + + NVMP + NVM Pages + 0 + 16 + + + PSZ + Page Size + 16 + 3 + + PSZSelect + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + SEE + SmartEEPROM Supported + 31 + 1 + + SEESelect + + A + 163840 bytes + 0xA + + + 9 + 147456 bytes + 0x9 + + + 8 + 131072 bytes + 0x8 + + + 7 + 114688 bytes + 0x7 + + + 6 + 98304 bytes + 0x6 + + + 5 + 81920 bytes + 0x5 + + + 4 + 65536 bytes + 0x4 + + + 3 + 49152 bytes + 0x3 + + + 2 + 32768 bytes + 0x2 + + + 1 + 16384 bytes + 0x1 + + + 0 + 0 bytes + 0x0 + + + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 16 + 0x0000 + + + DONE + Command Done Interrupt Clear + 0 + 1 + + + ADDRE + Address Error + 1 + 1 + + + PROGE + Programming Error Interrupt Clear + 2 + 1 + + + LOCKE + Lock Error Interrupt Clear + 3 + 1 + + + ECCSE + ECC Single Error Interrupt Clear + 4 + 1 + + + ECCDE + ECC Dual Error Interrupt Clear + 5 + 1 + + + NVME + NVM Error Interrupt Clear + 6 + 1 + + + SUSP + Suspended Write Or Erase Interrupt Clear + 7 + 1 + + + SEESFULL + Active SEES Full Interrupt Clear + 8 + 1 + + + SEESOVF + Active SEES Overflow Interrupt Clear + 9 + 1 + + + SEEWRC + SEE Write Completed Interrupt Clear + 10 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xE + 16 + 0x0000 + + + DONE + Command Done Interrupt Enable + 0 + 1 + + + ADDRE + Address Error Interrupt Enable + 1 + 1 + + + PROGE + Programming Error Interrupt Enable + 2 + 1 + + + LOCKE + Lock Error Interrupt Enable + 3 + 1 + + + ECCSE + ECC Single Error Interrupt Enable + 4 + 1 + + + ECCDE + ECC Dual Error Interrupt Enable + 5 + 1 + + + NVME + NVM Error Interrupt Enable + 6 + 1 + + + SUSP + Suspended Write Or Erase Interrupt Enable + 7 + 1 + + + SEESFULL + Active SEES Full Interrupt Enable + 8 + 1 + + + SEESOVF + Active SEES Overflow Interrupt Enable + 9 + 1 + + + SEEWRC + SEE Write Completed Interrupt Enable + 10 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x10 + 16 + 0x0000 + + + DONE + Command Done + 0 + 1 + + + ADDRE + Address Error + 1 + 1 + + + PROGE + Programming Error + 2 + 1 + + + LOCKE + Lock Error + 3 + 1 + + + ECCSE + ECC Single Error + 4 + 1 + + + ECCDE + ECC Dual Error + 5 + 1 + + + NVME + NVM Error + 6 + 1 + + + SUSP + Suspended Write Or Erase Operation + 7 + 1 + + + SEESFULL + Active SEES Full + 8 + 1 + + + SEESOVF + Active SEES Overflow + 9 + 1 + + + SEEWRC + SEE Write Completed + 10 + 1 + + + + + STATUS + Status + 0x12 + 16 + read-only + 0x0000 + + + READY + Ready to accept a command + 0 + 1 + + + PRM + Power Reduction Mode + 1 + 1 + + + LOAD + NVM Page Buffer Active Loading + 2 + 1 + + + SUSP + NVM Write Or Erase Operation Is Suspended + 3 + 1 + + + AFIRST + BANKA First + 4 + 1 + + + BPDIS + Boot Loader Protection Disable + 5 + 1 + + + BOOTPROT + Boot Loader Protection Size + 8 + 4 + + BOOTPROTSelect + + 0 + 0 kbytes + 0xF + + + 8 + 8 kbytes + 0xE + + + 16 + 16 kbytes + 0xD + + + 24 + 24 kbytes + 0xC + + + 32 + 32 kbytes + 0xB + + + 40 + 40 kbytes + 0xA + + + 48 + 48 kbytes + 0x9 + + + 56 + 56 kbytes + 0x8 + + + 64 + 64 kbytes + 0x7 + + + 72 + 72 kbytes + 0x6 + + + 80 + 80 kbytes + 0x5 + + + 88 + 88 kbytes + 0x4 + + + 96 + 96 kbytes + 0x3 + + + 104 + 104 kbytes + 0x2 + + + 112 + 112 kbytes + 0x1 + + + 120 + 120 kbytes + 0x0 + + + + + + + ADDR + Address + 0x14 + 32 + 0x00000000 + + + ADDR + NVM Address + 0 + 24 + + + + + RUNLOCK + Lock Section + 0x18 + 32 + read-only + 0x00000000 + + + RUNLOCK + Region Un-Lock Bits + 0 + 32 + + + + + 2 + 4 + PBLDATA[%s] + Page Buffer Load Data x + 0x1C + 32 + read-only + 0xFFFFFFFF + + + DATA + Page Buffer Data + 0 + 32 + + + + + ECCERR + ECC Error Status Register + 0x24 + 32 + read-only + 0x00000000 + + + ADDR + Error Address + 0 + 24 + + + TYPEL + Low Double-Word Error Type + 28 + 2 + + TYPELSelect + + None + No Error Detected Since Last Read + 0 + + + Single + At Least One Single Error Detected Since last Read + 1 + + + Dual + At Least One Dual Error Detected Since Last Read + 2 + + + + + TYPEH + High Double-Word Error Type + 30 + 2 + + TYPEHSelect + + None + No Error Detected Since Last Read + 0 + + + Single + At Least One Single Error Detected Since last Read + 1 + + + Dual + At Least One Dual Error Detected Since Last Read + 2 + + + + + + + DBGCTRL + Debug Control + 0x28 + 8 + 0x00 + + + ECCDIS + Debugger ECC Read Disable + 0 + 1 + + + ECCELOG + Debugger ECC Error Tracking Mode + 1 + 1 + + + + + SEECFG + SmartEEPROM Configuration Register + 0x2A + 8 + 0x00 + + + WMODE + Write Mode + 0 + 1 + + WMODESelect + + UNBUFFERED + A NVM write command is issued after each write in the pagebuffer + 0 + + + BUFFERED + A NVM write command is issued when a write to a new page is requested + 1 + + + + + APRDIS + Automatic Page Reallocation Disable + 1 + 1 + + + + + SEESTAT + SmartEEPROM Status Register + 0x2C + 32 + read-only + 0x00000000 + + + ASEES + Active SmartEEPROM Sector + 0 + 1 + + + LOAD + Page Buffer Loaded + 1 + 1 + + + BUSY + Busy + 2 + 1 + + + LOCK + SmartEEPROM Write Access Is Locked + 3 + 1 + + + RLOCK + SmartEEPROM Write Access To Register Address Space Is Locked + 4 + 1 + + + SBLK + Blocks Number In a Sector + 8 + 4 + + + PSZ + SmartEEPROM Page Size + 16 + 3 + + + + + + + OSCCTRL + U24011.0.0 + Oscillators Control + OSCCTRL + OSCCTRL_ + 0x40001000 + + 0 + 0x58 + registers + + + OSCCTRL_XOSC0 + 2 + + + OSCCTRL_XOSC1 + 3 + + + OSCCTRL_DFLL + 4 + + + OSCCTRL_DPLL0 + 5 + + + OSCCTRL_DPLL1 + 6 + + + + EVCTRL + Event Control + 0x0 + 8 + 0x00 + + + CFDEO0 + Clock 0 Failure Detector Event Output Enable + 0 + 1 + + + CFDEO1 + Clock 1 Failure Detector Event Output Enable + 1 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 32 + 0x00000000 + + + XOSCRDY0 + XOSC 0 Ready Interrupt Enable + 0 + 1 + + + XOSCRDY1 + XOSC 1 Ready Interrupt Enable + 1 + 1 + + + XOSCFAIL0 + XOSC 0 Clock Failure Detector Interrupt Enable + 2 + 1 + + + XOSCFAIL1 + XOSC 1 Clock Failure Detector Interrupt Enable + 3 + 1 + + + DFLLRDY + DFLL Ready Interrupt Enable + 8 + 1 + + + DFLLOOB + DFLL Out Of Bounds Interrupt Enable + 9 + 1 + + + DFLLLCKF + DFLL Lock Fine Interrupt Enable + 10 + 1 + + + DFLLLCKC + DFLL Lock Coarse Interrupt Enable + 11 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped Interrupt Enable + 12 + 1 + + + DPLL0LCKR + DPLL0 Lock Rise Interrupt Enable + 16 + 1 + + + DPLL0LCKF + DPLL0 Lock Fall Interrupt Enable + 17 + 1 + + + DPLL0LTO + DPLL0 Lock Timeout Interrupt Enable + 18 + 1 + + + DPLL0LDRTO + DPLL0 Loop Divider Ratio Update Complete Interrupt Enable + 19 + 1 + + + DPLL1LCKR + DPLL1 Lock Rise Interrupt Enable + 24 + 1 + + + DPLL1LCKF + DPLL1 Lock Fall Interrupt Enable + 25 + 1 + + + DPLL1LTO + DPLL1 Lock Timeout Interrupt Enable + 26 + 1 + + + DPLL1LDRTO + DPLL1 Loop Divider Ratio Update Complete Interrupt Enable + 27 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x8 + 32 + 0x00000000 + + + XOSCRDY0 + XOSC 0 Ready Interrupt Enable + 0 + 1 + + + XOSCRDY1 + XOSC 1 Ready Interrupt Enable + 1 + 1 + + + XOSCFAIL0 + XOSC 0 Clock Failure Detector Interrupt Enable + 2 + 1 + + + XOSCFAIL1 + XOSC 1 Clock Failure Detector Interrupt Enable + 3 + 1 + + + DFLLRDY + DFLL Ready Interrupt Enable + 8 + 1 + + + DFLLOOB + DFLL Out Of Bounds Interrupt Enable + 9 + 1 + + + DFLLLCKF + DFLL Lock Fine Interrupt Enable + 10 + 1 + + + DFLLLCKC + DFLL Lock Coarse Interrupt Enable + 11 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped Interrupt Enable + 12 + 1 + + + DPLL0LCKR + DPLL0 Lock Rise Interrupt Enable + 16 + 1 + + + DPLL0LCKF + DPLL0 Lock Fall Interrupt Enable + 17 + 1 + + + DPLL0LTO + DPLL0 Lock Timeout Interrupt Enable + 18 + 1 + + + DPLL0LDRTO + DPLL0 Loop Divider Ratio Update Complete Interrupt Enable + 19 + 1 + + + DPLL1LCKR + DPLL1 Lock Rise Interrupt Enable + 24 + 1 + + + DPLL1LCKF + DPLL1 Lock Fall Interrupt Enable + 25 + 1 + + + DPLL1LTO + DPLL1 Lock Timeout Interrupt Enable + 26 + 1 + + + DPLL1LDRTO + DPLL1 Loop Divider Ratio Update Complete Interrupt Enable + 27 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xC + 32 + 0x00000000 + + + XOSCRDY0 + XOSC 0 Ready + 0 + 1 + + + XOSCRDY1 + XOSC 1 Ready + 1 + 1 + + + XOSCFAIL0 + XOSC 0 Clock Failure Detector + 2 + 1 + + + XOSCFAIL1 + XOSC 1 Clock Failure Detector + 3 + 1 + + + DFLLRDY + DFLL Ready + 8 + 1 + + + DFLLOOB + DFLL Out Of Bounds + 9 + 1 + + + DFLLLCKF + DFLL Lock Fine + 10 + 1 + + + DFLLLCKC + DFLL Lock Coarse + 11 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped + 12 + 1 + + + DPLL0LCKR + DPLL0 Lock Rise + 16 + 1 + + + DPLL0LCKF + DPLL0 Lock Fall + 17 + 1 + + + DPLL0LTO + DPLL0 Lock Timeout + 18 + 1 + + + DPLL0LDRTO + DPLL0 Loop Divider Ratio Update Complete + 19 + 1 + + + DPLL1LCKR + DPLL1 Lock Rise + 24 + 1 + + + DPLL1LCKF + DPLL1 Lock Fall + 25 + 1 + + + DPLL1LTO + DPLL1 Lock Timeout + 26 + 1 + + + DPLL1LDRTO + DPLL1 Loop Divider Ratio Update Complete + 27 + 1 + + + + + STATUS + Status + 0x10 + 32 + read-only + 0x00000000 + + + XOSCRDY0 + XOSC 0 Ready + 0 + 1 + + + XOSCRDY1 + XOSC 1 Ready + 1 + 1 + + + XOSCFAIL0 + XOSC 0 Clock Failure Detector + 2 + 1 + + + XOSCFAIL1 + XOSC 1 Clock Failure Detector + 3 + 1 + + + XOSCCKSW0 + XOSC 0 Clock Switch + 4 + 1 + + + XOSCCKSW1 + XOSC 1 Clock Switch + 5 + 1 + + + DFLLRDY + DFLL Ready + 8 + 1 + + + DFLLOOB + DFLL Out Of Bounds + 9 + 1 + + + DFLLLCKF + DFLL Lock Fine + 10 + 1 + + + DFLLLCKC + DFLL Lock Coarse + 11 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped + 12 + 1 + + + DPLL0LCKR + DPLL0 Lock Rise + 16 + 1 + + + DPLL0LCKF + DPLL0 Lock Fall + 17 + 1 + + + DPLL0TO + DPLL0 Timeout + 18 + 1 + + + DPLL0LDRTO + DPLL0 Loop Divider Ratio Update Complete + 19 + 1 + + + DPLL1LCKR + DPLL1 Lock Rise + 24 + 1 + + + DPLL1LCKF + DPLL1 Lock Fall + 25 + 1 + + + DPLL1TO + DPLL1 Timeout + 26 + 1 + + + DPLL1LDRTO + DPLL1 Loop Divider Ratio Update Complete + 27 + 1 + + + + + 2 + 4 + XOSCCTRL[%s] + External Multipurpose Crystal Oscillator Control + 0x14 + 32 + 0x00000080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + LOWBUFGAIN + Low Buffer Gain Enable + 8 + 1 + + + IPTAT + Oscillator Current Reference + 9 + 2 + + + IMULT + Oscillator Current Multiplier + 11 + 4 + + + ENALC + Automatic Loop Control Enable + 15 + 1 + + + CFDEN + Clock Failure Detector Enable + 16 + 1 + + + SWBEN + Xosc Clock Switch Enable + 17 + 1 + + + STARTUP + Start-Up Time + 20 + 4 + + STARTUPSelect + + CYCLE1 + 31 us + 0 + + + CYCLE2 + 61 us + 1 + + + CYCLE4 + 122 us + 2 + + + CYCLE8 + 244 us + 3 + + + CYCLE16 + 488 us + 4 + + + CYCLE32 + 977 us + 5 + + + CYCLE64 + 1953 us + 6 + + + CYCLE128 + 3906 us + 7 + + + CYCLE256 + 7813 us + 8 + + + CYCLE512 + 15625 us + 9 + + + CYCLE1024 + 31250 us + 10 + + + CYCLE2048 + 62500 us + 11 + + + CYCLE4096 + 125000 us + 12 + + + CYCLE8192 + 250000 us + 13 + + + CYCLE16384 + 500000 us + 14 + + + CYCLE32768 + 1000000 us + 15 + + + + + CFDPRESC + Clock Failure Detector Prescaler + 24 + 4 + + CFDPRESCSelect + + DIV1 + 48 MHz + 0 + + + DIV2 + 24 MHz + 1 + + + DIV4 + 12 MHz + 2 + + + DIV8 + 6 MHz + 3 + + + DIV16 + 3 MHz + 4 + + + DIV32 + 1.5 MHz + 5 + + + DIV64 + 0.75 MHz + 6 + + + DIV128 + 0.3125 MHz + 7 + + + + + + + DFLLCTRLA + DFLL48M Control A + 0x1C + 8 + 0x82 + + + ENABLE + DFLL Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + + + DFLLCTRLB + DFLL48M Control B + 0x20 + 8 + 0x00 + + + MODE + Operating Mode Selection + 0 + 1 + + + STABLE + Stable DFLL Frequency + 1 + 1 + + + LLAW + Lose Lock After Wake + 2 + 1 + + + USBCRM + USB Clock Recovery Mode + 3 + 1 + + + CCDIS + Chill Cycle Disable + 4 + 1 + + + QLDIS + Quick Lock Disable + 5 + 1 + + + BPLCKC + Bypass Coarse Lock + 6 + 1 + + + WAITLOCK + Wait Lock + 7 + 1 + + + + + DFLLVAL + DFLL48M Value + 0x24 + 32 + 0x00000000 + + + FINE + Fine Value + 0 + 8 + + + COARSE + Coarse Value + 10 + 6 + + + DIFF + Multiplication Ratio Difference + 16 + 16 + + + + + DFLLMUL + DFLL48M Multiplier + 0x28 + 32 + 0x00000000 + + + MUL + DFLL Multiply Factor + 0 + 16 + + + FSTEP + Fine Maximum Step + 16 + 8 + + + CSTEP + Coarse Maximum Step + 26 + 6 + + + + + DFLLSYNC + DFLL48M Synchronization + 0x2C + 8 + 0x00 + + + ENABLE + ENABLE Synchronization Busy + 1 + 1 + + + DFLLCTRLB + DFLLCTRLB Synchronization Busy + 2 + 1 + + + DFLLVAL + DFLLVAL Synchronization Busy + 3 + 1 + + + DFLLMUL + DFLLMUL Synchronization Busy + 4 + 1 + + + + + 2 + 0x14 + DPLL[%s] + + 0x30 + + DPLLCTRLA + DPLL Control A + 0x0 + 8 + 0x80 + + + ENABLE + DPLL Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + + + DPLLRATIO + DPLL Ratio Control + 0x4 + 32 + 0x00000000 + + + LDR + Loop Divider Ratio + 0 + 13 + + + LDRFRAC + Loop Divider Ratio Fractional Part + 16 + 5 + + + + + DPLLCTRLB + DPLL Control B + 0x8 + 32 + 0x00000020 + + + FILTER + Proportional Integral Filter Selection + 0 + 4 + + FILTERSelect + + FILTER1 + Bandwidth = 92.7Khz and Damping Factor = 0.76 + 0 + + + FILTER2 + Bandwidth = 131Khz and Damping Factor = 1.08 + 1 + + + FILTER3 + Bandwidth = 46.4Khz and Damping Factor = 0.38 + 2 + + + FILTER4 + Bandwidth = 65.6Khz and Damping Factor = 0.54 + 3 + + + FILTER5 + Bandwidth = 131Khz and Damping Factor = 0.56 + 4 + + + FILTER6 + Bandwidth = 185Khz and Damping Factor = 0.79 + 5 + + + FILTER7 + Bandwidth = 65.6Khz and Damping Factor = 0.28 + 6 + + + FILTER8 + Bandwidth = 92.7Khz and Damping Factor = 0.39 + 7 + + + FILTER9 + Bandwidth = 46.4Khz and Damping Factor = 1.49 + 8 + + + FILTER10 + Bandwidth = 65.6Khz and Damping Factor = 2.11 + 9 + + + FILTER11 + Bandwidth = 23.2Khz and Damping Factor = 0.75 + 10 + + + FILTER12 + Bandwidth = 32.8Khz and Damping Factor = 1.06 + 11 + + + FILTER13 + Bandwidth = 65.6Khz and Damping Factor = 1.07 + 12 + + + FILTER14 + Bandwidth = 92.7Khz and Damping Factor = 1.51 + 13 + + + FILTER15 + Bandwidth = 32.8Khz and Damping Factor = 0.53 + 14 + + + FILTER16 + Bandwidth = 46.4Khz and Damping Factor = 0.75 + 15 + + + + + WUF + Wake Up Fast + 4 + 1 + + + REFCLK + Reference Clock Selection + 5 + 3 + + REFCLKSelect + + GCLK + Dedicated GCLK clock reference + 0x0 + + + XOSC32 + XOSC32K clock reference + 0x1 + + + XOSC0 + XOSC0 clock reference + 0x2 + + + XOSC1 + XOSC1 clock reference + 0x3 + + + + + LTIME + Lock Time + 8 + 3 + + LTIMESelect + + DEFAULT + No time-out. Automatic lock + 0x0 + + + 800US + Time-out if no lock within 800us + 0x4 + + + 900US + Time-out if no lock within 900us + 0x5 + + + 1MS + Time-out if no lock within 1ms + 0x6 + + + 1P1MS + Time-out if no lock within 1.1ms + 0x7 + + + + + LBYPASS + Lock Bypass + 11 + 1 + + + DCOFILTER + Sigma-Delta DCO Filter Selection + 12 + 3 + + DCOFILTERSelect + + FILTER1 + Capacitor(pF) = 0.5 and Bandwidth Fn (MHz) = 3.21 + 0 + + + FILTER2 + Capacitor(pF) = 1 and Bandwidth Fn (MHz) = 1.6 + 1 + + + FILTER3 + Capacitor(pF) = 1.5 and Bandwidth Fn (MHz) = 1.1 + 2 + + + FILTER4 + Capacitor(pF) = 2 and Bandwidth Fn (MHz) = 0.8 + 3 + + + FILTER5 + Capacitor(pF) = 2.5 and Bandwidth Fn (MHz) = 0.64 + 4 + + + FILTER6 + Capacitor(pF) = 3 and Bandwidth Fn (MHz) = 0.55 + 5 + + + FILTER7 + Capacitor(pF) = 3.5 and Bandwidth Fn (MHz) = 0.45 + 6 + + + FILTER8 + Capacitor(pF) = 4 and Bandwidth Fn (MHz) = 0.4 + 7 + + + + + DCOEN + DCO Filter Enable + 15 + 1 + + + DIV + Clock Divider + 16 + 11 + + + + + DPLLSYNCBUSY + DPLL Synchronization Busy + 0xC + 32 + read-only + 0x00000000 + + + ENABLE + DPLL Enable Synchronization Status + 1 + 1 + + + DPLLRATIO + DPLL Loop Divider Ratio Synchronization Status + 2 + 1 + + + + + DPLLSTATUS + DPLL Status + 0x10 + 32 + read-only + 0x00000000 + + + LOCK + DPLL Lock Status + 0 + 1 + + + CLKRDY + DPLL Clock Ready + 1 + 1 + + + + + + + + OSC32KCTRL + U24001.0.0 + 32kHz Oscillators Control + OSC32KCTRL + OSC32KCTRL_ + 0x40001400 + + 0 + 0x20 + registers + + + OSC32KCTRL + 7 + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 0 + 1 + + + XOSC32KFAIL + XOSC32K Clock Failure Detector Interrupt Enable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 0 + 1 + + + XOSC32KFAIL + XOSC32K Clock Failure Detector Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready + 0 + 1 + + + XOSC32KFAIL + XOSC32K Clock Failure Detector + 2 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready + 0 + 1 + + + XOSC32KFAIL + XOSC32K Clock Failure Detector + 2 + 1 + + + XOSC32KSW + XOSC32K Clock switch + 3 + 1 + + + + + RTCCTRL + RTC Clock Selection + 0x10 + 8 + 0x00 + + + RTCSEL + RTC Clock Selection + 0 + 3 + + RTCSELSelect + + ULP1K + 1.024kHz from 32kHz internal ULP oscillator + 0 + + + ULP32K + 32.768kHz from 32kHz internal ULP oscillator + 1 + + + XOSC1K + 1.024kHz from 32.768kHz internal oscillator + 4 + + + XOSC32K + 32.768kHz from 32.768kHz external crystal oscillator + 5 + + + + + + + XOSC32K + 32kHz External Crystal Oscillator (XOSC32K) Control + 0x14 + 16 + 0x2080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + EN32K + 32kHz Output Enable + 3 + 1 + + + EN1K + 1kHz Output Enable + 4 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE2048 + 62.6 ms + 0 + + + CYCLE4096 + 125 ms + 1 + + + CYCLE16384 + 500 ms + 2 + + + CYCLE32768 + 1000 ms + 3 + + + CYCLE65536 + 2000 ms + 4 + + + CYCLE131072 + 4000 ms + 5 + + + CYCLE262144 + 8000 ms + 6 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + CGM + Control Gain Mode + 13 + 2 + + CGMSelect + + XT + Standard mode + 1 + + + HS + High Speed mode + 2 + + + + + + + CFDCTRL + Clock Failure Detector Control + 0x16 + 8 + 0x00 + + + CFDEN + Clock Failure Detector Enable + 0 + 1 + + + SWBACK + Clock Switch Back + 1 + 1 + + + CFDPRESC + Clock Failure Detector Prescaler + 2 + 1 + + + + + EVCTRL + Event Control + 0x17 + 8 + 0x00 + + + CFDEO + Clock Failure Detector Event Output Enable + 0 + 1 + + + + + OSCULP32K + 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control + 0x1C + 32 + 0x00000000 + + + EN32K + Enable Out 32k + 1 + 1 + + + EN1K + Enable Out 1k + 2 + 1 + + + CALIB + Oscillator Calibration + 8 + 6 + + + WRTLOCK + Write Lock + 15 + 1 + + + + + + + PAC + U21201.2.0 + Peripheral Access Controller + PAC + PAC_ + 0x40000000 + + 0 + 0x44 + registers + + + PAC + 41 + + + + WRCTRL + Write control + 0x0 + 32 + 0x00000000 + + + PERID + Peripheral identifier + 0 + 16 + + + KEY + Peripheral access control key + 16 + 8 + + KEYSelect + + OFF + No action + 0 + + + CLR + Clear protection + 1 + + + SET + Set protection + 2 + + + SETLCK + Set and lock protection + 3 + + + + + + + EVCTRL + Event control + 0x4 + 8 + 0x00 + + + ERREO + Peripheral acess error event output + 0 + 1 + + + + + INTENCLR + Interrupt enable clear + 0x8 + 8 + 0x00 + + + ERR + Peripheral access error interrupt disable + 0 + 1 + + + + + INTENSET + Interrupt enable set + 0x9 + 8 + 0x00 + + + ERR + Peripheral access error interrupt enable + 0 + 1 + + + + + INTFLAGAHB + Bridge interrupt flag status + 0x10 + 32 + 0x00000000 + + + FLASH_ + FLASH + 0 + 1 + + + FLASH_ALT_ + FLASH_ALT + 1 + 1 + + + SEEPROM_ + SEEPROM + 2 + 1 + + + RAMCM4S_ + RAMCM4S + 3 + 1 + + + RAMPPPDSU_ + RAMPPPDSU + 4 + 1 + + + RAMDMAWR_ + RAMDMAWR + 5 + 1 + + + RAMDMACICM_ + RAMDMACICM + 6 + 1 + + + HPB0_ + HPB0 + 7 + 1 + + + HPB1_ + HPB1 + 8 + 1 + + + HPB2_ + HPB2 + 9 + 1 + + + HPB3_ + HPB3 + 10 + 1 + + + PUKCC_ + PUKCC + 11 + 1 + + + SDHC0_ + SDHC0 + 12 + 1 + + + QSPI_ + QSPI + 14 + 1 + + + BKUPRAM_ + BKUPRAM + 15 + 1 + + + + + INTFLAGA + Peripheral interrupt flag status - Bridge A + 0x14 + 32 + 0x00000000 + + + PAC_ + PAC + 0 + 1 + + + PM_ + PM + 1 + 1 + + + MCLK_ + MCLK + 2 + 1 + + + RSTC_ + RSTC + 3 + 1 + + + OSCCTRL_ + OSCCTRL + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL + 5 + 1 + + + SUPC_ + SUPC + 6 + 1 + + + GCLK_ + GCLK + 7 + 1 + + + WDT_ + WDT + 8 + 1 + + + RTC_ + RTC + 9 + 1 + + + EIC_ + EIC + 10 + 1 + + + FREQM_ + FREQM + 11 + 1 + + + SERCOM0_ + SERCOM0 + 12 + 1 + + + SERCOM1_ + SERCOM1 + 13 + 1 + + + TC0_ + TC0 + 14 + 1 + + + TC1_ + TC1 + 15 + 1 + + + + + INTFLAGB + Peripheral interrupt flag status - Bridge B + 0x18 + 32 + 0x00000000 + + + USB_ + USB + 0 + 1 + + + DSU_ + DSU + 1 + 1 + + + NVMCTRL_ + NVMCTRL + 2 + 1 + + + CMCC_ + CMCC + 3 + 1 + + + PORT_ + PORT + 4 + 1 + + + DMAC_ + DMAC + 5 + 1 + + + HMATRIX_ + HMATRIX + 6 + 1 + + + EVSYS_ + EVSYS + 7 + 1 + + + SERCOM2_ + SERCOM2 + 9 + 1 + + + SERCOM3_ + SERCOM3 + 10 + 1 + + + TCC0_ + TCC0 + 11 + 1 + + + TCC1_ + TCC1 + 12 + 1 + + + TC2_ + TC2 + 13 + 1 + + + TC3_ + TC3 + 14 + 1 + + + RAMECC_ + RAMECC + 16 + 1 + + + + + INTFLAGC + Peripheral interrupt flag status - Bridge C + 0x1C + 32 + 0x00000000 + + + CAN0_ + CAN0 + 0 + 1 + + + CAN1_ + CAN1 + 1 + 1 + + + TCC2_ + TCC2 + 3 + 1 + + + TCC3_ + TCC3 + 4 + 1 + + + TC4_ + TC4 + 5 + 1 + + + TC5_ + TC5 + 6 + 1 + + + PDEC_ + PDEC + 7 + 1 + + + AC_ + AC + 8 + 1 + + + AES_ + AES + 9 + 1 + + + TRNG_ + TRNG + 10 + 1 + + + ICM_ + ICM + 11 + 1 + + + PUKCC_ + PUKCC + 12 + 1 + + + QSPI_ + QSPI + 13 + 1 + + + CCL_ + CCL + 14 + 1 + + + + + INTFLAGD + Peripheral interrupt flag status - Bridge D + 0x20 + 32 + 0x00000000 + + + SERCOM4_ + SERCOM4 + 0 + 1 + + + SERCOM5_ + SERCOM5 + 1 + 1 + + + TCC4_ + TCC4 + 4 + 1 + + + ADC0_ + ADC0 + 7 + 1 + + + ADC1_ + ADC1 + 8 + 1 + + + DAC_ + DAC + 9 + 1 + + + I2S_ + I2S + 10 + 1 + + + PCC_ + PCC + 11 + 1 + + + + + STATUSA + Peripheral write protection status - Bridge A + 0x34 + 32 + read-only + 0x00010000 + + + PAC_ + PAC APB Protect Enable + 0 + 1 + + + PM_ + PM APB Protect Enable + 1 + 1 + + + MCLK_ + MCLK APB Protect Enable + 2 + 1 + + + RSTC_ + RSTC APB Protect Enable + 3 + 1 + + + OSCCTRL_ + OSCCTRL APB Protect Enable + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL APB Protect Enable + 5 + 1 + + + SUPC_ + SUPC APB Protect Enable + 6 + 1 + + + GCLK_ + GCLK APB Protect Enable + 7 + 1 + + + WDT_ + WDT APB Protect Enable + 8 + 1 + + + RTC_ + RTC APB Protect Enable + 9 + 1 + + + EIC_ + EIC APB Protect Enable + 10 + 1 + + + FREQM_ + FREQM APB Protect Enable + 11 + 1 + + + SERCOM0_ + SERCOM0 APB Protect Enable + 12 + 1 + + + SERCOM1_ + SERCOM1 APB Protect Enable + 13 + 1 + + + TC0_ + TC0 APB Protect Enable + 14 + 1 + + + TC1_ + TC1 APB Protect Enable + 15 + 1 + + + + + STATUSB + Peripheral write protection status - Bridge B + 0x38 + 32 + read-only + 0x00000002 + + + USB_ + USB APB Protect Enable + 0 + 1 + + + DSU_ + DSU APB Protect Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Protect Enable + 2 + 1 + + + CMCC_ + CMCC APB Protect Enable + 3 + 1 + + + PORT_ + PORT APB Protect Enable + 4 + 1 + + + DMAC_ + DMAC APB Protect Enable + 5 + 1 + + + HMATRIX_ + HMATRIX APB Protect Enable + 6 + 1 + + + EVSYS_ + EVSYS APB Protect Enable + 7 + 1 + + + SERCOM2_ + SERCOM2 APB Protect Enable + 9 + 1 + + + SERCOM3_ + SERCOM3 APB Protect Enable + 10 + 1 + + + TCC0_ + TCC0 APB Protect Enable + 11 + 1 + + + TCC1_ + TCC1 APB Protect Enable + 12 + 1 + + + TC2_ + TC2 APB Protect Enable + 13 + 1 + + + TC3_ + TC3 APB Protect Enable + 14 + 1 + + + RAMECC_ + RAMECC APB Protect Enable + 16 + 1 + + + + + STATUSC + Peripheral write protection status - Bridge C + 0x3C + 32 + read-only + 0x00000000 + + + CAN0_ + CAN0 APB Protect Enable + 0 + 1 + + + CAN1_ + CAN1 APB Protect Enable + 1 + 1 + + + TCC2_ + TCC2 APB Protect Enable + 3 + 1 + + + TCC3_ + TCC3 APB Protect Enable + 4 + 1 + + + TC4_ + TC4 APB Protect Enable + 5 + 1 + + + TC5_ + TC5 APB Protect Enable + 6 + 1 + + + PDEC_ + PDEC APB Protect Enable + 7 + 1 + + + AC_ + AC APB Protect Enable + 8 + 1 + + + AES_ + AES APB Protect Enable + 9 + 1 + + + TRNG_ + TRNG APB Protect Enable + 10 + 1 + + + ICM_ + ICM APB Protect Enable + 11 + 1 + + + PUKCC_ + PUKCC APB Protect Enable + 12 + 1 + + + QSPI_ + QSPI APB Protect Enable + 13 + 1 + + + CCL_ + CCL APB Protect Enable + 14 + 1 + + + + + STATUSD + Peripheral write protection status - Bridge D + 0x40 + 32 + read-only + 0x00000000 + + + SERCOM4_ + SERCOM4 APB Protect Enable + 0 + 1 + + + SERCOM5_ + SERCOM5 APB Protect Enable + 1 + 1 + + + TCC4_ + TCC4 APB Protect Enable + 4 + 1 + + + ADC0_ + ADC0 APB Protect Enable + 7 + 1 + + + ADC1_ + ADC1 APB Protect Enable + 8 + 1 + + + DAC_ + DAC APB Protect Enable + 9 + 1 + + + I2S_ + I2S APB Protect Enable + 10 + 1 + + + PCC_ + PCC APB Protect Enable + 11 + 1 + + + + + + + PCC + U20171.1.0 + Parallel Capture Controller + PCC + PCC_ + 0x43002C00 + + 0 + 0xE8 + registers + + + PCC + 129 + + + + MR + Mode Register + 0x0 + 32 + 0x00000000 + + + PCEN + Parallel Capture Enable + 0 + 1 + + + DSIZE + Data size + 4 + 2 + + + SCALE + Scale data + 8 + 1 + + + ALWYS + Always Sampling + 9 + 1 + + + HALFS + Half Sampling + 10 + 1 + + + FRSTS + First sample + 11 + 1 + + + ISIZE + Input Data Size + 16 + 3 + + + CID + Clear If Disabled + 30 + 2 + + + + + IER + Interrupt Enable Register + 0x4 + 32 + write-only + 0x00000000 + + + DRDY + Data Ready Interrupt Enable + 0 + 1 + + + OVRE + Overrun Error Interrupt Enable + 1 + 1 + + + + + IDR + Interrupt Disable Register + 0x8 + 32 + write-only + 0x00000000 + + + DRDY + Data Ready Interrupt Disable + 0 + 1 + + + OVRE + Overrun Error Interrupt Disable + 1 + 1 + + + + + IMR + Interrupt Mask Register + 0xC + 32 + read-only + 0x00000000 + + + DRDY + Data Ready Interrupt Mask + 0 + 1 + + + OVRE + Overrun Error Interrupt Mask + 1 + 1 + + + + + ISR + Interrupt Status Register + 0x10 + 32 + read-only + 0x00000000 + + + DRDY + Data Ready Interrupt Status + 0 + 1 + + + OVRE + Overrun Error Interrupt Status + 1 + 1 + + + + + RHR + Reception Holding Register + 0x14 + 32 + read-only + 0x00000000 + + + RDATA + Reception Data + 0 + 32 + + + + + WPMR + Write Protection Mode Register + 0xE0 + 32 + 0x00000000 + + + WPEN + Write Protection Enable + 0 + 1 + + + WPKEY + Write Protection Key + 8 + 24 + + + + + WPSR + Write Protection Status Register + 0xE4 + 32 + read-only + 0x00000000 + + + WPVS + Write Protection Violation Source + 0 + 1 + + + WPVSRC + Write Protection Violation Status + 8 + 16 + + + + + + + PDEC + U22631.0.0 + Quadrature Decodeur + PDEC + PDEC_ + 0x42001C00 + + 0 + 0x38 + registers + + + PDEC_OTHER + 115 + + + PDEC_MC0 + 116 + + + PDEC_MC1 + 117 + + + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operation Mode + 2 + 2 + + MODESelect + + QDEC + QDEC operating mode + 0 + + + HALL + HALL operating mode + 1 + + + COUNTER + COUNTER operating mode + 2 + + + + + RUNSTDBY + Run in Standby + 6 + 1 + + + CONF + PDEC Configuration + 8 + 3 + + CONFSelect + + X4 + Quadrature decoder direction + 0 + + + X4S + Secure Quadrature decoder direction + 1 + + + X2 + Decoder direction + 2 + + + X2S + Secure decoder direction + 3 + + + AUTOC + Auto correction mode + 4 + + + + + ALOCK + Auto Lock + 11 + 1 + + + SWAP + PDEC Phase A and B Swap + 14 + 1 + + + PEREN + Period Enable + 15 + 1 + + + PINEN0 + PDEC Input From Pin 0 Enable + 16 + 1 + + + PINEN1 + PDEC Input From Pin 1 Enable + 17 + 1 + + + PINEN2 + PDEC Input From Pin 2 Enable + 18 + 1 + + + PINVEN0 + IO Pin 0 Invert Enable + 20 + 1 + + + PINVEN1 + IO Pin 1 Invert Enable + 21 + 1 + + + PINVEN2 + IO Pin 2 Invert Enable + 22 + 1 + + + ANGULAR + Angular Counter Length + 24 + 3 + + + MAXCMP + Maximum Consecutive Missing Pulses + 28 + 4 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + LUPD + Lock Update + 1 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a counter restart or retrigger + 1 + + + UPDATE + Force update of double buffered registers + 2 + + + READSYNC + Force a read synchronization of COUNT + 3 + + + START + Start QDEC/HALL + 4 + + + STOP + Stop QDEC/HALL + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + LUPD + Lock Update + 1 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a counter restart or retrigger + 1 + + + UPDATE + Force update of double buffered registers + 2 + + + READSYNC + Force a read synchronization of COUNT + 3 + + + START + Start QDEC/HALL + 4 + + + STOP + Stop QDEC/HALL + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 2 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger on event + 1 + + + COUNT + Count on event + 2 + + + + + EVINV + Inverted Event Input Enable + 2 + 3 + + + EVEI + Event Input Enable + 5 + 3 + + + OVFEO + Overflow/Underflow Output Event Enable + 8 + 1 + + + ERREO + Error Output Event Enable + 9 + 1 + + + DIREO + Direction Output Event Enable + 10 + 1 + + + VLCEO + Velocity Output Event Enable + 11 + 1 + + + MCEO0 + Match Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + Overflow/Underflow Interrupt Disable + 0 + 1 + + + ERR + Error Interrupt Disable + 1 + 1 + + + DIR + Direction Interrupt Disable + 2 + 1 + + + VLC + Velocity Interrupt Disable + 3 + 1 + + + MC0 + Channel 0 Compare Match Disable + 4 + 1 + + + MC1 + Channel 1 Compare Match Disable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + Overflow/Underflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + DIR + Direction Interrupt Enable + 2 + 1 + + + VLC + Velocity Interrupt Enable + 3 + 1 + + + MC0 + Channel 0 Compare Match Enable + 4 + 1 + + + MC1 + Channel 1 Compare Match Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + Overflow/Underflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + DIR + Direction Change + 2 + 1 + + + VLC + Velocity + 3 + 1 + + + MC0 + Channel 0 Compare Match + 4 + 1 + + + MC1 + Channel 1 Compare Match + 5 + 1 + + + + + STATUS + Status + 0xC + 16 + 0x0040 + + + QERR + Quadrature Error Flag + 0 + 1 + + + IDXERR + Index Error Flag + 1 + 1 + + + MPERR + Missing Pulse Error flag + 2 + 1 + + + WINERR + Window Error Flag + 4 + 1 + + + HERR + Hall Error Flag + 5 + 1 + + + STOP + Stop + 6 + 1 + + + DIR + Direction Status Flag + 7 + 1 + + + PRESCBUFV + Prescaler Buffer Valid + 8 + 1 + + + FILTERBUFV + Filter Buffer Valid + 9 + 1 + + + CCBUFV0 + Compare Channel 0 Buffer Valid + 12 + 1 + + + CCBUFV1 + Compare Channel 1 Buffer Valid + 13 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + CTRLB + Control B Synchronization Busy + 2 + 1 + + + STATUS + Status Synchronization Busy + 3 + 1 + + + PRESC + Prescaler Synchronization Busy + 4 + 1 + + + FILTER + Filter Synchronization Busy + 5 + 1 + + + COUNT + Count Synchronization Busy + 6 + 1 + + + CC0 + Compare Channel 0 Synchronization Busy + 7 + 1 + + + CC1 + Compare Channel 1 Synchronization Busy + 8 + 1 + + + + + PRESC + Prescaler Value + 0x14 + 8 + 0x00 + + + PRESC + Prescaler Value + 0 + 4 + + PRESCSelect + + DIV1 + No division + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + DIV256 + Divide by 256 + 8 + + + DIV512 + Divide by 512 + 9 + + + DIV1024 + Divide by 1024 + 10 + + + + + + + FILTER + Filter Value + 0x15 + 8 + 0x00 + + + FILTER + Filter Value + 0 + 8 + + + + + PRESCBUF + Prescaler Buffer Value + 0x18 + 8 + 0x00 + + + PRESCBUF + Prescaler Buffer Value + 0 + 4 + + PRESCBUFSelect + + DIV1 + No division + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + DIV256 + Divide by 256 + 8 + + + DIV512 + Divide by 512 + 9 + + + DIV1024 + Divide by 1024 + 10 + + + + + + + FILTERBUF + Filter Buffer Value + 0x19 + 8 + 0x00 + + + FILTERBUF + Filter Buffer Value + 0 + 8 + + + + + COUNT + Counter Value + 0x1C + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 16 + + + + + 2 + 4 + CC[%s] + Channel n Compare Value + 0x20 + 32 + 0x00000000 + + + CC + Channel Compare Value + 0 + 16 + + + + + 2 + 4 + CCBUF[%s] + Channel Compare Buffer Value + 0x30 + 32 + 0x00000000 + + + CCBUF + Channel Compare Buffer Value + 0 + 16 + + + + + + + PM + U24061.0.0 + Power Manager + PM + PM_ + 0x40000400 + + 0 + 0x13 + registers + + + PM + 0 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + IORET + I/O Retention + 2 + 1 + + + + + SLEEPCFG + Sleep Configuration + 0x1 + 8 + 0x02 + + + SLEEPMODE + Sleep Mode + 0 + 3 + + SLEEPMODESelect + + IDLE + CPU, AHBx, and APBx clocks are OFF + 2 + + + STANDBY + All Clocks are OFF + 4 + + + HIBERNATE + Backup domain is ON as well as some PDRAMs + 5 + + + BACKUP + Only Backup domain is powered ON + 6 + + + OFF + All power domains are powered OFF + 7 + + + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + SLEEPRDY + Sleep Mode Entry Ready Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + SLEEPRDY + Sleep Mode Entry Ready Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + SLEEPRDY + Sleep Mode Entry Ready + 0 + 1 + + + + + STDBYCFG + Standby Configuration + 0x8 + 8 + 0x00 + + + RAMCFG + Ram Configuration + 0 + 2 + + RAMCFGSelect + + RET + All the system RAM is retained + 0 + + + PARTIAL + Only the first 32Kbytes of the system RAM is retained + 1 + + + OFF + All the system RAM is turned OFF + 2 + + + + + FASTWKUP + Fast Wakeup + 4 + 2 + + FASTWKUPSelect + + NO + Fast Wakeup is disabled + 0 + + + NVM + Fast Wakeup is enabled on NVM + 1 + + + MAINVREG + Fast Wakeup is enabled on the main voltage regulator (MAINVREG) + 2 + + + BOTH + Fast Wakeup is enabled on both NVM and MAINVREG + 3 + + + + + + + HIBCFG + Hibernate Configuration + 0x9 + 8 + 0x00 + + + RAMCFG + Ram Configuration + 0 + 2 + + RAMCFGSelect + + RET + All the system RAM is retained + 0 + + + PARTIAL + Only the first 32Kbytes of the system RAM is retained + 1 + + + OFF + All the system RAM is turned OFF + 2 + + + + + BRAMCFG + Backup Ram Configuration + 2 + 2 + + BRAMCFGSelect + + RET + All the backup RAM is retained + 0 + + + PARTIAL + Only the first 4Kbytes of the backup RAM is retained + 1 + + + OFF + All the backup RAM is turned OFF + 2 + + + + + + + BKUPCFG + Backup Configuration + 0xA + 8 + 0x00 + + + BRAMCFG + Ram Configuration + 0 + 2 + + BRAMCFGSelect + + RET + All the backup RAM is retained + 0 + + + PARTIAL + Only the first 4Kbytes of the backup RAM is retained + 1 + + + OFF + All the backup RAM is turned OFF + 2 + + + + + + + PWSAKDLY + Power Switch Acknowledge Delay + 0x12 + 8 + 0x00 + + + DLYVAL + Delay Value + 0 + 7 + + + IGNACK + Ignore Acknowledge + 7 + 1 + + + + + + + PORT + U22102.2.0 + Port Module + PORT + PORT_ + 0x41008000 + + 0 + 0x100 + registers + + + + 2 + 0x80 + GROUP[%s] + + 0x00 + + DIR + Data Direction + 0x0 + 32 + 0x00000000 + + + DIR + Port Data Direction + 0 + 32 + + + + + DIRCLR + Data Direction Clear + 0x4 + 32 + 0x00000000 + + + DIRCLR + Port Data Direction Clear + 0 + 32 + + + + + DIRSET + Data Direction Set + 0x8 + 32 + 0x00000000 + + + DIRSET + Port Data Direction Set + 0 + 32 + + + + + DIRTGL + Data Direction Toggle + 0xC + 32 + 0x00000000 + + + DIRTGL + Port Data Direction Toggle + 0 + 32 + + + + + OUT + Data Output Value + 0x10 + 32 + 0x00000000 + + + OUT + PORT Data Output Value + 0 + 32 + + + + + OUTCLR + Data Output Value Clear + 0x14 + 32 + 0x00000000 + + + OUTCLR + PORT Data Output Value Clear + 0 + 32 + + + + + OUTSET + Data Output Value Set + 0x18 + 32 + 0x00000000 + + + OUTSET + PORT Data Output Value Set + 0 + 32 + + + + + OUTTGL + Data Output Value Toggle + 0x1C + 32 + 0x00000000 + + + OUTTGL + PORT Data Output Value Toggle + 0 + 32 + + + + + IN + Data Input Value + 0x20 + 32 + read-only + 0x00000000 + + + IN + PORT Data Input Value + 0 + 32 + + + + + CTRL + Control + 0x24 + 32 + 0x00000000 + + + SAMPLING + Input Sampling Mode + 0 + 32 + + + + + WRCONFIG + Write Configuration + 0x28 + 32 + write-only + 0x00000000 + + + PINMASK + Pin Mask for Multiple Pin Configuration + 0 + 16 + + + PMUXEN + Peripheral Multiplexer Enable + 16 + 1 + + + INEN + Input Enable + 17 + 1 + + + PULLEN + Pull Enable + 18 + 1 + + + DRVSTR + Output Driver Strength Selection + 22 + 1 + + + PMUX + Peripheral Multiplexing + 24 + 4 + + + WRPMUX + Write PMUX + 28 + 1 + + + WRPINCFG + Write PINCFG + 30 + 1 + + + HWSEL + Half-Word Select + 31 + 1 + + + + + EVCTRL + Event Input Control + 0x2C + 32 + 0x00000000 + + + PID0 + PORT Event Pin Identifier 0 + 0 + 5 + + + EVACT0 + PORT Event Action 0 + 5 + 2 + + EVACT0Select + + OUT + Event output to pin + 0x0 + + + SET + Set output register of pin on event + 0x1 + + + CLR + Clear output register of pin on event + 0x2 + + + TGL + Toggle output register of pin on event + 0x3 + + + + + PORTEI0 + PORT Event Input Enable 0 + 7 + 1 + + + PID1 + PORT Event Pin Identifier 1 + 8 + 5 + + + EVACT1 + PORT Event Action 1 + 13 + 2 + + + PORTEI1 + PORT Event Input Enable 1 + 15 + 1 + + + PID2 + PORT Event Pin Identifier 2 + 16 + 5 + + + EVACT2 + PORT Event Action 2 + 21 + 2 + + + PORTEI2 + PORT Event Input Enable 2 + 23 + 1 + + + PID3 + PORT Event Pin Identifier 3 + 24 + 5 + + + EVACT3 + PORT Event Action 3 + 29 + 2 + + + PORTEI3 + PORT Event Input Enable 3 + 31 + 1 + + + + + 16 + 1 + PMUX[%s] + Peripheral Multiplexing + 0x30 + 8 + 0x00 + + + PMUXE + Peripheral Multiplexing for Even-Numbered Pin + 0 + 4 + + + PMUXO + Peripheral Multiplexing for Odd-Numbered Pin + 4 + 4 + + + + + 32 + 1 + PINCFG[%s] + Pin Configuration + 0x40 + 8 + 0x00 + + + PMUXEN + Peripheral Multiplexer Enable + 0 + 1 + + + INEN + Input Enable + 1 + 1 + + + PULLEN + Pull Enable + 2 + 1 + + + DRVSTR + Output Driver Strength Selection + 6 + 1 + + + + + + + + QSPI + U20081.6.3 + Quad SPI interface + QSPI + QSPI_ + 0x42003400 + + 0 + 0x48 + registers + + + QSPI + 134 + + + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + LASTXFER + Last Transfer + 24 + 1 + + + + + CTRLB + Control B + 0x4 + 32 + 0x00000000 + + + MODE + Serial Memory Mode + 0 + 1 + + MODESelect + + SPI + SPI operating mode + 0 + + + MEMORY + Serial Memory operating mode + 1 + + + + + LOOPEN + Local Loopback Enable + 1 + 1 + + + WDRBT + Wait Data Read Before Transfer + 2 + 1 + + + SMEMREG + Serial Memory reg + 3 + 1 + + + CSMODE + Chip Select Mode + 4 + 2 + + CSMODESelect + + NORELOAD + The chip select is deasserted if TD has not been reloaded before the end of the current transfer. + 0x0 + + + LASTXFER + The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred. + 0x1 + + + SYSTEMATICALLY + The chip select is deasserted systematically after each transfer. + 0x2 + + + + + DATALEN + Data Length + 8 + 4 + + DATALENSelect + + 8BITS + 8-bits transfer + 0x0 + + + 9BITS + 9 bits transfer + 0x1 + + + 10BITS + 10-bits transfer + 0x2 + + + 11BITS + 11-bits transfer + 0x3 + + + 12BITS + 12-bits transfer + 0x4 + + + 13BITS + 13-bits transfer + 0x5 + + + 14BITS + 14-bits transfer + 0x6 + + + 15BITS + 15-bits transfer + 0x7 + + + 16BITS + 16-bits transfer + 0x8 + + + + + DLYBCT + Delay Between Consecutive Transfers + 16 + 8 + + + DLYCS + Minimum Inactive CS Delay + 24 + 8 + + + + + BAUD + Baud Rate + 0x8 + 32 + 0x00000000 + + + CPOL + Clock Polarity + 0 + 1 + + + CPHA + Clock Phase + 1 + 1 + + + BAUD + Serial Clock Baud Rate + 8 + 8 + + + DLYBS + Delay Before SCK + 16 + 8 + + + + + RXDATA + Receive Data + 0xC + 32 + read-only + 0x00000000 + + + DATA + Receive Data + 0 + 16 + + + + + TXDATA + Transmit Data + 0x10 + 32 + write-only + 0x00000000 + + + DATA + Transmit Data + 0 + 16 + + + + + INTENCLR + Interrupt Enable Clear + 0x14 + 32 + 0x00000000 + + + RXC + Receive Data Register Full Interrupt Disable + 0 + 1 + + + DRE + Transmit Data Register Empty Interrupt Disable + 1 + 1 + + + TXC + Transmission Complete Interrupt Disable + 2 + 1 + + + ERROR + Overrun Error Interrupt Disable + 3 + 1 + + + CSRISE + Chip Select Rise Interrupt Disable + 8 + 1 + + + INSTREND + Instruction End Interrupt Disable + 10 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x18 + 32 + 0x00000000 + + + RXC + Receive Data Register Full Interrupt Enable + 0 + 1 + + + DRE + Transmit Data Register Empty Interrupt Enable + 1 + 1 + + + TXC + Transmission Complete Interrupt Enable + 2 + 1 + + + ERROR + Overrun Error Interrupt Enable + 3 + 1 + + + CSRISE + Chip Select Rise Interrupt Enable + 8 + 1 + + + INSTREND + Instruction End Interrupt Enable + 10 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x1C + 32 + 0x00000000 + + + RXC + Receive Data Register Full + 0 + 1 + + + DRE + Transmit Data Register Empty + 1 + 1 + + + TXC + Transmission Complete + 2 + 1 + + + ERROR + Overrun Error + 3 + 1 + + + CSRISE + Chip Select Rise + 8 + 1 + + + INSTREND + Instruction End + 10 + 1 + + + + + STATUS + Status Register + 0x20 + 32 + read-only + 0x00000200 + + + ENABLE + Enable + 1 + 1 + + + CSSTATUS + Chip Select + 9 + 1 + + + + + INSTRADDR + Instruction Address + 0x30 + 32 + 0x00000000 + + + ADDR + Instruction Address + 0 + 32 + + + + + INSTRCTRL + Instruction Code + 0x34 + 32 + 0x00000000 + + + INSTR + Instruction Code + 0 + 8 + + + OPTCODE + Option Code + 16 + 8 + + + + + INSTRFRAME + Instruction Frame + 0x38 + 32 + 0x00000000 + + + WIDTH + Instruction Code, Address, Option Code and Data Width + 0 + 3 + + WIDTHSelect + + SINGLE_BIT_SPI + Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI + 0x0 + + + DUAL_OUTPUT + Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI + 0x1 + + + QUAD_OUTPUT + Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI + 0x2 + + + DUAL_IO + Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI + 0x3 + + + QUAD_IO + Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI + 0x4 + + + DUAL_CMD + Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI + 0x5 + + + QUAD_CMD + Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI + 0x6 + + + + + INSTREN + Instruction Enable + 4 + 1 + + + ADDREN + Address Enable + 5 + 1 + + + OPTCODEEN + Option Enable + 6 + 1 + + + DATAEN + Data Enable + 7 + 1 + + + OPTCODELEN + Option Code Length + 8 + 2 + + OPTCODELENSelect + + 1BIT + 1-bit length option code + 0x0 + + + 2BITS + 2-bits length option code + 0x1 + + + 4BITS + 4-bits length option code + 0x2 + + + 8BITS + 8-bits length option code + 0x3 + + + + + ADDRLEN + Address Length + 10 + 1 + + ADDRLENSelect + + 24BITS + 24-bits address length + 0 + + + 32BITS + 32-bits address length + 1 + + + + + TFRTYPE + Data Transfer Type + 12 + 2 + + TFRTYPESelect + + READ + Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible. + 0x0 + + + READMEMORY + Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible. + 0x1 + + + WRITE + Write transfer into the serial memory.Scrambling is not performed. + 0x2 + + + WRITEMEMORY + Write data transfer into the serial memory.If enabled, scrambling is performed. + 0x3 + + + + + CRMODE + Continuous Read Mode + 14 + 1 + + + DDREN + Double Data Rate Enable + 15 + 1 + + + DUMMYLEN + Dummy Cycles Length + 16 + 5 + + + + + SCRAMBCTRL + Scrambling Mode + 0x40 + 32 + 0x00000000 + + + ENABLE + Scrambling/Unscrambling Enable + 0 + 1 + + + RANDOMDIS + Scrambling/Unscrambling Random Value Disable + 1 + 1 + + + + + SCRAMBKEY + Scrambling Key + 0x44 + 32 + write-only + 0x00000000 + + + KEY + Scrambling User Key + 0 + 32 + + + + + + + RAMECC + U22681.0.0 + RAM ECC + RAMECC + RAMECC_ + 0x41020000 + + 0 + 0x10 + registers + + + RAMECC + 45 + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 8 + 0x00 + + + SINGLEE + Single Bit ECC Error Interrupt Enable Clear + 0 + 1 + + + DUALE + Dual Bit ECC Error Interrupt Enable Clear + 1 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x1 + 8 + 0x00 + + + SINGLEE + Single Bit ECC Error Interrupt Enable Set + 0 + 1 + + + DUALE + Dual Bit ECC Error Interrupt Enable Set + 1 + 1 + + + + + INTFLAG + Interrupt Flag + 0x2 + 8 + 0x00 + + + SINGLEE + Single Bit ECC Error Interrupt + 0 + 1 + + + DUALE + Dual Bit ECC Error Interrupt + 1 + 1 + + + + + STATUS + Status + 0x3 + 8 + read-only + 0x00 + + + ECCDIS + ECC Disable + 0 + 1 + + + + + ERRADDR + Error Address + 0x4 + 32 + read-only + 0x00000000 + + + ERRADDR + Error Address + 0 + 17 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + ECCDIS + ECC Disable + 0 + 1 + + + ECCELOG + ECC Error Log + 1 + 1 + + + + + + + RSTC + U22394.0.0 + Reset Controller + RSTC + RSTC_ + 0x40000C00 + + 0 + 0x3 + registers + + + + RCAUSE + Reset Cause + 0x0 + 8 + read-only + + + POR + Power On Reset + 0 + 1 + + + BODCORE + Brown Out CORE Detector Reset + 1 + 1 + + + BODVDD + Brown Out VDD Detector Reset + 2 + 1 + + + NVM + NVM Reset + 3 + 1 + + + EXT + External Reset + 4 + 1 + + + WDT + Watchdog Reset + 5 + 1 + + + SYST + System Reset Request + 6 + 1 + + + BACKUP + Backup Reset + 7 + 1 + + + + + BKUPEXIT + Backup Exit Source + 0x2 + 8 + read-only + 0x00 + + + RTC + Real Timer Counter Interrupt + 1 + 1 + + + BBPS + Battery Backup Power Switch + 2 + 1 + + + HIB + Hibernate + 7 + 1 + + + + + + + RTC + U22502.1.0 + Real-Time Counter + RTC + RTC_ + 0x40002400 + + 0 + 0xA0 + registers + + + RTC + 11 + + + + MODE0 + 32-bit Counter with Single 32-bit Compare + RtcMode0 + 0x0 + + CTRLA + MODE0 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + BKTRST + BKUP Registers Reset On Tamper Enable + 13 + 1 + + + GPTRST + GP Registers Reset On Tamper Enable + 14 + 1 + + + COUNTSYNC + Count Read Synchronization Enable + 15 + 1 + + + + + CTRLB + MODE0 Control B + 0x2 + 16 + 0x0000 + + + GP0EN + General Purpose 0 Enable + 0 + 1 + + + GP2EN + General Purpose 2 Enable + 1 + 1 + + + DEBMAJ + Debouncer Majority Enable + 4 + 1 + + + DEBASYNC + Debouncer Asynchronous Enable + 5 + 1 + + + RTCOUT + RTC Output Enable + 6 + 1 + + + DMAEN + DMA Enable + 7 + 1 + + + DEBF + Debounce Freqnuency + 8 + 3 + + DEBFSelect + + DIV2 + CLK_RTC_DEB = CLK_RTC/2 + 0x0 + + + DIV4 + CLK_RTC_DEB = CLK_RTC/4 + 0x1 + + + DIV8 + CLK_RTC_DEB = CLK_RTC/8 + 0x2 + + + DIV16 + CLK_RTC_DEB = CLK_RTC/16 + 0x3 + + + DIV32 + CLK_RTC_DEB = CLK_RTC/32 + 0x4 + + + DIV64 + CLK_RTC_DEB = CLK_RTC/64 + 0x5 + + + DIV128 + CLK_RTC_DEB = CLK_RTC/128 + 0x6 + + + DIV256 + CLK_RTC_DEB = CLK_RTC/256 + 0x7 + + + + + ACTF + Active Layer Freqnuency + 12 + 3 + + ACTFSelect + + DIV2 + CLK_RTC_OUT = CLK_RTC/2 + 0x0 + + + DIV4 + CLK_RTC_OUT = CLK_RTC/4 + 0x1 + + + DIV8 + CLK_RTC_OUT = CLK_RTC/8 + 0x2 + + + DIV16 + CLK_RTC_OUT = CLK_RTC/16 + 0x3 + + + DIV32 + CLK_RTC_OUT = CLK_RTC/32 + 0x4 + + + DIV64 + CLK_RTC_OUT = CLK_RTC/64 + 0x5 + + + DIV128 + CLK_RTC_OUT = CLK_RTC/128 + 0x6 + + + DIV256 + CLK_RTC_OUT = CLK_RTC/256 + 0x7 + + + + + + + EVCTRL + MODE0 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + CMPEO1 + Compare 1 Event Output Enable + 9 + 1 + + + TAMPEREO + Tamper Event Output Enable + 14 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + TAMPEVEI + Tamper Event Input Enable + 16 + 1 + + + + + INTENCLR + MODE0 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + TAMPER + Tamper Enable + 14 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE0 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + TAMPER + Tamper Enable + 14 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE0 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + CMP0 + Compare 0 + 8 + 1 + + + CMP1 + Compare 1 + 9 + 1 + + + TAMPER + Tamper + 14 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE0 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + COUNT + COUNT Register Busy + 3 + 1 + + + COMP0 + COMP 0 Register Busy + 5 + 1 + + + COMP1 + COMP 1 Register Busy + 6 + 1 + + + COUNTSYNC + Count Synchronization Enable Bit Busy + 15 + 1 + + + GP0 + General Purpose 0 Register Busy + 16 + 1 + + + GP1 + General Purpose 1 Register Busy + 17 + 1 + + + GP2 + General Purpose 2 Register Busy + 18 + 1 + + + GP3 + General Purpose 3 Register Busy + 19 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE0 Counter Value + 0x18 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + 2 + 4 + COMP[%s] + MODE0 Compare n Value + 0x20 + 32 + 0x00000000 + + + COMP + Compare Value + 0 + 32 + + + + + 4 + 4 + GP[%s] + General Purpose + 0x40 + 32 + 0x00000000 + + + GP + General Purpose + 0 + 32 + + + + + TAMPCTRL + Tamper Control + 0x60 + 32 + 0x00000000 + + + IN0ACT + Tamper Input 0 Action + 0 + 2 + + IN0ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN0 to OUT + 0x3 + + + + + IN1ACT + Tamper Input 1 Action + 2 + 2 + + IN1ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN1 to OUT + 0x3 + + + + + IN2ACT + Tamper Input 2 Action + 4 + 2 + + IN2ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN2 to OUT + 0x3 + + + + + IN3ACT + Tamper Input 3 Action + 6 + 2 + + IN3ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN3 to OUT + 0x3 + + + + + IN4ACT + Tamper Input 4 Action + 8 + 2 + + IN4ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN4 to OUT + 0x3 + + + + + TAMLVL0 + Tamper Level Select 0 + 16 + 1 + + + TAMLVL1 + Tamper Level Select 1 + 17 + 1 + + + TAMLVL2 + Tamper Level Select 2 + 18 + 1 + + + TAMLVL3 + Tamper Level Select 3 + 19 + 1 + + + TAMLVL4 + Tamper Level Select 4 + 20 + 1 + + + DEBNC0 + Debouncer Enable 0 + 24 + 1 + + + DEBNC1 + Debouncer Enable 1 + 25 + 1 + + + DEBNC2 + Debouncer Enable 2 + 26 + 1 + + + DEBNC3 + Debouncer Enable 3 + 27 + 1 + + + DEBNC4 + Debouncer Enable 4 + 28 + 1 + + + + + TIMESTAMP + MODE0 Timestamp + 0x64 + 32 + read-only + 0x00000000 + + + COUNT + Count Timestamp Value + 0 + 32 + + + + + TAMPID + Tamper ID + 0x68 + 32 + 0x00000000 + + + TAMPID0 + Tamper Input 0 Detected + 0 + 1 + + + TAMPID1 + Tamper Input 1 Detected + 1 + 1 + + + TAMPID2 + Tamper Input 2 Detected + 2 + 1 + + + TAMPID3 + Tamper Input 3 Detected + 3 + 1 + + + TAMPID4 + Tamper Input 4 Detected + 4 + 1 + + + TAMPEVT + Tamper Event Detected + 31 + 1 + + + + + 8 + 4 + BKUP[%s] + Backup + 0x80 + 32 + 0x00000000 + + + BKUP + Backup + 0 + 32 + + + + + + MODE1 + 16-bit Counter with Two 16-bit Compares + MODE0 + RtcMode1 + 0x0 + + CTRLA + MODE1 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0 + + + COUNT16 + Mode 1: 16-bit Counter + 1 + + + CLOCK + Mode 2: Clock/Calendar + 2 + + + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + BKTRST + BKUP Registers Reset On Tamper Enable + 13 + 1 + + + GPTRST + GP Registers Reset On Tamper Enable + 14 + 1 + + + COUNTSYNC + Count Read Synchronization Enable + 15 + 1 + + + + + CTRLB + MODE1 Control B + 0x2 + 16 + 0x0000 + + + GP0EN + General Purpose 0 Enable + 0 + 1 + + + GP2EN + General Purpose 2 Enable + 1 + 1 + + + DEBMAJ + Debouncer Majority Enable + 4 + 1 + + + DEBASYNC + Debouncer Asynchronous Enable + 5 + 1 + + + RTCOUT + RTC Output Enable + 6 + 1 + + + DMAEN + DMA Enable + 7 + 1 + + + DEBF + Debounce Freqnuency + 8 + 3 + + DEBFSelect + + DIV2 + CLK_RTC_DEB = CLK_RTC/2 + 0x0 + + + DIV4 + CLK_RTC_DEB = CLK_RTC/4 + 0x1 + + + DIV8 + CLK_RTC_DEB = CLK_RTC/8 + 0x2 + + + DIV16 + CLK_RTC_DEB = CLK_RTC/16 + 0x3 + + + DIV32 + CLK_RTC_DEB = CLK_RTC/32 + 0x4 + + + DIV64 + CLK_RTC_DEB = CLK_RTC/64 + 0x5 + + + DIV128 + CLK_RTC_DEB = CLK_RTC/128 + 0x6 + + + DIV256 + CLK_RTC_DEB = CLK_RTC/256 + 0x7 + + + + + ACTF + Active Layer Freqnuency + 12 + 3 + + ACTFSelect + + DIV2 + CLK_RTC_OUT = CLK_RTC/2 + 0x0 + + + DIV4 + CLK_RTC_OUT = CLK_RTC/4 + 0x1 + + + DIV8 + CLK_RTC_OUT = CLK_RTC/8 + 0x2 + + + DIV16 + CLK_RTC_OUT = CLK_RTC/16 + 0x3 + + + DIV32 + CLK_RTC_OUT = CLK_RTC/32 + 0x4 + + + DIV64 + CLK_RTC_OUT = CLK_RTC/64 + 0x5 + + + DIV128 + CLK_RTC_OUT = CLK_RTC/128 + 0x6 + + + DIV256 + CLK_RTC_OUT = CLK_RTC/256 + 0x7 + + + + + + + EVCTRL + MODE1 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + CMPEO1 + Compare 1 Event Output Enable + 9 + 1 + + + CMPEO2 + Compare 2 Event Output Enable + 10 + 1 + + + CMPEO3 + Compare 3 Event Output Enable + 11 + 1 + + + TAMPEREO + Tamper Event Output Enable + 14 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + TAMPEVEI + Tamper Event Input Enable + 16 + 1 + + + + + INTENCLR + MODE1 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + CMP2 + Compare 2 Interrupt Enable + 10 + 1 + + + CMP3 + Compare 3 Interrupt Enable + 11 + 1 + + + TAMPER + Tamper Enable + 14 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE1 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + CMP2 + Compare 2 Interrupt Enable + 10 + 1 + + + CMP3 + Compare 3 Interrupt Enable + 11 + 1 + + + TAMPER + Tamper Enable + 14 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE1 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + CMP0 + Compare 0 + 8 + 1 + + + CMP1 + Compare 1 + 9 + 1 + + + CMP2 + Compare 2 + 10 + 1 + + + CMP3 + Compare 3 + 11 + 1 + + + TAMPER + Tamper + 14 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE1 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Bit Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + COUNT + COUNT Register Busy + 3 + 1 + + + PER + PER Register Busy + 4 + 1 + + + COMP0 + COMP 0 Register Busy + 5 + 1 + + + COMP1 + COMP 1 Register Busy + 6 + 1 + + + COMP2 + COMP 2 Register Busy + 7 + 1 + + + COMP3 + COMP 3 Register Busy + 8 + 1 + + + COUNTSYNC + Count Synchronization Enable Bit Busy + 15 + 1 + + + GP0 + General Purpose 0 Register Busy + 16 + 1 + + + GP1 + General Purpose 1 Register Busy + 17 + 1 + + + GP2 + General Purpose 2 Register Busy + 18 + 1 + + + GP3 + General Purpose 3 Register Busy + 19 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE1 Counter Value + 0x18 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + PER + MODE1 Counter Period + 0x1C + 16 + 0x0000 + + + PER + Counter Period + 0 + 16 + + + + + 4 + 2 + COMP[%s] + MODE1 Compare n Value + 0x20 + 16 + 0x0000 + + + COMP + Compare Value + 0 + 16 + + + + + 4 + 4 + GP[%s] + General Purpose + 0x40 + 32 + 0x00000000 + + + GP + General Purpose + 0 + 32 + + + + + TAMPCTRL + Tamper Control + 0x60 + 32 + 0x00000000 + + + IN0ACT + Tamper Input 0 Action + 0 + 2 + + IN0ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN0 to OUT + 0x3 + + + + + IN1ACT + Tamper Input 1 Action + 2 + 2 + + IN1ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN1 to OUT + 0x3 + + + + + IN2ACT + Tamper Input 2 Action + 4 + 2 + + IN2ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN2 to OUT + 0x3 + + + + + IN3ACT + Tamper Input 3 Action + 6 + 2 + + IN3ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN3 to OUT + 0x3 + + + + + IN4ACT + Tamper Input 4 Action + 8 + 2 + + IN4ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN4 to OUT + 0x3 + + + + + TAMLVL0 + Tamper Level Select 0 + 16 + 1 + + + TAMLVL1 + Tamper Level Select 1 + 17 + 1 + + + TAMLVL2 + Tamper Level Select 2 + 18 + 1 + + + TAMLVL3 + Tamper Level Select 3 + 19 + 1 + + + TAMLVL4 + Tamper Level Select 4 + 20 + 1 + + + DEBNC0 + Debouncer Enable 0 + 24 + 1 + + + DEBNC1 + Debouncer Enable 1 + 25 + 1 + + + DEBNC2 + Debouncer Enable 2 + 26 + 1 + + + DEBNC3 + Debouncer Enable 3 + 27 + 1 + + + DEBNC4 + Debouncer Enable 4 + 28 + 1 + + + + + TIMESTAMP + MODE1 Timestamp + 0x64 + 32 + read-only + 0x00000000 + + + COUNT + Count Timestamp Value + 0 + 16 + + + + + TAMPID + Tamper ID + 0x68 + 32 + 0x00000000 + + + TAMPID0 + Tamper Input 0 Detected + 0 + 1 + + + TAMPID1 + Tamper Input 1 Detected + 1 + 1 + + + TAMPID2 + Tamper Input 2 Detected + 2 + 1 + + + TAMPID3 + Tamper Input 3 Detected + 3 + 1 + + + TAMPID4 + Tamper Input 4 Detected + 4 + 1 + + + TAMPEVT + Tamper Event Detected + 31 + 1 + + + + + 8 + 4 + BKUP[%s] + Backup + 0x80 + 32 + 0x00000000 + + + BKUP + Backup + 0 + 32 + + + + + + MODE2 + Clock/Calendar with Alarm + MODE0 + RtcMode2 + 0x0 + + CTRLA + MODE2 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0 + + + COUNT16 + Mode 1: 16-bit Counter + 1 + + + CLOCK + Mode 2: Clock/Calendar + 2 + + + + + CLKREP + Clock Representation + 6 + 1 + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + BKTRST + BKUP Registers Reset On Tamper Enable + 13 + 1 + + + GPTRST + GP Registers Reset On Tamper Enable + 14 + 1 + + + CLOCKSYNC + Clock Read Synchronization Enable + 15 + 1 + + + + + CTRLB + MODE2 Control B + 0x2 + 16 + 0x0000 + + + GP0EN + General Purpose 0 Enable + 0 + 1 + + + GP2EN + General Purpose 2 Enable + 1 + 1 + + + DEBMAJ + Debouncer Majority Enable + 4 + 1 + + + DEBASYNC + Debouncer Asynchronous Enable + 5 + 1 + + + RTCOUT + RTC Output Enable + 6 + 1 + + + DMAEN + DMA Enable + 7 + 1 + + + DEBF + Debounce Freqnuency + 8 + 3 + + DEBFSelect + + DIV2 + CLK_RTC_DEB = CLK_RTC/2 + 0x0 + + + DIV4 + CLK_RTC_DEB = CLK_RTC/4 + 0x1 + + + DIV8 + CLK_RTC_DEB = CLK_RTC/8 + 0x2 + + + DIV16 + CLK_RTC_DEB = CLK_RTC/16 + 0x3 + + + DIV32 + CLK_RTC_DEB = CLK_RTC/32 + 0x4 + + + DIV64 + CLK_RTC_DEB = CLK_RTC/64 + 0x5 + + + DIV128 + CLK_RTC_DEB = CLK_RTC/128 + 0x6 + + + DIV256 + CLK_RTC_DEB = CLK_RTC/256 + 0x7 + + + + + ACTF + Active Layer Freqnuency + 12 + 3 + + ACTFSelect + + DIV2 + CLK_RTC_OUT = CLK_RTC/2 + 0x0 + + + DIV4 + CLK_RTC_OUT = CLK_RTC/4 + 0x1 + + + DIV8 + CLK_RTC_OUT = CLK_RTC/8 + 0x2 + + + DIV16 + CLK_RTC_OUT = CLK_RTC/16 + 0x3 + + + DIV32 + CLK_RTC_OUT = CLK_RTC/32 + 0x4 + + + DIV64 + CLK_RTC_OUT = CLK_RTC/64 + 0x5 + + + DIV128 + CLK_RTC_OUT = CLK_RTC/128 + 0x6 + + + DIV256 + CLK_RTC_OUT = CLK_RTC/256 + 0x7 + + + + + + + EVCTRL + MODE2 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + ALARMEO0 + Alarm 0 Event Output Enable + 8 + 1 + + + ALARMEO1 + Alarm 1 Event Output Enable + 9 + 1 + + + TAMPEREO + Tamper Event Output Enable + 14 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + TAMPEVEI + Tamper Event Input Enable + 16 + 1 + + + + + INTENCLR + MODE2 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + ALARM0 + Alarm 0 Interrupt Enable + 8 + 1 + + + ALARM1 + Alarm 1 Interrupt Enable + 9 + 1 + + + TAMPER + Tamper Enable + 14 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE2 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Enable + 7 + 1 + + + ALARM0 + Alarm 0 Interrupt Enable + 8 + 1 + + + ALARM1 + Alarm 1 Interrupt Enable + 9 + 1 + + + TAMPER + Tamper Enable + 14 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE2 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + ALARM0 + Alarm 0 + 8 + 1 + + + ALARM1 + Alarm 1 + 9 + 1 + + + TAMPER + Tamper + 14 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE2 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Bit Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + CLOCK + CLOCK Register Busy + 3 + 1 + + + ALARM0 + ALARM 0 Register Busy + 5 + 1 + + + ALARM1 + ALARM 1 Register Busy + 6 + 1 + + + MASK0 + MASK 0 Register Busy + 11 + 1 + + + MASK1 + MASK 1 Register Busy + 12 + 1 + + + CLOCKSYNC + Clock Synchronization Enable Bit Busy + 15 + 1 + + + GP0 + General Purpose 0 Register Busy + 16 + 1 + + + GP1 + General Purpose 1 Register Busy + 17 + 1 + + + GP2 + General Purpose 2 Register Busy + 18 + 1 + + + GP3 + General Purpose 3 Register Busy + 19 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + CLOCK + MODE2 Clock Value + 0x18 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + AM when CLKREP in 12-hour + 0x00 + + + PM + PM when CLKREP in 12-hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + 4 + 4 + GP[%s] + General Purpose + 0x40 + 32 + 0x00000000 + + + GP + General Purpose + 0 + 32 + + + + + ALARM0 + MODE2_ALARM Alarm n Value + 0x20 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + Morning hour + 0x00 + + + PM + Afternoon hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + MASK0 + MODE2_ALARM Alarm n Mask + 0x24 + 8 + 0x00 + + + SEL + Alarm Mask Selection + 0 + 3 + + SELSelect + + OFF + Alarm Disabled + 0x0 + + + SS + Match seconds only + 0x1 + + + MMSS + Match seconds and minutes only + 0x2 + + + HHMMSS + Match seconds, minutes, and hours only + 0x3 + + + DDHHMMSS + Match seconds, minutes, hours, and days only + 0x4 + + + MMDDHHMMSS + Match seconds, minutes, hours, days, and months only + 0x5 + + + YYMMDDHHMMSS + Match seconds, minutes, hours, days, months, and years + 0x6 + + + + + + + ALARM1 + MODE2_ALARM Alarm n Value + 0x28 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + Morning hour + 0x00 + + + PM + Afternoon hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + MASK1 + MODE2_ALARM Alarm n Mask + 0x2C + 8 + 0x00 + + + SEL + Alarm Mask Selection + 0 + 3 + + SELSelect + + OFF + Alarm Disabled + 0x0 + + + SS + Match seconds only + 0x1 + + + MMSS + Match seconds and minutes only + 0x2 + + + HHMMSS + Match seconds, minutes, and hours only + 0x3 + + + DDHHMMSS + Match seconds, minutes, hours, and days only + 0x4 + + + MMDDHHMMSS + Match seconds, minutes, hours, days, and months only + 0x5 + + + YYMMDDHHMMSS + Match seconds, minutes, hours, days, months, and years + 0x6 + + + + + + + TAMPCTRL + Tamper Control + 0x60 + 32 + 0x00000000 + + + IN0ACT + Tamper Input 0 Action + 0 + 2 + + IN0ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN0 to OUT + 0x3 + + + + + IN1ACT + Tamper Input 1 Action + 2 + 2 + + IN1ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN1 to OUT + 0x3 + + + + + IN2ACT + Tamper Input 2 Action + 4 + 2 + + IN2ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN2 to OUT + 0x3 + + + + + IN3ACT + Tamper Input 3 Action + 6 + 2 + + IN3ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN3 to OUT + 0x3 + + + + + IN4ACT + Tamper Input 4 Action + 8 + 2 + + IN4ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN4 to OUT + 0x3 + + + + + TAMLVL0 + Tamper Level Select 0 + 16 + 1 + + + TAMLVL1 + Tamper Level Select 1 + 17 + 1 + + + TAMLVL2 + Tamper Level Select 2 + 18 + 1 + + + TAMLVL3 + Tamper Level Select 3 + 19 + 1 + + + TAMLVL4 + Tamper Level Select 4 + 20 + 1 + + + DEBNC0 + Debouncer Enable 0 + 24 + 1 + + + DEBNC1 + Debouncer Enable 1 + 25 + 1 + + + DEBNC2 + Debouncer Enable 2 + 26 + 1 + + + DEBNC3 + Debouncer Enable 3 + 27 + 1 + + + DEBNC4 + Debouncer Enable 4 + 28 + 1 + + + + + TIMESTAMP + MODE2 Timestamp + 0x64 + 32 + read-only + 0x00000000 + + + SECOND + Second Timestamp Value + 0 + 6 + + + MINUTE + Minute Timestamp Value + 6 + 6 + + + HOUR + Hour Timestamp Value + 12 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and Driver Strength are controlled by Host Controller + 0 + + + AUTO + Automatic Selection by Preset Value is Enabled + 1 + + + + + + + CA0R + Capabilities 0 + 0x40 + 32 + read-only + 0x27E80080 + + + TEOCLKF + Timeout Clock Frequency + 0 + 6 + + TEOCLKFSelect + + OTHER + Get information via another method + 0 + + + + + TEOCLKU + Timeout Clock Unit + 7 + 1 + + TEOCLKUSelect + + KHZ + KHz + 0 + + + MHZ + MHz + 1 + + + + + BASECLKF + Base Clock Frequency + 8 + 8 + + BASECLKFSelect + + OTHER + Get information via another method + 0 + + + + + MAXBLKL + Max Block Length + 16 + 2 + + MAXBLKLSelect + + 512 + 512 bytes + 0 + + + 1024 + 1024 bytes + 1 + + + 2048 + 2048 bytes + 2 + + + + + ED8SUP + 8-bit Support for Embedded Device + 18 + 1 + + ED8SUPSelect + + NO + 8-bit Bus Width not Supported + 0 + + + YES + 8-bit Bus Width Supported + 1 + + + + + ADMA2SUP + ADMA2 Support + 19 + 1 + + ADMA2SUPSelect + + NO + ADMA2 not Supported + 0 + + + YES + ADMA2 Supported + 1 + + + + + HSSUP + High Speed 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Capabilities + 0x48 + 32 + read-only + 0x00000000 + + + MAXCUR33V + Maximum Current for 3.3V + 0 + 8 + + MAXCUR33VSelect + + OTHER + Get information via another method + 0 + + + 4MA + 4mA + 1 + + + 8MA + 8mA + 2 + + + 12MA + 12mA + 3 + + + + + MAXCUR30V + Maximum Current for 3.0V + 8 + 8 + + MAXCUR30VSelect + + OTHER + Get information via another method + 0 + + + 4MA + 4mA + 1 + + + 8MA + 8mA + 2 + + + 12MA + 12mA + 3 + + + + + MAXCUR18V + Maximum Current for 1.8V + 16 + 8 + + MAXCUR18VSelect + + OTHER + Get information via another method + 0 + + + 4MA + 4mA + 1 + + + 8MA + 8mA + 2 + + + 12MA + 12mA + 3 + + + + + + + FERACES + Force Event for Auto CMD Error Status + 0x50 + 16 + write-only + 0x0000 + + + ACMD12NE + Force Event for Auto CMD12 Not Executed + 0 + 1 + + ACMD12NESelect + + NO + No Interrupt + 0 + + + YES + Interrupt is generated + 1 + + + + + ACMDTEO + Force Event for Auto CMD Timeout Error + 1 + 1 + + ACMDTEOSelect + + NO + No Interrupt + 0 + + + YES + Interrupt is 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Host Controller Ver2.00 Compatible Clock Generator (Divider) + 0 + + + PROG + Programmable Clock Generator + 1 + + + + + DRVSEL + Driver Strength Select Value for Initialization + 14 + 2 + + DRVSELSelect + + B + Driver Type B is Selected + 0 + + + A + Driver Type A is Selected + 1 + + + C + Driver Type C is Selected + 2 + + + D + Driver Type D is Selected + 3 + + + + + + + SISR + Slot Interrupt Status + 0xFC + 16 + read-only + 0x20000 + + + INTSSL + Interrupt Signal for Each Slot + 0 + 1 + + + + + HCVR + Host Controller Version + 0xFE + 16 + read-only + 0x1802 + + + SVER + Spec Version + 0 + 8 + + + VVER + Vendor Version + 8 + 8 + + + + + MC1R + MMC Control 1 + 0x204 + 8 + 0x00 + + + CMDTYP + e.MMC Command Type + 0 + 2 + + CMDTYPSelect + + NORMAL + Not a MMC specific command + 0 + + + WAITIRQ + Wait IRQ Command + 1 + + + STREAM + Stream Command + 2 + + + BOOT + Boot Command + 3 + + + + + DDR + e.MMC HSDDR Mode + 3 + 1 + + + OPD + e.MMC Open Drain Mode + 4 + 1 + + + BOOTA + e.MMC Boot Acknowledge Enable + 5 + 1 + + + RSTN + e.MMC Reset Signal + 6 + 1 + + + FCD + e.MMC Force Card Detect + 7 + 1 + + + + + MC2R + MMC Control 2 + 0x205 + 8 + write-only + 0x00 + + + SRESP + e.MMC Abort Wait IRQ + 0 + 1 + + + ABOOT + e.MMC Abort Boot + 1 + 1 + + + + + ACR + AHB Control + 0x208 + 32 + 0x00000000 + + + BMAX + AHB Maximum Burst + 0 + 2 + + BMAXSelect + + INCR16 + 0 + + + INCR8 + 1 + + + INCR4 + 2 + + + SINGLE + 3 + + + + + + + CC2R + Clock Control 2 + 0x20C + 32 + 0x00000000 + + + FSDCLKD + Force SDCK Disabled + 0 + 1 + + FSDCLKDSelect + + NOEFFECT + No effect + 0 + + + DISABLE + SDCLK can be stopped at any time after DATA transfer.SDCLK enable forcing for 8 SDCLK cycles is disabled + 1 + + + + + + + CACR + Capabilities Control + 0x230 + 32 + 0x00000000 + + + CAPWREN + Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers) + 0 + 1 + + + KEY + Key (0x46) + 8 + 8 + + + + + DBGR + Debug + 0x234 + 8 + 0x00 + + + NIDBG + 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+ + + INTENSET + I2CM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + MB + Master On Bus Interrupt Enable + 0 + 1 + + + SB + Slave On Bus Interrupt Enable + 1 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + MB + Master On Bus Interrupt + 0 + 1 + + + SB + Slave On Bus Interrupt + 1 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CM Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + ARBLOST + Arbitration Lost + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + BUSSTATE + Bus State + 4 + 2 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + MEXTTOUT + Master SCL Low Extend Timeout + 8 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + LENERR + Length Error + 10 + 1 + + + + + SYNCBUSY + I2CM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + SYSOP + System Operation Synchronization Busy + 2 + 1 + + + LENGTH + Length Synchronization Busy + 4 + 1 + + + + + ADDR + I2CM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 11 + + + LENEN + Length Enable + 13 + 1 + + + HS + High Speed Mode + 14 + 1 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + LEN + Length + 16 + 8 + + + + + DATA + I2CM Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + DBGCTRL + I2CM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + I2CS + I2C Slave Mode + I2CM + SercomI2cs + 0x0 + + CTRLA + I2CS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CS Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + GCMD + PMBus Group Command + 9 + 1 + + + AACKEN + Automatic Address Acknowledge + 10 + 1 + + + AMODE + Address Mode + 14 + 2 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + CTRLC + I2CS Control C + 0x8 + 32 + 0x00000000 + + + SDASETUP + SDA Setup Time + 0 + 4 + + + DATA32B + Data 32 Bit + 24 + 1 + + DATA32BSelect + + DATA_TRANS_8BIT + Data transaction from/to DATA register are 8-bit + 0x0 + + + DATA_TRANS_32BIT + Data transaction from/to DATA register are 32-bit + 0x1 + + + + + + + INTENCLR + I2CS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + PREC + Stop Received Interrupt Disable + 0 + 1 + + + AMATCH + Address Match Interrupt Disable + 1 + 1 + + + DRDY + Data Interrupt Disable + 2 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + PREC + Stop Received Interrupt Enable + 0 + 1 + + + AMATCH + Address Match Interrupt Enable + 1 + 1 + + + DRDY + Data Interrupt Enable + 2 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + PREC + Stop Received Interrupt + 0 + 1 + + + AMATCH + Address Match Interrupt + 1 + 1 + + + DRDY + Data Interrupt + 2 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CS Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + COLL + Transmit Collision + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + DIR + Read/Write Direction + 3 + 1 + + + SR + Repeated Start + 4 + 1 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + HS + High Speed + 10 + 1 + + + LENERR + Transaction Length Error + 11 + 1 + + + + + SYNCBUSY + I2CS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + LENGTH + Length Synchronization Busy + 4 + 1 + + + + + LENGTH + I2CS Length + 0x22 + 16 + 0x0000 + + + LEN + Data Length + 0 + 8 + + + LENEN + Data Length Enable + 8 + 1 + + + + + ADDR + I2CS Address + 0x24 + 32 + 0x00000000 + + + GENCEN + General Call Address Enable + 0 + 1 + + + ADDR + Address Value + 1 + 10 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + ADDRMASK + Address Mask + 17 + 10 + + + + + DATA + I2CS Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 32 + + + + + + SPIS + SPI Slave Mode + I2CM + SercomSpis + 0x0 + + CTRLA + SPIS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] is used as data input + 0x0 + + + PAD1 + SERCOM PAD[1] is used as data input + 0x1 + + + PAD2 + SERCOM PAD[2] is used as data input + 0x2 + + + PAD3 + SERCOM PAD[3] is used as data input + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIS Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + CTRLC + SPIS Control C + 0x8 + 32 + 0x00000000 + + + ICSPACE + Inter-Character Spacing + 0 + 6 + + + DATA32B + Data 32 Bit + 24 + 1 + + DATA32BSelect + + DATA_TRANS_8BIT + Transaction from and to DATA register are 8-bit + 0x0 + + + DATA_TRANS_32BIT + Transaction from and to DATA register are 32-bit + 0x1 + + + + + + + BAUD + SPIS Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIS Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + LENERR + Transaction Length Error + 11 + 1 + + + + + SYNCBUSY + SPIS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + LENGTH + LENGTH Synchronization Busy + 4 + 1 + + + + + LENGTH + SPIS Length + 0x22 + 16 + 0x0000 + + + LEN + Data Length + 0 + 8 + + + LENEN + Data Length Enable + 8 + 1 + + + + + ADDR + SPIS Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIS Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 32 + + + + + DBGCTRL + SPIS Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + SPIM + SPI Master Mode + I2CM + SercomSpim + 0x0 + + CTRLA + SPIM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] is used as data input + 0x0 + + + PAD1 + SERCOM PAD[1] is used as data input + 0x1 + + + PAD2 + SERCOM PAD[2] is used as data input + 0x2 + + + PAD3 + SERCOM PAD[3] is used as data input + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIM Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + CTRLC + SPIM Control C + 0x8 + 32 + 0x00000000 + + + ICSPACE + Inter-Character Spacing + 0 + 6 + + + DATA32B + Data 32 Bit + 24 + 1 + + DATA32BSelect + + DATA_TRANS_8BIT + Transaction from and to DATA register are 8-bit + 0x0 + + + DATA_TRANS_32BIT + Transaction from and to DATA register are 32-bit + 0x1 + + + + + + + BAUD + SPIM Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIM Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + LENERR + Transaction Length Error + 11 + 1 + + + + + SYNCBUSY + SPIM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + LENGTH + LENGTH Synchronization Busy + 4 + 1 + + + + + LENGTH + SPIM Length + 0x22 + 16 + 0x0000 + + + LEN + Data Length + 0 + 8 + + + LENEN + Data Length Enable + 8 + 1 + + + + + ADDR + SPIM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIM Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 32 + + + + + DBGCTRL + SPIM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_EXT + USART EXTERNAL CLOCK Mode + I2CM + SercomUsart_ext + 0x0 + + CTRLA + USART_EXT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + TXINV + Transmit Data Invert + 9 + 1 + + + RXINV + Receive Data Invert + 10 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + SERCOM PAD[0] is used for data transmission + 0x0 + + + PAD3 + SERCOM_PAD[0] is used for data transmission + 0x3 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_LIN_MASTER_MODE + LIN Master - Break and sync generation + 0x2 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + USART_FRAME_ISO_7816 + ISO 7816 + 0x7 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_EXT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + LINCMD + LIN Command + 24 + 2 + + + + + CTRLC + USART_EXT Control C + 0x8 + 32 + 0x00000000 + + + GTIME + Guard Time + 0 + 3 + + + BRKLEN + LIN Master Break Length + 8 + 2 + + + HDRDLY + LIN Master Header Delay + 10 + 2 + + + INACK + Inhibit Not Acknowledge + 16 + 1 + + + DSNACK + Disable Successive NACK + 17 + 1 + + + MAXITER + Maximum Iterations + 20 + 3 + + + DATA32B + Data 32 Bit + 24 + 2 + + DATA32BSelect + + DATA_READ_WRITE_CHSIZE + Data reads and writes according CTRLB.CHSIZE + 0x0 + + + DATA_READ_CHSIZE_WRITE_32BIT + Data reads according CTRLB.CHSIZE and writes according 32-bit extension + 0x1 + + + DATA_READ_32BIT_WRITE_CHSIZE + Data reads according 32-bit extension and writes according CTRLB.CHSIZE + 0x2 + + + DATA_READ_WRITE_32BIT + Data reads and writes according 32-bit extension + 0x3 + + + + + + + BAUD + USART_EXT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_EXT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_EXT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_EXT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_EXT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_EXT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + ITER + Maximum Number of Repetitions Reached + 7 + 1 + + + + + SYNCBUSY + USART_EXT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + RXERRCNT + RXERRCNT Synchronization Busy + 3 + 1 + + + LENGTH + LENGTH Synchronization Busy + 4 + 1 + + + + + RXERRCNT + USART_EXT Receive Error Count + 0x20 + 8 + read-only + 0x00 + + + LENGTH + USART_EXT Length + 0x22 + 16 + 0x0000 + + + LEN + Data Length + 0 + 8 + + + LENEN + Data Length Enable + 8 + 2 + + + + + DATA + USART_EXT Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 32 + + + + + DBGCTRL + USART_EXT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_INT + USART INTERNAL CLOCK Mode + I2CM + SercomUsart_int + 0x0 + + CTRLA + USART_INT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + TXINV + Transmit Data Invert + 9 + 1 + + + RXINV + Receive Data Invert + 10 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + SERCOM PAD[0] is used for data transmission + 0x0 + + + PAD3 + SERCOM_PAD[0] is used for data transmission + 0x3 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_LIN_MASTER_MODE + LIN Master - Break and sync generation + 0x2 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + USART_FRAME_ISO_7816 + ISO 7816 + 0x7 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_INT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + LINCMD + LIN Command + 24 + 2 + + + + + CTRLC + USART_INT Control C + 0x8 + 32 + 0x00000000 + + + GTIME + Guard Time + 0 + 3 + + + BRKLEN + LIN Master Break Length + 8 + 2 + + + HDRDLY + LIN Master Header Delay + 10 + 2 + + + INACK + Inhibit Not Acknowledge + 16 + 1 + + + DSNACK + Disable Successive NACK + 17 + 1 + + + MAXITER + Maximum Iterations + 20 + 3 + + + DATA32B + Data 32 Bit + 24 + 2 + + DATA32BSelect + + DATA_READ_WRITE_CHSIZE + Data reads and writes according CTRLB.CHSIZE + 0x0 + + + DATA_READ_CHSIZE_WRITE_32BIT + Data reads according CTRLB.CHSIZE and writes according 32-bit extension + 0x1 + + + DATA_READ_32BIT_WRITE_CHSIZE + Data reads according 32-bit extension and writes according CTRLB.CHSIZE + 0x2 + + + DATA_READ_WRITE_32BIT + Data reads and writes according 32-bit extension + 0x3 + + + + + + + BAUD + USART_INT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_INT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_INT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_INT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_INT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_INT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + ITER + Maximum Number of Repetitions Reached + 7 + 1 + + + + + SYNCBUSY + USART_INT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + RXERRCNT + RXERRCNT Synchronization Busy + 3 + 1 + + + LENGTH + LENGTH Synchronization Busy + 4 + 1 + + + + + RXERRCNT + USART_INT Receive Error Count + 0x20 + 8 + read-only + 0x00 + + + LENGTH + USART_INT Length + 0x22 + 16 + 0x0000 + + + LEN + Data Length + 0 + 8 + + + LENEN + Data Length Enable + 8 + 2 + + + + + DATA + USART_INT Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 32 + + + + + DBGCTRL + USART_INT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + + + SERCOM1 + 0x40003400 + + SERCOM1_0 + 50 + + + SERCOM1_1 + 51 + + + SERCOM1_2 + 52 + + + SERCOM1_OTHER + 53 + + + + SERCOM2 + 0x41012000 + + SERCOM2_0 + 54 + + + SERCOM2_1 + 55 + + + SERCOM2_2 + 56 + + + SERCOM2_OTHER + 57 + + + + SERCOM3 + 0x41014000 + + SERCOM3_0 + 58 + + + SERCOM3_1 + 59 + + + SERCOM3_2 + 60 + + + SERCOM3_OTHER + 61 + + + + SERCOM4 + 0x43000000 + + SERCOM4_0 + 62 + + + SERCOM4_1 + 63 + + + SERCOM4_2 + 64 + + + SERCOM4_OTHER + 65 + + + + SERCOM5 + 0x43000400 + + SERCOM5_0 + 66 + + + SERCOM5_1 + 67 + + + SERCOM5_2 + 68 + + + SERCOM5_OTHER + 69 + + + + SUPC + U24071.1.0 + Supply Controller + SUPC + SUPC_ + 0x40001800 + + 0 + 0x2C + registers + + + SUPC_OTHER + 8 + + + SUPC_BODDET + 9 + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + BOD33RDY + BOD33 Ready + 0 + 1 + + + BOD33DET + BOD33 Detection + 1 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 2 + 1 + + + VREGRDY + Voltage Regulator Ready + 8 + 1 + + + VCORERDY + VDDCORE Ready + 10 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + BOD33RDY + BOD33 Ready + 0 + 1 + + + BOD33DET + BOD33 Detection + 1 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 2 + 1 + + + VREGRDY + Voltage Regulator Ready + 8 + 1 + + + VCORERDY + VDDCORE Ready + 10 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + BOD33RDY + BOD33 Ready + 0 + 1 + + + BOD33DET + BOD33 Detection + 1 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 2 + 1 + + + VREGRDY + Voltage Regulator Ready + 8 + 1 + + + VCORERDY + VDDCORE Ready + 10 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + BOD33RDY + BOD33 Ready + 0 + 1 + + + BOD33DET + BOD33 Detection + 1 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 2 + 1 + + + VREGRDY + Voltage Regulator Ready + 8 + 1 + + + VCORERDY + VDDCORE Ready + 10 + 1 + + + + + BOD33 + BOD33 Control + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + ACTION + Action when Threshold Crossed + 2 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BOD33 generates a reset + 0x1 + + + INT + The BOD33 generates an interrupt + 0x2 + + + BKUP + The BOD33 puts the device in backup sleep mode + 0x3 + + + + + STDBYCFG + Configuration in Standby mode + 4 + 1 + + + RUNSTDBY + Run in Standby mode + 5 + 1 + + + RUNHIB + Run in Hibernate mode + 6 + 1 + + + RUNBKUP + Run in Backup mode + 7 + 1 + + + HYST + Hysteresis value + 8 + 4 + + + PSEL + Prescaler Select + 12 + 3 + + PSELSelect + + NODIV + Not divided + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + + + LEVEL + Threshold Level for VDD + 16 + 8 + + + VBATLEVEL + Threshold Level in battery backup sleep mode for VBAT + 24 + 8 + + + + + VREG + VREG Control + 0x18 + 32 + 0x00000002 + + + ENABLE + Enable + 1 + 1 + + + SEL + Voltage Regulator Selection + 2 + 1 + + SELSelect + + LDO + LDO selection + 0x0 + + + BUCK + Buck selection + 0x1 + + + + + RUNBKUP + Run in Backup mode + 7 + 1 + + + VSEN + Voltage Scaling Enable + 16 + 1 + + + VSPER + Voltage Scaling Period + 24 + 3 + + + + + VREF + VREF Control + 0x1C + 32 + 0x00000000 + + + TSEN + Temperature Sensor Output Enable + 1 + 1 + + + VREFOE + Voltage Reference Output Enable + 2 + 1 + + + TSSEL + Temperature Sensor Selection + 3 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + On Demand Contrl + 7 + 1 + + + SEL + Voltage Reference Selection + 16 + 4 + + SELSelect + + 1V0 + 1.0V voltage reference typical value + 0x0 + + + 1V1 + 1.1V voltage reference typical value + 0x1 + + + 1V2 + 1.2V voltage reference typical value + 0x2 + + + 1V25 + 1.25V voltage reference typical value + 0x3 + + + 2V0 + 2.0V voltage reference typical value + 0x4 + + + 2V2 + 2.2V voltage reference typical value + 0x5 + + + 2V4 + 2.4V voltage reference typical value + 0x6 + + + 2V5 + 2.5V voltage reference typical value + 0x7 + + + + + + + BBPS + Battery Backup Power Switch + 0x20 + 32 + 0x00000000 + + + CONF + Battery Backup Configuration + 0 + 1 + + CONFSelect + + BOD33 + The power switch is handled by the BOD33 + 0x0 + + + FORCED + In Backup Domain, the backup domain is always supplied by battery backup power + 0x1 + + + + + WAKEEN + Wake Enable + 2 + 1 + + + + + BKOUT + Backup Output Control + 0x24 + 32 + 0x00000000 + + + ENOUT0 + Enable OUT0 + 0 + 1 + + + ENOUT1 + Enable OUT1 + 1 + 1 + + + CLROUT0 + Clear OUT0 + 8 + 1 + + + CLROUT1 + Clear OUT1 + 9 + 1 + + + SETOUT0 + Set OUT0 + 16 + 1 + + + SETOUT1 + Set OUT1 + 17 + 1 + + + RTCTGLOUT0 + RTC Toggle OUT0 + 24 + 1 + + + RTCTGLOUT1 + RTC Toggle OUT1 + 25 + 1 + + + + + BKIN + Backup Input Control + 0x28 + 32 + read-only + 0x00000000 + + + BKIN0 + Backup Input 0 + 0 + 1 + + + BKIN1 + Backup Input 1 + 1 + 1 + + + + + + + TC0 + U22493.0.0 + Basic Timer Counter + TC + TC_ + 0x40003800 + + 0 + 0x38 + registers + + + TC0 + 107 + + + + COUNT8 + 8-bit Counter Mode + TcCount8 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + CAPTMODE0 + Capture Mode Channel 0 + 24 + 2 + + CAPTMODE0Select + + DEFAULT + Default capture + 0 + + + CAPTMIN + Minimum capture + 1 + + + CAPTMAX + Maximum capture + 2 + + + + + CAPTMODE1 + Capture mode Channel 1 + 27 + 2 + + CAPTMODE1Select + + DEFAULT + Default capture + 0 + + + CAPTMIN + Minimum capture + 1 + + + CAPTMAX + Maximum capture + 2 + + + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT8 Count + 0x14 + 8 + 0x00 + + + COUNT + Counter Value + 0 + 8 + + + + + PER + COUNT8 Period + 0x1B + 8 + 0xFF + + + PER + Period Value + 0 + 8 + + + + + 2 + 1 + CC[%s] + COUNT8 Compare and Capture + 0x1C + 8 + 0x00 + + + CC + Counter/Compare Value + 0 + 8 + + + + + PERBUF + COUNT8 Period Buffer + 0x2F + 8 + 0xFF + + + PERBUF + Period Buffer Value + 0 + 8 + + + + + 2 + 1 + CCBUF[%s] + COUNT8 Compare and Capture Buffer + 0x30 + 8 + 0x00 + + + CCBUF + Counter/Compare Buffer Value + 0 + 8 + + + + + + COUNT16 + 16-bit Counter Mode + COUNT8 + TcCount16 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + CAPTMODE0 + Capture Mode Channel 0 + 24 + 2 + + CAPTMODE0Select + + DEFAULT + Default capture + 0 + + + CAPTMIN + Minimum capture + 1 + + + CAPTMAX + Maximum capture + 2 + + + + + CAPTMODE1 + Capture mode Channel 1 + 27 + 2 + + CAPTMODE1Select + + DEFAULT + Default capture + 0 + + + CAPTMIN + Minimum capture + 1 + + + CAPTMAX + Maximum capture + 2 + + + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT16 Count + 0x14 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + 2 + 2 + CC[%s] + COUNT16 Compare and Capture + 0x1C + 16 + 0x0000 + + + CC + Counter/Compare Value + 0 + 16 + + + + + 2 + 2 + CCBUF[%s] + COUNT16 Compare and Capture Buffer + 0x30 + 16 + 0x0000 + + + CCBUF + Counter/Compare Buffer Value + 0 + 16 + + + + + + COUNT32 + 32-bit Counter Mode + COUNT8 + TcCount32 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + CAPTMODE0 + Capture Mode Channel 0 + 24 + 2 + + CAPTMODE0Select + + DEFAULT + Default capture + 0 + + + CAPTMIN + Minimum capture + 1 + + + CAPTMAX + Maximum capture + 2 + + + + + CAPTMODE1 + Capture mode Channel 1 + 27 + 2 + + CAPTMODE1Select + + DEFAULT + Default capture + 0 + + + CAPTMIN + Minimum capture + 1 + + + CAPTMAX + Maximum capture + 2 + + + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT32 Count + 0x14 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + 2 + 4 + CC[%s] + COUNT32 Compare and Capture + 0x1C + 32 + 0x00000000 + + + CC + Counter/Compare Value + 0 + 32 + + + + + 2 + 4 + CCBUF[%s] + COUNT32 Compare and Capture Buffer + 0x30 + 32 + 0x00000000 + + + CCBUF + Counter/Compare Buffer Value + 0 + 32 + + + + + + + + TC1 + 0x40003C00 + + TC1 + 108 + + + + TC2 + 0x4101A000 + + TC2 + 109 + + + + TC3 + 0x4101C000 + + TC3 + 110 + + + + TC4 + 0x42001400 + + TC4 + 111 + + + + TC5 + 0x42001800 + + TC5 + 112 + + + + TCC0 + U22133.1.0 + Timer Counter Control + TCC + TCC_ + 0x41016000 + + 0 + 0x88 + registers + + + TCC0_OTHER + 85 + + + TCC0_MC0 + 86 + + + TCC0_MC1 + 87 + + + TCC0_MC2 + 88 + + + TCC0_MC3 + 89 + + + TCC0_MC4 + 90 + + + TCC0_MC5 + 91 + + + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RESOLUTION + Enhanced Resolution + 5 + 2 + + RESOLUTIONSelect + + NONE + Dithering is disabled + 0 + + + DITH4 + Dithering is done every 16 PWM frames + 1 + + + DITH5 + Dithering is done every 32 PWM frames + 2 + + + DITH6 + Dithering is done every 64 PWM frames + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + No division + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV64 + Divide by 64 + 5 + + + DIV256 + Divide by 256 + 6 + + + DIV1024 + Divide by 1024 + 7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization Selection + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset counter on next GCLK + 0 + + + PRESC + Reload or reset counter on next prescaler clock + 1 + + + RESYNC + Reload or reset counter on next GCLK and reset prescaler counter + 2 + + + + + ALOCK + Auto Lock + 14 + 1 + + + MSYNC + Master Synchronization (only for TCC Slave Instance) + 15 + 1 + + + DMAOS + DMA One-shot Trigger Mode + 23 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 24 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 25 + 1 + + + CPTEN2 + Capture Channel 2 Enable + 26 + 1 + + + CPTEN3 + Capture Channel 3 Enable + 27 + 1 + + + CPTEN4 + Capture Channel 4 Enable + 28 + 1 + + + CPTEN5 + Capture Channel 5 Enable + 29 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update or double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update or double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + SWRST + Swrst Busy + 0 + 1 + + + ENABLE + Enable Busy + 1 + 1 + + + CTRLB + Ctrlb Busy + 2 + 1 + + + STATUS + Status Busy + 3 + 1 + + + COUNT + Count Busy + 4 + 1 + + + PATT + Pattern Busy + 5 + 1 + + + WAVE + Wave Busy + 6 + 1 + + + PER + Period Busy + 7 + 1 + + + CC0 + Compare Channel 0 Busy + 8 + 1 + + + CC1 + Compare Channel 1 Busy + 9 + 1 + + + CC2 + Compare Channel 2 Busy + 10 + 1 + + + CC3 + Compare Channel 3 Busy + 11 + 1 + + + CC4 + Compare Channel 4 Busy + 12 + 1 + + + CC5 + Compare Channel 5 Busy + 13 + 1 + + + + + FCTRLA + Recoverable Fault A Configuration + 0xC + 32 + 0x00000000 + + + SRC + Fault A Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault A Keeper + 3 + 1 + + + QUAL + Fault A Qualification + 4 + 1 + + + BLANK + Fault A Blanking Mode + 5 + 2 + + BLANKSelect + + START + Blanking applied from start of the ramp + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault A Restart + 7 + 1 + + + HALT + Fault A Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault A Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault A Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + CAPTMARK + Capture with ramp index as MSB value + 7 + + + + + BLANKPRESC + Fault A Blanking Prescaler + 15 + 1 + + + BLANKVAL + Fault A Blanking Time + 16 + 8 + + + FILTERVAL + Fault A Filter Value + 24 + 4 + + + + + FCTRLB + Recoverable Fault B Configuration + 0x10 + 32 + 0x00000000 + + + SRC + Fault B Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault B Keeper + 3 + 1 + + + QUAL + Fault B Qualification + 4 + 1 + + + BLANK + Fault B Blanking Mode + 5 + 2 + + BLANKSelect + + START + Blanking applied from start of the ramp + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault B Restart + 7 + 1 + + + HALT + Fault B Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault B Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault B Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + CAPTMARK + Capture with ramp index as MSB value + 7 + + + + + BLANKPRESC + Fault B Blanking Prescaler + 15 + 1 + + + BLANKVAL + Fault B Blanking Time + 16 + 8 + + + FILTERVAL + Fault B Filter Value + 24 + 4 + + + + + WEXCTRL + Waveform Extension Configuration + 0x14 + 32 + 0x00000000 + + + OTMX + Output Matrix + 0 + 2 + + + DTIEN0 + Dead-time Insertion Generator 0 Enable + 8 + 1 + + + DTIEN1 + Dead-time Insertion Generator 1 Enable + 9 + 1 + + + DTIEN2 + Dead-time Insertion Generator 2 Enable + 10 + 1 + + + DTIEN3 + Dead-time Insertion Generator 3 Enable + 11 + 1 + + + DTLS + Dead-time Low Side Outputs Value + 16 + 8 + + + DTHS + Dead-time High Side Outputs Value + 24 + 8 + + + + + DRVCTRL + Driver Control + 0x18 + 32 + 0x00000000 + + + NRE0 + Non-Recoverable State 0 Output Enable + 0 + 1 + + + NRE1 + Non-Recoverable State 1 Output Enable + 1 + 1 + + + NRE2 + Non-Recoverable State 2 Output Enable + 2 + 1 + + + NRE3 + Non-Recoverable State 3 Output Enable + 3 + 1 + + + NRE4 + Non-Recoverable State 4 Output Enable + 4 + 1 + + + NRE5 + Non-Recoverable State 5 Output Enable + 5 + 1 + + + NRE6 + Non-Recoverable State 6 Output Enable + 6 + 1 + + + NRE7 + Non-Recoverable State 7 Output Enable + 7 + 1 + + + NRV0 + Non-Recoverable State 0 Output Value + 8 + 1 + + + NRV1 + Non-Recoverable State 1 Output Value + 9 + 1 + + + NRV2 + Non-Recoverable State 2 Output Value + 10 + 1 + + + NRV3 + Non-Recoverable State 3 Output Value + 11 + 1 + + + NRV4 + Non-Recoverable State 4 Output Value + 12 + 1 + + + NRV5 + Non-Recoverable State 5 Output Value + 13 + 1 + + + NRV6 + Non-Recoverable State 6 Output Value + 14 + 1 + + + NRV7 + Non-Recoverable State 7 Output Value + 15 + 1 + + + INVEN0 + Output Waveform 0 Inversion + 16 + 1 + + + INVEN1 + Output Waveform 1 Inversion + 17 + 1 + + + INVEN2 + Output Waveform 2 Inversion + 18 + 1 + + + INVEN3 + Output Waveform 3 Inversion + 19 + 1 + + + INVEN4 + Output Waveform 4 Inversion + 20 + 1 + + + INVEN5 + Output Waveform 5 Inversion + 21 + 1 + + + INVEN6 + Output Waveform 6 Inversion + 22 + 1 + + + INVEN7 + Output Waveform 7 Inversion + 23 + 1 + + + FILTERVAL0 + Non-Recoverable Fault Input 0 Filter Value + 24 + 4 + + + FILTERVAL1 + Non-Recoverable Fault Input 1 Filter Value + 28 + 4 + + + + + DBGCTRL + Debug Control + 0x1E + 8 + 0x00 + + + DBGRUN + Debug Running Mode + 0 + 1 + + + FDDBD + Fault Detection on Debug Break Detection + 2 + 1 + + + + + EVCTRL + Event Control + 0x20 + 32 + 0x00000000 + + + EVACT0 + Timer/counter Input Event0 Action + 0 + 3 + + EVACT0Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or re-trigger counter on event + 1 + + + COUNTEV + Count on event + 2 + + + START + Start counter on event + 3 + + + INC + Increment counter on event + 4 + + + COUNT + Count on active state of asynchronous event + 5 + + + STAMP + Stamp capture + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + EVACT1 + Timer/counter Input Event1 Action + 3 + 3 + + EVACT1Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Re-trigger counter on event + 1 + + + DIR + Direction control + 2 + + + STOP + Stop counter on event + 3 + + + DEC + Decrement counter on event + 4 + + + PPW + Period capture value in CC0 register, pulse width capture value in CC1 register + 5 + + + PWP + Period capture value in CC1 register, pulse width capture value in CC0 register + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + CNTSEL + Timer/counter Output Event Mode + 6 + 2 + + CNTSELSelect + + START + An interrupt/event is generated when a new counter cycle starts + 0 + + + END + An interrupt/event is generated when a counter cycle ends + 1 + + + BETWEEN + An interrupt/event is generated when a counter cycle ends, except for the first and last cycles + 2 + + + BOUNDARY + An interrupt/event is generated when a new counter cycle starts or a counter cycle ends + 3 + + + + + OVFEO + Overflow/Underflow Output Event Enable + 8 + 1 + + + TRGEO + Retrigger Output Event Enable + 9 + 1 + + + CNTEO + Timer/counter Output Event Enable + 10 + 1 + + + TCINV0 + Inverted Event 0 Input Enable + 12 + 1 + + + TCINV1 + Inverted Event 1 Input Enable + 13 + 1 + + + TCEI0 + Timer/counter Event 0 Input Enable + 14 + 1 + + + TCEI1 + Timer/counter Event 1 Input Enable + 15 + 1 + + + MCEI0 + Match or Capture Channel 0 Event Input Enable + 16 + 1 + + + MCEI1 + Match or Capture Channel 1 Event Input Enable + 17 + 1 + + + MCEI2 + Match or Capture Channel 2 Event Input Enable + 18 + 1 + + + MCEI3 + Match or Capture Channel 3 Event Input Enable + 19 + 1 + + + MCEI4 + Match or Capture Channel 4 Event Input Enable + 20 + 1 + + + MCEI5 + Match or Capture Channel 5 Event Input Enable + 21 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 24 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 25 + 1 + + + MCEO2 + Match or Capture Channel 2 Event Output Enable + 26 + 1 + + + MCEO3 + Match or Capture Channel 3 Event Output Enable + 27 + 1 + + + MCEO4 + Match or Capture Channel 4 Event Output Enable + 28 + 1 + + + MCEO5 + Match or Capture Channel 5 Event Output Enable + 29 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x24 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + UFS + Non-Recoverable Update Fault Interrupt Enable + 10 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + MC4 + Match or Capture Channel 4 Interrupt Enable + 20 + 1 + + + MC5 + Match or Capture Channel 5 Interrupt Enable + 21 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x28 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + UFS + Non-Recoverable Update Fault Interrupt Enable + 10 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + MC4 + Match or Capture Channel 4 Interrupt Enable + 20 + 1 + + + MC5 + Match or Capture Channel 5 Interrupt Enable + 21 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x2C + 32 + 0x00000000 + + + OVF + Overflow + 0 + 1 + + + TRG + Retrigger + 1 + 1 + + + CNT + Counter + 2 + 1 + + + ERR + Error + 3 + 1 + + + UFS + Non-Recoverable Update Fault + 10 + 1 + + + DFS + Non-Recoverable Debug Fault + 11 + 1 + + + FAULTA + Recoverable Fault A + 12 + 1 + + + FAULTB + Recoverable Fault B + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 + 15 + 1 + + + MC0 + Match or Capture 0 + 16 + 1 + + + MC1 + Match or Capture 1 + 17 + 1 + + + MC2 + Match or Capture 2 + 18 + 1 + + + MC3 + Match or Capture 3 + 19 + 1 + + + MC4 + Match or Capture 4 + 20 + 1 + + + MC5 + Match or Capture 5 + 21 + 1 + + + + + STATUS + Status + 0x30 + 32 + 0x00000001 + + + STOP + Stop + 0 + 1 + + + IDX + Ramp + 1 + 1 + + + UFS + Non-recoverable Update Fault State + 2 + 1 + + + DFS + Non-Recoverable Debug Fault State + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + PATTBUFV + Pattern Buffer Valid + 5 + 1 + + + PERBUFV + Period Buffer Valid + 7 + 1 + + + FAULTAIN + Recoverable Fault A Input + 8 + 1 + + + FAULTBIN + Recoverable Fault B Input + 9 + 1 + + + FAULT0IN + Non-Recoverable Fault0 Input + 10 + 1 + + + FAULT1IN + Non-Recoverable Fault1 Input + 11 + 1 + + + FAULTA + Recoverable Fault A State + 12 + 1 + + + FAULTB + Recoverable Fault B State + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 State + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 State + 15 + 1 + + + CCBUFV0 + Compare Channel 0 Buffer Valid + 16 + 1 + + + CCBUFV1 + Compare Channel 1 Buffer Valid + 17 + 1 + + + CCBUFV2 + Compare Channel 2 Buffer Valid + 18 + 1 + + + CCBUFV3 + Compare Channel 3 Buffer Valid + 19 + 1 + + + CCBUFV4 + Compare Channel 4 Buffer Valid + 20 + 1 + + + CCBUFV5 + Compare Channel 5 Buffer Valid + 21 + 1 + + + CMP0 + Compare Channel 0 Value + 24 + 1 + + + CMP1 + Compare Channel 1 Value + 25 + 1 + + + CMP2 + Compare Channel 2 Value + 26 + 1 + + + CMP3 + Compare Channel 3 Value + 27 + 1 + + + CMP4 + Compare Channel 4 Value + 28 + 1 + + + CMP5 + Compare Channel 5 Value + 29 + 1 + + + + + COUNT + Count + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 24 + + + + + COUNT_DITH4_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 4 + 20 + + + + + COUNT_DITH5_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 5 + 19 + + + + + COUNT_DITH6_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 6 + 18 + + + + + PATT + Pattern + 0x38 + 16 + 0x0000 + + + PGE0 + Pattern Generator 0 Output Enable + 0 + 1 + + + PGE1 + Pattern Generator 1 Output Enable + 1 + 1 + + + PGE2 + Pattern Generator 2 Output Enable + 2 + 1 + + + PGE3 + Pattern Generator 3 Output Enable + 3 + 1 + + + PGE4 + Pattern Generator 4 Output Enable + 4 + 1 + + + PGE5 + Pattern Generator 5 Output Enable + 5 + 1 + + + PGE6 + Pattern Generator 6 Output Enable + 6 + 1 + + + PGE7 + Pattern Generator 7 Output Enable + 7 + 1 + + + PGV0 + Pattern Generator 0 Output Value + 8 + 1 + + + PGV1 + Pattern Generator 1 Output Value + 9 + 1 + + + PGV2 + Pattern Generator 2 Output Value + 10 + 1 + + + PGV3 + Pattern Generator 3 Output Value + 11 + 1 + + + PGV4 + Pattern Generator 4 Output Value + 12 + 1 + + + PGV5 + Pattern Generator 5 Output Value + 13 + 1 + + + PGV6 + Pattern Generator 6 Output Value + 14 + 1 + + + PGV7 + Pattern Generator 7 Output Value + 15 + 1 + + + + + WAVE + Waveform Control + 0x3C + 32 + 0x00000000 + + + WAVEGEN + Waveform Generation + 0 + 3 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + DSCRITICAL + Dual-slope critical + 4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 7 + + + + + RAMP + Ramp Mode + 4 + 2 + + RAMPSelect + + RAMP1 + RAMP1 operation + 0 + + + RAMP2A + Alternative RAMP2 operation + 1 + + + RAMP2 + RAMP2 operation + 2 + + + RAMP2C + Critical RAMP2 operation + 3 + + + + + CIPEREN + Circular period Enable + 7 + 1 + + + CICCEN0 + Circular Channel 0 Enable + 8 + 1 + + + CICCEN1 + Circular Channel 1 Enable + 9 + 1 + + + CICCEN2 + Circular Channel 2 Enable + 10 + 1 + + + CICCEN3 + Circular Channel 3 Enable + 11 + 1 + + + POL0 + Channel 0 Polarity + 16 + 1 + + + POL1 + Channel 1 Polarity + 17 + 1 + + + POL2 + Channel 2 Polarity + 18 + 1 + + + POL3 + Channel 3 Polarity + 19 + 1 + + + POL4 + Channel 4 Polarity + 20 + 1 + + + POL5 + Channel 5 Polarity + 21 + 1 + + + SWAP0 + Swap DTI Output Pair 0 + 24 + 1 + + + SWAP1 + Swap DTI Output Pair 1 + 25 + 1 + + + SWAP2 + Swap DTI Output Pair 2 + 26 + 1 + + + SWAP3 + Swap DTI Output Pair 3 + 27 + 1 + + + + + PER + Period + 0x40 + 32 + 0xFFFFFFFF + + + PER + Period Value + 0 + 24 + + + + + PER_DITH4_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 4 + + + PER + Period Value + 4 + 20 + + + + + PER_DITH5_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 5 + + + PER + Period Value + 5 + 19 + + + + + PER_DITH6_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 6 + + + PER + Period Value + 6 + 18 + + + + + 6 + 4 + CC[%s] + Compare and Capture + 0x44 + 32 + 0x00000000 + + + CC + Channel Compare/Capture Value + 0 + 24 + + + + + 6 + 4 + CC_DITH4_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 4 + + + CC + Channel Compare/Capture Value + 4 + 20 + + + + + 6 + 4 + CC_DITH5_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 5 + + + CC + Channel Compare/Capture Value + 5 + 19 + + + + + 6 + 4 + CC_DITH6_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 6 + + + CC + Channel Compare/Capture Value + 6 + 18 + + + + + PATTBUF + Pattern Buffer + 0x64 + 16 + 0x0000 + + + PGEB0 + Pattern Generator 0 Output Enable Buffer + 0 + 1 + + + PGEB1 + Pattern Generator 1 Output Enable Buffer + 1 + 1 + + + PGEB2 + Pattern Generator 2 Output Enable Buffer + 2 + 1 + + + PGEB3 + Pattern Generator 3 Output Enable Buffer + 3 + 1 + + + PGEB4 + Pattern Generator 4 Output Enable Buffer + 4 + 1 + + + PGEB5 + Pattern Generator 5 Output Enable Buffer + 5 + 1 + + + PGEB6 + Pattern Generator 6 Output Enable Buffer + 6 + 1 + + + PGEB7 + Pattern Generator 7 Output Enable Buffer + 7 + 1 + + + PGVB0 + Pattern Generator 0 Output Enable + 8 + 1 + + + PGVB1 + Pattern Generator 1 Output Enable + 9 + 1 + + + PGVB2 + Pattern Generator 2 Output Enable + 10 + 1 + + + PGVB3 + Pattern Generator 3 Output Enable + 11 + 1 + + + PGVB4 + Pattern Generator 4 Output Enable + 12 + 1 + + + PGVB5 + Pattern Generator 5 Output Enable + 13 + 1 + + + PGVB6 + Pattern Generator 6 Output Enable + 14 + 1 + + + PGVB7 + Pattern Generator 7 Output Enable + 15 + 1 + + + + + PERBUF + Period Buffer + 0x6C + 32 + 0xFFFFFFFF + + + PERBUF + Period Buffer Value + 0 + 24 + + + + + PERBUF_DITH4_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 4 + + + PERBUF + Period Buffer Value + 4 + 20 + + + + + PERBUF_DITH5_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 5 + + + PERBUF + Period Buffer Value + 5 + 19 + + + + + PERBUF_DITH6_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 6 + + + PERBUF + Period Buffer Value + 6 + 18 + + + + + 6 + 4 + CCBUF[%s] + Compare and Capture Buffer + 0x70 + 32 + 0x00000000 + + + CCBUF + Channel Compare/Capture Buffer Value + 0 + 24 + + + + + 6 + 4 + CCBUF_DITH4_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + CCBUF + Channel Compare/Capture Buffer Value + 0 + 4 + + + DITHERBUF + Dithering Buffer Cycle Number + 4 + 20 + + + + + 6 + 4 + CCBUF_DITH5_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 5 + + + CCBUF + Channel Compare/Capture Buffer Value + 5 + 19 + + + + + 6 + 4 + CCBUF_DITH6_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 6 + + + CCBUF + Channel Compare/Capture Buffer Value + 6 + 18 + + + + + + + TCC1 + 0x41018000 + + TCC1_OTHER + 92 + + + TCC1_MC0 + 93 + + + TCC1_MC1 + 94 + + + TCC1_MC2 + 95 + + + TCC1_MC3 + 96 + + + + TCC2 + 0x42000C00 + + TCC2_OTHER + 97 + + + TCC2_MC0 + 98 + + + TCC2_MC1 + 99 + + + TCC2_MC2 + 100 + + + + TCC3 + 0x42001000 + + TCC3_OTHER + 101 + + + TCC3_MC0 + 102 + + + TCC3_MC1 + 103 + + + + TCC4 + 0x43001000 + + TCC4_OTHER + 104 + + + TCC4_MC0 + 105 + + + TCC4_MC1 + 106 + + + + TRNG + U22421.1.0 + True Random Generator + TRNG + TRNG_ + 0x42002800 + + 0 + 0x24 + registers + + + TRNG + 131 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + + + EVCTRL + Event Control + 0x4 + 8 + 0x00 + + + DATARDYEO + Data Ready Event Output + 0 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + DATARDY + Data Ready Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + DATARDY + Data Ready Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + DATARDY + Data Ready Interrupt Flag + 0 + 1 + + + + + DATA + Output Data + 0x20 + 32 + read-only + 0x00000000 + + + DATA + Output Data + 0 + 32 + + + + + + + USB + U22221.2.0 + Universal Serial Bus + USB + USB_ + 0x41000000 + + 0 + 0x200 + registers + + + USB_OTHER + 80 + + + USB_SOF_HSOF + 81 + + + USB_TRCPT0 + 82 + + + USB_TRCPT1 + 83 + + + + DEVICE + USB is Device + UsbDevice + 0x0 + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby Mode + 2 + 1 + + + MODE + Operating Mode + 7 + 1 + + MODESelect + + DEVICE + Device Mode + 0 + + + HOST + Host Mode + 1 + + + + + + + SYNCBUSY + Synchronization Busy + 0x2 + 8 + read-only + 0x00 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + + + QOSCTRL + USB Quality Of Service + 0x3 + 8 + 0x0F + + + CQOS + Configuration Quality of Service + 0 + 2 + + + DQOS + Data Quality of Service + 2 + 2 + + + + + CTRLB + DEVICE Control B + 0x8 + 16 + 0x0001 + + + DETACH + Detach + 0 + 1 + + + UPRSM + Upstream Resume + 1 + 1 + + + SPDCONF + Speed Configuration + 2 + 2 + + SPDCONFSelect + + FS + FS : Full Speed + 0x0 + + + LS + LS : Low Speed + 0x1 + + + HS + HS : High Speed capable + 0x2 + + + HSTM + HSTM: High Speed Test Mode (force high-speed mode for test mode) + 0x3 + + + + + NREPLY + No Reply + 4 + 1 + + + TSTJ + Test mode J + 5 + 1 + + + TSTK + Test mode K + 6 + 1 + + + TSTPCKT + Test packet mode + 7 + 1 + + + OPMODE2 + Specific Operational Mode + 8 + 1 + + + GNAK + Global NAK + 9 + 1 + + + LPMHDSK + Link Power Management Handshake + 10 + 2 + + LPMHDSKSelect + + NO + No handshake. LPM is not supported + 0 + + + ACK + ACK + 1 + + + NYET + NYET + 2 + + + STALL + STALL + 3 + + + + + + + DADD + DEVICE Device Address + 0xA + 8 + 0x00 + + + DADD + Device Address + 0 + 7 + + + ADDEN + Device Address Enable + 7 + 1 + + + + + STATUS + DEVICE Status + 0xC + 8 + read-only + 0x40 + + + SPEED + Speed Status + 2 + 2 + + SPEEDSelect + + FS + Full-speed mode + 0x0 + + + LS + Low-speed mode + 0x1 + + + HS + High-speed mode + 0x2 + + + + + LINESTATE + USB Line State Status + 6 + 2 + + LINESTATESelect + + 0 + SE0/RESET + 0x0 + + + 1 + FS-J or LS-K State + 0x1 + + + 2 + FS-K or LS-J State + 0x2 + + + + + + + FSMSTATUS + Finite State Machine Status + 0xD + 8 + read-only + 0x01 + + + FSMSTATE + Fine State Machine Status + 0 + 7 + + FSMSTATESelect + + OFF + OFF (L3). It corresponds to the powered-off, disconnected, and disabled state + 0x1 + + + ON + ON (L0). It corresponds to the Idle and Active states + 0x2 + + + SUSPEND + SUSPEND (L2) + 0x4 + + + SLEEP + SLEEP (L1) + 0x8 + + + DNRESUME + DNRESUME. Down Stream Resume. + 0x10 + + + UPRESUME + UPRESUME. Up Stream Resume. + 0x20 + + + RESET + RESET. USB lines Reset. + 0x40 + + + + + + + FNUM + DEVICE Device Frame Number + 0x10 + 16 + read-only + 0x0000 + + + MFNUM + Micro Frame Number + 0 + 3 + + + FNUM + Frame Number + 3 + 11 + + + FNCERR + Frame Number CRC Error + 15 + 1 + + + + + INTENCLR + DEVICE Device Interrupt Enable Clear + 0x14 + 16 + 0x0000 + + + SUSPEND + Suspend Interrupt Enable + 0 + 1 + + + MSOF + Micro Start of Frame Interrupt Enable in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame Interrupt Enable + 2 + 1 + + + EORST + End of Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + EORSM + End Of Resume Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + LPMNYET + Link Power Management Not Yet Interrupt Enable + 8 + 1 + + + LPMSUSP + Link Power Management Suspend Interrupt Enable + 9 + 1 + + + + + INTENSET + DEVICE Device Interrupt Enable Set + 0x18 + 16 + 0x0000 + + + SUSPEND + Suspend Interrupt Enable + 0 + 1 + + + MSOF + Micro Start of Frame Interrupt Enable in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame Interrupt Enable + 2 + 1 + + + EORST + End of Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + EORSM + End Of Resume Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + LPMNYET + Link Power Management Not Yet Interrupt Enable + 8 + 1 + + + LPMSUSP + Link Power Management Suspend Interrupt Enable + 9 + 1 + + + + + INTFLAG + DEVICE Device Interrupt Flag + 0x1C + 16 + 0x0000 + + + SUSPEND + Suspend + 0 + 1 + + + MSOF + Micro Start of Frame in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame + 2 + 1 + + + EORST + End of Reset + 3 + 1 + + + WAKEUP + Wake Up + 4 + 1 + + + EORSM + End Of Resume + 5 + 1 + + + UPRSM + Upstream Resume + 6 + 1 + + + RAMACER + Ram Access + 7 + 1 + + + LPMNYET + Link Power Management Not Yet + 8 + 1 + + + LPMSUSP + Link Power Management Suspend + 9 + 1 + + + + + EPINTSMRY + DEVICE End Point Interrupt Summary + 0x20 + 16 + read-only + 0x0000 + + + EPINT0 + End Point 0 Interrupt + 0 + 1 + + + EPINT1 + End Point 1 Interrupt + 1 + 1 + + + EPINT2 + End Point 2 Interrupt + 2 + 1 + + + EPINT3 + End Point 3 Interrupt + 3 + 1 + + + EPINT4 + End Point 4 Interrupt + 4 + 1 + + + EPINT5 + End Point 5 Interrupt + 5 + 1 + + + EPINT6 + End Point 6 Interrupt + 6 + 1 + + + EPINT7 + End Point 7 Interrupt + 7 + 1 + + + + + DESCADD + Descriptor Address + 0x24 + 32 + 0x00000000 + + + DESCADD + Descriptor Address Value + 0 + 32 + + + + + PADCAL + USB PAD Calibration + 0x28 + 16 + 0x0000 + + + TRANSP + USB Pad Transp calibration + 0 + 5 + + + TRANSN + USB Pad Transn calibration + 6 + 5 + + + TRIM + USB Pad Trim calibration + 12 + 3 + + + + + 8 + 0x20 + DEVICE_ENDPOINT[%s] + + 0x100 + + EPCFG + DEVICE_ENDPOINT End Point Configuration + 0x0 + 8 + 0x00 + + + EPTYPE0 + End Point Type0 + 0 + 3 + + + EPTYPE1 + End Point Type1 + 4 + 3 + + + NYETDIS + NYET Token Disable + 7 + 1 + + + + + EPSTATUSCLR + DEVICE_ENDPOINT End Point Pipe Status Clear + 0x4 + 8 + write-only + 0x00 + + + DTGLOUT + Data Toggle OUT Clear + 0 + 1 + + + DTGLIN + Data Toggle IN Clear + 1 + 1 + + + CURBK + Current Bank Clear + 2 + 1 + + + STALLRQ0 + Stall 0 Request Clear + 4 + 1 + + + STALLRQ1 + Stall 1 Request Clear + 5 + 1 + + + BK0RDY + Bank 0 Ready Clear + 6 + 1 + + + BK1RDY + Bank 1 Ready Clear + 7 + 1 + + + + + EPSTATUSSET + DEVICE_ENDPOINT End Point Pipe Status Set + 0x5 + 8 + write-only + 0x00 + + + DTGLOUT + Data Toggle OUT Set + 0 + 1 + + + DTGLIN + Data Toggle IN Set + 1 + 1 + + + CURBK + Current Bank Set + 2 + 1 + + + STALLRQ0 + Stall 0 Request Set + 4 + 1 + + + STALLRQ1 + Stall 1 Request Set + 5 + 1 + + + BK0RDY + Bank 0 Ready Set + 6 + 1 + + + BK1RDY + Bank 1 Ready Set + 7 + 1 + + + + + EPSTATUS + DEVICE_ENDPOINT End Point Pipe Status + 0x6 + 8 + read-only + 0x00 + + + DTGLOUT + Data Toggle Out + 0 + 1 + + + DTGLIN + Data Toggle In + 1 + 1 + + + CURBK + Current Bank + 2 + 1 + + + STALLRQ0 + Stall 0 Request + 4 + 1 + + + STALLRQ1 + Stall 1 Request + 5 + 1 + + + BK0RDY + Bank 0 ready + 6 + 1 + + + BK1RDY + Bank 1 ready + 7 + 1 + + + + + EPINTFLAG + DEVICE_ENDPOINT End Point Interrupt Flag + 0x7 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 + 0 + 1 + + + TRCPT1 + Transfer Complete 1 + 1 + 1 + + + TRFAIL0 + Error Flow 0 + 2 + 1 + + + TRFAIL1 + Error Flow 1 + 3 + 1 + + + RXSTP + Received Setup + 4 + 1 + + + STALL0 + Stall 0 In/out + 5 + 1 + + + STALL1 + Stall 1 In/out + 6 + 1 + + + + + EPINTENCLR + DEVICE_ENDPOINT End Point Interrupt Clear Flag + 0x8 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Disable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Disable + 1 + 1 + + + TRFAIL0 + Error Flow 0 Interrupt Disable + 2 + 1 + + + TRFAIL1 + Error Flow 1 Interrupt Disable + 3 + 1 + + + RXSTP + Received Setup Interrupt Disable + 4 + 1 + + + STALL0 + Stall 0 In/Out Interrupt Disable + 5 + 1 + + + STALL1 + Stall 1 In/Out Interrupt Disable + 6 + 1 + + + + + EPINTENSET + DEVICE_ENDPOINT End Point Interrupt Set Flag + 0x9 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Enable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Enable + 1 + 1 + + + TRFAIL0 + Error Flow 0 Interrupt Enable + 2 + 1 + + + TRFAIL1 + Error Flow 1 Interrupt Enable + 3 + 1 + + + RXSTP + Received Setup Interrupt Enable + 4 + 1 + + + STALL0 + Stall 0 In/out Interrupt enable + 5 + 1 + + + STALL1 + Stall 1 In/out Interrupt enable + 6 + 1 + + + + + + + HOST + USB is Host + DEVICE + UsbHost + 0x0 + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby Mode + 2 + 1 + + + MODE + Operating Mode + 7 + 1 + + MODESelect + + DEVICE + Device Mode + 0 + + + HOST + Host Mode + 1 + + + + + + + SYNCBUSY + Synchronization Busy + 0x2 + 8 + read-only + 0x00 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + + + QOSCTRL + USB Quality Of Service + 0x3 + 8 + 0x0F + + + CQOS + Configuration Quality of Service + 0 + 2 + + + DQOS + Data Quality of Service + 2 + 2 + + + + + CTRLB + HOST Control B + 0x8 + 16 + 0x0000 + + + RESUME + Send USB Resume + 1 + 1 + + + SPDCONF + Speed Configuration for Host + 2 + 2 + + SPDCONFSelect + + NORMAL + Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. + 0x0 + + + FS + Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. + 0x3 + + + + + AUTORESUME + Auto Resume Enable + 4 + 1 + + + TSTJ + Test mode J + 5 + 1 + + + TSTK + Test mode K + 6 + 1 + + + SOFE + Start of Frame Generation Enable + 8 + 1 + + + BUSRESET + Send USB Reset + 9 + 1 + + + VBUSOK + VBUS is OK + 10 + 1 + + + L1RESUME + Send L1 Resume + 11 + 1 + + + + + HSOFC + HOST Host Start Of Frame Control + 0xA + 8 + 0x00 + + + FLENC + Frame Length Control + 0 + 4 + + + FLENCE + Frame Length Control Enable + 7 + 1 + + + + + STATUS + HOST Status + 0xC + 8 + 0x00 + + + SPEED + Speed Status + 2 + 2 + + + LINESTATE + USB Line State Status + 6 + 2 + + + + + FSMSTATUS + Finite State Machine Status + 0xD + 8 + read-only + 0x01 + + + FSMSTATE + Fine State Machine Status + 0 + 7 + + FSMSTATESelect + + OFF + OFF (L3). It corresponds to the powered-off, disconnected, and disabled state + 0x1 + + + ON + ON (L0). It corresponds to the Idle and Active states + 0x2 + + + SUSPEND + SUSPEND (L2) + 0x4 + + + SLEEP + SLEEP (L1) + 0x8 + + + DNRESUME + DNRESUME. Down Stream Resume. + 0x10 + + + UPRESUME + UPRESUME. Up Stream Resume. + 0x20 + + + RESET + RESET. USB lines Reset. + 0x40 + + + + + + + FNUM + HOST Host Frame Number + 0x10 + 16 + 0x0000 + + + MFNUM + Micro Frame Number + 0 + 3 + + + FNUM + Frame Number + 3 + 11 + + + + + FLENHIGH + HOST Host Frame Length + 0x12 + 8 + read-only + 0x00 + + + FLENHIGH + Frame Length + 0 + 8 + + + + + INTENCLR + HOST Host Interrupt Enable Clear + 0x14 + 16 + 0x0000 + + + HSOF + Host Start Of Frame Interrupt Disable + 2 + 1 + + + RST + BUS Reset Interrupt Disable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Disable + 4 + 1 + + + DNRSM + DownStream to Device Interrupt Disable + 5 + 1 + + + UPRSM + Upstream Resume from Device Interrupt Disable + 6 + 1 + + + RAMACER + Ram Access Interrupt Disable + 7 + 1 + + + DCONN + Device Connection Interrupt Disable + 8 + 1 + + + DDISC + Device Disconnection Interrupt Disable + 9 + 1 + + + + + INTENSET + HOST Host Interrupt Enable Set + 0x18 + 16 + 0x0000 + + + HSOF + Host Start Of Frame Interrupt Enable + 2 + 1 + + + RST + Bus Reset Interrupt Enable + 3 + 1 + + + WAKEUP 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0x10 + 32 + + + SCR + ETM System Configuration Register + 0x14 + 32 + read-only + 0x00020D09 + + + TEEVR + ETM TraceEnable Event Register + 0x20 + 32 + + + TECR1 + ETM TraceEnable Control 1 Register + 0x24 + 32 + + + FFLR + ETM FIFO Full Level Register + 0x28 + 32 + + + CNTRLDVR1 + ETM Free-running Counter Reload Value + 0x140 + 32 + + + SYNCFR + ETM Synchronization Frequency Register + 0x1E0 + 32 + read-only + 0x00000400 + + + IDR + ETM ID Register + 0x1E4 + 32 + read-only + 0x4114F250 + + + CCER + ETM Configuration Code Extension Register + 0x1E8 + 32 + read-only + 0x18541800 + + + TESSEICR + ETM TraceEnable Start/Stop EmbeddedICE Control Register + 0x1F0 + 32 + + + TSEVT + ETM TimeStamp Event Register + 0x1F8 + 32 + + + TRACEIDR + ETM CoreSight Trace ID Register + 0x200 + 32 + 0x00000000 + + + IDR2 + ETM ID Register 2 + 0x208 + 32 + read-only + 0x00000000 + + + PDSR + ETM Device Power-Down Status Register + 0x314 + 32 + read-only + 0x00000001 + + + ITMISCIN + ETM Integration Test Miscellaneous Inputs + 0xEE0 + 32 + read-only + + + ITTRIGOUT + ETM Integration Test Trigger Out + 0xEE8 + 32 + write-only + + + ITATBCTR2 + ETM Integration Test ATB Control 2 + 0xEF0 + 32 + read-only + + + ITATBCTR0 + ETM Integration Test ATB Control 0 + 0xEF8 + 32 + write-only + + + ITCTRL + ETM Integration Mode Control Register + 0xF00 + 32 + 0x00000000 + + + INTEGRATION + 0 + 1 + + + + + CLAIMSET + ETM Claim Tag Set Register + 0xFA0 + 32 + + + CLAIMCLR + ETM Claim Tag Clear Register + 0xFA4 + 32 + + + LAR + ETM Lock Access Register + 0xFB0 + 32 + write-only + + + LSR + ETM Lock Status Register + 0xFB4 + 32 + read-only + + + Present + 0 + 1 + + + Access + 1 + 1 + + + ByteAcc + 2 + 1 + + + + + AUTHSTATUS + ETM Authentication Status Register + 0xFB8 + 32 + read-only + + + DEVTYPE + ETM CoreSight Device Type Register + 0xFCC + 32 + read-only + 0x00000013 + + + PIDR4 + ETM Peripheral Identification Register #4 + 0xFD0 + 32 + read-only + 0x00000004 + + + PIDR5 + ETM Peripheral Identification Register #5 + 0xFD4 + 32 + read-only + 0x00000000 + + + PIDR6 + ETM Peripheral Identification Register #6 + 0xFD8 + 32 + read-only + 0x00000000 + + + PIDR7 + ETM Peripheral Identification Register #7 + 0xFDC + 32 + read-only + 0x00000000 + + + PIDR0 + ETM Peripheral Identification Register #0 + 0xFE0 + 32 + read-only + 0x00000025 + + + PIDR1 + ETM Peripheral Identification Register #1 + 0xFE4 + 32 + read-only + 0x000000B9 + + + PIDR2 + ETM Peripheral Identification Register #2 + 0xFE8 + 32 + read-only + 0x0000000B + + + PIDR3 + ETM Peripheral Identification Register #3 + 0xFEC + 32 + read-only + 0x00000000 + + + CIDR0 + ETM Component Identification Register #0 + 0xFF0 + 32 + read-only + 0x0000000D + + + CIDR1 + ETM Component Identification Register #1 + 0xFF4 + 32 + read-only + 0x00000090 + + + CIDR2 + ETM Component Identification Register #2 + 0xFF8 + 32 + read-only + 0x00000005 + + + CIDR3 + ETM Component Identification Register #3 + 0xFFC + 32 + read-only + 0x000000B1 + + + + + FPU + Floating Point Unit + FPU + FPU_ + 0xE000EF30 + + 0 + 0x18 + registers + + + + FPCCR + Floating-Point Context Control Register + 0x4 + 32 + 0xC0000000 + + + LSPACT + 0 + 1 + + + USER + 1 + 1 + + + THREAD + 3 + 1 + + + HFRDY + 4 + 1 + + + MMRDY + 5 + 1 + + + BFRDY + 6 + 1 + + + MONRDY + 8 + 1 + + + LSPEN + 30 + 1 + + + ASPEN + 31 + 1 + + + + + FPCAR + Floating-Point Context Address Register + 0x8 + 32 + + + ADDRESS + Address for FP registers in exception stack frame + 3 + 29 + + + + + FPDSCR + Floating-Point Default Status Control Register + 0xC + 32 + 0x00000000 + + + RMODE + Default value for FPSCR.RMODE + 22 + 2 + + RMODESelect + + RN + Round to Nearest + 0x0 + + + RP + Round towards Positive Infinity + 0x1 + + + RM + Round towards Negative Infinity + 0x2 + + + RZ + Round towards Zero + 0x3 + + + + + FZ + Default value for FPSCR.FZ + 24 + 1 + + + DN + Default value for FPSCR.DN + 25 + 1 + + + AHP + Default value for FPSCR.AHP + 26 + 1 + + + + + MVFR0 + Media and FP Feature Register 0 + 0x10 + 32 + read-only + + + A_SIMD_registers + 0 + 4 + + + Single_precision + 4 + 4 + + + Double_precision + 8 + 4 + + + FP_excep_trapping + 12 + 4 + + + Divide + 16 + 4 + + + Square_root + 20 + 4 + + + Short_vectors + 24 + 4 + + + FP_rounding_modes + 28 + 4 + + + + + MVFR1 + Media and FP Feature Register 1 + 0x14 + 32 + read-only + + + FtZ_mode + 0 + 4 + + + D_NaN_mode + 4 + 4 + + + FP_HPFP + 24 + 4 + + + FP_fused_MAC + 28 + 4 + + + + + + + ITM + Instrumentation Trace Macrocell + ITM + ITM_ + 0xE0000000 + + 0 + 0xF00 + registers + + + + 32 + 4 + PORT_WORD_MODE[%s] + ITM Stimulus Port Registers + 0x0 + 32 + write-only + + + PORT + 0 + 32 + + + + + 32 + 4 + PORT_BYTE_MODE[%s] + ITM Stimulus Port Registers + PORT_WORD_MODE[%s] + 0x0 + 32 + write-only + + + PORT + 0 + 8 + + + + + 32 + 4 + PORT_HWORD_MODE[%s] + ITM Stimulus Port Registers + PORT_WORD_MODE[%s] + 0x0 + 32 + write-only + + + PORT + 0 + 16 + + + + + TER + ITM Trace Enable Register + 0xE00 + 32 + + + TPR + ITM Trace Privilege Register + 0xE40 + 32 + + + PRIVMASK + 0 + 4 + + + + + TCR + ITM Trace Control Register + 0xE80 + 32 + + + ITMENA + 0 + 1 + + + TSENA + 1 + 1 + + + SYNCENA + 2 + 1 + + + DWTENA + 3 + 1 + + + SWOENA + 4 + 1 + + + STALLENA + 5 + 1 + + + TSPrescale + 8 + 2 + + + GTSFREQ + 10 + 2 + + + TraceBusID + 16 + 7 + + + BUSY + 23 + 1 + + + + + IWR + ITM Integration Write Register + 0xEF8 + 32 + write-only + + + ATVALIDM + 0 + 1 + + + + + IRR + ITM Integration Read Register + 0xEFC + 32 + read-only + + + ATREADYM + 0 + 1 + + + + + + + MPU + Memory Protection Unit + MPU + MPU_ + 0xE000ED90 + + 0 + 0x2C + registers + + + + TYPE + MPU Type Register + 0x0 + 32 + read-only + + + SEPARATE + Separate instruction and Data Memory MapsRegions + 0 + 1 + + + DREGION + Number of Data Regions + 8 + 8 + + + IREGION + Number of Instruction Regions + 16 + 8 + + + + + CTRL + MPU Control Register + 0x4 + 32 + + + ENABLE + MPU Enable + 0 + 1 + + + HFNMIENA + Enable Hard Fault and NMI handlers + 1 + 1 + + + PRIVDEFENA + Enables privileged software access to default memory map + 2 + 1 + + + + + RNR + MPU Region Number Register + 0x8 + 32 + + + REGION + Region referenced by RBAR and RASR + 0 + 8 + + + + + RBAR + MPU Region Base Address Register + 0xC + 32 + + + REGION + Region number + 0 + 4 + + + VALID + Region number valid + 4 + 1 + + + ADDR + Region base address + 5 + 27 + + + + + RASR + MPU Region Attribute and Size Register + 0x10 + 32 + + + ENABLE + Region Enable + 0 + 1 + + + SIZE + Region Size + 1 + 1 + + + SRD + Sub-region disable + 8 + 8 + + + B + Bufferable bit + 16 + 1 + + + C + Cacheable bit + 17 + 1 + + + S + Shareable bit + 18 + 1 + + + TEX + TEX bit + 19 + 3 + + + AP + Access Permission + 24 + 3 + + + XN + Execute Never Attribute + 28 + 1 + + + + + RBAR_A1 + MPU Alias 1 Region Base Address Register + 0x14 + 32 + + + REGION + Region number + 0 + 4 + + + VALID + Region number valid + 4 + 1 + + + ADDR + Region base address + 5 + 27 + + + + + RASR_A1 + MPU Alias 1 Region Attribute and Size Register + 0x18 + 32 + + + ENABLE + Region Enable + 0 + 1 + + + SIZE + Region Size + 1 + 1 + + + SRD + Sub-region disable + 8 + 8 + + + B + Bufferable bit + 16 + 1 + + + C + Cacheable bit + 17 + 1 + + + S + Shareable bit + 18 + 1 + + + TEX + TEX bit + 19 + 3 + + + AP + Access Permission + 24 + 3 + + + XN + Execute Never Attribute + 28 + 1 + + + + + RBAR_A2 + MPU Alias 2 Region Base Address Register + 0x1C + 32 + + + REGION + Region number + 0 + 4 + + + VALID + Region number valid + 4 + 1 + + + ADDR + Region base address + 5 + 27 + + + + + RASR_A2 + MPU Alias 2 Region Attribute and Size Register + 0x20 + 32 + + + ENABLE + Region Enable + 0 + 1 + + + SIZE + Region Size + 1 + 1 + + + SRD + Sub-region disable + 8 + 8 + + + B + Bufferable bit + 16 + 1 + + + C + Cacheable bit + 17 + 1 + + + S + Shareable bit + 18 + 1 + + + TEX + TEX bit + 19 + 3 + + + AP + Access Permission + 24 + 3 + + + XN + Execute Never Attribute + 28 + 1 + + + + + RBAR_A3 + MPU Alias 3 Region Base Address Register + 0x24 + 32 + + + REGION + Region number + 0 + 4 + + + VALID + Region number valid + 4 + 1 + + + ADDR + Region base address + 5 + 27 + + + + + RASR_A3 + MPU Alias 3 Region Attribute and Size Register + 0x28 + 32 + + + ENABLE + Region Enable + 0 + 1 + + + SIZE + Region Size + 1 + 1 + + + SRD + Sub-region disable + 8 + 8 + + + B + Bufferable bit + 16 + 1 + + + C + Cacheable bit + 17 + 1 + + + S + Shareable bit + 18 + 1 + + + TEX + TEX bit + 19 + 3 + + + AP + Access Permission + 24 + 3 + + + XN + Execute Never Attribute + 28 + 1 + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + NVIC_ + 0xE000E100 + + 0 + 0xE04 + registers + + + + 5 + 4 + ISER[%s] + Interrupt Set Enable Register + 0x0 + 32 + 0 + + + SETENA + Interrupt set enable bits + 0 + 32 + + + + + 5 + 4 + ICER[%s] + Interrupt Clear Enable Register + 0x80 + 32 + 0 + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + + + + + 5 + 4 + ISPR[%s] + Interrupt Set Pending Register + 0x100 + 32 + 0 + + + SETPEND + Interrupt set-pending bits + 0 + 32 + + + + + 5 + 4 + ICPR[%s] + Interrupt Clear Pending Register + 0x180 + 32 + 0 + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + + + + + 5 + 4 + IABR[%s] + Interrupt Active Bit Register + 0x200 + 32 + 0 + + + ACTIVE + Interrupt active bits + 0 + 32 + + + + + 35 + 1 + IP[%s] + Interrupt Priority Register n + 0x300 + 8 + 0 + + + PRI0 + Priority of interrupt n + 0 + 3 + + + + + STIR + Software Trigger Interrupt Register + 0xE00 + 32 + write-only + + + INTID + Interrupt ID to trigger + 0 + 9 + + + + + + + SysTick + System timer + SysTick + SysTick_ + 0xE000E010 + + 0 + 0x10 + registers + + + + CSR + SysTick Control and Status Register + 0x0 + 32 + 0x4 + + + ENABLE + SysTick Counter Enable + 0 + 1 + + ENABLESelect + + VALUE_0 + Counter disabled + 0 + + + VALUE_1 + Counter enabled + 1 + + + + + TICKINT + SysTick Exception Request Enable + 1 + 1 + + TICKINTSelect + + VALUE_0 + Counting down to 0 does not assert the SysTick exception request + 0 + + + VALUE_1 + Counting down to 0 asserts the SysTick exception request + 1 + + + + + CLKSOURCE + Clock Source 0=external, 1=processor + 2 + 1 + + CLKSOURCESelect + + VALUE_0 + External clock + 0 + + + VALUE_1 + Processor clock + 1 + + + + + COUNTFLAG + Timer counted to 0 since last read of register + 16 + 1 + + + + + RVR + SysTick Reload Value Register + 0x4 + 32 + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0 + 0 + 24 + + + + + CVR + SysTick Current Value Register + 0x8 + 32 + + + CURRENT + Current value at the time the register is accessed + 0 + 24 + + + + + CALIB + SysTick Calibration Value Register + 0xC + 32 + read-only + 0 + + + TENMS + Reload value to use for 10ms timing + 0 + 24 + + + SKEW + TENMS is rounded from non-integer ratio + 30 + 1 + + SKEWSelect + + VALUE_0 + 10ms calibration value is exact + 0 + + + VALUE_1 + 10ms calibration value is inexact, because of the clock frequency + 1 + + + + + NOREF + No Separate Reference Clock + 31 + 1 + + NOREFSelect + + VALUE_0 + The reference clock is provided + 0 + + + VALUE_1 + The reference clock is not provided + 1 + + + + + + + + + SystemControl + System Control Registers + SystemControl + SystemControl_ + 0xE000E000 + + 0 + 0xD8C + registers + + + + ICTR + Interrupt Controller Type Register + 0x4 + 32 + read-only + + + INTLINESNUM + 0 + 4 + + + + + ACTLR + Auxiliary Control Register + 0x8 + 32 + + + DISMCYCINT + Disable interruption of LDM/STM instructions + 0 + 1 + + + DISDEFWBUF + Disable wruite buffer use during default memory map accesses + 1 + 1 + + + DISFOLD + Disable IT folding + 2 + 1 + + + DISFPCA + Disable automatic update of CONTROL.FPCA + 8 + 1 + + + DISOOFP + Disable out-of-order FP instructions + 9 + 1 + + + + + CPUID + CPUID Base Register + 0xD00 + 32 + read-only + 0x410FC240 + + + REVISION + Processor revision number + 0 + 4 + + + PARTNO + Process Part Number, 0xC24=Cortex-M4 + 4 + 12 + + + CONSTANT + Constant + 16 + 4 + + + VARIANT + Variant number + 20 + 4 + + + IMPLEMENTER + Implementer code, 0x41=ARM + 24 + 8 + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + 0 + + + VECTACTIVE + Active exception number + 0 + 9 + + + RETTOBASE + No preempted active exceptions to execute + 11 + 1 + + + VECTPENDING + Exception number of the highest priority pending enabled exception + 12 + 6 + + + ISRPENDING + Interrupt pending flag + 22 + 1 + + + ISRPREEMPT + Debug only + 23 + 1 + + + PENDSTCLR + SysTick clear-pending bit + 25 + 1 + + PENDSTCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the SysTick exception + 1 + + + + + PENDSTSET + SysTick set-pending bit + 26 + 1 + + PENDSTSETSelect + + VALUE_0 + Write: no effect; read: SysTick exception is not pending + 0 + + + VALUE_1 + Write: changes SysTick exception state to pending; read: SysTick exception is pending + 1 + + + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + PENDSVCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the PendSV exception + 1 + + + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + PENDSVSETSelect + + VALUE_0 + Write: no effect; read: PendSV exception is not pending + 0 + + + VALUE_1 + Write: changes PendSV exception state to pending; read: PendSV exception is pending + 1 + + + + + NMIPENDSET + NMI set-pending bit + 31 + 1 + + NMIPENDSETSelect + + VALUE_0 + Write: no effect; read: NMI exception is not pending + 0 + + + VALUE_1 + Write: changes NMI exception state to pending; read: NMI exception is pending + 1 + + + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + 0x00000000 + + + TBLOFF + Vector table base offset + 7 + 25 + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + 0xFA050000 + + + VECTRESET + Must write 0 + 0 + 1 + + + VECTCLRACTIVE + Must write 0 + 1 + 1 + + + SYSRESETREQ + System Reset Request + 2 + 1 + + SYSRESETREQSelect + + VALUE_0 + No system reset request + 0 + + + VALUE_1 + Asserts a signal to the outer system that requests a reset + 1 + + + + + PRIGROUP + Interrupt priority grouping + 8 + 3 + + + ENDIANNESS + Data endianness, 0=little, 1=big + 15 + 1 + + ENDIANNESSSelect + + VALUE_0 + Little-endian + 0 + + + VALUE_1 + Big-endian + 1 + + + + + VECTKEY + Register key + 16 + 16 + + + + + SCR + System Control Register + 0xD10 + 32 + 0 + + + SLEEPONEXIT + Sleep-on-exit on handler return + 1 + 1 + + SLEEPONEXITSelect + + VALUE_0 + Do not sleep when returning to Thread mode + 0 + + + VALUE_1 + Enter sleep, or deep sleep, on return from an ISR + 1 + + + + + SLEEPDEEP + Deep Sleep used as low power mode + 2 + 1 + + SLEEPDEEPSelect + + VALUE_0 + Sleep + 0 + + + VALUE_1 + Deep sleep + 1 + + + + + SEVONPEND + Send Event on Pending bit + 4 + 1 + + SEVONPENDSelect + + VALUE_0 + Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + 0 + + + VALUE_1 + Enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + 0x00000200 + + + NONBASETHRDENA + Indicates how processor enters Thread mode + 0 + 1 + + + USERSETMPEND + Enables unprivileged software access to STIR register + 1 + 1 + + + UNALIGN_TRP + Enables unaligned access traps + 3 + 1 + + UNALIGN_TRPSelect + + VALUE_0 + Do not trap unaligned halfword and word accesses + 0 + + + VALUE_1 + Trap unaligned halfword and word accesses + 1 + + + + + DIV_0_TRP + Enables divide by 0 trap + 4 + 1 + + + BFHFNMIGN + Ignore LDM/STM BusFault for -1/-2 priority handlers + 8 + 1 + + + STKALIGN + Indicates stack alignment on exception entry + 9 + 1 + + STKALIGNSelect + + VALUE_0 + 4-byte aligned + 0 + + + VALUE_1 + 8-byte aligned + 1 + + + + + + + SHPR1 + System Handler Priority Register 1 + 0xD18 + 32 + + + PRI_4 + Priority of system handler 4, MemManage + 0 + 8 + + + PRI_5 + Priority of system handler 5, BusFault + 8 + 8 + + + PRI_6 + Priority of system handler 6, UsageFault + 16 + 8 + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + 0 + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 8 + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + 0 + + + PRI_14 + Priority of system handler 14, PendSV + 16 + 8 + + + PRI_15 + Priority of system handler 15, SysTick exception + 24 + 8 + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + + + MEMFAULTACT + MemManage exception active bit + 0 + 1 + + + BUSFAULTACT + BusFault exception active bit + 1 + 1 + + + USGFAULTACT + UsageFault exception active bit + 3 + 1 + + + SVCALLACT + SVCall active bit + 7 + 1 + + + MONITORACT + DebugMonitor exception active bit + 8 + 1 + + + PENDSVACT + PendSV exception active bit + 10 + 1 + + + SYSTICKACT + SysTick exception active bit + 11 + 1 + + + USGFAULTPENDED + UsageFault exception pending bit + 12 + 1 + + + MEMFAULTPENDED + MemManage exception pending bit + 13 + 1 + + + BUSFAULTPENDED + BusFault exception pending bit + 14 + 1 + + + SVCALLPENDED + SVCall pending bit + 15 + 1 + + + MEMFAULTENA + MemManage enable bit + 16 + 1 + + + BUSFAULTENA + BusFault enable bit + 17 + 1 + + + USGFAULTENA + UsageFault enable bit + 18 + 1 + + + + + CFSR + Configurable Fault Status Register + 0xD28 + 32 + + + IACCVIOL + Instruction access violation + 0 + 1 + + + DACCVIOL + Data access violation + 1 + 1 + + + MUNSTKERR + MemManage Fault on unstacking for exception return + 3 + 1 + + + MSTKERR + MemManage Fault on stacking for exception entry + 4 + 1 + + + MLSPERR + MemManager Fault occured during FP lazy state preservation + 5 + 1 + + + MMARVALID + MemManage Fault Address Register valid + 7 + 1 + + + IBUSERR + Instruction bus error + 8 + 1 + + + PRECISERR + Precise data bus error + 9 + 1 + + + IMPRECISERR + Imprecise data bus error + 10 + 1 + + + UNSTKERR + BusFault on unstacking for exception return + 11 + 1 + + + STKERR + BusFault on stacking for exception entry + 12 + 1 + + + LSPERR + BusFault occured during FP lazy state preservation + 13 + 1 + + + BFARVALID + BusFault Address Register valid + 15 + 1 + + + UNDEFINSTR + Undefined instruction UsageFault + 16 + 1 + + + INVSTATE + Invalid state UsageFault + 17 + 1 + + + INVPC + Invalid PC load UsageFault + 18 + 1 + + + NOCP + No coprocessor UsageFault + 19 + 1 + + + UNALIGNED + Unaligned access UsageFault + 24 + 1 + + + DIVBYZERO + Divide by zero UsageFault + 25 + 1 + + + + + HFSR + HardFault Status Register + 0xD2C + 32 + + + VECTTBL + BusFault on a Vector Table read during exception processing + 1 + 1 + + + FORCED + Forced Hard Fault + 30 + 1 + + + DEBUGEVT + Debug: always write 0 + 31 + 1 + + + + + DFSR + Debug Fault Status Register + 0xD30 + 32 + + + HALTED + 0 + 1 + + + BKPT + 1 + 1 + + + DWTTRAP + 2 + 1 + + + VCATCH + 3 + 1 + + + EXTERNAL + 4 + 1 + + + + + MMFAR + MemManage Fault Address Register + 0xD34 + 32 + + + ADDRESS + Address that generated the MemManage fault + 0 + 32 + + + + + BFAR + BusFault Address Register + 0xD38 + 32 + + + ADDRESS + Address that generated the BusFault + 0 + 32 + + + + + AFSR + Auxiliary Fault Status Register + 0xD3C + 32 + + + IMPDEF + AUXFAULT input signals + 0 + 32 + + + + + 2 + 4 + PFR[%s] + Processor Feature Register + 0xD40 + 32 + + + DFR + Debug Feature Register + 0xD48 + 32 + read-only + + + ADR + Auxiliary Feature Register + 0xD4C + 32 + read-only + + + 4 + 4 + MMFR[%s] + Memory Model Feature Register + 0xD50 + 32 + read-only + + + 5 + 4 + ISAR[%s] + Instruction Set Attributes Register + 0xD60 + 32 + read-only + + + CPACR + Coprocessor Access Control Register + 0xD88 + 32 + + + CP10 + Access privileges for coprocessor 10 + 20 + 2 + + CP10Select + + DENIED + Access denied + 0x0 + + + PRIV + Privileged access only + 0x1 + + + FULL + Full access + 0x3 + + + + + CP11 + Access privileges for coprocessor 11 + 22 + 2 + + CP11Select + + DENIED + Access denied + 0x0 + + + PRIV + Privileged access only + 0x1 + + + FULL + Full access + 0x3 + + + + + + + + + TPI + Trace Port Interface Register + TPI + TPI_ + 0xE0040000 + + 0 + 0xFD0 + registers + + + + SSPSR + Supported Parallel Port Size Register + 0x0 + 32 + read-only + + + CSPSR + Current Parallel Port Size Register + 0x4 + 32 + + + ACPR + Asynchronous Clock Prescaler Register + 0x10 + 32 + + + PRESCALER + 0 + 13 + + + + + SPPR + Selected Pin Protocol Register + 0xF0 + 32 + + + TXMODE + 0 + 2 + + + + + FFSR + Formatter and Flush Status Register + 0x300 + 32 + read-only + + + FlInProg + 0 + 1 + + + FtStopped + 1 + 1 + + + TCPresent + 2 + 1 + + + FtNonStop + 3 + 1 + + + + + FFCR + Formatter and Flush Control Register + 0x304 + 32 + + + EnFCont + 1 + 1 + + + TrigIn + 8 + 1 + + + + + FSCR + Formatter Synchronization Counter Register + 0x308 + 32 + read-only + + + TRIGGER + TRIGGER + 0xEE8 + 32 + read-only + + + TRIGGER + 0 + 1 + + + + + FIFO0 + Integration ETM Data + 0xEEC + 32 + read-only + + + ETM0 + 0 + 8 + + + ETM1 + 8 + 8 + + + ETM2 + 16 + 8 + + + ETM_bytecount + 24 + 2 + + + ETM_ATVALID + 26 + 1 + + + ITM_bytecount + 27 + 2 + + + ITM_ATVALID + 29 + 1 + + + + + ITATBCTR2 + ITATBCTR2 + 0xEF0 + 32 + read-only + + + ATREADY + 0 + 1 + + + + + ITATBCTR0 + ITATBCTR0 + 0xEF8 + 32 + read-only + + + ATREADY + 0 + 1 + + + + + FIFO1 + Integration ITM Data + 0xEFC + 32 + read-only + + + ITM0 + 0 + 8 + + + ITM1 + 8 + 8 + + + ITM2 + 16 + 8 + + + ETM_bytecount + 24 + 2 + + + ETM_ATVALID + 26 + 1 + + + ITM_bytecount + 27 + 2 + + + ITM_ATVALID + 29 + 1 + + + + + ITCTRL + Integration Mode Control + 0xF00 + 32 + + + Mode + 0 + 1 + + + + + CLAIMSET + Claim tag set + 0xFA0 + 32 + + + CLAIMCLR + Claim tag clear + 0xFA4 + 32 + + + DEVID + TPIU_DEVID + 0xFC8 + 32 + read-only + + + NrTraceInput + 0 + 1 + + + AsynClkIn + 5 + 1 + + + MinBufSz + 6 + 3 + + + PTINVALID + 9 + 1 + + + MANCVALID + 10 + 1 + + + NRZVALID + 11 + 1 + + + + + DEVTYPE + TPIU_DEVTYPE + 0xFCC + 32 + read-only + + + SubType + 0 + 4 + + + MajorType + 4 + 4 + + + + + + + diff --git a/src/modules/chips/atsame51j20a/atsame51j20a.zig b/src/modules/chips/atsame51j20a/atsame51j20a.zig new file mode 100644 index 0000000..094644f --- /dev/null +++ b/src/modules/chips/atsame51j20a/atsame51j20a.zig @@ -0,0 +1,333 @@ +pub const std = @import("std"); +pub const cpu = @import("cpu"); +pub const micro = @import("microzig"); +pub const chip = @import("registers.zig"); + +const regs = chip.registers; +pub usingnamespace chip; + +pub const chip_name = "ATSAME51J20A"; + +pub const clock_frequencies = .{ + // On any reset the synchronous clocks start to their initial state: + // * DFLL48M is enabled and configured to run at 48 MHz + // * Generic Generator 0 uses DFLL48M as source and generates GCLK_MAIN + // * CPU and BUS clocks are undivided + // i.e. GENCTRL0 = 0x00000106 + .cpu = 48_000_000, +}; + +/// Get access to the pin specified by `spec`. +/// +/// - `spec`: P{port}{pin} +/// - `port`: A, B +/// - `pin`: 0..31 +pub fn parsePin(comptime spec: []const u8) type { + const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme."; + + if (spec[0] != 'P') + @compileError(invalid_format_msg); + if (spec[1] < 'A' or spec[1] > 'B') // J = 64 Pins; 2 Ports + @compileError("Unknown port '" ++ spec[1..2] ++ "'. Supported ports: A, B."); + + return struct { + // Try to parse the given pin number as u5, i.e. a value in '0'..'31'. + const pin_number: u5 = @import("std").fmt.parseInt(u5, spec[2..], 10) catch @compileError(invalid_format_msg); + const pin_mask: u32 = (1 << pin_number); + // Port is either 'A' or 'B'. + const port_number: usize = if (spec[1] == 'A') 0 else 1; + const gpio_port = @field(regs.PORT, "GROUP"); + }; +} + +pub const gpio = struct { + // See SAM D5x/E5x Family Data Sheet page 807. + + /// Configure the given pin as output with input disabled. + pub fn setOutput(comptime pin: type) void { + // To use pin Pxy as an output, write bit y of the DIR register to '1'. This + // can also be done by writing bit y int the DIRSET register to '1' - this + // will avoid disturbing the configuration of other pins (datasheet p. 803). + pin.gpio_port[pin.port_number].DIRSET = pin.pin_mask; + // Disable input for the given pin. + pin.gpio_port[pin.port_number].PINCFG[pin.pin_number].modify(.{ .INEN = 0 }); + } + + /// Configure the given pin as input. + pub fn setInput(comptime pin: type) void { + // To use pin Pxy as an input, bit y in the DIR register must be written to '0'. + // This can also be done by writing bit y in the DIRCLR register to '1'. + pin.gpio_port[pin.port_number].DIRCLR = pin.pin_mask; + // The input value can be read from bit y in register IN as soon as the INEN bit in the pin + // configuratation register is written to '1' to enable the pins input buffer. + pin.gpio_port[pin.port_number].PINCFG[pin.pin_number].modify(.{ .INEN = 1 }); + } + + /// Configure the given pin as input with pull-up. + pub fn setInputPullUp(comptime pin: type) void { + setInput(pin); + pin.gpio_port[pin.port_number].PINCFG[pin.pin_number].modify(.{ .PULLEN = 1 }); + // When enabling input with pull-up, bit y must be set to '1'. + write(pin, .high); + } + + /// Configure the given pin as input with pull-down. + pub fn setInputPullDown(comptime pin: type) void { + setInput(pin); + pin.gpio_port[pin.port_number].PINCFG[pin.pin_number].modify(.{ .PULLEN = 1 }); + // When enabling input with pull-down, bit y must be set to '0'. + write(pin, .low); + } + + /// Check if the given pin is configured as output. + /// Returns true on success, false otherwise. + pub fn isOutput(comptime pin: type) bool { + return (pin.gpio_port[pin.port_number].DIR & pin.pin_mask) != 0; + } + + pub fn read(comptime pin: type) micro.gpio.State { + return if ((pin.gpio_port[pin.port_number].IN & pin.pin_mask) != 0) + micro.gpio.State.high + else + micro.gpio.State.low; + } + + pub fn write(comptime pin: type, state: micro.gpio.State) void { + switch (state) { + .high => pin.gpio_port[pin.port_number].OUTSET = pin.pin_mask, + .low => pin.gpio_port[pin.port_number].OUTCLR = pin.pin_mask, + } + } + + pub fn toggle(comptime pin: type) void { + pin.gpio_port[pin.port_number].OUTTGL = pin.pin_mask; + } +}; + +// ############################################################################# +// Nonvolotile Memory Controller - NVMCTRL +// ############################################################################# + +pub fn nvmctrlInit() void { + regs.NVMCTRL.CTRLA.modify(.{ + .RWS = 5, // Number of wait states for a read operation + .AUTOWS = 1, // Enable wait states + }); +} + +// ############################################################################# +// Generic Clock Controller - GCLK +// ############################################################################# + +pub fn gclk2Init() void { + regs.GCLK.GENCTRL[2].modify(.{ + .DIV = 1, + .SRC = 6, // DFLL48M generator clock source + .GENEN = 1, // Enable generator + }); + + while (regs.GCLK.SYNCBUSY.read().GENCTRL & 2 != 0) { + // wait for sync + } +} + +// ############################################################################# +// UART +// ############################################################################# + +/// Calculate the BAUD register value based on the the expected output frequency +/// `fbaud` and the baud reference frequency `fref` (see data sheet p. 830). +pub fn asyncArithmeticBaudToRegister(fbaud: u32, fref: u32) u16 { + const fb = @intToFloat(f64, fbaud); + const fr = @intToFloat(f64, fref); + const res = 65536.0 * (1.0 - 16.0 * (fb / fr)); + + return @floatToInt(u16, res); +} + +/// Unique definitions for the chip, used by the microzig.uart.Config struct. +pub const uart = struct { + /// USART character size (p. 859). + pub const DataBits = enum(u3) { + eight = 0, + nine = 1, + five = 5, + six = 6, + seven = 7, + }; + + /// USART stop bits (p. 859). + pub const StopBits = enum(u1) { + one = 0, + tow = 1, + }; + + /// USART parity mode (p. 858). + pub const Parity = enum(u1) { + even = 0, + odd = 1, + }; +}; + +/// Instantiate a new USART interface. +/// +/// * `index` - SERCOM{index} should be used for UART +/// * `pins` - Not supported. Please use `.{ .tx = null, .rx = null }` +pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type { + if (pins.tx != null or pins.rx != null) + @compileError("SAMD/E5x doesn't support custom pins"); + + return struct { + const UARTn = switch (index) { + 5 => regs.SERCOM5.USART_INT, + else => @compileError("Currently only SERCOM5:USART_INT supported."), + }; + const Self = @This(); + + pub fn init(config: micro.uart.Config) !Self { + switch (index) { + 5 => { + gclk2Init(); + + regs.GCLK.PCHCTRL[35].modify(.{ + .GEN = 2, // Generic clock generator 2 (see p. 156) + .CHEN = 1, // Enable peripheral channel + }); + + // When the APB clock is not provided to a module, its + // registers cannot be read or written. + regs.MCLK.APBDMASK.modify(.{ .SERCOM5_ = 1 }); + + // Enable the peripheral multiplexer selection. + regs.PORT.GROUP[1].PINCFG[16].modify(.{ .PMUXEN = 1 }); + regs.PORT.GROUP[1].PINCFG[17].modify(.{ .PMUXEN = 1 }); + + // Multiplex PB16 and PB17 to peripheral function C, i.e. + // SERCOM5 (see page 32 and 823). + regs.PORT.GROUP[1].PMUX[8].modify(.{ .PMUXE = 2, .PMUXO = 2 }); + }, + else => unreachable, + } + + // Some of the registers are enable-protected, meaning they can only + // be written when the USART is disabled. + UARTn.CTRLA.modify(.{ .ENABLE = 0 }); + + // Wait until synchronized. + while (UARTn.SYNCBUSY.read().ENABLE != 0) {} + + // Select USART with internal clock (0x1). + UARTn.CTRLA.modify(.{ + .MODE = 1, // Select USART with internal clock (0x01) + .CMODE = 0, // Select asynchronous communication mode (0x00) + // Pin selection (data sheet p. 854) + .RXPO = 1, // SERCOM PAD[1] is used for data reception + .TXPO = 0, // SERCOM PAD[0] is used for data transmition + .DORD = 1, // Configure data order (MSB = 0, LSB = 1) + .IBON = 1, // Immediate buffer overflow notification + .SAMPR = 0, // 16x over-sampling using arithmetic baud rate generation + }); + + // Configure parity mode. + if (config.parity != null) { + // Enable parity mode. + UARTn.CTRLA.modify(.{ .FORM = 1 }); // USART frame with parity + UARTn.CTRLB.modify(.{ .PMODE = @enumToInt(config.parity.?) }); + } else { + // Disable parity mode. + UARTn.CTRLA.modify(.{ .FORM = 0 }); // USART frame + } + + // Write the Baud register (internal clock mode) to generate the + // desired baud rate. + UARTn.BAUD.* = asyncArithmeticBaudToRegister(config.baud_rate, 48_000_000); //@intCast(u16, config.baud_rate); + + UARTn.CTRLB.modify(.{ + .CHSIZE = @enumToInt(config.data_bits), // Configure the character size filed. + .SBMODE = @enumToInt(config.stop_bits), // Configure the number of stop bits. + .RXEN = 1, // Enable the receiver + .TXEN = 1, // Enable the transmitter + }); + + //UARTn.INTENSET.modify(.{ .DRE = 1, .TXC = 1, .RXC = 1, .CTSIC = 1 }); + + while (UARTn.SYNCBUSY.raw != 0) {} + + // Enable the peripheral. + UARTn.CTRLA.modify(.{ .ENABLE = 1 }); + while (UARTn.SYNCBUSY.raw != 0) {} + + return Self{}; + } + + pub fn canWrite(self: Self) bool { + _ = self; + // The DRE flag ist set when DATA is empty and ready to be written. + // The DATA register should only be written to when INTFLAG.DRE is set. + return UARTn.INTFLAG.read().DRE == 1; + } + pub fn tx(self: Self, ch: u8) void { + while (!self.canWrite()) {} // Wait for Previous transmission + UARTn.DATA.* = ch; // Load the data to be transmitted + } + + pub fn canRead(self: Self) bool { + _ = self; + // The RXC flag ist set when there are unread data in DATA. + return UARTn.INTFLAG.read().RXC == 1; + } + pub fn rx(self: Self) u8 { + while (!self.canRead()) {} // Wait till the data is received + return @intCast(u8, UARTn.DATA.*); // Read received data + } + }; +} + +// ############################################################################# +// Crypto +// ############################################################################# + +pub fn enableTrng() void { + // Enable the TRNG bus clock. + regs.MCLK.APBCMASK.modify(.{ .TRNG_ = 1 }); +} + +pub const crypto = struct { + pub const random = struct { + /// Fill the given slice with random data. + pub fn getBlock(buffer: []u8) void { + var rand: u32 = undefined; + + var i: usize = 0; + while (i < buffer.len) : (i += 1) { + if (i % 4 == 0) { + // Get a fresh 32 bit integer every 4th iteration. + rand = getWord(); + } + + // The shift value is always between 0 and 24, i.e. int cast will always succeed. + buffer[i] = @intCast(u8, (rand >> @intCast(u5, (8 * (i % 4)))) & 0xff); + } + } + + /// Get a real 32 bit random integer. + /// + /// In most cases you'll want to use `getBlock` instead. + pub fn getWord() u32 { + regs.TRNG.CTRLA.modify(.{ .ENABLE = 1 }); + while (regs.TRNG.INTFLAG.read().DATARDY == 0) { + // a new random number is generated every + // 84 CLK_TRNG_APB clock cycles (p. 1421). + } + regs.TRNG.CTRLA.modify(.{ .ENABLE = 0 }); + return regs.TRNG.DATA.*; + } + + /// Get a real 8 bit random integer. + /// + /// In most cases you'll want to use `getBlock` instead. + pub fn getByte() u8 { + return @intCast(u8, getWord() & 0xFF); + } + }; +}; diff --git a/src/modules/chips/atsame51j20a/registers.zig b/src/modules/chips/atsame51j20a/registers.zig new file mode 100644 index 0000000..de11221 --- /dev/null +++ b/src/modules/chips/atsame51j20a/registers.zig @@ -0,0 +1,25436 @@ +// this file was generated by regz: https://github.com/ZigEmbeddedGroup/regz +// commit: 4b04e50cf14a3df87662dc79863e9b7e3dfc6591 +// +// vendor: Microchip Technology +// device: ATSAME51J20A +// cpu: CM4 + +pub const VectorTable = extern struct { + initial_stack_pointer: u32, + Reset: InterruptVector = unhandled, + NMI: InterruptVector = unhandled, + HardFault: InterruptVector = unhandled, + MemManage: InterruptVector = unhandled, + BusFault: InterruptVector = unhandled, + UsageFault: InterruptVector = unhandled, + reserved0: [4]u32 = undefined, + SVCall: InterruptVector = unhandled, + reserved1: [2]u32 = undefined, + PendSV: InterruptVector = unhandled, + SysTick: InterruptVector = unhandled, + PM: InterruptVector = unhandled, + MCLK: InterruptVector = unhandled, + OSCCTRL_XOSC0: InterruptVector = unhandled, + OSCCTRL_XOSC1: InterruptVector = unhandled, + OSCCTRL_DFLL: InterruptVector = unhandled, + OSCCTRL_DPLL0: InterruptVector = unhandled, + OSCCTRL_DPLL1: InterruptVector = unhandled, + OSC32KCTRL: InterruptVector = unhandled, + SUPC_OTHER: InterruptVector = unhandled, + SUPC_BODDET: InterruptVector = unhandled, + WDT: InterruptVector = unhandled, + RTC: InterruptVector = unhandled, + EIC_EXTINT_0: InterruptVector = unhandled, + EIC_EXTINT_1: InterruptVector = unhandled, + EIC_EXTINT_2: InterruptVector = unhandled, + EIC_EXTINT_3: InterruptVector = unhandled, + EIC_EXTINT_4: InterruptVector = unhandled, + EIC_EXTINT_5: InterruptVector = unhandled, + EIC_EXTINT_6: InterruptVector = unhandled, + EIC_EXTINT_7: InterruptVector = unhandled, + EIC_EXTINT_8: InterruptVector = unhandled, + EIC_EXTINT_9: InterruptVector = unhandled, + EIC_EXTINT_10: InterruptVector = unhandled, + EIC_EXTINT_11: InterruptVector = unhandled, + EIC_EXTINT_12: InterruptVector = unhandled, + EIC_EXTINT_13: InterruptVector = unhandled, + EIC_EXTINT_14: InterruptVector = unhandled, + EIC_EXTINT_15: InterruptVector = unhandled, + FREQM: InterruptVector = unhandled, + NVMCTRL_0: InterruptVector = unhandled, + NVMCTRL_1: InterruptVector = unhandled, + DMAC_0: InterruptVector = unhandled, + DMAC_1: InterruptVector = unhandled, + DMAC_2: InterruptVector = unhandled, + DMAC_3: InterruptVector = unhandled, + DMAC_OTHER: InterruptVector = unhandled, + EVSYS_0: InterruptVector = unhandled, + EVSYS_1: InterruptVector = unhandled, + EVSYS_2: InterruptVector = unhandled, + EVSYS_3: InterruptVector = unhandled, + EVSYS_OTHER: InterruptVector = unhandled, + PAC: InterruptVector = unhandled, + reserved2: u32 = undefined, + reserved3: u32 = undefined, + reserved4: u32 = undefined, + RAMECC: InterruptVector = unhandled, + SERCOM0_0: InterruptVector = unhandled, + SERCOM0_1: InterruptVector = unhandled, + SERCOM0_2: InterruptVector = unhandled, + SERCOM0_OTHER: InterruptVector = unhandled, + SERCOM1_0: InterruptVector = unhandled, + SERCOM1_1: InterruptVector = unhandled, + SERCOM1_2: InterruptVector = unhandled, + SERCOM1_OTHER: InterruptVector = unhandled, + SERCOM2_0: InterruptVector = unhandled, + SERCOM2_1: InterruptVector = unhandled, + SERCOM2_2: InterruptVector = unhandled, + SERCOM2_OTHER: InterruptVector = unhandled, + SERCOM3_0: InterruptVector = unhandled, + SERCOM3_1: InterruptVector = unhandled, + SERCOM3_2: InterruptVector = unhandled, + SERCOM3_OTHER: InterruptVector = unhandled, + SERCOM4_0: InterruptVector = unhandled, + SERCOM4_1: InterruptVector = unhandled, + SERCOM4_2: InterruptVector = unhandled, + SERCOM4_OTHER: InterruptVector = unhandled, + SERCOM5_0: InterruptVector = unhandled, + SERCOM5_1: InterruptVector = unhandled, + SERCOM5_2: InterruptVector = unhandled, + SERCOM5_OTHER: InterruptVector = unhandled, + reserved5: u32 = undefined, + reserved6: u32 = undefined, + reserved7: u32 = undefined, + reserved8: u32 = undefined, + reserved9: u32 = undefined, + reserved10: u32 = undefined, + reserved11: u32 = undefined, + reserved12: u32 = undefined, + CAN0: InterruptVector = unhandled, + CAN1: InterruptVector = unhandled, + USB_OTHER: InterruptVector = unhandled, + USB_SOF_HSOF: InterruptVector = unhandled, + USB_TRCPT0: InterruptVector = unhandled, + USB_TRCPT1: InterruptVector = unhandled, + reserved13: u32 = undefined, + TCC0_OTHER: InterruptVector = unhandled, + TCC0_MC0: InterruptVector = unhandled, + TCC0_MC1: InterruptVector = unhandled, + TCC0_MC2: InterruptVector = unhandled, + TCC0_MC3: InterruptVector = unhandled, + TCC0_MC4: InterruptVector = unhandled, + TCC0_MC5: InterruptVector = unhandled, + TCC1_OTHER: InterruptVector = unhandled, + TCC1_MC0: InterruptVector = unhandled, + TCC1_MC1: InterruptVector = unhandled, + TCC1_MC2: InterruptVector = unhandled, + TCC1_MC3: InterruptVector = unhandled, + TCC2_OTHER: InterruptVector = unhandled, + TCC2_MC0: InterruptVector = unhandled, + TCC2_MC1: InterruptVector = unhandled, + TCC2_MC2: InterruptVector = unhandled, + TCC3_OTHER: InterruptVector = unhandled, + TCC3_MC0: InterruptVector = unhandled, + TCC3_MC1: InterruptVector = unhandled, + TCC4_OTHER: InterruptVector = unhandled, + TCC4_MC0: InterruptVector = unhandled, + TCC4_MC1: InterruptVector = unhandled, + TC0: InterruptVector = unhandled, + TC1: InterruptVector = unhandled, + TC2: InterruptVector = unhandled, + TC3: InterruptVector = unhandled, + TC4: InterruptVector = unhandled, + TC5: InterruptVector = unhandled, + reserved14: u32 = undefined, + reserved15: u32 = undefined, + PDEC_OTHER: InterruptVector = unhandled, + PDEC_MC0: InterruptVector = unhandled, + PDEC_MC1: InterruptVector = unhandled, + ADC0_OTHER: InterruptVector = unhandled, + ADC0_RESRDY: InterruptVector = unhandled, + ADC1_OTHER: InterruptVector = unhandled, + ADC1_RESRDY: InterruptVector = unhandled, + AC: InterruptVector = unhandled, + DAC_OTHER: InterruptVector = unhandled, + DAC_EMPTY_0: InterruptVector = unhandled, + DAC_EMPTY_1: InterruptVector = unhandled, + DAC_RESRDY_0: InterruptVector = unhandled, + DAC_RESRDY_1: InterruptVector = unhandled, + I2S: InterruptVector = unhandled, + PCC: InterruptVector = unhandled, + AES: InterruptVector = unhandled, + TRNG: InterruptVector = unhandled, + ICM: InterruptVector = unhandled, + reserved16: u32 = undefined, + QSPI: InterruptVector = unhandled, + SDHC0: InterruptVector = unhandled, +}; + +pub const registers = struct { + /// System Control Space + pub const SCS = struct { + pub const base_address = 0xe000e000; + + /// System Tick Timer + pub const SysTick = struct { + /// address: 0xe000e010 + /// SysTick Control and Status Register + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + ENABLE: u1, + TICKINT: u1, + CLKSOURCE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + COUNTFLAG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x10); + + /// address: 0xe000e014 + /// SysTick Reload Value Register + pub const LOAD = @intToPtr(*volatile Mmio(32, packed struct { + RELOAD: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x14); + + /// address: 0xe000e018 + /// SysTick Current Value Register + pub const VAL = @intToPtr(*volatile Mmio(32, packed struct { + CURRENT: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x18); + + /// address: 0xe000e01c + /// SysTick Calibration Register + pub const CALIB = @intToPtr(*volatile Mmio(32, packed struct { + TENMS: u24, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + SKEW: u1, + NOREF: u1, + }), base_address + 0x1c); + }; + }; + + /// Analog Comparators + pub const AC = struct { + pub const base_address = 0x42002000; + pub const version = "U25011.0.0"; + + /// address: 0x42002000 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x0); + + /// address: 0x42002001 + /// Control B + pub const CTRLB = @intToPtr(*volatile Mmio(8, packed struct { + /// Comparator 0 Start Comparison + START0: u1, + /// Comparator 1 Start Comparison + START1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x1); + + /// address: 0x42002002 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(16, packed struct { + /// Comparator 0 Event Output Enable + COMPEO0: u1, + /// Comparator 1 Event Output Enable + COMPEO1: u1, + reserved0: u1, + reserved1: u1, + /// Window 0 Event Output Enable + WINEO0: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Comparator 0 Event Input Enable + COMPEI0: u1, + /// Comparator 1 Event Input Enable + COMPEI1: u1, + reserved5: u1, + reserved6: u1, + /// Comparator 0 Input Event Invert Enable + INVEI0: u1, + /// Comparator 1 Input Event Invert Enable + INVEI1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x2); + + /// address: 0x42002004 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Comparator 0 Interrupt Enable + COMP0: u1, + /// Comparator 1 Interrupt Enable + COMP1: u1, + reserved0: u1, + reserved1: u1, + /// Window 0 Interrupt Enable + WIN0: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x4); + + /// address: 0x42002005 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Comparator 0 Interrupt Enable + COMP0: u1, + /// Comparator 1 Interrupt Enable + COMP1: u1, + reserved0: u1, + reserved1: u1, + /// Window 0 Interrupt Enable + WIN0: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x5); + + /// address: 0x42002006 + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Comparator 0 + COMP0: u1, + /// Comparator 1 + COMP1: u1, + reserved0: u1, + reserved1: u1, + /// Window 0 + WIN0: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x6); + + /// address: 0x42002007 + /// Status A + pub const STATUSA = @intToPtr(*volatile Mmio(8, packed struct { + /// Comparator 0 Current State + STATE0: u1, + /// Comparator 1 Current State + STATE1: u1, + reserved0: u1, + reserved1: u1, + /// Window 0 Current State + WSTATE0: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x7); + + /// address: 0x42002008 + /// Status B + pub const STATUSB = @intToPtr(*volatile Mmio(8, packed struct { + /// Comparator 0 Ready + READY0: u1, + /// Comparator 1 Ready + READY1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x8); + + /// address: 0x42002009 + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Run + DBGRUN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x9); + + /// address: 0x4200200a + /// Window Control + pub const WINCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Window 0 Mode Enable + WEN0: u1, + /// Window 0 Interrupt Selection + WINTSEL0: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0xa); + + /// address: 0x4200200c + /// Scaler n + pub const SCALER = @intToPtr(*volatile [2]Mmio(8, packed struct { + /// Scaler Value + VALUE: u6, + padding0: u1, + padding1: u1, + }), base_address + 0xc); + + /// address: 0x42002010 + /// Comparator Control n + pub const COMPCTRL = @intToPtr(*volatile [2]Mmio(32, packed struct { + reserved0: u1, + /// Enable + ENABLE: u1, + /// Single-Shot Mode + SINGLE: u1, + /// Interrupt Selection + INTSEL: u2, + reserved1: u1, + /// Run in Standby + RUNSTDBY: u1, + reserved2: u1, + /// Negative Input Mux Selection + MUXNEG: u3, + reserved3: u1, + /// Positive Input Mux Selection + MUXPOS: u3, + /// Swap Inputs and Invert + SWAP: u1, + /// Speed Selection + SPEED: u2, + reserved4: u1, + /// Hysteresis Enable + HYSTEN: u1, + /// Hysteresis Level + HYST: u2, + reserved5: u1, + reserved6: u1, + /// Filter Length + FLEN: u3, + reserved7: u1, + /// Output + OUT: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x10); + + /// address: 0x42002020 + /// Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset Synchronization Busy + SWRST: u1, + /// Enable Synchronization Busy + ENABLE: u1, + /// WINCTRL Synchronization Busy + WINCTRL: u1, + /// COMPCTRL 0 Synchronization Busy + COMPCTRL0: u1, + /// COMPCTRL 1 Synchronization Busy + COMPCTRL1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x20); + + /// address: 0x42002024 + /// Calibration + pub const CALIB = @intToPtr(*volatile Mmio(16, packed struct { + /// COMP0/1 Bias Scaling + BIAS0: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x24); + }; + + /// Analog Digital Converter + pub const ADC0 = struct { + pub const base_address = 0x43001c00; + pub const version = "U25001.0.0"; + + /// address: 0x43001c00 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(16, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + reserved0: u1, + /// Dual Mode Trigger Selection + DUALSEL: u2, + /// Slave Enable + SLAVEEN: u1, + /// Run in Standby + RUNSTDBY: u1, + /// On Demand Control + ONDEMAND: u1, + /// Prescaler Configuration + PRESCALER: u3, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Rail to Rail Operation Enable + R2R: u1, + }), base_address + 0x0); + + /// address: 0x43001c02 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Flush Event Input Enable + FLUSHEI: u1, + /// Start Conversion Event Input Enable + STARTEI: u1, + /// Flush Event Invert Enable + FLUSHINV: u1, + /// Start Conversion Event Invert Enable + STARTINV: u1, + /// Result Ready Event Out + RESRDYEO: u1, + /// Window Monitor Event Out + WINMONEO: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x2); + + /// address: 0x43001c03 + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Run + DBGRUN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x3); + + /// address: 0x43001c04 + /// Input Control + pub const INPUTCTRL = @intToPtr(*volatile Mmio(16, packed struct { + /// Positive Mux Input Selection + MUXPOS: u5, + reserved0: u1, + reserved1: u1, + /// Differential Mode + DIFFMODE: u1, + /// Negative Mux Input Selection + MUXNEG: u5, + reserved2: u1, + reserved3: u1, + /// Stop DMA Sequencing + DSEQSTOP: u1, + }), base_address + 0x4); + + /// address: 0x43001c06 + /// Control B + pub const CTRLB = @intToPtr(*volatile Mmio(16, packed struct { + /// Left-Adjusted Result + LEFTADJ: u1, + /// Free Running Mode + FREERUN: u1, + /// Digital Correction Logic Enable + CORREN: u1, + /// Conversion Result Resolution + RESSEL: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Window Monitor Mode + WINMODE: u3, + /// Window Single Sample + WINSS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x6); + + /// address: 0x43001c08 + /// Reference Control + pub const REFCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Reference Selection + REFSEL: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Reference Buffer Offset Compensation Enable + REFCOMP: u1, + }), base_address + 0x8); + + /// address: 0x43001c0a + /// Average Control + pub const AVGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Number of Samples to be Collected + SAMPLENUM: u4, + /// Adjusting Result / Division Coefficient + ADJRES: u3, + padding0: u1, + }), base_address + 0xa); + + /// address: 0x43001c0b + /// Sample Time Control + pub const SAMPCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Sampling Time Length + SAMPLEN: u6, + reserved0: u1, + /// Comparator Offset Compensation Enable + OFFCOMP: u1, + }), base_address + 0xb); + + /// address: 0x43001c0c + /// Window Monitor Lower Threshold + pub const WINLT = @intToPtr(*volatile u16, base_address + 0xc); + + /// address: 0x43001c0e + /// Window Monitor Upper Threshold + pub const WINUT = @intToPtr(*volatile u16, base_address + 0xe); + + /// address: 0x43001c10 + /// Gain Correction + pub const GAINCORR = @intToPtr(*volatile MmioInt(16, u12), base_address + 0x10); + + /// address: 0x43001c12 + /// Offset Correction + pub const OFFSETCORR = @intToPtr(*volatile MmioInt(16, u12), base_address + 0x12); + + /// address: 0x43001c14 + /// Software Trigger + pub const SWTRIG = @intToPtr(*volatile Mmio(8, packed struct { + /// ADC Conversion Flush + FLUSH: u1, + /// Start ADC Conversion + START: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x14); + + /// address: 0x43001c2c + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Result Ready Interrupt Disable + RESRDY: u1, + /// Overrun Interrupt Disable + OVERRUN: u1, + /// Window Monitor Interrupt Disable + WINMON: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x2c); + + /// address: 0x43001c2d + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Result Ready Interrupt Enable + RESRDY: u1, + /// Overrun Interrupt Enable + OVERRUN: u1, + /// Window Monitor Interrupt Enable + WINMON: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x2d); + + /// address: 0x43001c2e + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Result Ready Interrupt Flag + RESRDY: u1, + /// Overrun Interrupt Flag + OVERRUN: u1, + /// Window Monitor Interrupt Flag + WINMON: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x2e); + + /// address: 0x43001c2f + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { + /// ADC Busy Status + ADCBUSY: u1, + reserved0: u1, + /// Window Comparator Counter + WCC: u6, + }), base_address + 0x2f); + + /// address: 0x43001c30 + /// Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// SWRST Synchronization Busy + SWRST: u1, + /// ENABLE Synchronization Busy + ENABLE: u1, + /// Input Control Synchronization Busy + INPUTCTRL: u1, + /// Control B Synchronization Busy + CTRLB: u1, + /// Reference Control Synchronization Busy + REFCTRL: u1, + /// Average Control Synchronization Busy + AVGCTRL: u1, + /// Sampling Time Control Synchronization Busy + SAMPCTRL: u1, + /// Window Monitor Lower Threshold Synchronization Busy + WINLT: u1, + /// Window Monitor Upper Threshold Synchronization Busy + WINUT: u1, + /// Gain Correction Synchronization Busy + GAINCORR: u1, + /// Offset Correction Synchronization Busy + OFFSETCORR: u1, + /// Software Trigger Synchronization Busy + SWTRIG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x30); + + /// address: 0x43001c34 + /// DMA Sequencial Data + pub const DSEQDATA = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Sequential Data + DATA: u32, + }), base_address + 0x34); + + /// address: 0x43001c38 + /// DMA Sequential Control + pub const DSEQCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Input Control + INPUTCTRL: u1, + /// Control B + CTRLB: u1, + /// Reference Control + REFCTRL: u1, + /// Average Control + AVGCTRL: u1, + /// Sampling Time Control + SAMPCTRL: u1, + /// Window Monitor Lower Threshold + WINLT: u1, + /// Window Monitor Upper Threshold + WINUT: u1, + /// Gain Correction + GAINCORR: u1, + /// Offset Correction + OFFSETCORR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// ADC Auto-Start Conversion + AUTOSTART: u1, + }), base_address + 0x38); + + /// address: 0x43001c3c + /// DMA Sequencial Status + pub const DSEQSTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Input Control + INPUTCTRL: u1, + /// Control B + CTRLB: u1, + /// Reference Control + REFCTRL: u1, + /// Average Control + AVGCTRL: u1, + /// Sampling Time Control + SAMPCTRL: u1, + /// Window Monitor Lower Threshold + WINLT: u1, + /// Window Monitor Upper Threshold + WINUT: u1, + /// Gain Correction + GAINCORR: u1, + /// Offset Correction + OFFSETCORR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// DMA Sequencing Busy + BUSY: u1, + }), base_address + 0x3c); + + /// address: 0x43001c40 + /// Result Conversion Value + pub const RESULT = @intToPtr(*volatile u16, base_address + 0x40); + + /// address: 0x43001c44 + /// Last Sample Result + pub const RESS = @intToPtr(*volatile u16, base_address + 0x44); + + /// address: 0x43001c48 + /// Calibration + pub const CALIB = @intToPtr(*volatile Mmio(16, packed struct { + /// Bias Comparator Scaling + BIASCOMP: u3, + reserved0: u1, + /// Bias R2R Ampli scaling + BIASR2R: u3, + reserved1: u1, + /// Bias Reference Buffer Scaling + BIASREFBUF: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x48); + }; + pub const ADC1 = struct { + pub const base_address = 0x43002000; + + /// address: 0x43002000 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(16, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + reserved0: u1, + /// Dual Mode Trigger Selection + DUALSEL: u2, + /// Slave Enable + SLAVEEN: u1, + /// Run in Standby + RUNSTDBY: u1, + /// On Demand Control + ONDEMAND: u1, + /// Prescaler Configuration + PRESCALER: u3, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Rail to Rail Operation Enable + R2R: u1, + }), base_address + 0x0); + + /// address: 0x43002002 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Flush Event Input Enable + FLUSHEI: u1, + /// Start Conversion Event Input Enable + STARTEI: u1, + /// Flush Event Invert Enable + FLUSHINV: u1, + /// Start Conversion Event Invert Enable + STARTINV: u1, + /// Result Ready Event Out + RESRDYEO: u1, + /// Window Monitor Event Out + WINMONEO: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x2); + + /// address: 0x43002003 + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Run + DBGRUN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x3); + + /// address: 0x43002004 + /// Input Control + pub const INPUTCTRL = @intToPtr(*volatile Mmio(16, packed struct { + /// Positive Mux Input Selection + MUXPOS: u5, + reserved0: u1, + reserved1: u1, + /// Differential Mode + DIFFMODE: u1, + /// Negative Mux Input Selection + MUXNEG: u5, + reserved2: u1, + reserved3: u1, + /// Stop DMA Sequencing + DSEQSTOP: u1, + }), base_address + 0x4); + + /// address: 0x43002006 + /// Control B + pub const CTRLB = @intToPtr(*volatile Mmio(16, packed struct { + /// Left-Adjusted Result + LEFTADJ: u1, + /// Free Running Mode + FREERUN: u1, + /// Digital Correction Logic Enable + CORREN: u1, + /// Conversion Result Resolution + RESSEL: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Window Monitor Mode + WINMODE: u3, + /// Window Single Sample + WINSS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x6); + + /// address: 0x43002008 + /// Reference Control + pub const REFCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Reference Selection + REFSEL: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Reference Buffer Offset Compensation Enable + REFCOMP: u1, + }), base_address + 0x8); + + /// address: 0x4300200a + /// Average Control + pub const AVGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Number of Samples to be Collected + SAMPLENUM: u4, + /// Adjusting Result / Division Coefficient + ADJRES: u3, + padding0: u1, + }), base_address + 0xa); + + /// address: 0x4300200b + /// Sample Time Control + pub const SAMPCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Sampling Time Length + SAMPLEN: u6, + reserved0: u1, + /// Comparator Offset Compensation Enable + OFFCOMP: u1, + }), base_address + 0xb); + + /// address: 0x4300200c + /// Window Monitor Lower Threshold + pub const WINLT = @intToPtr(*volatile u16, base_address + 0xc); + + /// address: 0x4300200e + /// Window Monitor Upper Threshold + pub const WINUT = @intToPtr(*volatile u16, base_address + 0xe); + + /// address: 0x43002010 + /// Gain Correction + pub const GAINCORR = @intToPtr(*volatile MmioInt(16, u12), base_address + 0x10); + + /// address: 0x43002012 + /// Offset Correction + pub const OFFSETCORR = @intToPtr(*volatile MmioInt(16, u12), base_address + 0x12); + + /// address: 0x43002014 + /// Software Trigger + pub const SWTRIG = @intToPtr(*volatile Mmio(8, packed struct { + /// ADC Conversion Flush + FLUSH: u1, + /// Start ADC Conversion + START: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x14); + + /// address: 0x4300202c + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Result Ready Interrupt Disable + RESRDY: u1, + /// Overrun Interrupt Disable + OVERRUN: u1, + /// Window Monitor Interrupt Disable + WINMON: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x2c); + + /// address: 0x4300202d + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Result Ready Interrupt Enable + RESRDY: u1, + /// Overrun Interrupt Enable + OVERRUN: u1, + /// Window Monitor Interrupt Enable + WINMON: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x2d); + + /// address: 0x4300202e + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Result Ready Interrupt Flag + RESRDY: u1, + /// Overrun Interrupt Flag + OVERRUN: u1, + /// Window Monitor Interrupt Flag + WINMON: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x2e); + + /// address: 0x4300202f + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { + /// ADC Busy Status + ADCBUSY: u1, + reserved0: u1, + /// Window Comparator Counter + WCC: u6, + }), base_address + 0x2f); + + /// address: 0x43002030 + /// Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// SWRST Synchronization Busy + SWRST: u1, + /// ENABLE Synchronization Busy + ENABLE: u1, + /// Input Control Synchronization Busy + INPUTCTRL: u1, + /// Control B Synchronization Busy + CTRLB: u1, + /// Reference Control Synchronization Busy + REFCTRL: u1, + /// Average Control Synchronization Busy + AVGCTRL: u1, + /// Sampling Time Control Synchronization Busy + SAMPCTRL: u1, + /// Window Monitor Lower Threshold Synchronization Busy + WINLT: u1, + /// Window Monitor Upper Threshold Synchronization Busy + WINUT: u1, + /// Gain Correction Synchronization Busy + GAINCORR: u1, + /// Offset Correction Synchronization Busy + OFFSETCORR: u1, + /// Software Trigger Synchronization Busy + SWTRIG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x30); + + /// address: 0x43002034 + /// DMA Sequencial Data + pub const DSEQDATA = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Sequential Data + DATA: u32, + }), base_address + 0x34); + + /// address: 0x43002038 + /// DMA Sequential Control + pub const DSEQCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Input Control + INPUTCTRL: u1, + /// Control B + CTRLB: u1, + /// Reference Control + REFCTRL: u1, + /// Average Control + AVGCTRL: u1, + /// Sampling Time Control + SAMPCTRL: u1, + /// Window Monitor Lower Threshold + WINLT: u1, + /// Window Monitor Upper Threshold + WINUT: u1, + /// Gain Correction + GAINCORR: u1, + /// Offset Correction + OFFSETCORR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// ADC Auto-Start Conversion + AUTOSTART: u1, + }), base_address + 0x38); + + /// address: 0x4300203c + /// DMA Sequencial Status + pub const DSEQSTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Input Control + INPUTCTRL: u1, + /// Control B + CTRLB: u1, + /// Reference Control + REFCTRL: u1, + /// Average Control + AVGCTRL: u1, + /// Sampling Time Control + SAMPCTRL: u1, + /// Window Monitor Lower Threshold + WINLT: u1, + /// Window Monitor Upper Threshold + WINUT: u1, + /// Gain Correction + GAINCORR: u1, + /// Offset Correction + OFFSETCORR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// DMA Sequencing Busy + BUSY: u1, + }), base_address + 0x3c); + + /// address: 0x43002040 + /// Result Conversion Value + pub const RESULT = @intToPtr(*volatile u16, base_address + 0x40); + + /// address: 0x43002044 + /// Last Sample Result + pub const RESS = @intToPtr(*volatile u16, base_address + 0x44); + + /// address: 0x43002048 + /// Calibration + pub const CALIB = @intToPtr(*volatile Mmio(16, packed struct { + /// Bias Comparator Scaling + BIASCOMP: u3, + reserved0: u1, + /// Bias R2R Ampli scaling + BIASR2R: u3, + reserved1: u1, + /// Bias Reference Buffer Scaling + BIASREFBUF: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x48); + }; + + /// Advanced Encryption Standard + pub const AES = struct { + pub const base_address = 0x42002400; + pub const version = "U22382.2.0"; + + /// address: 0x42002400 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// AES Modes of operation + AESMODE: u3, + /// Cipher Feedback Block Size + CFBS: u3, + /// Encryption Key Size + KEYSIZE: u2, + /// Cipher Mode + CIPHER: u1, + /// Start Mode Select + STARTMODE: u1, + /// Last Output Data Mode + LOD: u1, + /// Last Key Generation + KEYGEN: u1, + /// XOR Key Operation + XORKEY: u1, + reserved0: u1, + /// Counter Measure Type + CTYPE: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x0); + + /// address: 0x42002404 + /// Control B + pub const CTRLB = @intToPtr(*volatile Mmio(8, packed struct { + /// Start Encryption/Decryption + START: u1, + /// New message + NEWMSG: u1, + /// End of message + EOM: u1, + /// GF Multiplication + GFMUL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x4); + + /// address: 0x42002405 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Encryption Complete Interrupt Enable + ENCCMP: u1, + /// GF Multiplication Complete Interrupt Enable + GFMCMP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x5); + + /// address: 0x42002406 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Encryption Complete Interrupt Enable + ENCCMP: u1, + /// GF Multiplication Complete Interrupt Enable + GFMCMP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x6); + + /// address: 0x42002407 + /// Interrupt Flag Status + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Encryption Complete + ENCCMP: u1, + /// GF Multiplication Complete + GFMCMP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x7); + + /// address: 0x42002408 + /// Data buffer pointer + pub const DATABUFPTR = @intToPtr(*volatile Mmio(8, packed struct { + /// Input Data Pointer + INDATAPTR: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x8); + + /// address: 0x42002409 + /// Debug control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Run + DBGRUN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x9); + + /// address: 0x4200240c + /// Keyword n + pub const KEYWORD = @intToPtr(*volatile [8]u32, base_address + 0xc); + + /// address: 0x42002438 + /// Indata + pub const INDATA = @intToPtr(*volatile u32, base_address + 0x38); + + /// address: 0x4200243c + /// Initialisation Vector n + pub const INTVECTV = @intToPtr(*volatile [4]u32, base_address + 0x3c); + + /// address: 0x4200245c + /// Hash key n + pub const HASHKEY = @intToPtr(*volatile [4]u32, base_address + 0x5c); + + /// address: 0x4200246c + /// Galois Hash n + pub const GHASH = @intToPtr(*volatile [4]u32, base_address + 0x6c); + + /// address: 0x42002480 + /// Cipher Length + pub const CIPLEN = @intToPtr(*volatile u32, base_address + 0x80); + + /// address: 0x42002484 + /// Random Seed + pub const RANDSEED = @intToPtr(*volatile u32, base_address + 0x84); + }; + + /// Control Area Network + pub const CAN0 = struct { + pub const base_address = 0x42000000; + pub const version = "U20033.2.1"; + + /// address: 0x42000000 + /// Core Release + pub const CREL = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + /// Sub-step of Core Release + SUBSTEP: u4, + /// Step of Core Release + STEP: u4, + /// Core Release + REL: u4, + }), base_address + 0x0); + + /// address: 0x42000004 + /// Endian + pub const ENDN = @intToPtr(*volatile Mmio(32, packed struct { + /// Endianness Test Value + ETV: u32, + }), base_address + 0x4); + + /// address: 0x42000008 + /// Message RAM Configuration + pub const MRCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Quality of Service + QOS: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x8); + + /// address: 0x4200000c + /// Fast Bit Timing and Prescaler + pub const DBTP = @intToPtr(*volatile Mmio(32, packed struct { + /// Data (Re)Synchronization Jump Width + DSJW: u4, + /// Data time segment after sample point + DTSEG2: u4, + /// Data time segment before sample point + DTSEG1: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Data Baud Rate Prescaler + DBRP: u5, + reserved3: u1, + reserved4: u1, + /// Tranceiver Delay Compensation + TDC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0xc); + + /// address: 0x42000010 + /// Test + pub const TEST = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Loop Back Mode + LBCK: u1, + /// Control of Transmit Pin + TX: u2, + /// Receive Pin + RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x10); + + /// address: 0x42000014 + /// RAM Watchdog + pub const RWD = @intToPtr(*volatile Mmio(32, packed struct { + /// Watchdog Configuration + WDC: u8, + /// Watchdog Value + WDV: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x42000018 + /// CC Control + pub const CCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Initialization + INIT: u1, + /// Configuration Change Enable + CCE: u1, + /// ASM Restricted Operation Mode + ASM: u1, + /// Clock Stop Acknowledge + CSA: u1, + /// Clock Stop Request + CSR: u1, + /// Bus Monitoring Mode + MON: u1, + /// Disable Automatic Retransmission + DAR: u1, + /// Test Mode Enable + TEST: u1, + /// FD Operation Enable + FDOE: u1, + /// Bit Rate Switch Enable + BRSE: u1, + reserved0: u1, + reserved1: u1, + /// Protocol Exception Handling Disable + PXHD: u1, + /// Edge Filtering during Bus Integration + EFBI: u1, + /// Transmit Pause + TXP: u1, + /// Non ISO Operation + NISO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4200001c + /// Nominal Bit Timing and Prescaler + pub const NBTP = @intToPtr(*volatile Mmio(32, packed struct { + /// Nominal Time segment after sample point + NTSEG2: u7, + reserved0: u1, + /// Nominal Time segment before sample point + NTSEG1: u8, + /// Nominal Baud Rate Prescaler + NBRP: u9, + /// Nominal (Re)Synchronization Jump Width + NSJW: u7, + }), base_address + 0x1c); + + /// address: 0x42000020 + /// Timestamp Counter Configuration + pub const TSCC = @intToPtr(*volatile Mmio(32, packed struct { + /// Timestamp Select + TSS: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Timestamp Counter Prescaler + TCP: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x20); + + /// address: 0x42000024 + /// Timestamp Counter Value + pub const TSCV = @intToPtr(*volatile Mmio(32, packed struct { + /// Timestamp Counter + TSC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x24); + + /// address: 0x42000028 + /// Timeout Counter Configuration + pub const TOCC = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable Timeout Counter + ETOC: u1, + /// Timeout Select + TOS: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Timeout Period + TOP: u16, + }), base_address + 0x28); + + /// address: 0x4200002c + /// Timeout Counter Value + pub const TOCV = @intToPtr(*volatile Mmio(32, packed struct { + /// Timeout Counter + TOC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x2c); + + /// address: 0x42000040 + /// Error Counter + pub const ECR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit Error Counter + TEC: u8, + /// Receive Error Counter + REC: u7, + /// Receive Error Passive + RP: u1, + /// CAN Error Logging + CEL: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x42000044 + /// Protocol Status + pub const PSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Last Error Code + LEC: u3, + /// Activity + ACT: u2, + /// Error Passive + EP: u1, + /// Warning Status + EW: u1, + /// Bus_Off Status + BO: u1, + /// Data Phase Last Error Code + DLEC: u3, + /// ESI flag of last received CAN FD Message + RESI: u1, + /// BRS flag of last received CAN FD Message + RBRS: u1, + /// Received a CAN FD Message + RFDF: u1, + /// Protocol Exception Event + PXE: u1, + reserved0: u1, + /// Transmitter Delay Compensation Value + TDCV: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x44); + + /// address: 0x42000048 + /// Extended ID Filter Configuration + pub const TDCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmitter Delay Compensation Filter Length + TDCF: u7, + reserved0: u1, + /// Transmitter Delay Compensation Offset + TDCO: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x48); + + /// address: 0x42000050 + /// Interrupt + pub const IR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 0 New Message + RF0N: u1, + /// Rx FIFO 0 Watermark Reached + RF0W: u1, + /// Rx FIFO 0 Full + RF0F: u1, + /// Rx FIFO 0 Message Lost + RF0L: u1, + /// Rx FIFO 1 New Message + RF1N: u1, + /// Rx FIFO 1 Watermark Reached + RF1W: u1, + /// Rx FIFO 1 FIFO Full + RF1F: u1, + /// Rx FIFO 1 Message Lost + RF1L: u1, + /// High Priority Message + HPM: u1, + /// Timestamp Completed + TC: u1, + /// Transmission Cancellation Finished + TCF: u1, + /// Tx FIFO Empty + TFE: u1, + /// Tx Event FIFO New Entry + TEFN: u1, + /// Tx Event FIFO Watermark Reached + TEFW: u1, + /// Tx Event FIFO Full + TEFF: u1, + /// Tx Event FIFO Element Lost + TEFL: u1, + /// Timestamp Wraparound + TSW: u1, + /// Message RAM Access Failure + MRAF: u1, + /// Timeout Occurred + TOO: u1, + /// Message stored to Dedicated Rx Buffer + DRX: u1, + /// Bit Error Corrected + BEC: u1, + /// Bit Error Uncorrected + BEU: u1, + /// Error Logging Overflow + ELO: u1, + /// Error Passive + EP: u1, + /// Warning Status + EW: u1, + /// Bus_Off Status + BO: u1, + /// Watchdog Interrupt + WDI: u1, + /// Protocol Error in Arbitration Phase + PEA: u1, + /// Protocol Error in Data Phase + PED: u1, + /// Access to Reserved Address + ARA: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x50); + + /// address: 0x42000054 + /// Interrupt Enable + pub const IE = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 0 New Message Interrupt Enable + RF0NE: u1, + /// Rx FIFO 0 Watermark Reached Interrupt Enable + RF0WE: u1, + /// Rx FIFO 0 Full Interrupt Enable + RF0FE: u1, + /// Rx FIFO 0 Message Lost Interrupt Enable + RF0LE: u1, + /// Rx FIFO 1 New Message Interrupt Enable + RF1NE: u1, + /// Rx FIFO 1 Watermark Reached Interrupt Enable + RF1WE: u1, + /// Rx FIFO 1 FIFO Full Interrupt Enable + RF1FE: u1, + /// Rx FIFO 1 Message Lost Interrupt Enable + RF1LE: u1, + /// High Priority Message Interrupt Enable + HPME: u1, + /// Timestamp Completed Interrupt Enable + TCE: u1, + /// Transmission Cancellation Finished Interrupt Enable + TCFE: u1, + /// Tx FIFO Empty Interrupt Enable + TFEE: u1, + /// Tx Event FIFO New Entry Interrupt Enable + TEFNE: u1, + /// Tx Event FIFO Watermark Reached Interrupt Enable + TEFWE: u1, + /// Tx Event FIFO Full Interrupt Enable + TEFFE: u1, + /// Tx Event FIFO Element Lost Interrupt Enable + TEFLE: u1, + /// Timestamp Wraparound Interrupt Enable + TSWE: u1, + /// Message RAM Access Failure Interrupt Enable + MRAFE: u1, + /// Timeout Occurred Interrupt Enable + TOOE: u1, + /// Message stored to Dedicated Rx Buffer Interrupt Enable + DRXE: u1, + /// Bit Error Corrected Interrupt Enable + BECE: u1, + /// Bit Error Uncorrected Interrupt Enable + BEUE: u1, + /// Error Logging Overflow Interrupt Enable + ELOE: u1, + /// Error Passive Interrupt Enable + EPE: u1, + /// Warning Status Interrupt Enable + EWE: u1, + /// Bus_Off Status Interrupt Enable + BOE: u1, + /// Watchdog Interrupt Interrupt Enable + WDIE: u1, + /// Protocol Error in Arbitration Phase Enable + PEAE: u1, + /// Protocol Error in Data Phase Enable + PEDE: u1, + /// Access to Reserved Address Enable + ARAE: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x54); + + /// address: 0x42000058 + /// Interrupt Line Select + pub const ILS = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 0 New Message Interrupt Line + RF0NL: u1, + /// Rx FIFO 0 Watermark Reached Interrupt Line + RF0WL: u1, + /// Rx FIFO 0 Full Interrupt Line + RF0FL: u1, + /// Rx FIFO 0 Message Lost Interrupt Line + RF0LL: u1, + /// Rx FIFO 1 New Message Interrupt Line + RF1NL: u1, + /// Rx FIFO 1 Watermark Reached Interrupt Line + RF1WL: u1, + /// Rx FIFO 1 FIFO Full Interrupt Line + RF1FL: u1, + /// Rx FIFO 1 Message Lost Interrupt Line + RF1LL: u1, + /// High Priority Message Interrupt Line + HPML: u1, + /// Timestamp Completed Interrupt Line + TCL: u1, + /// Transmission Cancellation Finished Interrupt Line + TCFL: u1, + /// Tx FIFO Empty Interrupt Line + TFEL: u1, + /// Tx Event FIFO New Entry Interrupt Line + TEFNL: u1, + /// Tx Event FIFO Watermark Reached Interrupt Line + TEFWL: u1, + /// Tx Event FIFO Full Interrupt Line + TEFFL: u1, + /// Tx Event FIFO Element Lost Interrupt Line + TEFLL: u1, + /// Timestamp Wraparound Interrupt Line + TSWL: u1, + /// Message RAM Access Failure Interrupt Line + MRAFL: u1, + /// Timeout Occurred Interrupt Line + TOOL: u1, + /// Message stored to Dedicated Rx Buffer Interrupt Line + DRXL: u1, + /// Bit Error Corrected Interrupt Line + BECL: u1, + /// Bit Error Uncorrected Interrupt Line + BEUL: u1, + /// Error Logging Overflow Interrupt Line + ELOL: u1, + /// Error Passive Interrupt Line + EPL: u1, + /// Warning Status Interrupt Line + EWL: u1, + /// Bus_Off Status Interrupt Line + BOL: u1, + /// Watchdog Interrupt Interrupt Line + WDIL: u1, + /// Protocol Error in Arbitration Phase Line + PEAL: u1, + /// Protocol Error in Data Phase Line + PEDL: u1, + /// Access to Reserved Address Line + ARAL: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x58); + + /// address: 0x4200005c + /// Interrupt Line Enable + pub const ILE = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable Interrupt Line 0 + EINT0: u1, + /// Enable Interrupt Line 1 + EINT1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x5c); + + /// address: 0x42000080 + /// Global Filter Configuration + pub const GFC = @intToPtr(*volatile Mmio(32, packed struct { + /// Reject Remote Frames Extended + RRFE: u1, + /// Reject Remote Frames Standard + RRFS: u1, + /// Accept Non-matching Frames Extended + ANFE: u2, + /// Accept Non-matching Frames Standard + ANFS: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x80); + + /// address: 0x42000084 + /// Standard ID Filter Configuration + pub const SIDFC = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter List Standard Start Address + FLSSA: u16, + /// List Size Standard + LSS: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x84); + + /// address: 0x42000088 + /// Extended ID Filter Configuration + pub const XIDFC = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter List Extended Start Address + FLESA: u16, + /// List Size Extended + LSE: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x88); + + /// address: 0x42000090 + /// Extended ID AND Mask + pub const XIDAM = @intToPtr(*volatile Mmio(32, packed struct { + /// Extended ID Mask + EIDM: u29, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x90); + + /// address: 0x42000094 + /// High Priority Message Status + pub const HPMS = @intToPtr(*volatile Mmio(32, packed struct { + /// Buffer Index + BIDX: u6, + /// Message Storage Indicator + MSI: u2, + /// Filter Index + FIDX: u7, + /// Filter List + FLST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x94); + + /// address: 0x42000098 + /// New Data 1 + pub const NDAT1 = @intToPtr(*volatile Mmio(32, packed struct { + /// New Data 0 + ND0: u1, + /// New Data 1 + ND1: u1, + /// New Data 2 + ND2: u1, + /// New Data 3 + ND3: u1, + /// New Data 4 + ND4: u1, + /// New Data 5 + ND5: u1, + /// New Data 6 + ND6: u1, + /// New Data 7 + ND7: u1, + /// New Data 8 + ND8: u1, + /// New Data 9 + ND9: u1, + /// New Data 10 + ND10: u1, + /// New Data 11 + ND11: u1, + /// New Data 12 + ND12: u1, + /// New Data 13 + ND13: u1, + /// New Data 14 + ND14: u1, + /// New Data 15 + ND15: u1, + /// New Data 16 + ND16: u1, + /// New Data 17 + ND17: u1, + /// New Data 18 + ND18: u1, + /// New Data 19 + ND19: u1, + /// New Data 20 + ND20: u1, + /// New Data 21 + ND21: u1, + /// New Data 22 + ND22: u1, + /// New Data 23 + ND23: u1, + /// New Data 24 + ND24: u1, + /// New Data 25 + ND25: u1, + /// New Data 26 + ND26: u1, + /// New Data 27 + ND27: u1, + /// New Data 28 + ND28: u1, + /// New Data 29 + ND29: u1, + /// New Data 30 + ND30: u1, + /// New Data 31 + ND31: u1, + }), base_address + 0x98); + + /// address: 0x4200009c + /// New Data 2 + pub const NDAT2 = @intToPtr(*volatile Mmio(32, packed struct { + /// New Data 32 + ND32: u1, + /// New Data 33 + ND33: u1, + /// New Data 34 + ND34: u1, + /// New Data 35 + ND35: u1, + /// New Data 36 + ND36: u1, + /// New Data 37 + ND37: u1, + /// New Data 38 + ND38: u1, + /// New Data 39 + ND39: u1, + /// New Data 40 + ND40: u1, + /// New Data 41 + ND41: u1, + /// New Data 42 + ND42: u1, + /// New Data 43 + ND43: u1, + /// New Data 44 + ND44: u1, + /// New Data 45 + ND45: u1, + /// New Data 46 + ND46: u1, + /// New Data 47 + ND47: u1, + /// New Data 48 + ND48: u1, + /// New Data 49 + ND49: u1, + /// New Data 50 + ND50: u1, + /// New Data 51 + ND51: u1, + /// New Data 52 + ND52: u1, + /// New Data 53 + ND53: u1, + /// New Data 54 + ND54: u1, + /// New Data 55 + ND55: u1, + /// New Data 56 + ND56: u1, + /// New Data 57 + ND57: u1, + /// New Data 58 + ND58: u1, + /// New Data 59 + ND59: u1, + /// New Data 60 + ND60: u1, + /// New Data 61 + ND61: u1, + /// New Data 62 + ND62: u1, + /// New Data 63 + ND63: u1, + }), base_address + 0x9c); + + /// address: 0x420000a0 + /// Rx FIFO 0 Configuration + pub const RXF0C = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 0 Start Address + F0SA: u16, + /// Rx FIFO 0 Size + F0S: u7, + reserved0: u1, + /// Rx FIFO 0 Watermark + F0WM: u7, + /// FIFO 0 Operation Mode + F0OM: u1, + }), base_address + 0xa0); + + /// address: 0x420000a4 + /// Rx FIFO 0 Status + pub const RXF0S = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 0 Fill Level + F0FL: u7, + reserved0: u1, + /// Rx FIFO 0 Get Index + F0GI: u6, + reserved1: u1, + reserved2: u1, + /// Rx FIFO 0 Put Index + F0PI: u6, + reserved3: u1, + reserved4: u1, + /// Rx FIFO 0 Full + F0F: u1, + /// Rx FIFO 0 Message Lost + RF0L: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xa4); + + /// address: 0x420000a8 + /// Rx FIFO 0 Acknowledge + pub const RXF0A = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 0 Acknowledge Index + F0AI: u6, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0xa8); + + /// address: 0x420000ac + /// Rx Buffer Configuration + pub const RXBC = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx Buffer Start Address + RBSA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xac); + + /// address: 0x420000b0 + /// Rx FIFO 1 Configuration + pub const RXF1C = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 1 Start Address + F1SA: u16, + /// Rx FIFO 1 Size + F1S: u7, + reserved0: u1, + /// Rx FIFO 1 Watermark + F1WM: u7, + /// FIFO 1 Operation Mode + F1OM: u1, + }), base_address + 0xb0); + + /// address: 0x420000b4 + /// Rx FIFO 1 Status + pub const RXF1S = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 1 Fill Level + F1FL: u7, + reserved0: u1, + /// Rx FIFO 1 Get Index + F1GI: u6, + reserved1: u1, + reserved2: u1, + /// Rx FIFO 1 Put Index + F1PI: u6, + reserved3: u1, + reserved4: u1, + /// Rx FIFO 1 Full + F1F: u1, + /// Rx FIFO 1 Message Lost + RF1L: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Debug Message Status + DMS: u2, + }), base_address + 0xb4); + + /// address: 0x420000b8 + /// Rx FIFO 1 Acknowledge + pub const RXF1A = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 1 Acknowledge Index + F1AI: u6, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0xb8); + + /// address: 0x420000bc + /// Rx Buffer / FIFO Element Size Configuration + pub const RXESC = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 0 Data Field Size + F0DS: u3, + reserved0: u1, + /// Rx FIFO 1 Data Field Size + F1DS: u3, + reserved1: u1, + /// Rx Buffer Data Field Size + RBDS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0xbc); + + /// address: 0x420000c0 + /// Tx Buffer Configuration + pub const TXBC = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx Buffers Start Address + TBSA: u16, + /// Number of Dedicated Transmit Buffers + NDTB: u6, + reserved0: u1, + reserved1: u1, + /// Transmit FIFO/Queue Size + TFQS: u6, + /// Tx FIFO/Queue Mode + TFQM: u1, + padding0: u1, + }), base_address + 0xc0); + + /// address: 0x420000c4 + /// Tx FIFO / Queue Status + pub const TXFQS = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx FIFO Free Level + TFFL: u6, + reserved0: u1, + reserved1: u1, + /// Tx FIFO Get Index + TFGI: u5, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Tx FIFO/Queue Put Index + TFQPI: u5, + /// Tx FIFO/Queue Full + TFQF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0xc4); + + /// address: 0x420000c8 + /// Tx Buffer Element Size Configuration + pub const TXESC = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx Buffer Data Field Size + TBDS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0xc8); + + /// address: 0x420000cc + /// Tx Buffer Request Pending + pub const TXBRP = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmission Request Pending 0 + TRP0: u1, + /// Transmission Request Pending 1 + TRP1: u1, + /// Transmission Request Pending 2 + TRP2: u1, + /// Transmission Request Pending 3 + TRP3: u1, + /// Transmission Request Pending 4 + TRP4: u1, + /// Transmission Request Pending 5 + TRP5: u1, + /// Transmission Request Pending 6 + TRP6: u1, + /// Transmission Request Pending 7 + TRP7: u1, + /// Transmission Request Pending 8 + TRP8: u1, + /// Transmission Request Pending 9 + TRP9: u1, + /// Transmission Request Pending 10 + TRP10: u1, + /// Transmission Request Pending 11 + TRP11: u1, + /// Transmission Request Pending 12 + TRP12: u1, + /// Transmission Request Pending 13 + TRP13: u1, + /// Transmission Request Pending 14 + TRP14: u1, + /// Transmission Request Pending 15 + TRP15: u1, + /// Transmission Request Pending 16 + TRP16: u1, + /// Transmission Request Pending 17 + TRP17: u1, + /// Transmission Request Pending 18 + TRP18: u1, + /// Transmission Request Pending 19 + TRP19: u1, + /// Transmission Request Pending 20 + TRP20: u1, + /// Transmission Request Pending 21 + TRP21: u1, + /// Transmission Request Pending 22 + TRP22: u1, + /// Transmission Request Pending 23 + TRP23: u1, + /// Transmission Request Pending 24 + TRP24: u1, + /// Transmission Request Pending 25 + TRP25: u1, + /// Transmission Request Pending 26 + TRP26: u1, + /// Transmission Request Pending 27 + TRP27: u1, + /// Transmission Request Pending 28 + TRP28: u1, + /// Transmission Request Pending 29 + TRP29: u1, + /// Transmission Request Pending 30 + TRP30: u1, + /// Transmission Request Pending 31 + TRP31: u1, + }), base_address + 0xcc); + + /// address: 0x420000d0 + /// Tx Buffer Add Request + pub const TXBAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Add Request 0 + AR0: u1, + /// Add Request 1 + AR1: u1, + /// Add Request 2 + AR2: u1, + /// Add Request 3 + AR3: u1, + /// Add Request 4 + AR4: u1, + /// Add Request 5 + AR5: u1, + /// Add Request 6 + AR6: u1, + /// Add Request 7 + AR7: u1, + /// Add Request 8 + AR8: u1, + /// Add Request 9 + AR9: u1, + /// Add Request 10 + AR10: u1, + /// Add Request 11 + AR11: u1, + /// Add Request 12 + AR12: u1, + /// Add Request 13 + AR13: u1, + /// Add Request 14 + AR14: u1, + /// Add Request 15 + AR15: u1, + /// Add Request 16 + AR16: u1, + /// Add Request 17 + AR17: u1, + /// Add Request 18 + AR18: u1, + /// Add Request 19 + AR19: u1, + /// Add Request 20 + AR20: u1, + /// Add Request 21 + AR21: u1, + /// Add Request 22 + AR22: u1, + /// Add Request 23 + AR23: u1, + /// Add Request 24 + AR24: u1, + /// Add Request 25 + AR25: u1, + /// Add Request 26 + AR26: u1, + /// Add Request 27 + AR27: u1, + /// Add Request 28 + AR28: u1, + /// Add Request 29 + AR29: u1, + /// Add Request 30 + AR30: u1, + /// Add Request 31 + AR31: u1, + }), base_address + 0xd0); + + /// address: 0x420000d4 + /// Tx Buffer Cancellation Request + pub const TXBCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Cancellation Request 0 + CR0: u1, + /// Cancellation Request 1 + CR1: u1, + /// Cancellation Request 2 + CR2: u1, + /// Cancellation Request 3 + CR3: u1, + /// Cancellation Request 4 + CR4: u1, + /// Cancellation Request 5 + CR5: u1, + /// Cancellation Request 6 + CR6: u1, + /// Cancellation Request 7 + CR7: u1, + /// Cancellation Request 8 + CR8: u1, + /// Cancellation Request 9 + CR9: u1, + /// Cancellation Request 10 + CR10: u1, + /// Cancellation Request 11 + CR11: u1, + /// Cancellation Request 12 + CR12: u1, + /// Cancellation Request 13 + CR13: u1, + /// Cancellation Request 14 + CR14: u1, + /// Cancellation Request 15 + CR15: u1, + /// Cancellation Request 16 + CR16: u1, + /// Cancellation Request 17 + CR17: u1, + /// Cancellation Request 18 + CR18: u1, + /// Cancellation Request 19 + CR19: u1, + /// Cancellation Request 20 + CR20: u1, + /// Cancellation Request 21 + CR21: u1, + /// Cancellation Request 22 + CR22: u1, + /// Cancellation Request 23 + CR23: u1, + /// Cancellation Request 24 + CR24: u1, + /// Cancellation Request 25 + CR25: u1, + /// Cancellation Request 26 + CR26: u1, + /// Cancellation Request 27 + CR27: u1, + /// Cancellation Request 28 + CR28: u1, + /// Cancellation Request 29 + CR29: u1, + /// Cancellation Request 30 + CR30: u1, + /// Cancellation Request 31 + CR31: u1, + }), base_address + 0xd4); + + /// address: 0x420000d8 + /// Tx Buffer Transmission Occurred + pub const TXBTO = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmission Occurred 0 + TO0: u1, + /// Transmission Occurred 1 + TO1: u1, + /// Transmission Occurred 2 + TO2: u1, + /// Transmission Occurred 3 + TO3: u1, + /// Transmission Occurred 4 + TO4: u1, + /// Transmission Occurred 5 + TO5: u1, + /// Transmission Occurred 6 + TO6: u1, + /// Transmission Occurred 7 + TO7: u1, + /// Transmission Occurred 8 + TO8: u1, + /// Transmission Occurred 9 + TO9: u1, + /// Transmission Occurred 10 + TO10: u1, + /// Transmission Occurred 11 + TO11: u1, + /// Transmission Occurred 12 + TO12: u1, + /// Transmission Occurred 13 + TO13: u1, + /// Transmission Occurred 14 + TO14: u1, + /// Transmission Occurred 15 + TO15: u1, + /// Transmission Occurred 16 + TO16: u1, + /// Transmission Occurred 17 + TO17: u1, + /// Transmission Occurred 18 + TO18: u1, + /// Transmission Occurred 19 + TO19: u1, + /// Transmission Occurred 20 + TO20: u1, + /// Transmission Occurred 21 + TO21: u1, + /// Transmission Occurred 22 + TO22: u1, + /// Transmission Occurred 23 + TO23: u1, + /// Transmission Occurred 24 + TO24: u1, + /// Transmission Occurred 25 + TO25: u1, + /// Transmission Occurred 26 + TO26: u1, + /// Transmission Occurred 27 + TO27: u1, + /// Transmission Occurred 28 + TO28: u1, + /// Transmission Occurred 29 + TO29: u1, + /// Transmission Occurred 30 + TO30: u1, + /// Transmission Occurred 31 + TO31: u1, + }), base_address + 0xd8); + + /// address: 0x420000dc + /// Tx Buffer Cancellation Finished + pub const TXBCF = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx Buffer Cancellation Finished 0 + CF0: u1, + /// Tx Buffer Cancellation Finished 1 + CF1: u1, + /// Tx Buffer Cancellation Finished 2 + CF2: u1, + /// Tx Buffer Cancellation Finished 3 + CF3: u1, + /// Tx Buffer Cancellation Finished 4 + CF4: u1, + /// Tx Buffer Cancellation Finished 5 + CF5: u1, + /// Tx Buffer Cancellation Finished 6 + CF6: u1, + /// Tx Buffer Cancellation Finished 7 + CF7: u1, + /// Tx Buffer Cancellation Finished 8 + CF8: u1, + /// Tx Buffer Cancellation Finished 9 + CF9: u1, + /// Tx Buffer Cancellation Finished 10 + CF10: u1, + /// Tx Buffer Cancellation Finished 11 + CF11: u1, + /// Tx Buffer Cancellation Finished 12 + CF12: u1, + /// Tx Buffer Cancellation Finished 13 + CF13: u1, + /// Tx Buffer Cancellation Finished 14 + CF14: u1, + /// Tx Buffer Cancellation Finished 15 + CF15: u1, + /// Tx Buffer Cancellation Finished 16 + CF16: u1, + /// Tx Buffer Cancellation Finished 17 + CF17: u1, + /// Tx Buffer Cancellation Finished 18 + CF18: u1, + /// Tx Buffer Cancellation Finished 19 + CF19: u1, + /// Tx Buffer Cancellation Finished 20 + CF20: u1, + /// Tx Buffer Cancellation Finished 21 + CF21: u1, + /// Tx Buffer Cancellation Finished 22 + CF22: u1, + /// Tx Buffer Cancellation Finished 23 + CF23: u1, + /// Tx Buffer Cancellation Finished 24 + CF24: u1, + /// Tx Buffer Cancellation Finished 25 + CF25: u1, + /// Tx Buffer Cancellation Finished 26 + CF26: u1, + /// Tx Buffer Cancellation Finished 27 + CF27: u1, + /// Tx Buffer Cancellation Finished 28 + CF28: u1, + /// Tx Buffer Cancellation Finished 29 + CF29: u1, + /// Tx Buffer Cancellation Finished 30 + CF30: u1, + /// Tx Buffer Cancellation Finished 31 + CF31: u1, + }), base_address + 0xdc); + + /// address: 0x420000e0 + /// Tx Buffer Transmission Interrupt Enable + pub const TXBTIE = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmission Interrupt Enable 0 + TIE0: u1, + /// Transmission Interrupt Enable 1 + TIE1: u1, + /// Transmission Interrupt Enable 2 + TIE2: u1, + /// Transmission Interrupt Enable 3 + TIE3: u1, + /// Transmission Interrupt Enable 4 + TIE4: u1, + /// Transmission Interrupt Enable 5 + TIE5: u1, + /// Transmission Interrupt Enable 6 + TIE6: u1, + /// Transmission Interrupt Enable 7 + TIE7: u1, + /// Transmission Interrupt Enable 8 + TIE8: u1, + /// Transmission Interrupt Enable 9 + TIE9: u1, + /// Transmission Interrupt Enable 10 + TIE10: u1, + /// Transmission Interrupt Enable 11 + TIE11: u1, + /// Transmission Interrupt Enable 12 + TIE12: u1, + /// Transmission Interrupt Enable 13 + TIE13: u1, + /// Transmission Interrupt Enable 14 + TIE14: u1, + /// Transmission Interrupt Enable 15 + TIE15: u1, + /// Transmission Interrupt Enable 16 + TIE16: u1, + /// Transmission Interrupt Enable 17 + TIE17: u1, + /// Transmission Interrupt Enable 18 + TIE18: u1, + /// Transmission Interrupt Enable 19 + TIE19: u1, + /// Transmission Interrupt Enable 20 + TIE20: u1, + /// Transmission Interrupt Enable 21 + TIE21: u1, + /// Transmission Interrupt Enable 22 + TIE22: u1, + /// Transmission Interrupt Enable 23 + TIE23: u1, + /// Transmission Interrupt Enable 24 + TIE24: u1, + /// Transmission Interrupt Enable 25 + TIE25: u1, + /// Transmission Interrupt Enable 26 + TIE26: u1, + /// Transmission Interrupt Enable 27 + TIE27: u1, + /// Transmission Interrupt Enable 28 + TIE28: u1, + /// Transmission Interrupt Enable 29 + TIE29: u1, + /// Transmission Interrupt Enable 30 + TIE30: u1, + /// Transmission Interrupt Enable 31 + TIE31: u1, + }), base_address + 0xe0); + + /// address: 0x420000e4 + /// Tx Buffer Cancellation Finished Interrupt Enable + pub const TXBCIE = @intToPtr(*volatile Mmio(32, packed struct { + /// Cancellation Finished Interrupt Enable 0 + CFIE0: u1, + /// Cancellation Finished Interrupt Enable 1 + CFIE1: u1, + /// Cancellation Finished Interrupt Enable 2 + CFIE2: u1, + /// Cancellation Finished Interrupt Enable 3 + CFIE3: u1, + /// Cancellation Finished Interrupt Enable 4 + CFIE4: u1, + /// Cancellation Finished Interrupt Enable 5 + CFIE5: u1, + /// Cancellation Finished Interrupt Enable 6 + CFIE6: u1, + /// Cancellation Finished Interrupt Enable 7 + CFIE7: u1, + /// Cancellation Finished Interrupt Enable 8 + CFIE8: u1, + /// Cancellation Finished Interrupt Enable 9 + CFIE9: u1, + /// Cancellation Finished Interrupt Enable 10 + CFIE10: u1, + /// Cancellation Finished Interrupt Enable 11 + CFIE11: u1, + /// Cancellation Finished Interrupt Enable 12 + CFIE12: u1, + /// Cancellation Finished Interrupt Enable 13 + CFIE13: u1, + /// Cancellation Finished Interrupt Enable 14 + CFIE14: u1, + /// Cancellation Finished Interrupt Enable 15 + CFIE15: u1, + /// Cancellation Finished Interrupt Enable 16 + CFIE16: u1, + /// Cancellation Finished Interrupt Enable 17 + CFIE17: u1, + /// Cancellation Finished Interrupt Enable 18 + CFIE18: u1, + /// Cancellation Finished Interrupt Enable 19 + CFIE19: u1, + /// Cancellation Finished Interrupt Enable 20 + CFIE20: u1, + /// Cancellation Finished Interrupt Enable 21 + CFIE21: u1, + /// Cancellation Finished Interrupt Enable 22 + CFIE22: u1, + /// Cancellation Finished Interrupt Enable 23 + CFIE23: u1, + /// Cancellation Finished Interrupt Enable 24 + CFIE24: u1, + /// Cancellation Finished Interrupt Enable 25 + CFIE25: u1, + /// Cancellation Finished Interrupt Enable 26 + CFIE26: u1, + /// Cancellation Finished Interrupt Enable 27 + CFIE27: u1, + /// Cancellation Finished Interrupt Enable 28 + CFIE28: u1, + /// Cancellation Finished Interrupt Enable 29 + CFIE29: u1, + /// Cancellation Finished Interrupt Enable 30 + CFIE30: u1, + /// Cancellation Finished Interrupt Enable 31 + CFIE31: u1, + }), base_address + 0xe4); + + /// address: 0x420000f0 + /// Tx Event FIFO Configuration + pub const TXEFC = @intToPtr(*volatile Mmio(32, packed struct { + /// Event FIFO Start Address + EFSA: u16, + /// Event FIFO Size + EFS: u6, + reserved0: u1, + reserved1: u1, + /// Event FIFO Watermark + EFWM: u6, + padding0: u1, + padding1: u1, + }), base_address + 0xf0); + + /// address: 0x420000f4 + /// Tx Event FIFO Status + pub const TXEFS = @intToPtr(*volatile Mmio(32, packed struct { + /// Event FIFO Fill Level + EFFL: u6, + reserved0: u1, + reserved1: u1, + /// Event FIFO Get Index + EFGI: u5, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Event FIFO Put Index + EFPI: u5, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Event FIFO Full + EFF: u1, + /// Tx Event FIFO Element Lost + TEFL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xf4); + + /// address: 0x420000f8 + /// Tx Event FIFO Acknowledge + pub const TXEFA = @intToPtr(*volatile Mmio(32, packed struct { + /// Event FIFO Acknowledge Index + EFAI: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0xf8); + }; + pub const CAN1 = struct { + pub const base_address = 0x42000400; + + /// address: 0x42000400 + /// Core Release + pub const CREL = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + /// Sub-step of Core Release + SUBSTEP: u4, + /// Step of Core Release + STEP: u4, + /// Core Release + REL: u4, + }), base_address + 0x0); + + /// address: 0x42000404 + /// Endian + pub const ENDN = @intToPtr(*volatile Mmio(32, packed struct { + /// Endianness Test Value + ETV: u32, + }), base_address + 0x4); + + /// address: 0x42000408 + /// Message RAM Configuration + pub const MRCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Quality of Service + QOS: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x8); + + /// address: 0x4200040c + /// Fast Bit Timing and Prescaler + pub const DBTP = @intToPtr(*volatile Mmio(32, packed struct { + /// Data (Re)Synchronization Jump Width + DSJW: u4, + /// Data time segment after sample point + DTSEG2: u4, + /// Data time segment before sample point + DTSEG1: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Data Baud Rate Prescaler + DBRP: u5, + reserved3: u1, + reserved4: u1, + /// Tranceiver Delay Compensation + TDC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0xc); + + /// address: 0x42000410 + /// Test + pub const TEST = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Loop Back Mode + LBCK: u1, + /// Control of Transmit Pin + TX: u2, + /// Receive Pin + RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x10); + + /// address: 0x42000414 + /// RAM Watchdog + pub const RWD = @intToPtr(*volatile Mmio(32, packed struct { + /// Watchdog Configuration + WDC: u8, + /// Watchdog Value + WDV: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x42000418 + /// CC Control + pub const CCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Initialization + INIT: u1, + /// Configuration Change Enable + CCE: u1, + /// ASM Restricted Operation Mode + ASM: u1, + /// Clock Stop Acknowledge + CSA: u1, + /// Clock Stop Request + CSR: u1, + /// Bus Monitoring Mode + MON: u1, + /// Disable Automatic Retransmission + DAR: u1, + /// Test Mode Enable + TEST: u1, + /// FD Operation Enable + FDOE: u1, + /// Bit Rate Switch Enable + BRSE: u1, + reserved0: u1, + reserved1: u1, + /// Protocol Exception Handling Disable + PXHD: u1, + /// Edge Filtering during Bus Integration + EFBI: u1, + /// Transmit Pause + TXP: u1, + /// Non ISO Operation + NISO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4200041c + /// Nominal Bit Timing and Prescaler + pub const NBTP = @intToPtr(*volatile Mmio(32, packed struct { + /// Nominal Time segment after sample point + NTSEG2: u7, + reserved0: u1, + /// Nominal Time segment before sample point + NTSEG1: u8, + /// Nominal Baud Rate Prescaler + NBRP: u9, + /// Nominal (Re)Synchronization Jump Width + NSJW: u7, + }), base_address + 0x1c); + + /// address: 0x42000420 + /// Timestamp Counter Configuration + pub const TSCC = @intToPtr(*volatile Mmio(32, packed struct { + /// Timestamp Select + TSS: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Timestamp Counter Prescaler + TCP: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x20); + + /// address: 0x42000424 + /// Timestamp Counter Value + pub const TSCV = @intToPtr(*volatile Mmio(32, packed struct { + /// Timestamp Counter + TSC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x24); + + /// address: 0x42000428 + /// Timeout Counter Configuration + pub const TOCC = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable Timeout Counter + ETOC: u1, + /// Timeout Select + TOS: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Timeout Period + TOP: u16, + }), base_address + 0x28); + + /// address: 0x4200042c + /// Timeout Counter Value + pub const TOCV = @intToPtr(*volatile Mmio(32, packed struct { + /// Timeout Counter + TOC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x2c); + + /// address: 0x42000440 + /// Error Counter + pub const ECR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit Error Counter + TEC: u8, + /// Receive Error Counter + REC: u7, + /// Receive Error Passive + RP: u1, + /// CAN Error Logging + CEL: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x42000444 + /// Protocol Status + pub const PSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Last Error Code + LEC: u3, + /// Activity + ACT: u2, + /// Error Passive + EP: u1, + /// Warning Status + EW: u1, + /// Bus_Off Status + BO: u1, + /// Data Phase Last Error Code + DLEC: u3, + /// ESI flag of last received CAN FD Message + RESI: u1, + /// BRS flag of last received CAN FD Message + RBRS: u1, + /// Received a CAN FD Message + RFDF: u1, + /// Protocol Exception Event + PXE: u1, + reserved0: u1, + /// Transmitter Delay Compensation Value + TDCV: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x44); + + /// address: 0x42000448 + /// Extended ID Filter Configuration + pub const TDCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmitter Delay Compensation Filter Length + TDCF: u7, + reserved0: u1, + /// Transmitter Delay Compensation Offset + TDCO: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x48); + + /// address: 0x42000450 + /// Interrupt + pub const IR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 0 New Message + RF0N: u1, + /// Rx FIFO 0 Watermark Reached + RF0W: u1, + /// Rx FIFO 0 Full + RF0F: u1, + /// Rx FIFO 0 Message Lost + RF0L: u1, + /// Rx FIFO 1 New Message + RF1N: u1, + /// Rx FIFO 1 Watermark Reached + RF1W: u1, + /// Rx FIFO 1 FIFO Full + RF1F: u1, + /// Rx FIFO 1 Message Lost + RF1L: u1, + /// High Priority Message + HPM: u1, + /// Timestamp Completed + TC: u1, + /// Transmission Cancellation Finished + TCF: u1, + /// Tx FIFO Empty + TFE: u1, + /// Tx Event FIFO New Entry + TEFN: u1, + /// Tx Event FIFO Watermark Reached + TEFW: u1, + /// Tx Event FIFO Full + TEFF: u1, + /// Tx Event FIFO Element Lost + TEFL: u1, + /// Timestamp Wraparound + TSW: u1, + /// Message RAM Access Failure + MRAF: u1, + /// Timeout Occurred + TOO: u1, + /// Message stored to Dedicated Rx Buffer + DRX: u1, + /// Bit Error Corrected + BEC: u1, + /// Bit Error Uncorrected + BEU: u1, + /// Error Logging Overflow + ELO: u1, + /// Error Passive + EP: u1, + /// Warning Status + EW: u1, + /// Bus_Off Status + BO: u1, + /// Watchdog Interrupt + WDI: u1, + /// Protocol Error in Arbitration Phase + PEA: u1, + /// Protocol Error in Data Phase + PED: u1, + /// Access to Reserved Address + ARA: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x50); + + /// address: 0x42000454 + /// Interrupt Enable + pub const IE = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 0 New Message Interrupt Enable + RF0NE: u1, + /// Rx FIFO 0 Watermark Reached Interrupt Enable + RF0WE: u1, + /// Rx FIFO 0 Full Interrupt Enable + RF0FE: u1, + /// Rx FIFO 0 Message Lost Interrupt Enable + RF0LE: u1, + /// Rx FIFO 1 New Message Interrupt Enable + RF1NE: u1, + /// Rx FIFO 1 Watermark Reached Interrupt Enable + RF1WE: u1, + /// Rx FIFO 1 FIFO Full Interrupt Enable + RF1FE: u1, + /// Rx FIFO 1 Message Lost Interrupt Enable + RF1LE: u1, + /// High Priority Message Interrupt Enable + HPME: u1, + /// Timestamp Completed Interrupt Enable + TCE: u1, + /// Transmission Cancellation Finished Interrupt Enable + TCFE: u1, + /// Tx FIFO Empty Interrupt Enable + TFEE: u1, + /// Tx Event FIFO New Entry Interrupt Enable + TEFNE: u1, + /// Tx Event FIFO Watermark Reached Interrupt Enable + TEFWE: u1, + /// Tx Event FIFO Full Interrupt Enable + TEFFE: u1, + /// Tx Event FIFO Element Lost Interrupt Enable + TEFLE: u1, + /// Timestamp Wraparound Interrupt Enable + TSWE: u1, + /// Message RAM Access Failure Interrupt Enable + MRAFE: u1, + /// Timeout Occurred Interrupt Enable + TOOE: u1, + /// Message stored to Dedicated Rx Buffer Interrupt Enable + DRXE: u1, + /// Bit Error Corrected Interrupt Enable + BECE: u1, + /// Bit Error Uncorrected Interrupt Enable + BEUE: u1, + /// Error Logging Overflow Interrupt Enable + ELOE: u1, + /// Error Passive Interrupt Enable + EPE: u1, + /// Warning Status Interrupt Enable + EWE: u1, + /// Bus_Off Status Interrupt Enable + BOE: u1, + /// Watchdog Interrupt Interrupt Enable + WDIE: u1, + /// Protocol Error in Arbitration Phase Enable + PEAE: u1, + /// Protocol Error in Data Phase Enable + PEDE: u1, + /// Access to Reserved Address Enable + ARAE: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x54); + + /// address: 0x42000458 + /// Interrupt Line Select + pub const ILS = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 0 New Message Interrupt Line + RF0NL: u1, + /// Rx FIFO 0 Watermark Reached Interrupt Line + RF0WL: u1, + /// Rx FIFO 0 Full Interrupt Line + RF0FL: u1, + /// Rx FIFO 0 Message Lost Interrupt Line + RF0LL: u1, + /// Rx FIFO 1 New Message Interrupt Line + RF1NL: u1, + /// Rx FIFO 1 Watermark Reached Interrupt Line + RF1WL: u1, + /// Rx FIFO 1 FIFO Full Interrupt Line + RF1FL: u1, + /// Rx FIFO 1 Message Lost Interrupt Line + RF1LL: u1, + /// High Priority Message Interrupt Line + HPML: u1, + /// Timestamp Completed Interrupt Line + TCL: u1, + /// Transmission Cancellation Finished Interrupt Line + TCFL: u1, + /// Tx FIFO Empty Interrupt Line + TFEL: u1, + /// Tx Event FIFO New Entry Interrupt Line + TEFNL: u1, + /// Tx Event FIFO Watermark Reached Interrupt Line + TEFWL: u1, + /// Tx Event FIFO Full Interrupt Line + TEFFL: u1, + /// Tx Event FIFO Element Lost Interrupt Line + TEFLL: u1, + /// Timestamp Wraparound Interrupt Line + TSWL: u1, + /// Message RAM Access Failure Interrupt Line + MRAFL: u1, + /// Timeout Occurred Interrupt Line + TOOL: u1, + /// Message stored to Dedicated Rx Buffer Interrupt Line + DRXL: u1, + /// Bit Error Corrected Interrupt Line + BECL: u1, + /// Bit Error Uncorrected Interrupt Line + BEUL: u1, + /// Error Logging Overflow Interrupt Line + ELOL: u1, + /// Error Passive Interrupt Line + EPL: u1, + /// Warning Status Interrupt Line + EWL: u1, + /// Bus_Off Status Interrupt Line + BOL: u1, + /// Watchdog Interrupt Interrupt Line + WDIL: u1, + /// Protocol Error in Arbitration Phase Line + PEAL: u1, + /// Protocol Error in Data Phase Line + PEDL: u1, + /// Access to Reserved Address Line + ARAL: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x58); + + /// address: 0x4200045c + /// Interrupt Line Enable + pub const ILE = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable Interrupt Line 0 + EINT0: u1, + /// Enable Interrupt Line 1 + EINT1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x5c); + + /// address: 0x42000480 + /// Global Filter Configuration + pub const GFC = @intToPtr(*volatile Mmio(32, packed struct { + /// Reject Remote Frames Extended + RRFE: u1, + /// Reject Remote Frames Standard + RRFS: u1, + /// Accept Non-matching Frames Extended + ANFE: u2, + /// Accept Non-matching Frames Standard + ANFS: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x80); + + /// address: 0x42000484 + /// Standard ID Filter Configuration + pub const SIDFC = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter List Standard Start Address + FLSSA: u16, + /// List Size Standard + LSS: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x84); + + /// address: 0x42000488 + /// Extended ID Filter Configuration + pub const XIDFC = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter List Extended Start Address + FLESA: u16, + /// List Size Extended + LSE: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x88); + + /// address: 0x42000490 + /// Extended ID AND Mask + pub const XIDAM = @intToPtr(*volatile Mmio(32, packed struct { + /// Extended ID Mask + EIDM: u29, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x90); + + /// address: 0x42000494 + /// High Priority Message Status + pub const HPMS = @intToPtr(*volatile Mmio(32, packed struct { + /// Buffer Index + BIDX: u6, + /// Message Storage Indicator + MSI: u2, + /// Filter Index + FIDX: u7, + /// Filter List + FLST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x94); + + /// address: 0x42000498 + /// New Data 1 + pub const NDAT1 = @intToPtr(*volatile Mmio(32, packed struct { + /// New Data 0 + ND0: u1, + /// New Data 1 + ND1: u1, + /// New Data 2 + ND2: u1, + /// New Data 3 + ND3: u1, + /// New Data 4 + ND4: u1, + /// New Data 5 + ND5: u1, + /// New Data 6 + ND6: u1, + /// New Data 7 + ND7: u1, + /// New Data 8 + ND8: u1, + /// New Data 9 + ND9: u1, + /// New Data 10 + ND10: u1, + /// New Data 11 + ND11: u1, + /// New Data 12 + ND12: u1, + /// New Data 13 + ND13: u1, + /// New Data 14 + ND14: u1, + /// New Data 15 + ND15: u1, + /// New Data 16 + ND16: u1, + /// New Data 17 + ND17: u1, + /// New Data 18 + ND18: u1, + /// New Data 19 + ND19: u1, + /// New Data 20 + ND20: u1, + /// New Data 21 + ND21: u1, + /// New Data 22 + ND22: u1, + /// New Data 23 + ND23: u1, + /// New Data 24 + ND24: u1, + /// New Data 25 + ND25: u1, + /// New Data 26 + ND26: u1, + /// New Data 27 + ND27: u1, + /// New Data 28 + ND28: u1, + /// New Data 29 + ND29: u1, + /// New Data 30 + ND30: u1, + /// New Data 31 + ND31: u1, + }), base_address + 0x98); + + /// address: 0x4200049c + /// New Data 2 + pub const NDAT2 = @intToPtr(*volatile Mmio(32, packed struct { + /// New Data 32 + ND32: u1, + /// New Data 33 + ND33: u1, + /// New Data 34 + ND34: u1, + /// New Data 35 + ND35: u1, + /// New Data 36 + ND36: u1, + /// New Data 37 + ND37: u1, + /// New Data 38 + ND38: u1, + /// New Data 39 + ND39: u1, + /// New Data 40 + ND40: u1, + /// New Data 41 + ND41: u1, + /// New Data 42 + ND42: u1, + /// New Data 43 + ND43: u1, + /// New Data 44 + ND44: u1, + /// New Data 45 + ND45: u1, + /// New Data 46 + ND46: u1, + /// New Data 47 + ND47: u1, + /// New Data 48 + ND48: u1, + /// New Data 49 + ND49: u1, + /// New Data 50 + ND50: u1, + /// New Data 51 + ND51: u1, + /// New Data 52 + ND52: u1, + /// New Data 53 + ND53: u1, + /// New Data 54 + ND54: u1, + /// New Data 55 + ND55: u1, + /// New Data 56 + ND56: u1, + /// New Data 57 + ND57: u1, + /// New Data 58 + ND58: u1, + /// New Data 59 + ND59: u1, + /// New Data 60 + ND60: u1, + /// New Data 61 + ND61: u1, + /// New Data 62 + ND62: u1, + /// New Data 63 + ND63: u1, + }), base_address + 0x9c); + + /// address: 0x420004a0 + /// Rx FIFO 0 Configuration + pub const RXF0C = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 0 Start Address + F0SA: u16, + /// Rx FIFO 0 Size + F0S: u7, + reserved0: u1, + /// Rx FIFO 0 Watermark + F0WM: u7, + /// FIFO 0 Operation Mode + F0OM: u1, + }), base_address + 0xa0); + + /// address: 0x420004a4 + /// Rx FIFO 0 Status + pub const RXF0S = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 0 Fill Level + F0FL: u7, + reserved0: u1, + /// Rx FIFO 0 Get Index + F0GI: u6, + reserved1: u1, + reserved2: u1, + /// Rx FIFO 0 Put Index + F0PI: u6, + reserved3: u1, + reserved4: u1, + /// Rx FIFO 0 Full + F0F: u1, + /// Rx FIFO 0 Message Lost + RF0L: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xa4); + + /// address: 0x420004a8 + /// Rx FIFO 0 Acknowledge + pub const RXF0A = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 0 Acknowledge Index + F0AI: u6, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0xa8); + + /// address: 0x420004ac + /// Rx Buffer Configuration + pub const RXBC = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx Buffer Start Address + RBSA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xac); + + /// address: 0x420004b0 + /// Rx FIFO 1 Configuration + pub const RXF1C = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 1 Start Address + F1SA: u16, + /// Rx FIFO 1 Size + F1S: u7, + reserved0: u1, + /// Rx FIFO 1 Watermark + F1WM: u7, + /// FIFO 1 Operation Mode + F1OM: u1, + }), base_address + 0xb0); + + /// address: 0x420004b4 + /// Rx FIFO 1 Status + pub const RXF1S = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 1 Fill Level + F1FL: u7, + reserved0: u1, + /// Rx FIFO 1 Get Index + F1GI: u6, + reserved1: u1, + reserved2: u1, + /// Rx FIFO 1 Put Index + F1PI: u6, + reserved3: u1, + reserved4: u1, + /// Rx FIFO 1 Full + F1F: u1, + /// Rx FIFO 1 Message Lost + RF1L: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Debug Message Status + DMS: u2, + }), base_address + 0xb4); + + /// address: 0x420004b8 + /// Rx FIFO 1 Acknowledge + pub const RXF1A = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 1 Acknowledge Index + F1AI: u6, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0xb8); + + /// address: 0x420004bc + /// Rx Buffer / FIFO Element Size Configuration + pub const RXESC = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 0 Data Field Size + F0DS: u3, + reserved0: u1, + /// Rx FIFO 1 Data Field Size + F1DS: u3, + reserved1: u1, + /// Rx Buffer Data Field Size + RBDS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0xbc); + + /// address: 0x420004c0 + /// Tx Buffer Configuration + pub const TXBC = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx Buffers Start Address + TBSA: u16, + /// Number of Dedicated Transmit Buffers + NDTB: u6, + reserved0: u1, + reserved1: u1, + /// Transmit FIFO/Queue Size + TFQS: u6, + /// Tx FIFO/Queue Mode + TFQM: u1, + padding0: u1, + }), base_address + 0xc0); + + /// address: 0x420004c4 + /// Tx FIFO / Queue Status + pub const TXFQS = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx FIFO Free Level + TFFL: u6, + reserved0: u1, + reserved1: u1, + /// Tx FIFO Get Index + TFGI: u5, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Tx FIFO/Queue Put Index + TFQPI: u5, + /// Tx FIFO/Queue Full + TFQF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0xc4); + + /// address: 0x420004c8 + /// Tx Buffer Element Size Configuration + pub const TXESC = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx Buffer Data Field Size + TBDS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0xc8); + + /// address: 0x420004cc + /// Tx Buffer Request Pending + pub const TXBRP = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmission Request Pending 0 + TRP0: u1, + /// Transmission Request Pending 1 + TRP1: u1, + /// Transmission Request Pending 2 + TRP2: u1, + /// Transmission Request Pending 3 + TRP3: u1, + /// Transmission Request Pending 4 + TRP4: u1, + /// Transmission Request Pending 5 + TRP5: u1, + /// Transmission Request Pending 6 + TRP6: u1, + /// Transmission Request Pending 7 + TRP7: u1, + /// Transmission Request Pending 8 + TRP8: u1, + /// Transmission Request Pending 9 + TRP9: u1, + /// Transmission Request Pending 10 + TRP10: u1, + /// Transmission Request Pending 11 + TRP11: u1, + /// Transmission Request Pending 12 + TRP12: u1, + /// Transmission Request Pending 13 + TRP13: u1, + /// Transmission Request Pending 14 + TRP14: u1, + /// Transmission Request Pending 15 + TRP15: u1, + /// Transmission Request Pending 16 + TRP16: u1, + /// Transmission Request Pending 17 + TRP17: u1, + /// Transmission Request Pending 18 + TRP18: u1, + /// Transmission Request Pending 19 + TRP19: u1, + /// Transmission Request Pending 20 + TRP20: u1, + /// Transmission Request Pending 21 + TRP21: u1, + /// Transmission Request Pending 22 + TRP22: u1, + /// Transmission Request Pending 23 + TRP23: u1, + /// Transmission Request Pending 24 + TRP24: u1, + /// Transmission Request Pending 25 + TRP25: u1, + /// Transmission Request Pending 26 + TRP26: u1, + /// Transmission Request Pending 27 + TRP27: u1, + /// Transmission Request Pending 28 + TRP28: u1, + /// Transmission Request Pending 29 + TRP29: u1, + /// Transmission Request Pending 30 + TRP30: u1, + /// Transmission Request Pending 31 + TRP31: u1, + }), base_address + 0xcc); + + /// address: 0x420004d0 + /// Tx Buffer Add Request + pub const TXBAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Add Request 0 + AR0: u1, + /// Add Request 1 + AR1: u1, + /// Add Request 2 + AR2: u1, + /// Add Request 3 + AR3: u1, + /// Add Request 4 + AR4: u1, + /// Add Request 5 + AR5: u1, + /// Add Request 6 + AR6: u1, + /// Add Request 7 + AR7: u1, + /// Add Request 8 + AR8: u1, + /// Add Request 9 + AR9: u1, + /// Add Request 10 + AR10: u1, + /// Add Request 11 + AR11: u1, + /// Add Request 12 + AR12: u1, + /// Add Request 13 + AR13: u1, + /// Add Request 14 + AR14: u1, + /// Add Request 15 + AR15: u1, + /// Add Request 16 + AR16: u1, + /// Add Request 17 + AR17: u1, + /// Add Request 18 + AR18: u1, + /// Add Request 19 + AR19: u1, + /// Add Request 20 + AR20: u1, + /// Add Request 21 + AR21: u1, + /// Add Request 22 + AR22: u1, + /// Add Request 23 + AR23: u1, + /// Add Request 24 + AR24: u1, + /// Add Request 25 + AR25: u1, + /// Add Request 26 + AR26: u1, + /// Add Request 27 + AR27: u1, + /// Add Request 28 + AR28: u1, + /// Add Request 29 + AR29: u1, + /// Add Request 30 + AR30: u1, + /// Add Request 31 + AR31: u1, + }), base_address + 0xd0); + + /// address: 0x420004d4 + /// Tx Buffer Cancellation Request + pub const TXBCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Cancellation Request 0 + CR0: u1, + /// Cancellation Request 1 + CR1: u1, + /// Cancellation Request 2 + CR2: u1, + /// Cancellation Request 3 + CR3: u1, + /// Cancellation Request 4 + CR4: u1, + /// Cancellation Request 5 + CR5: u1, + /// Cancellation Request 6 + CR6: u1, + /// Cancellation Request 7 + CR7: u1, + /// Cancellation Request 8 + CR8: u1, + /// Cancellation Request 9 + CR9: u1, + /// Cancellation Request 10 + CR10: u1, + /// Cancellation Request 11 + CR11: u1, + /// Cancellation Request 12 + CR12: u1, + /// Cancellation Request 13 + CR13: u1, + /// Cancellation Request 14 + CR14: u1, + /// Cancellation Request 15 + CR15: u1, + /// Cancellation Request 16 + CR16: u1, + /// Cancellation Request 17 + CR17: u1, + /// Cancellation Request 18 + CR18: u1, + /// Cancellation Request 19 + CR19: u1, + /// Cancellation Request 20 + CR20: u1, + /// Cancellation Request 21 + CR21: u1, + /// Cancellation Request 22 + CR22: u1, + /// Cancellation Request 23 + CR23: u1, + /// Cancellation Request 24 + CR24: u1, + /// Cancellation Request 25 + CR25: u1, + /// Cancellation Request 26 + CR26: u1, + /// Cancellation Request 27 + CR27: u1, + /// Cancellation Request 28 + CR28: u1, + /// Cancellation Request 29 + CR29: u1, + /// Cancellation Request 30 + CR30: u1, + /// Cancellation Request 31 + CR31: u1, + }), base_address + 0xd4); + + /// address: 0x420004d8 + /// Tx Buffer Transmission Occurred + pub const TXBTO = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmission Occurred 0 + TO0: u1, + /// Transmission Occurred 1 + TO1: u1, + /// Transmission Occurred 2 + TO2: u1, + /// Transmission Occurred 3 + TO3: u1, + /// Transmission Occurred 4 + TO4: u1, + /// Transmission Occurred 5 + TO5: u1, + /// Transmission Occurred 6 + TO6: u1, + /// Transmission Occurred 7 + TO7: u1, + /// Transmission Occurred 8 + TO8: u1, + /// Transmission Occurred 9 + TO9: u1, + /// Transmission Occurred 10 + TO10: u1, + /// Transmission Occurred 11 + TO11: u1, + /// Transmission Occurred 12 + TO12: u1, + /// Transmission Occurred 13 + TO13: u1, + /// Transmission Occurred 14 + TO14: u1, + /// Transmission Occurred 15 + TO15: u1, + /// Transmission Occurred 16 + TO16: u1, + /// Transmission Occurred 17 + TO17: u1, + /// Transmission Occurred 18 + TO18: u1, + /// Transmission Occurred 19 + TO19: u1, + /// Transmission Occurred 20 + TO20: u1, + /// Transmission Occurred 21 + TO21: u1, + /// Transmission Occurred 22 + TO22: u1, + /// Transmission Occurred 23 + TO23: u1, + /// Transmission Occurred 24 + TO24: u1, + /// Transmission Occurred 25 + TO25: u1, + /// Transmission Occurred 26 + TO26: u1, + /// Transmission Occurred 27 + TO27: u1, + /// Transmission Occurred 28 + TO28: u1, + /// Transmission Occurred 29 + TO29: u1, + /// Transmission Occurred 30 + TO30: u1, + /// Transmission Occurred 31 + TO31: u1, + }), base_address + 0xd8); + + /// address: 0x420004dc + /// Tx Buffer Cancellation Finished + pub const TXBCF = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx Buffer Cancellation Finished 0 + CF0: u1, + /// Tx Buffer Cancellation Finished 1 + CF1: u1, + /// Tx Buffer Cancellation Finished 2 + CF2: u1, + /// Tx Buffer Cancellation Finished 3 + CF3: u1, + /// Tx Buffer Cancellation Finished 4 + CF4: u1, + /// Tx Buffer Cancellation Finished 5 + CF5: u1, + /// Tx Buffer Cancellation Finished 6 + CF6: u1, + /// Tx Buffer Cancellation Finished 7 + CF7: u1, + /// Tx Buffer Cancellation Finished 8 + CF8: u1, + /// Tx Buffer Cancellation Finished 9 + CF9: u1, + /// Tx Buffer Cancellation Finished 10 + CF10: u1, + /// Tx Buffer Cancellation Finished 11 + CF11: u1, + /// Tx Buffer Cancellation Finished 12 + CF12: u1, + /// Tx Buffer Cancellation Finished 13 + CF13: u1, + /// Tx Buffer Cancellation Finished 14 + CF14: u1, + /// Tx Buffer Cancellation Finished 15 + CF15: u1, + /// Tx Buffer Cancellation Finished 16 + CF16: u1, + /// Tx Buffer Cancellation Finished 17 + CF17: u1, + /// Tx Buffer Cancellation Finished 18 + CF18: u1, + /// Tx Buffer Cancellation Finished 19 + CF19: u1, + /// Tx Buffer Cancellation Finished 20 + CF20: u1, + /// Tx Buffer Cancellation Finished 21 + CF21: u1, + /// Tx Buffer Cancellation Finished 22 + CF22: u1, + /// Tx Buffer Cancellation Finished 23 + CF23: u1, + /// Tx Buffer Cancellation Finished 24 + CF24: u1, + /// Tx Buffer Cancellation Finished 25 + CF25: u1, + /// Tx Buffer Cancellation Finished 26 + CF26: u1, + /// Tx Buffer Cancellation Finished 27 + CF27: u1, + /// Tx Buffer Cancellation Finished 28 + CF28: u1, + /// Tx Buffer Cancellation Finished 29 + CF29: u1, + /// Tx Buffer Cancellation Finished 30 + CF30: u1, + /// Tx Buffer Cancellation Finished 31 + CF31: u1, + }), base_address + 0xdc); + + /// address: 0x420004e0 + /// Tx Buffer Transmission Interrupt Enable + pub const TXBTIE = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmission Interrupt Enable 0 + TIE0: u1, + /// Transmission Interrupt Enable 1 + TIE1: u1, + /// Transmission Interrupt Enable 2 + TIE2: u1, + /// Transmission Interrupt Enable 3 + TIE3: u1, + /// Transmission Interrupt Enable 4 + TIE4: u1, + /// Transmission Interrupt Enable 5 + TIE5: u1, + /// Transmission Interrupt Enable 6 + TIE6: u1, + /// Transmission Interrupt Enable 7 + TIE7: u1, + /// Transmission Interrupt Enable 8 + TIE8: u1, + /// Transmission Interrupt Enable 9 + TIE9: u1, + /// Transmission Interrupt Enable 10 + TIE10: u1, + /// Transmission Interrupt Enable 11 + TIE11: u1, + /// Transmission Interrupt Enable 12 + TIE12: u1, + /// Transmission Interrupt Enable 13 + TIE13: u1, + /// Transmission Interrupt Enable 14 + TIE14: u1, + /// Transmission Interrupt Enable 15 + TIE15: u1, + /// Transmission Interrupt Enable 16 + TIE16: u1, + /// Transmission Interrupt Enable 17 + TIE17: u1, + /// Transmission Interrupt Enable 18 + TIE18: u1, + /// Transmission Interrupt Enable 19 + TIE19: u1, + /// Transmission Interrupt Enable 20 + TIE20: u1, + /// Transmission Interrupt Enable 21 + TIE21: u1, + /// Transmission Interrupt Enable 22 + TIE22: u1, + /// Transmission Interrupt Enable 23 + TIE23: u1, + /// Transmission Interrupt Enable 24 + TIE24: u1, + /// Transmission Interrupt Enable 25 + TIE25: u1, + /// Transmission Interrupt Enable 26 + TIE26: u1, + /// Transmission Interrupt Enable 27 + TIE27: u1, + /// Transmission Interrupt Enable 28 + TIE28: u1, + /// Transmission Interrupt Enable 29 + TIE29: u1, + /// Transmission Interrupt Enable 30 + TIE30: u1, + /// Transmission Interrupt Enable 31 + TIE31: u1, + }), base_address + 0xe0); + + /// address: 0x420004e4 + /// Tx Buffer Cancellation Finished Interrupt Enable + pub const TXBCIE = @intToPtr(*volatile Mmio(32, packed struct { + /// Cancellation Finished Interrupt Enable 0 + CFIE0: u1, + /// Cancellation Finished Interrupt Enable 1 + CFIE1: u1, + /// Cancellation Finished Interrupt Enable 2 + CFIE2: u1, + /// Cancellation Finished Interrupt Enable 3 + CFIE3: u1, + /// Cancellation Finished Interrupt Enable 4 + CFIE4: u1, + /// Cancellation Finished Interrupt Enable 5 + CFIE5: u1, + /// Cancellation Finished Interrupt Enable 6 + CFIE6: u1, + /// Cancellation Finished Interrupt Enable 7 + CFIE7: u1, + /// Cancellation Finished Interrupt Enable 8 + CFIE8: u1, + /// Cancellation Finished Interrupt Enable 9 + CFIE9: u1, + /// Cancellation Finished Interrupt Enable 10 + CFIE10: u1, + /// Cancellation Finished Interrupt Enable 11 + CFIE11: u1, + /// Cancellation Finished Interrupt Enable 12 + CFIE12: u1, + /// Cancellation Finished Interrupt Enable 13 + CFIE13: u1, + /// Cancellation Finished Interrupt Enable 14 + CFIE14: u1, + /// Cancellation Finished Interrupt Enable 15 + CFIE15: u1, + /// Cancellation Finished Interrupt Enable 16 + CFIE16: u1, + /// Cancellation Finished Interrupt Enable 17 + CFIE17: u1, + /// Cancellation Finished Interrupt Enable 18 + CFIE18: u1, + /// Cancellation Finished Interrupt Enable 19 + CFIE19: u1, + /// Cancellation Finished Interrupt Enable 20 + CFIE20: u1, + /// Cancellation Finished Interrupt Enable 21 + CFIE21: u1, + /// Cancellation Finished Interrupt Enable 22 + CFIE22: u1, + /// Cancellation Finished Interrupt Enable 23 + CFIE23: u1, + /// Cancellation Finished Interrupt Enable 24 + CFIE24: u1, + /// Cancellation Finished Interrupt Enable 25 + CFIE25: u1, + /// Cancellation Finished Interrupt Enable 26 + CFIE26: u1, + /// Cancellation Finished Interrupt Enable 27 + CFIE27: u1, + /// Cancellation Finished Interrupt Enable 28 + CFIE28: u1, + /// Cancellation Finished Interrupt Enable 29 + CFIE29: u1, + /// Cancellation Finished Interrupt Enable 30 + CFIE30: u1, + /// Cancellation Finished Interrupt Enable 31 + CFIE31: u1, + }), base_address + 0xe4); + + /// address: 0x420004f0 + /// Tx Event FIFO Configuration + pub const TXEFC = @intToPtr(*volatile Mmio(32, packed struct { + /// Event FIFO Start Address + EFSA: u16, + /// Event FIFO Size + EFS: u6, + reserved0: u1, + reserved1: u1, + /// Event FIFO Watermark + EFWM: u6, + padding0: u1, + padding1: u1, + }), base_address + 0xf0); + + /// address: 0x420004f4 + /// Tx Event FIFO Status + pub const TXEFS = @intToPtr(*volatile Mmio(32, packed struct { + /// Event FIFO Fill Level + EFFL: u6, + reserved0: u1, + reserved1: u1, + /// Event FIFO Get Index + EFGI: u5, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Event FIFO Put Index + EFPI: u5, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Event FIFO Full + EFF: u1, + /// Tx Event FIFO Element Lost + TEFL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xf4); + + /// address: 0x420004f8 + /// Tx Event FIFO Acknowledge + pub const TXEFA = @intToPtr(*volatile Mmio(32, packed struct { + /// Event FIFO Acknowledge Index + EFAI: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0xf8); + }; + + /// Configurable Custom Logic + pub const CCL = struct { + pub const base_address = 0x42003800; + pub const version = "U22251.1.0"; + + /// address: 0x42003800 + /// Control + pub const CTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Run in Standby + RUNSTDBY: u1, + padding0: u1, + }), base_address + 0x0); + + /// address: 0x42003804 + /// SEQ Control x + pub const SEQCTRL = @intToPtr(*volatile [2]Mmio(8, packed struct { + /// Sequential Selection + SEQSEL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x4); + + /// address: 0x42003808 + /// LUT Control x + pub const LUTCTRL = @intToPtr(*volatile [4]Mmio(32, packed struct { + reserved0: u1, + /// LUT Enable + ENABLE: u1, + reserved1: u1, + reserved2: u1, + /// Filter Selection + FILTSEL: u2, + reserved3: u1, + /// Edge Selection + EDGESEL: u1, + /// Input Selection 0 + INSEL0: u4, + /// Input Selection 1 + INSEL1: u4, + /// Input Selection 2 + INSEL2: u4, + /// Inverted Event Input Enable + INVEI: u1, + /// LUT Event Input Enable + LUTEI: u1, + /// LUT Event Output Enable + LUTEO: u1, + reserved4: u1, + /// Truth Value + TRUTH: u8, + }), base_address + 0x8); + }; + + /// Cortex M Cache Controller + pub const CMCC = struct { + pub const base_address = 0x41006000; + pub const version = "U20156.0.0"; + + /// address: 0x41006000 + /// Cache Type Register + pub const TYPE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// dynamic Clock Gating supported + GCLK: u1, + reserved1: u1, + reserved2: u1, + /// Round Robin Policy supported + RRP: u1, + /// Number of Way + WAYNUM: u2, + /// Lock Down supported + LCKDOWN: u1, + /// Cache Size + CSIZE: u3, + /// Cache Line Size + CLSIZE: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x0); + + /// address: 0x41006004 + /// Cache Configuration Register + pub const CFG = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Instruction Cache Disable + ICDIS: u1, + /// Data Cache Disable + DCDIS: u1, + reserved1: u1, + /// Cache size configured by software + CSIZESW: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x41006008 + /// Cache Control Register + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Cache Controller Enable + CEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x8); + + /// address: 0x4100600c + /// Cache Status Register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Cache Controller Status + CSTS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0xc); + + /// address: 0x41006010 + /// Cache Lock per Way Register + pub const LCKWAY = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x10); + + /// address: 0x41006020 + /// Cache Maintenance Register 0 + pub const MAINT0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Cache Controller invalidate All + INVALL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x20); + + /// address: 0x41006024 + /// Cache Maintenance Register 1 + pub const MAINT1 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Invalidate Index + INDEX: u8, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + /// Invalidate Way + WAY: u4, + }), base_address + 0x24); + + /// address: 0x41006028 + /// Cache Monitor Configuration Register + pub const MCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Cache Controller Monitor Counter Mode + MODE: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x28); + + /// address: 0x4100602c + /// Cache Monitor Enable Register + pub const MEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Cache Controller Monitor Enable + MENABLE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x2c); + + /// address: 0x41006030 + /// Cache Monitor Control Register + pub const MCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Cache Controller Software Reset + SWRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x30); + + /// address: 0x41006034 + /// Cache Monitor Status Register + pub const MSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Monitor Event Counter + EVENT_CNT: u32, + }), base_address + 0x34); + }; + + /// Digital-to-Analog Converter + pub const DAC = struct { + pub const base_address = 0x43002400; + pub const version = "U25021.0.0"; + + /// address: 0x43002400 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { + /// Software Reset + SWRST: u1, + /// Enable DAC Controller + ENABLE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x0); + + /// address: 0x43002401 + /// Control B + pub const CTRLB = @intToPtr(*volatile Mmio(8, packed struct { + /// Differential mode enable + DIFF: u1, + /// Reference Selection for DAC0/1 + REFSEL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x1); + + /// address: 0x43002402 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Start Conversion Event Input DAC 0 + STARTEI0: u1, + /// Start Conversion Event Input DAC 1 + STARTEI1: u1, + /// Data Buffer Empty Event Output DAC 0 + EMPTYEO0: u1, + /// Data Buffer Empty Event Output DAC 1 + EMPTYEO1: u1, + /// Enable Invertion of DAC 0 input event + INVEI0: u1, + /// Enable Invertion of DAC 1 input event + INVEI1: u1, + /// Result Ready Event Output 0 + RESRDYEO0: u1, + /// Result Ready Event Output 1 + RESRDYEO1: u1, + }), base_address + 0x2); + + /// address: 0x43002404 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Underrun 0 Interrupt Enable + UNDERRUN0: u1, + /// Underrun 1 Interrupt Enable + UNDERRUN1: u1, + /// Data Buffer 0 Empty Interrupt Enable + EMPTY0: u1, + /// Data Buffer 1 Empty Interrupt Enable + EMPTY1: u1, + /// Result 0 Ready Interrupt Enable + RESRDY0: u1, + /// Result 1 Ready Interrupt Enable + RESRDY1: u1, + /// Overrun 0 Interrupt Enable + OVERRUN0: u1, + /// Overrun 1 Interrupt Enable + OVERRUN1: u1, + }), base_address + 0x4); + + /// address: 0x43002405 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Underrun 0 Interrupt Enable + UNDERRUN0: u1, + /// Underrun 1 Interrupt Enable + UNDERRUN1: u1, + /// Data Buffer 0 Empty Interrupt Enable + EMPTY0: u1, + /// Data Buffer 1 Empty Interrupt Enable + EMPTY1: u1, + /// Result 0 Ready Interrupt Enable + RESRDY0: u1, + /// Result 1 Ready Interrupt Enable + RESRDY1: u1, + /// Overrun 0 Interrupt Enable + OVERRUN0: u1, + /// Overrun 1 Interrupt Enable + OVERRUN1: u1, + }), base_address + 0x5); + + /// address: 0x43002406 + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Result 0 Underrun + UNDERRUN0: u1, + /// Result 1 Underrun + UNDERRUN1: u1, + /// Data Buffer 0 Empty + EMPTY0: u1, + /// Data Buffer 1 Empty + EMPTY1: u1, + /// Result 0 Ready + RESRDY0: u1, + /// Result 1 Ready + RESRDY1: u1, + /// Result 0 Overrun + OVERRUN0: u1, + /// Result 1 Overrun + OVERRUN1: u1, + }), base_address + 0x6); + + /// address: 0x43002407 + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { + /// DAC 0 Startup Ready + READY0: u1, + /// DAC 1 Startup Ready + READY1: u1, + /// DAC 0 End of Conversion + EOC0: u1, + /// DAC 1 End of Conversion + EOC1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x7); + + /// address: 0x43002408 + /// Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// DAC Enable Status + ENABLE: u1, + /// Data DAC 0 + DATA0: u1, + /// Data DAC 1 + DATA1: u1, + /// Data Buffer DAC 0 + DATABUF0: u1, + /// Data Buffer DAC 1 + DATABUF1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x8); + + /// address: 0x4300240c + /// DAC n Control + pub const DACCTRL = @intToPtr(*volatile [2]Mmio(16, packed struct { + /// Left Adjusted Data + LEFTADJ: u1, + /// Enable DAC0 + ENABLE: u1, + /// Current Control + CCTRL: u2, + reserved0: u1, + /// Standalone Filter + FEXT: u1, + /// Run in Standby + RUNSTDBY: u1, + /// Dithering Mode + DITHER: u1, + /// Refresh period + REFRESH: u4, + reserved1: u1, + /// Sampling Rate + OSR: u3, + }), base_address + 0xc); + + /// address: 0x43002410 + /// DAC n Data + pub const DATA = @intToPtr(*volatile [2]u16, base_address + 0x10); + + /// address: 0x43002414 + /// DAC n Data Buffer + pub const DATABUF = @intToPtr(*volatile [2]u16, base_address + 0x14); + + /// address: 0x43002418 + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Run + DBGRUN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x18); + + /// address: 0x4300241c + /// Filter Result + pub const RESULT = @intToPtr(*volatile [2]u16, base_address + 0x1c); + }; + + /// Direct Memory Access Controller + pub const DMAC = struct { + pub const base_address = 0x4100a000; + pub const version = "U25031.0.1"; + + /// address: 0x4100a000 + /// Control + pub const CTRL = @intToPtr(*volatile Mmio(16, packed struct { + /// Software Reset + SWRST: u1, + /// DMA Enable + DMAENABLE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Priority Level 0 Enable + LVLEN0: u1, + /// Priority Level 1 Enable + LVLEN1: u1, + /// Priority Level 2 Enable + LVLEN2: u1, + /// Priority Level 3 Enable + LVLEN3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x4100a002 + /// CRC Control + pub const CRCCTRL = @intToPtr(*volatile Mmio(16, packed struct { + /// CRC Beat Size + CRCBEATSIZE: u2, + /// CRC Polynomial Type + CRCPOLY: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CRC Input Source + CRCSRC: u6, + /// CRC Operating Mode + CRCMODE: u2, + }), base_address + 0x2); + + /// address: 0x4100a004 + /// CRC Data Input + pub const CRCDATAIN = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x4100a008 + /// CRC Checksum + pub const CRCCHKSUM = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4100a00c + /// CRC Status + pub const CRCSTATUS = @intToPtr(*volatile Mmio(8, packed struct { + /// CRC Module Busy + CRCBUSY: u1, + /// CRC Zero + CRCZERO: u1, + /// CRC Error + CRCERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0xc); + + /// address: 0x4100a00d + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Run + DBGRUN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0xd); + + /// address: 0x4100a010 + /// Software Trigger Control + pub const SWTRIGCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel 0 Software Trigger + SWTRIG0: u1, + /// Channel 1 Software Trigger + SWTRIG1: u1, + /// Channel 2 Software Trigger + SWTRIG2: u1, + /// Channel 3 Software Trigger + SWTRIG3: u1, + /// Channel 4 Software Trigger + SWTRIG4: u1, + /// Channel 5 Software Trigger + SWTRIG5: u1, + /// Channel 6 Software Trigger + SWTRIG6: u1, + /// Channel 7 Software Trigger + SWTRIG7: u1, + /// Channel 8 Software Trigger + SWTRIG8: u1, + /// Channel 9 Software Trigger + SWTRIG9: u1, + /// Channel 10 Software Trigger + SWTRIG10: u1, + /// Channel 11 Software Trigger + SWTRIG11: u1, + /// Channel 12 Software Trigger + SWTRIG12: u1, + /// Channel 13 Software Trigger + SWTRIG13: u1, + /// Channel 14 Software Trigger + SWTRIG14: u1, + /// Channel 15 Software Trigger + SWTRIG15: u1, + /// Channel 16 Software Trigger + SWTRIG16: u1, + /// Channel 17 Software Trigger + SWTRIG17: u1, + /// Channel 18 Software Trigger + SWTRIG18: u1, + /// Channel 19 Software Trigger + SWTRIG19: u1, + /// Channel 20 Software Trigger + SWTRIG20: u1, + /// Channel 21 Software Trigger + SWTRIG21: u1, + /// Channel 22 Software Trigger + SWTRIG22: u1, + /// Channel 23 Software Trigger + SWTRIG23: u1, + /// Channel 24 Software Trigger + SWTRIG24: u1, + /// Channel 25 Software Trigger + SWTRIG25: u1, + /// Channel 26 Software Trigger + SWTRIG26: u1, + /// Channel 27 Software Trigger + SWTRIG27: u1, + /// Channel 28 Software Trigger + SWTRIG28: u1, + /// Channel 29 Software Trigger + SWTRIG29: u1, + /// Channel 30 Software Trigger + SWTRIG30: u1, + /// Channel 31 Software Trigger + SWTRIG31: u1, + }), base_address + 0x10); + + /// address: 0x4100a014 + /// Priority Control 0 + pub const PRICTRL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Level 0 Channel Priority Number + LVLPRI0: u5, + /// Level 0 Quality of Service + QOS0: u2, + /// Level 0 Round-Robin Scheduling Enable + RRLVLEN0: u1, + /// Level 1 Channel Priority Number + LVLPRI1: u5, + /// Level 1 Quality of Service + QOS1: u2, + /// Level 1 Round-Robin Scheduling Enable + RRLVLEN1: u1, + /// Level 2 Channel Priority Number + LVLPRI2: u5, + /// Level 2 Quality of Service + QOS2: u2, + /// Level 2 Round-Robin Scheduling Enable + RRLVLEN2: u1, + /// Level 3 Channel Priority Number + LVLPRI3: u5, + /// Level 3 Quality of Service + QOS3: u2, + /// Level 3 Round-Robin Scheduling Enable + RRLVLEN3: u1, + }), base_address + 0x14); + + /// address: 0x4100a020 + /// Interrupt Pending + pub const INTPEND = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel ID + ID: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Transfer Error + TERR: u1, + /// Transfer Complete + TCMPL: u1, + /// Channel Suspend + SUSP: u1, + reserved3: u1, + /// CRC Error + CRCERR: u1, + /// Fetch Error + FERR: u1, + /// Busy + BUSY: u1, + /// Pending + PEND: u1, + }), base_address + 0x20); + + /// address: 0x4100a024 + /// Interrupt Status + pub const INTSTATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel 0 Pending Interrupt + CHINT0: u1, + /// Channel 1 Pending Interrupt + CHINT1: u1, + /// Channel 2 Pending Interrupt + CHINT2: u1, + /// Channel 3 Pending Interrupt + CHINT3: u1, + /// Channel 4 Pending Interrupt + CHINT4: u1, + /// Channel 5 Pending Interrupt + CHINT5: u1, + /// Channel 6 Pending Interrupt + CHINT6: u1, + /// Channel 7 Pending Interrupt + CHINT7: u1, + /// Channel 8 Pending Interrupt + CHINT8: u1, + /// Channel 9 Pending Interrupt + CHINT9: u1, + /// Channel 10 Pending Interrupt + CHINT10: u1, + /// Channel 11 Pending Interrupt + CHINT11: u1, + /// Channel 12 Pending Interrupt + CHINT12: u1, + /// Channel 13 Pending Interrupt + CHINT13: u1, + /// Channel 14 Pending Interrupt + CHINT14: u1, + /// Channel 15 Pending Interrupt + CHINT15: u1, + /// Channel 16 Pending Interrupt + CHINT16: u1, + /// Channel 17 Pending Interrupt + CHINT17: u1, + /// Channel 18 Pending Interrupt + CHINT18: u1, + /// Channel 19 Pending Interrupt + CHINT19: u1, + /// Channel 20 Pending Interrupt + CHINT20: u1, + /// Channel 21 Pending Interrupt + CHINT21: u1, + /// Channel 22 Pending Interrupt + CHINT22: u1, + /// Channel 23 Pending Interrupt + CHINT23: u1, + /// Channel 24 Pending Interrupt + CHINT24: u1, + /// Channel 25 Pending Interrupt + CHINT25: u1, + /// Channel 26 Pending Interrupt + CHINT26: u1, + /// Channel 27 Pending Interrupt + CHINT27: u1, + /// Channel 28 Pending Interrupt + CHINT28: u1, + /// Channel 29 Pending Interrupt + CHINT29: u1, + /// Channel 30 Pending Interrupt + CHINT30: u1, + /// Channel 31 Pending Interrupt + CHINT31: u1, + }), base_address + 0x24); + + /// address: 0x4100a028 + /// Busy Channels + pub const BUSYCH = @intToPtr(*volatile Mmio(32, packed struct { + /// Busy Channel 0 + BUSYCH0: u1, + /// Busy Channel 1 + BUSYCH1: u1, + /// Busy Channel 2 + BUSYCH2: u1, + /// Busy Channel 3 + BUSYCH3: u1, + /// Busy Channel 4 + BUSYCH4: u1, + /// Busy Channel 5 + BUSYCH5: u1, + /// Busy Channel 6 + BUSYCH6: u1, + /// Busy Channel 7 + BUSYCH7: u1, + /// Busy Channel 8 + BUSYCH8: u1, + /// Busy Channel 9 + BUSYCH9: u1, + /// Busy Channel 10 + BUSYCH10: u1, + /// Busy Channel 11 + BUSYCH11: u1, + /// Busy Channel 12 + BUSYCH12: u1, + /// Busy Channel 13 + BUSYCH13: u1, + /// Busy Channel 14 + BUSYCH14: u1, + /// Busy Channel 15 + BUSYCH15: u1, + /// Busy Channel 16 + BUSYCH16: u1, + /// Busy Channel 17 + BUSYCH17: u1, + /// Busy Channel 18 + BUSYCH18: u1, + /// Busy Channel 19 + BUSYCH19: u1, + /// Busy Channel 20 + BUSYCH20: u1, + /// Busy Channel 21 + BUSYCH21: u1, + /// Busy Channel 22 + BUSYCH22: u1, + /// Busy Channel 23 + BUSYCH23: u1, + /// Busy Channel 24 + BUSYCH24: u1, + /// Busy Channel 25 + BUSYCH25: u1, + /// Busy Channel 26 + BUSYCH26: u1, + /// Busy Channel 27 + BUSYCH27: u1, + /// Busy Channel 28 + BUSYCH28: u1, + /// Busy Channel 29 + BUSYCH29: u1, + /// Busy Channel 30 + BUSYCH30: u1, + /// Busy Channel 31 + BUSYCH31: u1, + }), base_address + 0x28); + + /// address: 0x4100a02c + /// Pending Channels + pub const PENDCH = @intToPtr(*volatile Mmio(32, packed struct { + /// Pending Channel 0 + PENDCH0: u1, + /// Pending Channel 1 + PENDCH1: u1, + /// Pending Channel 2 + PENDCH2: u1, + /// Pending Channel 3 + PENDCH3: u1, + /// Pending Channel 4 + PENDCH4: u1, + /// Pending Channel 5 + PENDCH5: u1, + /// Pending Channel 6 + PENDCH6: u1, + /// Pending Channel 7 + PENDCH7: u1, + /// Pending Channel 8 + PENDCH8: u1, + /// Pending Channel 9 + PENDCH9: u1, + /// Pending Channel 10 + PENDCH10: u1, + /// Pending Channel 11 + PENDCH11: u1, + /// Pending Channel 12 + PENDCH12: u1, + /// Pending Channel 13 + PENDCH13: u1, + /// Pending Channel 14 + PENDCH14: u1, + /// Pending Channel 15 + PENDCH15: u1, + /// Pending Channel 16 + PENDCH16: u1, + /// Pending Channel 17 + PENDCH17: u1, + /// Pending Channel 18 + PENDCH18: u1, + /// Pending Channel 19 + PENDCH19: u1, + /// Pending Channel 20 + PENDCH20: u1, + /// Pending Channel 21 + PENDCH21: u1, + /// Pending Channel 22 + PENDCH22: u1, + /// Pending Channel 23 + PENDCH23: u1, + /// Pending Channel 24 + PENDCH24: u1, + /// Pending Channel 25 + PENDCH25: u1, + /// Pending Channel 26 + PENDCH26: u1, + /// Pending Channel 27 + PENDCH27: u1, + /// Pending Channel 28 + PENDCH28: u1, + /// Pending Channel 29 + PENDCH29: u1, + /// Pending Channel 30 + PENDCH30: u1, + /// Pending Channel 31 + PENDCH31: u1, + }), base_address + 0x2c); + + /// address: 0x4100a030 + /// Active Channel and Levels + pub const ACTIVE = @intToPtr(*volatile Mmio(32, packed struct { + /// Level 0 Channel Trigger Request Executing + LVLEX0: u1, + /// Level 1 Channel Trigger Request Executing + LVLEX1: u1, + /// Level 2 Channel Trigger Request Executing + LVLEX2: u1, + /// Level 3 Channel Trigger Request Executing + LVLEX3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Active Channel ID + ID: u5, + reserved4: u1, + reserved5: u1, + /// Active Channel Busy + ABUSY: u1, + /// Active Channel Block Transfer Count + BTCNT: u16, + }), base_address + 0x30); + + /// address: 0x4100a034 + /// Descriptor Memory Section Base Address + pub const BASEADDR = @intToPtr(*volatile u32, base_address + 0x34); + + /// address: 0x4100a038 + /// Write-Back Memory Section Base Address + pub const WRBADDR = @intToPtr(*volatile u32, base_address + 0x38); + + pub const CHANNEL = @ptrCast(*volatile [32]packed struct { + /// Channel n Control A + CHCTRLA: Mmio(32, packed struct { + /// Channel Software Reset + SWRST: u1, + /// Channel Enable + ENABLE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Channel Run in Standby + RUNSTDBY: u1, + reserved4: u1, + /// Trigger Source + TRIGSRC: u7, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Trigger Action + TRIGACT: u2, + reserved10: u1, + reserved11: u1, + /// Burst Length + BURSTLEN: u4, + /// FIFO Threshold + THRESHOLD: u2, + padding0: u1, + padding1: u1, + }), + + /// Channel n Control B + CHCTRLB: Mmio(8, packed struct { + /// Software Command + CMD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), + + /// Channel n Priority Level + CHPRILVL: Mmio(8, packed struct { + /// Channel Priority Level + PRILVL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), + + /// Channel n Event Control + CHEVCTRL: Mmio(8, packed struct { + /// Channel Event Input Action + EVACT: u3, + reserved0: u1, + /// Channel Event Output Mode + EVOMODE: u2, + /// Channel Event Input Enable + EVIE: u1, + /// Channel Event Output Enable + EVOE: u1, + }), + + /// Channel n Interrupt Enable Clear + CHINTENCLR: Mmio(8, packed struct { + /// Channel Transfer Error Interrupt Enable + TERR: u1, + /// Channel Transfer Complete Interrupt Enable + TCMPL: u1, + /// Channel Suspend Interrupt Enable + SUSP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), + + /// Channel n Interrupt Enable Set + CHINTENSET: Mmio(8, packed struct { + /// Channel Transfer Error Interrupt Enable + TERR: u1, + /// Channel Transfer Complete Interrupt Enable + TCMPL: u1, + /// Channel Suspend Interrupt Enable + SUSP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), + + /// Channel n Interrupt Flag Status and Clear + CHINTFLAG: Mmio(8, packed struct { + /// Channel Transfer Error + TERR: u1, + /// Channel Transfer Complete + TCMPL: u1, + /// Channel Suspend + SUSP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), + + /// Channel n Status + CHSTATUS: Mmio(8, packed struct { + /// Channel Pending + PEND: u1, + /// Channel Busy + BUSY: u1, + /// Channel Fetch Error + FERR: u1, + /// Channel CRC Error + CRCERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), + padding0: u32, + }, base_address + 0x40); + }; + + /// Device Service Unit + pub const DSU = struct { + pub const base_address = 0x41002000; + pub const version = "U24101.0.0"; + + /// address: 0x41002000 + /// Control + pub const CTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Software Reset + SWRST: u1, + reserved0: u1, + /// 32-bit Cyclic Redundancy Code + CRC: u1, + /// Memory built-in self-test + MBIST: u1, + /// Chip-Erase + CE: u1, + reserved1: u1, + /// Auxiliary Row Read + ARR: u1, + /// Start Memory Stream Access + SMSA: u1, + }), base_address + 0x0); + + /// address: 0x41002001 + /// Status A + pub const STATUSA = @intToPtr(*volatile Mmio(8, packed struct { + /// Done + DONE: u1, + /// CPU Reset Phase Extension + CRSTEXT: u1, + /// Bus Error + BERR: u1, + /// Failure + FAIL: u1, + /// Protection Error + PERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x1); + + /// address: 0x41002002 + /// Status B + pub const STATUSB = @intToPtr(*volatile Mmio(8, packed struct { + /// Protected + PROT: u1, + /// Debugger Present + DBGPRES: u1, + /// Debug Communication Channel 0 Dirty + DCCD0: u1, + /// Debug Communication Channel 1 Dirty + DCCD1: u1, + /// Hot-Plugging Enable + HPE: u1, + /// Chip Erase Locked + CELCK: u1, + /// Test Debug Communication Channel 0 Dirty + TDCCD0: u1, + /// Test Debug Communication Channel 1 Dirty + TDCCD1: u1, + }), base_address + 0x2); + + /// address: 0x41002004 + /// Address + pub const ADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Access Mode + AMOD: u2, + /// Address + ADDR: u30, + }), base_address + 0x4); + + /// address: 0x41002008 + /// Length + pub const LENGTH = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x8); + + /// address: 0x4100200c + /// Data + pub const DATA = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x41002010 + /// Debug Communication Channel n + pub const DCC = @intToPtr(*volatile [2]Mmio(32, packed struct { + /// Data + DATA: u32, + }), base_address + 0x10); + + /// address: 0x41002018 + /// Device Identification + pub const DID = @intToPtr(*volatile Mmio(32, packed struct { + /// Device Select + DEVSEL: u8, + /// Revision Number + REVISION: u4, + /// Die Number + DIE: u4, + /// Series + SERIES: u6, + reserved0: u1, + /// Family + FAMILY: u5, + /// Processor + PROCESSOR: u4, + }), base_address + 0x18); + + /// address: 0x4100201c + /// Configuration + pub const CFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Latency Quality Of Service + LQOS: u2, + /// DMA Trigger Level + DCCDMALEVEL: u2, + /// Trace Control + ETBRAMEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x1c); + + /// address: 0x410020f0 + /// Device Configuration + pub const DCFG = @intToPtr(*volatile [2]u32, base_address + 0xf0); + + /// address: 0x41003000 + /// CoreSight ROM Table Entry 0 + pub const ENTRY0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Entry Present + EPRES: u1, + /// Format + FMT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Address Offset + ADDOFF: u20, + }), base_address + 0x1000); + + /// address: 0x41003004 + /// CoreSight ROM Table Entry 1 + pub const ENTRY1 = @intToPtr(*volatile u32, base_address + 0x1004); + + /// address: 0x41003008 + /// CoreSight ROM Table End + pub const END = @intToPtr(*volatile u32, base_address + 0x1008); + + /// address: 0x41003fcc + /// CoreSight ROM Table Memory Type + pub const MEMTYPE = @intToPtr(*volatile Mmio(32, packed struct { + /// System Memory Present + SMEMP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x1fcc); + + /// address: 0x41003fd0 + /// Peripheral Identification 4 + pub const PID4 = @intToPtr(*volatile Mmio(32, packed struct { + /// JEP-106 Continuation Code + JEPCC: u4, + /// 4KB count + FKBC: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x1fd0); + + /// address: 0x41003fd4 + /// Peripheral Identification 5 + pub const PID5 = @intToPtr(*volatile u32, base_address + 0x1fd4); + + /// address: 0x41003fd8 + /// Peripheral Identification 6 + pub const PID6 = @intToPtr(*volatile u32, base_address + 0x1fd8); + + /// address: 0x41003fdc + /// Peripheral Identification 7 + pub const PID7 = @intToPtr(*volatile u32, base_address + 0x1fdc); + + /// address: 0x41003fe0 + /// Peripheral Identification 0 + pub const PID0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Part Number Low + PARTNBL: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x1fe0); + + /// address: 0x41003fe4 + /// Peripheral Identification 1 + pub const PID1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Part Number High + PARTNBH: u4, + /// Low part of the JEP-106 Identity Code + JEPIDCL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x1fe4); + + /// address: 0x41003fe8 + /// Peripheral Identification 2 + pub const PID2 = @intToPtr(*volatile Mmio(32, packed struct { + /// JEP-106 Identity Code High + JEPIDCH: u3, + /// JEP-106 Identity Code is used + JEPU: u1, + /// Revision Number + REVISION: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x1fe8); + + /// address: 0x41003fec + /// Peripheral Identification 3 + pub const PID3 = @intToPtr(*volatile Mmio(32, packed struct { + /// ARM CUSMOD + CUSMOD: u4, + /// Revision Number + REVAND: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x1fec); + + /// address: 0x41003ff0 + /// Component Identification 0 + pub const CID0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Preamble Byte 0 + PREAMBLEB0: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x1ff0); + + /// address: 0x41003ff4 + /// Component Identification 1 + pub const CID1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Preamble + PREAMBLE: u4, + /// Component Class + CCLASS: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x1ff4); + + /// address: 0x41003ff8 + /// Component Identification 2 + pub const CID2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Preamble Byte 2 + PREAMBLEB2: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x1ff8); + + /// address: 0x41003ffc + /// Component Identification 3 + pub const CID3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Preamble Byte 3 + PREAMBLEB3: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x1ffc); + }; + + /// External Interrupt Controller + pub const EIC = struct { + pub const base_address = 0x40002800; + pub const version = "U22543.0.0"; + + /// address: 0x40002800 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + reserved0: u1, + reserved1: u1, + /// Clock Selection + CKSEL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x0); + + /// address: 0x40002801 + /// Non-Maskable Interrupt Control + pub const NMICTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Non-Maskable Interrupt Sense Configuration + NMISENSE: u3, + /// Non-Maskable Interrupt Filter Enable + NMIFILTEN: u1, + /// Asynchronous Edge Detection Mode + NMIASYNCH: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x1); + + /// address: 0x40002802 + /// Non-Maskable Interrupt Flag Status and Clear + pub const NMIFLAG = @intToPtr(*volatile Mmio(16, packed struct { + /// Non-Maskable Interrupt + NMI: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x2); + + /// address: 0x40002804 + /// Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset Synchronization Busy Status + SWRST: u1, + /// Enable Synchronization Busy Status + ENABLE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x4); + + /// address: 0x40002808 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// External Interrupt Event Output Enable + EXTINTEO: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000280c + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// External Interrupt Enable + EXTINT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40002810 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { + /// External Interrupt Enable + EXTINT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40002814 + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { + /// External Interrupt + EXTINT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40002818 + /// External Interrupt Asynchronous Mode + pub const ASYNCH = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x18); + + /// address: 0x4000281c + /// External Interrupt Sense Configuration + pub const CONFIG = @intToPtr(*volatile [2]Mmio(32, packed struct { + /// Input Sense Configuration 0 + SENSE0: u3, + /// Filter Enable 0 + FILTEN0: u1, + /// Input Sense Configuration 1 + SENSE1: u3, + /// Filter Enable 1 + FILTEN1: u1, + /// Input Sense Configuration 2 + SENSE2: u3, + /// Filter Enable 2 + FILTEN2: u1, + /// Input Sense Configuration 3 + SENSE3: u3, + /// Filter Enable 3 + FILTEN3: u1, + /// Input Sense Configuration 4 + SENSE4: u3, + /// Filter Enable 4 + FILTEN4: u1, + /// Input Sense Configuration 5 + SENSE5: u3, + /// Filter Enable 5 + FILTEN5: u1, + /// Input Sense Configuration 6 + SENSE6: u3, + /// Filter Enable 6 + FILTEN6: u1, + /// Input Sense Configuration 7 + SENSE7: u3, + /// Filter Enable 7 + FILTEN7: u1, + }), base_address + 0x1c); + + /// address: 0x40002830 + /// Debouncer Enable + pub const DEBOUNCEN = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x30); + + /// address: 0x40002834 + /// Debouncer Prescaler + pub const DPRESCALER = @intToPtr(*volatile Mmio(32, packed struct { + /// Debouncer Prescaler + PRESCALER0: u3, + /// Debouncer number of states + STATES0: u1, + /// Debouncer Prescaler + PRESCALER1: u3, + /// Debouncer number of states + STATES1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Pin Sampler frequency selection + TICKON: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x34); + + /// address: 0x40002838 + /// Pin State + pub const PINSTATE = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + }; + + /// Event System Interface + pub const EVSYS = struct { + pub const base_address = 0x4100e000; + pub const version = "U25041.0.0"; + + /// address: 0x4100e000 + /// Control + pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { + /// Software Reset + SWRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x0); + + /// address: 0x4100e004 + /// Software Event + pub const SWEVT = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel 0 Software Selection + CHANNEL0: u1, + /// Channel 1 Software Selection + CHANNEL1: u1, + /// Channel 2 Software Selection + CHANNEL2: u1, + /// Channel 3 Software Selection + CHANNEL3: u1, + /// Channel 4 Software Selection + CHANNEL4: u1, + /// Channel 5 Software Selection + CHANNEL5: u1, + /// Channel 6 Software Selection + CHANNEL6: u1, + /// Channel 7 Software Selection + CHANNEL7: u1, + /// Channel 8 Software Selection + CHANNEL8: u1, + /// Channel 9 Software Selection + CHANNEL9: u1, + /// Channel 10 Software Selection + CHANNEL10: u1, + /// Channel 11 Software Selection + CHANNEL11: u1, + /// Channel 12 Software Selection + CHANNEL12: u1, + /// Channel 13 Software Selection + CHANNEL13: u1, + /// Channel 14 Software Selection + CHANNEL14: u1, + /// Channel 15 Software Selection + CHANNEL15: u1, + /// Channel 16 Software Selection + CHANNEL16: u1, + /// Channel 17 Software Selection + CHANNEL17: u1, + /// Channel 18 Software Selection + CHANNEL18: u1, + /// Channel 19 Software Selection + CHANNEL19: u1, + /// Channel 20 Software Selection + CHANNEL20: u1, + /// Channel 21 Software Selection + CHANNEL21: u1, + /// Channel 22 Software Selection + CHANNEL22: u1, + /// Channel 23 Software Selection + CHANNEL23: u1, + /// Channel 24 Software Selection + CHANNEL24: u1, + /// Channel 25 Software Selection + CHANNEL25: u1, + /// Channel 26 Software Selection + CHANNEL26: u1, + /// Channel 27 Software Selection + CHANNEL27: u1, + /// Channel 28 Software Selection + CHANNEL28: u1, + /// Channel 29 Software Selection + CHANNEL29: u1, + /// Channel 30 Software Selection + CHANNEL30: u1, + /// Channel 31 Software Selection + CHANNEL31: u1, + }), base_address + 0x4); + + /// address: 0x4100e008 + /// Priority Control + pub const PRICTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Channel Priority Number + PRI: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Round-Robin Scheduling Enable + RREN: u1, + }), base_address + 0x8); + + /// address: 0x4100e010 + /// Channel Pending Interrupt + pub const INTPEND = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel ID + ID: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Channel Overrun + OVR: u1, + /// Channel Event Detected + EVD: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Ready + READY: u1, + /// Busy + BUSY: u1, + }), base_address + 0x10); + + /// address: 0x4100e014 + /// Interrupt Status + pub const INTSTATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel 0 Pending Interrupt + CHINT0: u1, + /// Channel 1 Pending Interrupt + CHINT1: u1, + /// Channel 2 Pending Interrupt + CHINT2: u1, + /// Channel 3 Pending Interrupt + CHINT3: u1, + /// Channel 4 Pending Interrupt + CHINT4: u1, + /// Channel 5 Pending Interrupt + CHINT5: u1, + /// Channel 6 Pending Interrupt + CHINT6: u1, + /// Channel 7 Pending Interrupt + CHINT7: u1, + /// Channel 8 Pending Interrupt + CHINT8: u1, + /// Channel 9 Pending Interrupt + CHINT9: u1, + /// Channel 10 Pending Interrupt + CHINT10: u1, + /// Channel 11 Pending Interrupt + CHINT11: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x4100e018 + /// Busy Channels + pub const BUSYCH = @intToPtr(*volatile Mmio(32, packed struct { + /// Busy Channel 0 + BUSYCH0: u1, + /// Busy Channel 1 + BUSYCH1: u1, + /// Busy Channel 2 + BUSYCH2: u1, + /// Busy Channel 3 + BUSYCH3: u1, + /// Busy Channel 4 + BUSYCH4: u1, + /// Busy Channel 5 + BUSYCH5: u1, + /// Busy Channel 6 + BUSYCH6: u1, + /// Busy Channel 7 + BUSYCH7: u1, + /// Busy Channel 8 + BUSYCH8: u1, + /// Busy Channel 9 + BUSYCH9: u1, + /// Busy Channel 10 + BUSYCH10: u1, + /// Busy Channel 11 + BUSYCH11: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x18); + + /// address: 0x4100e01c + /// Ready Users + pub const READYUSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Ready User for Channel 0 + READYUSR0: u1, + /// Ready User for Channel 1 + READYUSR1: u1, + /// Ready User for Channel 2 + READYUSR2: u1, + /// Ready User for Channel 3 + READYUSR3: u1, + /// Ready User for Channel 4 + READYUSR4: u1, + /// Ready User for Channel 5 + READYUSR5: u1, + /// Ready User for Channel 6 + READYUSR6: u1, + /// Ready User for Channel 7 + READYUSR7: u1, + /// Ready User for Channel 8 + READYUSR8: u1, + /// Ready User for Channel 9 + READYUSR9: u1, + /// Ready User for Channel 10 + READYUSR10: u1, + /// Ready User for Channel 11 + READYUSR11: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x4100e120 + /// User Multiplexer n + pub const USER = @intToPtr(*volatile [67]Mmio(32, packed struct { + /// Channel Event Selection + CHANNEL: u6, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x120); + + pub const CHANNEL = @ptrCast(*volatile [32]packed struct { + /// Channel n Control + CHANNEL: Mmio(32, packed struct { + /// Event Generator Selection + EVGEN: u7, + reserved0: u1, + /// Path Selection + PATH: u2, + /// Edge Detection Selection + EDGSEL: u2, + reserved1: u1, + reserved2: u1, + /// Run in standby + RUNSTDBY: u1, + /// Generic Clock On Demand + ONDEMAND: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), + + /// Channel n Interrupt Enable Clear + CHINTENCLR: Mmio(8, packed struct { + /// Channel Overrun Interrupt Disable + OVR: u1, + /// Channel Event Detected Interrupt Disable + EVD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), + + /// Channel n Interrupt Enable Set + CHINTENSET: Mmio(8, packed struct { + /// Channel Overrun Interrupt Enable + OVR: u1, + /// Channel Event Detected Interrupt Enable + EVD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), + + /// Channel n Interrupt Flag Status and Clear + CHINTFLAG: Mmio(8, packed struct { + /// Channel Overrun + OVR: u1, + /// Channel Event Detected + EVD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), + + /// Channel n Status + CHSTATUS: Mmio(8, packed struct { + /// Ready User + RDYUSR: u1, + /// Busy Channel + BUSYCH: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), + }, base_address + 0x20); + }; + + /// Frequency Meter + pub const FREQM = struct { + pub const base_address = 0x40002c00; + pub const version = "U22571.1.0"; + + /// address: 0x40002c00 + /// Control A Register + pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x0); + + /// address: 0x40002c01 + /// Control B Register + pub const CTRLB = @intToPtr(*volatile Mmio(8, packed struct { + /// Start Measurement + START: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x1); + + /// address: 0x40002c02 + /// Config A register + pub const CFGA = @intToPtr(*volatile Mmio(16, packed struct { + /// Number of Reference Clock Cycles + REFNUM: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x2); + + /// address: 0x40002c08 + /// Interrupt Enable Clear Register + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Measurement Done Interrupt Enable + DONE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x8); + + /// address: 0x40002c09 + /// Interrupt Enable Set Register + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Measurement Done Interrupt Enable + DONE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x9); + + /// address: 0x40002c0a + /// Interrupt Flag Register + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Measurement Done + DONE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0xa); + + /// address: 0x40002c0b + /// Status Register + pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { + /// FREQM Status + BUSY: u1, + /// Sticky Count Value Overflow + OVF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xb); + + /// address: 0x40002c0c + /// Synchronization Busy Register + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + + /// address: 0x40002c10 + /// Count Value Register + pub const VALUE = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x10); + }; + + /// Generic Clock Generator + pub const GCLK = struct { + pub const base_address = 0x40001c00; + pub const version = "U21221.2.0"; + + /// address: 0x40001c00 + /// Control + pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { + /// Software Reset + SWRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x0); + + /// address: 0x40001c04 + /// Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset Synchroniation Busy bit + SWRST: u1, + reserved0: u1, + /// Generic Clock Generator Control n Synchronization Busy bits + GENCTRL: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x4); + + /// address: 0x40001c20 + /// Generic Clock Generator Control + pub const GENCTRL = @intToPtr(*volatile [12]Mmio(32, packed struct { + /// Source Select + SRC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Generic Clock Generator Enable + GENEN: u1, + /// Improve Duty Cycle + IDC: u1, + /// Output Off Value + OOV: u1, + /// Output Enable + OE: u1, + /// Divide Selection + DIVSEL: u1, + /// Run in Standby + RUNSTDBY: u1, + reserved4: u1, + reserved5: u1, + /// Division Factor + DIV: u16, + }), base_address + 0x20); + + /// address: 0x40001c80 + /// Peripheral Clock Control + pub const PCHCTRL = @intToPtr(*volatile [48]Mmio(32, packed struct { + /// Generic Clock Generator + GEN: u4, + reserved0: u1, + reserved1: u1, + /// Channel Enable + CHEN: u1, + /// Write Lock + WRTLOCK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x80); + }; + + /// HSB Matrix + pub const HMATRIX = struct { + pub const base_address = 0x4100c000; + pub const version = "I76382.1.4"; + + pub const PRS = @ptrCast(*volatile [16]packed struct { + /// Priority A for Slave + PRAS: u32, + + /// Priority B for Slave + PRBS: u32, + }, base_address + 0x80); + }; + + /// Integrity Check Monitor + pub const ICM = struct { + pub const base_address = 0x42002c00; + pub const version = "U20101.2.0"; + + /// address: 0x42002c00 + /// Configuration + pub const CFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Write Back Disable + WBDIS: u1, + /// End of Monitoring Disable + EOMDIS: u1, + /// Secondary List Branching Disable + SLBDIS: u1, + reserved0: u1, + /// Bus Burden Control + BBC: u4, + /// Automatic Switch To Compare Digest + ASCD: u1, + /// Dual Input Buffer + DUALBUFF: u1, + reserved1: u1, + reserved2: u1, + /// User Initial Hash Value + UIHASH: u1, + /// User SHA Algorithm + UALGO: u3, + /// Region Hash Area Protection + HAPROT: u6, + reserved3: u1, + reserved4: u1, + /// Region Descriptor Area Protection + DAPROT: u6, + padding0: u1, + padding1: u1, + }), base_address + 0x0); + + /// address: 0x42002c04 + /// Control + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// ICM Enable + ENABLE: u1, + /// ICM Disable Register + DISABLE: u1, + /// Software Reset + SWRST: u1, + reserved0: u1, + /// Recompute Internal Hash + REHASH: u4, + /// Region Monitoring Disable + RMDIS: u4, + /// Region Monitoring Enable + RMEN: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x42002c08 + /// Status + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// ICM Controller Enable Register + ENABLE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// RAW Region Monitoring Disabled Status + RAWRMDIS: u4, + /// Region Monitoring Disabled Status + RMDIS: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x42002c10 + /// Interrupt Enable + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { + /// Region Hash Completed Interrupt Enable + RHC: u4, + /// Region Digest Mismatch Interrupt Enable + RDM: u4, + /// Region Bus Error Interrupt Enable + RBE: u4, + /// Region Wrap Condition detected Interrupt Enable + RWC: u4, + /// Region End bit Condition Detected Interrupt Enable + REC: u4, + /// Region Status Updated Interrupt Disable + RSU: u4, + /// Undefined Register Access Detection Interrupt Enable + URAD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x10); + + /// address: 0x42002c14 + /// Interrupt Disable + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Region Hash Completed Interrupt Disable + RHC: u4, + /// Region Digest Mismatch Interrupt Disable + RDM: u4, + /// Region Bus Error Interrupt Disable + RBE: u4, + /// Region Wrap Condition Detected Interrupt Disable + RWC: u4, + /// Region End bit Condition detected Interrupt Disable + REC: u4, + /// Region Status Updated Interrupt Disable + RSU: u4, + /// Undefined Register Access Detection Interrupt Disable + URAD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x14); + + /// address: 0x42002c18 + /// Interrupt Mask + pub const IMR = @intToPtr(*volatile Mmio(32, packed struct { + /// Region Hash Completed Interrupt Mask + RHC: u4, + /// Region Digest Mismatch Interrupt Mask + RDM: u4, + /// Region Bus Error Interrupt Mask + RBE: u4, + /// Region Wrap Condition Detected Interrupt Mask + RWC: u4, + /// Region End bit Condition Detected Interrupt Mask + REC: u4, + /// Region Status Updated Interrupt Mask + RSU: u4, + /// Undefined Register Access Detection Interrupt Mask + URAD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x18); + + /// address: 0x42002c1c + /// Interrupt Status + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Region Hash Completed + RHC: u4, + /// Region Digest Mismatch + RDM: u4, + /// Region Bus Error + RBE: u4, + /// Region Wrap Condition Detected + RWC: u4, + /// Region End bit Condition Detected + REC: u4, + /// Region Status Updated Detected + RSU: u4, + /// Undefined Register Access Detection Status + URAD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x1c); + + /// address: 0x42002c20 + /// Undefined Access Status + pub const UASR = @intToPtr(*volatile Mmio(32, packed struct { + /// Undefined Register Access Trace + URAT: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x20); + + /// address: 0x42002c30 + /// Region Descriptor Area Start Address + pub const DSCR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Descriptor Area Start Address + DASA: u26, + }), base_address + 0x30); + + /// address: 0x42002c34 + /// Region Hash Area Start Address + pub const HASH = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Hash Area Start Address + HASA: u25, + }), base_address + 0x34); + + /// address: 0x42002c38 + /// User Initial Hash Value n + pub const UIHVAL = @intToPtr(*volatile [8]Mmio(32, packed struct { + /// Initial Hash Value + VAL: u32, + }), base_address + 0x38); + }; + + /// Inter-IC Sound Interface + pub const I2S = struct { + pub const base_address = 0x43002800; + pub const version = "U22242.0.0"; + + /// address: 0x43002800 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Clock Unit 0 Enable + CKEN0: u1, + /// Clock Unit 1 Enable + CKEN1: u1, + /// Tx Serializer Enable + TXEN: u1, + /// Rx Serializer Enable + RXEN: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x0); + + /// address: 0x43002804 + /// Clock Unit n Control + pub const CLKCTRL = @intToPtr(*volatile [2]Mmio(32, packed struct { + /// Slot Size + SLOTSIZE: u2, + /// Number of Slots in Frame + NBSLOTS: u3, + /// Frame Sync Width + FSWIDTH: u2, + /// Data Delay from Frame Sync + BITDELAY: u1, + /// Frame Sync Select + FSSEL: u1, + /// Frame Sync Invert + FSINV: u1, + /// Frame Sync Output Invert + FSOUTINV: u1, + /// Serial Clock Select + SCKSEL: u1, + /// Serial Clock Output Invert + SCKOUTINV: u1, + /// Master Clock Select + MCKSEL: u1, + /// Master Clock Enable + MCKEN: u1, + /// Master Clock Output Invert + MCKOUTINV: u1, + /// Master Clock Division Factor + MCKDIV: u6, + reserved0: u1, + reserved1: u1, + /// Master Clock Output Division Factor + MCKOUTDIV: u6, + padding0: u1, + padding1: u1, + }), base_address + 0x4); + + /// address: 0x4300280c + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(16, packed struct { + /// Receive Ready 0 Interrupt Enable + RXRDY0: u1, + /// Receive Ready 1 Interrupt Enable + RXRDY1: u1, + reserved0: u1, + reserved1: u1, + /// Receive Overrun 0 Interrupt Enable + RXOR0: u1, + /// Receive Overrun 1 Interrupt Enable + RXOR1: u1, + reserved2: u1, + reserved3: u1, + /// Transmit Ready 0 Interrupt Enable + TXRDY0: u1, + /// Transmit Ready 1 Interrupt Enable + TXRDY1: u1, + reserved4: u1, + reserved5: u1, + /// Transmit Underrun 0 Interrupt Enable + TXUR0: u1, + /// Transmit Underrun 1 Interrupt Enable + TXUR1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0xc); + + /// address: 0x43002810 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(16, packed struct { + /// Receive Ready 0 Interrupt Enable + RXRDY0: u1, + /// Receive Ready 1 Interrupt Enable + RXRDY1: u1, + reserved0: u1, + reserved1: u1, + /// Receive Overrun 0 Interrupt Enable + RXOR0: u1, + /// Receive Overrun 1 Interrupt Enable + RXOR1: u1, + reserved2: u1, + reserved3: u1, + /// Transmit Ready 0 Interrupt Enable + TXRDY0: u1, + /// Transmit Ready 1 Interrupt Enable + TXRDY1: u1, + reserved4: u1, + reserved5: u1, + /// Transmit Underrun 0 Interrupt Enable + TXUR0: u1, + /// Transmit Underrun 1 Interrupt Enable + TXUR1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x10); + + /// address: 0x43002814 + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(16, packed struct { + /// Receive Ready 0 + RXRDY0: u1, + /// Receive Ready 1 + RXRDY1: u1, + reserved0: u1, + reserved1: u1, + /// Receive Overrun 0 + RXOR0: u1, + /// Receive Overrun 1 + RXOR1: u1, + reserved2: u1, + reserved3: u1, + /// Transmit Ready 0 + TXRDY0: u1, + /// Transmit Ready 1 + TXRDY1: u1, + reserved4: u1, + reserved5: u1, + /// Transmit Underrun 0 + TXUR0: u1, + /// Transmit Underrun 1 + TXUR1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x14); + + /// address: 0x43002818 + /// Synchronization Status + pub const SYNCBUSY = @intToPtr(*volatile Mmio(16, packed struct { + /// Software Reset Synchronization Status + SWRST: u1, + /// Enable Synchronization Status + ENABLE: u1, + /// Clock Unit 0 Enable Synchronization Status + CKEN0: u1, + /// Clock Unit 1 Enable Synchronization Status + CKEN1: u1, + /// Tx Serializer Enable Synchronization Status + TXEN: u1, + /// Rx Serializer Enable Synchronization Status + RXEN: u1, + reserved0: u1, + reserved1: u1, + /// Tx Data Synchronization Status + TXDATA: u1, + /// Rx Data Synchronization Status + RXDATA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x18); + + /// address: 0x43002820 + /// Tx Serializer Control + pub const TXCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Serializer Mode + SERMODE: u2, + /// Line Default Line when Slot Disabled + TXDEFAULT: u2, + /// Transmit Data when Underrun + TXSAME: u1, + /// Clock Unit Selection + CLKSEL: u1, + reserved0: u1, + /// Data Slot Formatting Adjust + SLOTADJ: u1, + /// Data Word Size + DATASIZE: u3, + reserved1: u1, + /// Data Word Formatting Adjust + WORDADJ: u1, + /// Data Formatting Bit Extension + EXTEND: u2, + /// Data Formatting Bit Reverse + BITREV: u1, + /// Slot 0 Disabled for this Serializer + SLOTDIS0: u1, + /// Slot 1 Disabled for this Serializer + SLOTDIS1: u1, + /// Slot 2 Disabled for this Serializer + SLOTDIS2: u1, + /// Slot 3 Disabled for this Serializer + SLOTDIS3: u1, + /// Slot 4 Disabled for this Serializer + SLOTDIS4: u1, + /// Slot 5 Disabled for this Serializer + SLOTDIS5: u1, + /// Slot 6 Disabled for this Serializer + SLOTDIS6: u1, + /// Slot 7 Disabled for this Serializer + SLOTDIS7: u1, + /// Mono Mode + MONO: u1, + /// Single or Multiple DMA Channels + DMA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x20); + + /// address: 0x43002824 + /// Rx Serializer Control + pub const RXCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Serializer Mode + SERMODE: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Clock Unit Selection + CLKSEL: u1, + reserved3: u1, + /// Data Slot Formatting Adjust + SLOTADJ: u1, + /// Data Word Size + DATASIZE: u3, + reserved4: u1, + /// Data Word Formatting Adjust + WORDADJ: u1, + /// Data Formatting Bit Extension + EXTEND: u2, + /// Data Formatting Bit Reverse + BITREV: u1, + /// Slot 0 Disabled for this Serializer + SLOTDIS0: u1, + /// Slot 1 Disabled for this Serializer + SLOTDIS1: u1, + /// Slot 2 Disabled for this Serializer + SLOTDIS2: u1, + /// Slot 3 Disabled for this Serializer + SLOTDIS3: u1, + /// Slot 4 Disabled for this Serializer + SLOTDIS4: u1, + /// Slot 5 Disabled for this Serializer + SLOTDIS5: u1, + /// Slot 6 Disabled for this Serializer + SLOTDIS6: u1, + /// Slot 7 Disabled for this Serializer + SLOTDIS7: u1, + /// Mono Mode + MONO: u1, + /// Single or Multiple DMA Channels + DMA: u1, + /// Loop-back Test Mode + RXLOOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x24); + + /// address: 0x43002830 + /// Tx Data + pub const TXDATA = @intToPtr(*volatile Mmio(32, packed struct { + /// Sample Data + DATA: u32, + }), base_address + 0x30); + + /// address: 0x43002834 + /// Rx Data + pub const RXDATA = @intToPtr(*volatile Mmio(32, packed struct { + /// Sample Data + DATA: u32, + }), base_address + 0x34); + }; + + /// Main Clock + pub const MCLK = struct { + pub const base_address: usize = 0x40000800; + pub const version = "U24081.0.0"; + + /// address: 0x40000801 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Clock Ready Interrupt Enable + CKRDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x1); + + /// address: 0x40000802 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Clock Ready Interrupt Enable + CKRDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x2); + + /// address: 0x40000803 + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Clock Ready + CKRDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x3); + + /// address: 0x40000804 + /// HS Clock Division + pub const HSDIV = @intToPtr(*volatile Mmio(8, packed struct { + /// CPU Clock Division Factor + DIV: u8, + }), base_address + 0x4); + + /// address: 0x40000805 + /// CPU Clock Division + pub const CPUDIV = @intToPtr(*volatile Mmio(8, packed struct { + /// Low-Power Clock Division Factor + DIV: u8, + }), base_address + 0x5); + + /// address: 0x40000810 + /// AHB Mask + pub const AHBMASK = @intToPtr(*volatile Mmio(32, packed struct { + /// HPB0 AHB Clock Mask + HPB0_: u1, + /// HPB1 AHB Clock Mask + HPB1_: u1, + /// HPB2 AHB Clock Mask + HPB2_: u1, + /// HPB3 AHB Clock Mask + HPB3_: u1, + /// DSU AHB Clock Mask + DSU_: u1, + /// HMATRIX AHB Clock Mask + HMATRIX_: u1, + /// NVMCTRL AHB Clock Mask + NVMCTRL_: u1, + /// HSRAM AHB Clock Mask + HSRAM_: u1, + /// CMCC AHB Clock Mask + CMCC_: u1, + /// DMAC AHB Clock Mask + DMAC_: u1, + /// USB AHB Clock Mask + USB_: u1, + /// BKUPRAM AHB Clock Mask + BKUPRAM_: u1, + /// PAC AHB Clock Mask + PAC_: u1, + /// QSPI AHB Clock Mask + QSPI_: u1, + reserved0: u1, + /// SDHC0 AHB Clock Mask + SDHC0_: u1, + reserved1: u1, + /// CAN0 AHB Clock Mask + CAN0_: u1, + /// CAN1 AHB Clock Mask + CAN1_: u1, + /// ICM AHB Clock Mask + ICM_: u1, + /// PUKCC AHB Clock Mask + PUKCC_: u1, + /// QSPI_2X AHB Clock Mask + QSPI_2X_: u1, + /// NVMCTRL_SMEEPROM AHB Clock Mask + NVMCTRL_SMEEPROM_: u1, + /// NVMCTRL_CACHE AHB Clock Mask + NVMCTRL_CACHE_: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x10); + + /// address: 0x40000814 + /// APBA Mask + pub const APBAMASK = @intToPtr(*volatile Mmio(32, packed struct { + /// PAC APB Clock Enable + PAC_: u1, + /// PM APB Clock Enable + PM_: u1, + /// MCLK APB Clock Enable + MCLK_: u1, + /// RSTC APB Clock Enable + RSTC_: u1, + /// OSCCTRL APB Clock Enable + OSCCTRL_: u1, + /// OSC32KCTRL APB Clock Enable + OSC32KCTRL_: u1, + /// SUPC APB Clock Enable + SUPC_: u1, + /// GCLK APB Clock Enable + GCLK_: u1, + /// WDT APB Clock Enable + WDT_: u1, + /// RTC APB Clock Enable + RTC_: u1, + /// EIC APB Clock Enable + EIC_: u1, + /// FREQM APB Clock Enable + FREQM_: u1, + /// SERCOM0 APB Clock Enable + SERCOM0_: u1, + /// SERCOM1 APB Clock Enable + SERCOM1_: u1, + /// TC0 APB Clock Enable + TC0_: u1, + /// TC1 APB Clock Enable + TC1_: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40000818 + /// APBB Mask + pub const APBBMASK = @intToPtr(*volatile Mmio(32, packed struct { + /// USB APB Clock Enable + USB_: u1, + /// DSU APB Clock Enable + DSU_: u1, + /// NVMCTRL APB Clock Enable + NVMCTRL_: u1, + reserved0: u1, + /// PORT APB Clock Enable + PORT_: u1, + reserved1: u1, + /// HMATRIX APB Clock Enable + HMATRIX_: u1, + /// EVSYS APB Clock Enable + EVSYS_: u1, + reserved2: u1, + /// SERCOM2 APB Clock Enable + SERCOM2_: u1, + /// SERCOM3 APB Clock Enable + SERCOM3_: u1, + /// TCC0 APB Clock Enable + TCC0_: u1, + /// TCC1 APB Clock Enable + TCC1_: u1, + /// TC2 APB Clock Enable + TC2_: u1, + /// TC3 APB Clock Enable + TC3_: u1, + reserved3: u1, + /// RAMECC APB Clock Enable + RAMECC_: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x18); + + /// address: 0x4000081c + /// APBC Mask + pub const APBCMASK = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// TCC2 APB Clock Enable + TCC2_: u1, + /// TCC3 APB Clock Enable + TCC3_: u1, + /// TC4 APB Clock Enable + TC4_: u1, + /// TC5 APB Clock Enable + TC5_: u1, + /// PDEC APB Clock Enable + PDEC_: u1, + /// AC APB Clock Enable + AC_: u1, + /// AES APB Clock Enable + AES_: u1, + /// TRNG APB Clock Enable + TRNG_: u1, + /// ICM APB Clock Enable + ICM_: u1, + reserved3: u1, + /// QSPI APB Clock Enable + QSPI_: u1, + /// CCL APB Clock Enable + CCL_: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x1c); + + /// address: 0x40000820 + /// APBD Mask + pub const APBDMASK = @intToPtr(*volatile Mmio(32, packed struct { + /// SERCOM4 APB Clock Enable + SERCOM4_: u1, + /// SERCOM5 APB Clock Enable + SERCOM5_: u1, + reserved0: u1, + reserved1: u1, + /// TCC4 APB Clock Enable + TCC4_: u1, + reserved2: u1, + reserved3: u1, + /// ADC0 APB Clock Enable + ADC0_: u1, + /// ADC1 APB Clock Enable + ADC1_: u1, + /// DAC APB Clock Enable + DAC_: u1, + /// I2S APB Clock Enable + I2S_: u1, + /// PCC APB Clock Enable + PCC_: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x20); + }; + + /// Non-Volatile Memory Controller + pub const NVMCTRL = struct { + pub const base_address = 0x41004000; + pub const version = "U24091.0.0"; + + /// address: 0x41004000 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(16, packed struct { + reserved0: u1, + reserved1: u1, + /// Auto Wait State Enable + AUTOWS: u1, + /// Suspend Enable + SUSPEN: u1, + /// Write Mode + WMODE: u2, + /// Power Reduction Mode during Sleep + PRM: u2, + /// NVM Read Wait States + RWS: u4, + /// Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated + AHBNS0: u1, + /// Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated + AHBNS1: u1, + /// AHB0 Cache Disable + CACHEDIS0: u1, + /// AHB1 Cache Disable + CACHEDIS1: u1, + }), base_address + 0x0); + + /// address: 0x41004004 + /// Control B + pub const CTRLB = @intToPtr(*volatile Mmio(16, packed struct { + /// Command + CMD: u7, + reserved0: u1, + /// Command Execution + CMDEX: u8, + }), base_address + 0x4); + + /// address: 0x41004008 + /// NVM Parameter + pub const PARAM = @intToPtr(*volatile Mmio(32, packed struct { + /// NVM Pages + NVMP: u16, + /// Page Size + PSZ: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// SmartEEPROM Supported + SEE: u1, + }), base_address + 0x8); + + /// address: 0x4100400c + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Done Interrupt Clear + DONE: u1, + /// Address Error + ADDRE: u1, + /// Programming Error Interrupt Clear + PROGE: u1, + /// Lock Error Interrupt Clear + LOCKE: u1, + /// ECC Single Error Interrupt Clear + ECCSE: u1, + /// ECC Dual Error Interrupt Clear + ECCDE: u1, + /// NVM Error Interrupt Clear + NVME: u1, + /// Suspended Write Or Erase Interrupt Clear + SUSP: u1, + /// Active SEES Full Interrupt Clear + SEESFULL: u1, + /// Active SEES Overflow Interrupt Clear + SEESOVF: u1, + /// SEE Write Completed Interrupt Clear + SEEWRC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0xc); + + /// address: 0x4100400e + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Done Interrupt Enable + DONE: u1, + /// Address Error Interrupt Enable + ADDRE: u1, + /// Programming Error Interrupt Enable + PROGE: u1, + /// Lock Error Interrupt Enable + LOCKE: u1, + /// ECC Single Error Interrupt Enable + ECCSE: u1, + /// ECC Dual Error Interrupt Enable + ECCDE: u1, + /// NVM Error Interrupt Enable + NVME: u1, + /// Suspended Write Or Erase Interrupt Enable + SUSP: u1, + /// Active SEES Full Interrupt Enable + SEESFULL: u1, + /// Active SEES Overflow Interrupt Enable + SEESOVF: u1, + /// SEE Write Completed Interrupt Enable + SEEWRC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0xe); + + /// address: 0x41004010 + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Done + DONE: u1, + /// Address Error + ADDRE: u1, + /// Programming Error + PROGE: u1, + /// Lock Error + LOCKE: u1, + /// ECC Single Error + ECCSE: u1, + /// ECC Dual Error + ECCDE: u1, + /// NVM Error + NVME: u1, + /// Suspended Write Or Erase Operation + SUSP: u1, + /// Active SEES Full + SEESFULL: u1, + /// Active SEES Overflow + SEESOVF: u1, + /// SEE Write Completed + SEEWRC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x10); + + /// address: 0x41004012 + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(16, packed struct { + /// Ready to accept a command + READY: u1, + /// Power Reduction Mode + PRM: u1, + /// NVM Page Buffer Active Loading + LOAD: u1, + /// NVM Write Or Erase Operation Is Suspended + SUSP: u1, + /// BANKA First + AFIRST: u1, + /// Boot Loader Protection Disable + BPDIS: u1, + reserved0: u1, + reserved1: u1, + /// Boot Loader Protection Size + BOOTPROT: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x12); + + /// address: 0x41004014 + /// Address + pub const ADDR = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x14); + + /// address: 0x41004018 + /// Lock Section + pub const RUNLOCK = @intToPtr(*volatile u32, base_address + 0x18); + + /// address: 0x4100401c + /// Page Buffer Load Data x + pub const PBLDATA = @intToPtr(*volatile [2]Mmio(32, packed struct { + /// Page Buffer Data + DATA: u32, + }), base_address + 0x1c); + + /// address: 0x41004024 + /// ECC Error Status Register + pub const ECCERR = @intToPtr(*volatile Mmio(32, packed struct { + /// Error Address + ADDR: u24, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Low Double-Word Error Type + TYPEL: u2, + /// High Double-Word Error Type + TYPEH: u2, + }), base_address + 0x24); + + /// address: 0x41004028 + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debugger ECC Read Disable + ECCDIS: u1, + /// Debugger ECC Error Tracking Mode + ECCELOG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x28); + + /// address: 0x4100402a + /// SmartEEPROM Configuration Register + pub const SEECFG = @intToPtr(*volatile Mmio(8, packed struct { + /// Write Mode + WMODE: u1, + /// Automatic Page Reallocation Disable + APRDIS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x2a); + + /// address: 0x4100402c + /// SmartEEPROM Status Register + pub const SEESTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Active SmartEEPROM Sector + ASEES: u1, + /// Page Buffer Loaded + LOAD: u1, + /// Busy + BUSY: u1, + /// SmartEEPROM Write Access Is Locked + LOCK: u1, + /// SmartEEPROM Write Access To Register Address Space Is Locked + RLOCK: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Blocks Number In a Sector + SBLK: u4, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// SmartEEPROM Page Size + PSZ: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x2c); + }; + + /// Oscillators Control + pub const OSCCTRL = struct { + pub const base_address = 0x40001000; + pub const version = "U24011.0.0"; + + /// address: 0x40001000 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Clock 0 Failure Detector Event Output Enable + CFDEO0: u1, + /// Clock 1 Failure Detector Event Output Enable + CFDEO1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x0); + + /// address: 0x40001004 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// XOSC 0 Ready Interrupt Enable + XOSCRDY0: u1, + /// XOSC 1 Ready Interrupt Enable + XOSCRDY1: u1, + /// XOSC 0 Clock Failure Detector Interrupt Enable + XOSCFAIL0: u1, + /// XOSC 1 Clock Failure Detector Interrupt Enable + XOSCFAIL1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DFLL Ready Interrupt Enable + DFLLRDY: u1, + /// DFLL Out Of Bounds Interrupt Enable + DFLLOOB: u1, + /// DFLL Lock Fine Interrupt Enable + DFLLLCKF: u1, + /// DFLL Lock Coarse Interrupt Enable + DFLLLCKC: u1, + /// DFLL Reference Clock Stopped Interrupt Enable + DFLLRCS: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// DPLL0 Lock Rise Interrupt Enable + DPLL0LCKR: u1, + /// DPLL0 Lock Fall Interrupt Enable + DPLL0LCKF: u1, + /// DPLL0 Lock Timeout Interrupt Enable + DPLL0LTO: u1, + /// DPLL0 Loop Divider Ratio Update Complete Interrupt Enable + DPLL0LDRTO: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// DPLL1 Lock Rise Interrupt Enable + DPLL1LCKR: u1, + /// DPLL1 Lock Fall Interrupt Enable + DPLL1LCKF: u1, + /// DPLL1 Lock Timeout Interrupt Enable + DPLL1LTO: u1, + /// DPLL1 Loop Divider Ratio Update Complete Interrupt Enable + DPLL1LDRTO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x4); + + /// address: 0x40001008 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { + /// XOSC 0 Ready Interrupt Enable + XOSCRDY0: u1, + /// XOSC 1 Ready Interrupt Enable + XOSCRDY1: u1, + /// XOSC 0 Clock Failure Detector Interrupt Enable + XOSCFAIL0: u1, + /// XOSC 1 Clock Failure Detector Interrupt Enable + XOSCFAIL1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DFLL Ready Interrupt Enable + DFLLRDY: u1, + /// DFLL Out Of Bounds Interrupt Enable + DFLLOOB: u1, + /// DFLL Lock Fine Interrupt Enable + DFLLLCKF: u1, + /// DFLL Lock Coarse Interrupt Enable + DFLLLCKC: u1, + /// DFLL Reference Clock Stopped Interrupt Enable + DFLLRCS: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// DPLL0 Lock Rise Interrupt Enable + DPLL0LCKR: u1, + /// DPLL0 Lock Fall Interrupt Enable + DPLL0LCKF: u1, + /// DPLL0 Lock Timeout Interrupt Enable + DPLL0LTO: u1, + /// DPLL0 Loop Divider Ratio Update Complete Interrupt Enable + DPLL0LDRTO: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// DPLL1 Lock Rise Interrupt Enable + DPLL1LCKR: u1, + /// DPLL1 Lock Fall Interrupt Enable + DPLL1LCKF: u1, + /// DPLL1 Lock Timeout Interrupt Enable + DPLL1LTO: u1, + /// DPLL1 Loop Divider Ratio Update Complete Interrupt Enable + DPLL1LDRTO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x8); + + /// address: 0x4000100c + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { + /// XOSC 0 Ready + XOSCRDY0: u1, + /// XOSC 1 Ready + XOSCRDY1: u1, + /// XOSC 0 Clock Failure Detector + XOSCFAIL0: u1, + /// XOSC 1 Clock Failure Detector + XOSCFAIL1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DFLL Ready + DFLLRDY: u1, + /// DFLL Out Of Bounds + DFLLOOB: u1, + /// DFLL Lock Fine + DFLLLCKF: u1, + /// DFLL Lock Coarse + DFLLLCKC: u1, + /// DFLL Reference Clock Stopped + DFLLRCS: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// DPLL0 Lock Rise + DPLL0LCKR: u1, + /// DPLL0 Lock Fall + DPLL0LCKF: u1, + /// DPLL0 Lock Timeout + DPLL0LTO: u1, + /// DPLL0 Loop Divider Ratio Update Complete + DPLL0LDRTO: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// DPLL1 Lock Rise + DPLL1LCKR: u1, + /// DPLL1 Lock Fall + DPLL1LCKF: u1, + /// DPLL1 Lock Timeout + DPLL1LTO: u1, + /// DPLL1 Loop Divider Ratio Update Complete + DPLL1LDRTO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xc); + + /// address: 0x40001010 + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// XOSC 0 Ready + XOSCRDY0: u1, + /// XOSC 1 Ready + XOSCRDY1: u1, + /// XOSC 0 Clock Failure Detector + XOSCFAIL0: u1, + /// XOSC 1 Clock Failure Detector + XOSCFAIL1: u1, + /// XOSC 0 Clock Switch + XOSCCKSW0: u1, + /// XOSC 1 Clock Switch + XOSCCKSW1: u1, + reserved0: u1, + reserved1: u1, + /// DFLL Ready + DFLLRDY: u1, + /// DFLL Out Of Bounds + DFLLOOB: u1, + /// DFLL Lock Fine + DFLLLCKF: u1, + /// DFLL Lock Coarse + DFLLLCKC: u1, + /// DFLL Reference Clock Stopped + DFLLRCS: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// DPLL0 Lock Rise + DPLL0LCKR: u1, + /// DPLL0 Lock Fall + DPLL0LCKF: u1, + /// DPLL0 Timeout + DPLL0TO: u1, + /// DPLL0 Loop Divider Ratio Update Complete + DPLL0LDRTO: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// DPLL1 Lock Rise + DPLL1LCKR: u1, + /// DPLL1 Lock Fall + DPLL1LCKF: u1, + /// DPLL1 Timeout + DPLL1TO: u1, + /// DPLL1 Loop Divider Ratio Update Complete + DPLL1LDRTO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x10); + + /// address: 0x40001014 + /// External Multipurpose Crystal Oscillator Control + pub const XOSCCTRL = @intToPtr(*volatile [2]Mmio(32, packed struct { + reserved0: u1, + /// Oscillator Enable + ENABLE: u1, + /// Crystal Oscillator Enable + XTALEN: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Run in Standby + RUNSTDBY: u1, + /// On Demand Control + ONDEMAND: u1, + /// Low Buffer Gain Enable + LOWBUFGAIN: u1, + /// Oscillator Current Reference + IPTAT: u2, + /// Oscillator Current Multiplier + IMULT: u4, + /// Automatic Loop Control Enable + ENALC: u1, + /// Clock Failure Detector Enable + CFDEN: u1, + /// Xosc Clock Switch Enable + SWBEN: u1, + reserved4: u1, + reserved5: u1, + /// Start-Up Time + STARTUP: u4, + /// Clock Failure Detector Prescaler + CFDPRESC: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x14); + + /// address: 0x4000101c + /// DFLL48M Control A + pub const DFLLCTRLA = @intToPtr(*volatile Mmio(8, packed struct { + reserved0: u1, + /// DFLL Enable + ENABLE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Run in Standby + RUNSTDBY: u1, + /// On Demand Control + ONDEMAND: u1, + }), base_address + 0x1c); + + /// address: 0x40001020 + /// DFLL48M Control B + pub const DFLLCTRLB = @intToPtr(*volatile Mmio(8, packed struct { + /// Operating Mode Selection + MODE: u1, + /// Stable DFLL Frequency + STABLE: u1, + /// Lose Lock After Wake + LLAW: u1, + /// USB Clock Recovery Mode + USBCRM: u1, + /// Chill Cycle Disable + CCDIS: u1, + /// Quick Lock Disable + QLDIS: u1, + /// Bypass Coarse Lock + BPLCKC: u1, + /// Wait Lock + WAITLOCK: u1, + }), base_address + 0x20); + + /// address: 0x40001024 + /// DFLL48M Value + pub const DFLLVAL = @intToPtr(*volatile Mmio(32, packed struct { + /// Fine Value + FINE: u8, + reserved0: u1, + reserved1: u1, + /// Coarse Value + COARSE: u6, + /// Multiplication Ratio Difference + DIFF: u16, + }), base_address + 0x24); + + /// address: 0x40001028 + /// DFLL48M Multiplier + pub const DFLLMUL = @intToPtr(*volatile Mmio(32, packed struct { + /// DFLL Multiply Factor + MUL: u16, + /// Fine Maximum Step + FSTEP: u8, + reserved0: u1, + reserved1: u1, + /// Coarse Maximum Step + CSTEP: u6, + }), base_address + 0x28); + + /// address: 0x4000102c + /// DFLL48M Synchronization + pub const DFLLSYNC = @intToPtr(*volatile Mmio(8, packed struct { + reserved0: u1, + /// ENABLE Synchronization Busy + ENABLE: u1, + /// DFLLCTRLB Synchronization Busy + DFLLCTRLB: u1, + /// DFLLVAL Synchronization Busy + DFLLVAL: u1, + /// DFLLMUL Synchronization Busy + DFLLMUL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x2c); + + pub const DPLL = @ptrCast(*volatile [2]packed struct { + /// DPLL Control A + DPLLCTRLA: Mmio(8, packed struct { + reserved0: u1, + /// DPLL Enable + ENABLE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Run in Standby + RUNSTDBY: u1, + /// On Demand Control + ONDEMAND: u1, + }), + + /// DPLL Ratio Control + DPLLRATIO: Mmio(32, packed struct { + /// Loop Divider Ratio + LDR: u13, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Loop Divider Ratio Fractional Part + LDRFRAC: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), + + /// DPLL Control B + DPLLCTRLB: Mmio(32, packed struct { + /// Proportional Integral Filter Selection + FILTER: u4, + /// Wake Up Fast + WUF: u1, + /// Reference Clock Selection + REFCLK: u3, + /// Lock Time + LTIME: u3, + /// Lock Bypass + LBYPASS: u1, + /// Sigma-Delta DCO Filter Selection + DCOFILTER: u3, + /// DCO Filter Enable + DCOEN: u1, + /// Clock Divider + DIV: u11, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), + + /// DPLL Synchronization Busy + DPLLSYNCBUSY: Mmio(32, packed struct { + reserved0: u1, + /// DPLL Enable Synchronization Status + ENABLE: u1, + /// DPLL Loop Divider Ratio Synchronization Status + DPLLRATIO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), + + /// DPLL Status + DPLLSTATUS: Mmio(32, packed struct { + /// DPLL Lock Status + LOCK: u1, + /// DPLL Clock Ready + CLKRDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), + }, base_address + 0x30); + }; + + /// 32kHz Oscillators Control + pub const OSC32KCTRL = struct { + pub const base_address = 0x40001400; + pub const version = "U24001.0.0"; + + /// address: 0x40001400 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// XOSC32K Ready Interrupt Enable + XOSC32KRDY: u1, + reserved0: u1, + /// XOSC32K Clock Failure Detector Interrupt Enable + XOSC32KFAIL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x0); + + /// address: 0x40001404 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { + /// XOSC32K Ready Interrupt Enable + XOSC32KRDY: u1, + reserved0: u1, + /// XOSC32K Clock Failure Detector Interrupt Enable + XOSC32KFAIL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x4); + + /// address: 0x40001408 + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { + /// XOSC32K Ready + XOSC32KRDY: u1, + reserved0: u1, + /// XOSC32K Clock Failure Detector + XOSC32KFAIL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x8); + + /// address: 0x4000140c + /// Power and Clocks Status + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// XOSC32K Ready + XOSC32KRDY: u1, + reserved0: u1, + /// XOSC32K Clock Failure Detector + XOSC32KFAIL: u1, + /// XOSC32K Clock switch + XOSC32KSW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0xc); + + /// address: 0x40001410 + /// RTC Clock Selection + pub const RTCCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// RTC Clock Selection + RTCSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x10); + + /// address: 0x40001414 + /// 32kHz External Crystal Oscillator (XOSC32K) Control + pub const XOSC32K = @intToPtr(*volatile Mmio(16, packed struct { + reserved0: u1, + /// Oscillator Enable + ENABLE: u1, + /// Crystal Oscillator Enable + XTALEN: u1, + /// 32kHz Output Enable + EN32K: u1, + /// 1kHz Output Enable + EN1K: u1, + reserved1: u1, + /// Run in Standby + RUNSTDBY: u1, + /// On Demand Control + ONDEMAND: u1, + /// Oscillator Start-Up Time + STARTUP: u3, + reserved2: u1, + /// Write Lock + WRTLOCK: u1, + /// Control Gain Mode + CGM: u2, + padding0: u1, + }), base_address + 0x14); + + /// address: 0x40001416 + /// Clock Failure Detector Control + pub const CFDCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Clock Failure Detector Enable + CFDEN: u1, + /// Clock Switch Back + SWBACK: u1, + /// Clock Failure Detector Prescaler + CFDPRESC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x16); + + /// address: 0x40001417 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Clock Failure Detector Event Output Enable + CFDEO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x17); + + /// address: 0x4000141c + /// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control + pub const OSCULP32K = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Enable Out 32k + EN32K: u1, + /// Enable Out 1k + EN1K: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Oscillator Calibration + CALIB: u6, + reserved6: u1, + /// Write Lock + WRTLOCK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + }; + + /// Peripheral Access Controller + pub const PAC = struct { + pub const base_address = 0x40000000; + pub const version = "U21201.2.0"; + + /// address: 0x40000000 + /// Write control + pub const WRCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral identifier + PERID: u16, + /// Peripheral access control key + KEY: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x0); + + /// address: 0x40000004 + /// Event control + pub const EVCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Peripheral acess error event output + ERREO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x4); + + /// address: 0x40000008 + /// Interrupt enable clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Peripheral access error interrupt disable + ERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x8); + + /// address: 0x40000009 + /// Interrupt enable set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Peripheral access error interrupt enable + ERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x9); + + /// address: 0x40000010 + /// Bridge interrupt flag status + pub const INTFLAGAHB = @intToPtr(*volatile Mmio(32, packed struct { + /// FLASH + FLASH_: u1, + /// FLASH_ALT + FLASH_ALT_: u1, + /// SEEPROM + SEEPROM_: u1, + /// RAMCM4S + RAMCM4S_: u1, + /// RAMPPPDSU + RAMPPPDSU_: u1, + /// RAMDMAWR + RAMDMAWR_: u1, + /// RAMDMACICM + RAMDMACICM_: u1, + /// HPB0 + HPB0_: u1, + /// HPB1 + HPB1_: u1, + /// HPB2 + HPB2_: u1, + /// HPB3 + HPB3_: u1, + /// PUKCC + PUKCC_: u1, + /// SDHC0 + SDHC0_: u1, + reserved0: u1, + /// QSPI + QSPI_: u1, + /// BKUPRAM + BKUPRAM_: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40000014 + /// Peripheral interrupt flag status - Bridge A + pub const INTFLAGA = @intToPtr(*volatile Mmio(32, packed struct { + /// PAC + PAC_: u1, + /// PM + PM_: u1, + /// MCLK + MCLK_: u1, + /// RSTC + RSTC_: u1, + /// OSCCTRL + OSCCTRL_: u1, + /// OSC32KCTRL + OSC32KCTRL_: u1, + /// SUPC + SUPC_: u1, + /// GCLK + GCLK_: u1, + /// WDT + WDT_: u1, + /// RTC + RTC_: u1, + /// EIC + EIC_: u1, + /// FREQM + FREQM_: u1, + /// SERCOM0 + SERCOM0_: u1, + /// SERCOM1 + SERCOM1_: u1, + /// TC0 + TC0_: u1, + /// TC1 + TC1_: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40000018 + /// Peripheral interrupt flag status - Bridge B + pub const INTFLAGB = @intToPtr(*volatile Mmio(32, packed struct { + /// USB + USB_: u1, + /// DSU + DSU_: u1, + /// NVMCTRL + NVMCTRL_: u1, + /// CMCC + CMCC_: u1, + /// PORT + PORT_: u1, + /// DMAC + DMAC_: u1, + /// HMATRIX + HMATRIX_: u1, + /// EVSYS + EVSYS_: u1, + reserved0: u1, + /// SERCOM2 + SERCOM2_: u1, + /// SERCOM3 + SERCOM3_: u1, + /// TCC0 + TCC0_: u1, + /// TCC1 + TCC1_: u1, + /// TC2 + TC2_: u1, + /// TC3 + TC3_: u1, + reserved1: u1, + /// RAMECC + RAMECC_: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x18); + + /// address: 0x4000001c + /// Peripheral interrupt flag status - Bridge C + pub const INTFLAGC = @intToPtr(*volatile Mmio(32, packed struct { + /// CAN0 + CAN0_: u1, + /// CAN1 + CAN1_: u1, + reserved0: u1, + /// TCC2 + TCC2_: u1, + /// TCC3 + TCC3_: u1, + /// TC4 + TC4_: u1, + /// TC5 + TC5_: u1, + /// PDEC + PDEC_: u1, + /// AC + AC_: u1, + /// AES + AES_: u1, + /// TRNG + TRNG_: u1, + /// ICM + ICM_: u1, + /// PUKCC + PUKCC_: u1, + /// QSPI + QSPI_: u1, + /// CCL + CCL_: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x1c); + + /// address: 0x40000020 + /// Peripheral interrupt flag status - Bridge D + pub const INTFLAGD = @intToPtr(*volatile Mmio(32, packed struct { + /// SERCOM4 + SERCOM4_: u1, + /// SERCOM5 + SERCOM5_: u1, + reserved0: u1, + reserved1: u1, + /// TCC4 + TCC4_: u1, + reserved2: u1, + reserved3: u1, + /// ADC0 + ADC0_: u1, + /// ADC1 + ADC1_: u1, + /// DAC + DAC_: u1, + /// I2S + I2S_: u1, + /// PCC + PCC_: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x20); + + /// address: 0x40000034 + /// Peripheral write protection status - Bridge A + pub const STATUSA = @intToPtr(*volatile Mmio(32, packed struct { + /// PAC APB Protect Enable + PAC_: u1, + /// PM APB Protect Enable + PM_: u1, + /// MCLK APB Protect Enable + MCLK_: u1, + /// RSTC APB Protect Enable + RSTC_: u1, + /// OSCCTRL APB Protect Enable + OSCCTRL_: u1, + /// OSC32KCTRL APB Protect Enable + OSC32KCTRL_: u1, + /// SUPC APB Protect Enable + SUPC_: u1, + /// GCLK APB Protect Enable + GCLK_: u1, + /// WDT APB Protect Enable + WDT_: u1, + /// RTC APB Protect Enable + RTC_: u1, + /// EIC APB Protect Enable + EIC_: u1, + /// FREQM APB Protect Enable + FREQM_: u1, + /// SERCOM0 APB Protect Enable + SERCOM0_: u1, + /// SERCOM1 APB Protect Enable + SERCOM1_: u1, + /// TC0 APB Protect Enable + TC0_: u1, + /// TC1 APB Protect Enable + TC1_: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x34); + + /// address: 0x40000038 + /// Peripheral write protection status - Bridge B + pub const STATUSB = @intToPtr(*volatile Mmio(32, packed struct { + /// USB APB Protect Enable + USB_: u1, + /// DSU APB Protect Enable + DSU_: u1, + /// NVMCTRL APB Protect Enable + NVMCTRL_: u1, + /// CMCC APB Protect Enable + CMCC_: u1, + /// PORT APB Protect Enable + PORT_: u1, + /// DMAC APB Protect Enable + DMAC_: u1, + /// HMATRIX APB Protect Enable + HMATRIX_: u1, + /// EVSYS APB Protect Enable + EVSYS_: u1, + reserved0: u1, + /// SERCOM2 APB Protect Enable + SERCOM2_: u1, + /// SERCOM3 APB Protect Enable + SERCOM3_: u1, + /// TCC0 APB Protect Enable + TCC0_: u1, + /// TCC1 APB Protect Enable + TCC1_: u1, + /// TC2 APB Protect Enable + TC2_: u1, + /// TC3 APB Protect Enable + TC3_: u1, + reserved1: u1, + /// RAMECC APB Protect Enable + RAMECC_: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x38); + + /// address: 0x4000003c + /// Peripheral write protection status - Bridge C + pub const STATUSC = @intToPtr(*volatile Mmio(32, packed struct { + /// CAN0 APB Protect Enable + CAN0_: u1, + /// CAN1 APB Protect Enable + CAN1_: u1, + reserved0: u1, + /// TCC2 APB Protect Enable + TCC2_: u1, + /// TCC3 APB Protect Enable + TCC3_: u1, + /// TC4 APB Protect Enable + TC4_: u1, + /// TC5 APB Protect Enable + TC5_: u1, + /// PDEC APB Protect Enable + PDEC_: u1, + /// AC APB Protect Enable + AC_: u1, + /// AES APB Protect Enable + AES_: u1, + /// TRNG APB Protect Enable + TRNG_: u1, + /// ICM APB Protect Enable + ICM_: u1, + /// PUKCC APB Protect Enable + PUKCC_: u1, + /// QSPI APB Protect Enable + QSPI_: u1, + /// CCL APB Protect Enable + CCL_: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x3c); + + /// address: 0x40000040 + /// Peripheral write protection status - Bridge D + pub const STATUSD = @intToPtr(*volatile Mmio(32, packed struct { + /// SERCOM4 APB Protect Enable + SERCOM4_: u1, + /// SERCOM5 APB Protect Enable + SERCOM5_: u1, + reserved0: u1, + reserved1: u1, + /// TCC4 APB Protect Enable + TCC4_: u1, + reserved2: u1, + reserved3: u1, + /// ADC0 APB Protect Enable + ADC0_: u1, + /// ADC1 APB Protect Enable + ADC1_: u1, + /// DAC APB Protect Enable + DAC_: u1, + /// I2S APB Protect Enable + I2S_: u1, + /// PCC APB Protect Enable + PCC_: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x40); + }; + + /// Parallel Capture Controller + pub const PCC = struct { + pub const base_address = 0x43002c00; + pub const version = "U20171.1.0"; + + /// address: 0x43002c00 + /// Mode Register + pub const MR = @intToPtr(*volatile Mmio(32, packed struct { + /// Parallel Capture Enable + PCEN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Data size + DSIZE: u2, + reserved3: u1, + reserved4: u1, + /// Scale data + SCALE: u1, + /// Always Sampling + ALWYS: u1, + /// Half Sampling + HALFS: u1, + /// First sample + FRSTS: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Input Data Size + ISIZE: u3, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + /// Clear If Disabled + CID: u2, + }), base_address + 0x0); + + /// address: 0x43002c04 + /// Interrupt Enable Register + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { + /// Data Ready Interrupt Enable + DRDY: u1, + /// Overrun Error Interrupt Enable + OVRE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x4); + + /// address: 0x43002c08 + /// Interrupt Disable Register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Data Ready Interrupt Disable + DRDY: u1, + /// Overrun Error Interrupt Disable + OVRE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x8); + + /// address: 0x43002c0c + /// Interrupt Mask Register + pub const IMR = @intToPtr(*volatile Mmio(32, packed struct { + /// Data Ready Interrupt Mask + DRDY: u1, + /// Overrun Error Interrupt Mask + OVRE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + + /// address: 0x43002c10 + /// Interrupt Status Register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Data Ready Interrupt Status + DRDY: u1, + /// Overrun Error Interrupt Status + OVRE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x10); + + /// address: 0x43002c14 + /// Reception Holding Register + pub const RHR = @intToPtr(*volatile Mmio(32, packed struct { + /// Reception Data + RDATA: u32, + }), base_address + 0x14); + + /// address: 0x43002ce0 + /// Write Protection Mode Register + pub const WPMR = @intToPtr(*volatile Mmio(32, packed struct { + /// Write Protection Enable + WPEN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Write Protection Key + WPKEY: u24, + }), base_address + 0xe0); + + /// address: 0x43002ce4 + /// Write Protection Status Register + pub const WPSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Write Protection Violation Source + WPVS: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Write Protection Violation Status + WPVSRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0xe4); + }; + + /// Quadrature Decodeur + pub const PDEC = struct { + pub const base_address = 0x42001c00; + pub const version = "U22631.0.0"; + + /// address: 0x42001c00 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Operation Mode + MODE: u2, + reserved0: u1, + reserved1: u1, + /// Run in Standby + RUNSTDBY: u1, + reserved2: u1, + /// PDEC Configuration + CONF: u3, + /// Auto Lock + ALOCK: u1, + reserved3: u1, + reserved4: u1, + /// PDEC Phase A and B Swap + SWAP: u1, + /// Period Enable + PEREN: u1, + /// PDEC Input From Pin 0 Enable + PINEN0: u1, + /// PDEC Input From Pin 1 Enable + PINEN1: u1, + /// PDEC Input From Pin 2 Enable + PINEN2: u1, + reserved5: u1, + /// IO Pin 0 Invert Enable + PINVEN0: u1, + /// IO Pin 1 Invert Enable + PINVEN1: u1, + /// IO Pin 2 Invert Enable + PINVEN2: u1, + reserved6: u1, + /// Angular Counter Length + ANGULAR: u3, + reserved7: u1, + /// Maximum Consecutive Missing Pulses + MAXCMP: u4, + }), base_address + 0x0); + + /// address: 0x42001c04 + /// Control B Clear + pub const CTRLBCLR = @intToPtr(*volatile Mmio(8, packed struct { + reserved0: u1, + /// Lock Update + LUPD: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Command + CMD: u3, + }), base_address + 0x4); + + /// address: 0x42001c05 + /// Control B Set + pub const CTRLBSET = @intToPtr(*volatile Mmio(8, packed struct { + reserved0: u1, + /// Lock Update + LUPD: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Command + CMD: u3, + }), base_address + 0x5); + + /// address: 0x42001c06 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(16, packed struct { + /// Event Action + EVACT: u2, + /// Inverted Event Input Enable + EVINV: u3, + /// Event Input Enable + EVEI: u3, + /// Overflow/Underflow Output Event Enable + OVFEO: u1, + /// Error Output Event Enable + ERREO: u1, + /// Direction Output Event Enable + DIREO: u1, + /// Velocity Output Event Enable + VLCEO: u1, + /// Match Channel 0 Event Output Enable + MCEO0: u1, + /// Match Channel 1 Event Output Enable + MCEO1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x6); + + /// address: 0x42001c08 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Overflow/Underflow Interrupt Disable + OVF: u1, + /// Error Interrupt Disable + ERR: u1, + /// Direction Interrupt Disable + DIR: u1, + /// Velocity Interrupt Disable + VLC: u1, + /// Channel 0 Compare Match Disable + MC0: u1, + /// Channel 1 Compare Match Disable + MC1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x8); + + /// address: 0x42001c09 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Overflow/Underflow Interrupt Enable + OVF: u1, + /// Error Interrupt Enable + ERR: u1, + /// Direction Interrupt Enable + DIR: u1, + /// Velocity Interrupt Enable + VLC: u1, + /// Channel 0 Compare Match Enable + MC0: u1, + /// Channel 1 Compare Match Enable + MC1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x9); + + /// address: 0x42001c0a + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Overflow/Underflow + OVF: u1, + /// Error + ERR: u1, + /// Direction Change + DIR: u1, + /// Velocity + VLC: u1, + /// Channel 0 Compare Match + MC0: u1, + /// Channel 1 Compare Match + MC1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0xa); + + /// address: 0x42001c0c + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(16, packed struct { + /// Quadrature Error Flag + QERR: u1, + /// Index Error Flag + IDXERR: u1, + /// Missing Pulse Error flag + MPERR: u1, + reserved0: u1, + /// Window Error Flag + WINERR: u1, + /// Hall Error Flag + HERR: u1, + /// Stop + STOP: u1, + /// Direction Status Flag + DIR: u1, + /// Prescaler Buffer Valid + PRESCBUFV: u1, + /// Filter Buffer Valid + FILTERBUFV: u1, + reserved1: u1, + reserved2: u1, + /// Compare Channel 0 Buffer Valid + CCBUFV0: u1, + /// Compare Channel 1 Buffer Valid + CCBUFV1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0xc); + + /// address: 0x42001c0f + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Run Mode + DBGRUN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0xf); + + /// address: 0x42001c10 + /// Synchronization Status + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset Synchronization Busy + SWRST: u1, + /// Enable Synchronization Busy + ENABLE: u1, + /// Control B Synchronization Busy + CTRLB: u1, + /// Status Synchronization Busy + STATUS: u1, + /// Prescaler Synchronization Busy + PRESC: u1, + /// Filter Synchronization Busy + FILTER: u1, + /// Count Synchronization Busy + COUNT: u1, + /// Compare Channel 0 Synchronization Busy + CC0: u1, + /// Compare Channel 1 Synchronization Busy + CC1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x10); + + /// address: 0x42001c14 + /// Prescaler Value + pub const PRESC = @intToPtr(*volatile MmioInt(8, u4), base_address + 0x14); + + /// address: 0x42001c15 + /// Filter Value + pub const FILTER = @intToPtr(*volatile u8, base_address + 0x15); + + /// address: 0x42001c18 + /// Prescaler Buffer Value + pub const PRESCBUF = @intToPtr(*volatile MmioInt(8, u4), base_address + 0x18); + + /// address: 0x42001c19 + /// Filter Buffer Value + pub const FILTERBUF = @intToPtr(*volatile u8, base_address + 0x19); + + /// address: 0x42001c1c + /// Counter Value + pub const COUNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x1c); + + /// address: 0x42001c20 + /// Channel n Compare Value + pub const CC = @intToPtr(*volatile [2]MmioInt(32, u16), base_address + 0x20); + + /// address: 0x42001c30 + /// Channel Compare Buffer Value + pub const CCBUF = @intToPtr(*volatile [2]MmioInt(32, u16), base_address + 0x30); + }; + + /// Power Manager + pub const PM = struct { + pub const base_address = 0x40000400; + pub const version = "U24061.0.0"; + + /// address: 0x40000400 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { + reserved0: u1, + reserved1: u1, + /// I/O Retention + IORET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x0); + + /// address: 0x40000401 + /// Sleep Configuration + pub const SLEEPCFG = @intToPtr(*volatile Mmio(8, packed struct { + /// Sleep Mode + SLEEPMODE: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x1); + + /// address: 0x40000404 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Sleep Mode Entry Ready Enable + SLEEPRDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x4); + + /// address: 0x40000405 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Sleep Mode Entry Ready Enable + SLEEPRDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x5); + + /// address: 0x40000406 + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Sleep Mode Entry Ready + SLEEPRDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x6); + + /// address: 0x40000408 + /// Standby Configuration + pub const STDBYCFG = @intToPtr(*volatile Mmio(8, packed struct { + /// Ram Configuration + RAMCFG: u2, + reserved0: u1, + reserved1: u1, + /// Fast Wakeup + FASTWKUP: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x8); + + /// address: 0x40000409 + /// Hibernate Configuration + pub const HIBCFG = @intToPtr(*volatile Mmio(8, packed struct { + /// Ram Configuration + RAMCFG: u2, + /// Backup Ram Configuration + BRAMCFG: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x9); + + /// address: 0x4000040a + /// Backup Configuration + pub const BKUPCFG = @intToPtr(*volatile Mmio(8, packed struct { + /// Ram Configuration + BRAMCFG: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xa); + + /// address: 0x40000412 + /// Power Switch Acknowledge Delay + pub const PWSAKDLY = @intToPtr(*volatile Mmio(8, packed struct { + /// Delay Value + DLYVAL: u7, + /// Ignore Acknowledge + IGNACK: u1, + }), base_address + 0x12); + }; + + /// Port Module + pub const PORT = struct { + pub const base_address = @intToPtr([*]u8, 0x41008000); + pub const version = "U22102.2.0"; + + pub const GROUP = @ptrCast(*volatile [2]packed struct { + /// Data Direction + DIR: u32, + + /// Data Direction Clear + DIRCLR: u32, + + /// Data Direction Set + DIRSET: u32, + + /// Data Direction Toggle + DIRTGL: u32, + + /// Data Output Value + OUT: u32, + + /// Data Output Value Clear + OUTCLR: u32, + + /// Data Output Value Set + OUTSET: u32, + + /// Data Output Value Toggle + OUTTGL: u32, + + /// Data Input Value + IN: u32, + + /// Control + CTRL: Mmio(32, packed struct { + /// Input Sampling Mode + SAMPLING: u32, + }), + + /// Write Configuration + WRCONFIG: Mmio(32, packed struct { + /// Pin Mask for Multiple Pin Configuration + PINMASK: u16, + /// Peripheral Multiplexer Enable + PMUXEN: u1, + /// Input Enable + INEN: u1, + /// Pull Enable + PULLEN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Output Driver Strength Selection + DRVSTR: u1, + reserved3: u1, + /// Peripheral Multiplexing + PMUX: u4, + /// Write PMUX + WRPMUX: u1, + reserved4: u1, + /// Write PINCFG + WRPINCFG: u1, + /// Half-Word Select + HWSEL: u1, + }), + + /// Event Input Control + EVCTRL: Mmio(32, packed struct { + /// PORT Event Pin Identifier 0 + PID0: u5, + /// PORT Event Action 0 + EVACT0: u2, + /// PORT Event Input Enable 0 + PORTEI0: u1, + /// PORT Event Pin Identifier 1 + PID1: u5, + /// PORT Event Action 1 + EVACT1: u2, + /// PORT Event Input Enable 1 + PORTEI1: u1, + /// PORT Event Pin Identifier 2 + PID2: u5, + /// PORT Event Action 2 + EVACT2: u2, + /// PORT Event Input Enable 2 + PORTEI2: u1, + /// PORT Event Pin Identifier 3 + PID3: u5, + /// PORT Event Action 3 + EVACT3: u2, + /// PORT Event Input Enable 3 + PORTEI3: u1, + }), + + /// Peripheral Multiplexing + PMUX: [16]Mmio(8, packed struct { + /// Peripheral Multiplexing for Even-Numbered Pin + PMUXE: u4, + /// Peripheral Multiplexing for Odd-Numbered Pin + PMUXO: u4, + }), + + /// Pin Configuration + PINCFG: [32]Mmio(8, packed struct { + /// Peripheral Multiplexer Enable + PMUXEN: u1, + /// Input Enable + INEN: u1, + /// Pull Enable + PULLEN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Output Driver Strength Selection + DRVSTR: u1, + padding0: u1, + }), + padding0: u32, + padding1: u32, + padding2: u32, + padding3: u32, + padding4: u32, + padding5: u32, + padding6: u32, + padding7: u32, + //padding8: u32, + //padding9: u32, + //padding10: u32, + //padding11: u32, + //padding12: u32, + //padding13: u32, + //padding14: u32, + //padding15: u32, + //padding16: u32, + //padding17: u32, + //padding18: u32, + }, base_address); + }; + + /// Quad SPI interface + pub const QSPI = struct { + pub const base_address = 0x42003400; + pub const version = "U20081.6.3"; + + /// address: 0x42003400 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// Last Transfer + LASTXFER: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x0); + + /// address: 0x42003404 + /// Control B + pub const CTRLB = @intToPtr(*volatile Mmio(32, packed struct { + /// Serial Memory Mode + MODE: u1, + /// Local Loopback Enable + LOOPEN: u1, + /// Wait Data Read Before Transfer + WDRBT: u1, + /// Serial Memory reg + SMEMREG: u1, + /// Chip Select Mode + CSMODE: u2, + reserved0: u1, + reserved1: u1, + /// Data Length + DATALEN: u4, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Delay Between Consecutive Transfers + DLYBCT: u8, + /// Minimum Inactive CS Delay + DLYCS: u8, + }), base_address + 0x4); + + /// address: 0x42003408 + /// Baud Rate + pub const BAUD = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock Polarity + CPOL: u1, + /// Clock Phase + CPHA: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Serial Clock Baud Rate + BAUD: u8, + /// Delay Before SCK + DLYBS: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x8); + + /// address: 0x4200340c + /// Receive Data + pub const RXDATA = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive Data + DATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x42003410 + /// Transmit Data + pub const TXDATA = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit Data + DATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x42003414 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive Data Register Full Interrupt Disable + RXC: u1, + /// Transmit Data Register Empty Interrupt Disable + DRE: u1, + /// Transmission Complete Interrupt Disable + TXC: u1, + /// Overrun Error Interrupt Disable + ERROR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Chip Select Rise Interrupt Disable + CSRISE: u1, + reserved4: u1, + /// Instruction End Interrupt Disable + INSTREND: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x14); + + /// address: 0x42003418 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive Data Register Full Interrupt Enable + RXC: u1, + /// Transmit Data Register Empty Interrupt Enable + DRE: u1, + /// Transmission Complete Interrupt Enable + TXC: u1, + /// Overrun Error Interrupt Enable + ERROR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Chip Select Rise Interrupt Enable + CSRISE: u1, + reserved4: u1, + /// Instruction End Interrupt Enable + INSTREND: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x18); + + /// address: 0x4200341c + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive Data Register Full + RXC: u1, + /// Transmit Data Register Empty + DRE: u1, + /// Transmission Complete + TXC: u1, + /// Overrun Error + ERROR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Chip Select Rise + CSRISE: u1, + reserved4: u1, + /// Instruction End + INSTREND: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1c); + + /// address: 0x42003420 + /// Status Register + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Enable + ENABLE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Chip Select + CSSTATUS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + + /// address: 0x42003430 + /// Instruction Address + pub const INSTRADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Instruction Address + ADDR: u32, + }), base_address + 0x30); + + /// address: 0x42003434 + /// Instruction Code + pub const INSTRCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Instruction Code + INSTR: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Option Code + OPTCODE: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x42003438 + /// Instruction Frame + pub const INSTRFRAME = @intToPtr(*volatile Mmio(32, packed struct { + /// Instruction Code, Address, Option Code and Data Width + WIDTH: u3, + reserved0: u1, + /// Instruction Enable + INSTREN: u1, + /// Address Enable + ADDREN: u1, + /// Option Enable + OPTCODEEN: u1, + /// Data Enable + DATAEN: u1, + /// Option Code Length + OPTCODELEN: u2, + /// Address Length + ADDRLEN: u1, + reserved1: u1, + /// Data Transfer Type + TFRTYPE: u2, + /// Continuous Read Mode + CRMODE: u1, + /// Double Data Rate Enable + DDREN: u1, + /// Dummy Cycles Length + DUMMYLEN: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x38); + + /// address: 0x42003440 + /// Scrambling Mode + pub const SCRAMBCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Scrambling/Unscrambling Enable + ENABLE: u1, + /// Scrambling/Unscrambling Random Value Disable + RANDOMDIS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x40); + + /// address: 0x42003444 + /// Scrambling Key + pub const SCRAMBKEY = @intToPtr(*volatile Mmio(32, packed struct { + /// Scrambling User Key + KEY: u32, + }), base_address + 0x44); + }; + + /// RAM ECC + pub const RAMECC = struct { + pub const base_address = 0x41020000; + pub const version = "U22681.0.0"; + + /// address: 0x41020000 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Single Bit ECC Error Interrupt Enable Clear + SINGLEE: u1, + /// Dual Bit ECC Error Interrupt Enable Clear + DUALE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x0); + + /// address: 0x41020001 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Single Bit ECC Error Interrupt Enable Set + SINGLEE: u1, + /// Dual Bit ECC Error Interrupt Enable Set + DUALE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x1); + + /// address: 0x41020002 + /// Interrupt Flag + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Single Bit ECC Error Interrupt + SINGLEE: u1, + /// Dual Bit ECC Error Interrupt + DUALE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x2); + + /// address: 0x41020003 + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { + /// ECC Disable + ECCDIS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x3); + + /// address: 0x41020004 + /// Error Address + pub const ERRADDR = @intToPtr(*volatile MmioInt(32, u17), base_address + 0x4); + + /// address: 0x4102000f + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// ECC Disable + ECCDIS: u1, + /// ECC Error Log + ECCELOG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xf); + }; + + /// Reset Controller + pub const RSTC = struct { + pub const base_address = 0x40000c00; + pub const version = "U22394.0.0"; + + /// address: 0x40000c00 + /// Reset Cause + pub const RCAUSE = @intToPtr(*volatile Mmio(8, packed struct { + /// Power On Reset + POR: u1, + /// Brown Out CORE Detector Reset + BODCORE: u1, + /// Brown Out VDD Detector Reset + BODVDD: u1, + /// NVM Reset + NVM: u1, + /// External Reset + EXT: u1, + /// Watchdog Reset + WDT: u1, + /// System Reset Request + SYST: u1, + /// Backup Reset + BACKUP: u1, + }), base_address + 0x0); + + /// address: 0x40000c02 + /// Backup Exit Source + pub const BKUPEXIT = @intToPtr(*volatile Mmio(8, packed struct { + reserved0: u1, + /// Real Timer Counter Interrupt + RTC: u1, + /// Battery Backup Power Switch + BBPS: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Hibernate + HIB: u1, + }), base_address + 0x2); + }; + + /// Real-Time Counter + pub const RTC = struct { + pub const base_address = 0x40002400; + pub const version = "U22502.1.0"; + + /// 32-bit Counter with Single 32-bit Compare + pub const MODE0 = struct { + /// address: 0x40002400 + /// MODE0 Control A + pub const CTRLA = @intToPtr(*volatile Mmio(16, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Operating Mode + MODE: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Clear on Match + MATCHCLR: u1, + /// Prescaler + PRESCALER: u4, + reserved3: u1, + /// BKUP Registers Reset On Tamper Enable + BKTRST: u1, + /// GP Registers Reset On Tamper Enable + GPTRST: u1, + /// Count Read Synchronization Enable + COUNTSYNC: u1, + }), base_address + 0x0); + + /// address: 0x40002402 + /// MODE0 Control B + pub const CTRLB = @intToPtr(*volatile Mmio(16, packed struct { + /// General Purpose 0 Enable + GP0EN: u1, + /// General Purpose 2 Enable + GP2EN: u1, + reserved0: u1, + reserved1: u1, + /// Debouncer Majority Enable + DEBMAJ: u1, + /// Debouncer Asynchronous Enable + DEBASYNC: u1, + /// RTC Output Enable + RTCOUT: u1, + /// DMA Enable + DMAEN: u1, + /// Debounce Freqnuency + DEBF: u3, + reserved2: u1, + /// Active Layer Freqnuency + ACTF: u3, + padding0: u1, + }), base_address + 0x2); + + /// address: 0x40002404 + /// MODE0 Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Periodic Interval 0 Event Output Enable + PEREO0: u1, + /// Periodic Interval 1 Event Output Enable + PEREO1: u1, + /// Periodic Interval 2 Event Output Enable + PEREO2: u1, + /// Periodic Interval 3 Event Output Enable + PEREO3: u1, + /// Periodic Interval 4 Event Output Enable + PEREO4: u1, + /// Periodic Interval 5 Event Output Enable + PEREO5: u1, + /// Periodic Interval 6 Event Output Enable + PEREO6: u1, + /// Periodic Interval 7 Event Output Enable + PEREO7: u1, + /// Compare 0 Event Output Enable + CMPEO0: u1, + /// Compare 1 Event Output Enable + CMPEO1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Tamper Event Output Enable + TAMPEREO: u1, + /// Overflow Event Output Enable + OVFEO: u1, + /// Tamper Event Input Enable + TAMPEVEI: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x4); + + /// address: 0x40002408 + /// MODE0 Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(16, packed struct { + /// Periodic Interval 0 Interrupt Enable + PER0: u1, + /// Periodic Interval 1 Interrupt Enable + PER1: u1, + /// Periodic Interval 2 Interrupt Enable + PER2: u1, + /// Periodic Interval 3 Interrupt Enable + PER3: u1, + /// Periodic Interval 4 Interrupt Enable + PER4: u1, + /// Periodic Interval 5 Interrupt Enable + PER5: u1, + /// Periodic Interval 6 Interrupt Enable + PER6: u1, + /// Periodic Interval 7 Interrupt Enable + PER7: u1, + /// Compare 0 Interrupt Enable + CMP0: u1, + /// Compare 1 Interrupt Enable + CMP1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Tamper Enable + TAMPER: u1, + /// Overflow Interrupt Enable + OVF: u1, + }), base_address + 0x8); + + /// address: 0x4000240a + /// MODE0 Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(16, packed struct { + /// Periodic Interval 0 Interrupt Enable + PER0: u1, + /// Periodic Interval 1 Interrupt Enable + PER1: u1, + /// Periodic Interval 2 Interrupt Enable + PER2: u1, + /// Periodic Interval 3 Interrupt Enable + PER3: u1, + /// Periodic Interval 4 Interrupt Enable + PER4: u1, + /// Periodic Interval 5 Interrupt Enable + PER5: u1, + /// Periodic Interval 6 Interrupt Enable + PER6: u1, + /// Periodic Interval 7 Interrupt Enable + PER7: u1, + /// Compare 0 Interrupt Enable + CMP0: u1, + /// Compare 1 Interrupt Enable + CMP1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Tamper Enable + TAMPER: u1, + /// Overflow Interrupt Enable + OVF: u1, + }), base_address + 0xa); + + /// address: 0x4000240c + /// MODE0 Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(16, packed struct { + /// Periodic Interval 0 + PER0: u1, + /// Periodic Interval 1 + PER1: u1, + /// Periodic Interval 2 + PER2: u1, + /// Periodic Interval 3 + PER3: u1, + /// Periodic Interval 4 + PER4: u1, + /// Periodic Interval 5 + PER5: u1, + /// Periodic Interval 6 + PER6: u1, + /// Periodic Interval 7 + PER7: u1, + /// Compare 0 + CMP0: u1, + /// Compare 1 + CMP1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Tamper + TAMPER: u1, + /// Overflow + OVF: u1, + }), base_address + 0xc); + + /// address: 0x4000240e + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Run During Debug + DBGRUN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0xe); + + /// address: 0x40002410 + /// MODE0 Synchronization Busy Status + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset Busy + SWRST: u1, + /// Enable Bit Busy + ENABLE: u1, + /// FREQCORR Register Busy + FREQCORR: u1, + /// COUNT Register Busy + COUNT: u1, + reserved0: u1, + /// COMP 0 Register Busy + COMP0: u1, + /// COMP 1 Register Busy + COMP1: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Count Synchronization Enable Bit Busy + COUNTSYNC: u1, + /// General Purpose 0 Register Busy + GP0: u1, + /// General Purpose 1 Register Busy + GP1: u1, + /// General Purpose 2 Register Busy + GP2: u1, + /// General Purpose 3 Register Busy + GP3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x10); + + /// address: 0x40002414 + /// Frequency Correction + pub const FREQCORR = @intToPtr(*volatile Mmio(8, packed struct { + /// Correction Value + VALUE: u7, + /// Correction Sign + SIGN: u1, + }), base_address + 0x14); + + /// address: 0x40002418 + /// MODE0 Counter Value + pub const COUNT = @intToPtr(*volatile u32, base_address + 0x18); + + /// address: 0x40002420 + /// MODE0 Compare n Value + pub const COMP = @intToPtr(*volatile [2]u32, base_address + 0x20); + + /// address: 0x40002440 + /// General Purpose + pub const GP = @intToPtr(*volatile [4]u32, base_address + 0x40); + + /// address: 0x40002460 + /// Tamper Control + pub const TAMPCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Tamper Input 0 Action + IN0ACT: u2, + /// Tamper Input 1 Action + IN1ACT: u2, + /// Tamper Input 2 Action + IN2ACT: u2, + /// Tamper Input 3 Action + IN3ACT: u2, + /// Tamper Input 4 Action + IN4ACT: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Tamper Level Select 0 + TAMLVL0: u1, + /// Tamper Level Select 1 + TAMLVL1: u1, + /// Tamper Level Select 2 + TAMLVL2: u1, + /// Tamper Level Select 3 + TAMLVL3: u1, + /// Tamper Level Select 4 + TAMLVL4: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Debouncer Enable 0 + DEBNC0: u1, + /// Debouncer Enable 1 + DEBNC1: u1, + /// Debouncer Enable 2 + DEBNC2: u1, + /// Debouncer Enable 3 + DEBNC3: u1, + /// Debouncer Enable 4 + DEBNC4: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x60); + + /// address: 0x40002464 + /// MODE0 Timestamp + pub const TIMESTAMP = @intToPtr(*volatile Mmio(32, packed struct { + /// Count Timestamp Value + COUNT: u32, + }), base_address + 0x64); + + /// address: 0x40002468 + /// Tamper ID + pub const TAMPID = @intToPtr(*volatile Mmio(32, packed struct { + /// Tamper Input 0 Detected + TAMPID0: u1, + /// Tamper Input 1 Detected + TAMPID1: u1, + /// Tamper Input 2 Detected + TAMPID2: u1, + /// Tamper Input 3 Detected + TAMPID3: u1, + /// Tamper Input 4 Detected + TAMPID4: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Tamper Event Detected + TAMPEVT: u1, + }), base_address + 0x68); + + /// address: 0x40002480 + /// Backup + pub const BKUP = @intToPtr(*volatile [8]u32, base_address + 0x80); + }; + + /// 16-bit Counter with Two 16-bit Compares + pub const MODE1 = struct { + /// address: 0x40002400 + /// MODE1 Control A + pub const CTRLA = @intToPtr(*volatile Mmio(16, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Operating Mode + MODE: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Prescaler + PRESCALER: u4, + reserved4: u1, + /// BKUP Registers Reset On Tamper Enable + BKTRST: u1, + /// GP Registers Reset On Tamper Enable + GPTRST: u1, + /// Count Read Synchronization Enable + COUNTSYNC: u1, + }), base_address + 0x0); + + /// address: 0x40002402 + /// MODE1 Control B + pub const CTRLB = @intToPtr(*volatile Mmio(16, packed struct { + /// General Purpose 0 Enable + GP0EN: u1, + /// General Purpose 2 Enable + GP2EN: u1, + reserved0: u1, + reserved1: u1, + /// Debouncer Majority Enable + DEBMAJ: u1, + /// Debouncer Asynchronous Enable + DEBASYNC: u1, + /// RTC Output Enable + RTCOUT: u1, + /// DMA Enable + DMAEN: u1, + /// Debounce Freqnuency + DEBF: u3, + reserved2: u1, + /// Active Layer Freqnuency + ACTF: u3, + padding0: u1, + }), base_address + 0x2); + + /// address: 0x40002404 + /// MODE1 Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Periodic Interval 0 Event Output Enable + PEREO0: u1, + /// Periodic Interval 1 Event Output Enable + PEREO1: u1, + /// Periodic Interval 2 Event Output Enable + PEREO2: u1, + /// Periodic Interval 3 Event Output Enable + PEREO3: u1, + /// Periodic Interval 4 Event Output Enable + PEREO4: u1, + /// Periodic Interval 5 Event Output Enable + PEREO5: u1, + /// Periodic Interval 6 Event Output Enable + PEREO6: u1, + /// Periodic Interval 7 Event Output Enable + PEREO7: u1, + /// Compare 0 Event Output Enable + CMPEO0: u1, + /// Compare 1 Event Output Enable + CMPEO1: u1, + /// Compare 2 Event Output Enable + CMPEO2: u1, + /// Compare 3 Event Output Enable + CMPEO3: u1, + reserved0: u1, + reserved1: u1, + /// Tamper Event Output Enable + TAMPEREO: u1, + /// Overflow Event Output Enable + OVFEO: u1, + /// Tamper Event Input Enable + TAMPEVEI: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x4); + + /// address: 0x40002408 + /// MODE1 Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(16, packed struct { + /// Periodic Interval 0 Interrupt Enable + PER0: u1, + /// Periodic Interval 1 Interrupt Enable + PER1: u1, + /// Periodic Interval 2 Interrupt Enable + PER2: u1, + /// Periodic Interval 3 Interrupt Enable + PER3: u1, + /// Periodic Interval 4 Interrupt Enable + PER4: u1, + /// Periodic Interval 5 Interrupt Enable + PER5: u1, + /// Periodic Interval 6 Interrupt Enable + PER6: u1, + /// Periodic Interval 7 Interrupt Enable + PER7: u1, + /// Compare 0 Interrupt Enable + CMP0: u1, + /// Compare 1 Interrupt Enable + CMP1: u1, + /// Compare 2 Interrupt Enable + CMP2: u1, + /// Compare 3 Interrupt Enable + CMP3: u1, + reserved0: u1, + reserved1: u1, + /// Tamper Enable + TAMPER: u1, + /// Overflow Interrupt Enable + OVF: u1, + }), base_address + 0x8); + + /// address: 0x4000240a + /// MODE1 Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(16, packed struct { + /// Periodic Interval 0 Interrupt Enable + PER0: u1, + /// Periodic Interval 1 Interrupt Enable + PER1: u1, + /// Periodic Interval 2 Interrupt Enable + PER2: u1, + /// Periodic Interval 3 Interrupt Enable + PER3: u1, + /// Periodic Interval 4 Interrupt Enable + PER4: u1, + /// Periodic Interval 5 Interrupt Enable + PER5: u1, + /// Periodic Interval 6 Interrupt Enable + PER6: u1, + /// Periodic Interval 7 Interrupt Enable + PER7: u1, + /// Compare 0 Interrupt Enable + CMP0: u1, + /// Compare 1 Interrupt Enable + CMP1: u1, + /// Compare 2 Interrupt Enable + CMP2: u1, + /// Compare 3 Interrupt Enable + CMP3: u1, + reserved0: u1, + reserved1: u1, + /// Tamper Enable + TAMPER: u1, + /// Overflow Interrupt Enable + OVF: u1, + }), base_address + 0xa); + + /// address: 0x4000240c + /// MODE1 Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(16, packed struct { + /// Periodic Interval 0 + PER0: u1, + /// Periodic Interval 1 + PER1: u1, + /// Periodic Interval 2 + PER2: u1, + /// Periodic Interval 3 + PER3: u1, + /// Periodic Interval 4 + PER4: u1, + /// Periodic Interval 5 + PER5: u1, + /// Periodic Interval 6 + PER6: u1, + /// Periodic Interval 7 + PER7: u1, + /// Compare 0 + CMP0: u1, + /// Compare 1 + CMP1: u1, + /// Compare 2 + CMP2: u1, + /// Compare 3 + CMP3: u1, + reserved0: u1, + reserved1: u1, + /// Tamper + TAMPER: u1, + /// Overflow + OVF: u1, + }), base_address + 0xc); + + /// address: 0x4000240e + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Run During Debug + DBGRUN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0xe); + + /// address: 0x40002410 + /// MODE1 Synchronization Busy Status + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset Bit Busy + SWRST: u1, + /// Enable Bit Busy + ENABLE: u1, + /// FREQCORR Register Busy + FREQCORR: u1, + /// COUNT Register Busy + COUNT: u1, + /// PER Register Busy + PER: u1, + /// COMP 0 Register Busy + COMP0: u1, + /// COMP 1 Register Busy + COMP1: u1, + /// COMP 2 Register Busy + COMP2: u1, + /// COMP 3 Register Busy + COMP3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Count Synchronization Enable Bit Busy + COUNTSYNC: u1, + /// General Purpose 0 Register Busy + GP0: u1, + /// General Purpose 1 Register Busy + GP1: u1, + /// General Purpose 2 Register Busy + GP2: u1, + /// General Purpose 3 Register Busy + GP3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x10); + + /// address: 0x40002414 + /// Frequency Correction + pub const FREQCORR = @intToPtr(*volatile Mmio(8, packed struct { + /// Correction Value + VALUE: u7, + /// Correction Sign + SIGN: u1, + }), base_address + 0x14); + + /// address: 0x40002418 + /// MODE1 Counter Value + pub const COUNT = @intToPtr(*volatile u16, base_address + 0x18); + + /// address: 0x4000241c + /// MODE1 Counter Period + pub const PER = @intToPtr(*volatile u16, base_address + 0x1c); + + /// address: 0x40002420 + /// MODE1 Compare n Value + pub const COMP = @intToPtr(*volatile [4]u16, base_address + 0x20); + + /// address: 0x40002440 + /// General Purpose + pub const GP = @intToPtr(*volatile [4]u32, base_address + 0x40); + + /// address: 0x40002460 + /// Tamper Control + pub const TAMPCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Tamper Input 0 Action + IN0ACT: u2, + /// Tamper Input 1 Action + IN1ACT: u2, + /// Tamper Input 2 Action + IN2ACT: u2, + /// Tamper Input 3 Action + IN3ACT: u2, + /// Tamper Input 4 Action + IN4ACT: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Tamper Level Select 0 + TAMLVL0: u1, + /// Tamper Level Select 1 + TAMLVL1: u1, + /// Tamper Level Select 2 + TAMLVL2: u1, + /// Tamper Level Select 3 + TAMLVL3: u1, + /// Tamper Level Select 4 + TAMLVL4: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Debouncer Enable 0 + DEBNC0: u1, + /// Debouncer Enable 1 + DEBNC1: u1, + /// Debouncer Enable 2 + DEBNC2: u1, + /// Debouncer Enable 3 + DEBNC3: u1, + /// Debouncer Enable 4 + DEBNC4: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x60); + + /// address: 0x40002464 + /// MODE1 Timestamp + pub const TIMESTAMP = @intToPtr(*volatile Mmio(32, packed struct { + /// Count Timestamp Value + COUNT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x64); + + /// address: 0x40002468 + /// Tamper ID + pub const TAMPID = @intToPtr(*volatile Mmio(32, packed struct { + /// Tamper Input 0 Detected + TAMPID0: u1, + /// Tamper Input 1 Detected + TAMPID1: u1, + /// Tamper Input 2 Detected + TAMPID2: u1, + /// Tamper Input 3 Detected + TAMPID3: u1, + /// Tamper Input 4 Detected + TAMPID4: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Tamper Event Detected + TAMPEVT: u1, + }), base_address + 0x68); + + /// address: 0x40002480 + /// Backup + pub const BKUP = @intToPtr(*volatile [8]u32, base_address + 0x80); + }; + + /// Clock/Calendar with Alarm + pub const MODE2 = struct { + /// address: 0x40002400 + /// MODE2 Control A + pub const CTRLA = @intToPtr(*volatile Mmio(16, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Operating Mode + MODE: u2, + reserved0: u1, + reserved1: u1, + /// Clock Representation + CLKREP: u1, + /// Clear on Match + MATCHCLR: u1, + /// Prescaler + PRESCALER: u4, + reserved2: u1, + /// BKUP Registers Reset On Tamper Enable + BKTRST: u1, + /// GP Registers Reset On Tamper Enable + GPTRST: u1, + /// Clock Read Synchronization Enable + CLOCKSYNC: u1, + }), base_address + 0x0); + + /// address: 0x40002402 + /// MODE2 Control B + pub const CTRLB = @intToPtr(*volatile Mmio(16, packed struct { + /// General Purpose 0 Enable + GP0EN: u1, + /// General Purpose 2 Enable + GP2EN: u1, + reserved0: u1, + reserved1: u1, + /// Debouncer Majority Enable + DEBMAJ: u1, + /// Debouncer Asynchronous Enable + DEBASYNC: u1, + /// RTC Output Enable + RTCOUT: u1, + /// DMA Enable + DMAEN: u1, + /// Debounce Freqnuency + DEBF: u3, + reserved2: u1, + /// Active Layer Freqnuency + ACTF: u3, + padding0: u1, + }), base_address + 0x2); + + /// address: 0x40002404 + /// MODE2 Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Periodic Interval 0 Event Output Enable + PEREO0: u1, + /// Periodic Interval 1 Event Output Enable + PEREO1: u1, + /// Periodic Interval 2 Event Output Enable + PEREO2: u1, + /// Periodic Interval 3 Event Output Enable + PEREO3: u1, + /// Periodic Interval 4 Event Output Enable + PEREO4: u1, + /// Periodic Interval 5 Event Output Enable + PEREO5: u1, + /// Periodic Interval 6 Event Output Enable + PEREO6: u1, + /// Periodic Interval 7 Event Output Enable + PEREO7: u1, + /// Alarm 0 Event Output Enable + ALARMEO0: u1, + /// Alarm 1 Event Output Enable + ALARMEO1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Tamper Event Output Enable + TAMPEREO: u1, + /// Overflow Event Output Enable + OVFEO: u1, + /// Tamper Event Input Enable + TAMPEVEI: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x4); + + /// address: 0x40002408 + /// MODE2 Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(16, packed struct { + /// Periodic Interval 0 Interrupt Enable + PER0: u1, + /// Periodic Interval 1 Interrupt Enable + PER1: u1, + /// Periodic Interval 2 Interrupt Enable + PER2: u1, + /// Periodic Interval 3 Interrupt Enable + PER3: u1, + /// Periodic Interval 4 Interrupt Enable + PER4: u1, + /// Periodic Interval 5 Interrupt Enable + PER5: u1, + /// Periodic Interval 6 Interrupt Enable + PER6: u1, + /// Periodic Interval 7 Interrupt Enable + PER7: u1, + /// Alarm 0 Interrupt Enable + ALARM0: u1, + /// Alarm 1 Interrupt Enable + ALARM1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Tamper Enable + TAMPER: u1, + /// Overflow Interrupt Enable + OVF: u1, + }), base_address + 0x8); + + /// address: 0x4000240a + /// MODE2 Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(16, packed struct { + /// Periodic Interval 0 Enable + PER0: u1, + /// Periodic Interval 1 Enable + PER1: u1, + /// Periodic Interval 2 Enable + PER2: u1, + /// Periodic Interval 3 Enable + PER3: u1, + /// Periodic Interval 4 Enable + PER4: u1, + /// Periodic Interval 5 Enable + PER5: u1, + /// Periodic Interval 6 Enable + PER6: u1, + /// Periodic Interval 7 Enable + PER7: u1, + /// Alarm 0 Interrupt Enable + ALARM0: u1, + /// Alarm 1 Interrupt Enable + ALARM1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Tamper Enable + TAMPER: u1, + /// Overflow Interrupt Enable + OVF: u1, + }), base_address + 0xa); + + /// address: 0x4000240c + /// MODE2 Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(16, packed struct { + /// Periodic Interval 0 + PER0: u1, + /// Periodic Interval 1 + PER1: u1, + /// Periodic Interval 2 + PER2: u1, + /// Periodic Interval 3 + PER3: u1, + /// Periodic Interval 4 + PER4: u1, + /// Periodic Interval 5 + PER5: u1, + /// Periodic Interval 6 + PER6: u1, + /// Periodic Interval 7 + PER7: u1, + /// Alarm 0 + ALARM0: u1, + /// Alarm 1 + ALARM1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Tamper + TAMPER: u1, + /// Overflow + OVF: u1, + }), base_address + 0xc); + + /// address: 0x4000240e + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Run During Debug + DBGRUN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0xe); + + /// address: 0x40002410 + /// MODE2 Synchronization Busy Status + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset Bit Busy + SWRST: u1, + /// Enable Bit Busy + ENABLE: u1, + /// FREQCORR Register Busy + FREQCORR: u1, + /// CLOCK Register Busy + CLOCK: u1, + reserved0: u1, + /// ALARM 0 Register Busy + ALARM0: u1, + /// ALARM 1 Register Busy + ALARM1: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// MASK 0 Register Busy + MASK0: u1, + /// MASK 1 Register Busy + MASK1: u1, + reserved5: u1, + reserved6: u1, + /// Clock Synchronization Enable Bit Busy + CLOCKSYNC: u1, + /// General Purpose 0 Register Busy + GP0: u1, + /// General Purpose 1 Register Busy + GP1: u1, + /// General Purpose 2 Register Busy + GP2: u1, + /// General Purpose 3 Register Busy + GP3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x10); + + /// address: 0x40002414 + /// Frequency Correction + pub const FREQCORR = @intToPtr(*volatile Mmio(8, packed struct { + /// Correction Value + VALUE: u7, + /// Correction Sign + SIGN: u1, + }), base_address + 0x14); + + /// address: 0x40002418 + /// MODE2 Clock Value + pub const CLOCK = @intToPtr(*volatile Mmio(32, packed struct { + /// Second + SECOND: u6, + /// Minute + MINUTE: u6, + /// Hour + HOUR: u5, + /// Day + DAY: u5, + /// Month + MONTH: u4, + /// Year + YEAR: u6, + }), base_address + 0x18); + + /// address: 0x40002440 + /// General Purpose + pub const GP = @intToPtr(*volatile [4]u32, base_address + 0x40); + + /// address: 0x40002420 + /// MODE2_ALARM Alarm n Value + pub const ALARM0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Second + SECOND: u6, + /// Minute + MINUTE: u6, + /// Hour + HOUR: u5, + /// Day + DAY: u5, + /// Month + MONTH: u4, + /// Year + YEAR: u6, + }), base_address + 0x20); + + /// address: 0x40002424 + /// MODE2_ALARM Alarm n Mask + pub const MASK0 = @intToPtr(*volatile Mmio(8, packed struct { + /// Alarm Mask Selection + SEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x24); + + /// address: 0x40002428 + /// MODE2_ALARM Alarm n Value + pub const ALARM1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Second + SECOND: u6, + /// Minute + MINUTE: u6, + /// Hour + HOUR: u5, + /// Day + DAY: u5, + /// Month + MONTH: u4, + /// Year + YEAR: u6, + }), base_address + 0x28); + + /// address: 0x4000242c + /// MODE2_ALARM Alarm n Mask + pub const MASK1 = @intToPtr(*volatile Mmio(8, packed struct { + /// Alarm Mask Selection + SEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x2c); + + /// address: 0x40002460 + /// Tamper Control + pub const TAMPCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Tamper Input 0 Action + IN0ACT: u2, + /// Tamper Input 1 Action + IN1ACT: u2, + /// Tamper Input 2 Action + IN2ACT: u2, + /// Tamper Input 3 Action + IN3ACT: u2, + /// Tamper Input 4 Action + IN4ACT: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Tamper Level Select 0 + TAMLVL0: u1, + /// Tamper Level Select 1 + TAMLVL1: u1, + /// Tamper Level Select 2 + TAMLVL2: u1, + /// Tamper Level Select 3 + TAMLVL3: u1, + /// Tamper Level Select 4 + TAMLVL4: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Debouncer Enable 0 + DEBNC0: u1, + /// Debouncer Enable 1 + DEBNC1: u1, + /// Debouncer Enable 2 + DEBNC2: u1, + /// Debouncer Enable 3 + DEBNC3: u1, + /// Debouncer Enable 4 + DEBNC4: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x60); + + /// address: 0x40002464 + /// MODE2 Timestamp + pub const TIMESTAMP = @intToPtr(*volatile Mmio(32, packed struct { + /// Second Timestamp Value + SECOND: u6, + /// Minute Timestamp Value + MINUTE: u6, + /// Hour Timestamp Value + HOUR: u5, + /// Day Timestamp Value + DAY: u5, + /// Month Timestamp Value + MONTH: u4, + /// Year Timestamp Value + YEAR: u6, + }), base_address + 0x64); + + /// address: 0x40002468 + /// Tamper ID + pub const TAMPID = @intToPtr(*volatile Mmio(32, packed struct { + /// Tamper Input 0 Detected + TAMPID0: u1, + /// Tamper Input 1 Detected + TAMPID1: u1, + /// Tamper Input 2 Detected + TAMPID2: u1, + /// Tamper Input 3 Detected + TAMPID3: u1, + /// Tamper Input 4 Detected + TAMPID4: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Tamper Event Detected + TAMPEVT: u1, + }), base_address + 0x68); + + /// address: 0x40002480 + /// Backup + pub const BKUP = @intToPtr(*volatile [8]u32, base_address + 0x80); + }; + }; + + /// SD/MMC Host Controller + pub const SDHC0 = struct { + pub const base_address = 0x45000000; + pub const version = "U20111.8.3"; + + /// address: 0x45000000 + /// SDMA System Address / Argument 2 + pub const SSAR = @intToPtr(*volatile Mmio(32, packed struct { + /// SDMA System Address + ADDR: u32, + }), base_address + 0x0); + + /// address: 0x45000000 + /// SDMA System Address / Argument 2 + pub const SSAR_CMD23_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Argument 2 + ARG2: u32, + }), base_address + 0x0); + + /// address: 0x45000004 + /// Block Size + pub const BSR = @intToPtr(*volatile Mmio(16, packed struct { + /// Transfer Block Size + BLOCKSIZE: u10, + reserved0: u1, + reserved1: u1, + /// SDMA Buffer Boundary + BOUNDARY: u3, + padding0: u1, + }), base_address + 0x4); + + /// address: 0x45000006 + /// Block Count + pub const BCR = @intToPtr(*volatile Mmio(16, packed struct { + /// Blocks Count for Current Transfer + BCNT: u16, + }), base_address + 0x6); + + /// address: 0x45000008 + /// Argument 1 + pub const ARG1R = @intToPtr(*volatile Mmio(32, packed struct { + /// Argument 1 + ARG: u32, + }), base_address + 0x8); + + /// address: 0x4500000c + /// Transfer Mode + pub const TMR = @intToPtr(*volatile Mmio(16, packed struct { + /// DMA Enable + DMAEN: u1, + /// Block Count Enable + BCEN: u1, + /// Auto Command Enable + ACMDEN: u2, + /// Data Transfer Direction Selection + DTDSEL: u1, + /// Multi/Single Block Selection + MSBSEL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0xc); + + /// address: 0x4500000e + /// Command + pub const CR = @intToPtr(*volatile Mmio(16, packed struct { + /// Response Type + RESPTYP: u2, + reserved0: u1, + /// Command CRC Check Enable + CMDCCEN: u1, + /// Command Index Check Enable + CMDICEN: u1, + /// Data Present Select + DPSEL: u1, + /// Command Type + CMDTYP: u2, + /// Command Index + CMDIDX: u6, + padding0: u1, + padding1: u1, + }), base_address + 0xe); + + /// address: 0x45000010 + /// Response + pub const RR = @intToPtr(*volatile [4]Mmio(32, packed struct { + /// Command Response + CMDRESP: u32, + }), base_address + 0x10); + + /// address: 0x45000020 + /// Buffer Data Port + pub const BDPR = @intToPtr(*volatile Mmio(32, packed struct { + /// Buffer Data + BUFDATA: u32, + }), base_address + 0x20); + + /// address: 0x45000024 + /// Present State + pub const PSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Command Inhibit (CMD) + CMDINHC: u1, + /// Command Inhibit (DAT) + CMDINHD: u1, + /// DAT Line Active + DLACT: u1, + /// Re-Tuning Request + RTREQ: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Write Transfer Active + WTACT: u1, + /// Read Transfer Active + RTACT: u1, + /// Buffer Write Enable + BUFWREN: u1, + /// Buffer Read Enable + BUFRDEN: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Card Inserted + CARDINS: u1, + /// Card State Stable + CARDSS: u1, + /// Card Detect Pin Level + CARDDPL: u1, + /// Write Protect Pin Level + WRPPL: u1, + /// DAT[3:0] Line Level + DATLL: u4, + /// CMD Line Level + CMDLL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x24); + + /// address: 0x45000028 + /// Host Control 1 + pub const HC1R = @intToPtr(*volatile Mmio(8, packed struct { + /// LED Control + LEDCTRL: u1, + /// Data Width + DW: u1, + /// High Speed Enable + HSEN: u1, + /// DMA Select + DMASEL: u2, + reserved0: u1, + /// Card Detect Test Level + CARDDTL: u1, + /// Card Detect Signal Selection + CARDDSEL: u1, + }), base_address + 0x28); + + /// address: 0x45000028 + /// Host Control 1 + pub const HC1R_EMMC_MODE = @intToPtr(*volatile Mmio(8, packed struct { + reserved0: u1, + /// Data Width + DW: u1, + /// High Speed Enable + HSEN: u1, + /// DMA Select + DMASEL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x28); + + /// address: 0x45000029 + /// Power Control + pub const PCR = @intToPtr(*volatile Mmio(8, packed struct { + /// SD Bus Power + SDBPWR: u1, + /// SD Bus Voltage Select + SDBVSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x29); + + /// address: 0x4500002a + /// Block Gap Control + pub const BGCR = @intToPtr(*volatile Mmio(8, packed struct { + /// Stop at Block Gap Request + STPBGR: u1, + /// Continue Request + CONTR: u1, + /// Read Wait Control + RWCTRL: u1, + /// Interrupt at Block Gap + INTBG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x2a); + + /// address: 0x4500002a + /// Block Gap Control + pub const BGCR_EMMC_MODE = @intToPtr(*volatile Mmio(8, packed struct { + /// Stop at Block Gap Request + STPBGR: u1, + /// Continue Request + CONTR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x2a); + + /// address: 0x4500002b + /// Wakeup Control + pub const WCR = @intToPtr(*volatile Mmio(8, packed struct { + /// Wakeup Event Enable on Card Interrupt + WKENCINT: u1, + /// Wakeup Event Enable on Card Insertion + WKENCINS: u1, + /// Wakeup Event Enable on Card Removal + WKENCREM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x2b); + + /// address: 0x4500002c + /// Clock Control + pub const CCR = @intToPtr(*volatile Mmio(16, packed struct { + /// Internal Clock Enable + INTCLKEN: u1, + /// Internal Clock Stable + INTCLKS: u1, + /// SD Clock Enable + SDCLKEN: u1, + reserved0: u1, + reserved1: u1, + /// Clock Generator Select + CLKGSEL: u1, + /// Upper Bits of SDCLK Frequency Select + USDCLKFSEL: u2, + /// SDCLK Frequency Select + SDCLKFSEL: u8, + }), base_address + 0x2c); + + /// address: 0x4500002e + /// Timeout Control + pub const TCR = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Timeout Counter Value + DTCVAL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x2e); + + /// address: 0x4500002f + /// Software Reset + pub const SRR = @intToPtr(*volatile Mmio(8, packed struct { + /// Software Reset For All + SWRSTALL: u1, + /// Software Reset For CMD Line + SWRSTCMD: u1, + /// Software Reset For DAT Line + SWRSTDAT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x2f); + + /// address: 0x45000030 + /// Normal Interrupt Status + pub const NISTR = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Complete + CMDC: u1, + /// Transfer Complete + TRFC: u1, + /// Block Gap Event + BLKGE: u1, + /// DMA Interrupt + DMAINT: u1, + /// Buffer Write Ready + BWRRDY: u1, + /// Buffer Read Ready + BRDRDY: u1, + /// Card Insertion + CINS: u1, + /// Card Removal + CREM: u1, + /// Card Interrupt + CINT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Error Interrupt + ERRINT: u1, + }), base_address + 0x30); + + /// address: 0x45000030 + /// Normal Interrupt Status + pub const NISTR_EMMC_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Complete + CMDC: u1, + /// Transfer Complete + TRFC: u1, + /// Block Gap Event + BLKGE: u1, + /// DMA Interrupt + DMAINT: u1, + /// Buffer Write Ready + BWRRDY: u1, + /// Buffer Read Ready + BRDRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Boot Acknowledge Received + BOOTAR: u1, + /// Error Interrupt + ERRINT: u1, + }), base_address + 0x30); + + /// address: 0x45000032 + /// Error Interrupt Status + pub const EISTR = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Timeout Error + CMDTEO: u1, + /// Command CRC Error + CMDCRC: u1, + /// Command End Bit Error + CMDEND: u1, + /// Command Index Error + CMDIDX: u1, + /// Data Timeout Error + DATTEO: u1, + /// Data CRC Error + DATCRC: u1, + /// Data End Bit Error + DATEND: u1, + /// Current Limit Error + CURLIM: u1, + /// Auto CMD Error + ACMD: u1, + /// ADMA Error + ADMA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x32); + + /// address: 0x45000032 + /// Error Interrupt Status + pub const EISTR_EMMC_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Timeout Error + CMDTEO: u1, + /// Command CRC Error + CMDCRC: u1, + /// Command End Bit Error + CMDEND: u1, + /// Command Index Error + CMDIDX: u1, + /// Data Timeout Error + DATTEO: u1, + /// Data CRC Error + DATCRC: u1, + /// Data End Bit Error + DATEND: u1, + /// Current Limit Error + CURLIM: u1, + /// Auto CMD Error + ACMD: u1, + /// ADMA Error + ADMA: u1, + reserved0: u1, + reserved1: u1, + /// Boot Acknowledge Error + BOOTAE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x32); + + /// address: 0x45000034 + /// Normal Interrupt Status Enable + pub const NISTER = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Complete Status Enable + CMDC: u1, + /// Transfer Complete Status Enable + TRFC: u1, + /// Block Gap Event Status Enable + BLKGE: u1, + /// DMA Interrupt Status Enable + DMAINT: u1, + /// Buffer Write Ready Status Enable + BWRRDY: u1, + /// Buffer Read Ready Status Enable + BRDRDY: u1, + /// Card Insertion Status Enable + CINS: u1, + /// Card Removal Status Enable + CREM: u1, + /// Card Interrupt Status Enable + CINT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x34); + + /// address: 0x45000034 + /// Normal Interrupt Status Enable + pub const NISTER_EMMC_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Complete Status Enable + CMDC: u1, + /// Transfer Complete Status Enable + TRFC: u1, + /// Block Gap Event Status Enable + BLKGE: u1, + /// DMA Interrupt Status Enable + DMAINT: u1, + /// Buffer Write Ready Status Enable + BWRRDY: u1, + /// Buffer Read Ready Status Enable + BRDRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Boot Acknowledge Received Status Enable + BOOTAR: u1, + padding0: u1, + }), base_address + 0x34); + + /// address: 0x45000036 + /// Error Interrupt Status Enable + pub const EISTER = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Timeout Error Status Enable + CMDTEO: u1, + /// Command CRC Error Status Enable + CMDCRC: u1, + /// Command End Bit Error Status Enable + CMDEND: u1, + /// Command Index Error Status Enable + CMDIDX: u1, + /// Data Timeout Error Status Enable + DATTEO: u1, + /// Data CRC Error Status Enable + DATCRC: u1, + /// Data End Bit Error Status Enable + DATEND: u1, + /// Current Limit Error Status Enable + CURLIM: u1, + /// Auto CMD Error Status Enable + ACMD: u1, + /// ADMA Error Status Enable + ADMA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x36); + + /// address: 0x45000036 + /// Error Interrupt Status Enable + pub const EISTER_EMMC_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Timeout Error Status Enable + CMDTEO: u1, + /// Command CRC Error Status Enable + CMDCRC: u1, + /// Command End Bit Error Status Enable + CMDEND: u1, + /// Command Index Error Status Enable + CMDIDX: u1, + /// Data Timeout Error Status Enable + DATTEO: u1, + /// Data CRC Error Status Enable + DATCRC: u1, + /// Data End Bit Error Status Enable + DATEND: u1, + /// Current Limit Error Status Enable + CURLIM: u1, + /// Auto CMD Error Status Enable + ACMD: u1, + /// ADMA Error Status Enable + ADMA: u1, + reserved0: u1, + reserved1: u1, + /// Boot Acknowledge Error Status Enable + BOOTAE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x36); + + /// address: 0x45000038 + /// Normal Interrupt Signal Enable + pub const NISIER = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Complete Signal Enable + CMDC: u1, + /// Transfer Complete Signal Enable + TRFC: u1, + /// Block Gap Event Signal Enable + BLKGE: u1, + /// DMA Interrupt Signal Enable + DMAINT: u1, + /// Buffer Write Ready Signal Enable + BWRRDY: u1, + /// Buffer Read Ready Signal Enable + BRDRDY: u1, + /// Card Insertion Signal Enable + CINS: u1, + /// Card Removal Signal Enable + CREM: u1, + /// Card Interrupt Signal Enable + CINT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x38); + + /// address: 0x45000038 + /// Normal Interrupt Signal Enable + pub const NISIER_EMMC_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Complete Signal Enable + CMDC: u1, + /// Transfer Complete Signal Enable + TRFC: u1, + /// Block Gap Event Signal Enable + BLKGE: u1, + /// DMA Interrupt Signal Enable + DMAINT: u1, + /// Buffer Write Ready Signal Enable + BWRRDY: u1, + /// Buffer Read Ready Signal Enable + BRDRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Boot Acknowledge Received Signal Enable + BOOTAR: u1, + padding0: u1, + }), base_address + 0x38); + + /// address: 0x4500003a + /// Error Interrupt Signal Enable + pub const EISIER = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Timeout Error Signal Enable + CMDTEO: u1, + /// Command CRC Error Signal Enable + CMDCRC: u1, + /// Command End Bit Error Signal Enable + CMDEND: u1, + /// Command Index Error Signal Enable + CMDIDX: u1, + /// Data Timeout Error Signal Enable + DATTEO: u1, + /// Data CRC Error Signal Enable + DATCRC: u1, + /// Data End Bit Error Signal Enable + DATEND: u1, + /// Current Limit Error Signal Enable + CURLIM: u1, + /// Auto CMD Error Signal Enable + ACMD: u1, + /// ADMA Error Signal Enable + ADMA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x3a); + + /// address: 0x4500003a + /// Error Interrupt Signal Enable + pub const EISIER_EMMC_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Timeout Error Signal Enable + CMDTEO: u1, + /// Command CRC Error Signal Enable + CMDCRC: u1, + /// Command End Bit Error Signal Enable + CMDEND: u1, + /// Command Index Error Signal Enable + CMDIDX: u1, + /// Data Timeout Error Signal Enable + DATTEO: u1, + /// Data CRC Error Signal Enable + DATCRC: u1, + /// Data End Bit Error Signal Enable + DATEND: u1, + /// Current Limit Error Signal Enable + CURLIM: u1, + /// Auto CMD Error Signal Enable + ACMD: u1, + /// ADMA Error Signal Enable + ADMA: u1, + reserved0: u1, + reserved1: u1, + /// Boot Acknowledge Error Signal Enable + BOOTAE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x3a); + + /// address: 0x4500003c + /// Auto CMD Error Status + pub const ACESR = @intToPtr(*volatile Mmio(16, packed struct { + /// Auto CMD12 Not Executed + ACMD12NE: u1, + /// Auto CMD Timeout Error + ACMDTEO: u1, + /// Auto CMD CRC Error + ACMDCRC: u1, + /// Auto CMD End Bit Error + ACMDEND: u1, + /// Auto CMD Index Error + ACMDIDX: u1, + reserved0: u1, + reserved1: u1, + /// Command not Issued By Auto CMD12 Error + CMDNI: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x3c); + + /// address: 0x4500003e + /// Host Control 2 + pub const HC2R = @intToPtr(*volatile Mmio(16, packed struct { + /// UHS Mode Select + UHSMS: u3, + /// 1.8V Signaling Enable + VS18EN: u1, + /// Driver Strength Select + DRVSEL: u2, + /// Execute Tuning + EXTUN: u1, + /// Sampling Clock Select + SLCKSEL: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Asynchronous Interrupt Enable + ASINTEN: u1, + /// Preset Value Enable + PVALEN: u1, + }), base_address + 0x3e); + + /// address: 0x4500003e + /// Host Control 2 + pub const HC2R_EMMC_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// HS200 Mode Enable + HS200EN: u4, + /// Driver Strength Select + DRVSEL: u2, + /// Execute Tuning + EXTUN: u1, + /// Sampling Clock Select + SLCKSEL: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Preset Value Enable + PVALEN: u1, + }), base_address + 0x3e); + + /// address: 0x45000040 + /// Capabilities 0 + pub const CA0R = @intToPtr(*volatile Mmio(32, packed struct { + /// Timeout Clock Frequency + TEOCLKF: u6, + reserved0: u1, + /// Timeout Clock Unit + TEOCLKU: u1, + /// Base Clock Frequency + BASECLKF: u8, + /// Max Block Length + MAXBLKL: u2, + /// 8-bit Support for Embedded Device + ED8SUP: u1, + /// ADMA2 Support + ADMA2SUP: u1, + reserved1: u1, + /// High Speed Support + HSSUP: u1, + /// SDMA Support + SDMASUP: u1, + /// Suspend/Resume Support + SRSUP: u1, + /// Voltage Support 3.3V + V33VSUP: u1, + /// Voltage Support 3.0V + V30VSUP: u1, + /// Voltage Support 1.8V + V18VSUP: u1, + reserved2: u1, + /// 64-Bit System Bus Support + SB64SUP: u1, + /// Asynchronous Interrupt Support + ASINTSUP: u1, + /// Slot Type + SLTYPE: u2, + }), base_address + 0x40); + + /// address: 0x45000044 + /// Capabilities 1 + pub const CA1R = @intToPtr(*volatile Mmio(32, packed struct { + /// SDR50 Support + SDR50SUP: u1, + /// SDR104 Support + SDR104SUP: u1, + /// DDR50 Support + DDR50SUP: u1, + reserved0: u1, + /// Driver Type A Support + DRVASUP: u1, + /// Driver Type C Support + DRVCSUP: u1, + /// Driver Type D Support + DRVDSUP: u1, + reserved1: u1, + /// Timer Count for Re-Tuning + TCNTRT: u4, + reserved2: u1, + /// Use Tuning for SDR50 + TSDR50: u1, + reserved3: u1, + reserved4: u1, + /// Clock Multiplier + CLKMULT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x45000048 + /// Maximum Current Capabilities + pub const MCCAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum Current for 3.3V + MAXCUR33V: u8, + /// Maximum Current for 3.0V + MAXCUR30V: u8, + /// Maximum Current for 1.8V + MAXCUR18V: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x48); + + /// address: 0x45000050 + /// Force Event for Auto CMD Error Status + pub const FERACES = @intToPtr(*volatile Mmio(16, packed struct { + /// Force Event for Auto CMD12 Not Executed + ACMD12NE: u1, + /// Force Event for Auto CMD Timeout Error + ACMDTEO: u1, + /// Force Event for Auto CMD CRC Error + ACMDCRC: u1, + /// Force Event for Auto CMD End Bit Error + ACMDEND: u1, + /// Force Event for Auto CMD Index Error + ACMDIDX: u1, + reserved0: u1, + reserved1: u1, + /// Force Event for Command Not Issued By Auto CMD12 Error + CMDNI: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x50); + + /// address: 0x45000052 + /// Force Event for Error Interrupt Status + pub const FEREIS = @intToPtr(*volatile Mmio(16, packed struct { + /// Force Event for Command Timeout Error + CMDTEO: u1, + /// Force Event for Command CRC Error + CMDCRC: u1, + /// Force Event for Command End Bit Error + CMDEND: u1, + /// Force Event for Command Index Error + CMDIDX: u1, + /// Force Event for Data Timeout Error + DATTEO: u1, + /// Force Event for Data CRC Error + DATCRC: u1, + /// Force Event for Data End Bit Error + DATEND: u1, + /// Force Event for Current Limit Error + CURLIM: u1, + /// Force Event for Auto CMD Error + ACMD: u1, + /// Force Event for ADMA Error + ADMA: u1, + reserved0: u1, + reserved1: u1, + /// Force Event for Boot Acknowledge Error + BOOTAE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x52); + + /// address: 0x45000054 + /// ADMA Error Status + pub const AESR = @intToPtr(*volatile Mmio(8, packed struct { + /// ADMA Error State + ERRST: u2, + /// ADMA Length Mismatch Error + LMIS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x54); + + /// address: 0x45000058 + /// ADMA System Address n + pub const ASAR = @intToPtr(*volatile [1]Mmio(32, packed struct { + /// ADMA System Address + ADMASA: u32, + }), base_address + 0x58); + + /// address: 0x45000060 + /// Preset Value n + pub const PVR = @intToPtr(*volatile [8]Mmio(16, packed struct { + /// SDCLK Frequency Select Value for Initialization + SDCLKFSEL: u10, + /// Clock Generator Select Value for Initialization + CLKGSEL: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Driver Strength Select Value for Initialization + DRVSEL: u2, + }), base_address + 0x60); + + /// address: 0x450000fc + /// Slot Interrupt Status + pub const SISR = @intToPtr(*volatile Mmio(16, packed struct { + /// Interrupt Signal for Each Slot + INTSSL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0xfc); + + /// address: 0x450000fe + /// Host Controller Version + pub const HCVR = @intToPtr(*volatile Mmio(16, packed struct { + /// Spec Version + SVER: u8, + /// Vendor Version + VVER: u8, + }), base_address + 0xfe); + + /// address: 0x45000204 + /// MMC Control 1 + pub const MC1R = @intToPtr(*volatile Mmio(8, packed struct { + /// e.MMC Command Type + CMDTYP: u2, + reserved0: u1, + /// e.MMC HSDDR Mode + DDR: u1, + /// e.MMC Open Drain Mode + OPD: u1, + /// e.MMC Boot Acknowledge Enable + BOOTA: u1, + /// e.MMC Reset Signal + RSTN: u1, + /// e.MMC Force Card Detect + FCD: u1, + }), base_address + 0x204); + + /// address: 0x45000205 + /// MMC Control 2 + pub const MC2R = @intToPtr(*volatile Mmio(8, packed struct { + /// e.MMC Abort Wait IRQ + SRESP: u1, + /// e.MMC Abort Boot + ABOOT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x205); + + /// address: 0x45000208 + /// AHB Control + pub const ACR = @intToPtr(*volatile Mmio(32, packed struct { + /// AHB Maximum Burst + BMAX: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x208); + + /// address: 0x4500020c + /// Clock Control 2 + pub const CC2R = @intToPtr(*volatile Mmio(32, packed struct { + /// Force SDCK Disabled + FSDCLKD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x20c); + + /// address: 0x45000230 + /// Capabilities Control + pub const CACR = @intToPtr(*volatile Mmio(32, packed struct { + /// Capabilities Registers Write Enable (Required to write the correct frequencies + /// in the Capabilities Registers) + CAPWREN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Key (0x46) + KEY: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x230); + + /// address: 0x45000234 + /// Debug + pub const DBGR = @intToPtr(*volatile Mmio(8, packed struct { + /// Non-intrusive debug enable + NIDBG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x234); + }; + + /// Serial Communication Interface + pub const SERCOM0 = struct { + pub const base_address = 0x40003000; + pub const version = "U22015.0.0"; + + /// I2C Master Mode + pub const I2CM = struct { + /// address: 0x40003000 + /// I2CM Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Operating Mode + MODE: u3, + reserved0: u1, + reserved1: u1, + /// Run in Standby + RUNSTDBY: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Pin Usage + PINOUT: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// SDA Hold Time + SDAHOLD: u2, + /// Master SCL Low Extend Timeout + MEXTTOEN: u1, + /// Slave SCL Low Extend Timeout + SEXTTOEN: u1, + /// Transfer Speed + SPEED: u2, + reserved13: u1, + /// SCL Clock Stretch Mode + SCLSM: u1, + /// Inactive Time-Out + INACTOUT: u2, + /// SCL Low Timeout Enable + LOWTOUTEN: u1, + padding0: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// I2CM Control B + pub const CTRLB = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Smart Mode Enable + SMEN: u1, + /// Quick Command Enable + QCEN: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Command + CMD: u2, + /// Acknowledge Action + ACKACT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x4); + + /// address: 0x40003008 + /// I2CM Control C + pub const CTRLC = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + /// Data 32 Bit + DATA32B: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x8); + + /// address: 0x4000300c + /// I2CM Baud Rate + pub const BAUD = @intToPtr(*volatile Mmio(32, packed struct { + /// Baud Rate Value + BAUD: u8, + /// Baud Rate Value Low + BAUDLOW: u8, + /// High Speed Baud Rate Value + HSBAUD: u8, + /// High Speed Baud Rate Value Low + HSBAUDLOW: u8, + }), base_address + 0xc); + + /// address: 0x40003014 + /// I2CM Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Master On Bus Interrupt Disable + MB: u1, + /// Slave On Bus Interrupt Disable + SB: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Combined Error Interrupt Disable + ERROR: u1, + }), base_address + 0x14); + + /// address: 0x40003016 + /// I2CM Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Master On Bus Interrupt Enable + MB: u1, + /// Slave On Bus Interrupt Enable + SB: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Combined Error Interrupt Enable + ERROR: u1, + }), base_address + 0x16); + + /// address: 0x40003018 + /// I2CM Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Master On Bus Interrupt + MB: u1, + /// Slave On Bus Interrupt + SB: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Combined Error Interrupt + ERROR: u1, + }), base_address + 0x18); + + /// address: 0x4000301a + /// I2CM Status + pub const STATUS = @intToPtr(*volatile Mmio(16, packed struct { + /// Bus Error + BUSERR: u1, + /// Arbitration Lost + ARBLOST: u1, + /// Received Not Acknowledge + RXNACK: u1, + reserved0: u1, + /// Bus State + BUSSTATE: u2, + /// SCL Low Timeout + LOWTOUT: u1, + /// Clock Hold + CLKHOLD: u1, + /// Master SCL Low Extend Timeout + MEXTTOUT: u1, + /// Slave SCL Low Extend Timeout + SEXTTOUT: u1, + /// Length Error + LENERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x1a); + + /// address: 0x4000301c + /// I2CM Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset Synchronization Busy + SWRST: u1, + /// SERCOM Enable Synchronization Busy + ENABLE: u1, + /// System Operation Synchronization Busy + SYSOP: u1, + reserved0: u1, + /// Length Synchronization Busy + LENGTH: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x1c); + + /// address: 0x40003024 + /// I2CM Address + pub const ADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Address Value + ADDR: u11, + reserved0: u1, + reserved1: u1, + /// Length Enable + LENEN: u1, + /// High Speed Mode + HS: u1, + /// Ten Bit Addressing Enable + TENBITEN: u1, + /// Length + LEN: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x24); + + /// address: 0x40003028 + /// I2CM Data + pub const DATA = @intToPtr(*volatile u8, base_address + 0x28); + + /// address: 0x40003030 + /// I2CM Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Mode + DBGSTOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x30); + }; + + /// I2C Slave Mode + pub const I2CS = struct { + /// address: 0x40003000 + /// I2CS Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Operating Mode + MODE: u3, + reserved0: u1, + reserved1: u1, + /// Run during Standby + RUNSTDBY: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Pin Usage + PINOUT: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// SDA Hold Time + SDAHOLD: u2, + reserved13: u1, + /// Slave SCL Low Extend Timeout + SEXTTOEN: u1, + /// Transfer Speed + SPEED: u2, + reserved14: u1, + /// SCL Clock Stretch Mode + SCLSM: u1, + reserved15: u1, + reserved16: u1, + /// SCL Low Timeout Enable + LOWTOUTEN: u1, + padding0: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// I2CS Control B + pub const CTRLB = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Smart Mode Enable + SMEN: u1, + /// PMBus Group Command + GCMD: u1, + /// Automatic Address Acknowledge + AACKEN: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// Address Mode + AMODE: u2, + /// Command + CMD: u2, + /// Acknowledge Action + ACKACT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x4); + + /// address: 0x40003008 + /// I2CS Control C + pub const CTRLC = @intToPtr(*volatile Mmio(32, packed struct { + /// SDA Setup Time + SDASETUP: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + /// Data 32 Bit + DATA32B: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x8); + + /// address: 0x40003014 + /// I2CS Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Stop Received Interrupt Disable + PREC: u1, + /// Address Match Interrupt Disable + AMATCH: u1, + /// Data Interrupt Disable + DRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Combined Error Interrupt Disable + ERROR: u1, + }), base_address + 0x14); + + /// address: 0x40003016 + /// I2CS Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Stop Received Interrupt Enable + PREC: u1, + /// Address Match Interrupt Enable + AMATCH: u1, + /// Data Interrupt Enable + DRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Combined Error Interrupt Enable + ERROR: u1, + }), base_address + 0x16); + + /// address: 0x40003018 + /// I2CS Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Stop Received Interrupt + PREC: u1, + /// Address Match Interrupt + AMATCH: u1, + /// Data Interrupt + DRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Combined Error Interrupt + ERROR: u1, + }), base_address + 0x18); + + /// address: 0x4000301a + /// I2CS Status + pub const STATUS = @intToPtr(*volatile Mmio(16, packed struct { + /// Bus Error + BUSERR: u1, + /// Transmit Collision + COLL: u1, + /// Received Not Acknowledge + RXNACK: u1, + /// Read/Write Direction + DIR: u1, + /// Repeated Start + SR: u1, + reserved0: u1, + /// SCL Low Timeout + LOWTOUT: u1, + /// Clock Hold + CLKHOLD: u1, + reserved1: u1, + /// Slave SCL Low Extend Timeout + SEXTTOUT: u1, + /// High Speed + HS: u1, + /// Transaction Length Error + LENERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x1a); + + /// address: 0x4000301c + /// I2CS Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset Synchronization Busy + SWRST: u1, + /// SERCOM Enable Synchronization Busy + ENABLE: u1, + reserved0: u1, + reserved1: u1, + /// Length Synchronization Busy + LENGTH: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x1c); + + /// address: 0x40003022 + /// I2CS Length + pub const LENGTH = @intToPtr(*volatile Mmio(16, packed struct { + /// Data Length + LEN: u8, + /// Data Length Enable + LENEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x22); + + /// address: 0x40003024 + /// I2CS Address + pub const ADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// General Call Address Enable + GENCEN: u1, + /// Address Value + ADDR: u10, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Ten Bit Addressing Enable + TENBITEN: u1, + reserved4: u1, + /// Address Mask + ADDRMASK: u10, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x24); + + /// address: 0x40003028 + /// I2CS Data + pub const DATA = @intToPtr(*volatile u32, base_address + 0x28); + }; + + /// SPI Slave Mode + pub const SPIS = struct { + /// address: 0x40003000 + /// SPIS Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Operating Mode + MODE: u3, + reserved0: u1, + reserved1: u1, + /// Run during Standby + RUNSTDBY: u1, + /// Immediate Buffer Overflow Notification + IBON: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Data Out Pinout + DOPO: u2, + reserved9: u1, + reserved10: u1, + /// Data In Pinout + DIPO: u2, + reserved11: u1, + reserved12: u1, + /// Frame Format + FORM: u4, + /// Clock Phase + CPHA: u1, + /// Clock Polarity + CPOL: u1, + /// Data Order + DORD: u1, + padding0: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// SPIS Control B + pub const CTRLB = @intToPtr(*volatile Mmio(32, packed struct { + /// Character Size + CHSIZE: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Data Preload Enable + PLOADEN: u1, + reserved3: u1, + reserved4: u1, + /// Slave Select Low Detect Enable + SSDE: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Master Slave Select Enable + MSSEN: u1, + /// Address Mode + AMODE: u2, + reserved8: u1, + /// Receiver Enable + RXEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x4); + + /// address: 0x40003008 + /// SPIS Control C + pub const CTRLC = @intToPtr(*volatile Mmio(32, packed struct { + /// Inter-Character Spacing + ICSPACE: u6, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + /// Data 32 Bit + DATA32B: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x8); + + /// address: 0x4000300c + /// SPIS Baud Rate + pub const BAUD = @intToPtr(*volatile u8, base_address + 0xc); + + /// address: 0x40003014 + /// SPIS Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt Disable + DRE: u1, + /// Transmit Complete Interrupt Disable + TXC: u1, + /// Receive Complete Interrupt Disable + RXC: u1, + /// Slave Select Low Interrupt Disable + SSL: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Combined Error Interrupt Disable + ERROR: u1, + }), base_address + 0x14); + + /// address: 0x40003016 + /// SPIS Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt Enable + DRE: u1, + /// Transmit Complete Interrupt Enable + TXC: u1, + /// Receive Complete Interrupt Enable + RXC: u1, + /// Slave Select Low Interrupt Enable + SSL: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Combined Error Interrupt Enable + ERROR: u1, + }), base_address + 0x16); + + /// address: 0x40003018 + /// SPIS Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt + DRE: u1, + /// Transmit Complete Interrupt + TXC: u1, + /// Receive Complete Interrupt + RXC: u1, + /// Slave Select Low Interrupt Flag + SSL: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Combined Error Interrupt + ERROR: u1, + }), base_address + 0x18); + + /// address: 0x4000301a + /// SPIS Status + pub const STATUS = @intToPtr(*volatile Mmio(16, packed struct { + reserved0: u1, + reserved1: u1, + /// Buffer Overflow + BUFOVF: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Transaction Length Error + LENERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x1a); + + /// address: 0x4000301c + /// SPIS Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset Synchronization Busy + SWRST: u1, + /// SERCOM Enable Synchronization Busy + ENABLE: u1, + /// CTRLB Synchronization Busy + CTRLB: u1, + reserved0: u1, + /// LENGTH Synchronization Busy + LENGTH: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x1c); + + /// address: 0x40003022 + /// SPIS Length + pub const LENGTH = @intToPtr(*volatile Mmio(16, packed struct { + /// Data Length + LEN: u8, + /// Data Length Enable + LENEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x22); + + /// address: 0x40003024 + /// SPIS Address + pub const ADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Address Value + ADDR: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Address Mask + ADDRMASK: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x24); + + /// address: 0x40003028 + /// SPIS Data + pub const DATA = @intToPtr(*volatile u32, base_address + 0x28); + + /// address: 0x40003030 + /// SPIS Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Mode + DBGSTOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x30); + }; + + /// SPI Master Mode + pub const SPIM = struct { + /// address: 0x40003000 + /// SPIM Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Operating Mode + MODE: u3, + reserved0: u1, + reserved1: u1, + /// Run during Standby + RUNSTDBY: u1, + /// Immediate Buffer Overflow Notification + IBON: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Data Out Pinout + DOPO: u2, + reserved9: u1, + reserved10: u1, + /// Data In Pinout + DIPO: u2, + reserved11: u1, + reserved12: u1, + /// Frame Format + FORM: u4, + /// Clock Phase + CPHA: u1, + /// Clock Polarity + CPOL: u1, + /// Data Order + DORD: u1, + padding0: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// SPIM Control B + pub const CTRLB = @intToPtr(*volatile Mmio(32, packed struct { + /// Character Size + CHSIZE: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Data Preload Enable + PLOADEN: u1, + reserved3: u1, + reserved4: u1, + /// Slave Select Low Detect Enable + SSDE: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Master Slave Select Enable + MSSEN: u1, + /// Address Mode + AMODE: u2, + reserved8: u1, + /// Receiver Enable + RXEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x4); + + /// address: 0x40003008 + /// SPIM Control C + pub const CTRLC = @intToPtr(*volatile Mmio(32, packed struct { + /// Inter-Character Spacing + ICSPACE: u6, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + /// Data 32 Bit + DATA32B: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x8); + + /// address: 0x4000300c + /// SPIM Baud Rate + pub const BAUD = @intToPtr(*volatile u8, base_address + 0xc); + + /// address: 0x40003014 + /// SPIM Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt Disable + DRE: u1, + /// Transmit Complete Interrupt Disable + TXC: u1, + /// Receive Complete Interrupt Disable + RXC: u1, + /// Slave Select Low Interrupt Disable + SSL: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Combined Error Interrupt Disable + ERROR: u1, + }), base_address + 0x14); + + /// address: 0x40003016 + /// SPIM Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt Enable + DRE: u1, + /// Transmit Complete Interrupt Enable + TXC: u1, + /// Receive Complete Interrupt Enable + RXC: u1, + /// Slave Select Low Interrupt Enable + SSL: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Combined Error Interrupt Enable + ERROR: u1, + }), base_address + 0x16); + + /// address: 0x40003018 + /// SPIM Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt + DRE: u1, + /// Transmit Complete Interrupt + TXC: u1, + /// Receive Complete Interrupt + RXC: u1, + /// Slave Select Low Interrupt Flag + SSL: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Combined Error Interrupt + ERROR: u1, + }), base_address + 0x18); + + /// address: 0x4000301a + /// SPIM Status + pub const STATUS = @intToPtr(*volatile Mmio(16, packed struct { + reserved0: u1, + reserved1: u1, + /// Buffer Overflow + BUFOVF: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Transaction Length Error + LENERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x1a); + + /// address: 0x4000301c + /// SPIM Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset Synchronization Busy + SWRST: u1, + /// SERCOM Enable Synchronization Busy + ENABLE: u1, + /// CTRLB Synchronization Busy + CTRLB: u1, + reserved0: u1, + /// LENGTH Synchronization Busy + LENGTH: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x1c); + + /// address: 0x40003022 + /// SPIM Length + pub const LENGTH = @intToPtr(*volatile Mmio(16, packed struct { + /// Data Length + LEN: u8, + /// Data Length Enable + LENEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x22); + + /// address: 0x40003024 + /// SPIM Address + pub const ADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Address Value + ADDR: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Address Mask + ADDRMASK: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x24); + + /// address: 0x40003028 + /// SPIM Data + pub const DATA = @intToPtr(*volatile u32, base_address + 0x28); + + /// address: 0x40003030 + /// SPIM Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Mode + DBGSTOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x30); + }; + + /// USART EXTERNAL CLOCK Mode + pub const USART_EXT = struct { + /// address: 0x40003000 + /// USART_EXT Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Operating Mode + MODE: u3, + reserved0: u1, + reserved1: u1, + /// Run during Standby + RUNSTDBY: u1, + /// Immediate Buffer Overflow Notification + IBON: u1, + /// Transmit Data Invert + TXINV: u1, + /// Receive Data Invert + RXINV: u1, + reserved2: u1, + reserved3: u1, + /// Sample + SAMPR: u3, + /// Transmit Data Pinout + TXPO: u2, + reserved4: u1, + reserved5: u1, + /// Receive Data Pinout + RXPO: u2, + /// Sample Adjustment + SAMPA: u2, + /// Frame Format + FORM: u4, + /// Communication Mode + CMODE: u1, + /// Clock Polarity + CPOL: u1, + /// Data Order + DORD: u1, + padding0: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// USART_EXT Control B + pub const CTRLB = @intToPtr(*volatile Mmio(32, packed struct { + /// Character Size + CHSIZE: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Stop Bit Mode + SBMODE: u1, + reserved3: u1, + /// Collision Detection Enable + COLDEN: u1, + /// Start of Frame Detection Enable + SFDE: u1, + /// Encoding Format + ENC: u1, + reserved4: u1, + reserved5: u1, + /// Parity Mode + PMODE: u1, + reserved6: u1, + reserved7: u1, + /// Transmitter Enable + TXEN: u1, + /// Receiver Enable + RXEN: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// LIN Command + LINCMD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x4); + + /// address: 0x40003008 + /// USART_EXT Control C + pub const CTRLC = @intToPtr(*volatile Mmio(32, packed struct { + /// Guard Time + GTIME: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// LIN Master Break Length + BRKLEN: u2, + /// LIN Master Header Delay + HDRDLY: u2, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Inhibit Not Acknowledge + INACK: u1, + /// Disable Successive NACK + DSNACK: u1, + reserved9: u1, + reserved10: u1, + /// Maximum Iterations + MAXITER: u3, + reserved11: u1, + /// Data 32 Bit + DATA32B: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x8); + + /// address: 0x4000300c + /// USART_EXT Baud Rate + pub const BAUD = @intToPtr(*volatile u16, base_address + 0xc); + + /// address: 0x4000300c + /// USART_EXT Baud Rate + pub const BAUD_FRAC_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Baud Rate Value + BAUD: u13, + /// Fractional Part + FP: u3, + }), base_address + 0xc); + + /// address: 0x4000300c + /// USART_EXT Baud Rate + pub const BAUD_FRACFP_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Baud Rate Value + BAUD: u13, + /// Fractional Part + FP: u3, + }), base_address + 0xc); + + /// address: 0x4000300c + /// USART_EXT Baud Rate + pub const BAUD_USARTFP_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Baud Rate Value + BAUD: u16, + }), base_address + 0xc); + + /// address: 0x4000300e + /// USART_EXT Receive Pulse Length + pub const RXPL = @intToPtr(*volatile u8, base_address + 0xe); + + /// address: 0x40003014 + /// USART_EXT Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt Disable + DRE: u1, + /// Transmit Complete Interrupt Disable + TXC: u1, + /// Receive Complete Interrupt Disable + RXC: u1, + /// Receive Start Interrupt Disable + RXS: u1, + /// Clear To Send Input Change Interrupt Disable + CTSIC: u1, + /// Break Received Interrupt Disable + RXBRK: u1, + reserved0: u1, + /// Combined Error Interrupt Disable + ERROR: u1, + }), base_address + 0x14); + + /// address: 0x40003016 + /// USART_EXT Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt Enable + DRE: u1, + /// Transmit Complete Interrupt Enable + TXC: u1, + /// Receive Complete Interrupt Enable + RXC: u1, + /// Receive Start Interrupt Enable + RXS: u1, + /// Clear To Send Input Change Interrupt Enable + CTSIC: u1, + /// Break Received Interrupt Enable + RXBRK: u1, + reserved0: u1, + /// Combined Error Interrupt Enable + ERROR: u1, + }), base_address + 0x16); + + /// address: 0x40003018 + /// USART_EXT Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt + DRE: u1, + /// Transmit Complete Interrupt + TXC: u1, + /// Receive Complete Interrupt + RXC: u1, + /// Receive Start Interrupt + RXS: u1, + /// Clear To Send Input Change Interrupt + CTSIC: u1, + /// Break Received Interrupt + RXBRK: u1, + reserved0: u1, + /// Combined Error Interrupt + ERROR: u1, + }), base_address + 0x18); + + /// address: 0x4000301a + /// USART_EXT Status + pub const STATUS = @intToPtr(*volatile Mmio(16, packed struct { + /// Parity Error + PERR: u1, + /// Frame Error + FERR: u1, + /// Buffer Overflow + BUFOVF: u1, + /// Clear To Send + CTS: u1, + /// Inconsistent Sync Field + ISF: u1, + /// Collision Detected + COLL: u1, + /// Transmitter Empty + TXE: u1, + /// Maximum Number of Repetitions Reached + ITER: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x1a); + + /// address: 0x4000301c + /// USART_EXT Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset Synchronization Busy + SWRST: u1, + /// SERCOM Enable Synchronization Busy + ENABLE: u1, + /// CTRLB Synchronization Busy + CTRLB: u1, + /// RXERRCNT Synchronization Busy + RXERRCNT: u1, + /// LENGTH Synchronization Busy + LENGTH: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x1c); + + /// address: 0x40003020 + /// USART_EXT Receive Error Count + pub const RXERRCNT = @intToPtr(*volatile u8, base_address + 0x20); + + /// address: 0x40003022 + /// USART_EXT Length + pub const LENGTH = @intToPtr(*volatile Mmio(16, packed struct { + /// Data Length + LEN: u8, + /// Data Length Enable + LENEN: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x22); + + /// address: 0x40003028 + /// USART_EXT Data + pub const DATA = @intToPtr(*volatile u32, base_address + 0x28); + + /// address: 0x40003030 + /// USART_EXT Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Mode + DBGSTOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x30); + }; + + /// USART INTERNAL CLOCK Mode + pub const USART_INT = struct { + /// address: 0x40003000 + /// USART_INT Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Operating Mode + MODE: u3, + reserved0: u1, + reserved1: u1, + /// Run during Standby + RUNSTDBY: u1, + /// Immediate Buffer Overflow Notification + IBON: u1, + /// Transmit Data Invert + TXINV: u1, + /// Receive Data Invert + RXINV: u1, + reserved2: u1, + reserved3: u1, + /// Sample + SAMPR: u3, + /// Transmit Data Pinout + TXPO: u2, + reserved4: u1, + reserved5: u1, + /// Receive Data Pinout + RXPO: u2, + /// Sample Adjustment + SAMPA: u2, + /// Frame Format + FORM: u4, + /// Communication Mode + CMODE: u1, + /// Clock Polarity + CPOL: u1, + /// Data Order + DORD: u1, + padding0: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// USART_INT Control B + pub const CTRLB = @intToPtr(*volatile Mmio(32, packed struct { + /// Character Size + CHSIZE: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Stop Bit Mode + SBMODE: u1, + reserved3: u1, + /// Collision Detection Enable + COLDEN: u1, + /// Start of Frame Detection Enable + SFDE: u1, + /// Encoding Format + ENC: u1, + reserved4: u1, + reserved5: u1, + /// Parity Mode + PMODE: u1, + reserved6: u1, + reserved7: u1, + /// Transmitter Enable + TXEN: u1, + /// Receiver Enable + RXEN: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// LIN Command + LINCMD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x4); + + /// address: 0x40003008 + /// USART_INT Control C + pub const CTRLC = @intToPtr(*volatile Mmio(32, packed struct { + /// Guard Time + GTIME: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// LIN Master Break Length + BRKLEN: u2, + /// LIN Master Header Delay + HDRDLY: u2, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Inhibit Not Acknowledge + INACK: u1, + /// Disable Successive NACK + DSNACK: u1, + reserved9: u1, + reserved10: u1, + /// Maximum Iterations + MAXITER: u3, + reserved11: u1, + /// Data 32 Bit + DATA32B: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x8); + + /// address: 0x4000300c + /// USART_INT Baud Rate + pub const BAUD = @intToPtr(*volatile u16, base_address + 0xc); + + /// address: 0x4000300c + /// USART_INT Baud Rate + pub const BAUD_FRAC_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Baud Rate Value + BAUD: u13, + /// Fractional Part + FP: u3, + }), base_address + 0xc); + + /// address: 0x4000300c + /// USART_INT Baud Rate + pub const BAUD_FRACFP_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Baud Rate Value + BAUD: u13, + /// Fractional Part + FP: u3, + }), base_address + 0xc); + + /// address: 0x4000300c + /// USART_INT Baud Rate + pub const BAUD_USARTFP_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Baud Rate Value + BAUD: u16, + }), base_address + 0xc); + + /// address: 0x4000300e + /// USART_INT Receive Pulse Length + pub const RXPL = @intToPtr(*volatile u8, base_address + 0xe); + + /// address: 0x40003014 + /// USART_INT Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt Disable + DRE: u1, + /// Transmit Complete Interrupt Disable + TXC: u1, + /// Receive Complete Interrupt Disable + RXC: u1, + /// Receive Start Interrupt Disable + RXS: u1, + /// Clear To Send Input Change Interrupt Disable + CTSIC: u1, + /// Break Received Interrupt Disable + RXBRK: u1, + reserved0: u1, + /// Combined Error Interrupt Disable + ERROR: u1, + }), base_address + 0x14); + + /// address: 0x40003016 + /// USART_INT Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt Enable + DRE: u1, + /// Transmit Complete Interrupt Enable + TXC: u1, + /// Receive Complete Interrupt Enable + RXC: u1, + /// Receive Start Interrupt Enable + RXS: u1, + /// Clear To Send Input Change Interrupt Enable + CTSIC: u1, + /// Break Received Interrupt Enable + RXBRK: u1, + reserved0: u1, + /// Combined Error Interrupt Enable + ERROR: u1, + }), base_address + 0x16); + + /// address: 0x40003018 + /// USART_INT Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt + DRE: u1, + /// Transmit Complete Interrupt + TXC: u1, + /// Receive Complete Interrupt + RXC: u1, + /// Receive Start Interrupt + RXS: u1, + /// Clear To Send Input Change Interrupt + CTSIC: u1, + /// Break Received Interrupt + RXBRK: u1, + reserved0: u1, + /// Combined Error Interrupt + ERROR: u1, + }), base_address + 0x18); + + /// address: 0x4000301a + /// USART_INT Status + pub const STATUS = @intToPtr(*volatile Mmio(16, packed struct { + /// Parity Error + PERR: u1, + /// Frame Error + FERR: u1, + /// Buffer Overflow + BUFOVF: u1, + /// Clear To Send + CTS: u1, + /// Inconsistent Sync Field + ISF: u1, + /// Collision Detected + COLL: u1, + /// Transmitter Empty + TXE: u1, + /// Maximum Number of Repetitions Reached + ITER: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x1a); + + /// address: 0x4000301c + /// USART_INT Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset Synchronization Busy + SWRST: u1, + /// SERCOM Enable Synchronization Busy + ENABLE: u1, + /// CTRLB Synchronization Busy + CTRLB: u1, + /// RXERRCNT Synchronization Busy + RXERRCNT: u1, + /// LENGTH Synchronization Busy + LENGTH: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x1c); + + /// address: 0x40003020 + /// USART_INT Receive Error Count + pub const RXERRCNT = @intToPtr(*volatile u8, base_address + 0x20); + + /// address: 0x40003022 + /// USART_INT Length + pub const LENGTH = @intToPtr(*volatile Mmio(16, packed struct { + /// Data Length + LEN: u8, + /// Data Length Enable + LENEN: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x22); + + /// address: 0x40003028 + /// USART_INT Data + pub const DATA = @intToPtr(*volatile u32, base_address + 0x28); + + /// address: 0x40003030 + /// USART_INT Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Mode + DBGSTOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x30); + }; + }; + pub const SERCOM1 = struct { + pub const base_address = 0x40003400; + }; + pub const SERCOM2 = struct { + pub const base_address = 0x41012000; + }; + pub const SERCOM3 = struct { + pub const base_address = 0x41014000; + }; + pub const SERCOM4 = struct { + pub const base_address = 0x43000000; + }; + pub const SERCOM5 = struct { + pub const base_address: usize = 0x43000400; + + pub const USART_INT = struct { + /// address: 0x40003000 + /// USART_INT Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Operating Mode + MODE: u3, + reserved0: u1, + reserved1: u1, + /// Run during Standby + RUNSTDBY: u1, + /// Immediate Buffer Overflow Notification + IBON: u1, + /// Transmit Data Invert + TXINV: u1, + /// Receive Data Invert + RXINV: u1, + reserved2: u1, + reserved3: u1, + /// Sample + SAMPR: u3, + /// Transmit Data Pinout + TXPO: u2, + reserved4: u1, + reserved5: u1, + /// Receive Data Pinout + RXPO: u2, + /// Sample Adjustment + SAMPA: u2, + /// Frame Format + FORM: u4, + /// Communication Mode + CMODE: u1, + /// Clock Polarity + CPOL: u1, + /// Data Order + DORD: u1, + padding0: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// USART_INT Control B + pub const CTRLB = @intToPtr(*volatile Mmio(32, packed struct { + /// Character Size + CHSIZE: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Stop Bit Mode + SBMODE: u1, + reserved3: u1, + /// Collision Detection Enable + COLDEN: u1, + /// Start of Frame Detection Enable + SFDE: u1, + /// Encoding Format + ENC: u1, + reserved4: u1, + reserved5: u1, + /// Parity Mode + PMODE: u1, + reserved6: u1, + reserved7: u1, + /// Transmitter Enable + TXEN: u1, + /// Receiver Enable + RXEN: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// LIN Command + LINCMD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x4); + + /// address: 0x40003008 + /// USART_INT Control C + pub const CTRLC = @intToPtr(*volatile Mmio(32, packed struct { + /// Guard Time + GTIME: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// LIN Master Break Length + BRKLEN: u2, + /// LIN Master Header Delay + HDRDLY: u2, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Inhibit Not Acknowledge + INACK: u1, + /// Disable Successive NACK + DSNACK: u1, + reserved9: u1, + reserved10: u1, + /// Maximum Iterations + MAXITER: u3, + reserved11: u1, + /// Data 32 Bit + DATA32B: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x8); + + /// address: 0x4000300c + /// USART_INT Baud Rate + pub const BAUD = @intToPtr(*volatile u16, base_address + 0xc); + + /// address: 0x4000300c + /// USART_INT Baud Rate + pub const BAUD_FRAC_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Baud Rate Value + BAUD: u13, + /// Fractional Part + FP: u3, + }), base_address + 0xc); + + /// address: 0x4000300c + /// USART_INT Baud Rate + pub const BAUD_FRACFP_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Baud Rate Value + BAUD: u13, + /// Fractional Part + FP: u3, + }), base_address + 0xc); + + /// address: 0x4000300c + /// USART_INT Baud Rate + pub const BAUD_USARTFP_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Baud Rate Value + BAUD: u16, + }), base_address + 0xc); + + /// address: 0x4000300e + /// USART_INT Receive Pulse Length + pub const RXPL = @intToPtr(*volatile u8, base_address + 0xe); + + /// address: 0x40003014 + /// USART_INT Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt Disable + DRE: u1, + /// Transmit Complete Interrupt Disable + TXC: u1, + /// Receive Complete Interrupt Disable + RXC: u1, + /// Receive Start Interrupt Disable + RXS: u1, + /// Clear To Send Input Change Interrupt Disable + CTSIC: u1, + /// Break Received Interrupt Disable + RXBRK: u1, + reserved0: u1, + /// Combined Error Interrupt Disable + ERROR: u1, + }), base_address + 0x14); + + /// address: 0x40003016 + /// USART_INT Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt Enable + DRE: u1, + /// Transmit Complete Interrupt Enable + TXC: u1, + /// Receive Complete Interrupt Enable + RXC: u1, + /// Receive Start Interrupt Enable + RXS: u1, + /// Clear To Send Input Change Interrupt Enable + CTSIC: u1, + /// Break Received Interrupt Enable + RXBRK: u1, + reserved0: u1, + /// Combined Error Interrupt Enable + ERROR: u1, + }), base_address + 0x16); + + /// address: 0x40003018 + /// USART_INT Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt + DRE: u1, + /// Transmit Complete Interrupt + TXC: u1, + /// Receive Complete Interrupt + RXC: u1, + /// Receive Start Interrupt + RXS: u1, + /// Clear To Send Input Change Interrupt + CTSIC: u1, + /// Break Received Interrupt + RXBRK: u1, + reserved0: u1, + /// Combined Error Interrupt + ERROR: u1, + }), base_address + 0x18); + + /// address: 0x4000301a + /// USART_INT Status + pub const STATUS = @intToPtr(*volatile Mmio(16, packed struct { + /// Parity Error + PERR: u1, + /// Frame Error + FERR: u1, + /// Buffer Overflow + BUFOVF: u1, + /// Clear To Send + CTS: u1, + /// Inconsistent Sync Field + ISF: u1, + /// Collision Detected + COLL: u1, + /// Transmitter Empty + TXE: u1, + /// Maximum Number of Repetitions Reached + ITER: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x1a); + + /// address: 0x4000301c + /// USART_INT Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset Synchronization Busy + SWRST: u1, + /// SERCOM Enable Synchronization Busy + ENABLE: u1, + /// CTRLB Synchronization Busy + CTRLB: u1, + /// RXERRCNT Synchronization Busy + RXERRCNT: u1, + /// LENGTH Synchronization Busy + LENGTH: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x1c); + + /// address: 0x40003020 + /// USART_INT Receive Error Count + pub const RXERRCNT = @intToPtr(*volatile u8, base_address + 0x20); + + /// address: 0x40003022 + /// USART_INT Length + pub const LENGTH = @intToPtr(*volatile Mmio(16, packed struct { + /// Data Length + LEN: u8, + /// Data Length Enable + LENEN: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x22); + + /// address: 0x40003028 + /// USART_INT Data + pub const DATA = @intToPtr(*volatile u32, base_address + 0x28); + + /// address: 0x40003030 + /// USART_INT Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Mode + DBGSTOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x30); + }; + }; + + /// Supply Controller + pub const SUPC = struct { + pub const base_address = 0x40001800; + pub const version = "U24071.1.0"; + + /// address: 0x40001800 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// BOD33 Ready + BOD33RDY: u1, + /// BOD33 Detection + BOD33DET: u1, + /// BOD33 Synchronization Ready + B33SRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Voltage Regulator Ready + VREGRDY: u1, + reserved5: u1, + /// VDDCORE Ready + VCORERDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x0); + + /// address: 0x40001804 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { + /// BOD33 Ready + BOD33RDY: u1, + /// BOD33 Detection + BOD33DET: u1, + /// BOD33 Synchronization Ready + B33SRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Voltage Regulator Ready + VREGRDY: u1, + reserved5: u1, + /// VDDCORE Ready + VCORERDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x4); + + /// address: 0x40001808 + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { + /// BOD33 Ready + BOD33RDY: u1, + /// BOD33 Detection + BOD33DET: u1, + /// BOD33 Synchronization Ready + B33SRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Voltage Regulator Ready + VREGRDY: u1, + reserved5: u1, + /// VDDCORE Ready + VCORERDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x8); + + /// address: 0x4000180c + /// Power and Clocks Status + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// BOD33 Ready + BOD33RDY: u1, + /// BOD33 Detection + BOD33DET: u1, + /// BOD33 Synchronization Ready + B33SRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Voltage Regulator Ready + VREGRDY: u1, + reserved5: u1, + /// VDDCORE Ready + VCORERDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0xc); + + /// address: 0x40001810 + /// BOD33 Control + pub const BOD33 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Enable + ENABLE: u1, + /// Action when Threshold Crossed + ACTION: u2, + /// Configuration in Standby mode + STDBYCFG: u1, + /// Run in Standby mode + RUNSTDBY: u1, + /// Run in Hibernate mode + RUNHIB: u1, + /// Run in Backup mode + RUNBKUP: u1, + /// Hysteresis value + HYST: u4, + /// Prescaler Select + PSEL: u3, + reserved1: u1, + /// Threshold Level for VDD + LEVEL: u8, + /// Threshold Level in battery backup sleep mode for VBAT + VBATLEVEL: u8, + }), base_address + 0x10); + + /// address: 0x40001818 + /// VREG Control + pub const VREG = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Enable + ENABLE: u1, + /// Voltage Regulator Selection + SEL: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Run in Backup mode + RUNBKUP: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Voltage Scaling Enable + VSEN: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + /// Voltage Scaling Period + VSPER: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x18); + + /// address: 0x4000181c + /// VREF Control + pub const VREF = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Temperature Sensor Output Enable + TSEN: u1, + /// Voltage Reference Output Enable + VREFOE: u1, + /// Temperature Sensor Selection + TSSEL: u1, + reserved1: u1, + reserved2: u1, + /// Run during Standby + RUNSTDBY: u1, + /// On Demand Contrl + ONDEMAND: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// Voltage Reference Selection + SEL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x1c); + + /// address: 0x40001820 + /// Battery Backup Power Switch + pub const BBPS = @intToPtr(*volatile Mmio(32, packed struct { + /// Battery Backup Configuration + CONF: u1, + reserved0: u1, + /// Wake Enable + WAKEEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x20); + + /// address: 0x40001824 + /// Backup Output Control + pub const BKOUT = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable OUT0 + ENOUT0: u1, + /// Enable OUT1 + ENOUT1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Clear OUT0 + CLROUT0: u1, + /// Clear OUT1 + CLROUT1: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Set OUT0 + SETOUT0: u1, + /// Set OUT1 + SETOUT1: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + /// RTC Toggle OUT0 + RTCTGLOUT0: u1, + /// RTC Toggle OUT1 + RTCTGLOUT1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x24); + + /// address: 0x40001828 + /// Backup Input Control + pub const BKIN = @intToPtr(*volatile Mmio(32, packed struct { + /// Backup Input 0 + BKIN0: u1, + /// Backup Input 1 + BKIN1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x28); + }; + + /// Basic Timer Counter + pub const TC0 = struct { + pub const base_address = 0x40003800; + pub const version = "U22493.0.0"; + + /// 8-bit Counter Mode + pub const COUNT8 = struct { + /// address: 0x40003800 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Timer Counter Mode + MODE: u2, + /// Prescaler and Counter Synchronization + PRESCSYNC: u2, + /// Run during Standby + RUNSTDBY: u1, + /// Clock On Demand + ONDEMAND: u1, + /// Prescaler + PRESCALER: u3, + /// Auto Lock + ALOCK: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Capture Channel 0 Enable + CAPTEN0: u1, + /// Capture Channel 1 Enable + CAPTEN1: u1, + reserved4: u1, + reserved5: u1, + /// Capture On Pin 0 Enable + COPEN0: u1, + /// Capture On Pin 1 Enable + COPEN1: u1, + reserved6: u1, + reserved7: u1, + /// Capture Mode Channel 0 + CAPTMODE0: u2, + reserved8: u1, + /// Capture mode Channel 1 + CAPTMODE1: u2, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x0); + + /// address: 0x40003804 + /// Control B Clear + pub const CTRLBCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot on Counter + ONESHOT: u1, + reserved0: u1, + reserved1: u1, + /// Command + CMD: u3, + }), base_address + 0x4); + + /// address: 0x40003805 + /// Control B Set + pub const CTRLBSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot on Counter + ONESHOT: u1, + reserved0: u1, + reserved1: u1, + /// Command + CMD: u3, + }), base_address + 0x5); + + /// address: 0x40003806 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(16, packed struct { + /// Event Action + EVACT: u3, + reserved0: u1, + /// TC Event Input Polarity + TCINV: u1, + /// TC Event Enable + TCEI: u1, + reserved1: u1, + reserved2: u1, + /// Event Output Enable + OVFEO: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// MC Event Output Enable 0 + MCEO0: u1, + /// MC Event Output Enable 1 + MCEO1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x6); + + /// address: 0x40003808 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// OVF Interrupt Disable + OVF: u1, + /// ERR Interrupt Disable + ERR: u1, + reserved0: u1, + reserved1: u1, + /// MC Interrupt Disable 0 + MC0: u1, + /// MC Interrupt Disable 1 + MC1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x8); + + /// address: 0x40003809 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// OVF Interrupt Enable + OVF: u1, + /// ERR Interrupt Enable + ERR: u1, + reserved0: u1, + reserved1: u1, + /// MC Interrupt Enable 0 + MC0: u1, + /// MC Interrupt Enable 1 + MC1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x9); + + /// address: 0x4000380a + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// OVF Interrupt Flag + OVF: u1, + /// ERR Interrupt Flag + ERR: u1, + reserved0: u1, + reserved1: u1, + /// MC Interrupt Flag 0 + MC0: u1, + /// MC Interrupt Flag 1 + MC1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0xa); + + /// address: 0x4000380b + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { + /// Stop Status Flag + STOP: u1, + /// Slave Status Flag + SLAVE: u1, + reserved0: u1, + /// Synchronization Busy Status + PERBUFV: u1, + /// Compare channel buffer 0 valid + CCBUFV0: u1, + /// Compare channel buffer 1 valid + CCBUFV1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0xb); + + /// address: 0x4000380c + /// Waveform Generation Control + pub const WAVE = @intToPtr(*volatile Mmio(8, packed struct { + /// Waveform Generation Mode + WAVEGEN: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xc); + + /// address: 0x4000380d + /// Control C + pub const DRVCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Output Waveform Invert Enable 0 + INVEN0: u1, + /// Output Waveform Invert Enable 1 + INVEN1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xd); + + /// address: 0x4000380f + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Run During Debug + DBGRUN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0xf); + + /// address: 0x40003810 + /// Synchronization Status + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// swrst + SWRST: u1, + /// enable + ENABLE: u1, + /// CTRLB + CTRLB: u1, + /// STATUS + STATUS: u1, + /// Counter + COUNT: u1, + /// Period + PER: u1, + /// Compare Channel 0 + CC0: u1, + /// Compare Channel 1 + CC1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x10); + + /// address: 0x40003814 + /// COUNT8 Count + pub const COUNT = @intToPtr(*volatile u8, base_address + 0x14); + + /// address: 0x4000381b + /// COUNT8 Period + pub const PER = @intToPtr(*volatile u8, base_address + 0x1b); + + /// address: 0x4000381c + /// COUNT8 Compare and Capture + pub const CC = @intToPtr(*volatile [2]u8, base_address + 0x1c); + + /// address: 0x4000382f + /// COUNT8 Period Buffer + pub const PERBUF = @intToPtr(*volatile u8, base_address + 0x2f); + + /// address: 0x40003830 + /// COUNT8 Compare and Capture Buffer + pub const CCBUF = @intToPtr(*volatile [2]u8, base_address + 0x30); + }; + + /// 16-bit Counter Mode + pub const COUNT16 = struct { + /// address: 0x40003800 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Timer Counter Mode + MODE: u2, + /// Prescaler and Counter Synchronization + PRESCSYNC: u2, + /// Run during Standby + RUNSTDBY: u1, + /// Clock On Demand + ONDEMAND: u1, + /// Prescaler + PRESCALER: u3, + /// Auto Lock + ALOCK: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Capture Channel 0 Enable + CAPTEN0: u1, + /// Capture Channel 1 Enable + CAPTEN1: u1, + reserved4: u1, + reserved5: u1, + /// Capture On Pin 0 Enable + COPEN0: u1, + /// Capture On Pin 1 Enable + COPEN1: u1, + reserved6: u1, + reserved7: u1, + /// Capture Mode Channel 0 + CAPTMODE0: u2, + reserved8: u1, + /// Capture mode Channel 1 + CAPTMODE1: u2, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x0); + + /// address: 0x40003804 + /// Control B Clear + pub const CTRLBCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot on Counter + ONESHOT: u1, + reserved0: u1, + reserved1: u1, + /// Command + CMD: u3, + }), base_address + 0x4); + + /// address: 0x40003805 + /// Control B Set + pub const CTRLBSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot on Counter + ONESHOT: u1, + reserved0: u1, + reserved1: u1, + /// Command + CMD: u3, + }), base_address + 0x5); + + /// address: 0x40003806 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(16, packed struct { + /// Event Action + EVACT: u3, + reserved0: u1, + /// TC Event Input Polarity + TCINV: u1, + /// TC Event Enable + TCEI: u1, + reserved1: u1, + reserved2: u1, + /// Event Output Enable + OVFEO: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// MC Event Output Enable 0 + MCEO0: u1, + /// MC Event Output Enable 1 + MCEO1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x6); + + /// address: 0x40003808 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// OVF Interrupt Disable + OVF: u1, + /// ERR Interrupt Disable + ERR: u1, + reserved0: u1, + reserved1: u1, + /// MC Interrupt Disable 0 + MC0: u1, + /// MC Interrupt Disable 1 + MC1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x8); + + /// address: 0x40003809 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// OVF Interrupt Enable + OVF: u1, + /// ERR Interrupt Enable + ERR: u1, + reserved0: u1, + reserved1: u1, + /// MC Interrupt Enable 0 + MC0: u1, + /// MC Interrupt Enable 1 + MC1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x9); + + /// address: 0x4000380a + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// OVF Interrupt Flag + OVF: u1, + /// ERR Interrupt Flag + ERR: u1, + reserved0: u1, + reserved1: u1, + /// MC Interrupt Flag 0 + MC0: u1, + /// MC Interrupt Flag 1 + MC1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0xa); + + /// address: 0x4000380b + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { + /// Stop Status Flag + STOP: u1, + /// Slave Status Flag + SLAVE: u1, + reserved0: u1, + /// Synchronization Busy Status + PERBUFV: u1, + /// Compare channel buffer 0 valid + CCBUFV0: u1, + /// Compare channel buffer 1 valid + CCBUFV1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0xb); + + /// address: 0x4000380c + /// Waveform Generation Control + pub const WAVE = @intToPtr(*volatile Mmio(8, packed struct { + /// Waveform Generation Mode + WAVEGEN: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xc); + + /// address: 0x4000380d + /// Control C + pub const DRVCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Output Waveform Invert Enable 0 + INVEN0: u1, + /// Output Waveform Invert Enable 1 + INVEN1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xd); + + /// address: 0x4000380f + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Run During Debug + DBGRUN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0xf); + + /// address: 0x40003810 + /// Synchronization Status + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// swrst + SWRST: u1, + /// enable + ENABLE: u1, + /// CTRLB + CTRLB: u1, + /// STATUS + STATUS: u1, + /// Counter + COUNT: u1, + /// Period + PER: u1, + /// Compare Channel 0 + CC0: u1, + /// Compare Channel 1 + CC1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x10); + + /// address: 0x40003814 + /// COUNT16 Count + pub const COUNT = @intToPtr(*volatile u16, base_address + 0x14); + + /// address: 0x4000381c + /// COUNT16 Compare and Capture + pub const CC = @intToPtr(*volatile [2]u16, base_address + 0x1c); + + /// address: 0x40003830 + /// COUNT16 Compare and Capture Buffer + pub const CCBUF = @intToPtr(*volatile [2]u16, base_address + 0x30); + }; + + /// 32-bit Counter Mode + pub const COUNT32 = struct { + /// address: 0x40003800 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Timer Counter Mode + MODE: u2, + /// Prescaler and Counter Synchronization + PRESCSYNC: u2, + /// Run during Standby + RUNSTDBY: u1, + /// Clock On Demand + ONDEMAND: u1, + /// Prescaler + PRESCALER: u3, + /// Auto Lock + ALOCK: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Capture Channel 0 Enable + CAPTEN0: u1, + /// Capture Channel 1 Enable + CAPTEN1: u1, + reserved4: u1, + reserved5: u1, + /// Capture On Pin 0 Enable + COPEN0: u1, + /// Capture On Pin 1 Enable + COPEN1: u1, + reserved6: u1, + reserved7: u1, + /// Capture Mode Channel 0 + CAPTMODE0: u2, + reserved8: u1, + /// Capture mode Channel 1 + CAPTMODE1: u2, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x0); + + /// address: 0x40003804 + /// Control B Clear + pub const CTRLBCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot on Counter + ONESHOT: u1, + reserved0: u1, + reserved1: u1, + /// Command + CMD: u3, + }), base_address + 0x4); + + /// address: 0x40003805 + /// Control B Set + pub const CTRLBSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot on Counter + ONESHOT: u1, + reserved0: u1, + reserved1: u1, + /// Command + CMD: u3, + }), base_address + 0x5); + + /// address: 0x40003806 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(16, packed struct { + /// Event Action + EVACT: u3, + reserved0: u1, + /// TC Event Input Polarity + TCINV: u1, + /// TC Event Enable + TCEI: u1, + reserved1: u1, + reserved2: u1, + /// Event Output Enable + OVFEO: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// MC Event Output Enable 0 + MCEO0: u1, + /// MC Event Output Enable 1 + MCEO1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x6); + + /// address: 0x40003808 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// OVF Interrupt Disable + OVF: u1, + /// ERR Interrupt Disable + ERR: u1, + reserved0: u1, + reserved1: u1, + /// MC Interrupt Disable 0 + MC0: u1, + /// MC Interrupt Disable 1 + MC1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x8); + + /// address: 0x40003809 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// OVF Interrupt Enable + OVF: u1, + /// ERR Interrupt Enable + ERR: u1, + reserved0: u1, + reserved1: u1, + /// MC Interrupt Enable 0 + MC0: u1, + /// MC Interrupt Enable 1 + MC1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x9); + + /// address: 0x4000380a + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// OVF Interrupt Flag + OVF: u1, + /// ERR Interrupt Flag + ERR: u1, + reserved0: u1, + reserved1: u1, + /// MC Interrupt Flag 0 + MC0: u1, + /// MC Interrupt Flag 1 + MC1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0xa); + + /// address: 0x4000380b + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { + /// Stop Status Flag + STOP: u1, + /// Slave Status Flag + SLAVE: u1, + reserved0: u1, + /// Synchronization Busy Status + PERBUFV: u1, + /// Compare channel buffer 0 valid + CCBUFV0: u1, + /// Compare channel buffer 1 valid + CCBUFV1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0xb); + + /// address: 0x4000380c + /// Waveform Generation Control + pub const WAVE = @intToPtr(*volatile Mmio(8, packed struct { + /// Waveform Generation Mode + WAVEGEN: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xc); + + /// address: 0x4000380d + /// Control C + pub const DRVCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Output Waveform Invert Enable 0 + INVEN0: u1, + /// Output Waveform Invert Enable 1 + INVEN1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xd); + + /// address: 0x4000380f + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Run During Debug + DBGRUN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0xf); + + /// address: 0x40003810 + /// Synchronization Status + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// swrst + SWRST: u1, + /// enable + ENABLE: u1, + /// CTRLB + CTRLB: u1, + /// STATUS + STATUS: u1, + /// Counter + COUNT: u1, + /// Period + PER: u1, + /// Compare Channel 0 + CC0: u1, + /// Compare Channel 1 + CC1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x10); + + /// address: 0x40003814 + /// COUNT32 Count + pub const COUNT = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x4000381c + /// COUNT32 Compare and Capture + pub const CC = @intToPtr(*volatile [2]u32, base_address + 0x1c); + + /// address: 0x40003830 + /// COUNT32 Compare and Capture Buffer + pub const CCBUF = @intToPtr(*volatile [2]u32, base_address + 0x30); + }; + }; + pub const TC1 = struct { + pub const base_address = 0x40003c00; + }; + pub const TC2 = struct { + pub const base_address = 0x4101a000; + }; + pub const TC3 = struct { + pub const base_address = 0x4101c000; + }; + pub const TC4 = struct { + pub const base_address = 0x42001400; + }; + pub const TC5 = struct { + pub const base_address = 0x42001800; + }; + + /// Timer Counter Control + pub const TCC0 = struct { + pub const base_address = 0x41016000; + pub const version = "U22133.1.0"; + + /// address: 0x41016000 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Enhanced Resolution + RESOLUTION: u2, + reserved3: u1, + /// Prescaler + PRESCALER: u3, + /// Run in Standby + RUNSTDBY: u1, + /// Prescaler and Counter Synchronization Selection + PRESCSYNC: u2, + /// Auto Lock + ALOCK: u1, + /// Master Synchronization (only for TCC Slave Instance) + MSYNC: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// DMA One-shot Trigger Mode + DMAOS: u1, + /// Capture Channel 0 Enable + CPTEN0: u1, + /// Capture Channel 1 Enable + CPTEN1: u1, + /// Capture Channel 2 Enable + CPTEN2: u1, + /// Capture Channel 3 Enable + CPTEN3: u1, + /// Capture Channel 4 Enable + CPTEN4: u1, + /// Capture Channel 5 Enable + CPTEN5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x0); + + /// address: 0x41016004 + /// Control B Clear + pub const CTRLBCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot + ONESHOT: u1, + /// Ramp Index Command + IDXCMD: u2, + /// TCC Command + CMD: u3, + }), base_address + 0x4); + + /// address: 0x41016005 + /// Control B Set + pub const CTRLBSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot + ONESHOT: u1, + /// Ramp Index Command + IDXCMD: u2, + /// TCC Command + CMD: u3, + }), base_address + 0x5); + + /// address: 0x41016008 + /// Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Swrst Busy + SWRST: u1, + /// Enable Busy + ENABLE: u1, + /// Ctrlb Busy + CTRLB: u1, + /// Status Busy + STATUS: u1, + /// Count Busy + COUNT: u1, + /// Pattern Busy + PATT: u1, + /// Wave Busy + WAVE: u1, + /// Period Busy + PER: u1, + /// Compare Channel 0 Busy + CC0: u1, + /// Compare Channel 1 Busy + CC1: u1, + /// Compare Channel 2 Busy + CC2: u1, + /// Compare Channel 3 Busy + CC3: u1, + /// Compare Channel 4 Busy + CC4: u1, + /// Compare Channel 5 Busy + CC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x8); + + /// address: 0x4101600c + /// Recoverable Fault A Configuration + pub const FCTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Fault A Source + SRC: u2, + reserved0: u1, + /// Fault A Keeper + KEEP: u1, + /// Fault A Qualification + QUAL: u1, + /// Fault A Blanking Mode + BLANK: u2, + /// Fault A Restart + RESTART: u1, + /// Fault A Halt Mode + HALT: u2, + /// Fault A Capture Channel + CHSEL: u2, + /// Fault A Capture Action + CAPTURE: u3, + /// Fault A Blanking Prescaler + BLANKPRESC: u1, + /// Fault A Blanking Time + BLANKVAL: u8, + /// Fault A Filter Value + FILTERVAL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xc); + + /// address: 0x41016010 + /// Recoverable Fault B Configuration + pub const FCTRLB = @intToPtr(*volatile Mmio(32, packed struct { + /// Fault B Source + SRC: u2, + reserved0: u1, + /// Fault B Keeper + KEEP: u1, + /// Fault B Qualification + QUAL: u1, + /// Fault B Blanking Mode + BLANK: u2, + /// Fault B Restart + RESTART: u1, + /// Fault B Halt Mode + HALT: u2, + /// Fault B Capture Channel + CHSEL: u2, + /// Fault B Capture Action + CAPTURE: u3, + /// Fault B Blanking Prescaler + BLANKPRESC: u1, + /// Fault B Blanking Time + BLANKVAL: u8, + /// Fault B Filter Value + FILTERVAL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x10); + + /// address: 0x41016014 + /// Waveform Extension Configuration + pub const WEXCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Output Matrix + OTMX: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Dead-time Insertion Generator 0 Enable + DTIEN0: u1, + /// Dead-time Insertion Generator 1 Enable + DTIEN1: u1, + /// Dead-time Insertion Generator 2 Enable + DTIEN2: u1, + /// Dead-time Insertion Generator 3 Enable + DTIEN3: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Dead-time Low Side Outputs Value + DTLS: u8, + /// Dead-time High Side Outputs Value + DTHS: u8, + }), base_address + 0x14); + + /// address: 0x41016018 + /// Driver Control + pub const DRVCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Non-Recoverable State 0 Output Enable + NRE0: u1, + /// Non-Recoverable State 1 Output Enable + NRE1: u1, + /// Non-Recoverable State 2 Output Enable + NRE2: u1, + /// Non-Recoverable State 3 Output Enable + NRE3: u1, + /// Non-Recoverable State 4 Output Enable + NRE4: u1, + /// Non-Recoverable State 5 Output Enable + NRE5: u1, + /// Non-Recoverable State 6 Output Enable + NRE6: u1, + /// Non-Recoverable State 7 Output Enable + NRE7: u1, + /// Non-Recoverable State 0 Output Value + NRV0: u1, + /// Non-Recoverable State 1 Output Value + NRV1: u1, + /// Non-Recoverable State 2 Output Value + NRV2: u1, + /// Non-Recoverable State 3 Output Value + NRV3: u1, + /// Non-Recoverable State 4 Output Value + NRV4: u1, + /// Non-Recoverable State 5 Output Value + NRV5: u1, + /// Non-Recoverable State 6 Output Value + NRV6: u1, + /// Non-Recoverable State 7 Output Value + NRV7: u1, + /// Output Waveform 0 Inversion + INVEN0: u1, + /// Output Waveform 1 Inversion + INVEN1: u1, + /// Output Waveform 2 Inversion + INVEN2: u1, + /// Output Waveform 3 Inversion + INVEN3: u1, + /// Output Waveform 4 Inversion + INVEN4: u1, + /// Output Waveform 5 Inversion + INVEN5: u1, + /// Output Waveform 6 Inversion + INVEN6: u1, + /// Output Waveform 7 Inversion + INVEN7: u1, + /// Non-Recoverable Fault Input 0 Filter Value + FILTERVAL0: u4, + /// Non-Recoverable Fault Input 1 Filter Value + FILTERVAL1: u4, + }), base_address + 0x18); + + /// address: 0x4101601e + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Running Mode + DBGRUN: u1, + reserved0: u1, + /// Fault Detection on Debug Break Detection + FDDBD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x1e); + + /// address: 0x41016020 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Timer/counter Input Event0 Action + EVACT0: u3, + /// Timer/counter Input Event1 Action + EVACT1: u3, + /// Timer/counter Output Event Mode + CNTSEL: u2, + /// Overflow/Underflow Output Event Enable + OVFEO: u1, + /// Retrigger Output Event Enable + TRGEO: u1, + /// Timer/counter Output Event Enable + CNTEO: u1, + reserved0: u1, + /// Inverted Event 0 Input Enable + TCINV0: u1, + /// Inverted Event 1 Input Enable + TCINV1: u1, + /// Timer/counter Event 0 Input Enable + TCEI0: u1, + /// Timer/counter Event 1 Input Enable + TCEI1: u1, + /// Match or Capture Channel 0 Event Input Enable + MCEI0: u1, + /// Match or Capture Channel 1 Event Input Enable + MCEI1: u1, + /// Match or Capture Channel 2 Event Input Enable + MCEI2: u1, + /// Match or Capture Channel 3 Event Input Enable + MCEI3: u1, + /// Match or Capture Channel 4 Event Input Enable + MCEI4: u1, + /// Match or Capture Channel 5 Event Input Enable + MCEI5: u1, + reserved1: u1, + reserved2: u1, + /// Match or Capture Channel 0 Event Output Enable + MCEO0: u1, + /// Match or Capture Channel 1 Event Output Enable + MCEO1: u1, + /// Match or Capture Channel 2 Event Output Enable + MCEO2: u1, + /// Match or Capture Channel 3 Event Output Enable + MCEO3: u1, + /// Match or Capture Channel 4 Event Output Enable + MCEO4: u1, + /// Match or Capture Channel 5 Event Output Enable + MCEO5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x20); + + /// address: 0x41016024 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow Interrupt Enable + OVF: u1, + /// Retrigger Interrupt Enable + TRG: u1, + /// Counter Interrupt Enable + CNT: u1, + /// Error Interrupt Enable + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault Interrupt Enable + UFS: u1, + /// Non-Recoverable Debug Fault Interrupt Enable + DFS: u1, + /// Recoverable Fault A Interrupt Enable + FAULTA: u1, + /// Recoverable Fault B Interrupt Enable + FAULTB: u1, + /// Non-Recoverable Fault 0 Interrupt Enable + FAULT0: u1, + /// Non-Recoverable Fault 1 Interrupt Enable + FAULT1: u1, + /// Match or Capture Channel 0 Interrupt Enable + MC0: u1, + /// Match or Capture Channel 1 Interrupt Enable + MC1: u1, + /// Match or Capture Channel 2 Interrupt Enable + MC2: u1, + /// Match or Capture Channel 3 Interrupt Enable + MC3: u1, + /// Match or Capture Channel 4 Interrupt Enable + MC4: u1, + /// Match or Capture Channel 5 Interrupt Enable + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x24); + + /// address: 0x41016028 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow Interrupt Enable + OVF: u1, + /// Retrigger Interrupt Enable + TRG: u1, + /// Counter Interrupt Enable + CNT: u1, + /// Error Interrupt Enable + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault Interrupt Enable + UFS: u1, + /// Non-Recoverable Debug Fault Interrupt Enable + DFS: u1, + /// Recoverable Fault A Interrupt Enable + FAULTA: u1, + /// Recoverable Fault B Interrupt Enable + FAULTB: u1, + /// Non-Recoverable Fault 0 Interrupt Enable + FAULT0: u1, + /// Non-Recoverable Fault 1 Interrupt Enable + FAULT1: u1, + /// Match or Capture Channel 0 Interrupt Enable + MC0: u1, + /// Match or Capture Channel 1 Interrupt Enable + MC1: u1, + /// Match or Capture Channel 2 Interrupt Enable + MC2: u1, + /// Match or Capture Channel 3 Interrupt Enable + MC3: u1, + /// Match or Capture Channel 4 Interrupt Enable + MC4: u1, + /// Match or Capture Channel 5 Interrupt Enable + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x28); + + /// address: 0x4101602c + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow + OVF: u1, + /// Retrigger + TRG: u1, + /// Counter + CNT: u1, + /// Error + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault + UFS: u1, + /// Non-Recoverable Debug Fault + DFS: u1, + /// Recoverable Fault A + FAULTA: u1, + /// Recoverable Fault B + FAULTB: u1, + /// Non-Recoverable Fault 0 + FAULT0: u1, + /// Non-Recoverable Fault 1 + FAULT1: u1, + /// Match or Capture 0 + MC0: u1, + /// Match or Capture 1 + MC1: u1, + /// Match or Capture 2 + MC2: u1, + /// Match or Capture 3 + MC3: u1, + /// Match or Capture 4 + MC4: u1, + /// Match or Capture 5 + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x2c); + + /// address: 0x41016030 + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// Stop + STOP: u1, + /// Ramp + IDX: u1, + /// Non-recoverable Update Fault State + UFS: u1, + /// Non-Recoverable Debug Fault State + DFS: u1, + /// Slave + SLAVE: u1, + /// Pattern Buffer Valid + PATTBUFV: u1, + reserved0: u1, + /// Period Buffer Valid + PERBUFV: u1, + /// Recoverable Fault A Input + FAULTAIN: u1, + /// Recoverable Fault B Input + FAULTBIN: u1, + /// Non-Recoverable Fault0 Input + FAULT0IN: u1, + /// Non-Recoverable Fault1 Input + FAULT1IN: u1, + /// Recoverable Fault A State + FAULTA: u1, + /// Recoverable Fault B State + FAULTB: u1, + /// Non-Recoverable Fault 0 State + FAULT0: u1, + /// Non-Recoverable Fault 1 State + FAULT1: u1, + /// Compare Channel 0 Buffer Valid + CCBUFV0: u1, + /// Compare Channel 1 Buffer Valid + CCBUFV1: u1, + /// Compare Channel 2 Buffer Valid + CCBUFV2: u1, + /// Compare Channel 3 Buffer Valid + CCBUFV3: u1, + /// Compare Channel 4 Buffer Valid + CCBUFV4: u1, + /// Compare Channel 5 Buffer Valid + CCBUFV5: u1, + reserved1: u1, + reserved2: u1, + /// Compare Channel 0 Value + CMP0: u1, + /// Compare Channel 1 Value + CMP1: u1, + /// Compare Channel 2 Value + CMP2: u1, + /// Compare Channel 3 Value + CMP3: u1, + /// Compare Channel 4 Value + CMP4: u1, + /// Compare Channel 5 Value + CMP5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x30); + + /// address: 0x41016034 + /// Count + pub const COUNT = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x34); + + /// address: 0x41016034 + /// Count + pub const COUNT_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Counter Value + COUNT: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x41016034 + /// Count + pub const COUNT_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Counter Value + COUNT: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x41016034 + /// Count + pub const COUNT_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Counter Value + COUNT: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x41016038 + /// Pattern + pub const PATT = @intToPtr(*volatile Mmio(16, packed struct { + /// Pattern Generator 0 Output Enable + PGE0: u1, + /// Pattern Generator 1 Output Enable + PGE1: u1, + /// Pattern Generator 2 Output Enable + PGE2: u1, + /// Pattern Generator 3 Output Enable + PGE3: u1, + /// Pattern Generator 4 Output Enable + PGE4: u1, + /// Pattern Generator 5 Output Enable + PGE5: u1, + /// Pattern Generator 6 Output Enable + PGE6: u1, + /// Pattern Generator 7 Output Enable + PGE7: u1, + /// Pattern Generator 0 Output Value + PGV0: u1, + /// Pattern Generator 1 Output Value + PGV1: u1, + /// Pattern Generator 2 Output Value + PGV2: u1, + /// Pattern Generator 3 Output Value + PGV3: u1, + /// Pattern Generator 4 Output Value + PGV4: u1, + /// Pattern Generator 5 Output Value + PGV5: u1, + /// Pattern Generator 6 Output Value + PGV6: u1, + /// Pattern Generator 7 Output Value + PGV7: u1, + }), base_address + 0x38); + + /// address: 0x4101603c + /// Waveform Control + pub const WAVE = @intToPtr(*volatile Mmio(32, packed struct { + /// Waveform Generation + WAVEGEN: u3, + reserved0: u1, + /// Ramp Mode + RAMP: u2, + reserved1: u1, + /// Circular period Enable + CIPEREN: u1, + /// Circular Channel 0 Enable + CICCEN0: u1, + /// Circular Channel 1 Enable + CICCEN1: u1, + /// Circular Channel 2 Enable + CICCEN2: u1, + /// Circular Channel 3 Enable + CICCEN3: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Channel 0 Polarity + POL0: u1, + /// Channel 1 Polarity + POL1: u1, + /// Channel 2 Polarity + POL2: u1, + /// Channel 3 Polarity + POL3: u1, + /// Channel 4 Polarity + POL4: u1, + /// Channel 5 Polarity + POL5: u1, + reserved6: u1, + reserved7: u1, + /// Swap DTI Output Pair 0 + SWAP0: u1, + /// Swap DTI Output Pair 1 + SWAP1: u1, + /// Swap DTI Output Pair 2 + SWAP2: u1, + /// Swap DTI Output Pair 3 + SWAP3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x3c); + + /// address: 0x41016040 + /// Period + pub const PER = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x40); + + /// address: 0x41016040 + /// Period + pub const PER_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u4, + /// Period Value + PER: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x41016040 + /// Period + pub const PER_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u5, + /// Period Value + PER: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x41016040 + /// Period + pub const PER_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u6, + /// Period Value + PER: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x41016044 + /// Compare and Capture + pub const CC = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x44); + + /// address: 0x41016044 + /// Compare and Capture + pub const CC_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u4, + /// Channel Compare/Capture Value + CC: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x41016044 + /// Compare and Capture + pub const CC_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u5, + /// Channel Compare/Capture Value + CC: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x41016044 + /// Compare and Capture + pub const CC_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u6, + /// Channel Compare/Capture Value + CC: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x41016064 + /// Pattern Buffer + pub const PATTBUF = @intToPtr(*volatile Mmio(16, packed struct { + /// Pattern Generator 0 Output Enable Buffer + PGEB0: u1, + /// Pattern Generator 1 Output Enable Buffer + PGEB1: u1, + /// Pattern Generator 2 Output Enable Buffer + PGEB2: u1, + /// Pattern Generator 3 Output Enable Buffer + PGEB3: u1, + /// Pattern Generator 4 Output Enable Buffer + PGEB4: u1, + /// Pattern Generator 5 Output Enable Buffer + PGEB5: u1, + /// Pattern Generator 6 Output Enable Buffer + PGEB6: u1, + /// Pattern Generator 7 Output Enable Buffer + PGEB7: u1, + /// Pattern Generator 0 Output Enable + PGVB0: u1, + /// Pattern Generator 1 Output Enable + PGVB1: u1, + /// Pattern Generator 2 Output Enable + PGVB2: u1, + /// Pattern Generator 3 Output Enable + PGVB3: u1, + /// Pattern Generator 4 Output Enable + PGVB4: u1, + /// Pattern Generator 5 Output Enable + PGVB5: u1, + /// Pattern Generator 6 Output Enable + PGVB6: u1, + /// Pattern Generator 7 Output Enable + PGVB7: u1, + }), base_address + 0x64); + + /// address: 0x4101606c + /// Period Buffer + pub const PERBUF = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x6c); + + /// address: 0x4101606c + /// Period Buffer + pub const PERBUF_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u4, + /// Period Buffer Value + PERBUF: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x4101606c + /// Period Buffer + pub const PERBUF_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u5, + /// Period Buffer Value + PERBUF: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x4101606c + /// Period Buffer + pub const PERBUF_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u6, + /// Period Buffer Value + PERBUF: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x41016070 + /// Compare and Capture Buffer + pub const CCBUF = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x70); + + /// address: 0x41016070 + /// Compare and Capture Buffer + pub const CCBUF_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Channel Compare/Capture Buffer Value + CCBUF: u4, + /// Dithering Buffer Cycle Number + DITHERBUF: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + + /// address: 0x41016070 + /// Compare and Capture Buffer + pub const CCBUF_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u5, + /// Channel Compare/Capture Buffer Value + CCBUF: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + + /// address: 0x41016070 + /// Compare and Capture Buffer + pub const CCBUF_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u6, + /// Channel Compare/Capture Buffer Value + CCBUF: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + }; + pub const TCC1 = struct { + pub const base_address = 0x41018000; + + /// address: 0x41018000 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Enhanced Resolution + RESOLUTION: u2, + reserved3: u1, + /// Prescaler + PRESCALER: u3, + /// Run in Standby + RUNSTDBY: u1, + /// Prescaler and Counter Synchronization Selection + PRESCSYNC: u2, + /// Auto Lock + ALOCK: u1, + /// Master Synchronization (only for TCC Slave Instance) + MSYNC: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// DMA One-shot Trigger Mode + DMAOS: u1, + /// Capture Channel 0 Enable + CPTEN0: u1, + /// Capture Channel 1 Enable + CPTEN1: u1, + /// Capture Channel 2 Enable + CPTEN2: u1, + /// Capture Channel 3 Enable + CPTEN3: u1, + /// Capture Channel 4 Enable + CPTEN4: u1, + /// Capture Channel 5 Enable + CPTEN5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x0); + + /// address: 0x41018004 + /// Control B Clear + pub const CTRLBCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot + ONESHOT: u1, + /// Ramp Index Command + IDXCMD: u2, + /// TCC Command + CMD: u3, + }), base_address + 0x4); + + /// address: 0x41018005 + /// Control B Set + pub const CTRLBSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot + ONESHOT: u1, + /// Ramp Index Command + IDXCMD: u2, + /// TCC Command + CMD: u3, + }), base_address + 0x5); + + /// address: 0x41018008 + /// Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Swrst Busy + SWRST: u1, + /// Enable Busy + ENABLE: u1, + /// Ctrlb Busy + CTRLB: u1, + /// Status Busy + STATUS: u1, + /// Count Busy + COUNT: u1, + /// Pattern Busy + PATT: u1, + /// Wave Busy + WAVE: u1, + /// Period Busy + PER: u1, + /// Compare Channel 0 Busy + CC0: u1, + /// Compare Channel 1 Busy + CC1: u1, + /// Compare Channel 2 Busy + CC2: u1, + /// Compare Channel 3 Busy + CC3: u1, + /// Compare Channel 4 Busy + CC4: u1, + /// Compare Channel 5 Busy + CC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x8); + + /// address: 0x4101800c + /// Recoverable Fault A Configuration + pub const FCTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Fault A Source + SRC: u2, + reserved0: u1, + /// Fault A Keeper + KEEP: u1, + /// Fault A Qualification + QUAL: u1, + /// Fault A Blanking Mode + BLANK: u2, + /// Fault A Restart + RESTART: u1, + /// Fault A Halt Mode + HALT: u2, + /// Fault A Capture Channel + CHSEL: u2, + /// Fault A Capture Action + CAPTURE: u3, + /// Fault A Blanking Prescaler + BLANKPRESC: u1, + /// Fault A Blanking Time + BLANKVAL: u8, + /// Fault A Filter Value + FILTERVAL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xc); + + /// address: 0x41018010 + /// Recoverable Fault B Configuration + pub const FCTRLB = @intToPtr(*volatile Mmio(32, packed struct { + /// Fault B Source + SRC: u2, + reserved0: u1, + /// Fault B Keeper + KEEP: u1, + /// Fault B Qualification + QUAL: u1, + /// Fault B Blanking Mode + BLANK: u2, + /// Fault B Restart + RESTART: u1, + /// Fault B Halt Mode + HALT: u2, + /// Fault B Capture Channel + CHSEL: u2, + /// Fault B Capture Action + CAPTURE: u3, + /// Fault B Blanking Prescaler + BLANKPRESC: u1, + /// Fault B Blanking Time + BLANKVAL: u8, + /// Fault B Filter Value + FILTERVAL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x10); + + /// address: 0x41018014 + /// Waveform Extension Configuration + pub const WEXCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Output Matrix + OTMX: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Dead-time Insertion Generator 0 Enable + DTIEN0: u1, + /// Dead-time Insertion Generator 1 Enable + DTIEN1: u1, + /// Dead-time Insertion Generator 2 Enable + DTIEN2: u1, + /// Dead-time Insertion Generator 3 Enable + DTIEN3: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Dead-time Low Side Outputs Value + DTLS: u8, + /// Dead-time High Side Outputs Value + DTHS: u8, + }), base_address + 0x14); + + /// address: 0x41018018 + /// Driver Control + pub const DRVCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Non-Recoverable State 0 Output Enable + NRE0: u1, + /// Non-Recoverable State 1 Output Enable + NRE1: u1, + /// Non-Recoverable State 2 Output Enable + NRE2: u1, + /// Non-Recoverable State 3 Output Enable + NRE3: u1, + /// Non-Recoverable State 4 Output Enable + NRE4: u1, + /// Non-Recoverable State 5 Output Enable + NRE5: u1, + /// Non-Recoverable State 6 Output Enable + NRE6: u1, + /// Non-Recoverable State 7 Output Enable + NRE7: u1, + /// Non-Recoverable State 0 Output Value + NRV0: u1, + /// Non-Recoverable State 1 Output Value + NRV1: u1, + /// Non-Recoverable State 2 Output Value + NRV2: u1, + /// Non-Recoverable State 3 Output Value + NRV3: u1, + /// Non-Recoverable State 4 Output Value + NRV4: u1, + /// Non-Recoverable State 5 Output Value + NRV5: u1, + /// Non-Recoverable State 6 Output Value + NRV6: u1, + /// Non-Recoverable State 7 Output Value + NRV7: u1, + /// Output Waveform 0 Inversion + INVEN0: u1, + /// Output Waveform 1 Inversion + INVEN1: u1, + /// Output Waveform 2 Inversion + INVEN2: u1, + /// Output Waveform 3 Inversion + INVEN3: u1, + /// Output Waveform 4 Inversion + INVEN4: u1, + /// Output Waveform 5 Inversion + INVEN5: u1, + /// Output Waveform 6 Inversion + INVEN6: u1, + /// Output Waveform 7 Inversion + INVEN7: u1, + /// Non-Recoverable Fault Input 0 Filter Value + FILTERVAL0: u4, + /// Non-Recoverable Fault Input 1 Filter Value + FILTERVAL1: u4, + }), base_address + 0x18); + + /// address: 0x4101801e + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Running Mode + DBGRUN: u1, + reserved0: u1, + /// Fault Detection on Debug Break Detection + FDDBD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x1e); + + /// address: 0x41018020 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Timer/counter Input Event0 Action + EVACT0: u3, + /// Timer/counter Input Event1 Action + EVACT1: u3, + /// Timer/counter Output Event Mode + CNTSEL: u2, + /// Overflow/Underflow Output Event Enable + OVFEO: u1, + /// Retrigger Output Event Enable + TRGEO: u1, + /// Timer/counter Output Event Enable + CNTEO: u1, + reserved0: u1, + /// Inverted Event 0 Input Enable + TCINV0: u1, + /// Inverted Event 1 Input Enable + TCINV1: u1, + /// Timer/counter Event 0 Input Enable + TCEI0: u1, + /// Timer/counter Event 1 Input Enable + TCEI1: u1, + /// Match or Capture Channel 0 Event Input Enable + MCEI0: u1, + /// Match or Capture Channel 1 Event Input Enable + MCEI1: u1, + /// Match or Capture Channel 2 Event Input Enable + MCEI2: u1, + /// Match or Capture Channel 3 Event Input Enable + MCEI3: u1, + /// Match or Capture Channel 4 Event Input Enable + MCEI4: u1, + /// Match or Capture Channel 5 Event Input Enable + MCEI5: u1, + reserved1: u1, + reserved2: u1, + /// Match or Capture Channel 0 Event Output Enable + MCEO0: u1, + /// Match or Capture Channel 1 Event Output Enable + MCEO1: u1, + /// Match or Capture Channel 2 Event Output Enable + MCEO2: u1, + /// Match or Capture Channel 3 Event Output Enable + MCEO3: u1, + /// Match or Capture Channel 4 Event Output Enable + MCEO4: u1, + /// Match or Capture Channel 5 Event Output Enable + MCEO5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x20); + + /// address: 0x41018024 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow Interrupt Enable + OVF: u1, + /// Retrigger Interrupt Enable + TRG: u1, + /// Counter Interrupt Enable + CNT: u1, + /// Error Interrupt Enable + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault Interrupt Enable + UFS: u1, + /// Non-Recoverable Debug Fault Interrupt Enable + DFS: u1, + /// Recoverable Fault A Interrupt Enable + FAULTA: u1, + /// Recoverable Fault B Interrupt Enable + FAULTB: u1, + /// Non-Recoverable Fault 0 Interrupt Enable + FAULT0: u1, + /// Non-Recoverable Fault 1 Interrupt Enable + FAULT1: u1, + /// Match or Capture Channel 0 Interrupt Enable + MC0: u1, + /// Match or Capture Channel 1 Interrupt Enable + MC1: u1, + /// Match or Capture Channel 2 Interrupt Enable + MC2: u1, + /// Match or Capture Channel 3 Interrupt Enable + MC3: u1, + /// Match or Capture Channel 4 Interrupt Enable + MC4: u1, + /// Match or Capture Channel 5 Interrupt Enable + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x24); + + /// address: 0x41018028 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow Interrupt Enable + OVF: u1, + /// Retrigger Interrupt Enable + TRG: u1, + /// Counter Interrupt Enable + CNT: u1, + /// Error Interrupt Enable + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault Interrupt Enable + UFS: u1, + /// Non-Recoverable Debug Fault Interrupt Enable + DFS: u1, + /// Recoverable Fault A Interrupt Enable + FAULTA: u1, + /// Recoverable Fault B Interrupt Enable + FAULTB: u1, + /// Non-Recoverable Fault 0 Interrupt Enable + FAULT0: u1, + /// Non-Recoverable Fault 1 Interrupt Enable + FAULT1: u1, + /// Match or Capture Channel 0 Interrupt Enable + MC0: u1, + /// Match or Capture Channel 1 Interrupt Enable + MC1: u1, + /// Match or Capture Channel 2 Interrupt Enable + MC2: u1, + /// Match or Capture Channel 3 Interrupt Enable + MC3: u1, + /// Match or Capture Channel 4 Interrupt Enable + MC4: u1, + /// Match or Capture Channel 5 Interrupt Enable + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x28); + + /// address: 0x4101802c + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow + OVF: u1, + /// Retrigger + TRG: u1, + /// Counter + CNT: u1, + /// Error + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault + UFS: u1, + /// Non-Recoverable Debug Fault + DFS: u1, + /// Recoverable Fault A + FAULTA: u1, + /// Recoverable Fault B + FAULTB: u1, + /// Non-Recoverable Fault 0 + FAULT0: u1, + /// Non-Recoverable Fault 1 + FAULT1: u1, + /// Match or Capture 0 + MC0: u1, + /// Match or Capture 1 + MC1: u1, + /// Match or Capture 2 + MC2: u1, + /// Match or Capture 3 + MC3: u1, + /// Match or Capture 4 + MC4: u1, + /// Match or Capture 5 + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x2c); + + /// address: 0x41018030 + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// Stop + STOP: u1, + /// Ramp + IDX: u1, + /// Non-recoverable Update Fault State + UFS: u1, + /// Non-Recoverable Debug Fault State + DFS: u1, + /// Slave + SLAVE: u1, + /// Pattern Buffer Valid + PATTBUFV: u1, + reserved0: u1, + /// Period Buffer Valid + PERBUFV: u1, + /// Recoverable Fault A Input + FAULTAIN: u1, + /// Recoverable Fault B Input + FAULTBIN: u1, + /// Non-Recoverable Fault0 Input + FAULT0IN: u1, + /// Non-Recoverable Fault1 Input + FAULT1IN: u1, + /// Recoverable Fault A State + FAULTA: u1, + /// Recoverable Fault B State + FAULTB: u1, + /// Non-Recoverable Fault 0 State + FAULT0: u1, + /// Non-Recoverable Fault 1 State + FAULT1: u1, + /// Compare Channel 0 Buffer Valid + CCBUFV0: u1, + /// Compare Channel 1 Buffer Valid + CCBUFV1: u1, + /// Compare Channel 2 Buffer Valid + CCBUFV2: u1, + /// Compare Channel 3 Buffer Valid + CCBUFV3: u1, + /// Compare Channel 4 Buffer Valid + CCBUFV4: u1, + /// Compare Channel 5 Buffer Valid + CCBUFV5: u1, + reserved1: u1, + reserved2: u1, + /// Compare Channel 0 Value + CMP0: u1, + /// Compare Channel 1 Value + CMP1: u1, + /// Compare Channel 2 Value + CMP2: u1, + /// Compare Channel 3 Value + CMP3: u1, + /// Compare Channel 4 Value + CMP4: u1, + /// Compare Channel 5 Value + CMP5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x30); + + /// address: 0x41018034 + /// Count + pub const COUNT = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x34); + + /// address: 0x41018034 + /// Count + pub const COUNT_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Counter Value + COUNT: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x41018034 + /// Count + pub const COUNT_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Counter Value + COUNT: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x41018034 + /// Count + pub const COUNT_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Counter Value + COUNT: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x41018038 + /// Pattern + pub const PATT = @intToPtr(*volatile Mmio(16, packed struct { + /// Pattern Generator 0 Output Enable + PGE0: u1, + /// Pattern Generator 1 Output Enable + PGE1: u1, + /// Pattern Generator 2 Output Enable + PGE2: u1, + /// Pattern Generator 3 Output Enable + PGE3: u1, + /// Pattern Generator 4 Output Enable + PGE4: u1, + /// Pattern Generator 5 Output Enable + PGE5: u1, + /// Pattern Generator 6 Output Enable + PGE6: u1, + /// Pattern Generator 7 Output Enable + PGE7: u1, + /// Pattern Generator 0 Output Value + PGV0: u1, + /// Pattern Generator 1 Output Value + PGV1: u1, + /// Pattern Generator 2 Output Value + PGV2: u1, + /// Pattern Generator 3 Output Value + PGV3: u1, + /// Pattern Generator 4 Output Value + PGV4: u1, + /// Pattern Generator 5 Output Value + PGV5: u1, + /// Pattern Generator 6 Output Value + PGV6: u1, + /// Pattern Generator 7 Output Value + PGV7: u1, + }), base_address + 0x38); + + /// address: 0x4101803c + /// Waveform Control + pub const WAVE = @intToPtr(*volatile Mmio(32, packed struct { + /// Waveform Generation + WAVEGEN: u3, + reserved0: u1, + /// Ramp Mode + RAMP: u2, + reserved1: u1, + /// Circular period Enable + CIPEREN: u1, + /// Circular Channel 0 Enable + CICCEN0: u1, + /// Circular Channel 1 Enable + CICCEN1: u1, + /// Circular Channel 2 Enable + CICCEN2: u1, + /// Circular Channel 3 Enable + CICCEN3: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Channel 0 Polarity + POL0: u1, + /// Channel 1 Polarity + POL1: u1, + /// Channel 2 Polarity + POL2: u1, + /// Channel 3 Polarity + POL3: u1, + /// Channel 4 Polarity + POL4: u1, + /// Channel 5 Polarity + POL5: u1, + reserved6: u1, + reserved7: u1, + /// Swap DTI Output Pair 0 + SWAP0: u1, + /// Swap DTI Output Pair 1 + SWAP1: u1, + /// Swap DTI Output Pair 2 + SWAP2: u1, + /// Swap DTI Output Pair 3 + SWAP3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x3c); + + /// address: 0x41018040 + /// Period + pub const PER = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x40); + + /// address: 0x41018040 + /// Period + pub const PER_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u4, + /// Period Value + PER: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x41018040 + /// Period + pub const PER_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u5, + /// Period Value + PER: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x41018040 + /// Period + pub const PER_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u6, + /// Period Value + PER: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x41018044 + /// Compare and Capture + pub const CC = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x44); + + /// address: 0x41018044 + /// Compare and Capture + pub const CC_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u4, + /// Channel Compare/Capture Value + CC: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x41018044 + /// Compare and Capture + pub const CC_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u5, + /// Channel Compare/Capture Value + CC: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x41018044 + /// Compare and Capture + pub const CC_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u6, + /// Channel Compare/Capture Value + CC: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x41018064 + /// Pattern Buffer + pub const PATTBUF = @intToPtr(*volatile Mmio(16, packed struct { + /// Pattern Generator 0 Output Enable Buffer + PGEB0: u1, + /// Pattern Generator 1 Output Enable Buffer + PGEB1: u1, + /// Pattern Generator 2 Output Enable Buffer + PGEB2: u1, + /// Pattern Generator 3 Output Enable Buffer + PGEB3: u1, + /// Pattern Generator 4 Output Enable Buffer + PGEB4: u1, + /// Pattern Generator 5 Output Enable Buffer + PGEB5: u1, + /// Pattern Generator 6 Output Enable Buffer + PGEB6: u1, + /// Pattern Generator 7 Output Enable Buffer + PGEB7: u1, + /// Pattern Generator 0 Output Enable + PGVB0: u1, + /// Pattern Generator 1 Output Enable + PGVB1: u1, + /// Pattern Generator 2 Output Enable + PGVB2: u1, + /// Pattern Generator 3 Output Enable + PGVB3: u1, + /// Pattern Generator 4 Output Enable + PGVB4: u1, + /// Pattern Generator 5 Output Enable + PGVB5: u1, + /// Pattern Generator 6 Output Enable + PGVB6: u1, + /// Pattern Generator 7 Output Enable + PGVB7: u1, + }), base_address + 0x64); + + /// address: 0x4101806c + /// Period Buffer + pub const PERBUF = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x6c); + + /// address: 0x4101806c + /// Period Buffer + pub const PERBUF_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u4, + /// Period Buffer Value + PERBUF: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x4101806c + /// Period Buffer + pub const PERBUF_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u5, + /// Period Buffer Value + PERBUF: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x4101806c + /// Period Buffer + pub const PERBUF_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u6, + /// Period Buffer Value + PERBUF: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x41018070 + /// Compare and Capture Buffer + pub const CCBUF = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x70); + + /// address: 0x41018070 + /// Compare and Capture Buffer + pub const CCBUF_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Channel Compare/Capture Buffer Value + CCBUF: u4, + /// Dithering Buffer Cycle Number + DITHERBUF: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + + /// address: 0x41018070 + /// Compare and Capture Buffer + pub const CCBUF_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u5, + /// Channel Compare/Capture Buffer Value + CCBUF: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + + /// address: 0x41018070 + /// Compare and Capture Buffer + pub const CCBUF_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u6, + /// Channel Compare/Capture Buffer Value + CCBUF: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + }; + pub const TCC2 = struct { + pub const base_address = 0x42000c00; + + /// address: 0x42000c00 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Enhanced Resolution + RESOLUTION: u2, + reserved3: u1, + /// Prescaler + PRESCALER: u3, + /// Run in Standby + RUNSTDBY: u1, + /// Prescaler and Counter Synchronization Selection + PRESCSYNC: u2, + /// Auto Lock + ALOCK: u1, + /// Master Synchronization (only for TCC Slave Instance) + MSYNC: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// DMA One-shot Trigger Mode + DMAOS: u1, + /// Capture Channel 0 Enable + CPTEN0: u1, + /// Capture Channel 1 Enable + CPTEN1: u1, + /// Capture Channel 2 Enable + CPTEN2: u1, + /// Capture Channel 3 Enable + CPTEN3: u1, + /// Capture Channel 4 Enable + CPTEN4: u1, + /// Capture Channel 5 Enable + CPTEN5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x0); + + /// address: 0x42000c04 + /// Control B Clear + pub const CTRLBCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot + ONESHOT: u1, + /// Ramp Index Command + IDXCMD: u2, + /// TCC Command + CMD: u3, + }), base_address + 0x4); + + /// address: 0x42000c05 + /// Control B Set + pub const CTRLBSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot + ONESHOT: u1, + /// Ramp Index Command + IDXCMD: u2, + /// TCC Command + CMD: u3, + }), base_address + 0x5); + + /// address: 0x42000c08 + /// Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Swrst Busy + SWRST: u1, + /// Enable Busy + ENABLE: u1, + /// Ctrlb Busy + CTRLB: u1, + /// Status Busy + STATUS: u1, + /// Count Busy + COUNT: u1, + /// Pattern Busy + PATT: u1, + /// Wave Busy + WAVE: u1, + /// Period Busy + PER: u1, + /// Compare Channel 0 Busy + CC0: u1, + /// Compare Channel 1 Busy + CC1: u1, + /// Compare Channel 2 Busy + CC2: u1, + /// Compare Channel 3 Busy + CC3: u1, + /// Compare Channel 4 Busy + CC4: u1, + /// Compare Channel 5 Busy + CC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x8); + + /// address: 0x42000c0c + /// Recoverable Fault A Configuration + pub const FCTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Fault A Source + SRC: u2, + reserved0: u1, + /// Fault A Keeper + KEEP: u1, + /// Fault A Qualification + QUAL: u1, + /// Fault A Blanking Mode + BLANK: u2, + /// Fault A Restart + RESTART: u1, + /// Fault A Halt Mode + HALT: u2, + /// Fault A Capture Channel + CHSEL: u2, + /// Fault A Capture Action + CAPTURE: u3, + /// Fault A Blanking Prescaler + BLANKPRESC: u1, + /// Fault A Blanking Time + BLANKVAL: u8, + /// Fault A Filter Value + FILTERVAL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xc); + + /// address: 0x42000c10 + /// Recoverable Fault B Configuration + pub const FCTRLB = @intToPtr(*volatile Mmio(32, packed struct { + /// Fault B Source + SRC: u2, + reserved0: u1, + /// Fault B Keeper + KEEP: u1, + /// Fault B Qualification + QUAL: u1, + /// Fault B Blanking Mode + BLANK: u2, + /// Fault B Restart + RESTART: u1, + /// Fault B Halt Mode + HALT: u2, + /// Fault B Capture Channel + CHSEL: u2, + /// Fault B Capture Action + CAPTURE: u3, + /// Fault B Blanking Prescaler + BLANKPRESC: u1, + /// Fault B Blanking Time + BLANKVAL: u8, + /// Fault B Filter Value + FILTERVAL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x10); + + /// address: 0x42000c14 + /// Waveform Extension Configuration + pub const WEXCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Output Matrix + OTMX: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Dead-time Insertion Generator 0 Enable + DTIEN0: u1, + /// Dead-time Insertion Generator 1 Enable + DTIEN1: u1, + /// Dead-time Insertion Generator 2 Enable + DTIEN2: u1, + /// Dead-time Insertion Generator 3 Enable + DTIEN3: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Dead-time Low Side Outputs Value + DTLS: u8, + /// Dead-time High Side Outputs Value + DTHS: u8, + }), base_address + 0x14); + + /// address: 0x42000c18 + /// Driver Control + pub const DRVCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Non-Recoverable State 0 Output Enable + NRE0: u1, + /// Non-Recoverable State 1 Output Enable + NRE1: u1, + /// Non-Recoverable State 2 Output Enable + NRE2: u1, + /// Non-Recoverable State 3 Output Enable + NRE3: u1, + /// Non-Recoverable State 4 Output Enable + NRE4: u1, + /// Non-Recoverable State 5 Output Enable + NRE5: u1, + /// Non-Recoverable State 6 Output Enable + NRE6: u1, + /// Non-Recoverable State 7 Output Enable + NRE7: u1, + /// Non-Recoverable State 0 Output Value + NRV0: u1, + /// Non-Recoverable State 1 Output Value + NRV1: u1, + /// Non-Recoverable State 2 Output Value + NRV2: u1, + /// Non-Recoverable State 3 Output Value + NRV3: u1, + /// Non-Recoverable State 4 Output Value + NRV4: u1, + /// Non-Recoverable State 5 Output Value + NRV5: u1, + /// Non-Recoverable State 6 Output Value + NRV6: u1, + /// Non-Recoverable State 7 Output Value + NRV7: u1, + /// Output Waveform 0 Inversion + INVEN0: u1, + /// Output Waveform 1 Inversion + INVEN1: u1, + /// Output Waveform 2 Inversion + INVEN2: u1, + /// Output Waveform 3 Inversion + INVEN3: u1, + /// Output Waveform 4 Inversion + INVEN4: u1, + /// Output Waveform 5 Inversion + INVEN5: u1, + /// Output Waveform 6 Inversion + INVEN6: u1, + /// Output Waveform 7 Inversion + INVEN7: u1, + /// Non-Recoverable Fault Input 0 Filter Value + FILTERVAL0: u4, + /// Non-Recoverable Fault Input 1 Filter Value + FILTERVAL1: u4, + }), base_address + 0x18); + + /// address: 0x42000c1e + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Running Mode + DBGRUN: u1, + reserved0: u1, + /// Fault Detection on Debug Break Detection + FDDBD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x1e); + + /// address: 0x42000c20 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Timer/counter Input Event0 Action + EVACT0: u3, + /// Timer/counter Input Event1 Action + EVACT1: u3, + /// Timer/counter Output Event Mode + CNTSEL: u2, + /// Overflow/Underflow Output Event Enable + OVFEO: u1, + /// Retrigger Output Event Enable + TRGEO: u1, + /// Timer/counter Output Event Enable + CNTEO: u1, + reserved0: u1, + /// Inverted Event 0 Input Enable + TCINV0: u1, + /// Inverted Event 1 Input Enable + TCINV1: u1, + /// Timer/counter Event 0 Input Enable + TCEI0: u1, + /// Timer/counter Event 1 Input Enable + TCEI1: u1, + /// Match or Capture Channel 0 Event Input Enable + MCEI0: u1, + /// Match or Capture Channel 1 Event Input Enable + MCEI1: u1, + /// Match or Capture Channel 2 Event Input Enable + MCEI2: u1, + /// Match or Capture Channel 3 Event Input Enable + MCEI3: u1, + /// Match or Capture Channel 4 Event Input Enable + MCEI4: u1, + /// Match or Capture Channel 5 Event Input Enable + MCEI5: u1, + reserved1: u1, + reserved2: u1, + /// Match or Capture Channel 0 Event Output Enable + MCEO0: u1, + /// Match or Capture Channel 1 Event Output Enable + MCEO1: u1, + /// Match or Capture Channel 2 Event Output Enable + MCEO2: u1, + /// Match or Capture Channel 3 Event Output Enable + MCEO3: u1, + /// Match or Capture Channel 4 Event Output Enable + MCEO4: u1, + /// Match or Capture Channel 5 Event Output Enable + MCEO5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x20); + + /// address: 0x42000c24 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow Interrupt Enable + OVF: u1, + /// Retrigger Interrupt Enable + TRG: u1, + /// Counter Interrupt Enable + CNT: u1, + /// Error Interrupt Enable + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault Interrupt Enable + UFS: u1, + /// Non-Recoverable Debug Fault Interrupt Enable + DFS: u1, + /// Recoverable Fault A Interrupt Enable + FAULTA: u1, + /// Recoverable Fault B Interrupt Enable + FAULTB: u1, + /// Non-Recoverable Fault 0 Interrupt Enable + FAULT0: u1, + /// Non-Recoverable Fault 1 Interrupt Enable + FAULT1: u1, + /// Match or Capture Channel 0 Interrupt Enable + MC0: u1, + /// Match or Capture Channel 1 Interrupt Enable + MC1: u1, + /// Match or Capture Channel 2 Interrupt Enable + MC2: u1, + /// Match or Capture Channel 3 Interrupt Enable + MC3: u1, + /// Match or Capture Channel 4 Interrupt Enable + MC4: u1, + /// Match or Capture Channel 5 Interrupt Enable + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x24); + + /// address: 0x42000c28 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow Interrupt Enable + OVF: u1, + /// Retrigger Interrupt Enable + TRG: u1, + /// Counter Interrupt Enable + CNT: u1, + /// Error Interrupt Enable + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault Interrupt Enable + UFS: u1, + /// Non-Recoverable Debug Fault Interrupt Enable + DFS: u1, + /// Recoverable Fault A Interrupt Enable + FAULTA: u1, + /// Recoverable Fault B Interrupt Enable + FAULTB: u1, + /// Non-Recoverable Fault 0 Interrupt Enable + FAULT0: u1, + /// Non-Recoverable Fault 1 Interrupt Enable + FAULT1: u1, + /// Match or Capture Channel 0 Interrupt Enable + MC0: u1, + /// Match or Capture Channel 1 Interrupt Enable + MC1: u1, + /// Match or Capture Channel 2 Interrupt Enable + MC2: u1, + /// Match or Capture Channel 3 Interrupt Enable + MC3: u1, + /// Match or Capture Channel 4 Interrupt Enable + MC4: u1, + /// Match or Capture Channel 5 Interrupt Enable + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x28); + + /// address: 0x42000c2c + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow + OVF: u1, + /// Retrigger + TRG: u1, + /// Counter + CNT: u1, + /// Error + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault + UFS: u1, + /// Non-Recoverable Debug Fault + DFS: u1, + /// Recoverable Fault A + FAULTA: u1, + /// Recoverable Fault B + FAULTB: u1, + /// Non-Recoverable Fault 0 + FAULT0: u1, + /// Non-Recoverable Fault 1 + FAULT1: u1, + /// Match or Capture 0 + MC0: u1, + /// Match or Capture 1 + MC1: u1, + /// Match or Capture 2 + MC2: u1, + /// Match or Capture 3 + MC3: u1, + /// Match or Capture 4 + MC4: u1, + /// Match or Capture 5 + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x2c); + + /// address: 0x42000c30 + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// Stop + STOP: u1, + /// Ramp + IDX: u1, + /// Non-recoverable Update Fault State + UFS: u1, + /// Non-Recoverable Debug Fault State + DFS: u1, + /// Slave + SLAVE: u1, + /// Pattern Buffer Valid + PATTBUFV: u1, + reserved0: u1, + /// Period Buffer Valid + PERBUFV: u1, + /// Recoverable Fault A Input + FAULTAIN: u1, + /// Recoverable Fault B Input + FAULTBIN: u1, + /// Non-Recoverable Fault0 Input + FAULT0IN: u1, + /// Non-Recoverable Fault1 Input + FAULT1IN: u1, + /// Recoverable Fault A State + FAULTA: u1, + /// Recoverable Fault B State + FAULTB: u1, + /// Non-Recoverable Fault 0 State + FAULT0: u1, + /// Non-Recoverable Fault 1 State + FAULT1: u1, + /// Compare Channel 0 Buffer Valid + CCBUFV0: u1, + /// Compare Channel 1 Buffer Valid + CCBUFV1: u1, + /// Compare Channel 2 Buffer Valid + CCBUFV2: u1, + /// Compare Channel 3 Buffer Valid + CCBUFV3: u1, + /// Compare Channel 4 Buffer Valid + CCBUFV4: u1, + /// Compare Channel 5 Buffer Valid + CCBUFV5: u1, + reserved1: u1, + reserved2: u1, + /// Compare Channel 0 Value + CMP0: u1, + /// Compare Channel 1 Value + CMP1: u1, + /// Compare Channel 2 Value + CMP2: u1, + /// Compare Channel 3 Value + CMP3: u1, + /// Compare Channel 4 Value + CMP4: u1, + /// Compare Channel 5 Value + CMP5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x30); + + /// address: 0x42000c34 + /// Count + pub const COUNT = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x34); + + /// address: 0x42000c34 + /// Count + pub const COUNT_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Counter Value + COUNT: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x42000c34 + /// Count + pub const COUNT_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Counter Value + COUNT: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x42000c34 + /// Count + pub const COUNT_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Counter Value + COUNT: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x42000c38 + /// Pattern + pub const PATT = @intToPtr(*volatile Mmio(16, packed struct { + /// Pattern Generator 0 Output Enable + PGE0: u1, + /// Pattern Generator 1 Output Enable + PGE1: u1, + /// Pattern Generator 2 Output Enable + PGE2: u1, + /// Pattern Generator 3 Output Enable + PGE3: u1, + /// Pattern Generator 4 Output Enable + PGE4: u1, + /// Pattern Generator 5 Output Enable + PGE5: u1, + /// Pattern Generator 6 Output Enable + PGE6: u1, + /// Pattern Generator 7 Output Enable + PGE7: u1, + /// Pattern Generator 0 Output Value + PGV0: u1, + /// Pattern Generator 1 Output Value + PGV1: u1, + /// Pattern Generator 2 Output Value + PGV2: u1, + /// Pattern Generator 3 Output Value + PGV3: u1, + /// Pattern Generator 4 Output Value + PGV4: u1, + /// Pattern Generator 5 Output Value + PGV5: u1, + /// Pattern Generator 6 Output Value + PGV6: u1, + /// Pattern Generator 7 Output Value + PGV7: u1, + }), base_address + 0x38); + + /// address: 0x42000c3c + /// Waveform Control + pub const WAVE = @intToPtr(*volatile Mmio(32, packed struct { + /// Waveform Generation + WAVEGEN: u3, + reserved0: u1, + /// Ramp Mode + RAMP: u2, + reserved1: u1, + /// Circular period Enable + CIPEREN: u1, + /// Circular Channel 0 Enable + CICCEN0: u1, + /// Circular Channel 1 Enable + CICCEN1: u1, + /// Circular Channel 2 Enable + CICCEN2: u1, + /// Circular Channel 3 Enable + CICCEN3: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Channel 0 Polarity + POL0: u1, + /// Channel 1 Polarity + POL1: u1, + /// Channel 2 Polarity + POL2: u1, + /// Channel 3 Polarity + POL3: u1, + /// Channel 4 Polarity + POL4: u1, + /// Channel 5 Polarity + POL5: u1, + reserved6: u1, + reserved7: u1, + /// Swap DTI Output Pair 0 + SWAP0: u1, + /// Swap DTI Output Pair 1 + SWAP1: u1, + /// Swap DTI Output Pair 2 + SWAP2: u1, + /// Swap DTI Output Pair 3 + SWAP3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x3c); + + /// address: 0x42000c40 + /// Period + pub const PER = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x40); + + /// address: 0x42000c40 + /// Period + pub const PER_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u4, + /// Period Value + PER: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x42000c40 + /// Period + pub const PER_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u5, + /// Period Value + PER: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x42000c40 + /// Period + pub const PER_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u6, + /// Period Value + PER: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x42000c44 + /// Compare and Capture + pub const CC = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x44); + + /// address: 0x42000c44 + /// Compare and Capture + pub const CC_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u4, + /// Channel Compare/Capture Value + CC: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x42000c44 + /// Compare and Capture + pub const CC_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u5, + /// Channel Compare/Capture Value + CC: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x42000c44 + /// Compare and Capture + pub const CC_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u6, + /// Channel Compare/Capture Value + CC: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x42000c64 + /// Pattern Buffer + pub const PATTBUF = @intToPtr(*volatile Mmio(16, packed struct { + /// Pattern Generator 0 Output Enable Buffer + PGEB0: u1, + /// Pattern Generator 1 Output Enable Buffer + PGEB1: u1, + /// Pattern Generator 2 Output Enable Buffer + PGEB2: u1, + /// Pattern Generator 3 Output Enable Buffer + PGEB3: u1, + /// Pattern Generator 4 Output Enable Buffer + PGEB4: u1, + /// Pattern Generator 5 Output Enable Buffer + PGEB5: u1, + /// Pattern Generator 6 Output Enable Buffer + PGEB6: u1, + /// Pattern Generator 7 Output Enable Buffer + PGEB7: u1, + /// Pattern Generator 0 Output Enable + PGVB0: u1, + /// Pattern Generator 1 Output Enable + PGVB1: u1, + /// Pattern Generator 2 Output Enable + PGVB2: u1, + /// Pattern Generator 3 Output Enable + PGVB3: u1, + /// Pattern Generator 4 Output Enable + PGVB4: u1, + /// Pattern Generator 5 Output Enable + PGVB5: u1, + /// Pattern Generator 6 Output Enable + PGVB6: u1, + /// Pattern Generator 7 Output Enable + PGVB7: u1, + }), base_address + 0x64); + + /// address: 0x42000c6c + /// Period Buffer + pub const PERBUF = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x6c); + + /// address: 0x42000c6c + /// Period Buffer + pub const PERBUF_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u4, + /// Period Buffer Value + PERBUF: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x42000c6c + /// Period Buffer + pub const PERBUF_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u5, + /// Period Buffer Value + PERBUF: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x42000c6c + /// Period Buffer + pub const PERBUF_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u6, + /// Period Buffer Value + PERBUF: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x42000c70 + /// Compare and Capture Buffer + pub const CCBUF = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x70); + + /// address: 0x42000c70 + /// Compare and Capture Buffer + pub const CCBUF_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Channel Compare/Capture Buffer Value + CCBUF: u4, + /// Dithering Buffer Cycle Number + DITHERBUF: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + + /// address: 0x42000c70 + /// Compare and Capture Buffer + pub const CCBUF_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u5, + /// Channel Compare/Capture Buffer Value + CCBUF: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + + /// address: 0x42000c70 + /// Compare and Capture Buffer + pub const CCBUF_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u6, + /// Channel Compare/Capture Buffer Value + CCBUF: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + }; + pub const TCC3 = struct { + pub const base_address = 0x42001000; + + /// address: 0x42001000 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Enhanced Resolution + RESOLUTION: u2, + reserved3: u1, + /// Prescaler + PRESCALER: u3, + /// Run in Standby + RUNSTDBY: u1, + /// Prescaler and Counter Synchronization Selection + PRESCSYNC: u2, + /// Auto Lock + ALOCK: u1, + /// Master Synchronization (only for TCC Slave Instance) + MSYNC: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// DMA One-shot Trigger Mode + DMAOS: u1, + /// Capture Channel 0 Enable + CPTEN0: u1, + /// Capture Channel 1 Enable + CPTEN1: u1, + /// Capture Channel 2 Enable + CPTEN2: u1, + /// Capture Channel 3 Enable + CPTEN3: u1, + /// Capture Channel 4 Enable + CPTEN4: u1, + /// Capture Channel 5 Enable + CPTEN5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x0); + + /// address: 0x42001004 + /// Control B Clear + pub const CTRLBCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot + ONESHOT: u1, + /// Ramp Index Command + IDXCMD: u2, + /// TCC Command + CMD: u3, + }), base_address + 0x4); + + /// address: 0x42001005 + /// Control B Set + pub const CTRLBSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot + ONESHOT: u1, + /// Ramp Index Command + IDXCMD: u2, + /// TCC Command + CMD: u3, + }), base_address + 0x5); + + /// address: 0x42001008 + /// Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Swrst Busy + SWRST: u1, + /// Enable Busy + ENABLE: u1, + /// Ctrlb Busy + CTRLB: u1, + /// Status Busy + STATUS: u1, + /// Count Busy + COUNT: u1, + /// Pattern Busy + PATT: u1, + /// Wave Busy + WAVE: u1, + /// Period Busy + PER: u1, + /// Compare Channel 0 Busy + CC0: u1, + /// Compare Channel 1 Busy + CC1: u1, + /// Compare Channel 2 Busy + CC2: u1, + /// Compare Channel 3 Busy + CC3: u1, + /// Compare Channel 4 Busy + CC4: u1, + /// Compare Channel 5 Busy + CC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x8); + + /// address: 0x4200100c + /// Recoverable Fault A Configuration + pub const FCTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Fault A Source + SRC: u2, + reserved0: u1, + /// Fault A Keeper + KEEP: u1, + /// Fault A Qualification + QUAL: u1, + /// Fault A Blanking Mode + BLANK: u2, + /// Fault A Restart + RESTART: u1, + /// Fault A Halt Mode + HALT: u2, + /// Fault A Capture Channel + CHSEL: u2, + /// Fault A Capture Action + CAPTURE: u3, + /// Fault A Blanking Prescaler + BLANKPRESC: u1, + /// Fault A Blanking Time + BLANKVAL: u8, + /// Fault A Filter Value + FILTERVAL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xc); + + /// address: 0x42001010 + /// Recoverable Fault B Configuration + pub const FCTRLB = @intToPtr(*volatile Mmio(32, packed struct { + /// Fault B Source + SRC: u2, + reserved0: u1, + /// Fault B Keeper + KEEP: u1, + /// Fault B Qualification + QUAL: u1, + /// Fault B Blanking Mode + BLANK: u2, + /// Fault B Restart + RESTART: u1, + /// Fault B Halt Mode + HALT: u2, + /// Fault B Capture Channel + CHSEL: u2, + /// Fault B Capture Action + CAPTURE: u3, + /// Fault B Blanking Prescaler + BLANKPRESC: u1, + /// Fault B Blanking Time + BLANKVAL: u8, + /// Fault B Filter Value + FILTERVAL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x10); + + /// address: 0x42001014 + /// Waveform Extension Configuration + pub const WEXCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Output Matrix + OTMX: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Dead-time Insertion Generator 0 Enable + DTIEN0: u1, + /// Dead-time Insertion Generator 1 Enable + DTIEN1: u1, + /// Dead-time Insertion Generator 2 Enable + DTIEN2: u1, + /// Dead-time Insertion Generator 3 Enable + DTIEN3: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Dead-time Low Side Outputs Value + DTLS: u8, + /// Dead-time High Side Outputs Value + DTHS: u8, + }), base_address + 0x14); + + /// address: 0x42001018 + /// Driver Control + pub const DRVCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Non-Recoverable State 0 Output Enable + NRE0: u1, + /// Non-Recoverable State 1 Output Enable + NRE1: u1, + /// Non-Recoverable State 2 Output Enable + NRE2: u1, + /// Non-Recoverable State 3 Output Enable + NRE3: u1, + /// Non-Recoverable State 4 Output Enable + NRE4: u1, + /// Non-Recoverable State 5 Output Enable + NRE5: u1, + /// Non-Recoverable State 6 Output Enable + NRE6: u1, + /// Non-Recoverable State 7 Output Enable + NRE7: u1, + /// Non-Recoverable State 0 Output Value + NRV0: u1, + /// Non-Recoverable State 1 Output Value + NRV1: u1, + /// Non-Recoverable State 2 Output Value + NRV2: u1, + /// Non-Recoverable State 3 Output Value + NRV3: u1, + /// Non-Recoverable State 4 Output Value + NRV4: u1, + /// Non-Recoverable State 5 Output Value + NRV5: u1, + /// Non-Recoverable State 6 Output Value + NRV6: u1, + /// Non-Recoverable State 7 Output Value + NRV7: u1, + /// Output Waveform 0 Inversion + INVEN0: u1, + /// Output Waveform 1 Inversion + INVEN1: u1, + /// Output Waveform 2 Inversion + INVEN2: u1, + /// Output Waveform 3 Inversion + INVEN3: u1, + /// Output Waveform 4 Inversion + INVEN4: u1, + /// Output Waveform 5 Inversion + INVEN5: u1, + /// Output Waveform 6 Inversion + INVEN6: u1, + /// Output Waveform 7 Inversion + INVEN7: u1, + /// Non-Recoverable Fault Input 0 Filter Value + FILTERVAL0: u4, + /// Non-Recoverable Fault Input 1 Filter Value + FILTERVAL1: u4, + }), base_address + 0x18); + + /// address: 0x4200101e + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Running Mode + DBGRUN: u1, + reserved0: u1, + /// Fault Detection on Debug Break Detection + FDDBD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x1e); + + /// address: 0x42001020 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Timer/counter Input Event0 Action + EVACT0: u3, + /// Timer/counter Input Event1 Action + EVACT1: u3, + /// Timer/counter Output Event Mode + CNTSEL: u2, + /// Overflow/Underflow Output Event Enable + OVFEO: u1, + /// Retrigger Output Event Enable + TRGEO: u1, + /// Timer/counter Output Event Enable + CNTEO: u1, + reserved0: u1, + /// Inverted Event 0 Input Enable + TCINV0: u1, + /// Inverted Event 1 Input Enable + TCINV1: u1, + /// Timer/counter Event 0 Input Enable + TCEI0: u1, + /// Timer/counter Event 1 Input Enable + TCEI1: u1, + /// Match or Capture Channel 0 Event Input Enable + MCEI0: u1, + /// Match or Capture Channel 1 Event Input Enable + MCEI1: u1, + /// Match or Capture Channel 2 Event Input Enable + MCEI2: u1, + /// Match or Capture Channel 3 Event Input Enable + MCEI3: u1, + /// Match or Capture Channel 4 Event Input Enable + MCEI4: u1, + /// Match or Capture Channel 5 Event Input Enable + MCEI5: u1, + reserved1: u1, + reserved2: u1, + /// Match or Capture Channel 0 Event Output Enable + MCEO0: u1, + /// Match or Capture Channel 1 Event Output Enable + MCEO1: u1, + /// Match or Capture Channel 2 Event Output Enable + MCEO2: u1, + /// Match or Capture Channel 3 Event Output Enable + MCEO3: u1, + /// Match or Capture Channel 4 Event Output Enable + MCEO4: u1, + /// Match or Capture Channel 5 Event Output Enable + MCEO5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x20); + + /// address: 0x42001024 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow Interrupt Enable + OVF: u1, + /// Retrigger Interrupt Enable + TRG: u1, + /// Counter Interrupt Enable + CNT: u1, + /// Error Interrupt Enable + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault Interrupt Enable + UFS: u1, + /// Non-Recoverable Debug Fault Interrupt Enable + DFS: u1, + /// Recoverable Fault A Interrupt Enable + FAULTA: u1, + /// Recoverable Fault B Interrupt Enable + FAULTB: u1, + /// Non-Recoverable Fault 0 Interrupt Enable + FAULT0: u1, + /// Non-Recoverable Fault 1 Interrupt Enable + FAULT1: u1, + /// Match or Capture Channel 0 Interrupt Enable + MC0: u1, + /// Match or Capture Channel 1 Interrupt Enable + MC1: u1, + /// Match or Capture Channel 2 Interrupt Enable + MC2: u1, + /// Match or Capture Channel 3 Interrupt Enable + MC3: u1, + /// Match or Capture Channel 4 Interrupt Enable + MC4: u1, + /// Match or Capture Channel 5 Interrupt Enable + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x24); + + /// address: 0x42001028 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow Interrupt Enable + OVF: u1, + /// Retrigger Interrupt Enable + TRG: u1, + /// Counter Interrupt Enable + CNT: u1, + /// Error Interrupt Enable + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault Interrupt Enable + UFS: u1, + /// Non-Recoverable Debug Fault Interrupt Enable + DFS: u1, + /// Recoverable Fault A Interrupt Enable + FAULTA: u1, + /// Recoverable Fault B Interrupt Enable + FAULTB: u1, + /// Non-Recoverable Fault 0 Interrupt Enable + FAULT0: u1, + /// Non-Recoverable Fault 1 Interrupt Enable + FAULT1: u1, + /// Match or Capture Channel 0 Interrupt Enable + MC0: u1, + /// Match or Capture Channel 1 Interrupt Enable + MC1: u1, + /// Match or Capture Channel 2 Interrupt Enable + MC2: u1, + /// Match or Capture Channel 3 Interrupt Enable + MC3: u1, + /// Match or Capture Channel 4 Interrupt Enable + MC4: u1, + /// Match or Capture Channel 5 Interrupt Enable + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x28); + + /// address: 0x4200102c + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow + OVF: u1, + /// Retrigger + TRG: u1, + /// Counter + CNT: u1, + /// Error + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault + UFS: u1, + /// Non-Recoverable Debug Fault + DFS: u1, + /// Recoverable Fault A + FAULTA: u1, + /// Recoverable Fault B + FAULTB: u1, + /// Non-Recoverable Fault 0 + FAULT0: u1, + /// Non-Recoverable Fault 1 + FAULT1: u1, + /// Match or Capture 0 + MC0: u1, + /// Match or Capture 1 + MC1: u1, + /// Match or Capture 2 + MC2: u1, + /// Match or Capture 3 + MC3: u1, + /// Match or Capture 4 + MC4: u1, + /// Match or Capture 5 + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x2c); + + /// address: 0x42001030 + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// Stop + STOP: u1, + /// Ramp + IDX: u1, + /// Non-recoverable Update Fault State + UFS: u1, + /// Non-Recoverable Debug Fault State + DFS: u1, + /// Slave + SLAVE: u1, + /// Pattern Buffer Valid + PATTBUFV: u1, + reserved0: u1, + /// Period Buffer Valid + PERBUFV: u1, + /// Recoverable Fault A Input + FAULTAIN: u1, + /// Recoverable Fault B Input + FAULTBIN: u1, + /// Non-Recoverable Fault0 Input + FAULT0IN: u1, + /// Non-Recoverable Fault1 Input + FAULT1IN: u1, + /// Recoverable Fault A State + FAULTA: u1, + /// Recoverable Fault B State + FAULTB: u1, + /// Non-Recoverable Fault 0 State + FAULT0: u1, + /// Non-Recoverable Fault 1 State + FAULT1: u1, + /// Compare Channel 0 Buffer Valid + CCBUFV0: u1, + /// Compare Channel 1 Buffer Valid + CCBUFV1: u1, + /// Compare Channel 2 Buffer Valid + CCBUFV2: u1, + /// Compare Channel 3 Buffer Valid + CCBUFV3: u1, + /// Compare Channel 4 Buffer Valid + CCBUFV4: u1, + /// Compare Channel 5 Buffer Valid + CCBUFV5: u1, + reserved1: u1, + reserved2: u1, + /// Compare Channel 0 Value + CMP0: u1, + /// Compare Channel 1 Value + CMP1: u1, + /// Compare Channel 2 Value + CMP2: u1, + /// Compare Channel 3 Value + CMP3: u1, + /// Compare Channel 4 Value + CMP4: u1, + /// Compare Channel 5 Value + CMP5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x30); + + /// address: 0x42001034 + /// Count + pub const COUNT = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x34); + + /// address: 0x42001034 + /// Count + pub const COUNT_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Counter Value + COUNT: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x42001034 + /// Count + pub const COUNT_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Counter Value + COUNT: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x42001034 + /// Count + pub const COUNT_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Counter Value + COUNT: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x42001038 + /// Pattern + pub const PATT = @intToPtr(*volatile Mmio(16, packed struct { + /// Pattern Generator 0 Output Enable + PGE0: u1, + /// Pattern Generator 1 Output Enable + PGE1: u1, + /// Pattern Generator 2 Output Enable + PGE2: u1, + /// Pattern Generator 3 Output Enable + PGE3: u1, + /// Pattern Generator 4 Output Enable + PGE4: u1, + /// Pattern Generator 5 Output Enable + PGE5: u1, + /// Pattern Generator 6 Output Enable + PGE6: u1, + /// Pattern Generator 7 Output Enable + PGE7: u1, + /// Pattern Generator 0 Output Value + PGV0: u1, + /// Pattern Generator 1 Output Value + PGV1: u1, + /// Pattern Generator 2 Output Value + PGV2: u1, + /// Pattern Generator 3 Output Value + PGV3: u1, + /// Pattern Generator 4 Output Value + PGV4: u1, + /// Pattern Generator 5 Output Value + PGV5: u1, + /// Pattern Generator 6 Output Value + PGV6: u1, + /// Pattern Generator 7 Output Value + PGV7: u1, + }), base_address + 0x38); + + /// address: 0x4200103c + /// Waveform Control + pub const WAVE = @intToPtr(*volatile Mmio(32, packed struct { + /// Waveform Generation + WAVEGEN: u3, + reserved0: u1, + /// Ramp Mode + RAMP: u2, + reserved1: u1, + /// Circular period Enable + CIPEREN: u1, + /// Circular Channel 0 Enable + CICCEN0: u1, + /// Circular Channel 1 Enable + CICCEN1: u1, + /// Circular Channel 2 Enable + CICCEN2: u1, + /// Circular Channel 3 Enable + CICCEN3: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Channel 0 Polarity + POL0: u1, + /// Channel 1 Polarity + POL1: u1, + /// Channel 2 Polarity + POL2: u1, + /// Channel 3 Polarity + POL3: u1, + /// Channel 4 Polarity + POL4: u1, + /// Channel 5 Polarity + POL5: u1, + reserved6: u1, + reserved7: u1, + /// Swap DTI Output Pair 0 + SWAP0: u1, + /// Swap DTI Output Pair 1 + SWAP1: u1, + /// Swap DTI Output Pair 2 + SWAP2: u1, + /// Swap DTI Output Pair 3 + SWAP3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x3c); + + /// address: 0x42001040 + /// Period + pub const PER = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x40); + + /// address: 0x42001040 + /// Period + pub const PER_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u4, + /// Period Value + PER: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x42001040 + /// Period + pub const PER_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u5, + /// Period Value + PER: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x42001040 + /// Period + pub const PER_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u6, + /// Period Value + PER: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x42001044 + /// Compare and Capture + pub const CC = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x44); + + /// address: 0x42001044 + /// Compare and Capture + pub const CC_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u4, + /// Channel Compare/Capture Value + CC: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x42001044 + /// Compare and Capture + pub const CC_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u5, + /// Channel Compare/Capture Value + CC: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x42001044 + /// Compare and Capture + pub const CC_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u6, + /// Channel Compare/Capture Value + CC: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x42001064 + /// Pattern Buffer + pub const PATTBUF = @intToPtr(*volatile Mmio(16, packed struct { + /// Pattern Generator 0 Output Enable Buffer + PGEB0: u1, + /// Pattern Generator 1 Output Enable Buffer + PGEB1: u1, + /// Pattern Generator 2 Output Enable Buffer + PGEB2: u1, + /// Pattern Generator 3 Output Enable Buffer + PGEB3: u1, + /// Pattern Generator 4 Output Enable Buffer + PGEB4: u1, + /// Pattern Generator 5 Output Enable Buffer + PGEB5: u1, + /// Pattern Generator 6 Output Enable Buffer + PGEB6: u1, + /// Pattern Generator 7 Output Enable Buffer + PGEB7: u1, + /// Pattern Generator 0 Output Enable + PGVB0: u1, + /// Pattern Generator 1 Output Enable + PGVB1: u1, + /// Pattern Generator 2 Output Enable + PGVB2: u1, + /// Pattern Generator 3 Output Enable + PGVB3: u1, + /// Pattern Generator 4 Output Enable + PGVB4: u1, + /// Pattern Generator 5 Output Enable + PGVB5: u1, + /// Pattern Generator 6 Output Enable + PGVB6: u1, + /// Pattern Generator 7 Output Enable + PGVB7: u1, + }), base_address + 0x64); + + /// address: 0x4200106c + /// Period Buffer + pub const PERBUF = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x6c); + + /// address: 0x4200106c + /// Period Buffer + pub const PERBUF_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u4, + /// Period Buffer Value + PERBUF: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x4200106c + /// Period Buffer + pub const PERBUF_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u5, + /// Period Buffer Value + PERBUF: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x4200106c + /// Period Buffer + pub const PERBUF_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u6, + /// Period Buffer Value + PERBUF: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x42001070 + /// Compare and Capture Buffer + pub const CCBUF = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x70); + + /// address: 0x42001070 + /// Compare and Capture Buffer + pub const CCBUF_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Channel Compare/Capture Buffer Value + CCBUF: u4, + /// Dithering Buffer Cycle Number + DITHERBUF: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + + /// address: 0x42001070 + /// Compare and Capture Buffer + pub const CCBUF_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u5, + /// Channel Compare/Capture Buffer Value + CCBUF: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + + /// address: 0x42001070 + /// Compare and Capture Buffer + pub const CCBUF_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u6, + /// Channel Compare/Capture Buffer Value + CCBUF: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + }; + pub const TCC4 = struct { + pub const base_address = 0x43001000; + + /// address: 0x43001000 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Enhanced Resolution + RESOLUTION: u2, + reserved3: u1, + /// Prescaler + PRESCALER: u3, + /// Run in Standby + RUNSTDBY: u1, + /// Prescaler and Counter Synchronization Selection + PRESCSYNC: u2, + /// Auto Lock + ALOCK: u1, + /// Master Synchronization (only for TCC Slave Instance) + MSYNC: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// DMA One-shot Trigger Mode + DMAOS: u1, + /// Capture Channel 0 Enable + CPTEN0: u1, + /// Capture Channel 1 Enable + CPTEN1: u1, + /// Capture Channel 2 Enable + CPTEN2: u1, + /// Capture Channel 3 Enable + CPTEN3: u1, + /// Capture Channel 4 Enable + CPTEN4: u1, + /// Capture Channel 5 Enable + CPTEN5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x0); + + /// address: 0x43001004 + /// Control B Clear + pub const CTRLBCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot + ONESHOT: u1, + /// Ramp Index Command + IDXCMD: u2, + /// TCC Command + CMD: u3, + }), base_address + 0x4); + + /// address: 0x43001005 + /// Control B Set + pub const CTRLBSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot + ONESHOT: u1, + /// Ramp Index Command + IDXCMD: u2, + /// TCC Command + CMD: u3, + }), base_address + 0x5); + + /// address: 0x43001008 + /// Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Swrst Busy + SWRST: u1, + /// Enable Busy + ENABLE: u1, + /// Ctrlb Busy + CTRLB: u1, + /// Status Busy + STATUS: u1, + /// Count Busy + COUNT: u1, + /// Pattern Busy + PATT: u1, + /// Wave Busy + WAVE: u1, + /// Period Busy + PER: u1, + /// Compare Channel 0 Busy + CC0: u1, + /// Compare Channel 1 Busy + CC1: u1, + /// Compare Channel 2 Busy + CC2: u1, + /// Compare Channel 3 Busy + CC3: u1, + /// Compare Channel 4 Busy + CC4: u1, + /// Compare Channel 5 Busy + CC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x8); + + /// address: 0x4300100c + /// Recoverable Fault A Configuration + pub const FCTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Fault A Source + SRC: u2, + reserved0: u1, + /// Fault A Keeper + KEEP: u1, + /// Fault A Qualification + QUAL: u1, + /// Fault A Blanking Mode + BLANK: u2, + /// Fault A Restart + RESTART: u1, + /// Fault A Halt Mode + HALT: u2, + /// Fault A Capture Channel + CHSEL: u2, + /// Fault A Capture Action + CAPTURE: u3, + /// Fault A Blanking Prescaler + BLANKPRESC: u1, + /// Fault A Blanking Time + BLANKVAL: u8, + /// Fault A Filter Value + FILTERVAL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xc); + + /// address: 0x43001010 + /// Recoverable Fault B Configuration + pub const FCTRLB = @intToPtr(*volatile Mmio(32, packed struct { + /// Fault B Source + SRC: u2, + reserved0: u1, + /// Fault B Keeper + KEEP: u1, + /// Fault B Qualification + QUAL: u1, + /// Fault B Blanking Mode + BLANK: u2, + /// Fault B Restart + RESTART: u1, + /// Fault B Halt Mode + HALT: u2, + /// Fault B Capture Channel + CHSEL: u2, + /// Fault B Capture Action + CAPTURE: u3, + /// Fault B Blanking Prescaler + BLANKPRESC: u1, + /// Fault B Blanking Time + BLANKVAL: u8, + /// Fault B Filter Value + FILTERVAL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x10); + + /// address: 0x43001014 + /// Waveform Extension Configuration + pub const WEXCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Output Matrix + OTMX: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Dead-time Insertion Generator 0 Enable + DTIEN0: u1, + /// Dead-time Insertion Generator 1 Enable + DTIEN1: u1, + /// Dead-time Insertion Generator 2 Enable + DTIEN2: u1, + /// Dead-time Insertion Generator 3 Enable + DTIEN3: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Dead-time Low Side Outputs Value + DTLS: u8, + /// Dead-time High Side Outputs Value + DTHS: u8, + }), base_address + 0x14); + + /// address: 0x43001018 + /// Driver Control + pub const DRVCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Non-Recoverable State 0 Output Enable + NRE0: u1, + /// Non-Recoverable State 1 Output Enable + NRE1: u1, + /// Non-Recoverable State 2 Output Enable + NRE2: u1, + /// Non-Recoverable State 3 Output Enable + NRE3: u1, + /// Non-Recoverable State 4 Output Enable + NRE4: u1, + /// Non-Recoverable State 5 Output Enable + NRE5: u1, + /// Non-Recoverable State 6 Output Enable + NRE6: u1, + /// Non-Recoverable State 7 Output Enable + NRE7: u1, + /// Non-Recoverable State 0 Output Value + NRV0: u1, + /// Non-Recoverable State 1 Output Value + NRV1: u1, + /// Non-Recoverable State 2 Output Value + NRV2: u1, + /// Non-Recoverable State 3 Output Value + NRV3: u1, + /// Non-Recoverable State 4 Output Value + NRV4: u1, + /// Non-Recoverable State 5 Output Value + NRV5: u1, + /// Non-Recoverable State 6 Output Value + NRV6: u1, + /// Non-Recoverable State 7 Output Value + NRV7: u1, + /// Output Waveform 0 Inversion + INVEN0: u1, + /// Output Waveform 1 Inversion + INVEN1: u1, + /// Output Waveform 2 Inversion + INVEN2: u1, + /// Output Waveform 3 Inversion + INVEN3: u1, + /// Output Waveform 4 Inversion + INVEN4: u1, + /// Output Waveform 5 Inversion + INVEN5: u1, + /// Output Waveform 6 Inversion + INVEN6: u1, + /// Output Waveform 7 Inversion + INVEN7: u1, + /// Non-Recoverable Fault Input 0 Filter Value + FILTERVAL0: u4, + /// Non-Recoverable Fault Input 1 Filter Value + FILTERVAL1: u4, + }), base_address + 0x18); + + /// address: 0x4300101e + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Running Mode + DBGRUN: u1, + reserved0: u1, + /// Fault Detection on Debug Break Detection + FDDBD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x1e); + + /// address: 0x43001020 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Timer/counter Input Event0 Action + EVACT0: u3, + /// Timer/counter Input Event1 Action + EVACT1: u3, + /// Timer/counter Output Event Mode + CNTSEL: u2, + /// Overflow/Underflow Output Event Enable + OVFEO: u1, + /// Retrigger Output Event Enable + TRGEO: u1, + /// Timer/counter Output Event Enable + CNTEO: u1, + reserved0: u1, + /// Inverted Event 0 Input Enable + TCINV0: u1, + /// Inverted Event 1 Input Enable + TCINV1: u1, + /// Timer/counter Event 0 Input Enable + TCEI0: u1, + /// Timer/counter Event 1 Input Enable + TCEI1: u1, + /// Match or Capture Channel 0 Event Input Enable + MCEI0: u1, + /// Match or Capture Channel 1 Event Input Enable + MCEI1: u1, + /// Match or Capture Channel 2 Event Input Enable + MCEI2: u1, + /// Match or Capture Channel 3 Event Input Enable + MCEI3: u1, + /// Match or Capture Channel 4 Event Input Enable + MCEI4: u1, + /// Match or Capture Channel 5 Event Input Enable + MCEI5: u1, + reserved1: u1, + reserved2: u1, + /// Match or Capture Channel 0 Event Output Enable + MCEO0: u1, + /// Match or Capture Channel 1 Event Output Enable + MCEO1: u1, + /// Match or Capture Channel 2 Event Output Enable + MCEO2: u1, + /// Match or Capture Channel 3 Event Output Enable + MCEO3: u1, + /// Match or Capture Channel 4 Event Output Enable + MCEO4: u1, + /// Match or Capture Channel 5 Event Output Enable + MCEO5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x20); + + /// address: 0x43001024 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow Interrupt Enable + OVF: u1, + /// Retrigger Interrupt Enable + TRG: u1, + /// Counter Interrupt Enable + CNT: u1, + /// Error Interrupt Enable + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault Interrupt Enable + UFS: u1, + /// Non-Recoverable Debug Fault Interrupt Enable + DFS: u1, + /// Recoverable Fault A Interrupt Enable + FAULTA: u1, + /// Recoverable Fault B Interrupt Enable + FAULTB: u1, + /// Non-Recoverable Fault 0 Interrupt Enable + FAULT0: u1, + /// Non-Recoverable Fault 1 Interrupt Enable + FAULT1: u1, + /// Match or Capture Channel 0 Interrupt Enable + MC0: u1, + /// Match or Capture Channel 1 Interrupt Enable + MC1: u1, + /// Match or Capture Channel 2 Interrupt Enable + MC2: u1, + /// Match or Capture Channel 3 Interrupt Enable + MC3: u1, + /// Match or Capture Channel 4 Interrupt Enable + MC4: u1, + /// Match or Capture Channel 5 Interrupt Enable + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x24); + + /// address: 0x43001028 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow Interrupt Enable + OVF: u1, + /// Retrigger Interrupt Enable + TRG: u1, + /// Counter Interrupt Enable + CNT: u1, + /// Error Interrupt Enable + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault Interrupt Enable + UFS: u1, + /// Non-Recoverable Debug Fault Interrupt Enable + DFS: u1, + /// Recoverable Fault A Interrupt Enable + FAULTA: u1, + /// Recoverable Fault B Interrupt Enable + FAULTB: u1, + /// Non-Recoverable Fault 0 Interrupt Enable + FAULT0: u1, + /// Non-Recoverable Fault 1 Interrupt Enable + FAULT1: u1, + /// Match or Capture Channel 0 Interrupt Enable + MC0: u1, + /// Match or Capture Channel 1 Interrupt Enable + MC1: u1, + /// Match or Capture Channel 2 Interrupt Enable + MC2: u1, + /// Match or Capture Channel 3 Interrupt Enable + MC3: u1, + /// Match or Capture Channel 4 Interrupt Enable + MC4: u1, + /// Match or Capture Channel 5 Interrupt Enable + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x28); + + /// address: 0x4300102c + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow + OVF: u1, + /// Retrigger + TRG: u1, + /// Counter + CNT: u1, + /// Error + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault + UFS: u1, + /// Non-Recoverable Debug Fault + DFS: u1, + /// Recoverable Fault A + FAULTA: u1, + /// Recoverable Fault B + FAULTB: u1, + /// Non-Recoverable Fault 0 + FAULT0: u1, + /// Non-Recoverable Fault 1 + FAULT1: u1, + /// Match or Capture 0 + MC0: u1, + /// Match or Capture 1 + MC1: u1, + /// Match or Capture 2 + MC2: u1, + /// Match or Capture 3 + MC3: u1, + /// Match or Capture 4 + MC4: u1, + /// Match or Capture 5 + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x2c); + + /// address: 0x43001030 + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// Stop + STOP: u1, + /// Ramp + IDX: u1, + /// Non-recoverable Update Fault State + UFS: u1, + /// Non-Recoverable Debug Fault State + DFS: u1, + /// Slave + SLAVE: u1, + /// Pattern Buffer Valid + PATTBUFV: u1, + reserved0: u1, + /// Period Buffer Valid + PERBUFV: u1, + /// Recoverable Fault A Input + FAULTAIN: u1, + /// Recoverable Fault B Input + FAULTBIN: u1, + /// Non-Recoverable Fault0 Input + FAULT0IN: u1, + /// Non-Recoverable Fault1 Input + FAULT1IN: u1, + /// Recoverable Fault A State + FAULTA: u1, + /// Recoverable Fault B State + FAULTB: u1, + /// Non-Recoverable Fault 0 State + FAULT0: u1, + /// Non-Recoverable Fault 1 State + FAULT1: u1, + /// Compare Channel 0 Buffer Valid + CCBUFV0: u1, + /// Compare Channel 1 Buffer Valid + CCBUFV1: u1, + /// Compare Channel 2 Buffer Valid + CCBUFV2: u1, + /// Compare Channel 3 Buffer Valid + CCBUFV3: u1, + /// Compare Channel 4 Buffer Valid + CCBUFV4: u1, + /// Compare Channel 5 Buffer Valid + CCBUFV5: u1, + reserved1: u1, + reserved2: u1, + /// Compare Channel 0 Value + CMP0: u1, + /// Compare Channel 1 Value + CMP1: u1, + /// Compare Channel 2 Value + CMP2: u1, + /// Compare Channel 3 Value + CMP3: u1, + /// Compare Channel 4 Value + CMP4: u1, + /// Compare Channel 5 Value + CMP5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x30); + + /// address: 0x43001034 + /// Count + pub const COUNT = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x34); + + /// address: 0x43001034 + /// Count + pub const COUNT_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Counter Value + COUNT: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x43001034 + /// Count + pub const COUNT_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Counter Value + COUNT: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x43001034 + /// Count + pub const COUNT_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Counter Value + COUNT: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x43001038 + /// Pattern + pub const PATT = @intToPtr(*volatile Mmio(16, packed struct { + /// Pattern Generator 0 Output Enable + PGE0: u1, + /// Pattern Generator 1 Output Enable + PGE1: u1, + /// Pattern Generator 2 Output Enable + PGE2: u1, + /// Pattern Generator 3 Output Enable + PGE3: u1, + /// Pattern Generator 4 Output Enable + PGE4: u1, + /// Pattern Generator 5 Output Enable + PGE5: u1, + /// Pattern Generator 6 Output Enable + PGE6: u1, + /// Pattern Generator 7 Output Enable + PGE7: u1, + /// Pattern Generator 0 Output Value + PGV0: u1, + /// Pattern Generator 1 Output Value + PGV1: u1, + /// Pattern Generator 2 Output Value + PGV2: u1, + /// Pattern Generator 3 Output Value + PGV3: u1, + /// Pattern Generator 4 Output Value + PGV4: u1, + /// Pattern Generator 5 Output Value + PGV5: u1, + /// Pattern Generator 6 Output Value + PGV6: u1, + /// Pattern Generator 7 Output Value + PGV7: u1, + }), base_address + 0x38); + + /// address: 0x4300103c + /// Waveform Control + pub const WAVE = @intToPtr(*volatile Mmio(32, packed struct { + /// Waveform Generation + WAVEGEN: u3, + reserved0: u1, + /// Ramp Mode + RAMP: u2, + reserved1: u1, + /// Circular period Enable + CIPEREN: u1, + /// Circular Channel 0 Enable + CICCEN0: u1, + /// Circular Channel 1 Enable + CICCEN1: u1, + /// Circular Channel 2 Enable + CICCEN2: u1, + /// Circular Channel 3 Enable + CICCEN3: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Channel 0 Polarity + POL0: u1, + /// Channel 1 Polarity + POL1: u1, + /// Channel 2 Polarity + POL2: u1, + /// Channel 3 Polarity + POL3: u1, + /// Channel 4 Polarity + POL4: u1, + /// Channel 5 Polarity + POL5: u1, + reserved6: u1, + reserved7: u1, + /// Swap DTI Output Pair 0 + SWAP0: u1, + /// Swap DTI Output Pair 1 + SWAP1: u1, + /// Swap DTI Output Pair 2 + SWAP2: u1, + /// Swap DTI Output Pair 3 + SWAP3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x3c); + + /// address: 0x43001040 + /// Period + pub const PER = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x40); + + /// address: 0x43001040 + /// Period + pub const PER_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u4, + /// Period Value + PER: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x43001040 + /// Period + pub const PER_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u5, + /// Period Value + PER: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x43001040 + /// Period + pub const PER_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u6, + /// Period Value + PER: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x43001044 + /// Compare and Capture + pub const CC = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x44); + + /// address: 0x43001044 + /// Compare and Capture + pub const CC_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u4, + /// Channel Compare/Capture Value + CC: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x43001044 + /// Compare and Capture + pub const CC_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u5, + /// Channel Compare/Capture Value + CC: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x43001044 + /// Compare and Capture + pub const CC_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u6, + /// Channel Compare/Capture Value + CC: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x43001064 + /// Pattern Buffer + pub const PATTBUF = @intToPtr(*volatile Mmio(16, packed struct { + /// Pattern Generator 0 Output Enable Buffer + PGEB0: u1, + /// Pattern Generator 1 Output Enable Buffer + PGEB1: u1, + /// Pattern Generator 2 Output Enable Buffer + PGEB2: u1, + /// Pattern Generator 3 Output Enable Buffer + PGEB3: u1, + /// Pattern Generator 4 Output Enable Buffer + PGEB4: u1, + /// Pattern Generator 5 Output Enable Buffer + PGEB5: u1, + /// Pattern Generator 6 Output Enable Buffer + PGEB6: u1, + /// Pattern Generator 7 Output Enable Buffer + PGEB7: u1, + /// Pattern Generator 0 Output Enable + PGVB0: u1, + /// Pattern Generator 1 Output Enable + PGVB1: u1, + /// Pattern Generator 2 Output Enable + PGVB2: u1, + /// Pattern Generator 3 Output Enable + PGVB3: u1, + /// Pattern Generator 4 Output Enable + PGVB4: u1, + /// Pattern Generator 5 Output Enable + PGVB5: u1, + /// Pattern Generator 6 Output Enable + PGVB6: u1, + /// Pattern Generator 7 Output Enable + PGVB7: u1, + }), base_address + 0x64); + + /// address: 0x4300106c + /// Period Buffer + pub const PERBUF = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x6c); + + /// address: 0x4300106c + /// Period Buffer + pub const PERBUF_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u4, + /// Period Buffer Value + PERBUF: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x4300106c + /// Period Buffer + pub const PERBUF_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u5, + /// Period Buffer Value + PERBUF: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x4300106c + /// Period Buffer + pub const PERBUF_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u6, + /// Period Buffer Value + PERBUF: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x43001070 + /// Compare and Capture Buffer + pub const CCBUF = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x70); + + /// address: 0x43001070 + /// Compare and Capture Buffer + pub const CCBUF_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Channel Compare/Capture Buffer Value + CCBUF: u4, + /// Dithering Buffer Cycle Number + DITHERBUF: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + + /// address: 0x43001070 + /// Compare and Capture Buffer + pub const CCBUF_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u5, + /// Channel Compare/Capture Buffer Value + CCBUF: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + + /// address: 0x43001070 + /// Compare and Capture Buffer + pub const CCBUF_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u6, + /// Channel Compare/Capture Buffer Value + CCBUF: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + }; + + /// True Random Generator + pub const TRNG = struct { + pub const base_address = 0x42002800; + pub const version = "U22421.1.0"; + + /// address: 0x42002800 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { + reserved0: u1, + /// Enable + ENABLE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Run in Standby + RUNSTDBY: u1, + padding0: u1, + }), base_address + 0x0); + + /// address: 0x42002804 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Ready Event Output + DATARDYEO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x4); + + /// address: 0x42002808 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Ready Interrupt Enable + DATARDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x8); + + /// address: 0x42002809 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Ready Interrupt Enable + DATARDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x9); + + /// address: 0x4200280a + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Ready Interrupt Flag + DATARDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0xa); + + /// address: 0x42002820 + /// Output Data + pub const DATA = @intToPtr(*volatile u32, base_address + 0x20); + }; + + /// Universal Serial Bus + pub const USB = struct { + pub const base_address = 0x41000000; + pub const version = "U22221.2.0"; + + /// USB is Device + pub const DEVICE = struct { + /// address: 0x41000000 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Run in Standby Mode + RUNSTDBY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Operating Mode + MODE: u1, + }), base_address + 0x0); + + /// address: 0x41000002 + /// Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(8, packed struct { + /// Software Reset Synchronization Busy + SWRST: u1, + /// Enable Synchronization Busy + ENABLE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x2); + + /// address: 0x41000003 + /// USB Quality Of Service + pub const QOSCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Configuration Quality of Service + CQOS: u2, + /// Data Quality of Service + DQOS: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x3); + + /// address: 0x41000008 + /// DEVICE Control B + pub const CTRLB = @intToPtr(*volatile Mmio(16, packed struct { + /// Detach + DETACH: u1, + /// Upstream Resume + UPRSM: u1, + /// Speed Configuration + SPDCONF: u2, + /// No Reply + NREPLY: u1, + /// Test mode J + TSTJ: u1, + /// Test mode K + TSTK: u1, + /// Test packet mode + TSTPCKT: u1, + /// Specific Operational Mode + OPMODE2: u1, + /// Global NAK + GNAK: u1, + /// Link Power Management Handshake + LPMHDSK: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x8); + + /// address: 0x4100000a + /// DEVICE Device Address + pub const DADD = @intToPtr(*volatile Mmio(8, packed struct { + /// Device Address + DADD: u7, + /// Device Address Enable + ADDEN: u1, + }), base_address + 0xa); + + /// address: 0x4100000c + /// DEVICE Status + pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { + reserved0: u1, + reserved1: u1, + /// Speed Status + SPEED: u2, + reserved2: u1, + reserved3: u1, + /// USB Line State Status + LINESTATE: u2, + }), base_address + 0xc); + + /// address: 0x4100000d + /// Finite State Machine Status + pub const FSMSTATUS = @intToPtr(*volatile Mmio(8, packed struct { + /// Fine State Machine Status + FSMSTATE: u7, + padding0: u1, + }), base_address + 0xd); + + /// address: 0x41000010 + /// DEVICE Device Frame Number + pub const FNUM = @intToPtr(*volatile Mmio(16, packed struct { + /// Micro Frame Number + MFNUM: u3, + /// Frame Number + FNUM: u11, + reserved0: u1, + /// Frame Number CRC Error + FNCERR: u1, + }), base_address + 0x10); + + /// address: 0x41000014 + /// DEVICE Device Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(16, packed struct { + /// Suspend Interrupt Enable + SUSPEND: u1, + /// Micro Start of Frame Interrupt Enable in High Speed Mode + MSOF: u1, + /// Start Of Frame Interrupt Enable + SOF: u1, + /// End of Reset Interrupt Enable + EORST: u1, + /// Wake Up Interrupt Enable + WAKEUP: u1, + /// End Of Resume Interrupt Enable + EORSM: u1, + /// Upstream Resume Interrupt Enable + UPRSM: u1, + /// Ram Access Interrupt Enable + RAMACER: u1, + /// Link Power Management Not Yet Interrupt Enable + LPMNYET: u1, + /// Link Power Management Suspend Interrupt Enable + LPMSUSP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x14); + + /// address: 0x41000018 + /// DEVICE Device Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(16, packed struct { + /// Suspend Interrupt Enable + SUSPEND: u1, + /// Micro Start of Frame Interrupt Enable in High Speed Mode + MSOF: u1, + /// Start Of Frame Interrupt Enable + SOF: u1, + /// End of Reset Interrupt Enable + EORST: u1, + /// Wake Up Interrupt Enable + WAKEUP: u1, + /// End Of Resume Interrupt Enable + EORSM: u1, + /// Upstream Resume Interrupt Enable + UPRSM: u1, + /// Ram Access Interrupt Enable + RAMACER: u1, + /// Link Power Management Not Yet Interrupt Enable + LPMNYET: u1, + /// Link Power Management Suspend Interrupt Enable + LPMSUSP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x18); + + /// address: 0x4100001c + /// DEVICE Device Interrupt Flag + pub const INTFLAG = @intToPtr(*volatile Mmio(16, packed struct { + /// Suspend + SUSPEND: u1, + /// Micro Start of Frame in High Speed Mode + MSOF: u1, + /// Start Of Frame + SOF: u1, + /// End of Reset + EORST: u1, + /// Wake Up + WAKEUP: u1, + /// End Of Resume + EORSM: u1, + /// Upstream Resume + UPRSM: u1, + /// Ram Access + RAMACER: u1, + /// Link Power Management Not Yet + LPMNYET: u1, + /// Link Power Management Suspend + LPMSUSP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x1c); + + /// address: 0x41000020 + /// DEVICE End Point Interrupt Summary + pub const EPINTSMRY = @intToPtr(*volatile Mmio(16, packed struct { + /// End Point 0 Interrupt + EPINT0: u1, + /// End Point 1 Interrupt + EPINT1: u1, + /// End Point 2 Interrupt + EPINT2: u1, + /// End Point 3 Interrupt + EPINT3: u1, + /// End Point 4 Interrupt + EPINT4: u1, + /// End Point 5 Interrupt + EPINT5: u1, + /// End Point 6 Interrupt + EPINT6: u1, + /// End Point 7 Interrupt + EPINT7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x20); + + /// address: 0x41000024 + /// Descriptor Address + pub const DESCADD = @intToPtr(*volatile u32, base_address + 0x24); + + /// address: 0x41000028 + /// USB PAD Calibration + pub const PADCAL = @intToPtr(*volatile Mmio(16, packed struct { + /// USB Pad Transp calibration + TRANSP: u5, + reserved0: u1, + /// USB Pad Transn calibration + TRANSN: u5, + reserved1: u1, + /// USB Pad Trim calibration + TRIM: u3, + padding0: u1, + }), base_address + 0x28); + }; + + /// USB is Host + pub const HOST = struct { + /// address: 0x41000000 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Run in Standby Mode + RUNSTDBY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Operating Mode + MODE: u1, + }), base_address + 0x0); + + /// address: 0x41000002 + /// Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(8, packed struct { + /// Software Reset Synchronization Busy + SWRST: u1, + /// Enable Synchronization Busy + ENABLE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x2); + + /// address: 0x41000003 + /// USB Quality Of Service + pub const QOSCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Configuration Quality of Service + CQOS: u2, + /// Data Quality of Service + DQOS: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x3); + + /// address: 0x41000008 + /// HOST Control B + pub const CTRLB = @intToPtr(*volatile Mmio(16, packed struct { + reserved0: u1, + /// Send USB Resume + RESUME: u1, + /// Speed Configuration for Host + SPDCONF: u2, + /// Auto Resume Enable + AUTORESUME: u1, + /// Test mode J + TSTJ: u1, + /// Test mode K + TSTK: u1, + reserved1: u1, + /// Start of Frame Generation Enable + SOFE: u1, + /// Send USB Reset + BUSRESET: u1, + /// VBUS is OK + VBUSOK: u1, + /// Send L1 Resume + L1RESUME: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x8); + + /// address: 0x4100000a + /// HOST Host Start Of Frame Control + pub const HSOFC = @intToPtr(*volatile Mmio(8, packed struct { + /// Frame Length Control + FLENC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Frame Length Control Enable + FLENCE: u1, + }), base_address + 0xa); + + /// address: 0x4100000c + /// HOST Status + pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { + reserved0: u1, + reserved1: u1, + /// Speed Status + SPEED: u2, + reserved2: u1, + reserved3: u1, + /// USB Line State Status + LINESTATE: u2, + }), base_address + 0xc); + + /// address: 0x4100000d + /// Finite State Machine Status + pub const FSMSTATUS = @intToPtr(*volatile Mmio(8, packed struct { + /// Fine State Machine Status + FSMSTATE: u7, + padding0: u1, + }), base_address + 0xd); + + /// address: 0x41000010 + /// HOST Host Frame Number + pub const FNUM = @intToPtr(*volatile Mmio(16, packed struct { + /// Micro Frame Number + MFNUM: u3, + /// Frame Number + FNUM: u11, + padding0: u1, + padding1: u1, + }), base_address + 0x10); + + /// address: 0x41000012 + /// HOST Host Frame Length + pub const FLENHIGH = @intToPtr(*volatile u8, base_address + 0x12); + + /// address: 0x41000014 + /// HOST Host Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(16, packed struct { + reserved0: u1, + reserved1: u1, + /// Host Start Of Frame Interrupt Disable + HSOF: u1, + /// BUS Reset Interrupt Disable + RST: u1, + /// Wake Up Interrupt Disable + WAKEUP: u1, + /// DownStream to Device Interrupt Disable + DNRSM: u1, + /// Upstream Resume from Device Interrupt Disable + UPRSM: u1, + /// Ram Access Interrupt Disable + RAMACER: u1, + /// Device Connection Interrupt Disable + DCONN: u1, + /// Device Disconnection Interrupt Disable + DDISC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x14); + + /// address: 0x41000018 + /// HOST Host Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(16, packed struct { + reserved0: u1, + reserved1: u1, + /// Host Start Of Frame Interrupt Enable + HSOF: u1, + /// Bus Reset Interrupt Enable + RST: u1, + /// Wake Up Interrupt Enable + WAKEUP: u1, + /// DownStream to the Device Interrupt Enable + DNRSM: u1, + /// Upstream Resume fromthe device Interrupt Enable + UPRSM: u1, + /// Ram Access Interrupt Enable + RAMACER: u1, + /// Link Power Management Interrupt Enable + DCONN: u1, + /// Device Disconnection Interrupt Enable + DDISC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x18); + + /// address: 0x4100001c + /// HOST Host Interrupt Flag + pub const INTFLAG = @intToPtr(*volatile Mmio(16, packed struct { + reserved0: u1, + reserved1: u1, + /// Host Start Of Frame + HSOF: u1, + /// Bus Reset + RST: u1, + /// Wake Up + WAKEUP: u1, + /// Downstream + DNRSM: u1, + /// Upstream Resume from the Device + UPRSM: u1, + /// Ram Access + RAMACER: u1, + /// Device Connection + DCONN: u1, + /// Device Disconnection + DDISC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x1c); + + /// address: 0x41000020 + /// HOST Pipe Interrupt Summary + pub const PINTSMRY = @intToPtr(*volatile Mmio(16, packed struct { + /// Pipe 0 Interrupt + EPINT0: u1, + /// Pipe 1 Interrupt + EPINT1: u1, + /// Pipe 2 Interrupt + EPINT2: u1, + /// Pipe 3 Interrupt + EPINT3: u1, + /// Pipe 4 Interrupt + EPINT4: u1, + /// Pipe 5 Interrupt + EPINT5: u1, + /// Pipe 6 Interrupt + EPINT6: u1, + /// Pipe 7 Interrupt + EPINT7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x20); + + /// address: 0x41000024 + /// Descriptor Address + pub const DESCADD = @intToPtr(*volatile u32, base_address + 0x24); + + /// address: 0x41000028 + /// USB PAD Calibration + pub const PADCAL = @intToPtr(*volatile Mmio(16, packed struct { + /// USB Pad Transp calibration + TRANSP: u5, + reserved0: u1, + /// USB Pad Transn calibration + TRANSN: u5, + reserved1: u1, + /// USB Pad Trim calibration + TRIM: u3, + padding0: u1, + }), base_address + 0x28); + }; + }; + + /// Watchdog Timer + pub const WDT = struct { + pub const base_address = 0x40002000; + pub const version = "U22511.1.0"; + + /// address: 0x40002000 + /// Control + pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { + reserved0: u1, + /// Enable + ENABLE: u1, + /// Watchdog Timer Window Mode Enable + WEN: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Always-On + ALWAYSON: u1, + }), base_address + 0x0); + + /// address: 0x40002001 + /// Configuration + pub const CONFIG = @intToPtr(*volatile Mmio(8, packed struct { + /// Time-Out Period + PER: u4, + /// Window Mode Time-Out Period + WINDOW: u4, + }), base_address + 0x1); + + /// address: 0x40002002 + /// Early Warning Interrupt Control + pub const EWCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Early Warning Interrupt Time Offset + EWOFFSET: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x2); + + /// address: 0x40002004 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Early Warning Interrupt Enable + EW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x4); + + /// address: 0x40002005 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Early Warning Interrupt Enable + EW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x5); + + /// address: 0x40002006 + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Early Warning + EW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x6); + + /// address: 0x40002008 + /// Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Enable Synchronization Busy + ENABLE: u1, + /// Window Enable Synchronization Busy + WEN: u1, + /// Always-On Synchronization Busy + ALWAYSON: u1, + /// Clear Synchronization Busy + CLEAR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x8); + + /// address: 0x4000200c + /// Clear + pub const CLEAR = @intToPtr(*volatile u8, base_address + 0xc); + }; + + /// Core Debug Register + pub const CoreDebug = struct { + pub const base_address = 0xe000edf0; + + /// address: 0xe000edf0 + /// Debug Halting Control and Status Register + pub const DHCSR = @intToPtr(*volatile Mmio(32, packed struct { + C_DEBUGEN: u1, + C_HALT: u1, + C_STEP: u1, + C_MASKINTS: u1, + reserved0: u1, + C_SNAPSTALL: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + S_REGRDY: u1, + S_HALT: u1, + S_SLEEP: u1, + S_LOCKUP: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + S_RETIRE_ST: u1, + S_RESET_ST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x0); + + /// address: 0xe000edf4 + /// Debug Core Register Selector Register + pub const DCRSR = @intToPtr(*volatile Mmio(32, packed struct { + REGSEL: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + REGWnR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x4); + + /// address: 0xe000edf8 + /// Debug Core Register Data Register + pub const DCRDR = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0xe000edfc + /// Debug Exception and Monitor Control Register + pub const DEMCR = @intToPtr(*volatile Mmio(32, packed struct { + VC_CORERESET: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + VC_MMERR: u1, + VC_NOCPERR: u1, + VC_CHKERR: u1, + VC_STATERR: u1, + VC_BUSERR: u1, + VC_INTERR: u1, + VC_HARDERR: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + MON_EN: u1, + MON_PEND: u1, + MON_STEP: u1, + MON_REQ: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + TRCENA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0xc); + }; + + /// Data Watchpoint and Trace Register + pub const DWT = struct { + pub const base_address = 0xe0001000; + + /// address: 0xe0001000 + /// Control Register + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + CYCCNTENA: u1, + POSTPRESET: u4, + POSTINIT: u4, + CYCTAP: u1, + SYNCTAP: u2, + PCSAMPLENA: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + EXCTRCENA: u1, + CPIEVTENA: u1, + EXCEVTENA: u1, + SLEEPEVTENA: u1, + LSUEVTENA: u1, + FOLDEVTENA: u1, + CYCEVTENA: u1, + reserved3: u1, + NOPRFCNT: u1, + NOCYCCNT: u1, + NOEXTTRIG: u1, + NOTRCPKT: u1, + NUMCOMP: u4, + }), base_address + 0x0); + + /// address: 0xe0001004 + /// Cycle Count Register + pub const CYCCNT = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0xe0001008 + /// CPI Count Register + pub const CPICNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); + + /// address: 0xe000100c + /// Exception Overhead Count Register + pub const EXCCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xc); + + /// address: 0xe0001010 + /// Sleep Count Register + pub const SLEEPCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x10); + + /// address: 0xe0001014 + /// LSU Count Register + pub const LSUCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x14); + + /// address: 0xe0001018 + /// Folded-instruction Count Register + pub const FOLDCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x18); + + /// address: 0xe000101c + /// Program Counter Sample Register + pub const PCSR = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0xe0001020 + /// Comparator Register 0 + pub const COMP0 = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0xe0001024 + /// Mask Register 0 + pub const MASK0 = @intToPtr(*volatile Mmio(32, packed struct { + MASK: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x24); + + /// address: 0xe0001028 + /// Function Register 0 + pub const FUNCTION0 = @intToPtr(*volatile Mmio(32, packed struct { + FUNCTION: u4, + reserved0: u1, + EMITRANGE: u1, + reserved1: u1, + CYCMATCH: u1, + DATAVMATCH: u1, + LNK1ENA: u1, + DATAVSIZE: u2, + DATAVADDR0: u4, + DATAVADDR1: u4, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + MATCHED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x28); + + /// address: 0xe0001030 + /// Comparator Register 1 + pub const COMP1 = @intToPtr(*volatile u32, base_address + 0x30); + + /// address: 0xe0001034 + /// Mask Register 1 + pub const MASK1 = @intToPtr(*volatile Mmio(32, packed struct { + MASK: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x34); + + /// address: 0xe0001038 + /// Function Register 1 + pub const FUNCTION1 = @intToPtr(*volatile Mmio(32, packed struct { + FUNCTION: u4, + reserved0: u1, + EMITRANGE: u1, + reserved1: u1, + CYCMATCH: u1, + DATAVMATCH: u1, + LNK1ENA: u1, + DATAVSIZE: u2, + DATAVADDR0: u4, + DATAVADDR1: u4, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + MATCHED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x38); + + /// address: 0xe0001040 + /// Comparator Register 2 + pub const COMP2 = @intToPtr(*volatile u32, base_address + 0x40); + + /// address: 0xe0001044 + /// Mask Register 2 + pub const MASK2 = @intToPtr(*volatile Mmio(32, packed struct { + MASK: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x44); + + /// address: 0xe0001048 + /// Function Register 2 + pub const FUNCTION2 = @intToPtr(*volatile Mmio(32, packed struct { + FUNCTION: u4, + reserved0: u1, + EMITRANGE: u1, + reserved1: u1, + CYCMATCH: u1, + DATAVMATCH: u1, + LNK1ENA: u1, + DATAVSIZE: u2, + DATAVADDR0: u4, + DATAVADDR1: u4, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + MATCHED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x48); + + /// address: 0xe0001050 + /// Comparator Register 3 + pub const COMP3 = @intToPtr(*volatile u32, base_address + 0x50); + + /// address: 0xe0001054 + /// Mask Register 3 + pub const MASK3 = @intToPtr(*volatile Mmio(32, packed struct { + MASK: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x54); + + /// address: 0xe0001058 + /// Function Register 3 + pub const FUNCTION3 = @intToPtr(*volatile Mmio(32, packed struct { + FUNCTION: u4, + reserved0: u1, + EMITRANGE: u1, + reserved1: u1, + CYCMATCH: u1, + DATAVMATCH: u1, + LNK1ENA: u1, + DATAVSIZE: u2, + DATAVADDR0: u4, + DATAVADDR1: u4, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + MATCHED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x58); + }; + + /// Embedded Trace Macrocell + pub const ETM = struct { + pub const base_address = 0xe0041000; + + /// address: 0xe0041000 + /// ETM Main Control Register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// ETM Power Down + ETMPD: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Port Size bits 2:0 + PORTSIZE: u3, + /// Stall Processor + STALL: u1, + /// Branch Output + BROUT: u1, + /// Debug Request Control + DBGRQ: u1, + /// ETM Programming + PROG: u1, + /// ETM Port Select + PORTSEL: u1, + reserved3: u1, + /// Port Mode bit 2 + PORTMODE2: u1, + reserved4: u1, + reserved5: u1, + /// Port Mode bits 1:0 + PORTMODE: u2, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Port Size bit 3 + PORTSIZE3: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// TimeStamp Enable + TSEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x0); + + /// address: 0xe0041004 + /// ETM Configuration Code Register + pub const CCR = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0xe0041008 + /// ETM Trigger Event Register + pub const TRIGGER = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0xe0041010 + /// ETM Status Register + pub const SR = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0xe0041014 + /// ETM System Configuration Register + pub const SCR = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0xe0041020 + /// ETM TraceEnable Event Register + pub const TEEVR = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0xe0041024 + /// ETM TraceEnable Control 1 Register + pub const TECR1 = @intToPtr(*volatile u32, base_address + 0x24); + + /// address: 0xe0041028 + /// ETM FIFO Full Level Register + pub const FFLR = @intToPtr(*volatile u32, base_address + 0x28); + + /// address: 0xe0041140 + /// ETM Free-running Counter Reload Value + pub const CNTRLDVR1 = @intToPtr(*volatile u32, base_address + 0x140); + + /// address: 0xe00411e0 + /// ETM Synchronization Frequency Register + pub const SYNCFR = @intToPtr(*volatile u32, base_address + 0x1e0); + + /// address: 0xe00411e4 + /// ETM ID Register + pub const IDR = @intToPtr(*volatile u32, base_address + 0x1e4); + + /// address: 0xe00411e8 + /// ETM Configuration Code Extension Register + pub const CCER = @intToPtr(*volatile u32, base_address + 0x1e8); + + /// address: 0xe00411f0 + /// ETM TraceEnable Start/Stop EmbeddedICE Control Register + pub const TESSEICR = @intToPtr(*volatile u32, base_address + 0x1f0); + + /// address: 0xe00411f8 + /// ETM TimeStamp Event Register + pub const TSEVT = @intToPtr(*volatile u32, base_address + 0x1f8); + + /// address: 0xe0041200 + /// ETM CoreSight Trace ID Register + pub const TRACEIDR = @intToPtr(*volatile u32, base_address + 0x200); + + /// address: 0xe0041208 + /// ETM ID Register 2 + pub const IDR2 = @intToPtr(*volatile u32, base_address + 0x208); + + /// address: 0xe0041314 + /// ETM Device Power-Down Status Register + pub const PDSR = @intToPtr(*volatile u32, base_address + 0x314); + + /// address: 0xe0041ee0 + /// ETM Integration Test Miscellaneous Inputs + pub const ITMISCIN = @intToPtr(*volatile u32, base_address + 0xee0); + + /// address: 0xe0041ee8 + /// ETM Integration Test Trigger Out + pub const ITTRIGOUT = @intToPtr(*volatile u32, base_address + 0xee8); + + /// address: 0xe0041ef0 + /// ETM Integration Test ATB Control 2 + pub const ITATBCTR2 = @intToPtr(*volatile u32, base_address + 0xef0); + + /// address: 0xe0041ef8 + /// ETM Integration Test ATB Control 0 + pub const ITATBCTR0 = @intToPtr(*volatile u32, base_address + 0xef8); + + /// address: 0xe0041f00 + /// ETM Integration Mode Control Register + pub const ITCTRL = @intToPtr(*volatile Mmio(32, packed struct { + INTEGRATION: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0xf00); + + /// address: 0xe0041fa0 + /// ETM Claim Tag Set Register + pub const CLAIMSET = @intToPtr(*volatile u32, base_address + 0xfa0); + + /// address: 0xe0041fa4 + /// ETM Claim Tag Clear Register + pub const CLAIMCLR = @intToPtr(*volatile u32, base_address + 0xfa4); + + /// address: 0xe0041fb0 + /// ETM Lock Access Register + pub const LAR = @intToPtr(*volatile u32, base_address + 0xfb0); + + /// address: 0xe0041fb4 + /// ETM Lock Status Register + pub const LSR = @intToPtr(*volatile Mmio(32, packed struct { + Present: u1, + Access: u1, + ByteAcc: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0xfb4); + + /// address: 0xe0041fb8 + /// ETM Authentication Status Register + pub const AUTHSTATUS = @intToPtr(*volatile u32, base_address + 0xfb8); + + /// address: 0xe0041fcc + /// ETM CoreSight Device Type Register + pub const DEVTYPE = @intToPtr(*volatile u32, base_address + 0xfcc); + + /// address: 0xe0041fd0 + /// ETM Peripheral Identification Register #4 + pub const PIDR4 = @intToPtr(*volatile u32, base_address + 0xfd0); + + /// address: 0xe0041fd4 + /// ETM Peripheral Identification Register #5 + pub const PIDR5 = @intToPtr(*volatile u32, base_address + 0xfd4); + + /// address: 0xe0041fd8 + /// ETM Peripheral Identification Register #6 + pub const PIDR6 = @intToPtr(*volatile u32, base_address + 0xfd8); + + /// address: 0xe0041fdc + /// ETM Peripheral Identification Register #7 + pub const PIDR7 = @intToPtr(*volatile u32, base_address + 0xfdc); + + /// address: 0xe0041fe0 + /// ETM Peripheral Identification Register #0 + pub const PIDR0 = @intToPtr(*volatile u32, base_address + 0xfe0); + + /// address: 0xe0041fe4 + /// ETM Peripheral Identification Register #1 + pub const PIDR1 = @intToPtr(*volatile u32, base_address + 0xfe4); + + /// address: 0xe0041fe8 + /// ETM Peripheral Identification Register #2 + pub const PIDR2 = @intToPtr(*volatile u32, base_address + 0xfe8); + + /// address: 0xe0041fec + /// ETM Peripheral Identification Register #3 + pub const PIDR3 = @intToPtr(*volatile u32, base_address + 0xfec); + + /// address: 0xe0041ff0 + /// ETM Component Identification Register #0 + pub const CIDR0 = @intToPtr(*volatile u32, base_address + 0xff0); + + /// address: 0xe0041ff4 + /// ETM Component Identification Register #1 + pub const CIDR1 = @intToPtr(*volatile u32, base_address + 0xff4); + + /// address: 0xe0041ff8 + /// ETM Component Identification Register #2 + pub const CIDR2 = @intToPtr(*volatile u32, base_address + 0xff8); + + /// address: 0xe0041ffc + /// ETM Component Identification Register #3 + pub const CIDR3 = @intToPtr(*volatile u32, base_address + 0xffc); + }; + + /// Floating Point Unit + pub const FPU = struct { + pub const base_address = 0xe000ef30; + + /// address: 0xe000ef34 + /// Floating-Point Context Control Register + pub const FPCCR = @intToPtr(*volatile Mmio(32, packed struct { + LSPACT: u1, + USER: u1, + reserved0: u1, + THREAD: u1, + HFRDY: u1, + MMRDY: u1, + BFRDY: u1, + reserved1: u1, + MONRDY: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + LSPEN: u1, + ASPEN: u1, + }), base_address + 0x4); + + /// address: 0xe000ef38 + /// Floating-Point Context Address Register + pub const FPCAR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Address for FP registers in exception stack frame + ADDRESS: u29, + }), base_address + 0x8); + + /// address: 0xe000ef3c + /// Floating-Point Default Status Control Register + pub const FPDSCR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// Default value for FPSCR.RMODE + RMODE: u2, + /// Default value for FPSCR.FZ + FZ: u1, + /// Default value for FPSCR.DN + DN: u1, + /// Default value for FPSCR.AHP + AHP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0xc); + + /// address: 0xe000ef40 + /// Media and FP Feature Register 0 + pub const MVFR0 = @intToPtr(*volatile Mmio(32, packed struct { + A_SIMD_registers: u4, + Single_precision: u4, + Double_precision: u4, + FP_excep_trapping: u4, + Divide: u4, + Square_root: u4, + Short_vectors: u4, + FP_rounding_modes: u4, + }), base_address + 0x10); + + /// address: 0xe000ef44 + /// Media and FP Feature Register 1 + pub const MVFR1 = @intToPtr(*volatile Mmio(32, packed struct { + FtZ_mode: u4, + D_NaN_mode: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + FP_HPFP: u4, + FP_fused_MAC: u4, + }), base_address + 0x14); + }; + + /// Instrumentation Trace Macrocell + pub const ITM = struct { + pub const base_address = 0xe0000000; + + /// address: 0xe0000000 + /// ITM Stimulus Port Registers + pub const PORT_WORD_MODE = @intToPtr(*volatile [32]Mmio(32, packed struct { + PORT: u32, + }), base_address + 0x0); + + /// address: 0xe0000000 + /// ITM Stimulus Port Registers + pub const PORT_BYTE_MODE = @intToPtr(*volatile [32]Mmio(32, packed struct { + PORT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x0); + + /// address: 0xe0000000 + /// ITM Stimulus Port Registers + pub const PORT_HWORD_MODE = @intToPtr(*volatile [32]Mmio(32, packed struct { + PORT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0xe0000e00 + /// ITM Trace Enable Register + pub const TER = @intToPtr(*volatile u32, base_address + 0xe00); + + /// address: 0xe0000e40 + /// ITM Trace Privilege Register + pub const TPR = @intToPtr(*volatile Mmio(32, packed struct { + PRIVMASK: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0xe40); + + /// address: 0xe0000e80 + /// ITM Trace Control Register + pub const TCR = @intToPtr(*volatile Mmio(32, packed struct { + ITMENA: u1, + TSENA: u1, + SYNCENA: u1, + DWTENA: u1, + SWOENA: u1, + STALLENA: u1, + reserved0: u1, + reserved1: u1, + TSPrescale: u2, + GTSFREQ: u2, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + TraceBusID: u7, + BUSY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0xe80); + + /// address: 0xe0000ef8 + /// ITM Integration Write Register + pub const IWR = @intToPtr(*volatile Mmio(32, packed struct { + ATVALIDM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0xef8); + + /// address: 0xe0000efc + /// ITM Integration Read Register + pub const IRR = @intToPtr(*volatile Mmio(32, packed struct { + ATREADYM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0xefc); + }; + + /// Memory Protection Unit + pub const MPU = struct { + pub const base_address = 0xe000ed90; + + /// address: 0xe000ed90 + /// MPU Type Register + pub const TYPE = @intToPtr(*volatile Mmio(32, packed struct { + /// Separate instruction and Data Memory MapsRegions + SEPARATE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Number of Data Regions + DREGION: u8, + /// Number of Instruction Regions + IREGION: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x0); + + /// address: 0xe000ed94 + /// MPU Control Register + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// MPU Enable + ENABLE: u1, + /// Enable Hard Fault and NMI handlers + HFNMIENA: u1, + /// Enables privileged software access to default memory map + PRIVDEFENA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x4); + + /// address: 0xe000ed98 + /// MPU Region Number Register + pub const RNR = @intToPtr(*volatile Mmio(32, packed struct { + /// Region referenced by RBAR and RASR + REGION: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x8); + + /// address: 0xe000ed9c + /// MPU Region Base Address Register + pub const RBAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Region number + REGION: u4, + /// Region number valid + VALID: u1, + /// Region base address + ADDR: u27, + }), base_address + 0xc); + + /// address: 0xe000eda0 + /// MPU Region Attribute and Size Register + pub const RASR = @intToPtr(*volatile Mmio(32, packed struct { + /// Region Enable + ENABLE: u1, + /// Region Size + SIZE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Sub-region disable + SRD: u8, + /// Bufferable bit + B: u1, + /// Cacheable bit + C: u1, + /// Shareable bit + S: u1, + /// TEX bit + TEX: u3, + reserved6: u1, + reserved7: u1, + /// Access Permission + AP: u3, + reserved8: u1, + /// Execute Never Attribute + XN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x10); + + /// address: 0xe000eda4 + /// MPU Alias 1 Region Base Address Register + pub const RBAR_A1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Region number + REGION: u4, + /// Region number valid + VALID: u1, + /// Region base address + ADDR: u27, + }), base_address + 0x14); + + /// address: 0xe000eda8 + /// MPU Alias 1 Region Attribute and Size Register + pub const RASR_A1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Region Enable + ENABLE: u1, + /// Region Size + SIZE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Sub-region disable + SRD: u8, + /// Bufferable bit + B: u1, + /// Cacheable bit + C: u1, + /// Shareable bit + S: u1, + /// TEX bit + TEX: u3, + reserved6: u1, + reserved7: u1, + /// Access Permission + AP: u3, + reserved8: u1, + /// Execute Never Attribute + XN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x18); + + /// address: 0xe000edac + /// MPU Alias 2 Region Base Address Register + pub const RBAR_A2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Region number + REGION: u4, + /// Region number valid + VALID: u1, + /// Region base address + ADDR: u27, + }), base_address + 0x1c); + + /// address: 0xe000edb0 + /// MPU Alias 2 Region Attribute and Size Register + pub const RASR_A2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Region Enable + ENABLE: u1, + /// Region Size + SIZE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Sub-region disable + SRD: u8, + /// Bufferable bit + B: u1, + /// Cacheable bit + C: u1, + /// Shareable bit + S: u1, + /// TEX bit + TEX: u3, + reserved6: u1, + reserved7: u1, + /// Access Permission + AP: u3, + reserved8: u1, + /// Execute Never Attribute + XN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x20); + + /// address: 0xe000edb4 + /// MPU Alias 3 Region Base Address Register + pub const RBAR_A3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Region number + REGION: u4, + /// Region number valid + VALID: u1, + /// Region base address + ADDR: u27, + }), base_address + 0x24); + + /// address: 0xe000edb8 + /// MPU Alias 3 Region Attribute and Size Register + pub const RASR_A3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Region Enable + ENABLE: u1, + /// Region Size + SIZE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Sub-region disable + SRD: u8, + /// Bufferable bit + B: u1, + /// Cacheable bit + C: u1, + /// Shareable bit + S: u1, + /// TEX bit + TEX: u3, + reserved6: u1, + reserved7: u1, + /// Access Permission + AP: u3, + reserved8: u1, + /// Execute Never Attribute + XN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x28); + }; + + /// Nested Vectored Interrupt Controller + pub const NVIC = struct { + pub const base_address = 0xe000e100; + + /// address: 0xe000e100 + /// Interrupt Set Enable Register + pub const ISER = @intToPtr(*volatile [5]Mmio(32, packed struct { + /// Interrupt set enable bits + SETENA: u32, + }), base_address + 0x0); + + /// address: 0xe000e180 + /// Interrupt Clear Enable Register + pub const ICER = @intToPtr(*volatile [5]Mmio(32, packed struct { + /// Interrupt clear-enable bits + CLRENA: u32, + }), base_address + 0x80); + + /// address: 0xe000e200 + /// Interrupt Set Pending Register + pub const ISPR = @intToPtr(*volatile [5]Mmio(32, packed struct { + /// Interrupt set-pending bits + SETPEND: u32, + }), base_address + 0x100); + + /// address: 0xe000e280 + /// Interrupt Clear Pending Register + pub const ICPR = @intToPtr(*volatile [5]Mmio(32, packed struct { + /// Interrupt clear-pending bits + CLRPEND: u32, + }), base_address + 0x180); + + /// address: 0xe000e300 + /// Interrupt Active Bit Register + pub const IABR = @intToPtr(*volatile [5]Mmio(32, packed struct { + /// Interrupt active bits + ACTIVE: u32, + }), base_address + 0x200); + + /// address: 0xe000e400 + /// Interrupt Priority Register n + pub const IP = @intToPtr(*volatile [35]Mmio(8, packed struct { + /// Priority of interrupt n + PRI0: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x300); + + /// address: 0xe000ef00 + /// Software Trigger Interrupt Register + pub const STIR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt ID to trigger + INTID: u9, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0xe00); + }; + + /// System timer + pub const SysTick = struct { + pub const base_address = 0xe000e010; + }; + + /// System Control Registers + pub const SystemControl = struct { + pub const base_address = 0xe000e000; + + /// address: 0xe000e004 + /// Interrupt Controller Type Register + pub const ICTR = @intToPtr(*volatile Mmio(32, packed struct { + INTLINESNUM: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x4); + + /// address: 0xe000e008 + /// Auxiliary Control Register + pub const ACTLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Disable interruption of LDM/STM instructions + DISMCYCINT: u1, + /// Disable wruite buffer use during default memory map accesses + DISDEFWBUF: u1, + /// Disable IT folding + DISFOLD: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Disable automatic update of CONTROL.FPCA + DISFPCA: u1, + /// Disable out-of-order FP instructions + DISOOFP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x8); + + /// address: 0xe000ed00 + /// CPUID Base Register + pub const CPUID = @intToPtr(*volatile Mmio(32, packed struct { + /// Processor revision number + REVISION: u4, + /// Process Part Number, 0xC24=Cortex-M4 + PARTNO: u12, + /// Constant + CONSTANT: u4, + /// Variant number + VARIANT: u4, + /// Implementer code, 0x41=ARM + IMPLEMENTER: u8, + }), base_address + 0xd00); + + /// address: 0xe000ed04 + /// Interrupt Control and State Register + pub const ICSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Active exception number + VECTACTIVE: u9, + reserved0: u1, + reserved1: u1, + /// No preempted active exceptions to execute + RETTOBASE: u1, + /// Exception number of the highest priority pending enabled exception + VECTPENDING: u6, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Interrupt pending flag + ISRPENDING: u1, + /// Debug only + ISRPREEMPT: u1, + reserved6: u1, + /// SysTick clear-pending bit + PENDSTCLR: u1, + /// SysTick set-pending bit + PENDSTSET: u1, + /// PendSV clear-pending bit + PENDSVCLR: u1, + /// PendSV set-pending bit + PENDSVSET: u1, + reserved7: u1, + reserved8: u1, + /// NMI set-pending bit + NMIPENDSET: u1, + }), base_address + 0xd04); + + /// address: 0xe000ed08 + /// Vector Table Offset Register + pub const VTOR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Vector table base offset + TBLOFF: u25, + }), base_address + 0xd08); + + /// address: 0xe000ed0c + /// Application Interrupt and Reset Control Register + pub const AIRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Must write 0 + VECTRESET: u1, + /// Must write 0 + VECTCLRACTIVE: u1, + /// System Reset Request + SYSRESETREQ: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Interrupt priority grouping + PRIGROUP: u3, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Data endianness, 0=little, 1=big + ENDIANNESS: u1, + /// Register key + VECTKEY: u16, + }), base_address + 0xd0c); + + /// address: 0xe000ed10 + /// System Control Register + pub const SCR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Sleep-on-exit on handler return + SLEEPONEXIT: u1, + /// Deep Sleep used as low power mode + SLEEPDEEP: u1, + reserved1: u1, + /// Send Event on Pending bit + SEVONPEND: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0xd10); + + /// address: 0xe000ed14 + /// Configuration and Control Register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Indicates how processor enters Thread mode + NONBASETHRDENA: u1, + /// Enables unprivileged software access to STIR register + USERSETMPEND: u1, + reserved0: u1, + /// Enables unaligned access traps + UNALIGN_TRP: u1, + /// Enables divide by 0 trap + DIV_0_TRP: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Ignore LDM/STM BusFault for -1/-2 priority handlers + BFHFNMIGN: u1, + /// Indicates stack alignment on exception entry + STKALIGN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0xd14); + + /// address: 0xe000ed18 + /// System Handler Priority Register 1 + pub const SHPR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Priority of system handler 4, MemManage + PRI_4: u8, + /// Priority of system handler 5, BusFault + PRI_5: u8, + /// Priority of system handler 6, UsageFault + PRI_6: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0xd18); + + /// address: 0xe000ed1c + /// System Handler Priority Register 2 + pub const SHPR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + /// Priority of system handler 11, SVCall + PRI_11: u8, + }), base_address + 0xd1c); + + /// address: 0xe000ed20 + /// System Handler Priority Register 3 + pub const SHPR3 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Priority of system handler 14, PendSV + PRI_14: u8, + /// Priority of system handler 15, SysTick exception + PRI_15: u8, + }), base_address + 0xd20); + + /// address: 0xe000ed24 + /// System Handler Control and State Register + pub const SHCSR = @intToPtr(*volatile Mmio(32, packed struct { + /// MemManage exception active bit + MEMFAULTACT: u1, + /// BusFault exception active bit + BUSFAULTACT: u1, + reserved0: u1, + /// UsageFault exception active bit + USGFAULTACT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// SVCall active bit + SVCALLACT: u1, + /// DebugMonitor exception active bit + MONITORACT: u1, + reserved4: u1, + /// PendSV exception active bit + PENDSVACT: u1, + /// SysTick exception active bit + SYSTICKACT: u1, + /// UsageFault exception pending bit + USGFAULTPENDED: u1, + /// MemManage exception pending bit + MEMFAULTPENDED: u1, + /// BusFault exception pending bit + BUSFAULTPENDED: u1, + /// SVCall pending bit + SVCALLPENDED: u1, + /// MemManage enable bit + MEMFAULTENA: u1, + /// BusFault enable bit + BUSFAULTENA: u1, + /// UsageFault enable bit + USGFAULTENA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xd24); + + /// address: 0xe000ed28 + /// Configurable Fault Status Register + pub const CFSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Instruction access violation + IACCVIOL: u1, + /// Data access violation + DACCVIOL: u1, + reserved0: u1, + /// MemManage Fault on unstacking for exception return + MUNSTKERR: u1, + /// MemManage Fault on stacking for exception entry + MSTKERR: u1, + /// MemManager Fault occured during FP lazy state preservation + MLSPERR: u1, + reserved1: u1, + /// MemManage Fault Address Register valid + MMARVALID: u1, + /// Instruction bus error + IBUSERR: u1, + /// Precise data bus error + PRECISERR: u1, + /// Imprecise data bus error + IMPRECISERR: u1, + /// BusFault on unstacking for exception return + UNSTKERR: u1, + /// BusFault on stacking for exception entry + STKERR: u1, + /// BusFault occured during FP lazy state preservation + LSPERR: u1, + reserved2: u1, + /// BusFault Address Register valid + BFARVALID: u1, + /// Undefined instruction UsageFault + UNDEFINSTR: u1, + /// Invalid state UsageFault + INVSTATE: u1, + /// Invalid PC load UsageFault + INVPC: u1, + /// No coprocessor UsageFault + NOCP: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Unaligned access UsageFault + UNALIGNED: u1, + /// Divide by zero UsageFault + DIVBYZERO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xd28); + + /// address: 0xe000ed2c + /// HardFault Status Register + pub const HFSR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// BusFault on a Vector Table read during exception processing + VECTTBL: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + reserved26: u1, + reserved27: u1, + reserved28: u1, + /// Forced Hard Fault + FORCED: u1, + /// Debug: always write 0 + DEBUGEVT: u1, + }), base_address + 0xd2c); + + /// address: 0xe000ed30 + /// Debug Fault Status Register + pub const DFSR = @intToPtr(*volatile Mmio(32, packed struct { + HALTED: u1, + BKPT: u1, + DWTTRAP: u1, + VCATCH: u1, + EXTERNAL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0xd30); + + /// address: 0xe000ed34 + /// MemManage Fault Address Register + pub const MMFAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Address that generated the MemManage fault + ADDRESS: u32, + }), base_address + 0xd34); + + /// address: 0xe000ed38 + /// BusFault Address Register + pub const BFAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Address that generated the BusFault + ADDRESS: u32, + }), base_address + 0xd38); + + /// address: 0xe000ed3c + /// Auxiliary Fault Status Register + pub const AFSR = @intToPtr(*volatile Mmio(32, packed struct { + /// AUXFAULT input signals + IMPDEF: u32, + }), base_address + 0xd3c); + + /// address: 0xe000ed40 + /// Processor Feature Register + pub const PFR = @intToPtr(*volatile [2]u32, base_address + 0xd40); + + /// address: 0xe000ed48 + /// Debug Feature Register + pub const DFR = @intToPtr(*volatile u32, base_address + 0xd48); + + /// address: 0xe000ed4c + /// Auxiliary Feature Register + pub const ADR = @intToPtr(*volatile u32, base_address + 0xd4c); + + /// address: 0xe000ed50 + /// Memory Model Feature Register + pub const MMFR = @intToPtr(*volatile [4]u32, base_address + 0xd50); + + /// address: 0xe000ed60 + /// Instruction Set Attributes Register + pub const ISAR = @intToPtr(*volatile [5]u32, base_address + 0xd60); + + /// address: 0xe000ed88 + /// Coprocessor Access Control Register + pub const CPACR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + /// Access privileges for coprocessor 10 + CP10: u2, + /// Access privileges for coprocessor 11 + CP11: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0xd88); + }; + + /// Trace Port Interface Register + pub const TPI = struct { + pub const base_address = 0xe0040000; + + /// address: 0xe0040000 + /// Supported Parallel Port Size Register + pub const SSPSR = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0xe0040004 + /// Current Parallel Port Size Register + pub const CSPSR = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0xe0040010 + /// Asynchronous Clock Prescaler Register + pub const ACPR = @intToPtr(*volatile Mmio(32, packed struct { + PRESCALER: u13, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0xe00400f0 + /// Selected Pin Protocol Register + pub const SPPR = @intToPtr(*volatile Mmio(32, packed struct { + TXMODE: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xf0); + + /// address: 0xe0040300 + /// Formatter and Flush Status Register + pub const FFSR = @intToPtr(*volatile Mmio(32, packed struct { + FlInProg: u1, + FtStopped: u1, + TCPresent: u1, + FtNonStop: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x300); + + /// address: 0xe0040304 + /// Formatter and Flush Control Register + pub const FFCR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + EnFCont: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + TrigIn: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x304); + + /// address: 0xe0040308 + /// Formatter Synchronization Counter Register + pub const FSCR = @intToPtr(*volatile u32, base_address + 0x308); + + /// address: 0xe0040ee8 + /// TRIGGER + pub const TRIGGER = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xee8); + + /// address: 0xe0040eec + /// Integration ETM Data + pub const FIFO0 = @intToPtr(*volatile Mmio(32, packed struct { + ETM0: u8, + ETM1: u8, + ETM2: u8, + ETM_bytecount: u2, + ETM_ATVALID: u1, + ITM_bytecount: u2, + ITM_ATVALID: u1, + padding0: u1, + padding1: u1, + }), base_address + 0xeec); + + /// address: 0xe0040ef0 + /// ITATBCTR2 + pub const ITATBCTR2 = @intToPtr(*volatile Mmio(32, packed struct { + ATREADY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0xef0); + + /// address: 0xe0040ef8 + /// ITATBCTR0 + pub const ITATBCTR0 = @intToPtr(*volatile Mmio(32, packed struct { + ATREADY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0xef8); + + /// address: 0xe0040efc + /// Integration ITM Data + pub const FIFO1 = @intToPtr(*volatile Mmio(32, packed struct { + ITM0: u8, + ITM1: u8, + ITM2: u8, + ETM_bytecount: u2, + ETM_ATVALID: u1, + ITM_bytecount: u2, + ITM_ATVALID: u1, + padding0: u1, + padding1: u1, + }), base_address + 0xefc); + + /// address: 0xe0040f00 + /// Integration Mode Control + pub const ITCTRL = @intToPtr(*volatile Mmio(32, packed struct { + Mode: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0xf00); + + /// address: 0xe0040fa0 + /// Claim tag set + pub const CLAIMSET = @intToPtr(*volatile u32, base_address + 0xfa0); + + /// address: 0xe0040fa4 + /// Claim tag clear + pub const CLAIMCLR = @intToPtr(*volatile u32, base_address + 0xfa4); + + /// address: 0xe0040fc8 + /// TPIU_DEVID + pub const DEVID = @intToPtr(*volatile Mmio(32, packed struct { + NrTraceInput: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + AsynClkIn: u1, + MinBufSz: u3, + PTINVALID: u1, + MANCVALID: u1, + NRZVALID: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0xfc8); + + /// address: 0xe0040fcc + /// TPIU_DEVTYPE + pub const DEVTYPE = @intToPtr(*volatile Mmio(32, packed struct { + SubType: u4, + MajorType: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xfcc); + }; +}; + +const std = @import("std"); + +pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) { + return @intToPtr(*volatile Mmio(size, PackedT), addr); +} + +pub fn Mmio(comptime size: u8, comptime PackedT: type) type { + if ((size % 8) != 0) + @compileError("size must be divisible by 8!"); + + if (!std.math.isPowerOfTwo(size / 8)) + @compileError("size must encode a power of two number of bytes!"); + + const IntT = std.meta.Int(.unsigned, size); + + if (@sizeOf(PackedT) != (size / 8)) + @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) })); + + return extern struct { + const Self = @This(); + + raw: IntT, + + pub const underlying_type = PackedT; + + pub inline fn read(addr: *volatile Self) PackedT { + return @bitCast(PackedT, addr.raw); + } + + pub inline fn write(addr: *volatile Self, val: PackedT) void { + // This is a workaround for a compiler bug related to miscompilation + // If the tmp var is not used, result location will fuck things up + var tmp = @bitCast(IntT, val); + addr.raw = tmp; + } + + pub inline fn modify(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, field.name) = @field(fields, field.name); + } + write(addr, val); + } + + pub inline fn toggle(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?)); + } + write(addr, val); + } + }; +} + +pub fn MmioInt(comptime size: u8, comptime T: type) type { + return extern struct { + const Self = @This(); + + raw: std.meta.Int(.unsigned, size), + + pub inline fn read(addr: *volatile Self) T { + return @truncate(T, addr.raw); + } + + pub inline fn modify(addr: *volatile Self, val: T) void { + const Int = std.meta.Int(.unsigned, size); + const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1); + + var tmp = addr.raw; + addr.raw = (tmp & mask) | val; + } + }; +} + +pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) { + return @intToPtr(*volatile MmioInt(size, T), addr); +} + +pub const InterruptVector = extern union { + C: fn () callconv(.C) void, + Naked: fn () callconv(.Naked) void, + // Interrupt is not supported on arm +}; + +const unhandled = InterruptVector{ + .C = struct { + fn tmp() callconv(.C) noreturn { + @panic("unhandled interrupt"); + } + }.tmp, +};