diff --git a/tools/regz/src/Database.zig b/tools/regz/src/Database.zig index b18d60f..1771cd2 100644 --- a/tools/regz/src/Database.zig +++ b/tools/regz/src/Database.zig @@ -642,7 +642,6 @@ fn writeDescription( allocator: Allocator, writer: anytype, description: []const u8, - indent: usize, ) !void { const max_line_width = 80; @@ -656,13 +655,11 @@ fn writeDescription( while (it.next()) |token| { if (line.items.len + token.len > max_line_width) { if (line.items.len > 0) { - try writer.writeByteNTimes(' ', indent * 4); try writer.print("///{s}\n", .{line.items}); line.clearRetainingCapacity(); try line.append(' '); try line.appendSlice(token); } else { - try writer.writeByteNTimes(' ', indent * 4); try writer.print("/// {s}\n", .{token}); } } else { @@ -672,22 +669,25 @@ fn writeDescription( } if (line.items.len > 0) { - try writer.writeByteNTimes(' ', indent * 4); try writer.print("///{s}\n", .{line.items}); } } } -pub fn toZig(self: *Self, writer: anytype) !void { +pub fn toZig(self: *Self, out_writer: anytype) !void { if (self.device == null) { std.log.err("failed to find device info", .{}); return error.Explained; } + var fifo = std.fifo.LinearFifo(u8, .Dynamic).init(self.allocator); + defer fifo.deinit(); + + const writer = fifo.writer(); + try writer.print( \\// this file was generated by regz: https://github.com/ZigEmbeddedGroup/regz \\// commit: {s} - \\ , .{build_options.commit}); try writer.writeAll("//\n"); if (self.device.?.vendor) |vendor_name| @@ -759,7 +759,7 @@ pub fn toZig(self: *Self, writer: anytype) !void { } if (interrupt.description) |description| if (!useless_descriptions.has(description)) - try writeDescription(self.arena.child_allocator, writer, description, 1); + try writeDescription(self.arena.child_allocator, writer, description); try writer.print(" {s}: InterruptVector = unhandled,\n", .{std.zig.fmtId(interrupt.name)}); expected += 1; @@ -792,7 +792,7 @@ pub fn toZig(self: *Self, writer: anytype) !void { if (registers.len != 0 or has_clusters) { if (peripheral.description) |description| if (!useless_descriptions.has(description)) { try writer.writeByte('\n'); - try writeDescription(self.arena.child_allocator, writer, description, 1); + try writeDescription(self.arena.child_allocator, writer, description); }; try writer.print(" pub const {s} = struct {{\n", .{std.zig.fmtId(peripheral.name)}); @@ -804,13 +804,13 @@ pub fn toZig(self: *Self, writer: anytype) !void { for (registers) |_, range_offset| { const reg_idx = @intCast(u32, reg_range.begin + range_offset); - try self.genZigRegister(writer, peripheral.base_addr, reg_idx, 2, .namespaced); + try self.genZigRegister(writer, peripheral.base_addr, reg_idx, .namespaced); } if (has_clusters) { for (self.clusters_in_peripherals.items) |cip| { if (cip.peripheral_idx == peripheral_idx) { - try self.genZigCluster(writer, peripheral.base_addr, cip.cluster_idx, 2, .namespaced); + try self.genZigCluster(writer, peripheral.base_addr, cip.cluster_idx, .namespaced); } } @@ -828,6 +828,17 @@ pub fn toZig(self: *Self, writer: anytype) !void { } try writer.writeAll("\n" ++ @embedFile("mmio.zig")); + + // write zero to fifo so that it's null terminated + try writer.writeByte(0); + const text = fifo.readableSlice(0); + var ast = try std.zig.parse(self.allocator, @bitCast([:0]const u8, text[0 .. text.len - 1])); + defer ast.deinit(self.allocator); + + const formatted_text = try ast.render(self.allocator); + defer self.allocator.free(formatted_text); + + try out_writer.writeAll(formatted_text); } fn genZigCluster( @@ -835,7 +846,6 @@ fn genZigCluster( writer: anytype, base_addr: ?usize, cluster_idx: u32, - indent: usize, nesting: Nesting, ) !void { const cluster = db.clusters.items[cluster_idx]; @@ -854,19 +864,18 @@ fn genZigCluster( try writer.writeByte('\n'); if (cluster.description) |description| if (!useless_descriptions.has(description)) - try writeDescription(db.arena.child_allocator, writer, description, indent); + try writeDescription(db.arena.child_allocator, writer, description); if (dimension_opt) |dimension| { const name = try std.mem.replaceOwned(u8, db.arena.allocator(), cluster.name, "[%s]", ""); - try writer.writeByteNTimes(' ', indent * 4); try writer.print("pub const {s} = @ptrCast(*volatile [{}]packed struct {{", .{ name, dimension.dim }); // TODO: check address offset of register wrt the cluster var bits: usize = 0; for (registers) |register, offset| { const reg_idx = @intCast(u32, range.begin + offset); - try db.genZigRegister(writer, base_addr, reg_idx, indent + 1, .contained); + try db.genZigRegister(writer, base_addr, reg_idx, .contained); bits += register.size; } @@ -881,21 +890,17 @@ fn genZigCluster( const num_padding_words = (dimension.increment - bytes) / bytes_per_word; var i: usize = 0; while (i < num_padding_words) : (i += 1) { - try writer.writeByteNTimes(' ', (indent + 1) * 4); try writer.print("padding{}: u{},\n", .{ i, db.device.?.width }); } - try writer.writeByteNTimes(' ', indent * 4); try writer.print("}}, base_address + 0x{x});\n", .{cluster.addr_offset}); } else { - try writer.writeByteNTimes(' ', indent * 4); try writer.print("pub const {s} = struct {{\n", .{std.zig.fmtId(cluster.name)}); for (registers) |_, offset| { const reg_idx = @intCast(u32, range.begin + offset); - try db.genZigRegister(writer, base_addr, reg_idx, indent + 1, .namespaced); + try db.genZigRegister(writer, base_addr, reg_idx, .namespaced); } - try writer.writeByteNTimes(' ', indent * 4); try writer.writeAll("};\n"); } }, @@ -912,7 +917,6 @@ fn genZigSingleRegister( addr_offset: usize, field_range_opt: ?Range, array_prefix: []const u8, - indent: usize, nesting: Nesting, ) !void { if (field_range_opt) |field_range| { @@ -923,7 +927,6 @@ fn genZigSingleRegister( if (fields[0].width > width) return error.BadWidth; - try writer.writeByteNTimes(' ', indent * 4); if (fields[0].width == width) // TODO: oof please refactor this switch (nesting) { @@ -972,7 +975,6 @@ fn genZigSingleRegister( }), } } else { - try writer.writeByteNTimes(' ', indent * 4); switch (nesting) { .namespaced => try writer.print("pub const {s} = @intToPtr(*volatile {s}Mmio({}, packed struct {{\n", .{ std.zig.fmtId(name), @@ -991,10 +993,8 @@ fn genZigSingleRegister( width, fields, field_range.begin, - indent + 1, ); - try writer.writeByteNTimes(' ', indent * 4); switch (nesting) { .namespaced => if (has_base_addr) try writer.print("}}), base_address + 0x{x});\n", .{addr_offset}) @@ -1004,7 +1004,6 @@ fn genZigSingleRegister( } } } else { - try writer.writeByteNTimes(' ', indent * 4); switch (nesting) { .namespaced => if (has_base_addr) try writer.print("pub const {s} = @intToPtr(*volatile {s}u{}, base_address + 0x{x});\n", .{ @@ -1035,7 +1034,6 @@ fn genZigFields( reg_width: usize, fields: []Field, first_field_idx: u32, - indent: usize, ) !void { var expected_bit: usize = 0; var reserved_num: usize = 0; @@ -1049,7 +1047,6 @@ fn genZigFields( if (dimension.index) |dim_index| switch (dim_index) { .list => |list| for (list.items) |entry| { const name = try std.mem.replaceOwned(u8, self.arena.allocator(), field.name, "%s", entry); - try writer.writeByteNTimes(' ', indent * 4); try writer.print("{s}: u{},\n", .{ std.zig.fmtId(name), field.width }); expected_bit += field.width; }, @@ -1062,7 +1059,6 @@ fn genZigFields( while (i < dimension.dim) : (i += 1) { const num_str = try std.fmt.allocPrint(self.arena.allocator(), "{}", .{i}); const name = try std.mem.replaceOwned(u8, self.arena.allocator(), field.name, "%s", num_str); - try writer.writeByteNTimes(' ', indent * 4); try writer.print("{s}: u{},\n", .{ std.zig.fmtId(name), field.width }); expected_bit += field.width; } @@ -1086,7 +1082,6 @@ fn genZigFields( expected_bit += 1; reserved_num += 1; }) { - try writer.writeByteNTimes(' ', indent * 4); try writer.print("reserved{}: u1,\n", .{reserved_num}); } @@ -1110,15 +1105,13 @@ fn genZigFields( // TODO: default values? if (field.description) |description| if (!useless_descriptions.has(description)) { - try writeDescription(self.arena.child_allocator, writer, description, indent); + try writeDescription(self.arena.child_allocator, writer, description); if (enumerations_opt != null) { - try writer.writeByteNTimes(' ', indent * 4); try writer.writeAll("///\n"); } }; if (enumerations_opt) |enumerations| for (enumerations) |enumeration| { - try writer.writeByteNTimes(' ', indent * 4); try writer.print("/// 0x{x}: ", .{enumeration.value}); if (enumeration.description) |description| try writer.print("{s}\n", .{description}) @@ -1126,7 +1119,6 @@ fn genZigFields( try writer.writeAll("undocumented\n"); }; - try writer.writeByteNTimes(' ', indent * 4); try writer.print("{s}: u{},\n", .{ std.zig.fmtId(field.name), field.width }); expected_bit += field.width; @@ -1138,7 +1130,6 @@ fn genZigFields( expected_bit += 1; padding_num += 1; }) { - try writer.writeByteNTimes(' ', indent * 4); try writer.print("padding{}: u1,\n", .{padding_num}); } } @@ -1148,7 +1139,6 @@ fn genZigRegister( writer: anytype, base_addr: ?usize, reg_idx: u32, - indent: usize, nesting: Nesting, ) !void { const register = self.registers.items[reg_idx]; @@ -1179,12 +1169,11 @@ fn genZigRegister( try writer.writeByte('\n'); if (nesting == .namespaced) { const addr = if (base_addr) |base| base + addr_offset else addr_offset; - try writer.writeByteNTimes(' ', indent * 4); try writer.print("/// address: 0x{x}\n", .{addr}); } if (register.description) |description| - try writeDescription(self.arena.child_allocator, writer, description, indent); + try writeDescription(self.arena.child_allocator, writer, description); try self.genZigSingleRegister( writer, @@ -1194,7 +1183,6 @@ fn genZigRegister( addr_offset, field_range, "", - indent, nesting, ); } @@ -1215,12 +1203,11 @@ fn genZigRegister( try writer.writeByte('\n'); if (nesting == .namespaced) { const addr = if (base_addr) |base| base + addr_offset else addr_offset; - try writer.writeByteNTimes(' ', indent * 4); try writer.print("/// address: 0x{x}\n", .{addr}); } if (register.description) |description| - try writeDescription(self.arena.child_allocator, writer, description, indent); + try writeDescription(self.arena.child_allocator, writer, description); try self.genZigSingleRegister( writer, @@ -1230,7 +1217,6 @@ fn genZigRegister( addr_offset, field_range, "", - indent, nesting, ); } @@ -1272,12 +1258,11 @@ fn genZigRegister( try writer.writeByte('\n'); if (nesting == .namespaced) { const addr = if (base_addr) |base| base + register.addr_offset else register.addr_offset; - try writer.writeByteNTimes(' ', indent * 4); try writer.print("/// address: 0x{x}\n", .{addr}); } if (register.description) |description| - try writeDescription(self.arena.child_allocator, writer, description, indent); + try writeDescription(self.arena.child_allocator, writer, description); try self.genZigSingleRegister( writer, @@ -1287,7 +1272,6 @@ fn genZigRegister( register.addr_offset, field_range, array_prefix, - indent, nesting, );