From c30f71f33ff7929c634d571c74887fb9ba30b157 Mon Sep 17 00:00:00 2001 From: biom4st3r <37042156+biom4st3r@users.noreply.github.com> Date: Wed, 10 Jul 2024 02:01:41 -0500 Subject: [PATCH] Basic support for ATmega32u4 (#195) Co-authored-by: Vesim --- bsp/microchip/avr/build.zig | 31 + .../avr/src/boards/itsybitsy_32u4.zig | 35 + bsp/microchip/avr/src/chips/ATmega32U4.json | 4145 +++++++++++++++++ bsp/microchip/avr/src/hals/ATmega32U4.zig | 200 + 4 files changed, 4411 insertions(+) create mode 100644 bsp/microchip/avr/src/boards/itsybitsy_32u4.zig create mode 100644 bsp/microchip/avr/src/chips/ATmega32U4.json create mode 100644 bsp/microchip/avr/src/hals/ATmega32U4.zig diff --git a/bsp/microchip/avr/build.zig b/bsp/microchip/avr/build.zig index 09a96ec..c87415c 100644 --- a/bsp/microchip/avr/build.zig +++ b/bsp/microchip/avr/build.zig @@ -11,6 +11,9 @@ fn path(comptime suffix: []const u8) Build.LazyPath { const hal = .{ .root_source_file = path("/src/hals/ATmega328P.zig"), }; +const hal32u4 = .{ + .root_source_file = path("/src/hals/ATmega32U4.zig"), +}; pub const chips = struct { pub const atmega328p = MicroZig.Target{ @@ -29,6 +32,22 @@ pub const chips = struct { }, .hal = hal, }; + pub const atmega32u4 = MicroZig.Target{ + .preferred_format = .hex, + .chip = .{ + .name = "ATmega32U4", + .url = "https://www.microchip.com/en-us/product/ATmega32U4", + .cpu = MicroZig.cpus.avr5, + .register_definition = .{ + .json = path("/src/chips/ATmega32U4.json"), + }, + .memory_regions = &.{ + .{ .offset = 0x000000, .length = 32 * 1024, .kind = .flash }, + .{ .offset = 0x800100, .length = 2560, .kind = .ram }, + }, + }, + .hal = hal32u4, + }; }; pub const boards = struct { @@ -55,6 +74,18 @@ pub const boards = struct { }, }; }; + pub const adafruit = struct { + pub const itsybitsy_32u4 = MicroZig.Target{ + .preferred_format = .hex, + .chip = chips.atmega32u4.chip, + .hal = hal32u4, + .board = .{ + .name = "Adafruit ItsyBitsy 32u4", + .url = "https://cdn-learn.adafruit.com/downloads/pdf/introducting-itsy-bitsy-32u4.pdf", + .root_source_file = path("/src/boards/itsybitsy_32u4.zig"), + }, + }; + }; }; pub fn build(b: *Build) void { diff --git a/bsp/microchip/avr/src/boards/itsybitsy_32u4.zig b/bsp/microchip/avr/src/boards/itsybitsy_32u4.zig new file mode 100644 index 0000000..1b6945d --- /dev/null +++ b/bsp/microchip/avr/src/boards/itsybitsy_32u4.zig @@ -0,0 +1,35 @@ +pub const chip = @import("chip"); + +pub const clock_frequencies = .{ + .cpu = 16_000_000, +}; + +pub const pin_map = .{ + .A0 = "PF7", + .A1 = "PF6", + .A2 = "PF5", + .A3 = "PF4", + .A4 = "PF1", + .A5 = "PF0", + + .SCK = "PB1", // PCINT1 + .MOSI = "PB2", // PCINT2 + .MISO = "PB3", // PCINT3 + + .D13 = "PC7", // Led + .D12 = "PD6", + .D11 = "PB7", + .D10 = "PB6", + .D9 = "PB5", + .D7 = "PE6", + .D5 = "PC6", + + .SCL = "PD0", + .SDA = "PD1", + .D1 = "PD3", // TX + .D0 = "PD2", // RX + + .D4 = "PD4", + .D6 = "PD7", + .D8 = "PB4", +}; diff --git a/bsp/microchip/avr/src/chips/ATmega32U4.json b/bsp/microchip/avr/src/chips/ATmega32U4.json new file mode 100644 index 0000000..31f0dae --- /dev/null +++ b/bsp/microchip/avr/src/chips/ATmega32U4.json @@ -0,0 +1,4145 @@ +{ + "version": "0.1.0", + "types": { + "peripherals": { + "FUSE": { + "description": "Fuses", + "children": { + "registers": { + "EXTENDED": { + "offset": 2, + "size": 8, + "reset_value": 251, + "children": { + "fields": { + "BODLEVEL": { + "description": "Brown-out Detector trigger level", + "offset": 0, + "size": 3, + "enum": "types.peripherals.FUSE.children.enums.ENUM_BODLEVEL" + }, + "HWBE": { + "description": "Hardware Boot Enable", + "offset": 3, + "size": 1 + } + } + } + }, + "HIGH": { + "offset": 1, + "size": 8, + "reset_value": 153, + "children": { + "fields": { + "OCDEN": { + "description": "On-Chip Debug Enabled", + "offset": 7, + "size": 1 + }, + "JTAGEN": { + "description": "JTAG Interface Enabled", + "offset": 6, + "size": 1 + }, + "SPIEN": { + "description": "Serial program downloading (SPI) enabled", + "offset": 5, + "size": 1 + }, + "WDTON": { + "description": "Watchdog timer always on", + "offset": 4, + "size": 1 + }, + "EESAVE": { + "description": "Preserve EEPROM through the Chip Erase cycle", + "offset": 3, + "size": 1 + }, + "BOOTSZ": { + "description": "Select Boot Size", + "offset": 1, + "size": 2, + "enum": "types.peripherals.FUSE.children.enums.ENUM_BOOTSZ" + }, + "BOOTRST": { + "description": "Boot Reset vector Enabled", + "offset": 0, + "size": 1 + } + } + } + }, + "LOW": { + "offset": 0, + "size": 8, + "reset_value": 82, + "children": { + "fields": { + "CKDIV8": { + "description": "Divide clock by 8 internally", + "offset": 7, + "size": 1 + }, + "CKOUT": { + "description": "Clock output on PORTC7", + "offset": 6, + "size": 1 + }, + "SUT_CKSEL": { + "description": "Select Clock Source", + "offset": 0, + "size": 6, + "enum": "types.peripherals.FUSE.children.enums.ENUM_SUT_CKSEL" + } + } + } + } + }, + "enums": { + "ENUM_SUT_CKSEL": { + "size": 6, + "children": { + "enum_fields": { + "EXTCLK_6CK_0MS": { + "description": "Ext. Clock; Start-up time: 6 CK + 0 ms", + "value": 0 + }, + "EXTCLK_6CK_4MS1": { + "description": "Ext. Clock; Start-up time: 6 CK + 4.1 ms", + "value": 16 + }, + "EXTCLK_6CK_65MS": { + "description": "Ext. Clock; Start-up time: 6 CK + 65 ms", + "value": 32 + }, + "INTRCOSC_6CK_0MS": { + "description": "Int. RC Osc.; Start-up time: 6 CK + 0 ms", + "value": 2 + }, + "INTRCOSC_6CK_4MS1": { + "description": "Int. RC Osc.; Start-up time: 6 CK + 4.1 ms", + "value": 18 + }, + "INTRCOSC_6CK_65MS": { + "description": "Int. RC Osc.; Start-up time: 6 CK + 65 ms", + "value": 34 + }, + "EXTLOFXTAL_32KCK_0MS_INTCAP": { + "description": "Ext. Low-Freq. Crystal; Start-up time: 32K CK + 0 ms; Int. Cap.", + "value": 7 + }, + "EXTLOFXTAL_32KCK_4MS1_INTCAP": { + "description": "Ext. Low-Freq. Crystal; Start-up time: 32K CK + 4.1 ms; Int. Cap.", + "value": 23 + }, + "EXTLOFXTAL_32KCK_65MS_INTCAP": { + "description": "Ext. Low-Freq. Crystal; Start-up time: 32K CK + 65 ms; Int. Cap.", + "value": 39 + }, + "EXTLOFXTAL_1KCK_0MS_INTCAP": { + "description": "Ext. Low-Freq. Crystal; Start-up time: 1K CK + 0 ms; Int. Cap.", + "value": 6 + }, + "EXTLOFXTAL_1KCK_4MS1_INTCAP": { + "description": "Ext. Low-Freq. Crystal; Start-up time: 1K CK + 4.1 ms; Int. Cap.", + "value": 22 + }, + "EXTLOFXTAL_1KCK_65MS_INTCAP": { + "description": "Ext. Low-Freq. Crystal; Start-up time: 1K CK + 65 ms; Int. Cap.", + "value": 38 + }, + "EXTLOFXTAL_32KCK_0MS": { + "description": "Ext. Low-Freq. Crystal; Start-up time: 32K CK + 0 ms", + "value": 5 + }, + "EXTLOFXTAL_32KCK_4MS1": { + "description": "Ext. Low-Freq. Crystal; Start-up time: 32K CK + 4.1 ms", + "value": 21 + }, + "EXTLOFXTAL_32KCK_65MS": { + "description": "Ext. Low-Freq. Crystal; Start-up time: 32K CK + 65 ms", + "value": 37 + }, + "EXTLOFXTAL_1KCK_0MS": { + "description": "Ext. Low-Freq. Crystal; Start-up time: 1K CK + 0 ms", + "value": 4 + }, + "EXTLOFXTAL_1KCK_4MS1": { + "description": "Ext. Low-Freq. Crystal; Start-up time: 1K CK + 4.1 ms", + "value": 20 + }, + "EXTLOFXTAL_1KCK_65MS": { + "description": "Ext. Low-Freq. Crystal; Start-up time: 1K CK + 65 ms", + "value": 36 + }, + "EXTXOSC_0MHZ4_0MHZ9_258CK_4MS1": { + "description": "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 258 CK + 4.1 ms", + "value": 8 + }, + "EXTXOSC_0MHZ4_0MHZ9_258CK_65MS": { + "description": "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 258 CK + 65 ms", + "value": 24 + }, + "EXTXOSC_0MHZ4_0MHZ9_1KCK_0MS": { + "description": "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 1K CK + 0 ms", + "value": 40 + }, + "EXTXOSC_0MHZ4_0MHZ9_1KCK_4MS1": { + "description": "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 1K CK + 4.1 ms", + "value": 56 + }, + "EXTXOSC_0MHZ4_0MHZ9_1KCK_65MS": { + "description": "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 1K CK + 65 ms", + "value": 9 + }, + "EXTXOSC_0MHZ4_0MHZ9_16KCK_0MS": { + "description": "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 16K CK + 0 ms", + "value": 25 + }, + "EXTXOSC_0MHZ4_0MHZ9_16KCK_4MS1": { + "description": "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 16K CK + 4.1 ms", + "value": 41 + }, + "EXTXOSC_0MHZ4_0MHZ9_16KCK_65MS": { + "description": "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 16K CK + 65 ms", + "value": 57 + }, + "EXTXOSC_0MHZ9_3MHZ_258CK_4MS1": { + "description": "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 258 CK + 4.1 ms", + "value": 10 + }, + "EXTXOSC_0MHZ9_3MHZ_258CK_65MS": { + "description": "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 258 CK + 65 ms", + "value": 26 + }, + "EXTXOSC_0MHZ9_3MHZ_1KCK_0MS": { + "description": "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 1K CK + 0 ms", + "value": 42 + }, + "EXTXOSC_0MHZ9_3MHZ_1KCK_4MS1": { + "description": "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 1K CK + 4.1 ms", + "value": 58 + }, + "EXTXOSC_0MHZ9_3MHZ_1KCK_65MS": { + "description": "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 1K CK + 65 ms", + "value": 11 + }, + "EXTXOSC_0MHZ9_3MHZ_16KCK_0MS": { + "description": "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 16K CK + 0 ms", + "value": 27 + }, + "EXTXOSC_0MHZ9_3MHZ_16KCK_4MS1": { + "description": "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 16K CK + 4.1 ms", + "value": 43 + }, + "EXTXOSC_0MHZ9_3MHZ_16KCK_65MS": { + "description": "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 16K CK + 65 ms", + "value": 59 + }, + "EXTXOSC_3MHZ_8MHZ_258CK_4MS1": { + "description": "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 258 CK + 4.1 ms", + "value": 12 + }, + "EXTXOSC_3MHZ_8MHZ_258CK_65MS": { + "description": "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 258 CK + 65 ms", + "value": 28 + }, + "EXTXOSC_3MHZ_8MHZ_1KCK_0MS": { + "description": "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 1K CK + 0 ms", + "value": 44 + }, + "EXTXOSC_3MHZ_8MHZ_1KCK_4MS1": { + "description": "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 1K CK + 4.1 ms", + "value": 60 + }, + "EXTXOSC_3MHZ_8MHZ_1KCK_65MS": { + "description": "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 1K CK + 65 ms", + "value": 13 + }, + "EXTXOSC_3MHZ_8MHZ_16KCK_0MS": { + "description": "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 16K CK + 0 ms", + "value": 29 + }, + "EXTXOSC_3MHZ_8MHZ_16KCK_4MS1": { + "description": "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 16K CK + 4.1 ms", + "value": 45 + }, + "EXTXOSC_3MHZ_8MHZ_16KCK_65MS": { + "description": "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 16K CK + 65 ms", + "value": 61 + }, + "EXTXOSC_8MHZ_XX_258CK_4MS1": { + "description": "Ext. Crystal Osc. 8.0- MHz; Start-up time: 258 CK + 4.1 ms", + "value": 14 + }, + "EXTXOSC_8MHZ_XX_258CK_65MS": { + "description": "Ext. Crystal Osc. 8.0- MHz; Start-up time: 258 CK + 65 ms", + "value": 30 + }, + "EXTXOSC_8MHZ_XX_1KCK_0MS": { + "description": "Ext. Crystal Osc. 8.0- MHz; Start-up time: 1K CK + 0 ms", + "value": 46 + }, + "EXTXOSC_8MHZ_XX_1KCK_4MS1": { + "description": "Ext. Crystal Osc. 8.0- MHz; Start-up time: 1K CK + 4.1 ms", + "value": 62 + }, + "EXTXOSC_8MHZ_XX_1KCK_65MS": { + "description": "Ext. Crystal Osc. 8.0- MHz; Start-up time: 1K CK + 65 ms", + "value": 15 + }, + "EXTXOSC_8MHZ_XX_16KCK_0MS": { + "description": "Ext. Crystal Osc. 8.0- MHz; Start-up time: 16K CK + 0 ms", + "value": 31 + }, + "EXTXOSC_8MHZ_XX_16KCK_4MS1": { + "description": "Ext. Crystal Osc. 8.0- MHz; Start-up time: 16K CK + 4.1 ms", + "value": 47 + }, + "EXTXOSC_8MHZ_XX_16KCK_65MS": { + "description": "Ext. Crystal Osc. 8.0- MHz; Start-up time: 16K CK + 65 ms", + "value": 63 + } + } + } + }, + "ENUM_BOOTSZ": { + "size": 2, + "children": { + "enum_fields": { + "256W_3F00": { + "description": "Boot Flash size=256 words start address=$3F00", + "value": 3 + }, + "512W_3E00": { + "description": "Boot Flash size=512 words start address=$3E00", + "value": 2 + }, + "1024W_3C00": { + "description": "Boot Flash size=1024 words start address=$3C00", + "value": 1 + }, + "2048W_3800": { + "description": "Boot Flash size=2048 words start address=$3800", + "value": 0 + } + } + } + }, + "ENUM_BODLEVEL": { + "size": 3, + "children": { + "enum_fields": { + "DISABLED": { + "description": "Brown-out detection disabled; [BODLEVEL=111]", + "value": 7 + }, + "2V0": { + "description": "Brown-out detection at VCC=2.0 V", + "value": 6 + }, + "2V2": { + "description": "Brown-out detection at VCC=2.2 V", + "value": 5 + }, + "2V4": { + "description": "Brown-out detection at VCC=2.4 V", + "value": 4 + }, + "2V6": { + "description": "Brown-out detection at VCC=2.6 V", + "value": 3 + }, + "3V4": { + "description": "Brown-out detection at VCC=3.4 V", + "value": 2 + }, + "3V5": { + "description": "Brown-out detection at VCC=3.5 V", + "value": 1 + }, + "4V3": { + "description": "Brown-out detection at VCC=4.3 V", + "value": 0 + } + } + } + } + } + } + }, + "LOCKBIT": { + "description": "Lockbits", + "children": { + "registers": { + "LOCKBIT": { + "offset": 0, + "size": 8, + "reset_value": 255, + "children": { + "fields": { + "LB": { + "description": "Memory Lock", + "offset": 0, + "size": 2, + "enum": "types.peripherals.LOCKBIT.children.enums.ENUM_LB" + }, + "BLB0": { + "description": "Boot Loader Protection Mode", + "offset": 2, + "size": 2, + "enum": "types.peripherals.LOCKBIT.children.enums.ENUM_BLB" + }, + "BLB1": { + "description": "Boot Loader Protection Mode", + "offset": 4, + "size": 2, + "enum": "types.peripherals.LOCKBIT.children.enums.ENUM_BLB2" + } + } + } + } + }, + "enums": { + "ENUM_LB": { + "size": 2, + "children": { + "enum_fields": { + "PROG_VER_DISABLED": { + "description": "Further programming and verification disabled", + "value": 0 + }, + "PROG_DISABLED": { + "description": "Further programming disabled", + "value": 2 + }, + "NO_LOCK": { + "description": "No memory lock features enabled", + "value": 3 + } + } + } + }, + "ENUM_BLB": { + "size": 2, + "children": { + "enum_fields": { + "LPM_SPM_DISABLE": { + "description": "LPM and SPM prohibited in Application Section", + "value": 0 + }, + "LPM_DISABLE": { + "description": "LPM prohibited in Application Section", + "value": 1 + }, + "SPM_DISABLE": { + "description": "SPM prohibited in Application Section", + "value": 2 + }, + "NO_LOCK": { + "description": "No lock on SPM and LPM in Application Section", + "value": 3 + } + } + } + }, + "ENUM_BLB2": { + "size": 2, + "children": { + "enum_fields": { + "LPM_SPM_DISABLE": { + "description": "LPM and SPM prohibited in Boot Section", + "value": 0 + }, + "LPM_DISABLE": { + "description": "LPM prohibited in Boot Section", + "value": 1 + }, + "SPM_DISABLE": { + "description": "SPM prohibited in Boot Section", + "value": 2 + }, + "NO_LOCK": { + "description": "No lock on SPM and LPM in Boot Section", + "value": 3 + } + } + } + } + } + } + }, + "WDT": { + "description": "Watchdog Timer", + "children": { + "registers": { + "WDTCSR": { + "description": "Watchdog Timer Control Register", + "offset": 0, + "size": 8, + "children": { + "fields": { + "WDIF": { + "description": "Watchdog Timeout Interrupt Flag", + "offset": 7, + "size": 1 + }, + "WDIE": { + "description": "Watchdog Timeout Interrupt Enable", + "offset": 6, + "size": 1 + }, + "WDP_bit0": { + "description": "Watchdog Timer Prescaler Bits", + "offset": 0, + "size": 1 + }, + "WDP_bit1": { + "description": "Watchdog Timer Prescaler Bits", + "offset": 1, + "size": 1 + }, + "WDP_bit2": { + "description": "Watchdog Timer Prescaler Bits", + "offset": 2, + "size": 1 + }, + "WDP_bit3": { + "description": "Watchdog Timer Prescaler Bits", + "offset": 5, + "size": 1 + }, + "WDCE": { + "description": "Watchdog Change Enable", + "offset": 4, + "size": 1 + }, + "WDE": { + "description": "Watch Dog Enable", + "offset": 3, + "size": 1 + } + } + } + } + }, + "enums": { + "WDOG_TIMER_PRESCALE_4BITS": { + "size": 4, + "children": { + "enum_fields": { + "VAL_0x00": { + "description": "Oscillator Cycles 2K", + "value": 0 + }, + "VAL_0x01": { + "description": "Oscillator Cycles 4K", + "value": 1 + }, + "VAL_0x02": { + "description": "Oscillator Cycles 8K", + "value": 2 + }, + "VAL_0x03": { + "description": "Oscillator Cycles 16K", + "value": 3 + }, + "VAL_0x04": { + "description": "Oscillator Cycles 32K", + "value": 4 + }, + "VAL_0x05": { + "description": "Oscillator Cycles 64K", + "value": 5 + }, + "VAL_0x06": { + "description": "Oscillator Cycles 128K", + "value": 6 + }, + "VAL_0x07": { + "description": "Oscillator Cycles 256K", + "value": 7 + }, + "VAL_0x08": { + "description": "Oscillator Cycles 512K", + "value": 8 + }, + "VAL_0x09": { + "description": "Oscillator Cycles 1024K", + "value": 9 + } + } + } + } + } + } + }, + "PORT": { + "description": "I/O Port", + "children": { + "register_groups": { + "PORTD": { + "description": "I/O Port", + "children": { + "registers": { + "PORTD": { + "description": "Port D Data Register", + "offset": 2, + "size": 8 + }, + "DDRD": { + "description": "Port D Data Direction Register", + "offset": 1, + "size": 8 + }, + "PIND": { + "description": "Port D Input Pins", + "offset": 0, + "size": 8 + } + } + } + }, + "PORTB": { + "description": "I/O Port", + "children": { + "registers": { + "PORTB": { + "description": "Port B Data Register", + "offset": 2, + "size": 8 + }, + "DDRB": { + "description": "Port B Data Direction Register", + "offset": 1, + "size": 8 + }, + "PINB": { + "description": "Port B Input Pins", + "offset": 0, + "size": 8 + } + } + } + }, + "PORTC": { + "description": "I/O Port", + "children": { + "registers": { + "PORTC": { + "description": "Port C Data Register", + "offset": 2, + "size": 8 + }, + "DDRC": { + "description": "Port C Data Direction Register", + "offset": 1, + "size": 8 + }, + "PINC": { + "description": "Port C Input Pins", + "offset": 0, + "size": 8 + } + } + } + }, + "PORTE": { + "description": "I/O Port", + "children": { + "registers": { + "PORTE": { + "description": "Data Register, Port E", + "offset": 2, + "size": 8 + }, + "DDRE": { + "description": "Data Direction Register, Port E", + "offset": 1, + "size": 8 + }, + "PINE": { + "description": "Input Pins, Port E", + "offset": 0, + "size": 8 + } + } + } + }, + "PORTF": { + "description": "I/O Port", + "children": { + "registers": { + "PORTF": { + "description": "Data Register, Port F", + "offset": 2, + "size": 8 + }, + "DDRF": { + "description": "Data Direction Register, Port F", + "offset": 1, + "size": 8 + }, + "PINF": { + "description": "Input Pins, Port F", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "SPI": { + "description": "Serial Peripheral Interface", + "children": { + "registers": { + "SPCR": { + "description": "SPI Control Register", + "offset": 0, + "size": 8, + "children": { + "fields": { + "SPIE": { + "description": "SPI Interrupt Enable", + "offset": 7, + "size": 1 + }, + "SPE": { + "description": "SPI Enable", + "offset": 6, + "size": 1 + }, + "DORD": { + "description": "Data Order", + "offset": 5, + "size": 1 + }, + "MSTR": { + "description": "Master/Slave Select", + "offset": 4, + "size": 1 + }, + "CPOL": { + "description": "Clock polarity", + "offset": 3, + "size": 1 + }, + "CPHA": { + "description": "Clock Phase", + "offset": 2, + "size": 1 + }, + "SPR": { + "description": "SPI Clock Rate Selects", + "offset": 0, + "size": 2, + "enum": "types.peripherals.SPI.children.enums.COMM_SCK_RATE_3BIT" + } + } + } + }, + "SPSR": { + "description": "SPI Status Register", + "offset": 1, + "size": 8, + "children": { + "fields": { + "SPIF": { + "description": "SPI Interrupt Flag", + "offset": 7, + "size": 1 + }, + "WCOL": { + "description": "Write Collision Flag", + "offset": 6, + "size": 1 + }, + "SPI2X": { + "description": "Double SPI Speed Bit", + "offset": 0, + "size": 1 + } + } + } + }, + "SPDR": { + "description": "SPI Data Register", + "offset": 2, + "size": 8 + } + }, + "enums": { + "COMM_SCK_RATE_3BIT": { + "size": 8, + "__manually_patched__":"added size: 8", + "children": { + "enum_fields": { + "VAL_0x00": { + "description": "fosc/4", + "value": 0 + }, + "VAL_0x01": { + "description": "fosc/16", + "value": 1 + }, + "VAL_0x02": { + "description": "fosc/64", + "value": 2 + }, + "VAL_0x03": { + "description": "fosc/128", + "value": 3 + }, + "VAL_0x04": { + "description": "fosc/2", + "value": 4 + }, + "VAL_0x05": { + "description": "fosc/8", + "value": 5 + }, + "VAL_0x06": { + "description": "fosc/32", + "value": 6 + }, + "VAL_0x07": { + "description": "fosc/64", + "value": 7 + } + } + } + } + } + } + }, + "USART": { + "description": "USART", + "children": { + "register_groups": { + "USART1": { + "description": "USART", + "children": { + "registers": { + "UDR1": { + "description": "USART I/O Data Register", + "offset": 6, + "size": 8 + }, + "UCSR1A": { + "description": "USART Control and Status Register A", + "offset": 0, + "size": 8, + "children": { + "fields": { + "RXC1": { + "description": "USART Receive Complete", + "offset": 7, + "size": 1 + }, + "TXC1": { + "description": "USART Transmitt Complete", + "offset": 6, + "size": 1 + }, + "UDRE1": { + "description": "USART Data Register Empty", + "offset": 5, + "size": 1 + }, + "FE1": { + "description": "Framing Error", + "offset": 4, + "size": 1 + }, + "DOR1": { + "description": "Data overRun", + "offset": 3, + "size": 1 + }, + "UPE1": { + "description": "Parity Error", + "offset": 2, + "size": 1 + }, + "U2X1": { + "description": "Double the USART transmission speed", + "offset": 1, + "size": 1 + }, + "MPCM1": { + "description": "Multi-processor Communication Mode", + "offset": 0, + "size": 1 + } + } + } + }, + "UCSR1B": { + "description": "USART Control and Status Register B", + "offset": 1, + "size": 8, + "children": { + "fields": { + "RXCIE1": { + "description": "RX Complete Interrupt Enable", + "offset": 7, + "size": 1 + }, + "TXCIE1": { + "description": "TX Complete Interrupt Enable", + "offset": 6, + "size": 1 + }, + "UDRIE1": { + "description": "USART Data register Empty Interrupt Enable", + "offset": 5, + "size": 1 + }, + "RXEN1": { + "description": "Receiver Enable", + "offset": 4, + "size": 1 + }, + "TXEN1": { + "description": "Transmitter Enable", + "offset": 3, + "size": 1 + }, + "UCSZ12": { + "description": "Character Size", + "offset": 2, + "size": 1 + }, + "RXB81": { + "description": "Receive Data Bit 8", + "offset": 1, + "size": 1 + }, + "TXB81": { + "description": "Transmit Data Bit 8", + "offset": 0, + "size": 1 + } + } + } + }, + "UCSR1C": { + "description": "USART Control and Status Register C", + "offset": 2, + "size": 8, + "children": { + "fields": { + "UMSEL1": { + "description": "USART Mode Select", + "offset": 6, + "size": 2, + "enum": "types.peripherals.USART.children.enums.COMM_USART_MODE_2BIT" + }, + "UPM1": { + "description": "Parity Mode Bits", + "offset": 4, + "size": 2, + "enum": "types.peripherals.USART.children.enums.COMM_UPM_PARITY_MODE" + }, + "USBS1": { + "description": "Stop Bit Select", + "offset": 3, + "size": 1, + "enum": "types.peripherals.USART.children.enums.COMM_STOP_BIT_SEL" + }, + "UCSZ1": { + "description": "Character Size", + "offset": 1, + "size": 2 + }, + "UCPOL1": { + "description": "Clock Polarity", + "offset": 0, + "size": 1 + } + } + } + }, + "UCSR1D": { + "description": "USART Control and Status Register D", + "offset": 3, + "size": 8, + "children": { + "fields": { + "CTSEN": { + "description": "CTS Enable", + "offset": 1, + "size": 1 + }, + "RTSEN": { + "description": "RTS Enable", + "offset": 0, + "size": 1 + } + } + } + }, + "UBRR1": { + "description": "USART Baud Rate Register Bytes", + "offset": 4, + "size": 16 + } + } + } + } + }, + "enums": { + "COMM_USART_MODE_2BIT": { + "size": 2, + "children": { + "enum_fields": { + "VAL_0x00": { + "description": "Asynchronous USART", + "value": 0 + }, + "VAL_0x01": { + "description": "Synchronous USART", + "value": 1 + }, + "VAL_0x03": { + "description": "Master SPI", + "value": 3 + } + } + } + }, + "COMM_UPM_PARITY_MODE": { + "size": 2, + "children": { + "enum_fields": { + "VAL_0x00": { + "description": "Disabled", + "value": 0 + }, + "VAL_0x01": { + "description": "Reserved", + "value": 1 + }, + "VAL_0x02": { + "description": "Enabled, Even Parity", + "value": 2 + }, + "VAL_0x03": { + "description": "Enabled, Odd Parity", + "value": 3 + } + } + } + }, + "COMM_STOP_BIT_SEL": { + "size": 1, + "children": { + "enum_fields": { + "VAL_0x00": { + "description": "1-bit", + "value": 0 + }, + "VAL_0x01": { + "description": "2-bit", + "value": 1 + } + } + } + } + } + } + }, + "BOOT_LOAD": { + "description": "Bootloader", + "children": { + "registers": { + "SPMCSR": { + "description": "Store Program Memory Control Register", + "offset": 0, + "size": 8, + "children": { + "fields": { + "SPMIE": { + "description": "SPM Interrupt Enable", + "offset": 7, + "size": 1 + }, + "RWWSB": { + "description": "Read While Write Section Busy", + "offset": 6, + "size": 1 + }, + "SIGRD": { + "description": "Signature Row Read", + "offset": 5, + "size": 1 + }, + "RWWSRE": { + "description": "Read While Write section read enable", + "offset": 4, + "size": 1 + }, + "BLBSET": { + "description": "Boot Lock Bit Set", + "offset": 3, + "size": 1 + }, + "PGWRT": { + "description": "Page Write", + "offset": 2, + "size": 1 + }, + "PGERS": { + "description": "Page Erase", + "offset": 1, + "size": 1 + }, + "SPMEN": { + "description": "Store Program Memory Enable", + "offset": 0, + "size": 1 + } + } + } + } + } + } + }, + "EEPROM": { + "description": "EEPROM", + "children": { + "registers": { + "EEAR": { + "description": "EEPROM Address Register Low Bytes", + "offset": 2, + "size": 16 + }, + "EEDR": { + "description": "EEPROM Data Register", + "offset": 1, + "size": 8 + }, + "EECR": { + "description": "EEPROM Control Register", + "offset": 0, + "size": 8, + "children": { + "fields": { + "EEPM": { + "description": "EEPROM Programming Mode Bits", + "offset": 4, + "size": 2, + "enum": "types.peripherals.EEPROM.children.enums.EEP_MODE" + }, + "EERIE": { + "description": "EEPROM Ready Interrupt Enable", + "offset": 3, + "size": 1 + }, + "EEMPE": { + "description": "EEPROM Master Write Enable", + "offset": 2, + "size": 1 + }, + "EEPE": { + "description": "EEPROM Write Enable", + "offset": 1, + "size": 1 + }, + "EERE": { + "description": "EEPROM Read Enable", + "offset": 0, + "size": 1 + } + } + } + } + }, + "enums": { + "EEP_MODE": { + "size": 2, + "children": { + "enum_fields": { + "VAL_0x00": { + "description": "Erase and Write in one operation", + "value": 0 + }, + "VAL_0x01": { + "description": "Erase Only", + "value": 1 + }, + "VAL_0x02": { + "description": "Write Only", + "value": 2 + } + } + } + } + } + } + }, + "TC8": { + "description": "Timer/Counter, 8-bit", + "children": { + "register_groups": { + "TC0": { + "description": "Timer/Counter, 8-bit", + "children": { + "registers": { + "OCR0B": { + "description": "Timer/Counter0 Output Compare Register", + "offset": 19, + "size": 8 + }, + "OCR0A": { + "description": "Timer/Counter0 Output Compare Register", + "offset": 18, + "size": 8 + }, + "TCNT0": { + "description": "Timer/Counter0", + "offset": 17, + "size": 8 + }, + "TCCR0B": { + "description": "Timer/Counter Control Register B", + "offset": 16, + "size": 8, + "children": { + "fields": { + "FOC0A": { + "description": "Force Output Compare A", + "offset": 7, + "size": 1 + }, + "FOC0B": { + "description": "Force Output Compare B", + "offset": 6, + "size": 1 + }, + "WGM02": { + "offset": 3, + "size": 1 + }, + "CS0": { + "description": "Clock Select", + "offset": 0, + "size": 3, + "enum": "types.peripherals.TC8.children.enums.CLK_SEL_3BIT_EXT" + } + } + } + }, + "TCCR0A": { + "description": "Timer/Counter Control Register A", + "offset": 15, + "size": 8, + "children": { + "fields": { + "COM0A": { + "description": "Compare Output Mode, Phase Correct PWM Mode", + "offset": 6, + "size": 2 + }, + "COM0B": { + "description": "Compare Output Mode, Fast PWm", + "offset": 4, + "size": 2 + }, + "WGM0": { + "description": "Waveform Generation Mode", + "offset": 0, + "size": 2 + } + } + } + }, + "TIMSK0": { + "description": "Timer/Counter0 Interrupt Mask Register", + "offset": 57, + "size": 8, + "children": { + "fields": { + "OCIE0B": { + "description": "Timer/Counter0 Output Compare Match B Interrupt Enable", + "offset": 2, + "size": 1 + }, + "OCIE0A": { + "description": "Timer/Counter0 Output Compare Match A Interrupt Enable", + "offset": 1, + "size": 1 + }, + "TOIE0": { + "description": "Timer/Counter0 Overflow Interrupt Enable", + "offset": 0, + "size": 1 + } + } + } + }, + "TIFR0": { + "description": "Timer/Counter0 Interrupt Flag register", + "offset": 0, + "size": 8, + "children": { + "fields": { + "OCF0B": { + "description": "Timer/Counter0 Output Compare Flag 0B", + "offset": 2, + "size": 1 + }, + "OCF0A": { + "description": "Timer/Counter0 Output Compare Flag 0A", + "offset": 1, + "size": 1 + }, + "TOV0": { + "description": "Timer/Counter0 Overflow Flag", + "offset": 0, + "size": 1 + } + } + } + }, + "GTCCR": { + "description": "General Timer/Counter Control Register", + "offset": 14, + "size": 8, + "children": { + "fields": { + "TSM": { + "description": "Timer/Counter Synchronization Mode", + "offset": 7, + "size": 1 + }, + "PSRSYNC": { + "description": "Prescaler Reset Timer/Counter1 and Timer/Counter0", + "offset": 0, + "size": 1 + } + } + } + } + } + } + } + }, + "enums": { + "CLK_SEL_3BIT_EXT": { + "size": 3, + "children": { + "enum_fields": { + "VAL_0x00": { + "description": "No Clock Source (Stopped)", + "value": 0 + }, + "VAL_0x01": { + "description": "Running, No Prescaling", + "value": 1 + }, + "VAL_0x02": { + "description": "Running, CLK/8", + "value": 2 + }, + "VAL_0x03": { + "description": "Running, CLK/64", + "value": 3 + }, + "VAL_0x04": { + "description": "Running, CLK/256", + "value": 4 + }, + "VAL_0x05": { + "description": "Running, CLK/1024", + "value": 5 + }, + "VAL_0x06": { + "description": "Running, ExtClk Tx Falling Edge", + "value": 6 + }, + "VAL_0x07": { + "description": "Running, ExtClk Tx Rising Edge", + "value": 7 + } + } + } + } + } + } + }, + "TC10": { + "description": "Timer/Counter, 10-bit", + "children": { + "register_groups": { + "TC4": { + "description": "Timer/Counter, 10-bit", + "children": { + "registers": { + "TCCR4A": { + "description": "Timer/Counter4 Control Register A", + "offset": 135, + "size": 8, + "children": { + "fields": { + "COM4A": { + "description": "Compare Output Mode 1A, bits", + "offset": 6, + "size": 2 + }, + "COM4B": { + "description": "Compare Output Mode 4B, bits", + "offset": 4, + "size": 2 + }, + "FOC4A": { + "description": "Force Output Compare Match 4A", + "offset": 3, + "size": 1 + }, + "FOC4B": { + "description": "Force Output Compare Match 4B", + "offset": 2, + "size": 1 + }, + "PWM4A": { + "offset": 1, + "size": 1 + }, + "PWM4B": { + "offset": 0, + "size": 1 + } + } + } + }, + "TCCR4B": { + "description": "Timer/Counter4 Control Register B", + "offset": 136, + "size": 8, + "children": { + "fields": { + "PWM4X": { + "description": "PWM Inversion Mode", + "offset": 7, + "size": 1 + }, + "PSR4": { + "description": "Prescaler Reset Timer/Counter 4", + "offset": 6, + "size": 1 + }, + "DTPS4": { + "description": "Dead Time Prescaler Bits", + "offset": 4, + "size": 2 + }, + "CS4": { + "description": "Clock Select Bits", + "offset": 0, + "size": 4 + } + } + } + }, + "TCCR4C": { + "description": "Timer/Counter 4 Control Register C", + "offset": 137, + "size": 8, + "children": { + "fields": { + "COM4A1S": { + "description": "Comparator A Output Mode", + "offset": 7, + "size": 1 + }, + "COM4A0S": { + "description": "Comparator A Output Mode", + "offset": 6, + "size": 1 + }, + "COM4B1S": { + "description": "Comparator B Output Mode", + "offset": 5, + "size": 1 + }, + "COM4B0S": { + "description": "Comparator B Output Mode", + "offset": 4, + "size": 1 + }, + "COM4D": { + "description": "Comparator D Output Mode", + "offset": 2, + "size": 2 + }, + "FOC4D": { + "description": "Force Output Compare Match 4D", + "offset": 1, + "size": 1 + }, + "PWM4D": { + "description": "Pulse Width Modulator D Enable", + "offset": 0, + "size": 1 + } + } + } + }, + "TCCR4D": { + "description": "Timer/Counter 4 Control Register D", + "offset": 138, + "size": 8, + "children": { + "fields": { + "FPIE4": { + "description": "Fault Protection Interrupt Enable", + "offset": 7, + "size": 1 + }, + "FPEN4": { + "description": "Fault Protection Mode Enable", + "offset": 6, + "size": 1 + }, + "FPNC4": { + "description": "Fault Protection Noise Canceler", + "offset": 5, + "size": 1 + }, + "FPES4": { + "description": "Fault Protection Edge Select", + "offset": 4, + "size": 1 + }, + "FPAC4": { + "description": "Fault Protection Analog Comparator Enable", + "offset": 3, + "size": 1 + }, + "FPF4": { + "description": "Fault Protection Interrupt Flag", + "offset": 2, + "size": 1 + }, + "WGM4": { + "description": "Waveform Generation Mode bits", + "offset": 0, + "size": 2 + } + } + } + }, + "TCCR4E": { + "description": "Timer/Counter 4 Control Register E", + "offset": 139, + "size": 8, + "children": { + "fields": { + "TLOCK4": { + "description": "Register Update Lock", + "offset": 7, + "size": 1 + }, + "ENHC4": { + "description": "Enhanced Compare/PWM Mode", + "offset": 6, + "size": 1 + }, + "OC4OE": { + "description": "Output Compare Override Enable bit", + "offset": 0, + "size": 6 + } + } + } + }, + "TCNT4": { + "description": "Timer/Counter4 Low Bytes", + "offset": 133, + "size": 8 + }, + "TC4H": { + "description": "Timer/Counter4", + "offset": 134, + "size": 8 + }, + "OCR4A": { + "description": "Timer/Counter4 Output Compare Register A", + "offset": 150, + "size": 8 + }, + "OCR4B": { + "description": "Timer/Counter4 Output Compare Register B", + "offset": 151, + "size": 8 + }, + "OCR4C": { + "description": "Timer/Counter4 Output Compare Register C", + "offset": 152, + "size": 8 + }, + "OCR4D": { + "description": "Timer/Counter4 Output Compare Register D", + "offset": 153, + "size": 8 + }, + "TIMSK4": { + "description": "Timer/Counter4 Interrupt Mask Register", + "offset": 57, + "size": 8, + "children": { + "fields": { + "OCIE4D": { + "description": "Timer/Counter4 Output Compare D Match Interrupt Enable", + "offset": 7, + "size": 1 + }, + "OCIE4A": { + "description": "Timer/Counter4 Output Compare A Match Interrupt Enable", + "offset": 6, + "size": 1 + }, + "OCIE4B": { + "description": "Timer/Counter4 Output Compare B Match Interrupt Enable", + "offset": 5, + "size": 1 + }, + "TOIE4": { + "description": "Timer/Counter4 Overflow Interrupt Enable", + "offset": 2, + "size": 1 + } + } + } + }, + "TIFR4": { + "description": "Timer/Counter4 Interrupt Flag register", + "offset": 0, + "size": 8, + "children": { + "fields": { + "OCF4D": { + "description": "Output Compare Flag 4D", + "offset": 7, + "size": 1 + }, + "OCF4A": { + "description": "Output Compare Flag 4A", + "offset": 6, + "size": 1 + }, + "OCF4B": { + "description": "Output Compare Flag 4B", + "offset": 5, + "size": 1 + }, + "TOV4": { + "description": "Timer/Counter4 Overflow Flag", + "offset": 2, + "size": 1 + } + } + } + }, + "DT4": { + "description": "Timer/Counter 4 Dead Time Value", + "offset": 155, + "size": 8, + "children": { + "fields": { + "DT4L": { + "description": "Timer/Counter 4 Dead Time Value Bits", + "offset": 0, + "size": 8 + } + } + } + } + } + } + } + } + } + }, + "TC16": { + "description": "Timer/Counter, 16-bit", + "children": { + "register_groups": { + "TC3": { + "description": "Timer/Counter, 16-bit", + "children": { + "registers": { + "TCCR3A": { + "description": "Timer/Counter3 Control Register A", + "offset": 88, + "size": 8, + "children": { + "fields": { + "COM3A": { + "description": "Compare Output Mode 1A, bits", + "offset": 6, + "size": 2 + }, + "COM3B": { + "description": "Compare Output Mode 3B, bits", + "offset": 4, + "size": 2 + }, + "COM3C": { + "description": "Compare Output Mode 3C, bits", + "offset": 2, + "size": 2 + }, + "WGM3": { + "description": "Waveform Generation Mode", + "offset": 0, + "size": 2 + } + } + } + }, + "TCCR3B": { + "description": "Timer/Counter3 Control Register B", + "offset": 89, + "size": 8, + "children": { + "fields": { + "ICNC3": { + "description": "Input Capture 3 Noise Canceler", + "offset": 7, + "size": 1 + }, + "ICES3": { + "description": "Input Capture 3 Edge Select", + "offset": 6, + "size": 1 + }, + "WGM3": { + "description": "Waveform Generation Mode", + "offset": 3, + "size": 2 + }, + "CS3": { + "description": "Prescaler source of Timer/Counter 3", + "offset": 0, + "size": 3, + "enum": "types.peripherals.TC8.children.enums.CLK_SEL_3BIT_EXT" + } + } + } + }, + "TCCR3C": { + "description": "Timer/Counter 3 Control Register C", + "offset": 90, + "size": 8, + "children": { + "fields": { + "FOC3A": { + "description": "Force Output Compare 3A", + "offset": 7, + "size": 1 + }, + "FOC3B": { + "description": "Force Output Compare 3B", + "offset": 6, + "size": 1 + }, + "FOC3C": { + "description": "Force Output Compare 3C", + "offset": 5, + "size": 1 + } + } + } + }, + "TCNT3": { + "description": "Timer/Counter3 Bytes", + "offset": 92, + "size": 16 + }, + "OCR3A": { + "description": "Timer/Counter3 Output Compare Register A Bytes", + "offset": 96, + "size": 16 + }, + "OCR3B": { + "description": "Timer/Counter3 Output Compare Register B Bytes", + "offset": 98, + "size": 16 + }, + "OCR3C": { + "description": "Timer/Counter3 Output Compare Register B Bytes", + "offset": 100, + "size": 16 + }, + "ICR3": { + "description": "Timer/Counter3 Input Capture Register Bytes", + "offset": 94, + "size": 16 + }, + "TIMSK3": { + "description": "Timer/Counter3 Interrupt Mask Register", + "offset": 57, + "size": 8, + "children": { + "fields": { + "ICIE3": { + "description": "Timer/Counter3 Input Capture Interrupt Enable", + "offset": 5, + "size": 1 + }, + "OCIE3C": { + "description": "Timer/Counter3 Output Compare C Match Interrupt Enable", + "offset": 3, + "size": 1 + }, + "OCIE3B": { + "description": "Timer/Counter3 Output Compare B Match Interrupt Enable", + "offset": 2, + "size": 1 + }, + "OCIE3A": { + "description": "Timer/Counter3 Output Compare A Match Interrupt Enable", + "offset": 1, + "size": 1 + }, + "TOIE3": { + "description": "Timer/Counter3 Overflow Interrupt Enable", + "offset": 0, + "size": 1 + } + } + } + }, + "TIFR3": { + "description": "Timer/Counter3 Interrupt Flag register", + "offset": 0, + "size": 8, + "children": { + "fields": { + "ICF3": { + "description": "Input Capture Flag 3", + "offset": 5, + "size": 1 + }, + "OCF3C": { + "description": "Output Compare Flag 3C", + "offset": 3, + "size": 1 + }, + "OCF3B": { + "description": "Output Compare Flag 3B", + "offset": 2, + "size": 1 + }, + "OCF3A": { + "description": "Output Compare Flag 3A", + "offset": 1, + "size": 1 + }, + "TOV3": { + "description": "Timer/Counter3 Overflow Flag", + "offset": 0, + "size": 1 + } + } + } + } + } + } + }, + "TC1": { + "description": "Timer/Counter, 16-bit", + "children": { + "registers": { + "TCCR1A": { + "description": "Timer/Counter1 Control Register A", + "offset": 74, + "size": 8, + "children": { + "fields": { + "COM1A": { + "description": "Compare Output Mode 1A, bits", + "offset": 6, + "size": 2 + }, + "COM1B": { + "description": "Compare Output Mode 1B, bits", + "offset": 4, + "size": 2 + }, + "COM1C": { + "description": "Compare Output Mode 1C, bits", + "offset": 2, + "size": 2 + }, + "WGM1": { + "description": "Waveform Generation Mode", + "offset": 0, + "size": 2 + } + } + } + }, + "TCCR1B": { + "description": "Timer/Counter1 Control Register B", + "offset": 75, + "size": 8, + "children": { + "fields": { + "ICNC1": { + "description": "Input Capture 1 Noise Canceler", + "offset": 7, + "size": 1 + }, + "ICES1": { + "description": "Input Capture 1 Edge Select", + "offset": 6, + "size": 1 + }, + "WGM1": { + "description": "Waveform Generation Mode", + "offset": 3, + "size": 2 + }, + "CS1": { + "description": "Prescaler source of Timer/Counter 1", + "offset": 0, + "size": 3, + "enum": "types.peripherals.TC8.children.enums.CLK_SEL_3BIT_EXT" + } + } + } + }, + "TCCR1C": { + "description": "Timer/Counter 1 Control Register C", + "offset": 76, + "size": 8, + "children": { + "fields": { + "FOC1A": { + "description": "Force Output Compare 1A", + "offset": 7, + "size": 1 + }, + "FOC1B": { + "description": "Force Output Compare 1B", + "offset": 6, + "size": 1 + }, + "FOC1C": { + "description": "Force Output Compare 1C", + "offset": 5, + "size": 1 + } + } + } + }, + "TCNT1": { + "description": "Timer/Counter1 Bytes", + "offset": 78, + "size": 16 + }, + "OCR1A": { + "description": "Timer/Counter1 Output Compare Register A Bytes", + "offset": 82, + "size": 16 + }, + "OCR1B": { + "description": "Timer/Counter1 Output Compare Register B Bytes", + "offset": 84, + "size": 16 + }, + "OCR1C": { + "description": "Timer/Counter1 Output Compare Register C Bytes", + "offset": 86, + "size": 16 + }, + "ICR1": { + "description": "Timer/Counter1 Input Capture Register Bytes", + "offset": 80, + "size": 16 + }, + "TIMSK1": { + "description": "Timer/Counter1 Interrupt Mask Register", + "offset": 57, + "size": 8, + "children": { + "fields": { + "ICIE1": { + "description": "Timer/Counter1 Input Capture Interrupt Enable", + "offset": 5, + "size": 1 + }, + "OCIE1C": { + "description": "Timer/Counter1 Output Compare C Match Interrupt Enable", + "offset": 3, + "size": 1 + }, + "OCIE1B": { + "description": "Timer/Counter1 Output Compare B Match Interrupt Enable", + "offset": 2, + "size": 1 + }, + "OCIE1A": { + "description": "Timer/Counter1 Output Compare A Match Interrupt Enable", + "offset": 1, + "size": 1 + }, + "TOIE1": { + "description": "Timer/Counter1 Overflow Interrupt Enable", + "offset": 0, + "size": 1 + } + } + } + }, + "TIFR1": { + "description": "Timer/Counter1 Interrupt Flag register", + "offset": 0, + "size": 8, + "children": { + "fields": { + "ICF1": { + "description": "Input Capture Flag 1", + "offset": 5, + "size": 1 + }, + "OCF1C": { + "description": "Output Compare Flag 1C", + "offset": 3, + "size": 1 + }, + "OCF1B": { + "description": "Output Compare Flag 1B", + "offset": 2, + "size": 1 + }, + "OCF1A": { + "description": "Output Compare Flag 1A", + "offset": 1, + "size": 1 + }, + "TOV1": { + "description": "Timer/Counter1 Overflow Flag", + "offset": 0, + "size": 1 + } + } + } + } + } + } + } + }, + "enums": { + "CLK_SEL_3BIT_EXT": { + "size": 3, + "children": { + "enum_fields": { + "VAL_0x00": { + "description": "No Clock Source (Stopped)", + "value": 0 + }, + "VAL_0x01": { + "description": "Running, No Prescaling", + "value": 1 + }, + "VAL_0x02": { + "description": "Running, CLK/8", + "value": 2 + }, + "VAL_0x03": { + "description": "Running, CLK/64", + "value": 3 + }, + "VAL_0x04": { + "description": "Running, CLK/256", + "value": 4 + }, + "VAL_0x05": { + "description": "Running, CLK/1024", + "value": 5 + }, + "VAL_0x06": { + "description": "Running, ExtClk Tx Falling Edge", + "value": 6 + }, + "VAL_0x07": { + "description": "Running, ExtClk Tx Rising Edge", + "value": 7 + } + } + } + } + } + } + }, + "JTAG": { + "description": "JTAG Interface", + "children": { + "registers": { + "OCDR": { + "description": "On-Chip Debug Related Register in I/O Memory", + "offset": 0, + "size": 8 + }, + "MCUCR": { + "description": "MCU Control Register", + "offset": 4, + "size": 8, + "children": { + "fields": { + "JTD": { + "description": "JTAG Interface Disable", + "offset": 7, + "size": 1 + } + } + } + }, + "MCUSR": { + "description": "MCU Status Register", + "offset": 3, + "size": 8, + "children": { + "fields": { + "JTRF": { + "description": "JTAG Reset Flag", + "offset": 4, + "size": 1 + } + } + } + } + } + } + }, + "EXINT": { + "description": "External Interrupts", + "children": { + "registers": { + "EICRA": { + "description": "External Interrupt Control Register A", + "offset": 46, + "size": 8, + "children": { + "fields": { + "ISC3": { + "description": "External Interrupt Sense Control Bit", + "offset": 6, + "size": 2, + "enum": "types.peripherals.EXINT.children.enums.INTERRUPT_SENSE_CONTROL" + }, + "ISC2": { + "description": "External Interrupt Sense Control Bit", + "offset": 4, + "size": 2, + "enum": "types.peripherals.EXINT.children.enums.INTERRUPT_SENSE_CONTROL" + }, + "ISC1": { + "description": "External Interrupt Sense Control Bit", + "offset": 2, + "size": 2, + "enum": "types.peripherals.EXINT.children.enums.INTERRUPT_SENSE_CONTROL" + }, + "ISC0": { + "description": "External Interrupt Sense Control Bit", + "offset": 0, + "size": 2, + "enum": "types.peripherals.EXINT.children.enums.INTERRUPT_SENSE_CONTROL" + } + } + } + }, + "EICRB": { + "description": "External Interrupt Control Register B", + "offset": 47, + "size": 8, + "children": { + "fields": { + "ISC7": { + "description": "External Interrupt 7-4 Sense Control Bit", + "offset": 6, + "size": 2, + "enum": "types.peripherals.EXINT.children.enums.INTERRUPT_SENSE_CONTROL" + }, + "ISC6": { + "description": "External Interrupt 7-4 Sense Control Bit", + "offset": 4, + "size": 2, + "enum": "types.peripherals.EXINT.children.enums.INTERRUPT_SENSE_CONTROL" + }, + "ISC5": { + "description": "External Interrupt 7-4 Sense Control Bit", + "offset": 2, + "size": 2, + "enum": "types.peripherals.EXINT.children.enums.INTERRUPT_SENSE_CONTROL" + }, + "ISC4": { + "description": "External Interrupt 7-4 Sense Control Bit", + "offset": 0, + "size": 2, + "enum": "types.peripherals.EXINT.children.enums.INTERRUPT_SENSE_CONTROL" + } + } + } + }, + "EIMSK": { + "description": "External Interrupt Mask Register", + "offset": 2, + "size": 8, + "children": { + "fields": { + "INT": { + "description": "External Interrupt Request 7 Enable", + "offset": 0, + "size": 8 + } + } + } + }, + "EIFR": { + "description": "External Interrupt Flag Register", + "offset": 1, + "size": 8, + "children": { + "fields": { + "INTF": { + "description": "External Interrupt Flags", + "offset": 0, + "size": 8 + } + } + } + }, + "PCMSK0": { + "description": "Pin Change Mask Register 0", + "offset": 48, + "size": 8 + }, + "PCIFR": { + "description": "Pin Change Interrupt Flag Register", + "offset": 0, + "size": 8, + "children": { + "fields": { + "PCIF0": { + "description": "Pin Change Interrupt Flag 0", + "offset": 0, + "size": 1 + } + } + } + }, + "PCICR": { + "description": "Pin Change Interrupt Control Register", + "offset": 45, + "size": 8, + "children": { + "fields": { + "PCIE0": { + "description": "Pin Change Interrupt Enable 0", + "offset": 0, + "size": 1 + } + } + } + } + }, + "enums": { + "INTERRUPT_SENSE_CONTROL": { + "description": "Interrupt Sense Control", + "size": 2, + "children": { + "enum_fields": { + "VAL_0x00": { + "description": "Low Level of INTX", + "value": 0 + }, + "VAL_0x01": { + "description": "Any Logical Change of INTX", + "value": 1 + }, + "VAL_0x02": { + "description": "Falling Edge of INTX", + "value": 2 + }, + "VAL_0x03": { + "description": "Rising Edge of INTX", + "value": 3 + } + } + } + } + } + } + }, + "TWI": { + "description": "Two Wire Serial Interface", + "children": { + "registers": { + "TWAMR": { + "description": "TWI (Slave) Address Mask Register", + "offset": 5, + "size": 8, + "children": { + "fields": { + "TWAM": { + "offset": 1, + "size": 7 + } + } + } + }, + "TWBR": { + "description": "TWI Bit Rate register", + "offset": 0, + "size": 8 + }, + "TWCR": { + "description": "TWI Control Register", + "offset": 4, + "size": 8, + "children": { + "fields": { + "TWINT": { + "description": "TWI Interrupt Flag", + "offset": 7, + "size": 1 + }, + "TWEA": { + "description": "TWI Enable Acknowledge Bit", + "offset": 6, + "size": 1 + }, + "TWSTA": { + "description": "TWI Start Condition Bit", + "offset": 5, + "size": 1 + }, + "TWSTO": { + "description": "TWI Stop Condition Bit", + "offset": 4, + "size": 1 + }, + "TWWC": { + "description": "TWI Write Collition Flag", + "offset": 3, + "size": 1 + }, + "TWEN": { + "description": "TWI Enable Bit", + "offset": 2, + "size": 1 + }, + "TWIE": { + "description": "TWI Interrupt Enable", + "offset": 0, + "size": 1 + } + } + } + }, + "TWSR": { + "description": "TWI Status Register", + "offset": 1, + "size": 8, + "children": { + "fields": { + "TWS": { + "description": "TWI Status", + "offset": 3, + "size": 5 + }, + "TWPS": { + "description": "TWI Prescaler", + "offset": 0, + "size": 2, + "enum": "types.peripherals.TWI.children.enums.COMM_TWI_PRESACLE" + } + } + } + }, + "TWDR": { + "description": "TWI Data register", + "offset": 3, + "size": 8 + }, + "TWAR": { + "description": "TWI (Slave) Address register", + "offset": 2, + "size": 8, + "children": { + "fields": { + "TWA": { + "description": "TWI (Slave) Address register Bits", + "offset": 1, + "size": 7 + }, + "TWGCE": { + "description": "TWI General Call Recognition Enable Bit", + "offset": 0, + "size": 1 + } + } + } + } + }, + "enums": { + "COMM_TWI_PRESACLE": { + "size": 2, + "children": { + "enum_fields": { + "VAL_0x00": { + "description": "1", + "value": 0 + }, + "VAL_0x01": { + "description": "4", + "value": 1 + }, + "VAL_0x02": { + "description": "16", + "value": 2 + }, + "VAL_0x03": { + "description": "64", + "value": 3 + } + } + } + } + } + } + }, + "ADC": { + "description": "Analog-to-Digital Converter", + "children": { + "registers": { + "ADMUX": { + "description": "The ADC multiplexer Selection Register", + "offset": 4, + "size": 8, + "children": { + "fields": { + "REFS": { + "description": "Reference Selection Bits", + "offset": 6, + "size": 2, + "enum": "types.peripherals.ADC.children.enums.ANALOG_ADC_V_REF2" + }, + "ADLAR": { + "description": "Left Adjust Result", + "offset": 5, + "size": 1 + }, + "MUX": { + "description": "Analog Channel and Gain Selection Bits", + "offset": 0, + "size": 5 + } + } + } + }, + "ADCSRA": { + "description": "The ADC Control and Status register", + "offset": 2, + "size": 8, + "children": { + "fields": { + "ADEN": { + "description": "ADC Enable", + "offset": 7, + "size": 1 + }, + "ADSC": { + "description": "ADC Start Conversion", + "offset": 6, + "size": 1 + }, + "ADATE": { + "description": "ADC Auto Trigger Enable", + "offset": 5, + "size": 1 + }, + "ADIF": { + "description": "ADC Interrupt Flag", + "offset": 4, + "size": 1 + }, + "ADIE": { + "description": "ADC Interrupt Enable", + "offset": 3, + "size": 1 + }, + "ADPS": { + "description": "ADC Prescaler Select Bits", + "offset": 0, + "size": 3, + "enum": "types.peripherals.ADC.children.enums.ANALOG_ADC_PRESCALER" + } + } + } + }, + "ADC": { + "description": "ADC Data Register Bytes", + "offset": 0, + "size": 16 + }, + "ADCSRB": { + "description": "ADC Control and Status Register B", + "offset": 3, + "size": 8, + "children": { + "fields": { + "ADHSM": { + "description": "ADC High Speed Mode", + "offset": 7, + "size": 1 + }, + "MUX5": { + "description": "Analog Channel and Gain Selection Bits", + "offset": 5, + "size": 1 + }, + "ADTS_bit0": { + "description": "ADC Auto Trigger Sources", + "offset": 0, + "size": 1 + }, + "ADTS_bit1": { + "description": "ADC Auto Trigger Sources", + "offset": 1, + "size": 1 + }, + "ADTS_bit2": { + "description": "ADC Auto Trigger Sources", + "offset": 2, + "size": 1 + }, + "ADTS_bit3": { + "description": "ADC Auto Trigger Sources", + "offset": 4, + "size": 1 + } + } + } + }, + "DIDR0": { + "description": "Digital Input Disable Register 0", + "offset": 6, + "size": 8, + "children": { + "fields": { + "ADC7D": { + "description": "ADC7 Digital input Disable", + "offset": 7, + "size": 1 + }, + "ADC6D": { + "description": "ADC6 Digital input Disable", + "offset": 6, + "size": 1 + }, + "ADC5D": { + "description": "ADC5 Digital input Disable", + "offset": 5, + "size": 1 + }, + "ADC4D": { + "description": "ADC4 Digital input Disable", + "offset": 4, + "size": 1 + }, + "ADC3D": { + "description": "ADC3 Digital input Disable", + "offset": 3, + "size": 1 + }, + "ADC2D": { + "description": "ADC2 Digital input Disable", + "offset": 2, + "size": 1 + }, + "ADC1D": { + "description": "ADC1 Digital input Disable", + "offset": 1, + "size": 1 + }, + "ADC0D": { + "description": "ADC0 Digital input Disable", + "offset": 0, + "size": 1 + } + } + } + }, + "DIDR2": { + "description": "Digital Input Disable Register 2", + "offset": 5, + "size": 8, + "children": { + "fields": { + "ADC13D": { + "description": "ADC13 Digital input Disable", + "offset": 5, + "size": 1 + }, + "ADC12D": { + "description": "ADC12 Digital input Disable", + "offset": 4, + "size": 1 + }, + "ADC11D": { + "description": "ADC11 Digital input Disable", + "offset": 3, + "size": 1 + }, + "ADC10D": { + "description": "ADC10 Digital input Disable", + "offset": 2, + "size": 1 + }, + "ADC9D": { + "description": "ADC9 Digital input Disable", + "offset": 1, + "size": 1 + }, + "ADC8D": { + "description": "ADC8 Digital input Disable", + "offset": 0, + "size": 1 + } + } + } + } + }, + "enums": { + "ANALOG_ADC_V_REF2": { + "size": 2, + "children": { + "enum_fields": { + "VAL_0x00": { + "description": "AREF, Internal Vref turned off", + "value": 0 + }, + "VAL_0x01": { + "description": "AVCC with external capacitor at AREF pin", + "value": 1 + }, + "VAL_0x02": { + "description": "Reserved", + "value": 2 + }, + "VAL_0x03": { + "description": "Internal 2.56V Voltage Reference with external capacitor at AREF pin", + "value": 3 + } + } + } + }, + "ANALOG_ADC_PRESCALER": { + "size": 3, + "children": { + "enum_fields": { + "VAL_0x00": { + "description": "2", + "value": 0 + }, + "VAL_0x01": { + "description": "2", + "value": 1 + }, + "VAL_0x02": { + "description": "4", + "value": 2 + }, + "VAL_0x03": { + "description": "8", + "value": 3 + }, + "VAL_0x04": { + "description": "16", + "value": 4 + }, + "VAL_0x05": { + "description": "32", + "value": 5 + }, + "VAL_0x06": { + "description": "64", + "value": 6 + }, + "VAL_0x07": { + "description": "128", + "value": 7 + } + } + } + }, + "ANALOG_ADC_AUTO_TRIGGER2": { + "size": 3, + "children": { + "enum_fields": { + "VAL_0x00": { + "description": "Free Running mode", + "value": 0 + }, + "VAL_0x01": { + "description": "Analog Comparator", + "value": 1 + }, + "VAL_0x02": { + "description": "External Interrupt Request 0", + "value": 2 + }, + "VAL_0x03": { + "description": "Timer/Counter0 Compare Match A", + "value": 3 + }, + "VAL_0x04": { + "description": "Timer/Counter0 Overflow", + "value": 4 + }, + "VAL_0x05": { + "description": "Timer/Counter1 Compare Match B", + "value": 5 + }, + "VAL_0x06": { + "description": "Timer/Counter1 Overflow", + "value": 6 + }, + "VAL_0x07": { + "description": "Timer/Counter1 Capture Event", + "value": 7 + } + } + } + } + } + } + }, + "AC": { + "description": "Analog Comparator", + "children": { + "registers": { + "ADCSRB": { + "description": "ADC Control and Status Register B", + "offset": 43, + "size": 8, + "children": { + "fields": { + "ACME": { + "description": "Analog Comparator Multiplexer Enable", + "offset": 6, + "size": 1 + } + } + } + }, + "ACSR": { + "description": "Analog Comparator Control And Status Register", + "offset": 0, + "size": 8, + "children": { + "fields": { + "ACD": { + "description": "Analog Comparator Disable", + "offset": 7, + "size": 1 + }, + "ACBG": { + "description": "Analog Comparator Bandgap Select", + "offset": 6, + "size": 1 + }, + "ACO": { + "description": "Analog Compare Output", + "offset": 5, + "size": 1 + }, + "ACI": { + "description": "Analog Comparator Interrupt Flag", + "offset": 4, + "size": 1 + }, + "ACIE": { + "description": "Analog Comparator Interrupt Enable", + "offset": 3, + "size": 1 + }, + "ACIC": { + "description": "Analog Comparator Input Capture Enable", + "offset": 2, + "size": 1 + }, + "ACIS": { + "description": "Analog Comparator Interrupt Mode Select bits", + "offset": 0, + "size": 2, + "enum": "types.peripherals.AC.children.enums.ANALOG_COMP_INTERRUPT" + } + } + } + }, + "DIDR1": { + "offset": 47, + "size": 8, + "children": { + "fields": { + "AIN1D": { + "description": "AIN1 Digital Input Disable", + "offset": 1, + "size": 1 + }, + "AIN0D": { + "description": "AIN0 Digital Input Disable", + "offset": 0, + "size": 1 + } + } + } + } + }, + "enums": { + "ANALOG_COMP_INTERRUPT": { + "size": 2, + "children": { + "enum_fields": { + "VAL_0x00": { + "description": "Interrupt on Toggle", + "value": 0 + }, + "VAL_0x01": { + "description": "Reserved", + "value": 1 + }, + "VAL_0x02": { + "description": "Interrupt on Falling Edge", + "value": 2 + }, + "VAL_0x03": { + "description": "Interrupt on Rising Edge", + "value": 3 + } + } + } + } + } + } + }, + "CPU": { + "description": "CPU Registers", + "children": { + "registers": { + "SREG": { + "description": "Status Register", + "offset": 33, + "size": 8, + "children": { + "fields": { + "I": { + "description": "Global Interrupt Enable", + "offset": 7, + "size": 1 + }, + "T": { + "description": "Bit Copy Storage", + "offset": 6, + "size": 1 + }, + "H": { + "description": "Half Carry Flag", + "offset": 5, + "size": 1 + }, + "S": { + "description": "Sign Bit", + "offset": 4, + "size": 1 + }, + "V": { + "description": "Two's Complement Overflow Flag", + "offset": 3, + "size": 1 + }, + "N": { + "description": "Negative Flag", + "offset": 2, + "size": 1 + }, + "Z": { + "description": "Zero Flag", + "offset": 1, + "size": 1 + }, + "C": { + "description": "Carry Flag", + "offset": 0, + "size": 1 + } + } + } + }, + "SP": { + "description": "Stack Pointer ", + "offset": 31, + "size": 16 + }, + "MCUCR": { + "description": "MCU Control Register", + "offset": 23, + "size": 8, + "children": { + "fields": { + "JTD": { + "description": "JTAG Interface Disable", + "offset": 7, + "size": 1 + }, + "PUD": { + "description": "Pull-up disable", + "offset": 4, + "size": 1 + }, + "IVSEL": { + "description": "Interrupt Vector Select", + "offset": 1, + "size": 1 + }, + "IVCE": { + "description": "Interrupt Vector Change Enable", + "offset": 0, + "size": 1 + } + } + } + }, + "MCUSR": { + "description": "MCU Status Register", + "offset": 22, + "size": 8, + "children": { + "fields": { + "JTRF": { + "description": "JTAG Reset Flag", + "offset": 4, + "size": 1 + }, + "WDRF": { + "description": "Watchdog Reset Flag", + "offset": 3, + "size": 1 + }, + "BORF": { + "description": "Brown-out Reset Flag", + "offset": 2, + "size": 1 + }, + "EXTRF": { + "description": "External Reset Flag", + "offset": 1, + "size": 1 + }, + "PORF": { + "description": "Power-on reset flag", + "offset": 0, + "size": 1 + } + } + } + }, + "OSCCAL": { + "description": "Oscillator Calibration Value", + "offset": 40, + "size": 8, + "children": { + "fields": { + "OSCCAL": { + "description": "Oscillator Calibration ", + "offset": 0, + "size": 8 + } + } + } + }, + "RCCTRL": { + "description": "Oscillator Control Register", + "offset": 41, + "size": 8, + "children": { + "fields": { + "RCFREQ": { + "offset": 0, + "size": 1 + } + } + } + }, + "CLKPR": { + "offset": 35, + "size": 8, + "children": { + "fields": { + "CLKPCE": { + "offset": 7, + "size": 1 + }, + "CLKPS": { + "offset": 0, + "size": 4, + "enum": "types.peripherals.CPU.children.enums.CPU_CLK_PRESCALE_4_BITS_SMALL" + } + } + } + }, + "SMCR": { + "description": "Sleep Mode Control Register", + "offset": 21, + "size": 8, + "children": { + "fields": { + "SM": { + "description": "Sleep Mode Select bits", + "offset": 1, + "size": 3, + "enum": "types.peripherals.CPU.children.enums.CPU_SLEEP_MODE_3BITS" + }, + "SE": { + "description": "Sleep Enable", + "offset": 0, + "size": 1 + } + } + } + }, + "EIND": { + "description": "Extended Indirect Register", + "offset": 30, + "size": 8 + }, + "RAMPZ": { + "description": "Extended Z-pointer Register for ELPM/SPM", + "offset": 29, + "size": 8, + "children": { + "fields": { + "Res": { + "description": "Reserved", + "offset": 2, + "size": 6 + }, + "RAMPZ": { + "description": "Extended Z-Pointer Value", + "offset": 0, + "size": 2, + "enum": "types.peripherals.CPU.children.enums.RAMPZ_BITF" + } + } + } + }, + "GPIOR2": { + "description": "General Purpose IO Register 2", + "offset": 13, + "size": 8, + "children": { + "fields": { + "GPIOR": { + "description": "General Purpose IO Register 2 bis", + "offset": 0, + "size": 8 + } + } + } + }, + "GPIOR1": { + "description": "General Purpose IO Register 1", + "offset": 12, + "size": 8, + "children": { + "fields": { + "GPIOR": { + "description": "General Purpose IO Register 1 bis", + "offset": 0, + "size": 8 + } + } + } + }, + "GPIOR0": { + "description": "General Purpose IO Register 0", + "offset": 0, + "size": 8, + "children": { + "fields": { + "GPIOR07": { + "description": "General Purpose IO Register 0 bit 7", + "offset": 7, + "size": 1 + }, + "GPIOR06": { + "description": "General Purpose IO Register 0 bit 6", + "offset": 6, + "size": 1 + }, + "GPIOR05": { + "description": "General Purpose IO Register 0 bit 5", + "offset": 5, + "size": 1 + }, + "GPIOR04": { + "description": "General Purpose IO Register 0 bit 4", + "offset": 4, + "size": 1 + }, + "GPIOR03": { + "description": "General Purpose IO Register 0 bit 3", + "offset": 3, + "size": 1 + }, + "GPIOR02": { + "description": "General Purpose IO Register 0 bit 2", + "offset": 2, + "size": 1 + }, + "GPIOR01": { + "description": "General Purpose IO Register 0 bit 1", + "offset": 1, + "size": 1 + }, + "GPIOR00": { + "description": "General Purpose IO Register 0 bit 0", + "offset": 0, + "size": 1 + } + } + } + }, + "PRR1": { + "description": "Power Reduction Register1", + "offset": 39, + "size": 8, + "children": { + "fields": { + "PRUSB": { + "description": "Power Reduction USB", + "offset": 7, + "size": 1 + }, + "PRTIM4": { + "description": "Power Reduction Timer/Counter4", + "offset": 4, + "size": 1 + }, + "PRTIM3": { + "description": "Power Reduction Timer/Counter3", + "offset": 3, + "size": 1 + }, + "PRUSART1": { + "description": "Power Reduction USART1", + "offset": 0, + "size": 1 + } + } + } + }, + "PRR0": { + "description": "Power Reduction Register0", + "offset": 38, + "size": 8, + "children": { + "fields": { + "PRTWI": { + "description": "Power Reduction TWI", + "offset": 7, + "size": 1 + }, + "PRTIM2": { + "description": "Power Reduction Timer/Counter2", + "offset": 6, + "size": 1 + }, + "PRTIM0": { + "description": "Power Reduction Timer/Counter0", + "offset": 5, + "size": 1 + }, + "PRTIM1": { + "description": "Power Reduction Timer/Counter1", + "offset": 3, + "size": 1 + }, + "PRSPI": { + "description": "Power Reduction Serial Peripheral Interface", + "offset": 2, + "size": 1 + }, + "PRUSART0": { + "description": "Power Reduction USART", + "offset": 1, + "size": 1 + }, + "PRADC": { + "description": "Power Reduction ADC", + "offset": 0, + "size": 1 + } + } + } + }, + "CLKSTA": { + "offset": 137, + "size": 8, + "children": { + "fields": { + "RCON": { + "offset": 1, + "size": 1 + }, + "EXTON": { + "offset": 0, + "size": 1 + } + } + } + }, + "CLKSEL1": { + "offset": 136, + "size": 8, + "children": { + "fields": { + "RCCKSEL": { + "offset": 4, + "size": 4 + }, + "EXCKSEL": { + "offset": 0, + "size": 4 + } + } + } + }, + "CLKSEL0": { + "offset": 135, + "size": 8, + "children": { + "fields": { + "RCSUT": { + "offset": 6, + "size": 2 + }, + "EXSUT": { + "offset": 4, + "size": 2 + }, + "RCE": { + "offset": 3, + "size": 1 + }, + "EXTE": { + "offset": 2, + "size": 1 + }, + "CLKS": { + "offset": 0, + "size": 1 + } + } + } + } + }, + "enums": { + "CPU_CLK_PRESCALE_4_BITS_SMALL": { + "size": 4, + "children": { + "enum_fields": { + "VAL_0x00": { + "description": "1", + "value": 0 + }, + "VAL_0x01": { + "description": "2", + "value": 1 + }, + "VAL_0x02": { + "description": "4", + "value": 2 + }, + "VAL_0x03": { + "description": "8", + "value": 3 + }, + "VAL_0x04": { + "description": "16", + "value": 4 + }, + "VAL_0x05": { + "description": "32", + "value": 5 + }, + "VAL_0x06": { + "description": "64", + "value": 6 + }, + "VAL_0x07": { + "description": "128", + "value": 7 + }, + "VAL_0x08": { + "description": "256", + "value": 8 + } + } + } + }, + "CPU_SLEEP_MODE_3BITS": { + "size": 3, + "children": { + "enum_fields": { + "IDLE": { + "description": "Idle", + "value": 0 + }, + "ADC": { + "description": "ADC Noise Reduction (If Available)", + "value": 1 + }, + "PDOWN": { + "description": "Power Down", + "value": 2 + }, + "PSAVE": { + "description": "Power Save", + "value": 3 + }, + "VAL_0x04": { + "description": "Reserved", + "value": 4 + }, + "VAL_0x05": { + "description": "Reserved", + "value": 5 + }, + "STDBY": { + "description": "Standby", + "value": 6 + }, + "ESTDBY": { + "description": "Extended Standby", + "value": 7 + } + } + } + }, + "RAMPZ_BITF": { + "size": 2, + "children": { + "enum_fields": { + "VAL_0": { + "description": "Default value of Z-pointer MSB's.", + "value": 0 + } + } + } + }, + "OSCCAL_VALUE_ADDRESSES": { + "description": "Oscillator Calibration Values", + "size": 1, + "children": { + "enum_fields": { + "8_0_MHz": { + "description": "8.0 MHz", + "value": 0 + } + } + } + } + } + } + }, + "PLL": { + "description": "Phase Locked Loop", + "children": { + "registers": { + "PLLCSR": { + "description": "PLL Status and Control register", + "offset": 0, + "size": 8, + "children": { + "fields": { + "PINDIV": { + "description": "PLL prescaler Bit 2", + "offset": 4, + "size": 1 + }, + "PLLE": { + "description": "PLL Enable Bit", + "offset": 1, + "size": 1 + }, + "PLOCK": { + "description": "PLL Lock Status Bit", + "offset": 0, + "size": 1 + } + } + } + }, + "PLLFRQ": { + "description": "PLL Frequency Control Register", + "offset": 9, + "size": 8, + "children": { + "fields": { + "PINMUX": { + "offset": 7, + "size": 1 + }, + "PLLUSB": { + "offset": 6, + "size": 1 + }, + "PLLTM": { + "offset": 4, + "size": 2 + }, + "PDIV": { + "offset": 0, + "size": 4 + } + } + } + } + } + } + }, + "USB_DEVICE": { + "description": "USB Device Registers", + "children": { + "registers": { + "UEINT": { + "offset": 29, + "size": 8 + }, + "UEBCHX": { + "offset": 28, + "size": 8 + }, + "UEBCLX": { + "offset": 27, + "size": 8 + }, + "UEDATX": { + "offset": 26, + "size": 8, + "children": { + "fields": { + "DAT": { + "offset": 0, + "size": 8 + } + } + } + }, + "UEIENX": { + "offset": 25, + "size": 8, + "children": { + "fields": { + "FLERRE": { + "offset": 7, + "size": 1 + }, + "NAKINE": { + "offset": 6, + "size": 1 + }, + "NAKOUTE": { + "offset": 4, + "size": 1 + }, + "RXSTPE": { + "offset": 3, + "size": 1 + }, + "RXOUTE": { + "offset": 2, + "size": 1 + }, + "STALLEDE": { + "offset": 1, + "size": 1 + }, + "TXINE": { + "offset": 0, + "size": 1 + } + } + } + }, + "UESTA1X": { + "offset": 24, + "size": 8, + "children": { + "fields": { + "CTRLDIR": { + "offset": 2, + "size": 1 + }, + "CURRBK": { + "offset": 0, + "size": 2 + } + } + } + }, + "UESTA0X": { + "offset": 23, + "size": 8, + "children": { + "fields": { + "CFGOK": { + "offset": 7, + "size": 1 + }, + "OVERFI": { + "offset": 6, + "size": 1 + }, + "UNDERFI": { + "offset": 5, + "size": 1 + }, + "DTSEQ": { + "offset": 2, + "size": 2 + }, + "NBUSYBK": { + "offset": 0, + "size": 2 + } + } + } + }, + "UECFG1X": { + "offset": 22, + "size": 8, + "children": { + "fields": { + "EPSIZE": { + "offset": 4, + "size": 3 + }, + "EPBK": { + "offset": 2, + "size": 2 + }, + "ALLOC": { + "offset": 1, + "size": 1 + } + } + } + }, + "UECFG0X": { + "offset": 21, + "size": 8, + "children": { + "fields": { + "EPTYPE": { + "offset": 6, + "size": 2 + }, + "EPDIR": { + "offset": 0, + "size": 1 + } + } + } + }, + "UECONX": { + "offset": 20, + "size": 8, + "children": { + "fields": { + "STALLRQ": { + "offset": 5, + "size": 1 + }, + "STALLRQC": { + "offset": 4, + "size": 1 + }, + "RSTDT": { + "offset": 3, + "size": 1 + }, + "EPEN": { + "offset": 0, + "size": 1 + } + } + } + }, + "UERST": { + "offset": 19, + "size": 8, + "children": { + "fields": { + "EPRST": { + "offset": 0, + "size": 7 + } + } + } + }, + "UENUM": { + "offset": 18, + "size": 8 + }, + "UEINTX": { + "offset": 17, + "size": 8, + "children": { + "fields": { + "FIFOCON": { + "offset": 7, + "size": 1 + }, + "NAKINI": { + "offset": 6, + "size": 1 + }, + "RWAL": { + "offset": 5, + "size": 1 + }, + "NAKOUTI": { + "offset": 4, + "size": 1 + }, + "RXSTPI": { + "offset": 3, + "size": 1 + }, + "RXOUTI": { + "offset": 2, + "size": 1 + }, + "STALLEDI": { + "offset": 1, + "size": 1 + }, + "TXINI": { + "offset": 0, + "size": 1 + } + } + } + }, + "UDMFN": { + "offset": 15, + "size": 8, + "children": { + "fields": { + "FNCERR": { + "offset": 4, + "size": 1 + } + } + } + }, + "UDFNUM": { + "offset": 13, + "size": 16 + }, + "UDADDR": { + "offset": 12, + "size": 8, + "children": { + "fields": { + "ADDEN": { + "offset": 7, + "size": 1 + }, + "UADD": { + "offset": 0, + "size": 7 + } + } + } + }, + "UDIEN": { + "offset": 11, + "size": 8, + "children": { + "fields": { + "UPRSME": { + "offset": 6, + "size": 1 + }, + "EORSME": { + "offset": 5, + "size": 1 + }, + "WAKEUPE": { + "offset": 4, + "size": 1 + }, + "EORSTE": { + "offset": 3, + "size": 1 + }, + "SOFE": { + "offset": 2, + "size": 1 + }, + "SUSPE": { + "offset": 0, + "size": 1 + } + } + } + }, + "UDINT": { + "offset": 10, + "size": 8, + "children": { + "fields": { + "UPRSMI": { + "offset": 6, + "size": 1 + }, + "EORSMI": { + "offset": 5, + "size": 1 + }, + "WAKEUPI": { + "offset": 4, + "size": 1 + }, + "EORSTI": { + "offset": 3, + "size": 1 + }, + "SOFI": { + "offset": 2, + "size": 1 + }, + "SUSPI": { + "offset": 0, + "size": 1 + } + } + } + }, + "UDCON": { + "offset": 9, + "size": 8, + "children": { + "fields": { + "LSM": { + "description": "USB low speed mode", + "offset": 2, + "size": 1 + }, + "RSTCPU": { + "offset": 3, + "size": 1 + }, + "RMWKUP": { + "offset": 1, + "size": 1 + }, + "DETACH": { + "offset": 0, + "size": 1 + } + } + } + }, + "USBCON": { + "description": "USB General Control Register", + "offset": 1, + "size": 8, + "children": { + "fields": { + "USBE": { + "offset": 7, + "size": 1 + }, + "FRZCLK": { + "offset": 5, + "size": 1 + }, + "OTGPADE": { + "offset": 4, + "size": 1 + }, + "VBUSTE": { + "offset": 0, + "size": 1 + } + } + } + }, + "USBINT": { + "offset": 3, + "size": 8, + "children": { + "fields": { + "VBUSTI": { + "offset": 0, + "size": 1 + } + } + } + }, + "USBSTA": { + "offset": 2, + "size": 8, + "children": { + "fields": { + "SPEED": { + "offset": 3, + "size": 1 + }, + "VBUS": { + "offset": 0, + "size": 1 + } + } + } + }, + "UHWCON": { + "offset": 0, + "size": 8, + "children": { + "fields": { + "UVREGE": { + "offset": 0, + "size": 1 + } + } + } + } + } + } + } + } + }, + "devices": { + "ATmega32U4": { + "arch": "avr8", + "properties": { + "family": "megaAVR", + "arch": "AVR8" + }, + "children": { + "interrupts": { + "RESET": { + "index": 0, + "description": "External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. " + }, + "INT0": { + "index": 1, + "description": "External Interrupt Request 0" + }, + "INT1": { + "index": 2, + "description": "External Interrupt Request 1" + }, + "INT2": { + "index": 3, + "description": "External Interrupt Request 2" + }, + "INT3": { + "index": 4, + "description": "External Interrupt Request 3" + }, + "Reserved1": { + "index": 5, + "description": "Reserved1" + }, + "Reserved2": { + "index": 6, + "description": "Reserved2" + }, + "INT6": { + "index": 7, + "description": "External Interrupt Request 6" + }, + "Reserved3": { + "index": 8, + "description": "Reserved3" + }, + "PCINT0": { + "index": 9, + "description": "Pin Change Interrupt Request 0" + }, + "USB_GEN": { + "index": 10, + "description": "USB General Interrupt Request" + }, + "USB_COM": { + "index": 11, + "description": "USB Endpoint/Pipe Interrupt Communication Request" + }, + "WDT": { + "index": 12, + "description": "Watchdog Time-out Interrupt" + }, + "Reserved4": { + "index": 13, + "description": "Reserved4" + }, + "Reserved5": { + "index": 14, + "description": "Reserved5" + }, + "Reserved6": { + "index": 15, + "description": "Reserved6" + }, + "TIMER1_CAPT": { + "index": 16, + "description": "Timer/Counter1 Capture Event" + }, + "TIMER1_COMPA": { + "index": 17, + "description": "Timer/Counter1 Compare Match A" + }, + "TIMER1_COMPB": { + "index": 18, + "description": "Timer/Counter1 Compare Match B" + }, + "TIMER1_COMPC": { + "index": 19, + "description": "Timer/Counter1 Compare Match C" + }, + "TIMER1_OVF": { + "index": 20, + "description": "Timer/Counter1 Overflow" + }, + "TIMER0_COMPA": { + "index": 21, + "description": "Timer/Counter0 Compare Match A" + }, + "TIMER0_COMPB": { + "index": 22, + "description": "Timer/Counter0 Compare Match B" + }, + "TIMER0_OVF": { + "index": 23, + "description": "Timer/Counter0 Overflow" + }, + "SPI_STC": { + "index": 24, + "description": "SPI Serial Transfer Complete" + }, + "USART1_RX": { + "index": 25, + "description": "USART1, Rx Complete" + }, + "USART1_UDRE": { + "index": 26, + "description": "USART1 Data register Empty" + }, + "USART1_TX": { + "index": 27, + "description": "USART1, Tx Complete" + }, + "ANALOG_COMP": { + "index": 28, + "description": "Analog Comparator" + }, + "ADC": { + "index": 29, + "description": "ADC Conversion Complete" + }, + "EE_READY": { + "index": 30, + "description": "EEPROM Ready" + }, + "TIMER3_CAPT": { + "index": 31, + "description": "Timer/Counter3 Capture Event" + }, + "TIMER3_COMPA": { + "index": 32, + "description": "Timer/Counter3 Compare Match A" + }, + "TIMER3_COMPB": { + "index": 33, + "description": "Timer/Counter3 Compare Match B" + }, + "TIMER3_COMPC": { + "index": 34, + "description": "Timer/Counter3 Compare Match C" + }, + "TIMER3_OVF": { + "index": 35, + "description": "Timer/Counter3 Overflow" + }, + "TWI": { + "index": 36, + "description": "2-wire Serial Interface " + }, + "SPM_READY": { + "index": 37, + "description": "Store Program Memory Read" + }, + "TIMER4_COMPA": { + "index": 38, + "description": "Timer/Counter4 Compare Match A" + }, + "TIMER4_COMPB": { + "index": 39, + "description": "Timer/Counter4 Compare Match B" + }, + "TIMER4_COMPD": { + "index": 40, + "description": "Timer/Counter4 Compare Match D" + }, + "TIMER4_OVF": { + "index": 41, + "description": "Timer/Counter4 Overflow" + }, + "TIMER4_FPF": { + "index": 42, + "description": "Timer/Counter4 Fault Protection Interrupt" + } + }, + "peripheral_instances": { + "WDT": { + "description": "Watchdog Timer", + "offset": 96, + "type": "types.peripherals.WDT" + }, + "PORTB": { + "description": "I/O Port", + "offset": 35, + "type": "types.peripherals.PORT.children.register_groups.PORTB" + }, + "PORTC": { + "description": "I/O Port", + "offset": 38, + "type": "types.peripherals.PORT.children.register_groups.PORTC" + }, + "PORTD": { + "description": "I/O Port", + "offset": 41, + "type": "types.peripherals.PORT.children.register_groups.PORTD" + }, + "PORTE": { + "description": "I/O Port", + "offset": 44, + "type": "types.peripherals.PORT.children.register_groups.PORTE" + }, + "PORTF": { + "description": "I/O Port", + "offset": 47, + "type": "types.peripherals.PORT.children.register_groups.PORTF" + }, + "SPI": { + "description": "Serial Peripheral Interface", + "offset": 76, + "type": "types.peripherals.SPI" + }, + "USART1": { + "description": "USART", + "offset": 200, + "type": "types.peripherals.USART.children.register_groups.USART1" + }, + "BOOT_LOAD": { + "description": "Bootloader", + "offset": 87, + "type": "types.peripherals.BOOT_LOAD" + }, + "EEPROM": { + "description": "EEPROM", + "offset": 63, + "type": "types.peripherals.EEPROM" + }, + "TC0": { + "description": "Timer/Counter, 8-bit", + "offset": 53, + "type": "types.peripherals.TC8.children.register_groups.TC0" + }, + "TC1": { + "description": "Timer/Counter, 16-bit", + "offset": 54, + "type": "types.peripherals.TC16.children.register_groups.TC1" + }, + "TC3": { + "description": "Timer/Counter, 16-bit", + "offset": 56, + "type": "types.peripherals.TC16.children.register_groups.TC3" + }, + "TC4": { + "description": "Timer/Counter, 10-bit", + "offset": 57, + "type": "types.peripherals.TC10.children.register_groups.TC4" + }, + "JTAG": { + "description": "JTAG Interface", + "offset": 81, + "type": "types.peripherals.JTAG" + }, + "EXINT": { + "description": "External Interrupts", + "offset": 59, + "type": "types.peripherals.EXINT" + }, + "TWI": { + "description": "Two Wire Serial Interface", + "offset": 184, + "type": "types.peripherals.TWI" + }, + "ADC": { + "description": "Analog-to-Digital Converter", + "offset": 120, + "type": "types.peripherals.ADC" + }, + "AC": { + "description": "Analog Comparator", + "offset": 80, + "type": "types.peripherals.AC" + }, + "CPU": { + "description": "CPU Registers", + "offset": 62, + "type": "types.peripherals.CPU" + }, + "PLL": { + "description": "Phase Locked Loop", + "offset": 73, + "type": "types.peripherals.PLL" + }, + "USB_DEVICE": { + "description": "USB Device Registers", + "offset": 215, + "type": "types.peripherals.USB_DEVICE" + }, + "FUSE": { + "description": "Fuses", + "offset": 0, + "type": "types.peripherals.FUSE" + }, + "LOCKBIT": { + "description": "Lockbits", + "offset": 0, + "type": "types.peripherals.LOCKBIT" + } + } + } + } + } +} diff --git a/bsp/microchip/avr/src/hals/ATmega32U4.zig b/bsp/microchip/avr/src/hals/ATmega32U4.zig new file mode 100644 index 0000000..eea825f --- /dev/null +++ b/bsp/microchip/avr/src/hals/ATmega32U4.zig @@ -0,0 +1,200 @@ +// Almost an exact clone of ATmega328p +const std = @import("std"); +const micro = @import("microzig"); +const peripherals = micro.chip.peripherals; +const USART1 = peripherals.USART1; + +pub const cpu = micro.cpu; +const Port = enum(u8) { + B = 1, + C = 2, + D = 3, + E = 4, + F = 5, +}; + +pub const clock = struct { + pub const Domain = enum { + cpu, + }; +}; + +pub fn parsePin(comptime spec: []const u8) type { + const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme."; + + if (spec.len != 3) + @compileError(invalid_format_msg); + if (spec[0] != 'P') + @compileError(invalid_format_msg); + const pin = struct { + pub const port: Port = std.meta.stringToEnum(Port, spec[1..2]) orelse @compileError(invalid_format_msg); + pub const pin: u3 = std.fmt.parseInt(u3, spec[2..3], 10) catch @compileError(invalid_format_msg); + }; + switch (pin.port) { + .B => {}, + .C => if (pin.pin < 6) @compileError("Invalid pin: " ++ spec), + .D => {}, + .E => if (pin.pin != 2 and pin.pin != 6) @compileError("Invalid pin: " ++ spec), + .F => if (pin.pin == 2 or pin.pin == 3) @compileError("Invalid pin: " ++ spec), + } + return pin; +} + +pub const gpio = struct { + fn regs(comptime desc: type) type { + return struct { + // io address + const pin_addr: u5 = 3 * @intFromEnum(desc.port) + 0x00; + const dir_addr: u5 = 3 * @intFromEnum(desc.port) + 0x01; + const port_addr: u5 = 3 * @intFromEnum(desc.port) + 0x02; + + // ram mapping + const pin = @as(*volatile u8, @ptrFromInt(0x20 + @as(usize, pin_addr))); + const dir = @as(*volatile u8, @ptrFromInt(0x20 + @as(usize, dir_addr))); + const port = @as(*volatile u8, @ptrFromInt(0x20 + @as(usize, port_addr))); + }; + } + + pub fn setOutput(comptime pin: type) void { + cpu.sbi(regs(pin).dir_addr, pin.pin); + } + + pub fn setInput(comptime pin: type) void { + cpu.cbi(regs(pin).dir_addr, pin.pin); + } + + pub fn read(comptime pin: type) micro.gpio.State { + return if ((regs(pin).pin.* & (1 << pin.pin)) != 0) + .high + else + .low; + } + + pub fn write(comptime pin: type, state: micro.gpio.State) void { + if (state == .high) { + cpu.sbi(regs(pin).port_addr, pin.pin); + } else { + cpu.cbi(regs(pin).port_addr, pin.pin); + } + } + + pub fn toggle(comptime pin: type) void { + cpu.sbi(regs(pin).pin_addr, pin.pin); + } +}; + +pub const uart = struct { + pub const DataBits = enum { + five, + six, + seven, + eight, + nine, + }; + + pub const StopBits = enum { + one, + two, + }; + + pub const Parity = enum { + odd, + even, + }; +}; + +pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type { + if (index != 0) @compileError("Atmega32U4 only has a single uart!"); + if (pins.tx != null or pins.rx != null) + @compileError("Atmega32U4 has fixed pins for uart!"); + + return struct { + const Self = @This(); + + fn computeDivider(baud_rate: u32) !u12 { + const pclk = micro.clock.get().cpu; + const divider = ((pclk + (8 * baud_rate)) / (16 * baud_rate)) - 1; + + return std.math.cast(u12, divider) orelse return error.UnsupportedBaudRate; + } + + fn computeBaudRate(divider: u12) u32 { + return micro.clock.get().cpu / (16 * @as(u32, divider) + 1); + } + + pub fn init(config: micro.uart.Config) !Self { + const ucsz: u3 = switch (config.data_bits) { + .five => 0b000, + .six => 0b001, + .seven => 0b010, + .eight => 0b011, + .nine => return error.UnsupportedWordSize, // 0b111 + }; + + const upm: u2 = if (config.parity) |parity| switch (parity) { + .even => @as(u2, 0b10), // even + .odd => @as(u2, 0b11), // odd + } else 0b00; // parity disabled + + const usbs: u1 = switch (config.stop_bits) { + .one => 0b0, + .two => 0b1, + }; + + const umsel: u2 = 0b00; // Asynchronous USART + + // baud is computed like this: + // f(osc) + // BAUD = ---------------- + // 16 * (UBRRn + 1) + + const ubrr_val = try computeDivider(config.baud_rate); + + USART1.UCSR1A.modify(.{ + .MPCM1 = 0, + .U2X1 = 0, + }); + USART1.UCSR1B.write(.{ + .TXB81 = 0, // we don't care about these btw + .RXB81 = 0, // we don't care about these btw + .UCSZ12 = @as(u1, @truncate((ucsz & 0x04) >> 2)), + .TXEN1 = 1, + .RXEN1 = 1, + .UDRIE1 = 0, // no interrupts + .TXCIE1 = 0, // no interrupts + .RXCIE1 = 0, // no interrupts + }); + USART1.UCSR1C.write(.{ + .UCPOL1 = 0, // async mode + .UCSZ1 = @as(u2, @truncate((ucsz & 0x03) >> 0)), + .USBS1 = usbs, + .UPM1 = upm, + .UMSEL1 = umsel, + }); + + USART1.UBRR1.modify(ubrr_val); + + return Self{}; + } + + pub fn canWrite(self: Self) bool { + _ = self; + return (USART1.UCSR1A.read().UDRE1 == 1); + } + + pub fn tx(self: Self, ch: u8) void { + while (!self.canWrite()) {} // Wait for Previous transmission + USART1.UDR1.* = ch; // Load the data to be transmitted + } + + pub fn canRead(self: Self) bool { + _ = self; + return (USART1.UCSR1A.read().RXC1 == 1); + } + + pub fn rx(self: Self) u8 { + while (!self.canRead()) {} // Wait till the data is received + return USART1.UDR1.*; // Read received data + } + }; +}