From 8a5ee675885b6d50ff8e0a70d0d459ee8705aec9 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Tue, 15 Feb 2022 18:02:20 -0800 Subject: [PATCH] register arrays and clusters, nrf52 as well (#19) * register arrays and clusters, nrf52 as well * remove TODO comment --- src/core/mmio.zig | 2 +- src/modules/chips.zig | 10 + src/modules/chips/nrf52/nrf52.zig | 2 + src/modules/chips/nrf52/registers.zig | 21145 ++++++++++++++++ src/modules/chips/stm32f103/registers.zig | 16056 +++++++----- src/modules/chips/stm32f303/registers.zig | 26030 +++++++++++++------- src/tools/svd2zig.py | 281 +- 7 files changed, 48093 insertions(+), 15433 deletions(-) create mode 100644 src/modules/chips/nrf52/nrf52.zig create mode 100644 src/modules/chips/nrf52/registers.zig diff --git a/src/core/mmio.zig b/src/core/mmio.zig index a46ca0c..4df5ef4 100644 --- a/src/core/mmio.zig +++ b/src/core/mmio.zig @@ -14,7 +14,7 @@ pub fn MMIO(comptime size: u8, comptime PackedT: type) type { const IntT = std.meta.Int(.unsigned, size); if (@sizeOf(PackedT) != (size / 8)) - @compileError("IntT and PackedT must have the same size!"); + @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) })); return extern struct { const Self = @This(); diff --git a/src/modules/chips.zig b/src/modules/chips.zig index 25c6cf2..7058431 100644 --- a/src/modules/chips.zig +++ b/src/modules/chips.zig @@ -49,3 +49,13 @@ pub const stm32f303vc = Chip{ MemoryRegion{ .offset = 0x20000000, .length = 40 * 1024, .kind = .ram }, }, }; + +pub const nrf52832 = Chip{ + .name = "nRF52832", + .path = root_path ++ "chips/nrf52/nrf52.zig", + .cpu = cpus.cortex_m4, + .memory_regions = &.{ + MemoryRegion{ .offset = 0x00000000, .length = 0x80000, .kind = .flash }, + MemoryRegion{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, +}; diff --git a/src/modules/chips/nrf52/nrf52.zig b/src/modules/chips/nrf52/nrf52.zig new file mode 100644 index 0000000..5ae1cd3 --- /dev/null +++ b/src/modules/chips/nrf52/nrf52.zig @@ -0,0 +1,2 @@ +pub const cpu = @import("cpu"); +pub const registers = @import("registers.zig"); diff --git a/src/modules/chips/nrf52/registers.zig b/src/modules/chips/nrf52/registers.zig new file mode 100644 index 0000000..97e4fec --- /dev/null +++ b/src/modules/chips/nrf52/registers.zig @@ -0,0 +1,21145 @@ +// generated using svd2zig.py +// DO NOT EDIT +// based on nrf52 version 1 +const microzig_mmio = @import("microzig-mmio"); +const mmio = microzig_mmio.mmio; +const MMIO = microzig_mmio.MMIO; +const Name = "nrf52"; + +/// Factory Information Configuration Registers +pub const FICR = extern struct { + pub const Address: u32 = 0x10000000; + + /// Code memory page size + pub const CODEPAGESIZE = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Code memory size + pub const CODESIZE = @intToPtr(*volatile u32, Address + 0x00000014); + + /// Device address type + pub const DEVICEADDRTYPE = mmio(Address + 0x000000a0, 32, packed struct { + /// Device address type + DEVICEADDRTYPE: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Device identifier + pub const DEVICEID = @intToPtr(*volatile [2]u32, Address + 0x00000060); + /// Description collection[0]: Encryption Root, word 0 + pub const ER = @intToPtr(*volatile [4]u32, Address + 0x00000080); + /// Description collection[0]: Identity Root, word 0 + pub const IR = @intToPtr(*volatile [4]u32, Address + 0x00000090); + /// Description collection[0]: Device address 0 + pub const DEVICEADDR = @intToPtr(*volatile [2]u32, Address + 0x000000a4); + + pub const INFO = struct { + + /// Part code + pub const PART = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Part Variant, Hardware version and Production configuration + pub const VARIANT = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Package option + pub const PACKAGE = @intToPtr(*volatile u32, Address + 0x00000008); + + /// RAM variant + pub const RAM = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Flash variant + pub const FLASH = @intToPtr(*volatile u32, Address + 0x00000010); + /// Description collection[0]: Unspecified + pub const UNUSED0 = @intToPtr(*volatile [3]u32, Address + 0x00000014); + }; + + pub const TEMP = struct { + + /// Slope definition A0. + pub const A0 = mmio(Address + 0x00000000, 32, packed struct { + /// A (slope definition) register. + A: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Slope definition A1. + pub const A1 = mmio(Address + 0x00000004, 32, packed struct { + /// A (slope definition) register. + A: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Slope definition A2. + pub const A2 = mmio(Address + 0x00000008, 32, packed struct { + /// A (slope definition) register. + A: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Slope definition A3. + pub const A3 = mmio(Address + 0x0000000c, 32, packed struct { + /// A (slope definition) register. + A: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Slope definition A4. + pub const A4 = mmio(Address + 0x00000010, 32, packed struct { + /// A (slope definition) register. + A: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Slope definition A5. + pub const A5 = mmio(Address + 0x00000014, 32, packed struct { + /// A (slope definition) register. + A: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// y-intercept B0. + pub const B0 = mmio(Address + 0x00000018, 32, packed struct { + /// B (y-intercept) + B: u14 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// y-intercept B1. + pub const B1 = mmio(Address + 0x0000001c, 32, packed struct { + /// B (y-intercept) + B: u14 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// y-intercept B2. + pub const B2 = mmio(Address + 0x00000020, 32, packed struct { + /// B (y-intercept) + B: u14 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// y-intercept B3. + pub const B3 = mmio(Address + 0x00000024, 32, packed struct { + /// B (y-intercept) + B: u14 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// y-intercept B4. + pub const B4 = mmio(Address + 0x00000028, 32, packed struct { + /// B (y-intercept) + B: u14 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// y-intercept B5. + pub const B5 = mmio(Address + 0x0000002c, 32, packed struct { + /// B (y-intercept) + B: u14 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Segment end T0. + pub const T0 = mmio(Address + 0x00000030, 32, packed struct { + /// T (segment end)register. + T: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Segment end T1. + pub const T1 = mmio(Address + 0x00000034, 32, packed struct { + /// T (segment end)register. + T: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Segment end T2. + pub const T2 = mmio(Address + 0x00000038, 32, packed struct { + /// T (segment end)register. + T: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Segment end T3. + pub const T3 = mmio(Address + 0x0000003c, 32, packed struct { + /// T (segment end)register. + T: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Segment end T4. + pub const T4 = mmio(Address + 0x00000040, 32, packed struct { + /// T (segment end)register. + T: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; + + pub const NFC = struct { + + /// Default header for NFC Tag. Software can read these values to populate + /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + pub const TAGHEADER0 = mmio(Address + 0x00000000, 32, packed struct { + /// Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F + MFGID: u8 = 0, + /// Unique identifier byte 1 + UD1: u8 = 0, + /// Unique identifier byte 2 + UD2: u8 = 0, + /// Unique identifier byte 3 + UD3: u8 = 0, + }); + + /// Default header for NFC Tag. Software can read these values to populate + /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + pub const TAGHEADER1 = mmio(Address + 0x00000004, 32, packed struct { + /// Unique identifier byte 4 + UD4: u8 = 0, + /// Unique identifier byte 5 + UD5: u8 = 0, + /// Unique identifier byte 6 + UD6: u8 = 0, + /// Unique identifier byte 7 + UD7: u8 = 0, + }); + + /// Default header for NFC Tag. Software can read these values to populate + /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + pub const TAGHEADER2 = mmio(Address + 0x00000008, 32, packed struct { + /// Unique identifier byte 8 + UD8: u8 = 0, + /// Unique identifier byte 9 + UD9: u8 = 0, + /// Unique identifier byte 10 + UD10: u8 = 0, + /// Unique identifier byte 11 + UD11: u8 = 0, + }); + + /// Default header for NFC Tag. Software can read these values to populate + /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + pub const TAGHEADER3 = mmio(Address + 0x0000000c, 32, packed struct { + /// Unique identifier byte 12 + UD12: u8 = 0, + /// Unique identifier byte 13 + UD13: u8 = 0, + /// Unique identifier byte 14 + UD14: u8 = 0, + /// Unique identifier byte 15 + UD15: u8 = 0, + }); + }; +}; + +/// User Information Configuration Registers +pub const UICR = extern struct { + pub const Address: u32 = 0x10001000; + + /// Unspecified + pub const UNUSED0 = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Unspecified + pub const UNUSED1 = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Unspecified + pub const UNUSED2 = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Unspecified + pub const UNUSED3 = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Access Port protection + pub const APPROTECT = mmio(Address + 0x00000208, 32, packed struct { + /// Enable or disable Access Port protection. Any other value than 0xFF being + /// written to this field will enable protection. + PALL: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Setting of pins dedicated to NFC functionality: NFC antenna or GPIO + pub const NFCPINS = mmio(Address + 0x0000020c, 32, packed struct { + /// Setting of pins dedicated to NFC functionality + PROTECT: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Reserved for Nordic firmware design + pub const NRFFW = @intToPtr(*volatile [15]u32, Address + 0x00000014); + /// Description collection[0]: Reserved for Nordic hardware design + pub const NRFHW = @intToPtr(*volatile [12]u32, Address + 0x00000050); + /// Description collection[0]: Reserved for customer + pub const CUSTOMER = @intToPtr(*volatile [32]u32, Address + 0x00000080); + /// Description collection[0]: Mapping of the nRESET function (see POWER chapter + /// for details) + pub const PSELRESET = @intToPtr(*volatile [2]MMIO(32, packed struct { + /// GPIO number P0.n onto which Reset is exposed + PIN: u6 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }), Address + 0x00000200); +}; + +/// Block Protect +pub const BPROT = extern struct { + pub const Address: u32 = 0x40000000; + + /// Block protect configuration register 0 + pub const CONFIG0 = mmio(Address + 0x00000600, 32, packed struct { + /// Enable protection for region 0. Write '0' has no effect. + REGION0: u1 = 0, + /// Enable protection for region 1. Write '0' has no effect. + REGION1: u1 = 0, + /// Enable protection for region 2. Write '0' has no effect. + REGION2: u1 = 0, + /// Enable protection for region 3. Write '0' has no effect. + REGION3: u1 = 0, + /// Enable protection for region 4. Write '0' has no effect. + REGION4: u1 = 0, + /// Enable protection for region 5. Write '0' has no effect. + REGION5: u1 = 0, + /// Enable protection for region 6. Write '0' has no effect. + REGION6: u1 = 0, + /// Enable protection for region 7. Write '0' has no effect. + REGION7: u1 = 0, + /// Enable protection for region 8. Write '0' has no effect. + REGION8: u1 = 0, + /// Enable protection for region 9. Write '0' has no effect. + REGION9: u1 = 0, + /// Enable protection for region 10. Write '0' has no effect. + REGION10: u1 = 0, + /// Enable protection for region 11. Write '0' has no effect. + REGION11: u1 = 0, + /// Enable protection for region 12. Write '0' has no effect. + REGION12: u1 = 0, + /// Enable protection for region 13. Write '0' has no effect. + REGION13: u1 = 0, + /// Enable protection for region 14. Write '0' has no effect. + REGION14: u1 = 0, + /// Enable protection for region 15. Write '0' has no effect. + REGION15: u1 = 0, + /// Enable protection for region 16. Write '0' has no effect. + REGION16: u1 = 0, + /// Enable protection for region 17. Write '0' has no effect. + REGION17: u1 = 0, + /// Enable protection for region 18. Write '0' has no effect. + REGION18: u1 = 0, + /// Enable protection for region 19. Write '0' has no effect. + REGION19: u1 = 0, + /// Enable protection for region 20. Write '0' has no effect. + REGION20: u1 = 0, + /// Enable protection for region 21. Write '0' has no effect. + REGION21: u1 = 0, + /// Enable protection for region 22. Write '0' has no effect. + REGION22: u1 = 0, + /// Enable protection for region 23. Write '0' has no effect. + REGION23: u1 = 0, + /// Enable protection for region 24. Write '0' has no effect. + REGION24: u1 = 0, + /// Enable protection for region 25. Write '0' has no effect. + REGION25: u1 = 0, + /// Enable protection for region 26. Write '0' has no effect. + REGION26: u1 = 0, + /// Enable protection for region 27. Write '0' has no effect. + REGION27: u1 = 0, + /// Enable protection for region 28. Write '0' has no effect. + REGION28: u1 = 0, + /// Enable protection for region 29. Write '0' has no effect. + REGION29: u1 = 0, + /// Enable protection for region 30. Write '0' has no effect. + REGION30: u1 = 0, + /// Enable protection for region 31. Write '0' has no effect. + REGION31: u1 = 0, + }); + + /// Block protect configuration register 1 + pub const CONFIG1 = mmio(Address + 0x00000604, 32, packed struct { + /// Enable protection for region 32. Write '0' has no effect. + REGION32: u1 = 0, + /// Enable protection for region 33. Write '0' has no effect. + REGION33: u1 = 0, + /// Enable protection for region 34. Write '0' has no effect. + REGION34: u1 = 0, + /// Enable protection for region 35. Write '0' has no effect. + REGION35: u1 = 0, + /// Enable protection for region 36. Write '0' has no effect. + REGION36: u1 = 0, + /// Enable protection for region 37. Write '0' has no effect. + REGION37: u1 = 0, + /// Enable protection for region 38. Write '0' has no effect. + REGION38: u1 = 0, + /// Enable protection for region 39. Write '0' has no effect. + REGION39: u1 = 0, + /// Enable protection for region 40. Write '0' has no effect. + REGION40: u1 = 0, + /// Enable protection for region 41. Write '0' has no effect. + REGION41: u1 = 0, + /// Enable protection for region 42. Write '0' has no effect. + REGION42: u1 = 0, + /// Enable protection for region 43. Write '0' has no effect. + REGION43: u1 = 0, + /// Enable protection for region 44. Write '0' has no effect. + REGION44: u1 = 0, + /// Enable protection for region 45. Write '0' has no effect. + REGION45: u1 = 0, + /// Enable protection for region 46. Write '0' has no effect. + REGION46: u1 = 0, + /// Enable protection for region 47. Write '0' has no effect. + REGION47: u1 = 0, + /// Enable protection for region 48. Write '0' has no effect. + REGION48: u1 = 0, + /// Enable protection for region 49. Write '0' has no effect. + REGION49: u1 = 0, + /// Enable protection for region 50. Write '0' has no effect. + REGION50: u1 = 0, + /// Enable protection for region 51. Write '0' has no effect. + REGION51: u1 = 0, + /// Enable protection for region 52. Write '0' has no effect. + REGION52: u1 = 0, + /// Enable protection for region 53. Write '0' has no effect. + REGION53: u1 = 0, + /// Enable protection for region 54. Write '0' has no effect. + REGION54: u1 = 0, + /// Enable protection for region 55. Write '0' has no effect. + REGION55: u1 = 0, + /// Enable protection for region 56. Write '0' has no effect. + REGION56: u1 = 0, + /// Enable protection for region 57. Write '0' has no effect. + REGION57: u1 = 0, + /// Enable protection for region 58. Write '0' has no effect. + REGION58: u1 = 0, + /// Enable protection for region 59. Write '0' has no effect. + REGION59: u1 = 0, + /// Enable protection for region 60. Write '0' has no effect. + REGION60: u1 = 0, + /// Enable protection for region 61. Write '0' has no effect. + REGION61: u1 = 0, + /// Enable protection for region 62. Write '0' has no effect. + REGION62: u1 = 0, + /// Enable protection for region 63. Write '0' has no effect. + REGION63: u1 = 0, + }); + + /// Disable protection mechanism in debug interface mode + pub const DISABLEINDEBUG = mmio(Address + 0x00000608, 32, packed struct { + /// Disable the protection mechanism for NVM regions while in debug interface + /// mode. This register will only disable the protection mechanism if the device + /// is in debug interface mode. + DISABLEINDEBUG: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Unspecified + pub const UNUSED0 = @intToPtr(*volatile u32, Address + 0x0000060c); + + /// Block protect configuration register 2 + pub const CONFIG2 = mmio(Address + 0x00000610, 32, packed struct { + /// Enable protection for region 64. Write '0' has no effect. + REGION64: u1 = 0, + /// Enable protection for region 65. Write '0' has no effect. + REGION65: u1 = 0, + /// Enable protection for region 66. Write '0' has no effect. + REGION66: u1 = 0, + /// Enable protection for region 67. Write '0' has no effect. + REGION67: u1 = 0, + /// Enable protection for region 68. Write '0' has no effect. + REGION68: u1 = 0, + /// Enable protection for region 69. Write '0' has no effect. + REGION69: u1 = 0, + /// Enable protection for region 70. Write '0' has no effect. + REGION70: u1 = 0, + /// Enable protection for region 71. Write '0' has no effect. + REGION71: u1 = 0, + /// Enable protection for region 72. Write '0' has no effect. + REGION72: u1 = 0, + /// Enable protection for region 73. Write '0' has no effect. + REGION73: u1 = 0, + /// Enable protection for region 74. Write '0' has no effect. + REGION74: u1 = 0, + /// Enable protection for region 75. Write '0' has no effect. + REGION75: u1 = 0, + /// Enable protection for region 76. Write '0' has no effect. + REGION76: u1 = 0, + /// Enable protection for region 77. Write '0' has no effect. + REGION77: u1 = 0, + /// Enable protection for region 78. Write '0' has no effect. + REGION78: u1 = 0, + /// Enable protection for region 79. Write '0' has no effect. + REGION79: u1 = 0, + /// Enable protection for region 80. Write '0' has no effect. + REGION80: u1 = 0, + /// Enable protection for region 81. Write '0' has no effect. + REGION81: u1 = 0, + /// Enable protection for region 82. Write '0' has no effect. + REGION82: u1 = 0, + /// Enable protection for region 83. Write '0' has no effect. + REGION83: u1 = 0, + /// Enable protection for region 84. Write '0' has no effect. + REGION84: u1 = 0, + /// Enable protection for region 85. Write '0' has no effect. + REGION85: u1 = 0, + /// Enable protection for region 86. Write '0' has no effect. + REGION86: u1 = 0, + /// Enable protection for region 87. Write '0' has no effect. + REGION87: u1 = 0, + /// Enable protection for region 88. Write '0' has no effect. + REGION88: u1 = 0, + /// Enable protection for region 89. Write '0' has no effect. + REGION89: u1 = 0, + /// Enable protection for region 90. Write '0' has no effect. + REGION90: u1 = 0, + /// Enable protection for region 91. Write '0' has no effect. + REGION91: u1 = 0, + /// Enable protection for region 92. Write '0' has no effect. + REGION92: u1 = 0, + /// Enable protection for region 93. Write '0' has no effect. + REGION93: u1 = 0, + /// Enable protection for region 94. Write '0' has no effect. + REGION94: u1 = 0, + /// Enable protection for region 95. Write '0' has no effect. + REGION95: u1 = 0, + }); + + /// Block protect configuration register 3 + pub const CONFIG3 = mmio(Address + 0x00000614, 32, packed struct { + /// Enable protection for region 96. Write '0' has no effect. + REGION96: u1 = 0, + /// Enable protection for region 97. Write '0' has no effect. + REGION97: u1 = 0, + /// Enable protection for region 98. Write '0' has no effect. + REGION98: u1 = 0, + /// Enable protection for region 99. Write '0' has no effect. + REGION99: u1 = 0, + /// Enable protection for region 100. Write '0' has no effect. + REGION100: u1 = 0, + /// Enable protection for region 101. Write '0' has no effect. + REGION101: u1 = 0, + /// Enable protection for region 102. Write '0' has no effect. + REGION102: u1 = 0, + /// Enable protection for region 103. Write '0' has no effect. + REGION103: u1 = 0, + /// Enable protection for region 104. Write '0' has no effect. + REGION104: u1 = 0, + /// Enable protection for region 105. Write '0' has no effect. + REGION105: u1 = 0, + /// Enable protection for region 106. Write '0' has no effect. + REGION106: u1 = 0, + /// Enable protection for region 107. Write '0' has no effect. + REGION107: u1 = 0, + /// Enable protection for region 108. Write '0' has no effect. + REGION108: u1 = 0, + /// Enable protection for region 109. Write '0' has no effect. + REGION109: u1 = 0, + /// Enable protection for region 110. Write '0' has no effect. + REGION110: u1 = 0, + /// Enable protection for region 111. Write '0' has no effect. + REGION111: u1 = 0, + /// Enable protection for region 112. Write '0' has no effect. + REGION112: u1 = 0, + /// Enable protection for region 113. Write '0' has no effect. + REGION113: u1 = 0, + /// Enable protection for region 114. Write '0' has no effect. + REGION114: u1 = 0, + /// Enable protection for region 115. Write '0' has no effect. + REGION115: u1 = 0, + /// Enable protection for region 116. Write '0' has no effect. + REGION116: u1 = 0, + /// Enable protection for region 117. Write '0' has no effect. + REGION117: u1 = 0, + /// Enable protection for region 118. Write '0' has no effect. + REGION118: u1 = 0, + /// Enable protection for region 119. Write '0' has no effect. + REGION119: u1 = 0, + /// Enable protection for region 120. Write '0' has no effect. + REGION120: u1 = 0, + /// Enable protection for region 121. Write '0' has no effect. + REGION121: u1 = 0, + /// Enable protection for region 122. Write '0' has no effect. + REGION122: u1 = 0, + /// Enable protection for region 123. Write '0' has no effect. + REGION123: u1 = 0, + /// Enable protection for region 124. Write '0' has no effect. + REGION124: u1 = 0, + /// Enable protection for region 125. Write '0' has no effect. + REGION125: u1 = 0, + /// Enable protection for region 126. Write '0' has no effect. + REGION126: u1 = 0, + /// Enable protection for region 127. Write '0' has no effect. + REGION127: u1 = 0, + }); +}; + +/// Power control +pub const POWER = extern struct { + pub const Address: u32 = 0x40000000; + + /// Enable constant latency mode + pub const TASKS_CONSTLAT = @intToPtr(*volatile u32, Address + 0x00000078); + + /// Enable low power mode (variable latency) + pub const TASKS_LOWPWR = @intToPtr(*volatile u32, Address + 0x0000007c); + + /// Power failure warning + pub const EVENTS_POFWARN = @intToPtr(*volatile u32, Address + 0x00000108); + + /// CPU entered WFI/WFE sleep + pub const EVENTS_SLEEPENTER = @intToPtr(*volatile u32, Address + 0x00000114); + + /// CPU exited WFI/WFE sleep + pub const EVENTS_SLEEPEXIT = @intToPtr(*volatile u32, Address + 0x00000118); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for POFWARN event + POFWARN: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + /// Write '1' to Enable interrupt for SLEEPENTER event + SLEEPENTER: u1 = 0, + /// Write '1' to Enable interrupt for SLEEPEXIT event + SLEEPEXIT: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for POFWARN event + POFWARN: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + /// Write '1' to Disable interrupt for SLEEPENTER event + SLEEPENTER: u1 = 0, + /// Write '1' to Disable interrupt for SLEEPEXIT event + SLEEPEXIT: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Reset reason + pub const RESETREAS = mmio(Address + 0x00000400, 32, packed struct { + /// Reset from pin-reset detected + RESETPIN: u1 = 0, + /// Reset from watchdog detected + DOG: u1 = 0, + /// Reset from soft reset detected + SREQ: u1 = 0, + /// Reset from CPU lock-up detected + LOCKUP: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Reset due to wake up from System OFF mode when wakeup is triggered from + /// DETECT signal from GPIO + OFF: u1 = 0, + /// Reset due to wake up from System OFF mode when wakeup is triggered from + /// ANADETECT signal from LPCOMP + LPCOMP: u1 = 0, + /// Reset due to wake up from System OFF mode when wakeup is triggered from + /// entering into debug interface mode + DIF: u1 = 0, + /// Reset due to wake up from System OFF mode by NFC field detect + NFC: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Deprecated register - RAM status register + pub const RAMSTATUS = mmio(Address + 0x00000428, 32, packed struct { + /// RAM block 0 is on or off/powering up + RAMBLOCK0: u1 = 0, + /// RAM block 1 is on or off/powering up + RAMBLOCK1: u1 = 0, + /// RAM block 2 is on or off/powering up + RAMBLOCK2: u1 = 0, + /// RAM block 3 is on or off/powering up + RAMBLOCK3: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// System OFF register + pub const SYSTEMOFF = mmio(Address + 0x00000500, 32, packed struct { + /// Enable System OFF mode + SYSTEMOFF: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Power failure comparator configuration + pub const POFCON = mmio(Address + 0x00000510, 32, packed struct { + /// Enable or disable power failure comparator + POF: u1 = 0, + /// Power failure comparator threshold setting + THRESHOLD: u4 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// General purpose retention register + pub const GPREGRET = mmio(Address + 0x0000051c, 32, packed struct { + /// General purpose retention register + GPREGRET: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// General purpose retention register + pub const GPREGRET2 = mmio(Address + 0x00000520, 32, packed struct { + /// General purpose retention register + GPREGRET: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Deprecated register - RAM on/off register (this register is retained) + pub const RAMON = mmio(Address + 0x00000524, 32, packed struct { + /// Keep RAM block 0 on or off in system ON Mode + ONRAM0: u1 = 0, + /// Keep RAM block 1 on or off in system ON Mode + ONRAM1: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Keep retention on RAM block 0 when RAM block is switched off + OFFRAM0: u1 = 0, + /// Keep retention on RAM block 1 when RAM block is switched off + OFFRAM1: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Deprecated register - RAM on/off register (this register is retained) + pub const RAMONB = mmio(Address + 0x00000554, 32, packed struct { + /// Keep RAM block 2 on or off in system ON Mode + ONRAM2: u1 = 0, + /// Keep RAM block 3 on or off in system ON Mode + ONRAM3: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Keep retention on RAM block 2 when RAM block is switched off + OFFRAM2: u1 = 0, + /// Keep retention on RAM block 3 when RAM block is switched off + OFFRAM3: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// DC/DC enable register + pub const DCDCEN = mmio(Address + 0x00000578, 32, packed struct { + /// Enable or disable DC/DC converter + DCDCEN: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// Clock control +pub const CLOCK = extern struct { + pub const Address: u32 = 0x40000000; + + /// Start HFCLK crystal oscillator + pub const TASKS_HFCLKSTART = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop HFCLK crystal oscillator + pub const TASKS_HFCLKSTOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Start LFCLK source + pub const TASKS_LFCLKSTART = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Stop LFCLK source + pub const TASKS_LFCLKSTOP = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Start calibration of LFRC oscillator + pub const TASKS_CAL = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Start calibration timer + pub const TASKS_CTSTART = @intToPtr(*volatile u32, Address + 0x00000014); + + /// Stop calibration timer + pub const TASKS_CTSTOP = @intToPtr(*volatile u32, Address + 0x00000018); + + /// HFCLK oscillator started + pub const EVENTS_HFCLKSTARTED = @intToPtr(*volatile u32, Address + 0x00000100); + + /// LFCLK started + pub const EVENTS_LFCLKSTARTED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Calibration of LFCLK RC oscillator complete event + pub const EVENTS_DONE = @intToPtr(*volatile u32, Address + 0x0000010c); + + /// Calibration timer timeout + pub const EVENTS_CTTO = @intToPtr(*volatile u32, Address + 0x00000110); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for HFCLKSTARTED event + HFCLKSTARTED: u1 = 0, + /// Write '1' to Enable interrupt for LFCLKSTARTED event + LFCLKSTARTED: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for DONE event + DONE: u1 = 0, + /// Write '1' to Enable interrupt for CTTO event + CTTO: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for HFCLKSTARTED event + HFCLKSTARTED: u1 = 0, + /// Write '1' to Disable interrupt for LFCLKSTARTED event + LFCLKSTARTED: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for DONE event + DONE: u1 = 0, + /// Write '1' to Disable interrupt for CTTO event + CTTO: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Status indicating that HFCLKSTART task has been triggered + pub const HFCLKRUN = mmio(Address + 0x00000408, 32, packed struct { + /// HFCLKSTART task triggered or not + STATUS: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// HFCLK status + pub const HFCLKSTAT = mmio(Address + 0x0000040c, 32, packed struct { + /// Source of HFCLK + SRC: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// HFCLK state + STATE: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Status indicating that LFCLKSTART task has been triggered + pub const LFCLKRUN = mmio(Address + 0x00000414, 32, packed struct { + /// LFCLKSTART task triggered or not + STATUS: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// LFCLK status + pub const LFCLKSTAT = mmio(Address + 0x00000418, 32, packed struct { + /// Source of LFCLK + SRC: u2 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// LFCLK state + STATE: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Copy of LFCLKSRC register, set when LFCLKSTART task was triggered + pub const LFCLKSRCCOPY = mmio(Address + 0x0000041c, 32, packed struct { + /// Clock source + SRC: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Clock source for the LFCLK + pub const LFCLKSRC = mmio(Address + 0x00000518, 32, packed struct { + /// Clock source + SRC: u2 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Enable or disable bypass of LFCLK crystal oscillator with external clock + /// source + BYPASS: u1 = 0, + /// Enable or disable external source for LFCLK + EXTERNAL: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Calibration timer interval + pub const CTIV = mmio(Address + 0x00000538, 32, packed struct { + /// Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds + /// to 31.75 seconds. + CTIV: u7 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Clocking options for the Trace Port debug interface + pub const TRACECONFIG = mmio(Address + 0x0000055c, 32, packed struct { + /// Speed of Trace Port clock. Note that the TRACECLK pin will output this clock + /// divided by two. + TRACEPORTSPEED: u2 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Pin multiplexing of trace signals. + TRACEMUX: u2 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// 2.4 GHz Radio +pub const RADIO = extern struct { + pub const Address: u32 = 0x40001000; + + /// Enable RADIO in TX mode + pub const TASKS_TXEN = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Enable RADIO in RX mode + pub const TASKS_RXEN = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Start RADIO + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Stop RADIO + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Disable RADIO + pub const TASKS_DISABLE = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Start the RSSI and take one single sample of the receive signal strength. + pub const TASKS_RSSISTART = @intToPtr(*volatile u32, Address + 0x00000014); + + /// Stop the RSSI measurement + pub const TASKS_RSSISTOP = @intToPtr(*volatile u32, Address + 0x00000018); + + /// Start the bit counter + pub const TASKS_BCSTART = @intToPtr(*volatile u32, Address + 0x0000001c); + + /// Stop the bit counter + pub const TASKS_BCSTOP = @intToPtr(*volatile u32, Address + 0x00000020); + + /// RADIO has ramped up and is ready to be started + pub const EVENTS_READY = @intToPtr(*volatile u32, Address + 0x00000100); + + /// Address sent or received + pub const EVENTS_ADDRESS = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Packet payload sent or received + pub const EVENTS_PAYLOAD = @intToPtr(*volatile u32, Address + 0x00000108); + + /// Packet sent or received + pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x0000010c); + + /// RADIO has been disabled + pub const EVENTS_DISABLED = @intToPtr(*volatile u32, Address + 0x00000110); + + /// A device address match occurred on the last received packet + pub const EVENTS_DEVMATCH = @intToPtr(*volatile u32, Address + 0x00000114); + + /// No device address match occurred on the last received packet + pub const EVENTS_DEVMISS = @intToPtr(*volatile u32, Address + 0x00000118); + + /// Sampling of receive signal strength complete. + pub const EVENTS_RSSIEND = @intToPtr(*volatile u32, Address + 0x0000011c); + + /// Bit counter reached bit count value. + pub const EVENTS_BCMATCH = @intToPtr(*volatile u32, Address + 0x00000128); + + /// Packet received with CRC ok + pub const EVENTS_CRCOK = @intToPtr(*volatile u32, Address + 0x00000130); + + /// Packet received with CRC error + pub const EVENTS_CRCERROR = @intToPtr(*volatile u32, Address + 0x00000134); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between READY event and START task + READY_START: u1 = 0, + /// Shortcut between END event and DISABLE task + END_DISABLE: u1 = 0, + /// Shortcut between DISABLED event and TXEN task + DISABLED_TXEN: u1 = 0, + /// Shortcut between DISABLED event and RXEN task + DISABLED_RXEN: u1 = 0, + /// Shortcut between ADDRESS event and RSSISTART task + ADDRESS_RSSISTART: u1 = 0, + /// Shortcut between END event and START task + END_START: u1 = 0, + /// Shortcut between ADDRESS event and BCSTART task + ADDRESS_BCSTART: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between DISABLED event and RSSISTOP task + DISABLED_RSSISTOP: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for READY event + READY: u1 = 0, + /// Write '1' to Enable interrupt for ADDRESS event + ADDRESS: u1 = 0, + /// Write '1' to Enable interrupt for PAYLOAD event + PAYLOAD: u1 = 0, + /// Write '1' to Enable interrupt for END event + END: u1 = 0, + /// Write '1' to Enable interrupt for DISABLED event + DISABLED: u1 = 0, + /// Write '1' to Enable interrupt for DEVMATCH event + DEVMATCH: u1 = 0, + /// Write '1' to Enable interrupt for DEVMISS event + DEVMISS: u1 = 0, + /// Write '1' to Enable interrupt for RSSIEND event + RSSIEND: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for BCMATCH event + BCMATCH: u1 = 0, + reserved3: u1 = 0, + /// Write '1' to Enable interrupt for CRCOK event + CRCOK: u1 = 0, + /// Write '1' to Enable interrupt for CRCERROR event + CRCERROR: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for READY event + READY: u1 = 0, + /// Write '1' to Disable interrupt for ADDRESS event + ADDRESS: u1 = 0, + /// Write '1' to Disable interrupt for PAYLOAD event + PAYLOAD: u1 = 0, + /// Write '1' to Disable interrupt for END event + END: u1 = 0, + /// Write '1' to Disable interrupt for DISABLED event + DISABLED: u1 = 0, + /// Write '1' to Disable interrupt for DEVMATCH event + DEVMATCH: u1 = 0, + /// Write '1' to Disable interrupt for DEVMISS event + DEVMISS: u1 = 0, + /// Write '1' to Disable interrupt for RSSIEND event + RSSIEND: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for BCMATCH event + BCMATCH: u1 = 0, + reserved3: u1 = 0, + /// Write '1' to Disable interrupt for CRCOK event + CRCOK: u1 = 0, + /// Write '1' to Disable interrupt for CRCERROR event + CRCERROR: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// CRC status + pub const CRCSTATUS = mmio(Address + 0x00000400, 32, packed struct { + /// CRC status of packet received + CRCSTATUS: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Received address + pub const RXMATCH = mmio(Address + 0x00000408, 32, packed struct { + /// Received address + RXMATCH: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// CRC field of previously received packet + pub const RXCRC = mmio(Address + 0x0000040c, 32, packed struct { + /// CRC field of previously received packet + RXCRC: u24 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Device address match index + pub const DAI = mmio(Address + 0x00000410, 32, packed struct { + /// Device address match index + DAI: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Packet pointer + pub const PACKETPTR = @intToPtr(*volatile u32, Address + 0x00000504); + + /// Frequency + pub const FREQUENCY = mmio(Address + 0x00000508, 32, packed struct { + /// Radio channel frequency + FREQUENCY: u7 = 0, + reserved1: u1 = 0, + /// Channel map selection. + MAP: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Output power + pub const TXPOWER = mmio(Address + 0x0000050c, 32, packed struct { + /// RADIO output power. + TXPOWER: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Data rate and modulation + pub const MODE = mmio(Address + 0x00000510, 32, packed struct { + /// Radio data rate and modulation setting. The radio supports Frequency-shift + /// Keying (FSK) modulation. + MODE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Packet configuration register 0 + pub const PCNF0 = mmio(Address + 0x00000514, 32, packed struct { + /// Length on air of LENGTH field in number of bits. + LFLEN: u4 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Length on air of S0 field in number of bytes. + S0LEN: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + /// Length on air of S1 field in number of bits. + S1LEN: u4 = 0, + /// Include or exclude S1 field in RAM + S1INCL: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + /// Length of preamble on air. Decision point: TASKS_START task + PLEN: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Packet configuration register 1 + pub const PCNF1 = mmio(Address + 0x00000518, 32, packed struct { + /// Maximum length of packet payload. If the packet payload is larger than + /// MAXLEN, the radio will truncate the payload to MAXLEN. + MAXLEN: u8 = 0, + /// Static length in number of bytes + STATLEN: u8 = 0, + /// Base address length in number of bytes + BALEN: u3 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// On air endianness of packet, this applies to the S0, LENGTH, S1 and the + /// PAYLOAD fields. + ENDIAN: u1 = 0, + /// Enable or disable packet whitening + WHITEEN: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Base address 0 + pub const BASE0 = @intToPtr(*volatile u32, Address + 0x0000051c); + + /// Base address 1 + pub const BASE1 = @intToPtr(*volatile u32, Address + 0x00000520); + + /// Prefixes bytes for logical addresses 0-3 + pub const PREFIX0 = mmio(Address + 0x00000524, 32, packed struct { + /// Address prefix 0. + AP0: u8 = 0, + /// Address prefix 1. + AP1: u8 = 0, + /// Address prefix 2. + AP2: u8 = 0, + /// Address prefix 3. + AP3: u8 = 0, + }); + + /// Prefixes bytes for logical addresses 4-7 + pub const PREFIX1 = mmio(Address + 0x00000528, 32, packed struct { + /// Address prefix 4. + AP4: u8 = 0, + /// Address prefix 5. + AP5: u8 = 0, + /// Address prefix 6. + AP6: u8 = 0, + /// Address prefix 7. + AP7: u8 = 0, + }); + + /// Transmit address select + pub const TXADDRESS = mmio(Address + 0x0000052c, 32, packed struct { + /// Transmit address select + TXADDRESS: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Receive address select + pub const RXADDRESSES = mmio(Address + 0x00000530, 32, packed struct { + /// Enable or disable reception on logical address 0. + ADDR0: u1 = 0, + /// Enable or disable reception on logical address 1. + ADDR1: u1 = 0, + /// Enable or disable reception on logical address 2. + ADDR2: u1 = 0, + /// Enable or disable reception on logical address 3. + ADDR3: u1 = 0, + /// Enable or disable reception on logical address 4. + ADDR4: u1 = 0, + /// Enable or disable reception on logical address 5. + ADDR5: u1 = 0, + /// Enable or disable reception on logical address 6. + ADDR6: u1 = 0, + /// Enable or disable reception on logical address 7. + ADDR7: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// CRC configuration + pub const CRCCNF = mmio(Address + 0x00000534, 32, packed struct { + /// CRC length in number of bytes. + LEN: u2 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Include or exclude packet address field out of CRC calculation. + SKIPADDR: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// CRC polynomial + pub const CRCPOLY = mmio(Address + 0x00000538, 32, packed struct { + /// CRC polynomial + CRCPOLY: u24 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// CRC initial value + pub const CRCINIT = mmio(Address + 0x0000053c, 32, packed struct { + /// CRC initial value + CRCINIT: u24 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Unspecified + pub const UNUSED0 = @intToPtr(*volatile u32, Address + 0x00000540); + + /// Inter Frame Spacing in us + pub const TIFS = mmio(Address + 0x00000544, 32, packed struct { + /// Inter Frame Spacing in us + TIFS: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// RSSI sample + pub const RSSISAMPLE = mmio(Address + 0x00000548, 32, packed struct { + /// RSSI sample + RSSISAMPLE: u7 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Current radio state + pub const STATE = mmio(Address + 0x00000550, 32, packed struct { + /// Current radio state + STATE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Data whitening initial value + pub const DATAWHITEIV = mmio(Address + 0x00000554, 32, packed struct { + /// Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it + /// has no effect, and it will always be read back and used by the device as + /// '1'. + DATAWHITEIV: u7 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Bit counter compare + pub const BCC = @intToPtr(*volatile u32, Address + 0x00000560); + + /// Device address match configuration + pub const DACNF = mmio(Address + 0x00000640, 32, packed struct { + /// Enable or disable device address matching using device address 0 + ENA0: u1 = 0, + /// Enable or disable device address matching using device address 1 + ENA1: u1 = 0, + /// Enable or disable device address matching using device address 2 + ENA2: u1 = 0, + /// Enable or disable device address matching using device address 3 + ENA3: u1 = 0, + /// Enable or disable device address matching using device address 4 + ENA4: u1 = 0, + /// Enable or disable device address matching using device address 5 + ENA5: u1 = 0, + /// Enable or disable device address matching using device address 6 + ENA6: u1 = 0, + /// Enable or disable device address matching using device address 7 + ENA7: u1 = 0, + /// TxAdd for device address 0 + TXADD0: u1 = 0, + /// TxAdd for device address 1 + TXADD1: u1 = 0, + /// TxAdd for device address 2 + TXADD2: u1 = 0, + /// TxAdd for device address 3 + TXADD3: u1 = 0, + /// TxAdd for device address 4 + TXADD4: u1 = 0, + /// TxAdd for device address 5 + TXADD5: u1 = 0, + /// TxAdd for device address 6 + TXADD6: u1 = 0, + /// TxAdd for device address 7 + TXADD7: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Radio mode configuration register 0 + pub const MODECNF0 = mmio(Address + 0x00000650, 32, packed struct { + /// Radio ramp-up time + RU: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Default TX value + DTX: u2 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Peripheral power control + pub const POWER = mmio(Address + 0x00000ffc, 32, packed struct { + /// Peripheral power control. The peripheral and its registers will be reset to + /// its initial state by switching the peripheral off and then back on again. + POWER: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Device address base segment 0 + pub const DAB = @intToPtr(*volatile [8]u32, Address + 0x00000600); + /// Description collection[0]: Device address prefix 0 + pub const DAP = @intToPtr(*volatile [8]MMIO(32, packed struct { + /// Device address prefix 0 + DAP: u16 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }), Address + 0x00000620); +}; + +/// UART with EasyDMA +pub const UARTE0 = extern struct { + pub const Address: u32 = 0x40002000; + + /// Start UART receiver + pub const TASKS_STARTRX = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop UART receiver + pub const TASKS_STOPRX = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Start UART transmitter + pub const TASKS_STARTTX = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Stop UART transmitter + pub const TASKS_STOPTX = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Flush RX FIFO into RX buffer + pub const TASKS_FLUSHRX = @intToPtr(*volatile u32, Address + 0x0000002c); + + /// CTS is activated (set low). Clear To Send. + pub const EVENTS_CTS = @intToPtr(*volatile u32, Address + 0x00000100); + + /// CTS is deactivated (set high). Not Clear To Send. + pub const EVENTS_NCTS = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Data received in RXD (but potentially not yet transferred to Data RAM) + pub const EVENTS_RXDRDY = @intToPtr(*volatile u32, Address + 0x00000108); + + /// Receive buffer is filled up + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x00000110); + + /// Data sent from TXD + pub const EVENTS_TXDRDY = @intToPtr(*volatile u32, Address + 0x0000011c); + + /// Last TX byte transmitted + pub const EVENTS_ENDTX = @intToPtr(*volatile u32, Address + 0x00000120); + + /// Error detected + pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); + + /// Receiver timeout + pub const EVENTS_RXTO = @intToPtr(*volatile u32, Address + 0x00000144); + + /// UART receiver has started + pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, Address + 0x0000014c); + + /// UART transmitter has started + pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, Address + 0x00000150); + + /// Transmitter stopped + pub const EVENTS_TXSTOPPED = @intToPtr(*volatile u32, Address + 0x00000158); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between ENDRX event and STARTRX task + ENDRX_STARTRX: u1 = 0, + /// Shortcut between ENDRX event and STOPRX task + ENDRX_STOPRX: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + /// Enable or disable interrupt for CTS event + CTS: u1 = 0, + /// Enable or disable interrupt for NCTS event + NCTS: u1 = 0, + /// Enable or disable interrupt for RXDRDY event + RXDRDY: u1 = 0, + reserved1: u1 = 0, + /// Enable or disable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Enable or disable interrupt for TXDRDY event + TXDRDY: u1 = 0, + /// Enable or disable interrupt for ENDTX event + ENDTX: u1 = 0, + /// Enable or disable interrupt for ERROR event + ERROR: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + /// Enable or disable interrupt for RXTO event + RXTO: u1 = 0, + reserved11: u1 = 0, + /// Enable or disable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Enable or disable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved12: u1 = 0, + /// Enable or disable interrupt for TXSTOPPED event + TXSTOPPED: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for CTS event + CTS: u1 = 0, + /// Write '1' to Enable interrupt for NCTS event + NCTS: u1 = 0, + /// Write '1' to Enable interrupt for RXDRDY event + RXDRDY: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Enable interrupt for TXDRDY event + TXDRDY: u1 = 0, + /// Write '1' to Enable interrupt for ENDTX event + ENDTX: u1 = 0, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Enable interrupt for RXTO event + RXTO: u1 = 0, + reserved11: u1 = 0, + /// Write '1' to Enable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Write '1' to Enable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved12: u1 = 0, + /// Write '1' to Enable interrupt for TXSTOPPED event + TXSTOPPED: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for CTS event + CTS: u1 = 0, + /// Write '1' to Disable interrupt for NCTS event + NCTS: u1 = 0, + /// Write '1' to Disable interrupt for RXDRDY event + RXDRDY: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Disable interrupt for TXDRDY event + TXDRDY: u1 = 0, + /// Write '1' to Disable interrupt for ENDTX event + ENDTX: u1 = 0, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Disable interrupt for RXTO event + RXTO: u1 = 0, + reserved11: u1 = 0, + /// Write '1' to Disable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Write '1' to Disable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved12: u1 = 0, + /// Write '1' to Disable interrupt for TXSTOPPED event + TXSTOPPED: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Error source + pub const ERRORSRC = mmio(Address + 0x00000480, 32, packed struct { + /// Overrun error + OVERRUN: u1 = 0, + /// Parity error + PARITY: u1 = 0, + /// Framing error occurred + FRAMING: u1 = 0, + /// Break condition + BREAK: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable UART + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable UARTE + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Baud rate. Accuracy depends on the HFCLK source selected. + pub const BAUDRATE = @intToPtr(*volatile u32, Address + 0x00000524); + + /// Configuration of parity and hardware flow control + pub const CONFIG = mmio(Address + 0x0000056c, 32, packed struct { + /// Hardware flow control + HWFC: u1 = 0, + /// Parity + PARITY: u3 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + pub const PSEL = struct { + + /// Pin select for RTS signal + pub const RTS = mmio(Address + 0x00000000, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for TXD signal + pub const TXD = mmio(Address + 0x00000004, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for CTS signal + pub const CTS = mmio(Address + 0x00000008, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for RXD signal + pub const RXD = mmio(Address + 0x0000000c, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + }; + + pub const RXD = struct { + + /// Data pointer + pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Maximum number of bytes in receive buffer + pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// Maximum number of bytes in receive buffer + MAXCNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Number of bytes transferred in the last transaction + pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + /// Number of bytes transferred in the last transaction + AMOUNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; + + pub const TXD = struct { + + /// Data pointer + pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Maximum number of bytes in transmit buffer + pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// Maximum number of bytes in transmit buffer + MAXCNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Number of bytes transferred in the last transaction + pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + /// Number of bytes transferred in the last transaction + AMOUNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; +}; + +/// Universal Asynchronous Receiver/Transmitter +pub const UART0 = extern struct { + pub const Address: u32 = 0x40002000; + + /// Start UART receiver + pub const TASKS_STARTRX = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop UART receiver + pub const TASKS_STOPRX = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Start UART transmitter + pub const TASKS_STARTTX = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Stop UART transmitter + pub const TASKS_STOPTX = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Suspend UART + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); + + /// CTS is activated (set low). Clear To Send. + pub const EVENTS_CTS = @intToPtr(*volatile u32, Address + 0x00000100); + + /// CTS is deactivated (set high). Not Clear To Send. + pub const EVENTS_NCTS = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Data received in RXD + pub const EVENTS_RXDRDY = @intToPtr(*volatile u32, Address + 0x00000108); + + /// Data sent from TXD + pub const EVENTS_TXDRDY = @intToPtr(*volatile u32, Address + 0x0000011c); + + /// Error detected + pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); + + /// Receiver timeout + pub const EVENTS_RXTO = @intToPtr(*volatile u32, Address + 0x00000144); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between CTS event and STARTRX task + CTS_STARTRX: u1 = 0, + /// Shortcut between NCTS event and STOPRX task + NCTS_STOPRX: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for CTS event + CTS: u1 = 0, + /// Write '1' to Enable interrupt for NCTS event + NCTS: u1 = 0, + /// Write '1' to Enable interrupt for RXDRDY event + RXDRDY: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for TXDRDY event + TXDRDY: u1 = 0, + reserved5: u1 = 0, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + /// Write '1' to Enable interrupt for RXTO event + RXTO: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for CTS event + CTS: u1 = 0, + /// Write '1' to Disable interrupt for NCTS event + NCTS: u1 = 0, + /// Write '1' to Disable interrupt for RXDRDY event + RXDRDY: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for TXDRDY event + TXDRDY: u1 = 0, + reserved5: u1 = 0, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + /// Write '1' to Disable interrupt for RXTO event + RXTO: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Error source + pub const ERRORSRC = mmio(Address + 0x00000480, 32, packed struct { + /// Overrun error + OVERRUN: u1 = 0, + /// Parity error + PARITY: u1 = 0, + /// Framing error occurred + FRAMING: u1 = 0, + /// Break condition + BREAK: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable UART + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable UART + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Pin select for RTS + pub const PSELRTS = @intToPtr(*volatile u32, Address + 0x00000508); + + /// Pin select for TXD + pub const PSELTXD = @intToPtr(*volatile u32, Address + 0x0000050c); + + /// Pin select for CTS + pub const PSELCTS = @intToPtr(*volatile u32, Address + 0x00000510); + + /// Pin select for RXD + pub const PSELRXD = @intToPtr(*volatile u32, Address + 0x00000514); + + /// RXD register + pub const RXD = mmio(Address + 0x00000518, 32, packed struct { + /// RX data received in previous transfers, double buffered + RXD: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// TXD register + pub const TXD = mmio(Address + 0x0000051c, 32, packed struct { + /// TX data to be transferred + TXD: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Baud rate + pub const BAUDRATE = @intToPtr(*volatile u32, Address + 0x00000524); + + /// Configuration of parity and hardware flow control + pub const CONFIG = mmio(Address + 0x0000056c, 32, packed struct { + /// Hardware flow control + HWFC: u1 = 0, + /// Parity + PARITY: u3 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// Serial Peripheral Interface Master with EasyDMA 0 +pub const SPIM0 = extern struct { + pub const Address: u32 = 0x40003000; + + /// Start SPI transaction + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Stop SPI transaction + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); + + /// Suspend SPI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); + + /// Resume SPI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); + + /// SPI transaction has stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// End of RXD buffer reached + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x00000110); + + /// End of RXD buffer and TXD buffer reached + pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000118); + + /// End of TXD buffer reached + pub const EVENTS_ENDTX = @intToPtr(*volatile u32, Address + 0x00000120); + + /// Transaction started + pub const EVENTS_STARTED = @intToPtr(*volatile u32, Address + 0x0000014c); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between END event and START task + END_START: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Enable interrupt for END event + END: u1 = 0, + reserved5: u1 = 0, + /// Write '1' to Enable interrupt for ENDTX event + ENDTX: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + /// Write '1' to Enable interrupt for STARTED event + STARTED: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Disable interrupt for END event + END: u1 = 0, + reserved5: u1 = 0, + /// Write '1' to Disable interrupt for ENDTX event + ENDTX: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + /// Write '1' to Disable interrupt for STARTED event + STARTED: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable SPIM + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable SPIM + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// SPI frequency. Accuracy depends on the HFCLK source selected. + pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); + + /// Configuration register + pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { + /// Bit order + ORDER: u1 = 0, + /// Serial clock (SCK) phase + CPHA: u1 = 0, + /// Serial clock (SCK) polarity + CPOL: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Over-read character. Character clocked out in case and over-read of the TXD + /// buffer. + pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { + /// Over-read character. Character clocked out in case and over-read of the TXD + /// buffer. + ORC: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + pub const PSEL = struct { + + /// Pin select for SCK + pub const SCK = mmio(Address + 0x00000000, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for MOSI signal + pub const MOSI = mmio(Address + 0x00000004, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for MISO signal + pub const MISO = mmio(Address + 0x00000008, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + }; + + pub const RXD = struct { + + /// Data pointer + pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Maximum number of bytes in receive buffer + pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// Maximum number of bytes in receive buffer + MAXCNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Number of bytes transferred in the last transaction + pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + /// Number of bytes transferred in the last transaction + AMOUNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// EasyDMA list type + pub const LIST = mmio(Address + 0x0000000c, 32, packed struct { + /// List type + LIST: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; + + pub const TXD = struct { + + /// Data pointer + pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Maximum number of bytes in transmit buffer + pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// Maximum number of bytes in transmit buffer + MAXCNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Number of bytes transferred in the last transaction + pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + /// Number of bytes transferred in the last transaction + AMOUNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// EasyDMA list type + pub const LIST = mmio(Address + 0x0000000c, 32, packed struct { + /// List type + LIST: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; +}; + +/// SPI Slave 0 +pub const SPIS0 = extern struct { + pub const Address: u32 = 0x40003000; + + /// Acquire SPI semaphore + pub const TASKS_ACQUIRE = @intToPtr(*volatile u32, Address + 0x00000024); + + /// Release SPI semaphore, enabling the SPI slave to acquire it + pub const TASKS_RELEASE = @intToPtr(*volatile u32, Address + 0x00000028); + + /// Granted transaction completed + pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000104); + + /// End of RXD buffer reached + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x00000110); + + /// Semaphore acquired + pub const EVENTS_ACQUIRED = @intToPtr(*volatile u32, Address + 0x00000128); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between END event and ACQUIRE task + END_ACQUIRE: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for END event + END: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Enable interrupt for ACQUIRED event + ACQUIRED: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for END event + END: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Disable interrupt for ACQUIRED event + ACQUIRED: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Semaphore status register + pub const SEMSTAT = mmio(Address + 0x00000400, 32, packed struct { + /// Semaphore status + SEMSTAT: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Status from last transaction + pub const STATUS = mmio(Address + 0x00000440, 32, packed struct { + /// TX buffer over-read detected, and prevented + OVERREAD: u1 = 0, + /// RX buffer overflow detected, and prevented + OVERFLOW: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable SPI slave + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable SPI slave + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration register + pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { + /// Bit order + ORDER: u1 = 0, + /// Serial clock (SCK) phase + CPHA: u1 = 0, + /// Serial clock (SCK) polarity + CPOL: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Default character. Character clocked out in case of an ignored transaction. + pub const DEF = mmio(Address + 0x0000055c, 32, packed struct { + /// Default character. Character clocked out in case of an ignored transaction. + DEF: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Over-read character + pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { + /// Over-read character. Character clocked out after an over-read of the + /// transmit buffer. + ORC: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + pub const PSEL = struct { + + /// Pin select for SCK + pub const SCK = mmio(Address + 0x00000000, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for MISO signal + pub const MISO = mmio(Address + 0x00000004, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for MOSI signal + pub const MOSI = mmio(Address + 0x00000008, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for CSN signal + pub const CSN = mmio(Address + 0x0000000c, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + }; + + pub const RXD = struct { + + /// RXD data pointer + pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Maximum number of bytes in receive buffer + pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// Maximum number of bytes in receive buffer + MAXCNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Number of bytes received in last granted transaction + pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + /// Number of bytes received in the last granted transaction + AMOUNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; + + pub const TXD = struct { + + /// TXD data pointer + pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Maximum number of bytes in transmit buffer + pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// Maximum number of bytes in transmit buffer + MAXCNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Number of bytes transmitted in last granted transaction + pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + /// Number of bytes transmitted in last granted transaction + AMOUNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; +}; + +/// I2C compatible Two-Wire Master Interface with EasyDMA 0 +pub const TWIM0 = extern struct { + pub const Address: u32 = 0x40003000; + + /// Start TWI receive sequence + pub const TASKS_STARTRX = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Start TWI transmit sequence + pub const TASKS_STARTTX = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Stop TWI transaction. Must be issued while the TWI master is not suspended. + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); + + /// Suspend TWI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); + + /// Resume TWI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); + + /// TWI stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// TWI error + pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); + + /// Last byte has been sent out after the SUSPEND task has been issued, TWI + /// traffic is now suspended. + pub const EVENTS_SUSPENDED = @intToPtr(*volatile u32, Address + 0x00000148); + + /// Receive sequence started + pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, Address + 0x0000014c); + + /// Transmit sequence started + pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, Address + 0x00000150); + + /// Byte boundary, starting to receive the last byte + pub const EVENTS_LASTRX = @intToPtr(*volatile u32, Address + 0x0000015c); + + /// Byte boundary, starting to transmit the last byte + pub const EVENTS_LASTTX = @intToPtr(*volatile u32, Address + 0x00000160); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between LASTTX event and STARTRX task + LASTTX_STARTRX: u1 = 0, + /// Shortcut between LASTTX event and SUSPEND task + LASTTX_SUSPEND: u1 = 0, + /// Shortcut between LASTTX event and STOP task + LASTTX_STOP: u1 = 0, + /// Shortcut between LASTRX event and STARTTX task + LASTRX_STARTTX: u1 = 0, + reserved8: u1 = 0, + /// Shortcut between LASTRX event and STOP task + LASTRX_STOP: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + reserved1: u1 = 0, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Enable or disable interrupt for ERROR event + ERROR: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + /// Enable or disable interrupt for SUSPENDED event + SUSPENDED: u1 = 0, + /// Enable or disable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Enable or disable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + /// Enable or disable interrupt for LASTRX event + LASTRX: u1 = 0, + /// Enable or disable interrupt for LASTTX event + LASTTX: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + /// Write '1' to Enable interrupt for SUSPENDED event + SUSPENDED: u1 = 0, + /// Write '1' to Enable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Write '1' to Enable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + /// Write '1' to Enable interrupt for LASTRX event + LASTRX: u1 = 0, + /// Write '1' to Enable interrupt for LASTTX event + LASTTX: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + /// Write '1' to Disable interrupt for SUSPENDED event + SUSPENDED: u1 = 0, + /// Write '1' to Disable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Write '1' to Disable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + /// Write '1' to Disable interrupt for LASTRX event + LASTRX: u1 = 0, + /// Write '1' to Disable interrupt for LASTTX event + LASTTX: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Error source + pub const ERRORSRC = mmio(Address + 0x000004c4, 32, packed struct { + /// Overrun error + OVERRUN: u1 = 0, + /// NACK received after sending the address (write '1' to clear) + ANACK: u1 = 0, + /// NACK received after sending a data byte (write '1' to clear) + DNACK: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable TWIM + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable TWIM + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// TWI frequency + pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); + + /// Address used in the TWI transfer + pub const ADDRESS = mmio(Address + 0x00000588, 32, packed struct { + /// Address used in the TWI transfer + ADDRESS: u7 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + pub const PSEL = struct { + + /// Pin select for SCL signal + pub const SCL = mmio(Address + 0x00000000, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for SDA signal + pub const SDA = mmio(Address + 0x00000004, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + }; + + pub const RXD = struct { + + /// Data pointer + pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Maximum number of bytes in receive buffer + pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// Maximum number of bytes in receive buffer + MAXCNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Number of bytes transferred in the last transaction + pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + /// Number of bytes transferred in the last transaction. In case of NACK error, + /// includes the NACK'ed byte. + AMOUNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// EasyDMA list type + pub const LIST = mmio(Address + 0x0000000c, 32, packed struct { + /// List type + LIST: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; + + pub const TXD = struct { + + /// Data pointer + pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Maximum number of bytes in transmit buffer + pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// Maximum number of bytes in transmit buffer + MAXCNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Number of bytes transferred in the last transaction + pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + /// Number of bytes transferred in the last transaction. In case of NACK error, + /// includes the NACK'ed byte. + AMOUNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// EasyDMA list type + pub const LIST = mmio(Address + 0x0000000c, 32, packed struct { + /// List type + LIST: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; +}; + +/// I2C compatible Two-Wire Slave Interface with EasyDMA 0 +pub const TWIS0 = extern struct { + pub const Address: u32 = 0x40003000; + + /// Stop TWI transaction + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); + + /// Suspend TWI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); + + /// Resume TWI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); + + /// Prepare the TWI slave to respond to a write command + pub const TASKS_PREPARERX = @intToPtr(*volatile u32, Address + 0x00000030); + + /// Prepare the TWI slave to respond to a read command + pub const TASKS_PREPARETX = @intToPtr(*volatile u32, Address + 0x00000034); + + /// TWI stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// TWI error + pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); + + /// Receive sequence started + pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, Address + 0x0000014c); + + /// Transmit sequence started + pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, Address + 0x00000150); + + /// Write command received + pub const EVENTS_WRITE = @intToPtr(*volatile u32, Address + 0x00000164); + + /// Read command received + pub const EVENTS_READ = @intToPtr(*volatile u32, Address + 0x00000168); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between WRITE event and SUSPEND task + WRITE_SUSPEND: u1 = 0, + /// Shortcut between READ event and SUSPEND task + READ_SUSPEND: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + reserved1: u1 = 0, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Enable or disable interrupt for ERROR event + ERROR: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + /// Enable or disable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Enable or disable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + /// Enable or disable interrupt for WRITE event + WRITE: u1 = 0, + /// Enable or disable interrupt for READ event + READ: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + /// Write '1' to Enable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Write '1' to Enable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + /// Write '1' to Enable interrupt for WRITE event + WRITE: u1 = 0, + /// Write '1' to Enable interrupt for READ event + READ: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + /// Write '1' to Disable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Write '1' to Disable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + /// Write '1' to Disable interrupt for WRITE event + WRITE: u1 = 0, + /// Write '1' to Disable interrupt for READ event + READ: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Error source + pub const ERRORSRC = mmio(Address + 0x000004d0, 32, packed struct { + /// RX buffer overflow detected, and prevented + OVERFLOW: u1 = 0, + reserved1: u1 = 0, + /// NACK sent after receiving a data byte + DNACK: u1 = 0, + /// TX buffer over-read detected, and prevented + OVERREAD: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Status register indicating which address had a match + pub const MATCH = mmio(Address + 0x000004d4, 32, packed struct { + /// Which of the addresses in {ADDRESS} matched the incoming address + MATCH: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable TWIS + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable TWIS + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration register for the address match mechanism + pub const CONFIG = mmio(Address + 0x00000594, 32, packed struct { + /// Enable or disable address matching on ADDRESS[0] + ADDRESS0: u1 = 0, + /// Enable or disable address matching on ADDRESS[1] + ADDRESS1: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Over-read character. Character sent out in case of an over-read of the + /// transmit buffer. + pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { + /// Over-read character. Character sent out in case of an over-read of the + /// transmit buffer. + ORC: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: TWI slave address 0 + pub const ADDRESS = @intToPtr(*volatile [2]MMIO(32, packed struct { + /// TWI slave address + ADDRESS: u7 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }), Address + 0x00000588); + + pub const PSEL = struct { + + /// Pin select for SCL signal + pub const SCL = mmio(Address + 0x00000000, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for SDA signal + pub const SDA = mmio(Address + 0x00000004, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + }; + + pub const RXD = struct { + + /// RXD Data pointer + pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Maximum number of bytes in RXD buffer + pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// Maximum number of bytes in RXD buffer + MAXCNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Number of bytes transferred in the last RXD transaction + pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + /// Number of bytes transferred in the last RXD transaction + AMOUNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; + + pub const TXD = struct { + + /// TXD Data pointer + pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Maximum number of bytes in TXD buffer + pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// Maximum number of bytes in TXD buffer + MAXCNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Number of bytes transferred in the last TXD transaction + pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + /// Number of bytes transferred in the last TXD transaction + AMOUNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; +}; + +/// Serial Peripheral Interface 0 +pub const SPI0 = extern struct { + pub const Address: u32 = 0x40003000; + + /// TXD byte sent and RXD byte received + pub const EVENTS_READY = @intToPtr(*volatile u32, Address + 0x00000108); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for READY event + READY: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for READY event + READY: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable SPI + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable SPI + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// RXD register + pub const RXD = mmio(Address + 0x00000518, 32, packed struct { + /// RX data received. Double buffered + RXD: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// TXD register + pub const TXD = mmio(Address + 0x0000051c, 32, packed struct { + /// TX data to send. Double buffered + TXD: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// SPI frequency + pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); + + /// Configuration register + pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { + /// Bit order + ORDER: u1 = 0, + /// Serial clock (SCK) phase + CPHA: u1 = 0, + /// Serial clock (SCK) polarity + CPOL: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + pub const PSEL = struct { + + /// Pin select for SCK + pub const SCK = mmio(Address + 0x00000000, 32, packed struct { + /// Pin number configuration for SPI SCK signal + PSELSCK: u32 = 0, + }); + + /// Pin select for MOSI + pub const MOSI = mmio(Address + 0x00000004, 32, packed struct { + /// Pin number configuration for SPI MOSI signal + PSELMOSI: u32 = 0, + }); + + /// Pin select for MISO + pub const MISO = mmio(Address + 0x00000008, 32, packed struct { + /// Pin number configuration for SPI MISO signal + PSELMISO: u32 = 0, + }); + }; +}; + +/// I2C compatible Two-Wire Interface 0 +pub const TWI0 = extern struct { + pub const Address: u32 = 0x40003000; + + /// Start TWI receive sequence + pub const TASKS_STARTRX = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Start TWI transmit sequence + pub const TASKS_STARTTX = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Stop TWI transaction + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); + + /// Suspend TWI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); + + /// Resume TWI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); + + /// TWI stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// TWI RXD byte received + pub const EVENTS_RXDREADY = @intToPtr(*volatile u32, Address + 0x00000108); + + /// TWI TXD byte sent + pub const EVENTS_TXDSENT = @intToPtr(*volatile u32, Address + 0x0000011c); + + /// TWI error + pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); + + /// TWI byte boundary, generated before each byte that is sent or received + pub const EVENTS_BB = @intToPtr(*volatile u32, Address + 0x00000138); + + /// TWI entered the suspended state + pub const EVENTS_SUSPENDED = @intToPtr(*volatile u32, Address + 0x00000148); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between BB event and SUSPEND task + BB_SUSPEND: u1 = 0, + /// Shortcut between BB event and STOP task + BB_STOP: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Write '1' to Enable interrupt for RXDREADY event + RXDREADY: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Enable interrupt for TXDSENT event + TXDSENT: u1 = 0, + reserved6: u1 = 0, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + /// Write '1' to Enable interrupt for BB event + BB: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + /// Write '1' to Enable interrupt for SUSPENDED event + SUSPENDED: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Write '1' to Disable interrupt for RXDREADY event + RXDREADY: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Disable interrupt for TXDSENT event + TXDSENT: u1 = 0, + reserved6: u1 = 0, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + /// Write '1' to Disable interrupt for BB event + BB: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + /// Write '1' to Disable interrupt for SUSPENDED event + SUSPENDED: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Error source + pub const ERRORSRC = mmio(Address + 0x000004c4, 32, packed struct { + /// Overrun error + OVERRUN: u1 = 0, + /// NACK received after sending the address (write '1' to clear) + ANACK: u1 = 0, + /// NACK received after sending a data byte (write '1' to clear) + DNACK: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable TWI + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable TWI + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Pin select for SCL + pub const PSELSCL = @intToPtr(*volatile u32, Address + 0x00000508); + + /// Pin select for SDA + pub const PSELSDA = @intToPtr(*volatile u32, Address + 0x0000050c); + + /// RXD register + pub const RXD = mmio(Address + 0x00000518, 32, packed struct { + /// RXD register + RXD: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// TXD register + pub const TXD = mmio(Address + 0x0000051c, 32, packed struct { + /// TXD register + TXD: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// TWI frequency + pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); + + /// Address used in the TWI transfer + pub const ADDRESS = mmio(Address + 0x00000588, 32, packed struct { + /// Address used in the TWI transfer + ADDRESS: u7 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// Serial Peripheral Interface Master with EasyDMA 1 +pub const SPIM1 = extern struct { + pub const Address: u32 = 0x40004000; + + /// Start SPI transaction + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Stop SPI transaction + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); + + /// Suspend SPI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); + + /// Resume SPI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); + + /// SPI transaction has stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// End of RXD buffer reached + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x00000110); + + /// End of RXD buffer and TXD buffer reached + pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000118); + + /// End of TXD buffer reached + pub const EVENTS_ENDTX = @intToPtr(*volatile u32, Address + 0x00000120); + + /// Transaction started + pub const EVENTS_STARTED = @intToPtr(*volatile u32, Address + 0x0000014c); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between END event and START task + END_START: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Enable interrupt for END event + END: u1 = 0, + reserved5: u1 = 0, + /// Write '1' to Enable interrupt for ENDTX event + ENDTX: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + /// Write '1' to Enable interrupt for STARTED event + STARTED: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Disable interrupt for END event + END: u1 = 0, + reserved5: u1 = 0, + /// Write '1' to Disable interrupt for ENDTX event + ENDTX: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + /// Write '1' to Disable interrupt for STARTED event + STARTED: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable SPIM + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable SPIM + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// SPI frequency. Accuracy depends on the HFCLK source selected. + pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); + + /// Configuration register + pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { + /// Bit order + ORDER: u1 = 0, + /// Serial clock (SCK) phase + CPHA: u1 = 0, + /// Serial clock (SCK) polarity + CPOL: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Over-read character. Character clocked out in case and over-read of the TXD + /// buffer. + pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { + /// Over-read character. Character clocked out in case and over-read of the TXD + /// buffer. + ORC: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// SPI Slave 1 +pub const SPIS1 = extern struct { + pub const Address: u32 = 0x40004000; + + /// Acquire SPI semaphore + pub const TASKS_ACQUIRE = @intToPtr(*volatile u32, Address + 0x00000024); + + /// Release SPI semaphore, enabling the SPI slave to acquire it + pub const TASKS_RELEASE = @intToPtr(*volatile u32, Address + 0x00000028); + + /// Granted transaction completed + pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000104); + + /// End of RXD buffer reached + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x00000110); + + /// Semaphore acquired + pub const EVENTS_ACQUIRED = @intToPtr(*volatile u32, Address + 0x00000128); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between END event and ACQUIRE task + END_ACQUIRE: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for END event + END: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Enable interrupt for ACQUIRED event + ACQUIRED: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for END event + END: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Disable interrupt for ACQUIRED event + ACQUIRED: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Semaphore status register + pub const SEMSTAT = mmio(Address + 0x00000400, 32, packed struct { + /// Semaphore status + SEMSTAT: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Status from last transaction + pub const STATUS = mmio(Address + 0x00000440, 32, packed struct { + /// TX buffer over-read detected, and prevented + OVERREAD: u1 = 0, + /// RX buffer overflow detected, and prevented + OVERFLOW: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable SPI slave + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable SPI slave + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration register + pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { + /// Bit order + ORDER: u1 = 0, + /// Serial clock (SCK) phase + CPHA: u1 = 0, + /// Serial clock (SCK) polarity + CPOL: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Default character. Character clocked out in case of an ignored transaction. + pub const DEF = mmio(Address + 0x0000055c, 32, packed struct { + /// Default character. Character clocked out in case of an ignored transaction. + DEF: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Over-read character + pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { + /// Over-read character. Character clocked out after an over-read of the + /// transmit buffer. + ORC: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// I2C compatible Two-Wire Master Interface with EasyDMA 1 +pub const TWIM1 = extern struct { + pub const Address: u32 = 0x40004000; + + /// Start TWI receive sequence + pub const TASKS_STARTRX = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Start TWI transmit sequence + pub const TASKS_STARTTX = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Stop TWI transaction. Must be issued while the TWI master is not suspended. + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); + + /// Suspend TWI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); + + /// Resume TWI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); + + /// TWI stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// TWI error + pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); + + /// Last byte has been sent out after the SUSPEND task has been issued, TWI + /// traffic is now suspended. + pub const EVENTS_SUSPENDED = @intToPtr(*volatile u32, Address + 0x00000148); + + /// Receive sequence started + pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, Address + 0x0000014c); + + /// Transmit sequence started + pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, Address + 0x00000150); + + /// Byte boundary, starting to receive the last byte + pub const EVENTS_LASTRX = @intToPtr(*volatile u32, Address + 0x0000015c); + + /// Byte boundary, starting to transmit the last byte + pub const EVENTS_LASTTX = @intToPtr(*volatile u32, Address + 0x00000160); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between LASTTX event and STARTRX task + LASTTX_STARTRX: u1 = 0, + /// Shortcut between LASTTX event and SUSPEND task + LASTTX_SUSPEND: u1 = 0, + /// Shortcut between LASTTX event and STOP task + LASTTX_STOP: u1 = 0, + /// Shortcut between LASTRX event and STARTTX task + LASTRX_STARTTX: u1 = 0, + reserved8: u1 = 0, + /// Shortcut between LASTRX event and STOP task + LASTRX_STOP: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + reserved1: u1 = 0, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Enable or disable interrupt for ERROR event + ERROR: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + /// Enable or disable interrupt for SUSPENDED event + SUSPENDED: u1 = 0, + /// Enable or disable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Enable or disable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + /// Enable or disable interrupt for LASTRX event + LASTRX: u1 = 0, + /// Enable or disable interrupt for LASTTX event + LASTTX: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + /// Write '1' to Enable interrupt for SUSPENDED event + SUSPENDED: u1 = 0, + /// Write '1' to Enable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Write '1' to Enable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + /// Write '1' to Enable interrupt for LASTRX event + LASTRX: u1 = 0, + /// Write '1' to Enable interrupt for LASTTX event + LASTTX: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + /// Write '1' to Disable interrupt for SUSPENDED event + SUSPENDED: u1 = 0, + /// Write '1' to Disable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Write '1' to Disable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + /// Write '1' to Disable interrupt for LASTRX event + LASTRX: u1 = 0, + /// Write '1' to Disable interrupt for LASTTX event + LASTTX: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Error source + pub const ERRORSRC = mmio(Address + 0x000004c4, 32, packed struct { + /// Overrun error + OVERRUN: u1 = 0, + /// NACK received after sending the address (write '1' to clear) + ANACK: u1 = 0, + /// NACK received after sending a data byte (write '1' to clear) + DNACK: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable TWIM + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable TWIM + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// TWI frequency + pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); + + /// Address used in the TWI transfer + pub const ADDRESS = mmio(Address + 0x00000588, 32, packed struct { + /// Address used in the TWI transfer + ADDRESS: u7 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// I2C compatible Two-Wire Slave Interface with EasyDMA 1 +pub const TWIS1 = extern struct { + pub const Address: u32 = 0x40004000; + + /// Stop TWI transaction + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); + + /// Suspend TWI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); + + /// Resume TWI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); + + /// Prepare the TWI slave to respond to a write command + pub const TASKS_PREPARERX = @intToPtr(*volatile u32, Address + 0x00000030); + + /// Prepare the TWI slave to respond to a read command + pub const TASKS_PREPARETX = @intToPtr(*volatile u32, Address + 0x00000034); + + /// TWI stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// TWI error + pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); + + /// Receive sequence started + pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, Address + 0x0000014c); + + /// Transmit sequence started + pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, Address + 0x00000150); + + /// Write command received + pub const EVENTS_WRITE = @intToPtr(*volatile u32, Address + 0x00000164); + + /// Read command received + pub const EVENTS_READ = @intToPtr(*volatile u32, Address + 0x00000168); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between WRITE event and SUSPEND task + WRITE_SUSPEND: u1 = 0, + /// Shortcut between READ event and SUSPEND task + READ_SUSPEND: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + reserved1: u1 = 0, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Enable or disable interrupt for ERROR event + ERROR: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + /// Enable or disable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Enable or disable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + /// Enable or disable interrupt for WRITE event + WRITE: u1 = 0, + /// Enable or disable interrupt for READ event + READ: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + /// Write '1' to Enable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Write '1' to Enable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + /// Write '1' to Enable interrupt for WRITE event + WRITE: u1 = 0, + /// Write '1' to Enable interrupt for READ event + READ: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + /// Write '1' to Disable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Write '1' to Disable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + /// Write '1' to Disable interrupt for WRITE event + WRITE: u1 = 0, + /// Write '1' to Disable interrupt for READ event + READ: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Error source + pub const ERRORSRC = mmio(Address + 0x000004d0, 32, packed struct { + /// RX buffer overflow detected, and prevented + OVERFLOW: u1 = 0, + reserved1: u1 = 0, + /// NACK sent after receiving a data byte + DNACK: u1 = 0, + /// TX buffer over-read detected, and prevented + OVERREAD: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Status register indicating which address had a match + pub const MATCH = mmio(Address + 0x000004d4, 32, packed struct { + /// Which of the addresses in {ADDRESS} matched the incoming address + MATCH: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable TWIS + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable TWIS + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration register for the address match mechanism + pub const CONFIG = mmio(Address + 0x00000594, 32, packed struct { + /// Enable or disable address matching on ADDRESS[0] + ADDRESS0: u1 = 0, + /// Enable or disable address matching on ADDRESS[1] + ADDRESS1: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Over-read character. Character sent out in case of an over-read of the + /// transmit buffer. + pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { + /// Over-read character. Character sent out in case of an over-read of the + /// transmit buffer. + ORC: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: TWI slave address 0 + pub const ADDRESS = @intToPtr(*volatile [2]MMIO(32, packed struct { + /// TWI slave address + ADDRESS: u7 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }), Address + 0x00000588); +}; + +/// Serial Peripheral Interface 1 +pub const SPI1 = extern struct { + pub const Address: u32 = 0x40004000; + + /// TXD byte sent and RXD byte received + pub const EVENTS_READY = @intToPtr(*volatile u32, Address + 0x00000108); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for READY event + READY: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for READY event + READY: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable SPI + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable SPI + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// RXD register + pub const RXD = mmio(Address + 0x00000518, 32, packed struct { + /// RX data received. Double buffered + RXD: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// TXD register + pub const TXD = mmio(Address + 0x0000051c, 32, packed struct { + /// TX data to send. Double buffered + TXD: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// SPI frequency + pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); + + /// Configuration register + pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { + /// Bit order + ORDER: u1 = 0, + /// Serial clock (SCK) phase + CPHA: u1 = 0, + /// Serial clock (SCK) polarity + CPOL: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// I2C compatible Two-Wire Interface 1 +pub const TWI1 = extern struct { + pub const Address: u32 = 0x40004000; + + /// Start TWI receive sequence + pub const TASKS_STARTRX = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Start TWI transmit sequence + pub const TASKS_STARTTX = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Stop TWI transaction + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); + + /// Suspend TWI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); + + /// Resume TWI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); + + /// TWI stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// TWI RXD byte received + pub const EVENTS_RXDREADY = @intToPtr(*volatile u32, Address + 0x00000108); + + /// TWI TXD byte sent + pub const EVENTS_TXDSENT = @intToPtr(*volatile u32, Address + 0x0000011c); + + /// TWI error + pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); + + /// TWI byte boundary, generated before each byte that is sent or received + pub const EVENTS_BB = @intToPtr(*volatile u32, Address + 0x00000138); + + /// TWI entered the suspended state + pub const EVENTS_SUSPENDED = @intToPtr(*volatile u32, Address + 0x00000148); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between BB event and SUSPEND task + BB_SUSPEND: u1 = 0, + /// Shortcut between BB event and STOP task + BB_STOP: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Write '1' to Enable interrupt for RXDREADY event + RXDREADY: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Enable interrupt for TXDSENT event + TXDSENT: u1 = 0, + reserved6: u1 = 0, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + /// Write '1' to Enable interrupt for BB event + BB: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + /// Write '1' to Enable interrupt for SUSPENDED event + SUSPENDED: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Write '1' to Disable interrupt for RXDREADY event + RXDREADY: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Disable interrupt for TXDSENT event + TXDSENT: u1 = 0, + reserved6: u1 = 0, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + /// Write '1' to Disable interrupt for BB event + BB: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + /// Write '1' to Disable interrupt for SUSPENDED event + SUSPENDED: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Error source + pub const ERRORSRC = mmio(Address + 0x000004c4, 32, packed struct { + /// Overrun error + OVERRUN: u1 = 0, + /// NACK received after sending the address (write '1' to clear) + ANACK: u1 = 0, + /// NACK received after sending a data byte (write '1' to clear) + DNACK: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable TWI + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable TWI + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Pin select for SCL + pub const PSELSCL = @intToPtr(*volatile u32, Address + 0x00000508); + + /// Pin select for SDA + pub const PSELSDA = @intToPtr(*volatile u32, Address + 0x0000050c); + + /// RXD register + pub const RXD = mmio(Address + 0x00000518, 32, packed struct { + /// RXD register + RXD: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// TXD register + pub const TXD = mmio(Address + 0x0000051c, 32, packed struct { + /// TXD register + TXD: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// TWI frequency + pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); + + /// Address used in the TWI transfer + pub const ADDRESS = mmio(Address + 0x00000588, 32, packed struct { + /// Address used in the TWI transfer + ADDRESS: u7 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// NFC-A compatible radio +pub const NFCT = extern struct { + pub const Address: u32 = 0x40005000; + + /// Activate NFC peripheral for incoming and outgoing frames, change state to + /// activated + pub const TASKS_ACTIVATE = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Disable NFC peripheral + pub const TASKS_DISABLE = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Enable NFC sense field mode, change state to sense mode + pub const TASKS_SENSE = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Start transmission of a outgoing frame, change state to transmit + pub const TASKS_STARTTX = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Initializes the EasyDMA for receive. + pub const TASKS_ENABLERXDATA = @intToPtr(*volatile u32, Address + 0x0000001c); + + /// Force state machine to IDLE state + pub const TASKS_GOIDLE = @intToPtr(*volatile u32, Address + 0x00000024); + + /// Force state machine to SLEEP_A state + pub const TASKS_GOSLEEP = @intToPtr(*volatile u32, Address + 0x00000028); + + /// The NFC peripheral is ready to receive and send frames + pub const EVENTS_READY = @intToPtr(*volatile u32, Address + 0x00000100); + + /// Remote NFC field detected + pub const EVENTS_FIELDDETECTED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Remote NFC field lost + pub const EVENTS_FIELDLOST = @intToPtr(*volatile u32, Address + 0x00000108); + + /// Marks the start of the first symbol of a transmitted frame + pub const EVENTS_TXFRAMESTART = @intToPtr(*volatile u32, Address + 0x0000010c); + + /// Marks the end of the last transmitted on-air symbol of a frame + pub const EVENTS_TXFRAMEEND = @intToPtr(*volatile u32, Address + 0x00000110); + + /// Marks the end of the first symbol of a received frame + pub const EVENTS_RXFRAMESTART = @intToPtr(*volatile u32, Address + 0x00000114); + + /// Received data have been checked (CRC, parity) and transferred to RAM, and + /// EasyDMA has ended accessing the RX buffer + pub const EVENTS_RXFRAMEEND = @intToPtr(*volatile u32, Address + 0x00000118); + + /// NFC error reported. The ERRORSTATUS register contains details on the source + /// of the error. + pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x0000011c); + + /// NFC RX frame error reported. The FRAMESTATUS.RX register contains details on + /// the source of the error. + pub const EVENTS_RXERROR = @intToPtr(*volatile u32, Address + 0x00000128); + + /// RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x0000012c); + + /// Transmission of data in RAM has ended, and EasyDMA has ended accessing the + /// TX buffer + pub const EVENTS_ENDTX = @intToPtr(*volatile u32, Address + 0x00000130); + + /// Auto collision resolution process has started + pub const EVENTS_AUTOCOLRESSTARTED = @intToPtr(*volatile u32, Address + 0x00000138); + + /// NFC Auto collision resolution error reported. + pub const EVENTS_COLLISION = @intToPtr(*volatile u32, Address + 0x00000148); + + /// NFC Auto collision resolution successfully completed + pub const EVENTS_SELECTED = @intToPtr(*volatile u32, Address + 0x0000014c); + + /// EasyDMA is ready to receive or send frames. + pub const EVENTS_STARTED = @intToPtr(*volatile u32, Address + 0x00000150); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between FIELDDETECTED event and ACTIVATE task + FIELDDETECTED_ACTIVATE: u1 = 0, + /// Shortcut between FIELDLOST event and SENSE task + FIELDLOST_SENSE: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + /// Enable or disable interrupt for READY event + READY: u1 = 0, + /// Enable or disable interrupt for FIELDDETECTED event + FIELDDETECTED: u1 = 0, + /// Enable or disable interrupt for FIELDLOST event + FIELDLOST: u1 = 0, + /// Enable or disable interrupt for TXFRAMESTART event + TXFRAMESTART: u1 = 0, + /// Enable or disable interrupt for TXFRAMEEND event + TXFRAMEEND: u1 = 0, + /// Enable or disable interrupt for RXFRAMESTART event + RXFRAMESTART: u1 = 0, + /// Enable or disable interrupt for RXFRAMEEND event + RXFRAMEEND: u1 = 0, + /// Enable or disable interrupt for ERROR event + ERROR: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Enable or disable interrupt for RXERROR event + RXERROR: u1 = 0, + /// Enable or disable interrupt for ENDRX event + ENDRX: u1 = 0, + /// Enable or disable interrupt for ENDTX event + ENDTX: u1 = 0, + reserved3: u1 = 0, + /// Enable or disable interrupt for AUTOCOLRESSTARTED event + AUTOCOLRESSTARTED: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + /// Enable or disable interrupt for COLLISION event + COLLISION: u1 = 0, + /// Enable or disable interrupt for SELECTED event + SELECTED: u1 = 0, + /// Enable or disable interrupt for STARTED event + STARTED: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for READY event + READY: u1 = 0, + /// Write '1' to Enable interrupt for FIELDDETECTED event + FIELDDETECTED: u1 = 0, + /// Write '1' to Enable interrupt for FIELDLOST event + FIELDLOST: u1 = 0, + /// Write '1' to Enable interrupt for TXFRAMESTART event + TXFRAMESTART: u1 = 0, + /// Write '1' to Enable interrupt for TXFRAMEEND event + TXFRAMEEND: u1 = 0, + /// Write '1' to Enable interrupt for RXFRAMESTART event + RXFRAMESTART: u1 = 0, + /// Write '1' to Enable interrupt for RXFRAMEEND event + RXFRAMEEND: u1 = 0, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for RXERROR event + RXERROR: u1 = 0, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1 = 0, + /// Write '1' to Enable interrupt for ENDTX event + ENDTX: u1 = 0, + reserved3: u1 = 0, + /// Write '1' to Enable interrupt for AUTOCOLRESSTARTED event + AUTOCOLRESSTARTED: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Enable interrupt for COLLISION event + COLLISION: u1 = 0, + /// Write '1' to Enable interrupt for SELECTED event + SELECTED: u1 = 0, + /// Write '1' to Enable interrupt for STARTED event + STARTED: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for READY event + READY: u1 = 0, + /// Write '1' to Disable interrupt for FIELDDETECTED event + FIELDDETECTED: u1 = 0, + /// Write '1' to Disable interrupt for FIELDLOST event + FIELDLOST: u1 = 0, + /// Write '1' to Disable interrupt for TXFRAMESTART event + TXFRAMESTART: u1 = 0, + /// Write '1' to Disable interrupt for TXFRAMEEND event + TXFRAMEEND: u1 = 0, + /// Write '1' to Disable interrupt for RXFRAMESTART event + RXFRAMESTART: u1 = 0, + /// Write '1' to Disable interrupt for RXFRAMEEND event + RXFRAMEEND: u1 = 0, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for RXERROR event + RXERROR: u1 = 0, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1 = 0, + /// Write '1' to Disable interrupt for ENDTX event + ENDTX: u1 = 0, + reserved3: u1 = 0, + /// Write '1' to Disable interrupt for AUTOCOLRESSTARTED event + AUTOCOLRESSTARTED: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Disable interrupt for COLLISION event + COLLISION: u1 = 0, + /// Write '1' to Disable interrupt for SELECTED event + SELECTED: u1 = 0, + /// Write '1' to Disable interrupt for STARTED event + STARTED: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// NFC Error Status register + pub const ERRORSTATUS = mmio(Address + 0x00000404, 32, packed struct { + /// No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX + FRAMEDELAYTIMEOUT: u1 = 0, + reserved1: u1 = 0, + /// Field level is too high at max load resistance + NFCFIELDTOOSTRONG: u1 = 0, + /// Field level is too low at min load resistance + NFCFIELDTOOWEAK: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Current value driven to the NFC Load Control + pub const CURRENTLOADCTRL = mmio(Address + 0x00000430, 32, packed struct { + /// Current value driven to the NFC Load Control + CURRENTLOADCTRL: u6 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Indicates the presence or not of a valid field + pub const FIELDPRESENT = mmio(Address + 0x0000043c, 32, packed struct { + /// Indicates the presence or not of a valid field. Available only in the + /// activated state. + FIELDPRESENT: u1 = 0, + /// Indicates if the low level has locked to the field + LOCKDETECT: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Minimum frame delay + pub const FRAMEDELAYMIN = mmio(Address + 0x00000504, 32, packed struct { + /// Minimum frame delay in number of 13.56 MHz clocks + FRAMEDELAYMIN: u16 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Maximum frame delay + pub const FRAMEDELAYMAX = mmio(Address + 0x00000508, 32, packed struct { + /// Maximum frame delay in number of 13.56 MHz clocks + FRAMEDELAYMAX: u16 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration register for the Frame Delay Timer + pub const FRAMEDELAYMODE = mmio(Address + 0x0000050c, 32, packed struct { + /// Configuration register for the Frame Delay Timer + FRAMEDELAYMODE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Packet pointer for TXD and RXD data storage in Data RAM + pub const PACKETPTR = mmio(Address + 0x00000510, 32, packed struct { + /// Packet pointer for TXD and RXD data storage in Data RAM. This address is a + /// byte aligned RAM address. + PTR: u32 = 0, + }); + + /// Size of allocated for TXD and RXD data storage buffer in Data RAM + pub const MAXLEN = mmio(Address + 0x00000514, 32, packed struct { + /// Size of allocated for TXD and RXD data storage buffer in Data RAM + MAXLEN: u9 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Last NFCID1 part (4, 7 or 10 bytes ID) + pub const NFCID1_LAST = mmio(Address + 0x00000590, 32, packed struct { + /// NFCID1 byte Z (very last byte sent) + NFCID1_Z: u8 = 0, + /// NFCID1 byte Y + NFCID1_Y: u8 = 0, + /// NFCID1 byte X + NFCID1_X: u8 = 0, + /// NFCID1 byte W + NFCID1_W: u8 = 0, + }); + + /// Second last NFCID1 part (7 or 10 bytes ID) + pub const NFCID1_2ND_LAST = mmio(Address + 0x00000594, 32, packed struct { + /// NFCID1 byte V + NFCID1_V: u8 = 0, + /// NFCID1 byte U + NFCID1_U: u8 = 0, + /// NFCID1 byte T + NFCID1_T: u8 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Third last NFCID1 part (10 bytes ID) + pub const NFCID1_3RD_LAST = mmio(Address + 0x00000598, 32, packed struct { + /// NFCID1 byte S + NFCID1_S: u8 = 0, + /// NFCID1 byte R + NFCID1_R: u8 = 0, + /// NFCID1 byte Q + NFCID1_Q: u8 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// NFC-A SENS_RES auto-response settings + pub const SENSRES = mmio(Address + 0x000005a0, 32, packed struct { + /// Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the + /// NFC Forum, NFC Digital Protocol Technical Specification + BITFRAMESDD: u5 = 0, + /// Reserved for future use. Shall be 0. + RFU5: u1 = 0, + /// NFCID1 size. This value is used by the Auto collision resolution engine. + NFCIDSIZE: u2 = 0, + /// Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES + /// response in the NFC Forum, NFC Digital Protocol Technical Specification + PLATFCONFIG: u4 = 0, + /// Reserved for future use. Shall be 0. + RFU74: u4 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// NFC-A SEL_RES auto-response settings + pub const SELRES = mmio(Address + 0x000005a4, 32, packed struct { + /// Reserved for future use. Shall be 0. + RFU10: u2 = 0, + /// Cascade bit (controlled by hardware, write has no effect) + CASCADE: u1 = 0, + /// Reserved for future use. Shall be 0. + RFU43: u2 = 0, + /// Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC + /// Digital Protocol Technical Specification + PROTOCOL: u2 = 0, + /// Reserved for future use. Shall be 0. + RFU7: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + pub const FRAMESTATUS = struct { + + /// Result of last incoming frames + pub const RX = mmio(Address + 0x00000000, 32, packed struct { + /// No valid End of Frame detected + CRCERROR: u1 = 0, + reserved1: u1 = 0, + /// Parity status of received frame + PARITYSTATUS: u1 = 0, + /// Overrun detected + OVERRUN: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; + + pub const TXD = struct { + + /// Configuration of outgoing frames + pub const FRAMECONFIG = mmio(Address + 0x00000000, 32, packed struct { + /// Adding parity or not in the frame + PARITY: u1 = 0, + /// Discarding unused bits in start or at end of a Frame + DISCARDMODE: u1 = 0, + /// Adding SoF or not in TX frames + SOF: u1 = 0, + reserved1: u1 = 0, + /// CRC mode for outgoing frames + CRCMODETX: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Size of outgoing frame + pub const AMOUNT = mmio(Address + 0x00000004, 32, packed struct { + /// Number of bits in the last or first byte read from RAM that shall be + /// included in the frame (excluding parity bit). + TXDATABITS: u3 = 0, + /// Number of complete bytes that shall be included in the frame, excluding CRC, + /// parity and framing + TXDATABYTES: u9 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; + + pub const RXD = struct { + + /// Configuration of incoming frames + pub const FRAMECONFIG = mmio(Address + 0x00000000, 32, packed struct { + /// Parity expected or not in RX frame + PARITY: u1 = 0, + reserved1: u1 = 0, + /// SoF expected or not in RX frames + SOF: u1 = 0, + reserved2: u1 = 0, + /// CRC mode for incoming frames + CRCMODERX: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Size of last incoming frame + pub const AMOUNT = mmio(Address + 0x00000004, 32, packed struct { + /// Number of bits in the last byte in the frame, if less than 8 (including CRC, + /// but excluding parity and SoF/EoF framing). + RXDATABITS: u3 = 0, + /// Number of complete bytes received in the frame (including CRC, but excluding + /// parity and SoF/EoF framing) + RXDATABYTES: u9 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; +}; + +/// GPIO Tasks and Events +pub const GPIOTE = extern struct { + pub const Address: u32 = 0x40006000; + + /// Event generated from multiple input GPIO pins with SENSE mechanism enabled + pub const EVENTS_PORT = @intToPtr(*volatile u32, Address + 0x0000017c); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for IN[0] event + IN0: u1 = 0, + /// Write '1' to Enable interrupt for IN[1] event + IN1: u1 = 0, + /// Write '1' to Enable interrupt for IN[2] event + IN2: u1 = 0, + /// Write '1' to Enable interrupt for IN[3] event + IN3: u1 = 0, + /// Write '1' to Enable interrupt for IN[4] event + IN4: u1 = 0, + /// Write '1' to Enable interrupt for IN[5] event + IN5: u1 = 0, + /// Write '1' to Enable interrupt for IN[6] event + IN6: u1 = 0, + /// Write '1' to Enable interrupt for IN[7] event + IN7: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for PORT event + PORT: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for IN[0] event + IN0: u1 = 0, + /// Write '1' to Disable interrupt for IN[1] event + IN1: u1 = 0, + /// Write '1' to Disable interrupt for IN[2] event + IN2: u1 = 0, + /// Write '1' to Disable interrupt for IN[3] event + IN3: u1 = 0, + /// Write '1' to Disable interrupt for IN[4] event + IN4: u1 = 0, + /// Write '1' to Disable interrupt for IN[5] event + IN5: u1 = 0, + /// Write '1' to Disable interrupt for IN[6] event + IN6: u1 = 0, + /// Write '1' to Disable interrupt for IN[7] event + IN7: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for PORT event + PORT: u1 = 0, + }); + /// Description collection[0]: Task for writing to pin specified in + /// CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. + pub const TASKS_OUT = @intToPtr(*volatile [8]u32, Address + 0x00000000); + /// Description collection[0]: Task for writing to pin specified in + /// CONFIG[0].PSEL. Action on pin is to set it high. + pub const TASKS_SET = @intToPtr(*volatile [8]u32, Address + 0x00000030); + /// Description collection[0]: Task for writing to pin specified in + /// CONFIG[0].PSEL. Action on pin is to set it low. + pub const TASKS_CLR = @intToPtr(*volatile [8]u32, Address + 0x00000060); + /// Description collection[0]: Event generated from pin specified in + /// CONFIG[0].PSEL + pub const EVENTS_IN = @intToPtr(*volatile [8]u32, Address + 0x00000100); + /// Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks + /// and IN[n] event + pub const CONFIG = @intToPtr(*volatile [8]MMIO(32, packed struct { + /// Mode + MODE: u2 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event + PSEL: u5 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + /// When In task mode: Operation to be performed on output when OUT[n] task is + /// triggered. When In event mode: Operation on input that shall trigger IN[n] + /// event. + POLARITY: u2 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + /// When in task mode: Initial value of the output when the GPIOTE channel is + /// configured. When in event mode: No effect. + OUTINIT: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }), Address + 0x00000510); +}; + +/// Analog to Digital Converter +pub const SAADC = extern struct { + pub const Address: u32 = 0x40007000; + + /// Start the ADC and prepare the result buffer in RAM + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Take one ADC sample, if scan is enabled all channels are sampled + pub const TASKS_SAMPLE = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Stop the ADC and terminate any on-going conversion + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Starts offset auto-calibration + pub const TASKS_CALIBRATEOFFSET = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// The ADC has started + pub const EVENTS_STARTED = @intToPtr(*volatile u32, Address + 0x00000100); + + /// The ADC has filled up the Result buffer + pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000104); + + /// A conversion task has been completed. Depending on the mode, multiple + /// conversions might be needed for a result to be transferred to RAM. + pub const EVENTS_DONE = @intToPtr(*volatile u32, Address + 0x00000108); + + /// A result is ready to get transferred to RAM. + pub const EVENTS_RESULTDONE = @intToPtr(*volatile u32, Address + 0x0000010c); + + /// Calibration is complete + pub const EVENTS_CALIBRATEDONE = @intToPtr(*volatile u32, Address + 0x00000110); + + /// The ADC has stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000114); + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + /// Enable or disable interrupt for STARTED event + STARTED: u1 = 0, + /// Enable or disable interrupt for END event + END: u1 = 0, + /// Enable or disable interrupt for DONE event + DONE: u1 = 0, + /// Enable or disable interrupt for RESULTDONE event + RESULTDONE: u1 = 0, + /// Enable or disable interrupt for CALIBRATEDONE event + CALIBRATEDONE: u1 = 0, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Enable or disable interrupt for CH[0].LIMITH event + CH0LIMITH: u1 = 0, + /// Enable or disable interrupt for CH[0].LIMITL event + CH0LIMITL: u1 = 0, + /// Enable or disable interrupt for CH[1].LIMITH event + CH1LIMITH: u1 = 0, + /// Enable or disable interrupt for CH[1].LIMITL event + CH1LIMITL: u1 = 0, + /// Enable or disable interrupt for CH[2].LIMITH event + CH2LIMITH: u1 = 0, + /// Enable or disable interrupt for CH[2].LIMITL event + CH2LIMITL: u1 = 0, + /// Enable or disable interrupt for CH[3].LIMITH event + CH3LIMITH: u1 = 0, + /// Enable or disable interrupt for CH[3].LIMITL event + CH3LIMITL: u1 = 0, + /// Enable or disable interrupt for CH[4].LIMITH event + CH4LIMITH: u1 = 0, + /// Enable or disable interrupt for CH[4].LIMITL event + CH4LIMITL: u1 = 0, + /// Enable or disable interrupt for CH[5].LIMITH event + CH5LIMITH: u1 = 0, + /// Enable or disable interrupt for CH[5].LIMITL event + CH5LIMITL: u1 = 0, + /// Enable or disable interrupt for CH[6].LIMITH event + CH6LIMITH: u1 = 0, + /// Enable or disable interrupt for CH[6].LIMITL event + CH6LIMITL: u1 = 0, + /// Enable or disable interrupt for CH[7].LIMITH event + CH7LIMITH: u1 = 0, + /// Enable or disable interrupt for CH[7].LIMITL event + CH7LIMITL: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for STARTED event + STARTED: u1 = 0, + /// Write '1' to Enable interrupt for END event + END: u1 = 0, + /// Write '1' to Enable interrupt for DONE event + DONE: u1 = 0, + /// Write '1' to Enable interrupt for RESULTDONE event + RESULTDONE: u1 = 0, + /// Write '1' to Enable interrupt for CALIBRATEDONE event + CALIBRATEDONE: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Write '1' to Enable interrupt for CH[0].LIMITH event + CH0LIMITH: u1 = 0, + /// Write '1' to Enable interrupt for CH[0].LIMITL event + CH0LIMITL: u1 = 0, + /// Write '1' to Enable interrupt for CH[1].LIMITH event + CH1LIMITH: u1 = 0, + /// Write '1' to Enable interrupt for CH[1].LIMITL event + CH1LIMITL: u1 = 0, + /// Write '1' to Enable interrupt for CH[2].LIMITH event + CH2LIMITH: u1 = 0, + /// Write '1' to Enable interrupt for CH[2].LIMITL event + CH2LIMITL: u1 = 0, + /// Write '1' to Enable interrupt for CH[3].LIMITH event + CH3LIMITH: u1 = 0, + /// Write '1' to Enable interrupt for CH[3].LIMITL event + CH3LIMITL: u1 = 0, + /// Write '1' to Enable interrupt for CH[4].LIMITH event + CH4LIMITH: u1 = 0, + /// Write '1' to Enable interrupt for CH[4].LIMITL event + CH4LIMITL: u1 = 0, + /// Write '1' to Enable interrupt for CH[5].LIMITH event + CH5LIMITH: u1 = 0, + /// Write '1' to Enable interrupt for CH[5].LIMITL event + CH5LIMITL: u1 = 0, + /// Write '1' to Enable interrupt for CH[6].LIMITH event + CH6LIMITH: u1 = 0, + /// Write '1' to Enable interrupt for CH[6].LIMITL event + CH6LIMITL: u1 = 0, + /// Write '1' to Enable interrupt for CH[7].LIMITH event + CH7LIMITH: u1 = 0, + /// Write '1' to Enable interrupt for CH[7].LIMITL event + CH7LIMITL: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for STARTED event + STARTED: u1 = 0, + /// Write '1' to Disable interrupt for END event + END: u1 = 0, + /// Write '1' to Disable interrupt for DONE event + DONE: u1 = 0, + /// Write '1' to Disable interrupt for RESULTDONE event + RESULTDONE: u1 = 0, + /// Write '1' to Disable interrupt for CALIBRATEDONE event + CALIBRATEDONE: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Write '1' to Disable interrupt for CH[0].LIMITH event + CH0LIMITH: u1 = 0, + /// Write '1' to Disable interrupt for CH[0].LIMITL event + CH0LIMITL: u1 = 0, + /// Write '1' to Disable interrupt for CH[1].LIMITH event + CH1LIMITH: u1 = 0, + /// Write '1' to Disable interrupt for CH[1].LIMITL event + CH1LIMITL: u1 = 0, + /// Write '1' to Disable interrupt for CH[2].LIMITH event + CH2LIMITH: u1 = 0, + /// Write '1' to Disable interrupt for CH[2].LIMITL event + CH2LIMITL: u1 = 0, + /// Write '1' to Disable interrupt for CH[3].LIMITH event + CH3LIMITH: u1 = 0, + /// Write '1' to Disable interrupt for CH[3].LIMITL event + CH3LIMITL: u1 = 0, + /// Write '1' to Disable interrupt for CH[4].LIMITH event + CH4LIMITH: u1 = 0, + /// Write '1' to Disable interrupt for CH[4].LIMITL event + CH4LIMITL: u1 = 0, + /// Write '1' to Disable interrupt for CH[5].LIMITH event + CH5LIMITH: u1 = 0, + /// Write '1' to Disable interrupt for CH[5].LIMITL event + CH5LIMITL: u1 = 0, + /// Write '1' to Disable interrupt for CH[6].LIMITH event + CH6LIMITH: u1 = 0, + /// Write '1' to Disable interrupt for CH[6].LIMITL event + CH6LIMITL: u1 = 0, + /// Write '1' to Disable interrupt for CH[7].LIMITH event + CH7LIMITH: u1 = 0, + /// Write '1' to Disable interrupt for CH[7].LIMITL event + CH7LIMITL: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Status + pub const STATUS = mmio(Address + 0x00000400, 32, packed struct { + /// Status + STATUS: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable ADC + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable ADC + ENABLE: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Resolution configuration + pub const RESOLUTION = mmio(Address + 0x000005f0, 32, packed struct { + /// Set the resolution + VAL: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The + /// RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher + /// RESOLUTION should be used. + pub const OVERSAMPLE = mmio(Address + 0x000005f4, 32, packed struct { + /// Oversample control + OVERSAMPLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Controls normal or continuous sample rate + pub const SAMPLERATE = mmio(Address + 0x000005f8, 32, packed struct { + /// Capture and compare value. Sample rate is 16 MHz/CC + CC: u11 = 0, + reserved1: u1 = 0, + /// Select mode for sample rate control + MODE: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + pub const RESULT = struct { + + /// Data pointer + pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Maximum number of buffer words to transfer + pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// Maximum number of buffer words to transfer + MAXCNT: u15 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Number of buffer words transferred since last START + pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + /// Number of buffer words transferred since last START. This register can be + /// read after an END or STOPPED event. + AMOUNT: u15 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; +}; + +/// Timer/Counter 0 +pub const TIMER0 = extern struct { + pub const Address: u32 = 0x40008000; + + /// Start Timer + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop Timer + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Increment Timer (Counter mode only) + pub const TASKS_COUNT = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Clear time + pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Deprecated register - Shut down timer + pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between COMPARE[0] event and CLEAR task + COMPARE0_CLEAR: u1 = 0, + /// Shortcut between COMPARE[1] event and CLEAR task + COMPARE1_CLEAR: u1 = 0, + /// Shortcut between COMPARE[2] event and CLEAR task + COMPARE2_CLEAR: u1 = 0, + /// Shortcut between COMPARE[3] event and CLEAR task + COMPARE3_CLEAR: u1 = 0, + /// Shortcut between COMPARE[4] event and CLEAR task + COMPARE4_CLEAR: u1 = 0, + /// Shortcut between COMPARE[5] event and CLEAR task + COMPARE5_CLEAR: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between COMPARE[0] event and STOP task + COMPARE0_STOP: u1 = 0, + /// Shortcut between COMPARE[1] event and STOP task + COMPARE1_STOP: u1 = 0, + /// Shortcut between COMPARE[2] event and STOP task + COMPARE2_STOP: u1 = 0, + /// Shortcut between COMPARE[3] event and STOP task + COMPARE3_STOP: u1 = 0, + /// Shortcut between COMPARE[4] event and STOP task + COMPARE4_STOP: u1 = 0, + /// Shortcut between COMPARE[5] event and STOP task + COMPARE5_STOP: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[4] event + COMPARE4: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[5] event + COMPARE5: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[4] event + COMPARE4: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[5] event + COMPARE5: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Timer mode selection + pub const MODE = mmio(Address + 0x00000504, 32, packed struct { + /// Timer mode + MODE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configure the number of bits used by the TIMER + pub const BITMODE = mmio(Address + 0x00000508, 32, packed struct { + /// Timer bit width + BITMODE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Timer prescaler register + pub const PRESCALER = mmio(Address + 0x00000510, 32, packed struct { + /// Prescaler value + PRESCALER: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Capture Timer value to CC[0] register + pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, Address + 0x00000040); + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, Address + 0x00000140); + /// Description collection[0]: Capture/Compare register 0 + pub const CC = @intToPtr(*volatile [6]u32, Address + 0x00000540); +}; + +/// Timer/Counter 1 +pub const TIMER1 = extern struct { + pub const Address: u32 = 0x40009000; + + /// Start Timer + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop Timer + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Increment Timer (Counter mode only) + pub const TASKS_COUNT = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Clear time + pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Deprecated register - Shut down timer + pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between COMPARE[0] event and CLEAR task + COMPARE0_CLEAR: u1 = 0, + /// Shortcut between COMPARE[1] event and CLEAR task + COMPARE1_CLEAR: u1 = 0, + /// Shortcut between COMPARE[2] event and CLEAR task + COMPARE2_CLEAR: u1 = 0, + /// Shortcut between COMPARE[3] event and CLEAR task + COMPARE3_CLEAR: u1 = 0, + /// Shortcut between COMPARE[4] event and CLEAR task + COMPARE4_CLEAR: u1 = 0, + /// Shortcut between COMPARE[5] event and CLEAR task + COMPARE5_CLEAR: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between COMPARE[0] event and STOP task + COMPARE0_STOP: u1 = 0, + /// Shortcut between COMPARE[1] event and STOP task + COMPARE1_STOP: u1 = 0, + /// Shortcut between COMPARE[2] event and STOP task + COMPARE2_STOP: u1 = 0, + /// Shortcut between COMPARE[3] event and STOP task + COMPARE3_STOP: u1 = 0, + /// Shortcut between COMPARE[4] event and STOP task + COMPARE4_STOP: u1 = 0, + /// Shortcut between COMPARE[5] event and STOP task + COMPARE5_STOP: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[4] event + COMPARE4: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[5] event + COMPARE5: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[4] event + COMPARE4: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[5] event + COMPARE5: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Timer mode selection + pub const MODE = mmio(Address + 0x00000504, 32, packed struct { + /// Timer mode + MODE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configure the number of bits used by the TIMER + pub const BITMODE = mmio(Address + 0x00000508, 32, packed struct { + /// Timer bit width + BITMODE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Timer prescaler register + pub const PRESCALER = mmio(Address + 0x00000510, 32, packed struct { + /// Prescaler value + PRESCALER: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Capture Timer value to CC[0] register + pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, Address + 0x00000040); + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, Address + 0x00000140); + /// Description collection[0]: Capture/Compare register 0 + pub const CC = @intToPtr(*volatile [6]u32, Address + 0x00000540); +}; + +/// Timer/Counter 2 +pub const TIMER2 = extern struct { + pub const Address: u32 = 0x4000a000; + + /// Start Timer + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop Timer + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Increment Timer (Counter mode only) + pub const TASKS_COUNT = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Clear time + pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Deprecated register - Shut down timer + pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between COMPARE[0] event and CLEAR task + COMPARE0_CLEAR: u1 = 0, + /// Shortcut between COMPARE[1] event and CLEAR task + COMPARE1_CLEAR: u1 = 0, + /// Shortcut between COMPARE[2] event and CLEAR task + COMPARE2_CLEAR: u1 = 0, + /// Shortcut between COMPARE[3] event and CLEAR task + COMPARE3_CLEAR: u1 = 0, + /// Shortcut between COMPARE[4] event and CLEAR task + COMPARE4_CLEAR: u1 = 0, + /// Shortcut between COMPARE[5] event and CLEAR task + COMPARE5_CLEAR: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between COMPARE[0] event and STOP task + COMPARE0_STOP: u1 = 0, + /// Shortcut between COMPARE[1] event and STOP task + COMPARE1_STOP: u1 = 0, + /// Shortcut between COMPARE[2] event and STOP task + COMPARE2_STOP: u1 = 0, + /// Shortcut between COMPARE[3] event and STOP task + COMPARE3_STOP: u1 = 0, + /// Shortcut between COMPARE[4] event and STOP task + COMPARE4_STOP: u1 = 0, + /// Shortcut between COMPARE[5] event and STOP task + COMPARE5_STOP: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[4] event + COMPARE4: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[5] event + COMPARE5: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[4] event + COMPARE4: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[5] event + COMPARE5: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Timer mode selection + pub const MODE = mmio(Address + 0x00000504, 32, packed struct { + /// Timer mode + MODE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configure the number of bits used by the TIMER + pub const BITMODE = mmio(Address + 0x00000508, 32, packed struct { + /// Timer bit width + BITMODE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Timer prescaler register + pub const PRESCALER = mmio(Address + 0x00000510, 32, packed struct { + /// Prescaler value + PRESCALER: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Capture Timer value to CC[0] register + pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, Address + 0x00000040); + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, Address + 0x00000140); + /// Description collection[0]: Capture/Compare register 0 + pub const CC = @intToPtr(*volatile [6]u32, Address + 0x00000540); +}; + +/// Real time counter 0 +pub const RTC0 = extern struct { + pub const Address: u32 = 0x4000b000; + + /// Start RTC COUNTER + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop RTC COUNTER + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Clear RTC COUNTER + pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Set COUNTER to 0xFFFFF0 + pub const TASKS_TRIGOVRFLW = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Event on COUNTER increment + pub const EVENTS_TICK = @intToPtr(*volatile u32, Address + 0x00000100); + + /// Event on COUNTER overflow + pub const EVENTS_OVRFLW = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for TICK event + TICK: u1 = 0, + /// Write '1' to Enable interrupt for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for TICK event + TICK: u1 = 0, + /// Write '1' to Disable interrupt for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable event routing + pub const EVTEN = mmio(Address + 0x00000340, 32, packed struct { + /// Enable or disable event routing for TICK event + TICK: u1 = 0, + /// Enable or disable event routing for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Enable or disable event routing for COMPARE[0] event + COMPARE0: u1 = 0, + /// Enable or disable event routing for COMPARE[1] event + COMPARE1: u1 = 0, + /// Enable or disable event routing for COMPARE[2] event + COMPARE2: u1 = 0, + /// Enable or disable event routing for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable event routing + pub const EVTENSET = mmio(Address + 0x00000344, 32, packed struct { + /// Write '1' to Enable event routing for TICK event + TICK: u1 = 0, + /// Write '1' to Enable event routing for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable event routing for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Enable event routing for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Enable event routing for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Enable event routing for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable event routing + pub const EVTENCLR = mmio(Address + 0x00000348, 32, packed struct { + /// Write '1' to Disable event routing for TICK event + TICK: u1 = 0, + /// Write '1' to Disable event routing for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable event routing for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Disable event routing for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Disable event routing for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Disable event routing for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Current COUNTER value + pub const COUNTER = mmio(Address + 0x00000504, 32, packed struct { + /// Counter value + COUNTER: u24 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written + /// when RTC is stopped + pub const PRESCALER = mmio(Address + 0x00000508, 32, packed struct { + /// Prescaler value + PRESCALER: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [4]u32, Address + 0x00000140); + /// Description collection[0]: Compare register 0 + pub const CC = @intToPtr(*volatile [4]MMIO(32, packed struct { + /// Compare value + COMPARE: u24 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }), Address + 0x00000540); +}; + +/// Temperature Sensor +pub const TEMP = extern struct { + pub const Address: u32 = 0x4000c000; + + /// Start temperature measurement + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop temperature measurement + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Temperature measurement complete, data ready + pub const EVENTS_DATARDY = @intToPtr(*volatile u32, Address + 0x00000100); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for DATARDY event + DATARDY: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for DATARDY event + DATARDY: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Temperature in degC (0.25deg steps) + pub const TEMP = @intToPtr(*volatile u32, Address + 0x00000508); + + /// Slope of 1st piece wise linear function + pub const A0 = mmio(Address + 0x00000520, 32, packed struct { + /// Slope of 1st piece wise linear function + A0: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Slope of 2nd piece wise linear function + pub const A1 = mmio(Address + 0x00000524, 32, packed struct { + /// Slope of 2nd piece wise linear function + A1: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Slope of 3rd piece wise linear function + pub const A2 = mmio(Address + 0x00000528, 32, packed struct { + /// Slope of 3rd piece wise linear function + A2: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Slope of 4th piece wise linear function + pub const A3 = mmio(Address + 0x0000052c, 32, packed struct { + /// Slope of 4th piece wise linear function + A3: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Slope of 5th piece wise linear function + pub const A4 = mmio(Address + 0x00000530, 32, packed struct { + /// Slope of 5th piece wise linear function + A4: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Slope of 6th piece wise linear function + pub const A5 = mmio(Address + 0x00000534, 32, packed struct { + /// Slope of 6th piece wise linear function + A5: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// y-intercept of 1st piece wise linear function + pub const B0 = mmio(Address + 0x00000540, 32, packed struct { + /// y-intercept of 1st piece wise linear function + B0: u14 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// y-intercept of 2nd piece wise linear function + pub const B1 = mmio(Address + 0x00000544, 32, packed struct { + /// y-intercept of 2nd piece wise linear function + B1: u14 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// y-intercept of 3rd piece wise linear function + pub const B2 = mmio(Address + 0x00000548, 32, packed struct { + /// y-intercept of 3rd piece wise linear function + B2: u14 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// y-intercept of 4th piece wise linear function + pub const B3 = mmio(Address + 0x0000054c, 32, packed struct { + /// y-intercept of 4th piece wise linear function + B3: u14 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// y-intercept of 5th piece wise linear function + pub const B4 = mmio(Address + 0x00000550, 32, packed struct { + /// y-intercept of 5th piece wise linear function + B4: u14 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// y-intercept of 6th piece wise linear function + pub const B5 = mmio(Address + 0x00000554, 32, packed struct { + /// y-intercept of 6th piece wise linear function + B5: u14 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// End point of 1st piece wise linear function + pub const T0 = mmio(Address + 0x00000560, 32, packed struct { + /// End point of 1st piece wise linear function + T0: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// End point of 2nd piece wise linear function + pub const T1 = mmio(Address + 0x00000564, 32, packed struct { + /// End point of 2nd piece wise linear function + T1: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// End point of 3rd piece wise linear function + pub const T2 = mmio(Address + 0x00000568, 32, packed struct { + /// End point of 3rd piece wise linear function + T2: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// End point of 4th piece wise linear function + pub const T3 = mmio(Address + 0x0000056c, 32, packed struct { + /// End point of 4th piece wise linear function + T3: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// End point of 5th piece wise linear function + pub const T4 = mmio(Address + 0x00000570, 32, packed struct { + /// End point of 5th piece wise linear function + T4: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// Random Number Generator +pub const RNG = extern struct { + pub const Address: u32 = 0x4000d000; + + /// Task starting the random number generator + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Task stopping the random number generator + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Event being generated for every new random number written to the VALUE + /// register + pub const EVENTS_VALRDY = @intToPtr(*volatile u32, Address + 0x00000100); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between VALRDY event and STOP task + VALRDY_STOP: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for VALRDY event + VALRDY: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for VALRDY event + VALRDY: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration register + pub const CONFIG = mmio(Address + 0x00000504, 32, packed struct { + /// Bias correction + DERCEN: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Output random number + pub const VALUE = mmio(Address + 0x00000508, 32, packed struct { + /// Generated random number + VALUE: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// AES ECB Mode Encryption +pub const ECB = extern struct { + pub const Address: u32 = 0x4000e000; + + /// Start ECB block encrypt + pub const TASKS_STARTECB = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Abort a possible executing ECB operation + pub const TASKS_STOPECB = @intToPtr(*volatile u32, Address + 0x00000004); + + /// ECB block encrypt complete + pub const EVENTS_ENDECB = @intToPtr(*volatile u32, Address + 0x00000100); + + /// ECB block encrypt aborted because of a STOPECB task or due to an error + pub const EVENTS_ERRORECB = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for ENDECB event + ENDECB: u1 = 0, + /// Write '1' to Enable interrupt for ERRORECB event + ERRORECB: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for ENDECB event + ENDECB: u1 = 0, + /// Write '1' to Disable interrupt for ERRORECB event + ERRORECB: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// ECB block encrypt memory pointers + pub const ECBDATAPTR = @intToPtr(*volatile u32, Address + 0x00000504); +}; + +/// AES CCM Mode Encryption +pub const CCM = extern struct { + pub const Address: u32 = 0x4000f000; + + /// Start generation of key-stream. This operation will stop by itself when + /// completed. + pub const TASKS_KSGEN = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Start encryption/decryption. This operation will stop by itself when + /// completed. + pub const TASKS_CRYPT = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Stop encryption/decryption + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Key-stream generation complete + pub const EVENTS_ENDKSGEN = @intToPtr(*volatile u32, Address + 0x00000100); + + /// Encrypt/decrypt complete + pub const EVENTS_ENDCRYPT = @intToPtr(*volatile u32, Address + 0x00000104); + + /// CCM error event + pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000108); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between ENDKSGEN event and CRYPT task + ENDKSGEN_CRYPT: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for ENDKSGEN event + ENDKSGEN: u1 = 0, + /// Write '1' to Enable interrupt for ENDCRYPT event + ENDCRYPT: u1 = 0, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for ENDKSGEN event + ENDKSGEN: u1 = 0, + /// Write '1' to Disable interrupt for ENDCRYPT event + ENDCRYPT: u1 = 0, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// MIC check result + pub const MICSTATUS = mmio(Address + 0x00000400, 32, packed struct { + /// The result of the MIC check performed during the previous decryption + /// operation + MICSTATUS: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable CCM + ENABLE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Operation mode + pub const MODE = mmio(Address + 0x00000504, 32, packed struct { + /// The mode of operation to be used + MODE: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Data rate that the CCM shall run in synch with + DATARATE: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + /// Packet length configuration + LENGTH: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Pointer to data structure holding AES key and NONCE vector + pub const CNFPTR = @intToPtr(*volatile u32, Address + 0x00000508); + + /// Input pointer + pub const INPTR = @intToPtr(*volatile u32, Address + 0x0000050c); + + /// Output pointer + pub const OUTPTR = @intToPtr(*volatile u32, Address + 0x00000510); + + /// Pointer to data area used for temporary storage + pub const SCRATCHPTR = @intToPtr(*volatile u32, Address + 0x00000514); +}; + +/// Accelerated Address Resolver +pub const AAR = extern struct { + pub const Address: u32 = 0x4000f000; + + /// Start resolving addresses based on IRKs specified in the IRK data structure + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop resolving addresses + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Address resolution procedure complete + pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000100); + + /// Address resolved + pub const EVENTS_RESOLVED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Address not resolved + pub const EVENTS_NOTRESOLVED = @intToPtr(*volatile u32, Address + 0x00000108); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for END event + END: u1 = 0, + /// Write '1' to Enable interrupt for RESOLVED event + RESOLVED: u1 = 0, + /// Write '1' to Enable interrupt for NOTRESOLVED event + NOTRESOLVED: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for END event + END: u1 = 0, + /// Write '1' to Disable interrupt for RESOLVED event + RESOLVED: u1 = 0, + /// Write '1' to Disable interrupt for NOTRESOLVED event + NOTRESOLVED: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Resolution status + pub const STATUS = mmio(Address + 0x00000400, 32, packed struct { + /// The IRK that was used last time an address was resolved + STATUS: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable AAR + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable AAR + ENABLE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Number of IRKs + pub const NIRK = mmio(Address + 0x00000504, 32, packed struct { + /// Number of Identity root keys available in the IRK data structure + NIRK: u5 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Pointer to IRK data structure + pub const IRKPTR = @intToPtr(*volatile u32, Address + 0x00000508); + + /// Pointer to the resolvable address + pub const ADDRPTR = @intToPtr(*volatile u32, Address + 0x00000510); + + /// Pointer to data area used for temporary storage + pub const SCRATCHPTR = @intToPtr(*volatile u32, Address + 0x00000514); +}; + +/// Watchdog Timer +pub const WDT = extern struct { + pub const Address: u32 = 0x40010000; + + /// Start the watchdog + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Watchdog timeout + pub const EVENTS_TIMEOUT = @intToPtr(*volatile u32, Address + 0x00000100); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for TIMEOUT event + TIMEOUT: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for TIMEOUT event + TIMEOUT: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Run status + pub const RUNSTATUS = mmio(Address + 0x00000400, 32, packed struct { + /// Indicates whether or not the watchdog is running + RUNSTATUS: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Request status + pub const REQSTATUS = mmio(Address + 0x00000404, 32, packed struct { + /// Request status for RR[0] register + RR0: u1 = 0, + /// Request status for RR[1] register + RR1: u1 = 0, + /// Request status for RR[2] register + RR2: u1 = 0, + /// Request status for RR[3] register + RR3: u1 = 0, + /// Request status for RR[4] register + RR4: u1 = 0, + /// Request status for RR[5] register + RR5: u1 = 0, + /// Request status for RR[6] register + RR6: u1 = 0, + /// Request status for RR[7] register + RR7: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Counter reload value + pub const CRV = @intToPtr(*volatile u32, Address + 0x00000504); + + /// Enable register for reload request registers + pub const RREN = mmio(Address + 0x00000508, 32, packed struct { + /// Enable or disable RR[0] register + RR0: u1 = 0, + /// Enable or disable RR[1] register + RR1: u1 = 0, + /// Enable or disable RR[2] register + RR2: u1 = 0, + /// Enable or disable RR[3] register + RR3: u1 = 0, + /// Enable or disable RR[4] register + RR4: u1 = 0, + /// Enable or disable RR[5] register + RR5: u1 = 0, + /// Enable or disable RR[6] register + RR6: u1 = 0, + /// Enable or disable RR[7] register + RR7: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration register + pub const CONFIG = mmio(Address + 0x0000050c, 32, packed struct { + /// Configure the watchdog to either be paused, or kept running, while the CPU + /// is sleeping + SLEEP: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Configure the watchdog to either be paused, or kept running, while the CPU + /// is halted by the debugger + HALT: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Reload request 0 + pub const RR = @intToPtr(*volatile [8]u32, Address + 0x00000600); +}; + +/// Real time counter 1 +pub const RTC1 = extern struct { + pub const Address: u32 = 0x40011000; + + /// Start RTC COUNTER + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop RTC COUNTER + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Clear RTC COUNTER + pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Set COUNTER to 0xFFFFF0 + pub const TASKS_TRIGOVRFLW = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Event on COUNTER increment + pub const EVENTS_TICK = @intToPtr(*volatile u32, Address + 0x00000100); + + /// Event on COUNTER overflow + pub const EVENTS_OVRFLW = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for TICK event + TICK: u1 = 0, + /// Write '1' to Enable interrupt for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for TICK event + TICK: u1 = 0, + /// Write '1' to Disable interrupt for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable event routing + pub const EVTEN = mmio(Address + 0x00000340, 32, packed struct { + /// Enable or disable event routing for TICK event + TICK: u1 = 0, + /// Enable or disable event routing for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Enable or disable event routing for COMPARE[0] event + COMPARE0: u1 = 0, + /// Enable or disable event routing for COMPARE[1] event + COMPARE1: u1 = 0, + /// Enable or disable event routing for COMPARE[2] event + COMPARE2: u1 = 0, + /// Enable or disable event routing for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable event routing + pub const EVTENSET = mmio(Address + 0x00000344, 32, packed struct { + /// Write '1' to Enable event routing for TICK event + TICK: u1 = 0, + /// Write '1' to Enable event routing for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable event routing for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Enable event routing for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Enable event routing for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Enable event routing for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable event routing + pub const EVTENCLR = mmio(Address + 0x00000348, 32, packed struct { + /// Write '1' to Disable event routing for TICK event + TICK: u1 = 0, + /// Write '1' to Disable event routing for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable event routing for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Disable event routing for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Disable event routing for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Disable event routing for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Current COUNTER value + pub const COUNTER = mmio(Address + 0x00000504, 32, packed struct { + /// Counter value + COUNTER: u24 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written + /// when RTC is stopped + pub const PRESCALER = mmio(Address + 0x00000508, 32, packed struct { + /// Prescaler value + PRESCALER: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [4]u32, Address + 0x00000140); + /// Description collection[0]: Compare register 0 + pub const CC = @intToPtr(*volatile [4]MMIO(32, packed struct { + /// Compare value + COMPARE: u24 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }), Address + 0x00000540); +}; + +/// Quadrature Decoder +pub const QDEC = extern struct { + pub const Address: u32 = 0x40012000; + + /// Task starting the quadrature decoder + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Task stopping the quadrature decoder + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Read and clear ACC and ACCDBL + pub const TASKS_READCLRACC = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Read and clear ACC + pub const TASKS_RDCLRACC = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Read and clear ACCDBL + pub const TASKS_RDCLRDBL = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Event being generated for every new sample value written to the SAMPLE + /// register + pub const EVENTS_SAMPLERDY = @intToPtr(*volatile u32, Address + 0x00000100); + + /// Non-null report ready + pub const EVENTS_REPORTRDY = @intToPtr(*volatile u32, Address + 0x00000104); + + /// ACC or ACCDBL register overflow + pub const EVENTS_ACCOF = @intToPtr(*volatile u32, Address + 0x00000108); + + /// Double displacement(s) detected + pub const EVENTS_DBLRDY = @intToPtr(*volatile u32, Address + 0x0000010c); + + /// QDEC has been stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000110); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between REPORTRDY event and READCLRACC task + REPORTRDY_READCLRACC: u1 = 0, + /// Shortcut between SAMPLERDY event and STOP task + SAMPLERDY_STOP: u1 = 0, + /// Shortcut between REPORTRDY event and RDCLRACC task + REPORTRDY_RDCLRACC: u1 = 0, + /// Shortcut between REPORTRDY event and STOP task + REPORTRDY_STOP: u1 = 0, + /// Shortcut between DBLRDY event and RDCLRDBL task + DBLRDY_RDCLRDBL: u1 = 0, + /// Shortcut between DBLRDY event and STOP task + DBLRDY_STOP: u1 = 0, + /// Shortcut between SAMPLERDY event and READCLRACC task + SAMPLERDY_READCLRACC: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for SAMPLERDY event + SAMPLERDY: u1 = 0, + /// Write '1' to Enable interrupt for REPORTRDY event + REPORTRDY: u1 = 0, + /// Write '1' to Enable interrupt for ACCOF event + ACCOF: u1 = 0, + /// Write '1' to Enable interrupt for DBLRDY event + DBLRDY: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for SAMPLERDY event + SAMPLERDY: u1 = 0, + /// Write '1' to Disable interrupt for REPORTRDY event + REPORTRDY: u1 = 0, + /// Write '1' to Disable interrupt for ACCOF event + ACCOF: u1 = 0, + /// Write '1' to Disable interrupt for DBLRDY event + DBLRDY: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable the quadrature decoder + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable the quadrature decoder + ENABLE: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// LED output pin polarity + pub const LEDPOL = mmio(Address + 0x00000504, 32, packed struct { + /// LED output pin polarity + LEDPOL: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Sample period + pub const SAMPLEPER = mmio(Address + 0x00000508, 32, packed struct { + /// Sample period. The SAMPLE register will be updated for every new sample + SAMPLEPER: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Motion sample value + pub const SAMPLE = @intToPtr(*volatile u32, Address + 0x0000050c); + + /// Number of samples to be taken before REPORTRDY and DBLRDY events can be + /// generated + pub const REPORTPER = mmio(Address + 0x00000510, 32, packed struct { + /// Specifies the number of samples to be accumulated in the ACC register before + /// the REPORTRDY and DBLRDY events can be generated + REPORTPER: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Register accumulating the valid transitions + pub const ACC = @intToPtr(*volatile u32, Address + 0x00000514); + + /// Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task + pub const ACCREAD = @intToPtr(*volatile u32, Address + 0x00000518); + + /// Enable input debounce filters + pub const DBFEN = mmio(Address + 0x00000528, 32, packed struct { + /// Enable input debounce filters + DBFEN: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Time period the LED is switched ON prior to sampling + pub const LEDPRE = mmio(Address + 0x00000540, 32, packed struct { + /// Period in us the LED is switched on prior to sampling + LEDPRE: u9 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Register accumulating the number of detected double transitions + pub const ACCDBL = mmio(Address + 0x00000544, 32, packed struct { + /// Register accumulating the number of detected double or illegal transitions. + /// ( SAMPLE = 2 ). + ACCDBL: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task + pub const ACCDBLREAD = mmio(Address + 0x00000548, 32, packed struct { + /// Snapshot of the ACCDBL register. This field is updated when the READCLRACC + /// or RDCLRDBL task is triggered. + ACCDBLREAD: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + pub const PSEL = struct { + + /// Pin select for LED signal + pub const LED = mmio(Address + 0x00000000, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for A signal + pub const A = mmio(Address + 0x00000004, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for B signal + pub const B = mmio(Address + 0x00000008, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + }; +}; + +/// Comparator +pub const COMP = extern struct { + pub const Address: u32 = 0x40013000; + + /// Start comparator + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop comparator + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Sample comparator value + pub const TASKS_SAMPLE = @intToPtr(*volatile u32, Address + 0x00000008); + + /// COMP is ready and output is valid + pub const EVENTS_READY = @intToPtr(*volatile u32, Address + 0x00000100); + + /// Downward crossing + pub const EVENTS_DOWN = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Upward crossing + pub const EVENTS_UP = @intToPtr(*volatile u32, Address + 0x00000108); + + /// Downward or upward crossing + pub const EVENTS_CROSS = @intToPtr(*volatile u32, Address + 0x0000010c); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between READY event and SAMPLE task + READY_SAMPLE: u1 = 0, + /// Shortcut between READY event and STOP task + READY_STOP: u1 = 0, + /// Shortcut between DOWN event and STOP task + DOWN_STOP: u1 = 0, + /// Shortcut between UP event and STOP task + UP_STOP: u1 = 0, + /// Shortcut between CROSS event and STOP task + CROSS_STOP: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + /// Enable or disable interrupt for READY event + READY: u1 = 0, + /// Enable or disable interrupt for DOWN event + DOWN: u1 = 0, + /// Enable or disable interrupt for UP event + UP: u1 = 0, + /// Enable or disable interrupt for CROSS event + CROSS: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for READY event + READY: u1 = 0, + /// Write '1' to Enable interrupt for DOWN event + DOWN: u1 = 0, + /// Write '1' to Enable interrupt for UP event + UP: u1 = 0, + /// Write '1' to Enable interrupt for CROSS event + CROSS: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for READY event + READY: u1 = 0, + /// Write '1' to Disable interrupt for DOWN event + DOWN: u1 = 0, + /// Write '1' to Disable interrupt for UP event + UP: u1 = 0, + /// Write '1' to Disable interrupt for CROSS event + CROSS: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Compare result + pub const RESULT = mmio(Address + 0x00000400, 32, packed struct { + /// Result of last compare. Decision point SAMPLE task. + RESULT: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// COMP enable + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable COMP + ENABLE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Pin select + pub const PSEL = mmio(Address + 0x00000504, 32, packed struct { + /// Analog pin select + PSEL: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Reference source select for single-ended mode + pub const REFSEL = mmio(Address + 0x00000508, 32, packed struct { + /// Reference select + REFSEL: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// External reference select + pub const EXTREFSEL = mmio(Address + 0x0000050c, 32, packed struct { + /// External analog reference select + EXTREFSEL: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Threshold configuration for hysteresis unit + pub const TH = mmio(Address + 0x00000530, 32, packed struct { + /// VDOWN = (THDOWN+1)/64*VREF + THDOWN: u6 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// VUP = (THUP+1)/64*VREF + THUP: u6 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Mode configuration + pub const MODE = mmio(Address + 0x00000534, 32, packed struct { + /// Speed and power modes + SP: u2 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Main operation modes + MAIN: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Comparator hysteresis enable + pub const HYST = mmio(Address + 0x00000538, 32, packed struct { + /// Comparator hysteresis + HYST: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Current source select on analog input + pub const ISOURCE = mmio(Address + 0x0000053c, 32, packed struct { + /// Comparator hysteresis + ISOURCE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// Low Power Comparator +pub const LPCOMP = extern struct { + pub const Address: u32 = 0x40013000; + + /// Start comparator + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop comparator + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Sample comparator value + pub const TASKS_SAMPLE = @intToPtr(*volatile u32, Address + 0x00000008); + + /// LPCOMP is ready and output is valid + pub const EVENTS_READY = @intToPtr(*volatile u32, Address + 0x00000100); + + /// Downward crossing + pub const EVENTS_DOWN = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Upward crossing + pub const EVENTS_UP = @intToPtr(*volatile u32, Address + 0x00000108); + + /// Downward or upward crossing + pub const EVENTS_CROSS = @intToPtr(*volatile u32, Address + 0x0000010c); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between READY event and SAMPLE task + READY_SAMPLE: u1 = 0, + /// Shortcut between READY event and STOP task + READY_STOP: u1 = 0, + /// Shortcut between DOWN event and STOP task + DOWN_STOP: u1 = 0, + /// Shortcut between UP event and STOP task + UP_STOP: u1 = 0, + /// Shortcut between CROSS event and STOP task + CROSS_STOP: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for READY event + READY: u1 = 0, + /// Write '1' to Enable interrupt for DOWN event + DOWN: u1 = 0, + /// Write '1' to Enable interrupt for UP event + UP: u1 = 0, + /// Write '1' to Enable interrupt for CROSS event + CROSS: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for READY event + READY: u1 = 0, + /// Write '1' to Disable interrupt for DOWN event + DOWN: u1 = 0, + /// Write '1' to Disable interrupt for UP event + UP: u1 = 0, + /// Write '1' to Disable interrupt for CROSS event + CROSS: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Compare result + pub const RESULT = mmio(Address + 0x00000400, 32, packed struct { + /// Result of last compare. Decision point SAMPLE task. + RESULT: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable LPCOMP + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable LPCOMP + ENABLE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Input pin select + pub const PSEL = mmio(Address + 0x00000504, 32, packed struct { + /// Analog pin select + PSEL: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Reference select + pub const REFSEL = mmio(Address + 0x00000508, 32, packed struct { + /// Reference select + REFSEL: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// External reference select + pub const EXTREFSEL = mmio(Address + 0x0000050c, 32, packed struct { + /// External analog reference select + EXTREFSEL: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Analog detect configuration + pub const ANADETECT = mmio(Address + 0x00000520, 32, packed struct { + /// Analog detect configuration + ANADETECT: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Comparator hysteresis enable + pub const HYST = mmio(Address + 0x00000538, 32, packed struct { + /// Comparator hysteresis enable + HYST: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// Software interrupt 0 +pub const SWI0 = extern struct { + pub const Address: u32 = 0x40014000; + + /// Unused. + pub const UNUSED = @intToPtr(*volatile u32, Address + 0x00000000); +}; + +/// Event Generator Unit 0 +pub const EGU0 = extern struct { + pub const Address: u32 = 0x40014000; + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + /// Enable or disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Trigger 0 for triggering the corresponding + /// TRIGGERED[0] event + pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, Address + 0x00000000); + /// Description collection[0]: Event number 0 generated by triggering the + /// corresponding TRIGGER[0] task + pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, Address + 0x00000100); +}; + +/// Software interrupt 1 +pub const SWI1 = extern struct { + pub const Address: u32 = 0x40015000; + + /// Unused. + pub const UNUSED = @intToPtr(*volatile u32, Address + 0x00000000); +}; + +/// Event Generator Unit 1 +pub const EGU1 = extern struct { + pub const Address: u32 = 0x40015000; + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + /// Enable or disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Trigger 0 for triggering the corresponding + /// TRIGGERED[0] event + pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, Address + 0x00000000); + /// Description collection[0]: Event number 0 generated by triggering the + /// corresponding TRIGGER[0] task + pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, Address + 0x00000100); +}; + +/// Software interrupt 2 +pub const SWI2 = extern struct { + pub const Address: u32 = 0x40016000; + + /// Unused. + pub const UNUSED = @intToPtr(*volatile u32, Address + 0x00000000); +}; + +/// Event Generator Unit 2 +pub const EGU2 = extern struct { + pub const Address: u32 = 0x40016000; + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + /// Enable or disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Trigger 0 for triggering the corresponding + /// TRIGGERED[0] event + pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, Address + 0x00000000); + /// Description collection[0]: Event number 0 generated by triggering the + /// corresponding TRIGGER[0] task + pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, Address + 0x00000100); +}; + +/// Software interrupt 3 +pub const SWI3 = extern struct { + pub const Address: u32 = 0x40017000; + + /// Unused. + pub const UNUSED = @intToPtr(*volatile u32, Address + 0x00000000); +}; + +/// Event Generator Unit 3 +pub const EGU3 = extern struct { + pub const Address: u32 = 0x40017000; + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + /// Enable or disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Trigger 0 for triggering the corresponding + /// TRIGGERED[0] event + pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, Address + 0x00000000); + /// Description collection[0]: Event number 0 generated by triggering the + /// corresponding TRIGGER[0] task + pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, Address + 0x00000100); +}; + +/// Software interrupt 4 +pub const SWI4 = extern struct { + pub const Address: u32 = 0x40018000; + + /// Unused. + pub const UNUSED = @intToPtr(*volatile u32, Address + 0x00000000); +}; + +/// Event Generator Unit 4 +pub const EGU4 = extern struct { + pub const Address: u32 = 0x40018000; + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + /// Enable or disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Trigger 0 for triggering the corresponding + /// TRIGGERED[0] event + pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, Address + 0x00000000); + /// Description collection[0]: Event number 0 generated by triggering the + /// corresponding TRIGGER[0] task + pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, Address + 0x00000100); +}; + +/// Software interrupt 5 +pub const SWI5 = extern struct { + pub const Address: u32 = 0x40019000; + + /// Unused. + pub const UNUSED = @intToPtr(*volatile u32, Address + 0x00000000); +}; + +/// Event Generator Unit 5 +pub const EGU5 = extern struct { + pub const Address: u32 = 0x40019000; + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + /// Enable or disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Trigger 0 for triggering the corresponding + /// TRIGGERED[0] event + pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, Address + 0x00000000); + /// Description collection[0]: Event number 0 generated by triggering the + /// corresponding TRIGGER[0] task + pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, Address + 0x00000100); +}; + +/// Timer/Counter 3 +pub const TIMER3 = extern struct { + pub const Address: u32 = 0x4001a000; + + /// Start Timer + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop Timer + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Increment Timer (Counter mode only) + pub const TASKS_COUNT = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Clear time + pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Deprecated register - Shut down timer + pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between COMPARE[0] event and CLEAR task + COMPARE0_CLEAR: u1 = 0, + /// Shortcut between COMPARE[1] event and CLEAR task + COMPARE1_CLEAR: u1 = 0, + /// Shortcut between COMPARE[2] event and CLEAR task + COMPARE2_CLEAR: u1 = 0, + /// Shortcut between COMPARE[3] event and CLEAR task + COMPARE3_CLEAR: u1 = 0, + /// Shortcut between COMPARE[4] event and CLEAR task + COMPARE4_CLEAR: u1 = 0, + /// Shortcut between COMPARE[5] event and CLEAR task + COMPARE5_CLEAR: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between COMPARE[0] event and STOP task + COMPARE0_STOP: u1 = 0, + /// Shortcut between COMPARE[1] event and STOP task + COMPARE1_STOP: u1 = 0, + /// Shortcut between COMPARE[2] event and STOP task + COMPARE2_STOP: u1 = 0, + /// Shortcut between COMPARE[3] event and STOP task + COMPARE3_STOP: u1 = 0, + /// Shortcut between COMPARE[4] event and STOP task + COMPARE4_STOP: u1 = 0, + /// Shortcut between COMPARE[5] event and STOP task + COMPARE5_STOP: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[4] event + COMPARE4: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[5] event + COMPARE5: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[4] event + COMPARE4: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[5] event + COMPARE5: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Timer mode selection + pub const MODE = mmio(Address + 0x00000504, 32, packed struct { + /// Timer mode + MODE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configure the number of bits used by the TIMER + pub const BITMODE = mmio(Address + 0x00000508, 32, packed struct { + /// Timer bit width + BITMODE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Timer prescaler register + pub const PRESCALER = mmio(Address + 0x00000510, 32, packed struct { + /// Prescaler value + PRESCALER: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Capture Timer value to CC[0] register + pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, Address + 0x00000040); + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, Address + 0x00000140); + /// Description collection[0]: Capture/Compare register 0 + pub const CC = @intToPtr(*volatile [6]u32, Address + 0x00000540); +}; + +/// Timer/Counter 4 +pub const TIMER4 = extern struct { + pub const Address: u32 = 0x4001b000; + + /// Start Timer + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop Timer + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Increment Timer (Counter mode only) + pub const TASKS_COUNT = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Clear time + pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Deprecated register - Shut down timer + pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between COMPARE[0] event and CLEAR task + COMPARE0_CLEAR: u1 = 0, + /// Shortcut between COMPARE[1] event and CLEAR task + COMPARE1_CLEAR: u1 = 0, + /// Shortcut between COMPARE[2] event and CLEAR task + COMPARE2_CLEAR: u1 = 0, + /// Shortcut between COMPARE[3] event and CLEAR task + COMPARE3_CLEAR: u1 = 0, + /// Shortcut between COMPARE[4] event and CLEAR task + COMPARE4_CLEAR: u1 = 0, + /// Shortcut between COMPARE[5] event and CLEAR task + COMPARE5_CLEAR: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between COMPARE[0] event and STOP task + COMPARE0_STOP: u1 = 0, + /// Shortcut between COMPARE[1] event and STOP task + COMPARE1_STOP: u1 = 0, + /// Shortcut between COMPARE[2] event and STOP task + COMPARE2_STOP: u1 = 0, + /// Shortcut between COMPARE[3] event and STOP task + COMPARE3_STOP: u1 = 0, + /// Shortcut between COMPARE[4] event and STOP task + COMPARE4_STOP: u1 = 0, + /// Shortcut between COMPARE[5] event and STOP task + COMPARE5_STOP: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[4] event + COMPARE4: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[5] event + COMPARE5: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[4] event + COMPARE4: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[5] event + COMPARE5: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Timer mode selection + pub const MODE = mmio(Address + 0x00000504, 32, packed struct { + /// Timer mode + MODE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configure the number of bits used by the TIMER + pub const BITMODE = mmio(Address + 0x00000508, 32, packed struct { + /// Timer bit width + BITMODE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Timer prescaler register + pub const PRESCALER = mmio(Address + 0x00000510, 32, packed struct { + /// Prescaler value + PRESCALER: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Capture Timer value to CC[0] register + pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, Address + 0x00000040); + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, Address + 0x00000140); + /// Description collection[0]: Capture/Compare register 0 + pub const CC = @intToPtr(*volatile [6]u32, Address + 0x00000540); +}; + +/// Pulse Width Modulation Unit 0 +pub const PWM0 = extern struct { + pub const Address: u32 = 0x4001c000; + + /// Stops PWM pulse generation on all channels at the end of current PWM period, + /// and stops sequence playback + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Steps by one value in the current sequence on all enabled channels if + /// DECODER.MODE=NextStep. Does not cause PWM generation to start it was not + /// running. + pub const TASKS_NEXTSTEP = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Response to STOP task, emitted when PWM pulses are no longer generated + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Emitted at the end of each PWM period + pub const EVENTS_PWMPERIODEND = @intToPtr(*volatile u32, Address + 0x00000118); + + /// Concatenated sequences have been played the amount of times defined in + /// LOOP.CNT + pub const EVENTS_LOOPSDONE = @intToPtr(*volatile u32, Address + 0x0000011c); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between SEQEND[0] event and STOP task + SEQEND0_STOP: u1 = 0, + /// Shortcut between SEQEND[1] event and STOP task + SEQEND1_STOP: u1 = 0, + /// Shortcut between LOOPSDONE event and SEQSTART[0] task + LOOPSDONE_SEQSTART0: u1 = 0, + /// Shortcut between LOOPSDONE event and SEQSTART[1] task + LOOPSDONE_SEQSTART1: u1 = 0, + /// Shortcut between LOOPSDONE event and STOP task + LOOPSDONE_STOP: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + reserved1: u1 = 0, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Enable or disable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1 = 0, + /// Enable or disable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1 = 0, + /// Enable or disable interrupt for SEQEND[0] event + SEQEND0: u1 = 0, + /// Enable or disable interrupt for SEQEND[1] event + SEQEND1: u1 = 0, + /// Enable or disable interrupt for PWMPERIODEND event + PWMPERIODEND: u1 = 0, + /// Enable or disable interrupt for LOOPSDONE event + LOOPSDONE: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Write '1' to Enable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1 = 0, + /// Write '1' to Enable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1 = 0, + /// Write '1' to Enable interrupt for SEQEND[0] event + SEQEND0: u1 = 0, + /// Write '1' to Enable interrupt for SEQEND[1] event + SEQEND1: u1 = 0, + /// Write '1' to Enable interrupt for PWMPERIODEND event + PWMPERIODEND: u1 = 0, + /// Write '1' to Enable interrupt for LOOPSDONE event + LOOPSDONE: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Write '1' to Disable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1 = 0, + /// Write '1' to Disable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1 = 0, + /// Write '1' to Disable interrupt for SEQEND[0] event + SEQEND0: u1 = 0, + /// Write '1' to Disable interrupt for SEQEND[1] event + SEQEND1: u1 = 0, + /// Write '1' to Disable interrupt for PWMPERIODEND event + PWMPERIODEND: u1 = 0, + /// Write '1' to Disable interrupt for LOOPSDONE event + LOOPSDONE: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// PWM module enable register + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable PWM module + ENABLE: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Selects operating mode of the wave counter + pub const MODE = mmio(Address + 0x00000504, 32, packed struct { + /// Selects up or up and down as wave counter mode + UPDOWN: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Value up to which the pulse generator counter counts + pub const COUNTERTOP = mmio(Address + 0x00000508, 32, packed struct { + /// Value up to which the pulse generator counter counts. This register is + /// ignored when DECODER.MODE=WaveForm and only values from RAM will be used. + COUNTERTOP: u15 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration for PWM_CLK + pub const PRESCALER = mmio(Address + 0x0000050c, 32, packed struct { + /// Pre-scaler of PWM_CLK + PRESCALER: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration of the decoder + pub const DECODER = mmio(Address + 0x00000510, 32, packed struct { + /// How a sequence is read from RAM and spread to the compare register + LOAD: u2 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Selects source for advancing the active sequence + MODE: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Amount of playback of a loop + pub const LOOP = mmio(Address + 0x00000514, 32, packed struct { + /// Amount of playback of pattern cycles + CNT: u16 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Loads the first PWM value on all enabled channels + /// from sequence 0, and starts playing that sequence at the rate defined in + /// SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not + /// running. + pub const TASKS_SEQSTART = @intToPtr(*volatile [2]u32, Address + 0x00000008); + /// Description collection[0]: First PWM period started on sequence 0 + pub const EVENTS_SEQSTARTED = @intToPtr(*volatile [2]u32, Address + 0x00000108); + /// Description collection[0]: Emitted at end of every sequence 0, when last + /// value from RAM has been applied to wave counter + pub const EVENTS_SEQEND = @intToPtr(*volatile [2]u32, Address + 0x00000110); + + pub const PSEL = struct { + /// Description collection[0]: Output pin select for PWM channel 0 + pub const OUT = @intToPtr(*volatile [4]MMIO(32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }), Address + 0x00000000); + }; +}; + +/// Pulse Density Modulation (Digital Microphone) Interface +pub const PDM = extern struct { + pub const Address: u32 = 0x4001d000; + + /// Starts continuous PDM transfer + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stops PDM transfer + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// PDM transfer has started + pub const EVENTS_STARTED = @intToPtr(*volatile u32, Address + 0x00000100); + + /// PDM transfer has finished + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last + /// sample after a STOP task has been received) to Data RAM + pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000108); + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + /// Enable or disable interrupt for STARTED event + STARTED: u1 = 0, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Enable or disable interrupt for END event + END: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for STARTED event + STARTED: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Write '1' to Enable interrupt for END event + END: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for STARTED event + STARTED: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Write '1' to Disable interrupt for END event + END: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// PDM module enable register + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable PDM module + ENABLE: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// PDM clock generator control + pub const PDMCLKCTRL = mmio(Address + 0x00000504, 32, packed struct { + /// PDM_CLK frequency + FREQ: u32 = 0, + }); + + /// Defines the routing of the connected PDM microphones' signals + pub const MODE = mmio(Address + 0x00000508, 32, packed struct { + /// Mono or stereo operation + OPERATION: u1 = 0, + /// Defines on which PDM_CLK edge Left (or mono) is sampled + EDGE: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Left output gain adjustment + pub const GAINL = mmio(Address + 0x00000518, 32, packed struct { + /// Left output gain adjustment, in 0.5 dB steps, around the default module gain + /// (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain + /// adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB + /// gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust + GAINL: u7 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Right output gain adjustment + pub const GAINR = mmio(Address + 0x0000051c, 32, packed struct { + /// Right output gain adjustment, in 0.5 dB steps, around the default module + /// gain (see electrical parameters) + GAINR: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + pub const PSEL = struct { + + /// Pin number configuration for PDM CLK signal + pub const CLK = mmio(Address + 0x00000000, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin number configuration for PDM DIN signal + pub const DIN = mmio(Address + 0x00000004, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + }; + + pub const SAMPLE = struct { + + /// RAM address pointer to write samples to with EasyDMA + pub const PTR = mmio(Address + 0x00000000, 32, packed struct { + /// Address to write PDM samples to over DMA + SAMPLEPTR: u32 = 0, + }); + + /// Number of samples to allocate memory for in EasyDMA mode + pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// Length of DMA RAM allocation in number of samples + BUFFSIZE: u15 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; +}; + +/// Non Volatile Memory Controller +pub const NVMC = extern struct { + pub const Address: u32 = 0x4001e000; + + /// Ready flag + pub const READY = mmio(Address + 0x00000400, 32, packed struct { + /// NVMC is ready or busy + READY: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration register + pub const CONFIG = mmio(Address + 0x00000504, 32, packed struct { + /// Program memory access mode. It is strongly recommended to only activate + /// erase and write modes when they are actively used. Enabling write or erase + /// will invalidate the cache and keep it invalidated. + WEN: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Register for erasing a page in Code area + pub const ERASEPAGE = @intToPtr(*volatile u32, Address + 0x00000508); + + /// Deprecated register - Register for erasing a page in Code area. Equivalent + /// to ERASEPAGE. + pub const ERASEPCR1 = @intToPtr(*volatile u32, Address + 0x00000508); + + /// Register for erasing all non-volatile user memory + pub const ERASEALL = mmio(Address + 0x0000050c, 32, packed struct { + /// Erase all non-volatile memory including UICR registers. Note that code erase + /// has to be enabled by CONFIG.EEN before the UICR can be erased. + ERASEALL: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Deprecated register - Register for erasing a page in Code area. Equivalent + /// to ERASEPAGE. + pub const ERASEPCR0 = @intToPtr(*volatile u32, Address + 0x00000510); + + /// Register for erasing User Information Configuration Registers + pub const ERASEUICR = mmio(Address + 0x00000514, 32, packed struct { + /// Register starting erase of all User Information Configuration Registers. + /// Note that code erase has to be enabled by CONFIG.EEN before the UICR can be + /// erased. + ERASEUICR: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// I-Code cache configuration register. + pub const ICACHECNF = mmio(Address + 0x00000540, 32, packed struct { + /// Cache enable + CACHEEN: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Cache profiling enable + CACHEPROFEN: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// I-Code cache hit counter. + pub const IHIT = mmio(Address + 0x00000548, 32, packed struct { + /// Number of cache hits + HITS: u32 = 0, + }); + + /// I-Code cache miss counter. + pub const IMISS = mmio(Address + 0x0000054c, 32, packed struct { + /// Number of cache misses + MISSES: u32 = 0, + }); +}; + +/// Programmable Peripheral Interconnect +pub const PPI = extern struct { + pub const Address: u32 = 0x4001f000; + + /// Channel enable register + pub const CHEN = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable channel 0 + CH0: u1 = 0, + /// Enable or disable channel 1 + CH1: u1 = 0, + /// Enable or disable channel 2 + CH2: u1 = 0, + /// Enable or disable channel 3 + CH3: u1 = 0, + /// Enable or disable channel 4 + CH4: u1 = 0, + /// Enable or disable channel 5 + CH5: u1 = 0, + /// Enable or disable channel 6 + CH6: u1 = 0, + /// Enable or disable channel 7 + CH7: u1 = 0, + /// Enable or disable channel 8 + CH8: u1 = 0, + /// Enable or disable channel 9 + CH9: u1 = 0, + /// Enable or disable channel 10 + CH10: u1 = 0, + /// Enable or disable channel 11 + CH11: u1 = 0, + /// Enable or disable channel 12 + CH12: u1 = 0, + /// Enable or disable channel 13 + CH13: u1 = 0, + /// Enable or disable channel 14 + CH14: u1 = 0, + /// Enable or disable channel 15 + CH15: u1 = 0, + /// Enable or disable channel 16 + CH16: u1 = 0, + /// Enable or disable channel 17 + CH17: u1 = 0, + /// Enable or disable channel 18 + CH18: u1 = 0, + /// Enable or disable channel 19 + CH19: u1 = 0, + /// Enable or disable channel 20 + CH20: u1 = 0, + /// Enable or disable channel 21 + CH21: u1 = 0, + /// Enable or disable channel 22 + CH22: u1 = 0, + /// Enable or disable channel 23 + CH23: u1 = 0, + /// Enable or disable channel 24 + CH24: u1 = 0, + /// Enable or disable channel 25 + CH25: u1 = 0, + /// Enable or disable channel 26 + CH26: u1 = 0, + /// Enable or disable channel 27 + CH27: u1 = 0, + /// Enable or disable channel 28 + CH28: u1 = 0, + /// Enable or disable channel 29 + CH29: u1 = 0, + /// Enable or disable channel 30 + CH30: u1 = 0, + /// Enable or disable channel 31 + CH31: u1 = 0, + }); + + /// Channel enable set register + pub const CHENSET = mmio(Address + 0x00000504, 32, packed struct { + /// Channel 0 enable set register. Writing '0' has no effect + CH0: u1 = 0, + /// Channel 1 enable set register. Writing '0' has no effect + CH1: u1 = 0, + /// Channel 2 enable set register. Writing '0' has no effect + CH2: u1 = 0, + /// Channel 3 enable set register. Writing '0' has no effect + CH3: u1 = 0, + /// Channel 4 enable set register. Writing '0' has no effect + CH4: u1 = 0, + /// Channel 5 enable set register. Writing '0' has no effect + CH5: u1 = 0, + /// Channel 6 enable set register. Writing '0' has no effect + CH6: u1 = 0, + /// Channel 7 enable set register. Writing '0' has no effect + CH7: u1 = 0, + /// Channel 8 enable set register. Writing '0' has no effect + CH8: u1 = 0, + /// Channel 9 enable set register. Writing '0' has no effect + CH9: u1 = 0, + /// Channel 10 enable set register. Writing '0' has no effect + CH10: u1 = 0, + /// Channel 11 enable set register. Writing '0' has no effect + CH11: u1 = 0, + /// Channel 12 enable set register. Writing '0' has no effect + CH12: u1 = 0, + /// Channel 13 enable set register. Writing '0' has no effect + CH13: u1 = 0, + /// Channel 14 enable set register. Writing '0' has no effect + CH14: u1 = 0, + /// Channel 15 enable set register. Writing '0' has no effect + CH15: u1 = 0, + /// Channel 16 enable set register. Writing '0' has no effect + CH16: u1 = 0, + /// Channel 17 enable set register. Writing '0' has no effect + CH17: u1 = 0, + /// Channel 18 enable set register. Writing '0' has no effect + CH18: u1 = 0, + /// Channel 19 enable set register. Writing '0' has no effect + CH19: u1 = 0, + /// Channel 20 enable set register. Writing '0' has no effect + CH20: u1 = 0, + /// Channel 21 enable set register. Writing '0' has no effect + CH21: u1 = 0, + /// Channel 22 enable set register. Writing '0' has no effect + CH22: u1 = 0, + /// Channel 23 enable set register. Writing '0' has no effect + CH23: u1 = 0, + /// Channel 24 enable set register. Writing '0' has no effect + CH24: u1 = 0, + /// Channel 25 enable set register. Writing '0' has no effect + CH25: u1 = 0, + /// Channel 26 enable set register. Writing '0' has no effect + CH26: u1 = 0, + /// Channel 27 enable set register. Writing '0' has no effect + CH27: u1 = 0, + /// Channel 28 enable set register. Writing '0' has no effect + CH28: u1 = 0, + /// Channel 29 enable set register. Writing '0' has no effect + CH29: u1 = 0, + /// Channel 30 enable set register. Writing '0' has no effect + CH30: u1 = 0, + /// Channel 31 enable set register. Writing '0' has no effect + CH31: u1 = 0, + }); + + /// Channel enable clear register + pub const CHENCLR = mmio(Address + 0x00000508, 32, packed struct { + /// Channel 0 enable clear register. Writing '0' has no effect + CH0: u1 = 0, + /// Channel 1 enable clear register. Writing '0' has no effect + CH1: u1 = 0, + /// Channel 2 enable clear register. Writing '0' has no effect + CH2: u1 = 0, + /// Channel 3 enable clear register. Writing '0' has no effect + CH3: u1 = 0, + /// Channel 4 enable clear register. Writing '0' has no effect + CH4: u1 = 0, + /// Channel 5 enable clear register. Writing '0' has no effect + CH5: u1 = 0, + /// Channel 6 enable clear register. Writing '0' has no effect + CH6: u1 = 0, + /// Channel 7 enable clear register. Writing '0' has no effect + CH7: u1 = 0, + /// Channel 8 enable clear register. Writing '0' has no effect + CH8: u1 = 0, + /// Channel 9 enable clear register. Writing '0' has no effect + CH9: u1 = 0, + /// Channel 10 enable clear register. Writing '0' has no effect + CH10: u1 = 0, + /// Channel 11 enable clear register. Writing '0' has no effect + CH11: u1 = 0, + /// Channel 12 enable clear register. Writing '0' has no effect + CH12: u1 = 0, + /// Channel 13 enable clear register. Writing '0' has no effect + CH13: u1 = 0, + /// Channel 14 enable clear register. Writing '0' has no effect + CH14: u1 = 0, + /// Channel 15 enable clear register. Writing '0' has no effect + CH15: u1 = 0, + /// Channel 16 enable clear register. Writing '0' has no effect + CH16: u1 = 0, + /// Channel 17 enable clear register. Writing '0' has no effect + CH17: u1 = 0, + /// Channel 18 enable clear register. Writing '0' has no effect + CH18: u1 = 0, + /// Channel 19 enable clear register. Writing '0' has no effect + CH19: u1 = 0, + /// Channel 20 enable clear register. Writing '0' has no effect + CH20: u1 = 0, + /// Channel 21 enable clear register. Writing '0' has no effect + CH21: u1 = 0, + /// Channel 22 enable clear register. Writing '0' has no effect + CH22: u1 = 0, + /// Channel 23 enable clear register. Writing '0' has no effect + CH23: u1 = 0, + /// Channel 24 enable clear register. Writing '0' has no effect + CH24: u1 = 0, + /// Channel 25 enable clear register. Writing '0' has no effect + CH25: u1 = 0, + /// Channel 26 enable clear register. Writing '0' has no effect + CH26: u1 = 0, + /// Channel 27 enable clear register. Writing '0' has no effect + CH27: u1 = 0, + /// Channel 28 enable clear register. Writing '0' has no effect + CH28: u1 = 0, + /// Channel 29 enable clear register. Writing '0' has no effect + CH29: u1 = 0, + /// Channel 30 enable clear register. Writing '0' has no effect + CH30: u1 = 0, + /// Channel 31 enable clear register. Writing '0' has no effect + CH31: u1 = 0, + }); + /// Description collection[0]: Channel group 0 + pub const CHG = @intToPtr(*volatile [6]MMIO(32, packed struct { + /// Include or exclude channel 0 + CH0: u1 = 0, + /// Include or exclude channel 1 + CH1: u1 = 0, + /// Include or exclude channel 2 + CH2: u1 = 0, + /// Include or exclude channel 3 + CH3: u1 = 0, + /// Include or exclude channel 4 + CH4: u1 = 0, + /// Include or exclude channel 5 + CH5: u1 = 0, + /// Include or exclude channel 6 + CH6: u1 = 0, + /// Include or exclude channel 7 + CH7: u1 = 0, + /// Include or exclude channel 8 + CH8: u1 = 0, + /// Include or exclude channel 9 + CH9: u1 = 0, + /// Include or exclude channel 10 + CH10: u1 = 0, + /// Include or exclude channel 11 + CH11: u1 = 0, + /// Include or exclude channel 12 + CH12: u1 = 0, + /// Include or exclude channel 13 + CH13: u1 = 0, + /// Include or exclude channel 14 + CH14: u1 = 0, + /// Include or exclude channel 15 + CH15: u1 = 0, + /// Include or exclude channel 16 + CH16: u1 = 0, + /// Include or exclude channel 17 + CH17: u1 = 0, + /// Include or exclude channel 18 + CH18: u1 = 0, + /// Include or exclude channel 19 + CH19: u1 = 0, + /// Include or exclude channel 20 + CH20: u1 = 0, + /// Include or exclude channel 21 + CH21: u1 = 0, + /// Include or exclude channel 22 + CH22: u1 = 0, + /// Include or exclude channel 23 + CH23: u1 = 0, + /// Include or exclude channel 24 + CH24: u1 = 0, + /// Include or exclude channel 25 + CH25: u1 = 0, + /// Include or exclude channel 26 + CH26: u1 = 0, + /// Include or exclude channel 27 + CH27: u1 = 0, + /// Include or exclude channel 28 + CH28: u1 = 0, + /// Include or exclude channel 29 + CH29: u1 = 0, + /// Include or exclude channel 30 + CH30: u1 = 0, + /// Include or exclude channel 31 + CH31: u1 = 0, + }), Address + 0x00000800); +}; + +/// Memory Watch Unit +pub const MWU = extern struct { + pub const Address: u32 = 0x40020000; + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + /// Enable or disable interrupt for REGION[0].WA event + REGION0WA: u1 = 0, + /// Enable or disable interrupt for REGION[0].RA event + REGION0RA: u1 = 0, + /// Enable or disable interrupt for REGION[1].WA event + REGION1WA: u1 = 0, + /// Enable or disable interrupt for REGION[1].RA event + REGION1RA: u1 = 0, + /// Enable or disable interrupt for REGION[2].WA event + REGION2WA: u1 = 0, + /// Enable or disable interrupt for REGION[2].RA event + REGION2RA: u1 = 0, + /// Enable or disable interrupt for REGION[3].WA event + REGION3WA: u1 = 0, + /// Enable or disable interrupt for REGION[3].RA event + REGION3RA: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Enable or disable interrupt for PREGION[0].WA event + PREGION0WA: u1 = 0, + /// Enable or disable interrupt for PREGION[0].RA event + PREGION0RA: u1 = 0, + /// Enable or disable interrupt for PREGION[1].WA event + PREGION1WA: u1 = 0, + /// Enable or disable interrupt for PREGION[1].RA event + PREGION1RA: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for REGION[0].WA event + REGION0WA: u1 = 0, + /// Write '1' to Enable interrupt for REGION[0].RA event + REGION0RA: u1 = 0, + /// Write '1' to Enable interrupt for REGION[1].WA event + REGION1WA: u1 = 0, + /// Write '1' to Enable interrupt for REGION[1].RA event + REGION1RA: u1 = 0, + /// Write '1' to Enable interrupt for REGION[2].WA event + REGION2WA: u1 = 0, + /// Write '1' to Enable interrupt for REGION[2].RA event + REGION2RA: u1 = 0, + /// Write '1' to Enable interrupt for REGION[3].WA event + REGION3WA: u1 = 0, + /// Write '1' to Enable interrupt for REGION[3].RA event + REGION3RA: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for PREGION[0].WA event + PREGION0WA: u1 = 0, + /// Write '1' to Enable interrupt for PREGION[0].RA event + PREGION0RA: u1 = 0, + /// Write '1' to Enable interrupt for PREGION[1].WA event + PREGION1WA: u1 = 0, + /// Write '1' to Enable interrupt for PREGION[1].RA event + PREGION1RA: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for REGION[0].WA event + REGION0WA: u1 = 0, + /// Write '1' to Disable interrupt for REGION[0].RA event + REGION0RA: u1 = 0, + /// Write '1' to Disable interrupt for REGION[1].WA event + REGION1WA: u1 = 0, + /// Write '1' to Disable interrupt for REGION[1].RA event + REGION1RA: u1 = 0, + /// Write '1' to Disable interrupt for REGION[2].WA event + REGION2WA: u1 = 0, + /// Write '1' to Disable interrupt for REGION[2].RA event + REGION2RA: u1 = 0, + /// Write '1' to Disable interrupt for REGION[3].WA event + REGION3WA: u1 = 0, + /// Write '1' to Disable interrupt for REGION[3].RA event + REGION3RA: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for PREGION[0].WA event + PREGION0WA: u1 = 0, + /// Write '1' to Disable interrupt for PREGION[0].RA event + PREGION0RA: u1 = 0, + /// Write '1' to Disable interrupt for PREGION[1].WA event + PREGION1WA: u1 = 0, + /// Write '1' to Disable interrupt for PREGION[1].RA event + PREGION1RA: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable non-maskable interrupt + pub const NMIEN = mmio(Address + 0x00000320, 32, packed struct { + /// Enable or disable non-maskable interrupt for REGION[0].WA event + REGION0WA: u1 = 0, + /// Enable or disable non-maskable interrupt for REGION[0].RA event + REGION0RA: u1 = 0, + /// Enable or disable non-maskable interrupt for REGION[1].WA event + REGION1WA: u1 = 0, + /// Enable or disable non-maskable interrupt for REGION[1].RA event + REGION1RA: u1 = 0, + /// Enable or disable non-maskable interrupt for REGION[2].WA event + REGION2WA: u1 = 0, + /// Enable or disable non-maskable interrupt for REGION[2].RA event + REGION2RA: u1 = 0, + /// Enable or disable non-maskable interrupt for REGION[3].WA event + REGION3WA: u1 = 0, + /// Enable or disable non-maskable interrupt for REGION[3].RA event + REGION3RA: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Enable or disable non-maskable interrupt for PREGION[0].WA event + PREGION0WA: u1 = 0, + /// Enable or disable non-maskable interrupt for PREGION[0].RA event + PREGION0RA: u1 = 0, + /// Enable or disable non-maskable interrupt for PREGION[1].WA event + PREGION1WA: u1 = 0, + /// Enable or disable non-maskable interrupt for PREGION[1].RA event + PREGION1RA: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable non-maskable interrupt + pub const NMIENSET = mmio(Address + 0x00000324, 32, packed struct { + /// Write '1' to Enable non-maskable interrupt for REGION[0].WA event + REGION0WA: u1 = 0, + /// Write '1' to Enable non-maskable interrupt for REGION[0].RA event + REGION0RA: u1 = 0, + /// Write '1' to Enable non-maskable interrupt for REGION[1].WA event + REGION1WA: u1 = 0, + /// Write '1' to Enable non-maskable interrupt for REGION[1].RA event + REGION1RA: u1 = 0, + /// Write '1' to Enable non-maskable interrupt for REGION[2].WA event + REGION2WA: u1 = 0, + /// Write '1' to Enable non-maskable interrupt for REGION[2].RA event + REGION2RA: u1 = 0, + /// Write '1' to Enable non-maskable interrupt for REGION[3].WA event + REGION3WA: u1 = 0, + /// Write '1' to Enable non-maskable interrupt for REGION[3].RA event + REGION3RA: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable non-maskable interrupt for PREGION[0].WA event + PREGION0WA: u1 = 0, + /// Write '1' to Enable non-maskable interrupt for PREGION[0].RA event + PREGION0RA: u1 = 0, + /// Write '1' to Enable non-maskable interrupt for PREGION[1].WA event + PREGION1WA: u1 = 0, + /// Write '1' to Enable non-maskable interrupt for PREGION[1].RA event + PREGION1RA: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable non-maskable interrupt + pub const NMIENCLR = mmio(Address + 0x00000328, 32, packed struct { + /// Write '1' to Disable non-maskable interrupt for REGION[0].WA event + REGION0WA: u1 = 0, + /// Write '1' to Disable non-maskable interrupt for REGION[0].RA event + REGION0RA: u1 = 0, + /// Write '1' to Disable non-maskable interrupt for REGION[1].WA event + REGION1WA: u1 = 0, + /// Write '1' to Disable non-maskable interrupt for REGION[1].RA event + REGION1RA: u1 = 0, + /// Write '1' to Disable non-maskable interrupt for REGION[2].WA event + REGION2WA: u1 = 0, + /// Write '1' to Disable non-maskable interrupt for REGION[2].RA event + REGION2RA: u1 = 0, + /// Write '1' to Disable non-maskable interrupt for REGION[3].WA event + REGION3WA: u1 = 0, + /// Write '1' to Disable non-maskable interrupt for REGION[3].RA event + REGION3RA: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable non-maskable interrupt for PREGION[0].WA event + PREGION0WA: u1 = 0, + /// Write '1' to Disable non-maskable interrupt for PREGION[0].RA event + PREGION0RA: u1 = 0, + /// Write '1' to Disable non-maskable interrupt for PREGION[1].WA event + PREGION1WA: u1 = 0, + /// Write '1' to Disable non-maskable interrupt for PREGION[1].RA event + PREGION1RA: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable/disable regions watch + pub const REGIONEN = mmio(Address + 0x00000510, 32, packed struct { + /// Enable/disable write access watch in region[0] + RGN0WA: u1 = 0, + /// Enable/disable read access watch in region[0] + RGN0RA: u1 = 0, + /// Enable/disable write access watch in region[1] + RGN1WA: u1 = 0, + /// Enable/disable read access watch in region[1] + RGN1RA: u1 = 0, + /// Enable/disable write access watch in region[2] + RGN2WA: u1 = 0, + /// Enable/disable read access watch in region[2] + RGN2RA: u1 = 0, + /// Enable/disable write access watch in region[3] + RGN3WA: u1 = 0, + /// Enable/disable read access watch in region[3] + RGN3RA: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Enable/disable write access watch in PREGION[0] + PRGN0WA: u1 = 0, + /// Enable/disable read access watch in PREGION[0] + PRGN0RA: u1 = 0, + /// Enable/disable write access watch in PREGION[1] + PRGN1WA: u1 = 0, + /// Enable/disable read access watch in PREGION[1] + PRGN1RA: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable regions watch + pub const REGIONENSET = mmio(Address + 0x00000514, 32, packed struct { + /// Enable write access watch in region[0] + RGN0WA: u1 = 0, + /// Enable read access watch in region[0] + RGN0RA: u1 = 0, + /// Enable write access watch in region[1] + RGN1WA: u1 = 0, + /// Enable read access watch in region[1] + RGN1RA: u1 = 0, + /// Enable write access watch in region[2] + RGN2WA: u1 = 0, + /// Enable read access watch in region[2] + RGN2RA: u1 = 0, + /// Enable write access watch in region[3] + RGN3WA: u1 = 0, + /// Enable read access watch in region[3] + RGN3RA: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Enable write access watch in PREGION[0] + PRGN0WA: u1 = 0, + /// Enable read access watch in PREGION[0] + PRGN0RA: u1 = 0, + /// Enable write access watch in PREGION[1] + PRGN1WA: u1 = 0, + /// Enable read access watch in PREGION[1] + PRGN1RA: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable regions watch + pub const REGIONENCLR = mmio(Address + 0x00000518, 32, packed struct { + /// Disable write access watch in region[0] + RGN0WA: u1 = 0, + /// Disable read access watch in region[0] + RGN0RA: u1 = 0, + /// Disable write access watch in region[1] + RGN1WA: u1 = 0, + /// Disable read access watch in region[1] + RGN1RA: u1 = 0, + /// Disable write access watch in region[2] + RGN2WA: u1 = 0, + /// Disable read access watch in region[2] + RGN2RA: u1 = 0, + /// Disable write access watch in region[3] + RGN3WA: u1 = 0, + /// Disable read access watch in region[3] + RGN3RA: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Disable write access watch in PREGION[0] + PRGN0WA: u1 = 0, + /// Disable read access watch in PREGION[0] + PRGN0RA: u1 = 0, + /// Disable write access watch in PREGION[1] + PRGN1WA: u1 = 0, + /// Disable read access watch in PREGION[1] + PRGN1RA: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// Pulse Width Modulation Unit 1 +pub const PWM1 = extern struct { + pub const Address: u32 = 0x40021000; + + /// Stops PWM pulse generation on all channels at the end of current PWM period, + /// and stops sequence playback + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Steps by one value in the current sequence on all enabled channels if + /// DECODER.MODE=NextStep. Does not cause PWM generation to start it was not + /// running. + pub const TASKS_NEXTSTEP = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Response to STOP task, emitted when PWM pulses are no longer generated + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Emitted at the end of each PWM period + pub const EVENTS_PWMPERIODEND = @intToPtr(*volatile u32, Address + 0x00000118); + + /// Concatenated sequences have been played the amount of times defined in + /// LOOP.CNT + pub const EVENTS_LOOPSDONE = @intToPtr(*volatile u32, Address + 0x0000011c); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between SEQEND[0] event and STOP task + SEQEND0_STOP: u1 = 0, + /// Shortcut between SEQEND[1] event and STOP task + SEQEND1_STOP: u1 = 0, + /// Shortcut between LOOPSDONE event and SEQSTART[0] task + LOOPSDONE_SEQSTART0: u1 = 0, + /// Shortcut between LOOPSDONE event and SEQSTART[1] task + LOOPSDONE_SEQSTART1: u1 = 0, + /// Shortcut between LOOPSDONE event and STOP task + LOOPSDONE_STOP: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + reserved1: u1 = 0, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Enable or disable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1 = 0, + /// Enable or disable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1 = 0, + /// Enable or disable interrupt for SEQEND[0] event + SEQEND0: u1 = 0, + /// Enable or disable interrupt for SEQEND[1] event + SEQEND1: u1 = 0, + /// Enable or disable interrupt for PWMPERIODEND event + PWMPERIODEND: u1 = 0, + /// Enable or disable interrupt for LOOPSDONE event + LOOPSDONE: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Write '1' to Enable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1 = 0, + /// Write '1' to Enable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1 = 0, + /// Write '1' to Enable interrupt for SEQEND[0] event + SEQEND0: u1 = 0, + /// Write '1' to Enable interrupt for SEQEND[1] event + SEQEND1: u1 = 0, + /// Write '1' to Enable interrupt for PWMPERIODEND event + PWMPERIODEND: u1 = 0, + /// Write '1' to Enable interrupt for LOOPSDONE event + LOOPSDONE: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Write '1' to Disable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1 = 0, + /// Write '1' to Disable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1 = 0, + /// Write '1' to Disable interrupt for SEQEND[0] event + SEQEND0: u1 = 0, + /// Write '1' to Disable interrupt for SEQEND[1] event + SEQEND1: u1 = 0, + /// Write '1' to Disable interrupt for PWMPERIODEND event + PWMPERIODEND: u1 = 0, + /// Write '1' to Disable interrupt for LOOPSDONE event + LOOPSDONE: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// PWM module enable register + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable PWM module + ENABLE: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Selects operating mode of the wave counter + pub const MODE = mmio(Address + 0x00000504, 32, packed struct { + /// Selects up or up and down as wave counter mode + UPDOWN: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Value up to which the pulse generator counter counts + pub const COUNTERTOP = mmio(Address + 0x00000508, 32, packed struct { + /// Value up to which the pulse generator counter counts. This register is + /// ignored when DECODER.MODE=WaveForm and only values from RAM will be used. + COUNTERTOP: u15 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration for PWM_CLK + pub const PRESCALER = mmio(Address + 0x0000050c, 32, packed struct { + /// Pre-scaler of PWM_CLK + PRESCALER: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration of the decoder + pub const DECODER = mmio(Address + 0x00000510, 32, packed struct { + /// How a sequence is read from RAM and spread to the compare register + LOAD: u2 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Selects source for advancing the active sequence + MODE: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Amount of playback of a loop + pub const LOOP = mmio(Address + 0x00000514, 32, packed struct { + /// Amount of playback of pattern cycles + CNT: u16 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Loads the first PWM value on all enabled channels + /// from sequence 0, and starts playing that sequence at the rate defined in + /// SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not + /// running. + pub const TASKS_SEQSTART = @intToPtr(*volatile [2]u32, Address + 0x00000008); + /// Description collection[0]: First PWM period started on sequence 0 + pub const EVENTS_SEQSTARTED = @intToPtr(*volatile [2]u32, Address + 0x00000108); + /// Description collection[0]: Emitted at end of every sequence 0, when last + /// value from RAM has been applied to wave counter + pub const EVENTS_SEQEND = @intToPtr(*volatile [2]u32, Address + 0x00000110); +}; + +/// Pulse Width Modulation Unit 2 +pub const PWM2 = extern struct { + pub const Address: u32 = 0x40022000; + + /// Stops PWM pulse generation on all channels at the end of current PWM period, + /// and stops sequence playback + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Steps by one value in the current sequence on all enabled channels if + /// DECODER.MODE=NextStep. Does not cause PWM generation to start it was not + /// running. + pub const TASKS_NEXTSTEP = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Response to STOP task, emitted when PWM pulses are no longer generated + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Emitted at the end of each PWM period + pub const EVENTS_PWMPERIODEND = @intToPtr(*volatile u32, Address + 0x00000118); + + /// Concatenated sequences have been played the amount of times defined in + /// LOOP.CNT + pub const EVENTS_LOOPSDONE = @intToPtr(*volatile u32, Address + 0x0000011c); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between SEQEND[0] event and STOP task + SEQEND0_STOP: u1 = 0, + /// Shortcut between SEQEND[1] event and STOP task + SEQEND1_STOP: u1 = 0, + /// Shortcut between LOOPSDONE event and SEQSTART[0] task + LOOPSDONE_SEQSTART0: u1 = 0, + /// Shortcut between LOOPSDONE event and SEQSTART[1] task + LOOPSDONE_SEQSTART1: u1 = 0, + /// Shortcut between LOOPSDONE event and STOP task + LOOPSDONE_STOP: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + reserved1: u1 = 0, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Enable or disable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1 = 0, + /// Enable or disable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1 = 0, + /// Enable or disable interrupt for SEQEND[0] event + SEQEND0: u1 = 0, + /// Enable or disable interrupt for SEQEND[1] event + SEQEND1: u1 = 0, + /// Enable or disable interrupt for PWMPERIODEND event + PWMPERIODEND: u1 = 0, + /// Enable or disable interrupt for LOOPSDONE event + LOOPSDONE: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Write '1' to Enable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1 = 0, + /// Write '1' to Enable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1 = 0, + /// Write '1' to Enable interrupt for SEQEND[0] event + SEQEND0: u1 = 0, + /// Write '1' to Enable interrupt for SEQEND[1] event + SEQEND1: u1 = 0, + /// Write '1' to Enable interrupt for PWMPERIODEND event + PWMPERIODEND: u1 = 0, + /// Write '1' to Enable interrupt for LOOPSDONE event + LOOPSDONE: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Write '1' to Disable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1 = 0, + /// Write '1' to Disable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1 = 0, + /// Write '1' to Disable interrupt for SEQEND[0] event + SEQEND0: u1 = 0, + /// Write '1' to Disable interrupt for SEQEND[1] event + SEQEND1: u1 = 0, + /// Write '1' to Disable interrupt for PWMPERIODEND event + PWMPERIODEND: u1 = 0, + /// Write '1' to Disable interrupt for LOOPSDONE event + LOOPSDONE: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// PWM module enable register + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable PWM module + ENABLE: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Selects operating mode of the wave counter + pub const MODE = mmio(Address + 0x00000504, 32, packed struct { + /// Selects up or up and down as wave counter mode + UPDOWN: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Value up to which the pulse generator counter counts + pub const COUNTERTOP = mmio(Address + 0x00000508, 32, packed struct { + /// Value up to which the pulse generator counter counts. This register is + /// ignored when DECODER.MODE=WaveForm and only values from RAM will be used. + COUNTERTOP: u15 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration for PWM_CLK + pub const PRESCALER = mmio(Address + 0x0000050c, 32, packed struct { + /// Pre-scaler of PWM_CLK + PRESCALER: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration of the decoder + pub const DECODER = mmio(Address + 0x00000510, 32, packed struct { + /// How a sequence is read from RAM and spread to the compare register + LOAD: u2 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Selects source for advancing the active sequence + MODE: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Amount of playback of a loop + pub const LOOP = mmio(Address + 0x00000514, 32, packed struct { + /// Amount of playback of pattern cycles + CNT: u16 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Loads the first PWM value on all enabled channels + /// from sequence 0, and starts playing that sequence at the rate defined in + /// SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not + /// running. + pub const TASKS_SEQSTART = @intToPtr(*volatile [2]u32, Address + 0x00000008); + /// Description collection[0]: First PWM period started on sequence 0 + pub const EVENTS_SEQSTARTED = @intToPtr(*volatile [2]u32, Address + 0x00000108); + /// Description collection[0]: Emitted at end of every sequence 0, when last + /// value from RAM has been applied to wave counter + pub const EVENTS_SEQEND = @intToPtr(*volatile [2]u32, Address + 0x00000110); +}; + +/// Serial Peripheral Interface Master with EasyDMA 2 +pub const SPIM2 = extern struct { + pub const Address: u32 = 0x40023000; + + /// Start SPI transaction + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Stop SPI transaction + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); + + /// Suspend SPI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); + + /// Resume SPI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); + + /// SPI transaction has stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// End of RXD buffer reached + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x00000110); + + /// End of RXD buffer and TXD buffer reached + pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000118); + + /// End of TXD buffer reached + pub const EVENTS_ENDTX = @intToPtr(*volatile u32, Address + 0x00000120); + + /// Transaction started + pub const EVENTS_STARTED = @intToPtr(*volatile u32, Address + 0x0000014c); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between END event and START task + END_START: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Enable interrupt for END event + END: u1 = 0, + reserved5: u1 = 0, + /// Write '1' to Enable interrupt for ENDTX event + ENDTX: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + /// Write '1' to Enable interrupt for STARTED event + STARTED: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Disable interrupt for END event + END: u1 = 0, + reserved5: u1 = 0, + /// Write '1' to Disable interrupt for ENDTX event + ENDTX: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + /// Write '1' to Disable interrupt for STARTED event + STARTED: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable SPIM + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable SPIM + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// SPI frequency. Accuracy depends on the HFCLK source selected. + pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); + + /// Configuration register + pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { + /// Bit order + ORDER: u1 = 0, + /// Serial clock (SCK) phase + CPHA: u1 = 0, + /// Serial clock (SCK) polarity + CPOL: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Over-read character. Character clocked out in case and over-read of the TXD + /// buffer. + pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { + /// Over-read character. Character clocked out in case and over-read of the TXD + /// buffer. + ORC: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// SPI Slave 2 +pub const SPIS2 = extern struct { + pub const Address: u32 = 0x40023000; + + /// Acquire SPI semaphore + pub const TASKS_ACQUIRE = @intToPtr(*volatile u32, Address + 0x00000024); + + /// Release SPI semaphore, enabling the SPI slave to acquire it + pub const TASKS_RELEASE = @intToPtr(*volatile u32, Address + 0x00000028); + + /// Granted transaction completed + pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000104); + + /// End of RXD buffer reached + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x00000110); + + /// Semaphore acquired + pub const EVENTS_ACQUIRED = @intToPtr(*volatile u32, Address + 0x00000128); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between END event and ACQUIRE task + END_ACQUIRE: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for END event + END: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Enable interrupt for ACQUIRED event + ACQUIRED: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for END event + END: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Disable interrupt for ACQUIRED event + ACQUIRED: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Semaphore status register + pub const SEMSTAT = mmio(Address + 0x00000400, 32, packed struct { + /// Semaphore status + SEMSTAT: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Status from last transaction + pub const STATUS = mmio(Address + 0x00000440, 32, packed struct { + /// TX buffer over-read detected, and prevented + OVERREAD: u1 = 0, + /// RX buffer overflow detected, and prevented + OVERFLOW: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable SPI slave + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable SPI slave + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration register + pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { + /// Bit order + ORDER: u1 = 0, + /// Serial clock (SCK) phase + CPHA: u1 = 0, + /// Serial clock (SCK) polarity + CPOL: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Default character. Character clocked out in case of an ignored transaction. + pub const DEF = mmio(Address + 0x0000055c, 32, packed struct { + /// Default character. Character clocked out in case of an ignored transaction. + DEF: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Over-read character + pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { + /// Over-read character. Character clocked out after an over-read of the + /// transmit buffer. + ORC: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// Serial Peripheral Interface 2 +pub const SPI2 = extern struct { + pub const Address: u32 = 0x40023000; + + /// TXD byte sent and RXD byte received + pub const EVENTS_READY = @intToPtr(*volatile u32, Address + 0x00000108); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for READY event + READY: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for READY event + READY: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable SPI + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable SPI + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// RXD register + pub const RXD = mmio(Address + 0x00000518, 32, packed struct { + /// RX data received. Double buffered + RXD: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// TXD register + pub const TXD = mmio(Address + 0x0000051c, 32, packed struct { + /// TX data to send. Double buffered + TXD: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// SPI frequency + pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); + + /// Configuration register + pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { + /// Bit order + ORDER: u1 = 0, + /// Serial clock (SCK) phase + CPHA: u1 = 0, + /// Serial clock (SCK) polarity + CPOL: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// Real time counter 2 +pub const RTC2 = extern struct { + pub const Address: u32 = 0x40024000; + + /// Start RTC COUNTER + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop RTC COUNTER + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Clear RTC COUNTER + pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Set COUNTER to 0xFFFFF0 + pub const TASKS_TRIGOVRFLW = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Event on COUNTER increment + pub const EVENTS_TICK = @intToPtr(*volatile u32, Address + 0x00000100); + + /// Event on COUNTER overflow + pub const EVENTS_OVRFLW = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for TICK event + TICK: u1 = 0, + /// Write '1' to Enable interrupt for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for TICK event + TICK: u1 = 0, + /// Write '1' to Disable interrupt for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable event routing + pub const EVTEN = mmio(Address + 0x00000340, 32, packed struct { + /// Enable or disable event routing for TICK event + TICK: u1 = 0, + /// Enable or disable event routing for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Enable or disable event routing for COMPARE[0] event + COMPARE0: u1 = 0, + /// Enable or disable event routing for COMPARE[1] event + COMPARE1: u1 = 0, + /// Enable or disable event routing for COMPARE[2] event + COMPARE2: u1 = 0, + /// Enable or disable event routing for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable event routing + pub const EVTENSET = mmio(Address + 0x00000344, 32, packed struct { + /// Write '1' to Enable event routing for TICK event + TICK: u1 = 0, + /// Write '1' to Enable event routing for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable event routing for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Enable event routing for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Enable event routing for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Enable event routing for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable event routing + pub const EVTENCLR = mmio(Address + 0x00000348, 32, packed struct { + /// Write '1' to Disable event routing for TICK event + TICK: u1 = 0, + /// Write '1' to Disable event routing for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable event routing for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Disable event routing for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Disable event routing for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Disable event routing for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Current COUNTER value + pub const COUNTER = mmio(Address + 0x00000504, 32, packed struct { + /// Counter value + COUNTER: u24 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written + /// when RTC is stopped + pub const PRESCALER = mmio(Address + 0x00000508, 32, packed struct { + /// Prescaler value + PRESCALER: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [4]u32, Address + 0x00000140); + /// Description collection[0]: Compare register 0 + pub const CC = @intToPtr(*volatile [4]MMIO(32, packed struct { + /// Compare value + COMPARE: u24 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }), Address + 0x00000540); +}; + +/// Inter-IC Sound +pub const I2S = extern struct { + pub const Address: u32 = 0x40025000; + + /// Starts continuous I2S transfer. Also starts MCK generator when this is + /// enabled. + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stops I2S transfer. Also stops MCK generator. Triggering this task will + /// cause the {event:STOPPED} event to be generated. + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// The RXD.PTR register has been copied to internal double-buffers. When the + /// I2S module is started and RX is enabled, this event will be generated for + /// every RXTXD.MAXCNT words that are received on the SDIN pin. + pub const EVENTS_RXPTRUPD = @intToPtr(*volatile u32, Address + 0x00000104); + + /// I2S transfer stopped. + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000108); + + /// The TDX.PTR register has been copied to internal double-buffers. When the + /// I2S module is started and TX is enabled, this event will be generated for + /// every RXTXD.MAXCNT words that are sent on the SDOUT pin. + pub const EVENTS_TXPTRUPD = @intToPtr(*volatile u32, Address + 0x00000114); + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + reserved1: u1 = 0, + /// Enable or disable interrupt for RXPTRUPD event + RXPTRUPD: u1 = 0, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Enable or disable interrupt for TXPTRUPD event + TXPTRUPD: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for RXPTRUPD event + RXPTRUPD: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Enable interrupt for TXPTRUPD event + TXPTRUPD: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for RXPTRUPD event + RXPTRUPD: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Disable interrupt for TXPTRUPD event + TXPTRUPD: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable I2S module. + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable I2S module. + ENABLE: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + pub const CONFIG = struct { + + /// I2S mode. + pub const MODE = mmio(Address + 0x00000000, 32, packed struct { + /// I2S mode. + MODE: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Reception (RX) enable. + pub const RXEN = mmio(Address + 0x00000004, 32, packed struct { + /// Reception (RX) enable. + RXEN: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Transmission (TX) enable. + pub const TXEN = mmio(Address + 0x00000008, 32, packed struct { + /// Transmission (TX) enable. + TXEN: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Master clock generator enable. + pub const MCKEN = mmio(Address + 0x0000000c, 32, packed struct { + /// Master clock generator enable. + MCKEN: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Master clock generator frequency. + pub const MCKFREQ = @intToPtr(*volatile u32, Address + 0x00000010); + + /// MCK / LRCK ratio. + pub const RATIO = mmio(Address + 0x00000014, 32, packed struct { + /// MCK / LRCK ratio. + RATIO: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Sample width. + pub const SWIDTH = mmio(Address + 0x00000018, 32, packed struct { + /// Sample width. + SWIDTH: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Alignment of sample within a frame. + pub const ALIGN = mmio(Address + 0x0000001c, 32, packed struct { + /// Alignment of sample within a frame. + ALIGN: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Frame format. + pub const FORMAT = mmio(Address + 0x00000020, 32, packed struct { + /// Frame format. + FORMAT: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable channels. + pub const CHANNELS = mmio(Address + 0x00000024, 32, packed struct { + /// Enable channels. + CHANNELS: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; + + pub const RXD = struct { + + /// Receive buffer RAM start address. + pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + }; + + pub const TXD = struct { + + /// Transmit buffer RAM start address. + pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + }; + + pub const RXTXD = struct { + + /// Size of RXD and TXD buffers. + pub const MAXCNT = mmio(Address + 0x00000000, 32, packed struct { + /// Size of RXD and TXD buffers in number of 32 bit words. + MAXCNT: u14 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; + + pub const PSEL = struct { + + /// Pin select for MCK signal. + pub const MCK = mmio(Address + 0x00000000, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for SCK signal. + pub const SCK = mmio(Address + 0x00000004, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for LRCK signal. + pub const LRCK = mmio(Address + 0x00000008, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for SDIN signal. + pub const SDIN = mmio(Address + 0x0000000c, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for SDOUT signal. + pub const SDOUT = mmio(Address + 0x00000010, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + }; +}; + +/// FPU +pub const FPU = extern struct { + pub const Address: u32 = 0x40026000; + + /// Unused. + pub const UNUSED = @intToPtr(*volatile u32, Address + 0x00000000); +}; + +/// GPIO Port 1 +pub const P0 = extern struct { + pub const Address: u32 = 0x50000000; + + /// Write GPIO port + pub const OUT = mmio(Address + 0x00000504, 32, packed struct { + /// Pin 0 + PIN0: u1 = 0, + /// Pin 1 + PIN1: u1 = 0, + /// Pin 2 + PIN2: u1 = 0, + /// Pin 3 + PIN3: u1 = 0, + /// Pin 4 + PIN4: u1 = 0, + /// Pin 5 + PIN5: u1 = 0, + /// Pin 6 + PIN6: u1 = 0, + /// Pin 7 + PIN7: u1 = 0, + /// Pin 8 + PIN8: u1 = 0, + /// Pin 9 + PIN9: u1 = 0, + /// Pin 10 + PIN10: u1 = 0, + /// Pin 11 + PIN11: u1 = 0, + /// Pin 12 + PIN12: u1 = 0, + /// Pin 13 + PIN13: u1 = 0, + /// Pin 14 + PIN14: u1 = 0, + /// Pin 15 + PIN15: u1 = 0, + /// Pin 16 + PIN16: u1 = 0, + /// Pin 17 + PIN17: u1 = 0, + /// Pin 18 + PIN18: u1 = 0, + /// Pin 19 + PIN19: u1 = 0, + /// Pin 20 + PIN20: u1 = 0, + /// Pin 21 + PIN21: u1 = 0, + /// Pin 22 + PIN22: u1 = 0, + /// Pin 23 + PIN23: u1 = 0, + /// Pin 24 + PIN24: u1 = 0, + /// Pin 25 + PIN25: u1 = 0, + /// Pin 26 + PIN26: u1 = 0, + /// Pin 27 + PIN27: u1 = 0, + /// Pin 28 + PIN28: u1 = 0, + /// Pin 29 + PIN29: u1 = 0, + /// Pin 30 + PIN30: u1 = 0, + /// Pin 31 + PIN31: u1 = 0, + }); + + /// Set individual bits in GPIO port + pub const OUTSET = mmio(Address + 0x00000508, 32, packed struct { + /// Pin 0 + PIN0: u1 = 0, + /// Pin 1 + PIN1: u1 = 0, + /// Pin 2 + PIN2: u1 = 0, + /// Pin 3 + PIN3: u1 = 0, + /// Pin 4 + PIN4: u1 = 0, + /// Pin 5 + PIN5: u1 = 0, + /// Pin 6 + PIN6: u1 = 0, + /// Pin 7 + PIN7: u1 = 0, + /// Pin 8 + PIN8: u1 = 0, + /// Pin 9 + PIN9: u1 = 0, + /// Pin 10 + PIN10: u1 = 0, + /// Pin 11 + PIN11: u1 = 0, + /// Pin 12 + PIN12: u1 = 0, + /// Pin 13 + PIN13: u1 = 0, + /// Pin 14 + PIN14: u1 = 0, + /// Pin 15 + PIN15: u1 = 0, + /// Pin 16 + PIN16: u1 = 0, + /// Pin 17 + PIN17: u1 = 0, + /// Pin 18 + PIN18: u1 = 0, + /// Pin 19 + PIN19: u1 = 0, + /// Pin 20 + PIN20: u1 = 0, + /// Pin 21 + PIN21: u1 = 0, + /// Pin 22 + PIN22: u1 = 0, + /// Pin 23 + PIN23: u1 = 0, + /// Pin 24 + PIN24: u1 = 0, + /// Pin 25 + PIN25: u1 = 0, + /// Pin 26 + PIN26: u1 = 0, + /// Pin 27 + PIN27: u1 = 0, + /// Pin 28 + PIN28: u1 = 0, + /// Pin 29 + PIN29: u1 = 0, + /// Pin 30 + PIN30: u1 = 0, + /// Pin 31 + PIN31: u1 = 0, + }); + + /// Clear individual bits in GPIO port + pub const OUTCLR = mmio(Address + 0x0000050c, 32, packed struct { + /// Pin 0 + PIN0: u1 = 0, + /// Pin 1 + PIN1: u1 = 0, + /// Pin 2 + PIN2: u1 = 0, + /// Pin 3 + PIN3: u1 = 0, + /// Pin 4 + PIN4: u1 = 0, + /// Pin 5 + PIN5: u1 = 0, + /// Pin 6 + PIN6: u1 = 0, + /// Pin 7 + PIN7: u1 = 0, + /// Pin 8 + PIN8: u1 = 0, + /// Pin 9 + PIN9: u1 = 0, + /// Pin 10 + PIN10: u1 = 0, + /// Pin 11 + PIN11: u1 = 0, + /// Pin 12 + PIN12: u1 = 0, + /// Pin 13 + PIN13: u1 = 0, + /// Pin 14 + PIN14: u1 = 0, + /// Pin 15 + PIN15: u1 = 0, + /// Pin 16 + PIN16: u1 = 0, + /// Pin 17 + PIN17: u1 = 0, + /// Pin 18 + PIN18: u1 = 0, + /// Pin 19 + PIN19: u1 = 0, + /// Pin 20 + PIN20: u1 = 0, + /// Pin 21 + PIN21: u1 = 0, + /// Pin 22 + PIN22: u1 = 0, + /// Pin 23 + PIN23: u1 = 0, + /// Pin 24 + PIN24: u1 = 0, + /// Pin 25 + PIN25: u1 = 0, + /// Pin 26 + PIN26: u1 = 0, + /// Pin 27 + PIN27: u1 = 0, + /// Pin 28 + PIN28: u1 = 0, + /// Pin 29 + PIN29: u1 = 0, + /// Pin 30 + PIN30: u1 = 0, + /// Pin 31 + PIN31: u1 = 0, + }); + + /// Read GPIO port + pub const IN = mmio(Address + 0x00000510, 32, packed struct { + /// Pin 0 + PIN0: u1 = 0, + /// Pin 1 + PIN1: u1 = 0, + /// Pin 2 + PIN2: u1 = 0, + /// Pin 3 + PIN3: u1 = 0, + /// Pin 4 + PIN4: u1 = 0, + /// Pin 5 + PIN5: u1 = 0, + /// Pin 6 + PIN6: u1 = 0, + /// Pin 7 + PIN7: u1 = 0, + /// Pin 8 + PIN8: u1 = 0, + /// Pin 9 + PIN9: u1 = 0, + /// Pin 10 + PIN10: u1 = 0, + /// Pin 11 + PIN11: u1 = 0, + /// Pin 12 + PIN12: u1 = 0, + /// Pin 13 + PIN13: u1 = 0, + /// Pin 14 + PIN14: u1 = 0, + /// Pin 15 + PIN15: u1 = 0, + /// Pin 16 + PIN16: u1 = 0, + /// Pin 17 + PIN17: u1 = 0, + /// Pin 18 + PIN18: u1 = 0, + /// Pin 19 + PIN19: u1 = 0, + /// Pin 20 + PIN20: u1 = 0, + /// Pin 21 + PIN21: u1 = 0, + /// Pin 22 + PIN22: u1 = 0, + /// Pin 23 + PIN23: u1 = 0, + /// Pin 24 + PIN24: u1 = 0, + /// Pin 25 + PIN25: u1 = 0, + /// Pin 26 + PIN26: u1 = 0, + /// Pin 27 + PIN27: u1 = 0, + /// Pin 28 + PIN28: u1 = 0, + /// Pin 29 + PIN29: u1 = 0, + /// Pin 30 + PIN30: u1 = 0, + /// Pin 31 + PIN31: u1 = 0, + }); + + /// Direction of GPIO pins + pub const DIR = mmio(Address + 0x00000514, 32, packed struct { + /// Pin 0 + PIN0: u1 = 0, + /// Pin 1 + PIN1: u1 = 0, + /// Pin 2 + PIN2: u1 = 0, + /// Pin 3 + PIN3: u1 = 0, + /// Pin 4 + PIN4: u1 = 0, + /// Pin 5 + PIN5: u1 = 0, + /// Pin 6 + PIN6: u1 = 0, + /// Pin 7 + PIN7: u1 = 0, + /// Pin 8 + PIN8: u1 = 0, + /// Pin 9 + PIN9: u1 = 0, + /// Pin 10 + PIN10: u1 = 0, + /// Pin 11 + PIN11: u1 = 0, + /// Pin 12 + PIN12: u1 = 0, + /// Pin 13 + PIN13: u1 = 0, + /// Pin 14 + PIN14: u1 = 0, + /// Pin 15 + PIN15: u1 = 0, + /// Pin 16 + PIN16: u1 = 0, + /// Pin 17 + PIN17: u1 = 0, + /// Pin 18 + PIN18: u1 = 0, + /// Pin 19 + PIN19: u1 = 0, + /// Pin 20 + PIN20: u1 = 0, + /// Pin 21 + PIN21: u1 = 0, + /// Pin 22 + PIN22: u1 = 0, + /// Pin 23 + PIN23: u1 = 0, + /// Pin 24 + PIN24: u1 = 0, + /// Pin 25 + PIN25: u1 = 0, + /// Pin 26 + PIN26: u1 = 0, + /// Pin 27 + PIN27: u1 = 0, + /// Pin 28 + PIN28: u1 = 0, + /// Pin 29 + PIN29: u1 = 0, + /// Pin 30 + PIN30: u1 = 0, + /// Pin 31 + PIN31: u1 = 0, + }); + + /// DIR set register + pub const DIRSET = mmio(Address + 0x00000518, 32, packed struct { + /// Set as output pin 0 + PIN0: u1 = 0, + /// Set as output pin 1 + PIN1: u1 = 0, + /// Set as output pin 2 + PIN2: u1 = 0, + /// Set as output pin 3 + PIN3: u1 = 0, + /// Set as output pin 4 + PIN4: u1 = 0, + /// Set as output pin 5 + PIN5: u1 = 0, + /// Set as output pin 6 + PIN6: u1 = 0, + /// Set as output pin 7 + PIN7: u1 = 0, + /// Set as output pin 8 + PIN8: u1 = 0, + /// Set as output pin 9 + PIN9: u1 = 0, + /// Set as output pin 10 + PIN10: u1 = 0, + /// Set as output pin 11 + PIN11: u1 = 0, + /// Set as output pin 12 + PIN12: u1 = 0, + /// Set as output pin 13 + PIN13: u1 = 0, + /// Set as output pin 14 + PIN14: u1 = 0, + /// Set as output pin 15 + PIN15: u1 = 0, + /// Set as output pin 16 + PIN16: u1 = 0, + /// Set as output pin 17 + PIN17: u1 = 0, + /// Set as output pin 18 + PIN18: u1 = 0, + /// Set as output pin 19 + PIN19: u1 = 0, + /// Set as output pin 20 + PIN20: u1 = 0, + /// Set as output pin 21 + PIN21: u1 = 0, + /// Set as output pin 22 + PIN22: u1 = 0, + /// Set as output pin 23 + PIN23: u1 = 0, + /// Set as output pin 24 + PIN24: u1 = 0, + /// Set as output pin 25 + PIN25: u1 = 0, + /// Set as output pin 26 + PIN26: u1 = 0, + /// Set as output pin 27 + PIN27: u1 = 0, + /// Set as output pin 28 + PIN28: u1 = 0, + /// Set as output pin 29 + PIN29: u1 = 0, + /// Set as output pin 30 + PIN30: u1 = 0, + /// Set as output pin 31 + PIN31: u1 = 0, + }); + + /// DIR clear register + pub const DIRCLR = mmio(Address + 0x0000051c, 32, packed struct { + /// Set as input pin 0 + PIN0: u1 = 0, + /// Set as input pin 1 + PIN1: u1 = 0, + /// Set as input pin 2 + PIN2: u1 = 0, + /// Set as input pin 3 + PIN3: u1 = 0, + /// Set as input pin 4 + PIN4: u1 = 0, + /// Set as input pin 5 + PIN5: u1 = 0, + /// Set as input pin 6 + PIN6: u1 = 0, + /// Set as input pin 7 + PIN7: u1 = 0, + /// Set as input pin 8 + PIN8: u1 = 0, + /// Set as input pin 9 + PIN9: u1 = 0, + /// Set as input pin 10 + PIN10: u1 = 0, + /// Set as input pin 11 + PIN11: u1 = 0, + /// Set as input pin 12 + PIN12: u1 = 0, + /// Set as input pin 13 + PIN13: u1 = 0, + /// Set as input pin 14 + PIN14: u1 = 0, + /// Set as input pin 15 + PIN15: u1 = 0, + /// Set as input pin 16 + PIN16: u1 = 0, + /// Set as input pin 17 + PIN17: u1 = 0, + /// Set as input pin 18 + PIN18: u1 = 0, + /// Set as input pin 19 + PIN19: u1 = 0, + /// Set as input pin 20 + PIN20: u1 = 0, + /// Set as input pin 21 + PIN21: u1 = 0, + /// Set as input pin 22 + PIN22: u1 = 0, + /// Set as input pin 23 + PIN23: u1 = 0, + /// Set as input pin 24 + PIN24: u1 = 0, + /// Set as input pin 25 + PIN25: u1 = 0, + /// Set as input pin 26 + PIN26: u1 = 0, + /// Set as input pin 27 + PIN27: u1 = 0, + /// Set as input pin 28 + PIN28: u1 = 0, + /// Set as input pin 29 + PIN29: u1 = 0, + /// Set as input pin 30 + PIN30: u1 = 0, + /// Set as input pin 31 + PIN31: u1 = 0, + }); + + /// Latch register indicating what GPIO pins that have met the criteria set in + /// the PIN_CNF[n].SENSE registers + pub const LATCH = mmio(Address + 0x00000520, 32, packed struct { + /// Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. + /// Write '1' to clear. + PIN0: u1 = 0, + /// Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. + /// Write '1' to clear. + PIN1: u1 = 0, + /// Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. + /// Write '1' to clear. + PIN2: u1 = 0, + /// Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. + /// Write '1' to clear. + PIN3: u1 = 0, + /// Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. + /// Write '1' to clear. + PIN4: u1 = 0, + /// Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. + /// Write '1' to clear. + PIN5: u1 = 0, + /// Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. + /// Write '1' to clear. + PIN6: u1 = 0, + /// Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. + /// Write '1' to clear. + PIN7: u1 = 0, + /// Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. + /// Write '1' to clear. + PIN8: u1 = 0, + /// Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. + /// Write '1' to clear. + PIN9: u1 = 0, + /// Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. + /// Write '1' to clear. + PIN10: u1 = 0, + /// Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. + /// Write '1' to clear. + PIN11: u1 = 0, + /// Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. + /// Write '1' to clear. + PIN12: u1 = 0, + /// Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. + /// Write '1' to clear. + PIN13: u1 = 0, + /// Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. + /// Write '1' to clear. + PIN14: u1 = 0, + /// Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. + /// Write '1' to clear. + PIN15: u1 = 0, + /// Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. + /// Write '1' to clear. + PIN16: u1 = 0, + /// Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. + /// Write '1' to clear. + PIN17: u1 = 0, + /// Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. + /// Write '1' to clear. + PIN18: u1 = 0, + /// Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. + /// Write '1' to clear. + PIN19: u1 = 0, + /// Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. + /// Write '1' to clear. + PIN20: u1 = 0, + /// Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. + /// Write '1' to clear. + PIN21: u1 = 0, + /// Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. + /// Write '1' to clear. + PIN22: u1 = 0, + /// Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. + /// Write '1' to clear. + PIN23: u1 = 0, + /// Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. + /// Write '1' to clear. + PIN24: u1 = 0, + /// Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. + /// Write '1' to clear. + PIN25: u1 = 0, + /// Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. + /// Write '1' to clear. + PIN26: u1 = 0, + /// Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. + /// Write '1' to clear. + PIN27: u1 = 0, + /// Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. + /// Write '1' to clear. + PIN28: u1 = 0, + /// Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. + /// Write '1' to clear. + PIN29: u1 = 0, + /// Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. + /// Write '1' to clear. + PIN30: u1 = 0, + /// Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. + /// Write '1' to clear. + PIN31: u1 = 0, + }); + + /// Select between default DETECT signal behaviour and LDETECT mode + pub const DETECTMODE = mmio(Address + 0x00000524, 32, packed struct { + /// Select between default DETECT signal behaviour and LDETECT mode + DETECTMODE: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Configuration of GPIO pins + pub const PIN_CNF = @intToPtr(*volatile [32]MMIO(32, packed struct { + /// Pin direction. Same physical register as DIR register + DIR: u1 = 0, + /// Connect or disconnect input buffer + INPUT: u1 = 0, + /// Pull configuration + PULL: u2 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Drive configuration + DRIVE: u3 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + /// Pin sensing mechanism + SENSE: u2 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }), Address + 0x00000700); +}; + +const std = @import("std"); +const root = @import("root"); +const cpu = @import("cpu"); +const config = @import("microzig-config"); +const InterruptVector = extern union { + C: fn () callconv(.C) void, + Naked: fn () callconv(.Naked) void, + // Interrupt is not supported on arm +}; + +fn makeUnhandledHandler(comptime str: []const u8) InterruptVector { + return InterruptVector{ + .C = struct { + fn unhandledInterrupt() callconv(.C) noreturn { + @panic("unhandled interrupt: " ++ str); + } + }.unhandledInterrupt, + }; +} + +pub const VectorTable = extern struct { + initial_stack_pointer: u32 = config.end_of_stack, + Reset: InterruptVector = InterruptVector{ .C = cpu.startup_logic._start }, + NMI: InterruptVector = makeUnhandledHandler("NMI"), + HardFault: InterruptVector = makeUnhandledHandler("HardFault"), + MemManage: InterruptVector = makeUnhandledHandler("MemManage"), + BusFault: InterruptVector = makeUnhandledHandler("BusFault"), + UsageFault: InterruptVector = makeUnhandledHandler("UsageFault"), + + reserved: [4]u32 = .{ 0, 0, 0, 0 }, + SVCall: InterruptVector = makeUnhandledHandler("SVCall"), + DebugMonitor: InterruptVector = makeUnhandledHandler("DebugMonitor"), + reserved1: u32 = 0, + + PendSV: InterruptVector = makeUnhandledHandler("PendSV"), + SysTick: InterruptVector = makeUnhandledHandler("SysTick"), + + POWER_CLOCK: InterruptVector = makeUnhandledHandler("POWER_CLOCK"), + RADIO: InterruptVector = makeUnhandledHandler("RADIO"), + UARTE0_UART0: InterruptVector = makeUnhandledHandler("UARTE0_UART0"), + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0: InterruptVector = makeUnhandledHandler("SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0"), + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1: InterruptVector = makeUnhandledHandler("SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1"), + NFCT: InterruptVector = makeUnhandledHandler("NFCT"), + GPIOTE: InterruptVector = makeUnhandledHandler("GPIOTE"), + SAADC: InterruptVector = makeUnhandledHandler("SAADC"), + TIMER0: InterruptVector = makeUnhandledHandler("TIMER0"), + TIMER1: InterruptVector = makeUnhandledHandler("TIMER1"), + TIMER2: InterruptVector = makeUnhandledHandler("TIMER2"), + RTC0: InterruptVector = makeUnhandledHandler("RTC0"), + TEMP: InterruptVector = makeUnhandledHandler("TEMP"), + RNG: InterruptVector = makeUnhandledHandler("RNG"), + ECB: InterruptVector = makeUnhandledHandler("ECB"), + CCM_AAR: InterruptVector = makeUnhandledHandler("CCM_AAR"), + WDT: InterruptVector = makeUnhandledHandler("WDT"), + RTC1: InterruptVector = makeUnhandledHandler("RTC1"), + QDEC: InterruptVector = makeUnhandledHandler("QDEC"), + COMP_LPCOMP: InterruptVector = makeUnhandledHandler("COMP_LPCOMP"), + SWI0_EGU0: InterruptVector = makeUnhandledHandler("SWI0_EGU0"), + SWI1_EGU1: InterruptVector = makeUnhandledHandler("SWI1_EGU1"), + SWI2_EGU2: InterruptVector = makeUnhandledHandler("SWI2_EGU2"), + SWI3_EGU3: InterruptVector = makeUnhandledHandler("SWI3_EGU3"), + SWI4_EGU4: InterruptVector = makeUnhandledHandler("SWI4_EGU4"), + SWI5_EGU5: InterruptVector = makeUnhandledHandler("SWI5_EGU5"), + TIMER3: InterruptVector = makeUnhandledHandler("TIMER3"), + TIMER4: InterruptVector = makeUnhandledHandler("TIMER4"), + PWM0: InterruptVector = makeUnhandledHandler("PWM0"), + PDM: InterruptVector = makeUnhandledHandler("PDM"), + reserved2: u32 = 0, + reserved3: u32 = 0, + MWU: InterruptVector = makeUnhandledHandler("MWU"), + PWM1: InterruptVector = makeUnhandledHandler("PWM1"), + PWM2: InterruptVector = makeUnhandledHandler("PWM2"), + SPIM2_SPIS2_SPI2: InterruptVector = makeUnhandledHandler("SPIM2_SPIS2_SPI2"), + RTC2: InterruptVector = makeUnhandledHandler("RTC2"), + I2S: InterruptVector = makeUnhandledHandler("I2S"), + FPU: InterruptVector = makeUnhandledHandler("FPU"), +}; + +fn isValidField(field_name: []const u8) bool { + return !std.mem.startsWith(u8, field_name, "reserved") and + !std.mem.eql(u8, field_name, "initial_stack_pointer") and + !std.mem.eql(u8, field_name, "reset"); +} + +export const vectors: VectorTable linksection("microzig_flash_start") = blk: { + var temp: VectorTable = .{}; + if (@hasDecl(root, "vector_table")) { + const vector_table = root.vector_table; + if (@typeInfo(vector_table) != .Struct) + @compileLog("root.vector_table must be a struct"); + + inline for (@typeInfo(vector_table).Struct.decls) |decl| { + const calling_convention = @typeInfo(@TypeOf(@field(vector_table, decl.name))).Fn.calling_convention; + const handler = @field(vector_table, decl.name); + + if (!@hasField(VectorTable, decl.name)) { + var msg: []const u8 = "There is no such interrupt as '" ++ decl.name ++ "', declarations in 'root.vector_table' must be one of:\n"; + inline for (std.meta.fields(VectorTable)) |field| { + if (isValidField(field.name)) { + msg = msg ++ " " ++ field.name ++ "\n"; + } + } + + @compileError(msg); + } + + if (!isValidField(decl.name)) + @compileError("You are not allowed to specify '" ++ decl.name ++ "' in the vector table, for your sins you must now pay a $5 fine to the ZSF: https://github.com/sponsors/ziglang"); + + @field(temp, decl.name) = switch (calling_convention) { + .C => .{ .C = handler }, + .Naked => .{ .Naked = handler }, + // for unspecified calling convention we are going to generate small wrapper + .Unspecified => .{ + .C = struct { + fn wrapper() callconv(.C) void { + if (calling_convention == .Unspecified) // TODO: workaround for some weird stage1 bug + @call(.{ .modifier = .always_inline }, handler, .{}); + } + }.wrapper, + }, + + else => @compileError("unsupported calling convention for function " ++ decl.name), + }; + } + } + break :blk temp; +}; diff --git a/src/modules/chips/stm32f103/registers.zig b/src/modules/chips/stm32f103/registers.zig index 4cbe4cd..f56973f 100644 --- a/src/modules/chips/stm32f103/registers.zig +++ b/src/modules/chips/stm32f103/registers.zig @@ -1,30 +1,22 @@ // generated using svd2zig.py // DO NOT EDIT // based on STM32F103xx version 1.3 -const mmio = @import("microzig-mmio").mmio; +const microzig_mmio = @import("microzig-mmio"); +const mmio = microzig_mmio.mmio; +const MMIO = microzig_mmio.MMIO; const Name = "STM32F103xx"; + +/// Flexible static memory controller pub const FSMC = extern struct { pub const Address: u32 = 0xa0000000; - // byte offset: 0 SRAM/NOR-Flash chip-select control register 1 + + /// SRAM/NOR-Flash chip-select control register 1 pub const BCR1 = mmio(Address + 0x00000000, 32, packed struct { - MBKEN: u1, // bit offset: 0 desc: MBKEN - MUXEN: u1, // bit offset: 1 desc: MUXEN - MTYP: u2, // bit offset: 2 desc: MTYP - MWID: u2, // bit offset: 4 desc: MWID - FACCEN: u1, // bit offset: 6 desc: FACCEN reserved1: u1 = 0, - BURSTEN: u1, // bit offset: 8 desc: BURSTEN - WAITPOL: u1, // bit offset: 9 desc: WAITPOL reserved2: u1 = 0, - WAITCFG: u1, // bit offset: 11 desc: WAITCFG - WREN: u1, // bit offset: 12 desc: WREN - WAITEN: u1, // bit offset: 13 desc: WAITEN - EXTMOD: u1, // bit offset: 14 desc: EXTMOD - ASYNCWAIT: u1, // bit offset: 15 desc: ASYNCWAIT reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - CBURSTRW: u1, // bit offset: 19 desc: CBURSTRW padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -38,38 +30,19 @@ pub const FSMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 SRAM/NOR-Flash chip-select timing register 1 + + /// SRAM/NOR-Flash chip-select timing register 1 pub const BTR1 = mmio(Address + 0x00000004, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST - BUSTURN: u4, // bit offset: 16 desc: BUSTURN - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 SRAM/NOR-Flash chip-select control register 2 + + /// SRAM/NOR-Flash chip-select control register 2 pub const BCR2 = mmio(Address + 0x00000008, 32, packed struct { - MBKEN: u1, // bit offset: 0 desc: MBKEN - MUXEN: u1, // bit offset: 1 desc: MUXEN - MTYP: u2, // bit offset: 2 desc: MTYP - MWID: u2, // bit offset: 4 desc: MWID - FACCEN: u1, // bit offset: 6 desc: FACCEN reserved1: u1 = 0, - BURSTEN: u1, // bit offset: 8 desc: BURSTEN - WAITPOL: u1, // bit offset: 9 desc: WAITPOL - WRAPMOD: u1, // bit offset: 10 desc: WRAPMOD - WAITCFG: u1, // bit offset: 11 desc: WAITCFG - WREN: u1, // bit offset: 12 desc: WREN - WAITEN: u1, // bit offset: 13 desc: WAITEN - EXTMOD: u1, // bit offset: 14 desc: EXTMOD - ASYNCWAIT: u1, // bit offset: 15 desc: ASYNCWAIT reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CBURSTRW: u1, // bit offset: 19 desc: CBURSTRW padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -83,38 +56,19 @@ pub const FSMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 SRAM/NOR-Flash chip-select timing register 2 + + /// SRAM/NOR-Flash chip-select timing register 2 pub const BTR2 = mmio(Address + 0x0000000c, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST - BUSTURN: u4, // bit offset: 16 desc: BUSTURN - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 SRAM/NOR-Flash chip-select control register 3 + + /// SRAM/NOR-Flash chip-select control register 3 pub const BCR3 = mmio(Address + 0x00000010, 32, packed struct { - MBKEN: u1, // bit offset: 0 desc: MBKEN - MUXEN: u1, // bit offset: 1 desc: MUXEN - MTYP: u2, // bit offset: 2 desc: MTYP - MWID: u2, // bit offset: 4 desc: MWID - FACCEN: u1, // bit offset: 6 desc: FACCEN reserved1: u1 = 0, - BURSTEN: u1, // bit offset: 8 desc: BURSTEN - WAITPOL: u1, // bit offset: 9 desc: WAITPOL - WRAPMOD: u1, // bit offset: 10 desc: WRAPMOD - WAITCFG: u1, // bit offset: 11 desc: WAITCFG - WREN: u1, // bit offset: 12 desc: WREN - WAITEN: u1, // bit offset: 13 desc: WAITEN - EXTMOD: u1, // bit offset: 14 desc: EXTMOD - ASYNCWAIT: u1, // bit offset: 15 desc: ASYNCWAIT reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CBURSTRW: u1, // bit offset: 19 desc: CBURSTRW padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -128,38 +82,19 @@ pub const FSMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 SRAM/NOR-Flash chip-select timing register 3 + + /// SRAM/NOR-Flash chip-select timing register 3 pub const BTR3 = mmio(Address + 0x00000014, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST - BUSTURN: u4, // bit offset: 16 desc: BUSTURN - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 SRAM/NOR-Flash chip-select control register 4 + + /// SRAM/NOR-Flash chip-select control register 4 pub const BCR4 = mmio(Address + 0x00000018, 32, packed struct { - MBKEN: u1, // bit offset: 0 desc: MBKEN - MUXEN: u1, // bit offset: 1 desc: MUXEN - MTYP: u2, // bit offset: 2 desc: MTYP - MWID: u2, // bit offset: 4 desc: MWID - FACCEN: u1, // bit offset: 6 desc: FACCEN reserved1: u1 = 0, - BURSTEN: u1, // bit offset: 8 desc: BURSTEN - WAITPOL: u1, // bit offset: 9 desc: WAITPOL - WRAPMOD: u1, // bit offset: 10 desc: WRAPMOD - WAITCFG: u1, // bit offset: 11 desc: WAITCFG - WREN: u1, // bit offset: 12 desc: WREN - WAITEN: u1, // bit offset: 13 desc: WAITEN - EXTMOD: u1, // bit offset: 14 desc: EXTMOD - ASYNCWAIT: u1, // bit offset: 15 desc: ASYNCWAIT reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CBURSTRW: u1, // bit offset: 19 desc: CBURSTRW padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -173,31 +108,18 @@ pub const FSMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 SRAM/NOR-Flash chip-select timing register 4 + + /// SRAM/NOR-Flash chip-select timing register 4 pub const BTR4 = mmio(Address + 0x0000001c, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST - BUSTURN: u4, // bit offset: 16 desc: BUSTURN - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 96 PC Card/NAND Flash control register 2 + + /// PC Card/NAND Flash control register 2 pub const PCR2 = mmio(Address + 0x00000060, 32, packed struct { reserved1: u1 = 0, - PWAITEN: u1, // bit offset: 1 desc: PWAITEN - PBKEN: u1, // bit offset: 2 desc: PBKEN - PTYP: u1, // bit offset: 3 desc: PTYP - PWID: u2, // bit offset: 4 desc: PWID - ECCEN: u1, // bit offset: 6 desc: ECCEN reserved3: u1 = 0, reserved2: u1 = 0, - TCLR: u4, // bit offset: 9 desc: TCLR - TAR: u4, // bit offset: 13 desc: TAR - ECCPS: u3, // bit offset: 17 desc: ECCPS padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -211,15 +133,9 @@ pub const FSMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 100 FIFO status and interrupt register 2 + + /// FIFO status and interrupt register 2 pub const SR2 = mmio(Address + 0x00000064, 32, packed struct { - IRS: u1, // bit offset: 0 desc: IRS - ILS: u1, // bit offset: 1 desc: ILS - IFS: u1, // bit offset: 2 desc: IFS - IREN: u1, // bit offset: 3 desc: IREN - ILEN: u1, // bit offset: 4 desc: ILEN - IFEN: u1, // bit offset: 5 desc: IFEN - FEMPT: u1, // bit offset: 6 desc: FEMPT padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -246,37 +162,33 @@ pub const FSMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 104 Common memory space timing register 2 - pub const PMEM2 = mmio(Address + 0x00000068, 32, packed struct { - MEMSETx: u8, // bit offset: 0 desc: MEMSETx - MEMWAITx: u8, // bit offset: 8 desc: MEMWAITx - MEMHOLDx: u8, // bit offset: 16 desc: MEMHOLDx - MEMHIZx: u8, // bit offset: 24 desc: MEMHIZx - }); - // byte offset: 108 Attribute memory space timing register 2 + + /// Common memory space timing register 2 + pub const PMEM2 = mmio(Address + 0x00000068, 32, packed struct {}); + + /// Attribute memory space timing register 2 pub const PATT2 = mmio(Address + 0x0000006c, 32, packed struct { - ATTSETx: u8, // bit offset: 0 desc: Attribute memory x setup time - ATTWAITx: u8, // bit offset: 8 desc: Attribute memory x wait time - ATTHOLDx: u8, // bit offset: 16 desc: Attribute memory x hold time - ATTHIZx: u8, // bit offset: 24 desc: Attribute memory x databus HiZ time + /// Attribute memory x setup time + ATTSETx: u8 = 0, + /// Attribute memory x wait time + ATTWAITx: u8 = 0, + /// Attribute memory x hold time + ATTHOLDx: u8 = 0, + /// Attribute memory x databus HiZ time + ATTHIZx: u8 = 0, }); - // byte offset: 116 ECC result register 2 + + /// ECC result register 2 pub const ECCR2 = mmio(Address + 0x00000074, 32, packed struct { - ECCx: u32, // bit offset: 0 desc: ECC result + /// ECC result + ECCx: u32 = 0, }); - // byte offset: 128 PC Card/NAND Flash control register 3 + + /// PC Card/NAND Flash control register 3 pub const PCR3 = mmio(Address + 0x00000080, 32, packed struct { reserved1: u1 = 0, - PWAITEN: u1, // bit offset: 1 desc: PWAITEN - PBKEN: u1, // bit offset: 2 desc: PBKEN - PTYP: u1, // bit offset: 3 desc: PTYP - PWID: u2, // bit offset: 4 desc: PWID - ECCEN: u1, // bit offset: 6 desc: ECCEN reserved3: u1 = 0, reserved2: u1 = 0, - TCLR: u4, // bit offset: 9 desc: TCLR - TAR: u4, // bit offset: 13 desc: TAR - ECCPS: u3, // bit offset: 17 desc: ECCPS padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -290,15 +202,9 @@ pub const FSMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 132 FIFO status and interrupt register 3 + + /// FIFO status and interrupt register 3 pub const SR3 = mmio(Address + 0x00000084, 32, packed struct { - IRS: u1, // bit offset: 0 desc: IRS - ILS: u1, // bit offset: 1 desc: ILS - IFS: u1, // bit offset: 2 desc: IFS - IREN: u1, // bit offset: 3 desc: IREN - ILEN: u1, // bit offset: 4 desc: ILEN - IFEN: u1, // bit offset: 5 desc: IFEN - FEMPT: u1, // bit offset: 6 desc: FEMPT padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -325,37 +231,21 @@ pub const FSMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 136 Common memory space timing register 3 - pub const PMEM3 = mmio(Address + 0x00000088, 32, packed struct { - MEMSETx: u8, // bit offset: 0 desc: MEMSETx - MEMWAITx: u8, // bit offset: 8 desc: MEMWAITx - MEMHOLDx: u8, // bit offset: 16 desc: MEMHOLDx - MEMHIZx: u8, // bit offset: 24 desc: MEMHIZx - }); - // byte offset: 140 Attribute memory space timing register 3 - pub const PATT3 = mmio(Address + 0x0000008c, 32, packed struct { - ATTSETx: u8, // bit offset: 0 desc: ATTSETx - ATTWAITx: u8, // bit offset: 8 desc: ATTWAITx - ATTHOLDx: u8, // bit offset: 16 desc: ATTHOLDx - ATTHIZx: u8, // bit offset: 24 desc: ATTHIZx - }); - // byte offset: 148 ECC result register 3 - pub const ECCR3 = mmio(Address + 0x00000094, 32, packed struct { - ECCx: u32, // bit offset: 0 desc: ECCx - }); - // byte offset: 160 PC Card/NAND Flash control register 4 + + /// Common memory space timing register 3 + pub const PMEM3 = mmio(Address + 0x00000088, 32, packed struct {}); + + /// Attribute memory space timing register 3 + pub const PATT3 = mmio(Address + 0x0000008c, 32, packed struct {}); + + /// ECC result register 3 + pub const ECCR3 = mmio(Address + 0x00000094, 32, packed struct {}); + + /// PC Card/NAND Flash control register 4 pub const PCR4 = mmio(Address + 0x000000a0, 32, packed struct { reserved1: u1 = 0, - PWAITEN: u1, // bit offset: 1 desc: PWAITEN - PBKEN: u1, // bit offset: 2 desc: PBKEN - PTYP: u1, // bit offset: 3 desc: PTYP - PWID: u2, // bit offset: 4 desc: PWID - ECCEN: u1, // bit offset: 6 desc: ECCEN reserved3: u1 = 0, reserved2: u1 = 0, - TCLR: u4, // bit offset: 9 desc: TCLR - TAR: u4, // bit offset: 13 desc: TAR - ECCPS: u3, // bit offset: 17 desc: ECCPS padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -369,15 +259,9 @@ pub const FSMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 164 FIFO status and interrupt register 4 + + /// FIFO status and interrupt register 4 pub const SR4 = mmio(Address + 0x000000a4, 32, packed struct { - IRS: u1, // bit offset: 0 desc: IRS - ILS: u1, // bit offset: 1 desc: ILS - IFS: u1, // bit offset: 2 desc: IFS - IREN: u1, // bit offset: 3 desc: IREN - ILEN: u1, // bit offset: 4 desc: ILEN - IFEN: u1, // bit offset: 5 desc: IFEN - FEMPT: u1, // bit offset: 6 desc: FEMPT padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -404,99 +288,77 @@ pub const FSMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 168 Common memory space timing register 4 - pub const PMEM4 = mmio(Address + 0x000000a8, 32, packed struct { - MEMSETx: u8, // bit offset: 0 desc: MEMSETx - MEMWAITx: u8, // bit offset: 8 desc: MEMWAITx - MEMHOLDx: u8, // bit offset: 16 desc: MEMHOLDx - MEMHIZx: u8, // bit offset: 24 desc: MEMHIZx - }); - // byte offset: 172 Attribute memory space timing register 4 - pub const PATT4 = mmio(Address + 0x000000ac, 32, packed struct { - ATTSETx: u8, // bit offset: 0 desc: ATTSETx - ATTWAITx: u8, // bit offset: 8 desc: ATTWAITx - ATTHOLDx: u8, // bit offset: 16 desc: ATTHOLDx - ATTHIZx: u8, // bit offset: 24 desc: ATTHIZx - }); - // byte offset: 176 I/O space timing register 4 - pub const PIO4 = mmio(Address + 0x000000b0, 32, packed struct { - IOSETx: u8, // bit offset: 0 desc: IOSETx - IOWAITx: u8, // bit offset: 8 desc: IOWAITx - IOHOLDx: u8, // bit offset: 16 desc: IOHOLDx - IOHIZx: u8, // bit offset: 24 desc: IOHIZx - }); - // byte offset: 260 SRAM/NOR-Flash write timing registers 1 + + /// Common memory space timing register 4 + pub const PMEM4 = mmio(Address + 0x000000a8, 32, packed struct {}); + + /// Attribute memory space timing register 4 + pub const PATT4 = mmio(Address + 0x000000ac, 32, packed struct {}); + + /// I/O space timing register 4 + pub const PIO4 = mmio(Address + 0x000000b0, 32, packed struct {}); + + /// SRAM/NOR-Flash write timing registers 1 pub const BWTR1 = mmio(Address + 0x00000104, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 268 SRAM/NOR-Flash write timing registers 2 + + /// SRAM/NOR-Flash write timing registers 2 pub const BWTR2 = mmio(Address + 0x0000010c, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 276 SRAM/NOR-Flash write timing registers 3 + + /// SRAM/NOR-Flash write timing registers 3 pub const BWTR3 = mmio(Address + 0x00000114, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 284 SRAM/NOR-Flash write timing registers 4 + + /// SRAM/NOR-Flash write timing registers 4 pub const BWTR4 = mmio(Address + 0x0000011c, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD padding2: u1 = 0, padding1: u1 = 0, }); }; + +/// Power control pub const PWR = extern struct { pub const Address: u32 = 0x40007000; - // byte offset: 0 Power control register (PWR_CR) + + /// Power control register (PWR_CR) pub const CR = mmio(Address + 0x00000000, 32, packed struct { - LPDS: u1, // bit offset: 0 desc: Low Power Deep Sleep - PDDS: u1, // bit offset: 1 desc: Power Down Deep Sleep - CWUF: u1, // bit offset: 2 desc: Clear Wake-up Flag - CSBF: u1, // bit offset: 3 desc: Clear STANDBY Flag - PVDE: u1, // bit offset: 4 desc: Power Voltage Detector Enable - PLS: u3, // bit offset: 5 desc: PVD Level Selection - DBP: u1, // bit offset: 8 desc: Disable Backup Domain write protection + /// Low Power Deep Sleep + LPDS: u1 = 0, + /// Power Down Deep Sleep + PDDS: u1 = 0, + /// Clear Wake-up Flag + CWUF: u1 = 0, + /// Clear STANDBY Flag + CSBF: u1 = 0, + /// Power Voltage Detector Enable + PVDE: u1 = 0, + /// PVD Level Selection + PLS: u3 = 0, + /// Disable Backup Domain write protection + DBP: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -521,17 +383,22 @@ pub const PWR = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Power control register (PWR_CR) + + /// Power control register (PWR_CR) pub const CSR = mmio(Address + 0x00000004, 32, packed struct { - WUF: u1, // bit offset: 0 desc: Wake-Up Flag - SBF: u1, // bit offset: 1 desc: STANDBY Flag - PVDO: u1, // bit offset: 2 desc: PVD Output + /// Wake-Up Flag + WUF: u1 = 0, + /// STANDBY Flag + SBF: u1 = 0, + /// PVD Output + PVDO: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - EWUP: u1, // bit offset: 8 desc: Enable WKUP pin + /// Enable WKUP pin + EWUP: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -557,25 +424,38 @@ pub const PWR = extern struct { padding1: u1 = 0, }); }; + +/// Reset and clock control pub const RCC = extern struct { pub const Address: u32 = 0x40021000; - // byte offset: 0 Clock control register + + /// Clock control register pub const CR = mmio(Address + 0x00000000, 32, packed struct { - HSION: u1, // bit offset: 0 desc: Internal High Speed clock enable - HSIRDY: u1, // bit offset: 1 desc: Internal High Speed clock ready flag + /// Internal High Speed clock enable + HSION: u1 = 0, + /// Internal High Speed clock ready flag + HSIRDY: u1 = 0, reserved1: u1 = 0, - HSITRIM: u5, // bit offset: 3 desc: Internal High Speed clock trimming - HSICAL: u8, // bit offset: 8 desc: Internal High Speed clock Calibration - HSEON: u1, // bit offset: 16 desc: External High Speed clock enable - HSERDY: u1, // bit offset: 17 desc: External High Speed clock ready flag - HSEBYP: u1, // bit offset: 18 desc: External High Speed clock Bypass - CSSON: u1, // bit offset: 19 desc: Clock Security System enable + /// Internal High Speed clock trimming + HSITRIM: u5 = 0, + /// Internal High Speed clock Calibration + HSICAL: u8 = 0, + /// External High Speed clock enable + HSEON: u1 = 0, + /// External High Speed clock ready flag + HSERDY: u1 = 0, + /// External High Speed clock Bypass + HSEBYP: u1 = 0, + /// Clock Security System enable + CSSON: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - PLLON: u1, // bit offset: 24 desc: PLL enable - PLLRDY: u1, // bit offset: 25 desc: PLL clock ready flag + /// PLL enable + PLLON: u1 = 0, + /// PLL clock ready flag + PLLRDY: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, @@ -583,52 +463,82 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Clock configuration register (RCC_CFGR) + + /// Clock configuration register (RCC_CFGR) pub const CFGR = mmio(Address + 0x00000004, 32, packed struct { - SW: u2, // bit offset: 0 desc: System clock Switch - SWS: u2, // bit offset: 2 desc: System Clock Switch Status - HPRE: u4, // bit offset: 4 desc: AHB prescaler - PPRE1: u3, // bit offset: 8 desc: APB Low speed prescaler (APB1) - PPRE2: u3, // bit offset: 11 desc: APB High speed prescaler (APB2) - ADCPRE: u2, // bit offset: 14 desc: ADC prescaler - PLLSRC: u1, // bit offset: 16 desc: PLL entry clock source - PLLXTPRE: u1, // bit offset: 17 desc: HSE divider for PLL entry - PLLMUL: u4, // bit offset: 18 desc: PLL Multiplication Factor - OTGFSPRE: u1, // bit offset: 22 desc: USB OTG FS prescaler + /// System clock Switch + SW: u2 = 0, + /// System Clock Switch Status + SWS: u2 = 0, + /// AHB prescaler + HPRE: u4 = 0, + /// APB Low speed prescaler (APB1) + PPRE1: u3 = 0, + /// APB High speed prescaler (APB2) + PPRE2: u3 = 0, + /// ADC prescaler + ADCPRE: u2 = 0, + /// PLL entry clock source + PLLSRC: u1 = 0, + /// HSE divider for PLL entry + PLLXTPRE: u1 = 0, + /// PLL Multiplication Factor + PLLMUL: u4 = 0, + /// USB OTG FS prescaler + OTGFSPRE: u1 = 0, reserved1: u1 = 0, - MCO: u3, // bit offset: 24 desc: Microcontroller clock output + /// Microcontroller clock output + MCO: u3 = 0, padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Clock interrupt register (RCC_CIR) + + /// Clock interrupt register (RCC_CIR) pub const CIR = mmio(Address + 0x00000008, 32, packed struct { - LSIRDYF: u1, // bit offset: 0 desc: LSI Ready Interrupt flag - LSERDYF: u1, // bit offset: 1 desc: LSE Ready Interrupt flag - HSIRDYF: u1, // bit offset: 2 desc: HSI Ready Interrupt flag - HSERDYF: u1, // bit offset: 3 desc: HSE Ready Interrupt flag - PLLRDYF: u1, // bit offset: 4 desc: PLL Ready Interrupt flag + /// LSI Ready Interrupt flag + LSIRDYF: u1 = 0, + /// LSE Ready Interrupt flag + LSERDYF: u1 = 0, + /// HSI Ready Interrupt flag + HSIRDYF: u1 = 0, + /// HSE Ready Interrupt flag + HSERDYF: u1 = 0, + /// PLL Ready Interrupt flag + PLLRDYF: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CSSF: u1, // bit offset: 7 desc: Clock Security System Interrupt flag - LSIRDYIE: u1, // bit offset: 8 desc: LSI Ready Interrupt Enable - LSERDYIE: u1, // bit offset: 9 desc: LSE Ready Interrupt Enable - HSIRDYIE: u1, // bit offset: 10 desc: HSI Ready Interrupt Enable - HSERDYIE: u1, // bit offset: 11 desc: HSE Ready Interrupt Enable - PLLRDYIE: u1, // bit offset: 12 desc: PLL Ready Interrupt Enable + /// Clock Security System Interrupt flag + CSSF: u1 = 0, + /// LSI Ready Interrupt Enable + LSIRDYIE: u1 = 0, + /// LSE Ready Interrupt Enable + LSERDYIE: u1 = 0, + /// HSI Ready Interrupt Enable + HSIRDYIE: u1 = 0, + /// HSE Ready Interrupt Enable + HSERDYIE: u1 = 0, + /// PLL Ready Interrupt Enable + PLLRDYIE: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - LSIRDYC: u1, // bit offset: 16 desc: LSI Ready Interrupt Clear - LSERDYC: u1, // bit offset: 17 desc: LSE Ready Interrupt Clear - HSIRDYC: u1, // bit offset: 18 desc: HSI Ready Interrupt Clear - HSERDYC: u1, // bit offset: 19 desc: HSE Ready Interrupt Clear - PLLRDYC: u1, // bit offset: 20 desc: PLL Ready Interrupt Clear + /// LSI Ready Interrupt Clear + LSIRDYC: u1 = 0, + /// LSE Ready Interrupt Clear + LSERDYC: u1 = 0, + /// HSI Ready Interrupt Clear + HSIRDYC: u1 = 0, + /// HSE Ready Interrupt Clear + HSERDYC: u1 = 0, + /// PLL Ready Interrupt Clear + PLLRDYC: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, - CSSC: u1, // bit offset: 23 desc: Clock security system interrupt clear + /// Clock security system interrupt clear + CSSC: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -638,30 +548,49 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 APB2 peripheral reset register (RCC_APB2RSTR) + + /// APB2 peripheral reset register (RCC_APB2RSTR) pub const APB2RSTR = mmio(Address + 0x0000000c, 32, packed struct { - AFIORST: u1, // bit offset: 0 desc: Alternate function I/O reset + /// Alternate function I/O reset + AFIORST: u1 = 0, reserved1: u1 = 0, - IOPARST: u1, // bit offset: 2 desc: IO port A reset - IOPBRST: u1, // bit offset: 3 desc: IO port B reset - IOPCRST: u1, // bit offset: 4 desc: IO port C reset - IOPDRST: u1, // bit offset: 5 desc: IO port D reset - IOPERST: u1, // bit offset: 6 desc: IO port E reset - IOPFRST: u1, // bit offset: 7 desc: IO port F reset - IOPGRST: u1, // bit offset: 8 desc: IO port G reset - ADC1RST: u1, // bit offset: 9 desc: ADC 1 interface reset - ADC2RST: u1, // bit offset: 10 desc: ADC 2 interface reset - TIM1RST: u1, // bit offset: 11 desc: TIM1 timer reset - SPI1RST: u1, // bit offset: 12 desc: SPI 1 reset - TIM8RST: u1, // bit offset: 13 desc: TIM8 timer reset - USART1RST: u1, // bit offset: 14 desc: USART1 reset - ADC3RST: u1, // bit offset: 15 desc: ADC 3 interface reset + /// IO port A reset + IOPARST: u1 = 0, + /// IO port B reset + IOPBRST: u1 = 0, + /// IO port C reset + IOPCRST: u1 = 0, + /// IO port D reset + IOPDRST: u1 = 0, + /// IO port E reset + IOPERST: u1 = 0, + /// IO port F reset + IOPFRST: u1 = 0, + /// IO port G reset + IOPGRST: u1 = 0, + /// ADC 1 interface reset + ADC1RST: u1 = 0, + /// ADC 2 interface reset + ADC2RST: u1 = 0, + /// TIM1 timer reset + TIM1RST: u1 = 0, + /// SPI 1 reset + SPI1RST: u1 = 0, + /// TIM8 timer reset + TIM8RST: u1 = 0, + /// USART1 reset + USART1RST: u1 = 0, + /// ADC 3 interface reset + ADC3RST: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - TIM9RST: u1, // bit offset: 19 desc: TIM9 timer reset - TIM10RST: u1, // bit offset: 20 desc: TIM10 timer reset - TIM11RST: u1, // bit offset: 21 desc: TIM11 timer reset + /// TIM9 timer reset + TIM9RST: u1 = 0, + /// TIM10 timer reset + TIM10RST: u1 = 0, + /// TIM11 timer reset + TIM11RST: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, @@ -673,54 +602,86 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 APB1 peripheral reset register (RCC_APB1RSTR) + + /// APB1 peripheral reset register (RCC_APB1RSTR) pub const APB1RSTR = mmio(Address + 0x00000010, 32, packed struct { - TIM2RST: u1, // bit offset: 0 desc: Timer 2 reset - TIM3RST: u1, // bit offset: 1 desc: Timer 3 reset - TIM4RST: u1, // bit offset: 2 desc: Timer 4 reset - TIM5RST: u1, // bit offset: 3 desc: Timer 5 reset - TIM6RST: u1, // bit offset: 4 desc: Timer 6 reset - TIM7RST: u1, // bit offset: 5 desc: Timer 7 reset - TIM12RST: u1, // bit offset: 6 desc: Timer 12 reset - TIM13RST: u1, // bit offset: 7 desc: Timer 13 reset - TIM14RST: u1, // bit offset: 8 desc: Timer 14 reset + /// Timer 2 reset + TIM2RST: u1 = 0, + /// Timer 3 reset + TIM3RST: u1 = 0, + /// Timer 4 reset + TIM4RST: u1 = 0, + /// Timer 5 reset + TIM5RST: u1 = 0, + /// Timer 6 reset + TIM6RST: u1 = 0, + /// Timer 7 reset + TIM7RST: u1 = 0, + /// Timer 12 reset + TIM12RST: u1 = 0, + /// Timer 13 reset + TIM13RST: u1 = 0, + /// Timer 14 reset + TIM14RST: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - WWDGRST: u1, // bit offset: 11 desc: Window watchdog reset + /// Window watchdog reset + WWDGRST: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - SPI2RST: u1, // bit offset: 14 desc: SPI2 reset - SPI3RST: u1, // bit offset: 15 desc: SPI3 reset + /// SPI2 reset + SPI2RST: u1 = 0, + /// SPI3 reset + SPI3RST: u1 = 0, reserved5: u1 = 0, - USART2RST: u1, // bit offset: 17 desc: USART 2 reset - USART3RST: u1, // bit offset: 18 desc: USART 3 reset - UART4RST: u1, // bit offset: 19 desc: UART 4 reset - UART5RST: u1, // bit offset: 20 desc: UART 5 reset - I2C1RST: u1, // bit offset: 21 desc: I2C1 reset - I2C2RST: u1, // bit offset: 22 desc: I2C2 reset - USBRST: u1, // bit offset: 23 desc: USB reset + /// USART 2 reset + USART2RST: u1 = 0, + /// USART 3 reset + USART3RST: u1 = 0, + /// UART 4 reset + UART4RST: u1 = 0, + /// UART 5 reset + UART5RST: u1 = 0, + /// I2C1 reset + I2C1RST: u1 = 0, + /// I2C2 reset + I2C2RST: u1 = 0, + /// USB reset + USBRST: u1 = 0, reserved6: u1 = 0, - CANRST: u1, // bit offset: 25 desc: CAN reset + /// CAN reset + CANRST: u1 = 0, reserved7: u1 = 0, - BKPRST: u1, // bit offset: 27 desc: Backup interface reset - PWRRST: u1, // bit offset: 28 desc: Power interface reset - DACRST: u1, // bit offset: 29 desc: DAC interface reset + /// Backup interface reset + BKPRST: u1 = 0, + /// Power interface reset + PWRRST: u1 = 0, + /// DAC interface reset + DACRST: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 AHB Peripheral Clock enable register (RCC_AHBENR) + + /// AHB Peripheral Clock enable register (RCC_AHBENR) pub const AHBENR = mmio(Address + 0x00000014, 32, packed struct { - DMA1EN: u1, // bit offset: 0 desc: DMA1 clock enable - DMA2EN: u1, // bit offset: 1 desc: DMA2 clock enable - SRAMEN: u1, // bit offset: 2 desc: SRAM interface clock enable + /// DMA1 clock enable + DMA1EN: u1 = 0, + /// DMA2 clock enable + DMA2EN: u1 = 0, + /// SRAM interface clock enable + SRAMEN: u1 = 0, reserved1: u1 = 0, - FLITFEN: u1, // bit offset: 4 desc: FLITF clock enable + /// FLITF clock enable + FLITFEN: u1 = 0, reserved2: u1 = 0, - CRCEN: u1, // bit offset: 6 desc: CRC clock enable + /// CRC clock enable + CRCEN: u1 = 0, reserved3: u1 = 0, - FSMCEN: u1, // bit offset: 8 desc: FSMC clock enable + /// FSMC clock enable + FSMCEN: u1 = 0, reserved4: u1 = 0, - SDIOEN: u1, // bit offset: 10 desc: SDIO clock enable + /// SDIO clock enable + SDIOEN: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -743,30 +704,49 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 APB2 peripheral clock enable register (RCC_APB2ENR) + + /// APB2 peripheral clock enable register (RCC_APB2ENR) pub const APB2ENR = mmio(Address + 0x00000018, 32, packed struct { - AFIOEN: u1, // bit offset: 0 desc: Alternate function I/O clock enable + /// Alternate function I/O clock enable + AFIOEN: u1 = 0, reserved1: u1 = 0, - IOPAEN: u1, // bit offset: 2 desc: I/O port A clock enable - IOPBEN: u1, // bit offset: 3 desc: I/O port B clock enable - IOPCEN: u1, // bit offset: 4 desc: I/O port C clock enable - IOPDEN: u1, // bit offset: 5 desc: I/O port D clock enable - IOPEEN: u1, // bit offset: 6 desc: I/O port E clock enable - IOPFEN: u1, // bit offset: 7 desc: I/O port F clock enable - IOPGEN: u1, // bit offset: 8 desc: I/O port G clock enable - ADC1EN: u1, // bit offset: 9 desc: ADC 1 interface clock enable - ADC2EN: u1, // bit offset: 10 desc: ADC 2 interface clock enable - TIM1EN: u1, // bit offset: 11 desc: TIM1 Timer clock enable - SPI1EN: u1, // bit offset: 12 desc: SPI 1 clock enable - TIM8EN: u1, // bit offset: 13 desc: TIM8 Timer clock enable - USART1EN: u1, // bit offset: 14 desc: USART1 clock enable - ADC3EN: u1, // bit offset: 15 desc: ADC3 interface clock enable + /// I/O port A clock enable + IOPAEN: u1 = 0, + /// I/O port B clock enable + IOPBEN: u1 = 0, + /// I/O port C clock enable + IOPCEN: u1 = 0, + /// I/O port D clock enable + IOPDEN: u1 = 0, + /// I/O port E clock enable + IOPEEN: u1 = 0, + /// I/O port F clock enable + IOPFEN: u1 = 0, + /// I/O port G clock enable + IOPGEN: u1 = 0, + /// ADC 1 interface clock enable + ADC1EN: u1 = 0, + /// ADC 2 interface clock enable + ADC2EN: u1 = 0, + /// TIM1 Timer clock enable + TIM1EN: u1 = 0, + /// SPI 1 clock enable + SPI1EN: u1 = 0, + /// TIM8 Timer clock enable + TIM8EN: u1 = 0, + /// USART1 clock enable + USART1EN: u1 = 0, + /// ADC3 interface clock enable + ADC3EN: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - TIM9EN: u1, // bit offset: 19 desc: TIM9 Timer clock enable - TIM10EN: u1, // bit offset: 20 desc: TIM10 Timer clock enable - TIM11EN: u1, // bit offset: 21 desc: TIM11 Timer clock enable + /// TIM9 Timer clock enable + TIM9EN: u1 = 0, + /// TIM10 Timer clock enable + TIM10EN: u1 = 0, + /// TIM11 Timer clock enable + TIM11EN: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, @@ -778,59 +758,90 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 APB1 peripheral clock enable register (RCC_APB1ENR) + + /// APB1 peripheral clock enable register (RCC_APB1ENR) pub const APB1ENR = mmio(Address + 0x0000001c, 32, packed struct { - TIM2EN: u1, // bit offset: 0 desc: Timer 2 clock enable - TIM3EN: u1, // bit offset: 1 desc: Timer 3 clock enable - TIM4EN: u1, // bit offset: 2 desc: Timer 4 clock enable - TIM5EN: u1, // bit offset: 3 desc: Timer 5 clock enable - TIM6EN: u1, // bit offset: 4 desc: Timer 6 clock enable - TIM7EN: u1, // bit offset: 5 desc: Timer 7 clock enable - TIM12EN: u1, // bit offset: 6 desc: Timer 12 clock enable - TIM13EN: u1, // bit offset: 7 desc: Timer 13 clock enable - TIM14EN: u1, // bit offset: 8 desc: Timer 14 clock enable + /// Timer 2 clock enable + TIM2EN: u1 = 0, + /// Timer 3 clock enable + TIM3EN: u1 = 0, + /// Timer 4 clock enable + TIM4EN: u1 = 0, + /// Timer 5 clock enable + TIM5EN: u1 = 0, + /// Timer 6 clock enable + TIM6EN: u1 = 0, + /// Timer 7 clock enable + TIM7EN: u1 = 0, + /// Timer 12 clock enable + TIM12EN: u1 = 0, + /// Timer 13 clock enable + TIM13EN: u1 = 0, + /// Timer 14 clock enable + TIM14EN: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - WWDGEN: u1, // bit offset: 11 desc: Window watchdog clock enable + /// Window watchdog clock enable + WWDGEN: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - SPI2EN: u1, // bit offset: 14 desc: SPI 2 clock enable - SPI3EN: u1, // bit offset: 15 desc: SPI 3 clock enable + /// SPI 2 clock enable + SPI2EN: u1 = 0, + /// SPI 3 clock enable + SPI3EN: u1 = 0, reserved5: u1 = 0, - USART2EN: u1, // bit offset: 17 desc: USART 2 clock enable - USART3EN: u1, // bit offset: 18 desc: USART 3 clock enable - UART4EN: u1, // bit offset: 19 desc: UART 4 clock enable - UART5EN: u1, // bit offset: 20 desc: UART 5 clock enable - I2C1EN: u1, // bit offset: 21 desc: I2C 1 clock enable - I2C2EN: u1, // bit offset: 22 desc: I2C 2 clock enable - USBEN: u1, // bit offset: 23 desc: USB clock enable + /// USART 2 clock enable + USART2EN: u1 = 0, + /// USART 3 clock enable + USART3EN: u1 = 0, + /// UART 4 clock enable + UART4EN: u1 = 0, + /// UART 5 clock enable + UART5EN: u1 = 0, + /// I2C 1 clock enable + I2C1EN: u1 = 0, + /// I2C 2 clock enable + I2C2EN: u1 = 0, + /// USB clock enable + USBEN: u1 = 0, reserved6: u1 = 0, - CANEN: u1, // bit offset: 25 desc: CAN clock enable + /// CAN clock enable + CANEN: u1 = 0, reserved7: u1 = 0, - BKPEN: u1, // bit offset: 27 desc: Backup interface clock enable - PWREN: u1, // bit offset: 28 desc: Power interface clock enable - DACEN: u1, // bit offset: 29 desc: DAC interface clock enable + /// Backup interface clock enable + BKPEN: u1 = 0, + /// Power interface clock enable + PWREN: u1 = 0, + /// DAC interface clock enable + DACEN: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 Backup domain control register (RCC_BDCR) + + /// Backup domain control register (RCC_BDCR) pub const BDCR = mmio(Address + 0x00000020, 32, packed struct { - LSEON: u1, // bit offset: 0 desc: External Low Speed oscillator enable - LSERDY: u1, // bit offset: 1 desc: External Low Speed oscillator ready - LSEBYP: u1, // bit offset: 2 desc: External Low Speed oscillator bypass + /// External Low Speed oscillator enable + LSEON: u1 = 0, + /// External Low Speed oscillator ready + LSERDY: u1 = 0, + /// External Low Speed oscillator bypass + LSEBYP: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - RTCSEL: u2, // bit offset: 8 desc: RTC clock source selection + /// RTC clock source selection + RTCSEL: u2 = 0, reserved10: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, - RTCEN: u1, // bit offset: 15 desc: RTC clock enable - BDRST: u1, // bit offset: 16 desc: Backup domain software reset + /// RTC clock enable + RTCEN: u1 = 0, + /// Backup domain software reset + BDRST: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -847,10 +858,13 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 Control/status register (RCC_CSR) + + /// Control/status register (RCC_CSR) pub const CSR = mmio(Address + 0x00000024, 32, packed struct { - LSION: u1, // bit offset: 0 desc: Internal low speed oscillator enable - LSIRDY: u1, // bit offset: 1 desc: Internal low speed oscillator ready + /// Internal low speed oscillator enable + LSION: u1 = 0, + /// Internal low speed oscillator ready + LSIRDY: u1 = 0, reserved22: u1 = 0, reserved21: u1 = 0, reserved20: u1 = 0, @@ -873,74 +887,134 @@ pub const RCC = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - RMVF: u1, // bit offset: 24 desc: Remove reset flag + /// Remove reset flag + RMVF: u1 = 0, reserved23: u1 = 0, - PINRSTF: u1, // bit offset: 26 desc: PIN reset flag - PORRSTF: u1, // bit offset: 27 desc: POR/PDR reset flag - SFTRSTF: u1, // bit offset: 28 desc: Software reset flag - IWDGRSTF: u1, // bit offset: 29 desc: Independent watchdog reset flag - WWDGRSTF: u1, // bit offset: 30 desc: Window watchdog reset flag - LPWRRSTF: u1, // bit offset: 31 desc: Low-power reset flag + /// PIN reset flag + PINRSTF: u1 = 0, + /// POR/PDR reset flag + PORRSTF: u1 = 0, + /// Software reset flag + SFTRSTF: u1 = 0, + /// Independent watchdog reset flag + IWDGRSTF: u1 = 0, + /// Window watchdog reset flag + WWDGRSTF: u1 = 0, + /// Low-power reset flag + LPWRRSTF: u1 = 0, }); }; + +/// General purpose I/O pub const GPIOA = extern struct { pub const Address: u32 = 0x40010800; - // byte offset: 0 Port configuration register low (GPIOn_CRL) + + /// Port configuration register low (GPIOn_CRL) pub const CRL = mmio(Address + 0x00000000, 32, packed struct { - MODE0: u2, // bit offset: 0 desc: Port n.0 mode bits - CNF0: u2, // bit offset: 2 desc: Port n.0 configuration bits - MODE1: u2, // bit offset: 4 desc: Port n.1 mode bits - CNF1: u2, // bit offset: 6 desc: Port n.1 configuration bits - MODE2: u2, // bit offset: 8 desc: Port n.2 mode bits - CNF2: u2, // bit offset: 10 desc: Port n.2 configuration bits - MODE3: u2, // bit offset: 12 desc: Port n.3 mode bits - CNF3: u2, // bit offset: 14 desc: Port n.3 configuration bits - MODE4: u2, // bit offset: 16 desc: Port n.4 mode bits - CNF4: u2, // bit offset: 18 desc: Port n.4 configuration bits - MODE5: u2, // bit offset: 20 desc: Port n.5 mode bits - CNF5: u2, // bit offset: 22 desc: Port n.5 configuration bits - MODE6: u2, // bit offset: 24 desc: Port n.6 mode bits - CNF6: u2, // bit offset: 26 desc: Port n.6 configuration bits - MODE7: u2, // bit offset: 28 desc: Port n.7 mode bits - CNF7: u2, // bit offset: 30 desc: Port n.7 configuration bits - }); - // byte offset: 4 Port configuration register high (GPIOn_CRL) + /// Port n.0 mode bits + MODE0: u2 = 0, + /// Port n.0 configuration bits + CNF0: u2 = 0, + /// Port n.1 mode bits + MODE1: u2 = 0, + /// Port n.1 configuration bits + CNF1: u2 = 0, + /// Port n.2 mode bits + MODE2: u2 = 0, + /// Port n.2 configuration bits + CNF2: u2 = 0, + /// Port n.3 mode bits + MODE3: u2 = 0, + /// Port n.3 configuration bits + CNF3: u2 = 0, + /// Port n.4 mode bits + MODE4: u2 = 0, + /// Port n.4 configuration bits + CNF4: u2 = 0, + /// Port n.5 mode bits + MODE5: u2 = 0, + /// Port n.5 configuration bits + CNF5: u2 = 0, + /// Port n.6 mode bits + MODE6: u2 = 0, + /// Port n.6 configuration bits + CNF6: u2 = 0, + /// Port n.7 mode bits + MODE7: u2 = 0, + /// Port n.7 configuration bits + CNF7: u2 = 0, + }); + + /// Port configuration register high (GPIOn_CRL) pub const CRH = mmio(Address + 0x00000004, 32, packed struct { - MODE8: u2, // bit offset: 0 desc: Port n.8 mode bits - CNF8: u2, // bit offset: 2 desc: Port n.8 configuration bits - MODE9: u2, // bit offset: 4 desc: Port n.9 mode bits - CNF9: u2, // bit offset: 6 desc: Port n.9 configuration bits - MODE10: u2, // bit offset: 8 desc: Port n.10 mode bits - CNF10: u2, // bit offset: 10 desc: Port n.10 configuration bits - MODE11: u2, // bit offset: 12 desc: Port n.11 mode bits - CNF11: u2, // bit offset: 14 desc: Port n.11 configuration bits - MODE12: u2, // bit offset: 16 desc: Port n.12 mode bits - CNF12: u2, // bit offset: 18 desc: Port n.12 configuration bits - MODE13: u2, // bit offset: 20 desc: Port n.13 mode bits - CNF13: u2, // bit offset: 22 desc: Port n.13 configuration bits - MODE14: u2, // bit offset: 24 desc: Port n.14 mode bits - CNF14: u2, // bit offset: 26 desc: Port n.14 configuration bits - MODE15: u2, // bit offset: 28 desc: Port n.15 mode bits - CNF15: u2, // bit offset: 30 desc: Port n.15 configuration bits - }); - // byte offset: 8 Port input data register (GPIOn_IDR) + /// Port n.8 mode bits + MODE8: u2 = 0, + /// Port n.8 configuration bits + CNF8: u2 = 0, + /// Port n.9 mode bits + MODE9: u2 = 0, + /// Port n.9 configuration bits + CNF9: u2 = 0, + /// Port n.10 mode bits + MODE10: u2 = 0, + /// Port n.10 configuration bits + CNF10: u2 = 0, + /// Port n.11 mode bits + MODE11: u2 = 0, + /// Port n.11 configuration bits + CNF11: u2 = 0, + /// Port n.12 mode bits + MODE12: u2 = 0, + /// Port n.12 configuration bits + CNF12: u2 = 0, + /// Port n.13 mode bits + MODE13: u2 = 0, + /// Port n.13 configuration bits + CNF13: u2 = 0, + /// Port n.14 mode bits + MODE14: u2 = 0, + /// Port n.14 configuration bits + CNF14: u2 = 0, + /// Port n.15 mode bits + MODE15: u2 = 0, + /// Port n.15 configuration bits + CNF15: u2 = 0, + }); + + /// Port input data register (GPIOn_IDR) pub const IDR = mmio(Address + 0x00000008, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data - IDR1: u1, // bit offset: 1 desc: Port input data - IDR2: u1, // bit offset: 2 desc: Port input data - IDR3: u1, // bit offset: 3 desc: Port input data - IDR4: u1, // bit offset: 4 desc: Port input data - IDR5: u1, // bit offset: 5 desc: Port input data - IDR6: u1, // bit offset: 6 desc: Port input data - IDR7: u1, // bit offset: 7 desc: Port input data - IDR8: u1, // bit offset: 8 desc: Port input data - IDR9: u1, // bit offset: 9 desc: Port input data - IDR10: u1, // bit offset: 10 desc: Port input data - IDR11: u1, // bit offset: 11 desc: Port input data - IDR12: u1, // bit offset: 12 desc: Port input data - IDR13: u1, // bit offset: 13 desc: Port input data - IDR14: u1, // bit offset: 14 desc: Port input data - IDR15: u1, // bit offset: 15 desc: Port input data + /// Port input data + IDR0: u1 = 0, + /// Port input data + IDR1: u1 = 0, + /// Port input data + IDR2: u1 = 0, + /// Port input data + IDR3: u1 = 0, + /// Port input data + IDR4: u1 = 0, + /// Port input data + IDR5: u1 = 0, + /// Port input data + IDR6: u1 = 0, + /// Port input data + IDR7: u1 = 0, + /// Port input data + IDR8: u1 = 0, + /// Port input data + IDR9: u1 = 0, + /// Port input data + IDR10: u1 = 0, + /// Port input data + IDR11: u1 = 0, + /// Port input data + IDR12: u1 = 0, + /// Port input data + IDR13: u1 = 0, + /// Port input data + IDR14: u1 = 0, + /// Port input data + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -958,24 +1032,41 @@ pub const GPIOA = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Port output data register (GPIOn_ODR) + + /// Port output data register (GPIOn_ODR) pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data - ODR1: u1, // bit offset: 1 desc: Port output data - ODR2: u1, // bit offset: 2 desc: Port output data - ODR3: u1, // bit offset: 3 desc: Port output data - ODR4: u1, // bit offset: 4 desc: Port output data - ODR5: u1, // bit offset: 5 desc: Port output data - ODR6: u1, // bit offset: 6 desc: Port output data - ODR7: u1, // bit offset: 7 desc: Port output data - ODR8: u1, // bit offset: 8 desc: Port output data - ODR9: u1, // bit offset: 9 desc: Port output data - ODR10: u1, // bit offset: 10 desc: Port output data - ODR11: u1, // bit offset: 11 desc: Port output data - ODR12: u1, // bit offset: 12 desc: Port output data - ODR13: u1, // bit offset: 13 desc: Port output data - ODR14: u1, // bit offset: 14 desc: Port output data - ODR15: u1, // bit offset: 15 desc: Port output data + /// Port output data + ODR0: u1 = 0, + /// Port output data + ODR1: u1 = 0, + /// Port output data + ODR2: u1 = 0, + /// Port output data + ODR3: u1 = 0, + /// Port output data + ODR4: u1 = 0, + /// Port output data + ODR5: u1 = 0, + /// Port output data + ODR6: u1 = 0, + /// Port output data + ODR7: u1 = 0, + /// Port output data + ODR8: u1 = 0, + /// Port output data + ODR9: u1 = 0, + /// Port output data + ODR10: u1 = 0, + /// Port output data + ODR11: u1 = 0, + /// Port output data + ODR12: u1 = 0, + /// Port output data + ODR13: u1 = 0, + /// Port output data + ODR14: u1 = 0, + /// Port output data + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -993,59 +1084,109 @@ pub const GPIOA = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Port bit set/reset register (GPIOn_BSRR) + + /// Port bit set/reset register (GPIOn_BSRR) pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Set bit 0 - BS1: u1, // bit offset: 1 desc: Set bit 1 - BS2: u1, // bit offset: 2 desc: Set bit 1 - BS3: u1, // bit offset: 3 desc: Set bit 3 - BS4: u1, // bit offset: 4 desc: Set bit 4 - BS5: u1, // bit offset: 5 desc: Set bit 5 - BS6: u1, // bit offset: 6 desc: Set bit 6 - BS7: u1, // bit offset: 7 desc: Set bit 7 - BS8: u1, // bit offset: 8 desc: Set bit 8 - BS9: u1, // bit offset: 9 desc: Set bit 9 - BS10: u1, // bit offset: 10 desc: Set bit 10 - BS11: u1, // bit offset: 11 desc: Set bit 11 - BS12: u1, // bit offset: 12 desc: Set bit 12 - BS13: u1, // bit offset: 13 desc: Set bit 13 - BS14: u1, // bit offset: 14 desc: Set bit 14 - BS15: u1, // bit offset: 15 desc: Set bit 15 - BR0: u1, // bit offset: 16 desc: Reset bit 0 - BR1: u1, // bit offset: 17 desc: Reset bit 1 - BR2: u1, // bit offset: 18 desc: Reset bit 2 - BR3: u1, // bit offset: 19 desc: Reset bit 3 - BR4: u1, // bit offset: 20 desc: Reset bit 4 - BR5: u1, // bit offset: 21 desc: Reset bit 5 - BR6: u1, // bit offset: 22 desc: Reset bit 6 - BR7: u1, // bit offset: 23 desc: Reset bit 7 - BR8: u1, // bit offset: 24 desc: Reset bit 8 - BR9: u1, // bit offset: 25 desc: Reset bit 9 - BR10: u1, // bit offset: 26 desc: Reset bit 10 - BR11: u1, // bit offset: 27 desc: Reset bit 11 - BR12: u1, // bit offset: 28 desc: Reset bit 12 - BR13: u1, // bit offset: 29 desc: Reset bit 13 - BR14: u1, // bit offset: 30 desc: Reset bit 14 - BR15: u1, // bit offset: 31 desc: Reset bit 15 - }); - // byte offset: 20 Port bit reset register (GPIOn_BRR) + /// Set bit 0 + BS0: u1 = 0, + /// Set bit 1 + BS1: u1 = 0, + /// Set bit 1 + BS2: u1 = 0, + /// Set bit 3 + BS3: u1 = 0, + /// Set bit 4 + BS4: u1 = 0, + /// Set bit 5 + BS5: u1 = 0, + /// Set bit 6 + BS6: u1 = 0, + /// Set bit 7 + BS7: u1 = 0, + /// Set bit 8 + BS8: u1 = 0, + /// Set bit 9 + BS9: u1 = 0, + /// Set bit 10 + BS10: u1 = 0, + /// Set bit 11 + BS11: u1 = 0, + /// Set bit 12 + BS12: u1 = 0, + /// Set bit 13 + BS13: u1 = 0, + /// Set bit 14 + BS14: u1 = 0, + /// Set bit 15 + BS15: u1 = 0, + /// Reset bit 0 + BR0: u1 = 0, + /// Reset bit 1 + BR1: u1 = 0, + /// Reset bit 2 + BR2: u1 = 0, + /// Reset bit 3 + BR3: u1 = 0, + /// Reset bit 4 + BR4: u1 = 0, + /// Reset bit 5 + BR5: u1 = 0, + /// Reset bit 6 + BR6: u1 = 0, + /// Reset bit 7 + BR7: u1 = 0, + /// Reset bit 8 + BR8: u1 = 0, + /// Reset bit 9 + BR9: u1 = 0, + /// Reset bit 10 + BR10: u1 = 0, + /// Reset bit 11 + BR11: u1 = 0, + /// Reset bit 12 + BR12: u1 = 0, + /// Reset bit 13 + BR13: u1 = 0, + /// Reset bit 14 + BR14: u1 = 0, + /// Reset bit 15 + BR15: u1 = 0, + }); + + /// Port bit reset register (GPIOn_BRR) pub const BRR = mmio(Address + 0x00000014, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Reset bit 0 - BR1: u1, // bit offset: 1 desc: Reset bit 1 - BR2: u1, // bit offset: 2 desc: Reset bit 1 - BR3: u1, // bit offset: 3 desc: Reset bit 3 - BR4: u1, // bit offset: 4 desc: Reset bit 4 - BR5: u1, // bit offset: 5 desc: Reset bit 5 - BR6: u1, // bit offset: 6 desc: Reset bit 6 - BR7: u1, // bit offset: 7 desc: Reset bit 7 - BR8: u1, // bit offset: 8 desc: Reset bit 8 - BR9: u1, // bit offset: 9 desc: Reset bit 9 - BR10: u1, // bit offset: 10 desc: Reset bit 10 - BR11: u1, // bit offset: 11 desc: Reset bit 11 - BR12: u1, // bit offset: 12 desc: Reset bit 12 - BR13: u1, // bit offset: 13 desc: Reset bit 13 - BR14: u1, // bit offset: 14 desc: Reset bit 14 - BR15: u1, // bit offset: 15 desc: Reset bit 15 + /// Reset bit 0 + BR0: u1 = 0, + /// Reset bit 1 + BR1: u1 = 0, + /// Reset bit 1 + BR2: u1 = 0, + /// Reset bit 3 + BR3: u1 = 0, + /// Reset bit 4 + BR4: u1 = 0, + /// Reset bit 5 + BR5: u1 = 0, + /// Reset bit 6 + BR6: u1 = 0, + /// Reset bit 7 + BR7: u1 = 0, + /// Reset bit 8 + BR8: u1 = 0, + /// Reset bit 9 + BR9: u1 = 0, + /// Reset bit 10 + BR10: u1 = 0, + /// Reset bit 11 + BR11: u1 = 0, + /// Reset bit 12 + BR12: u1 = 0, + /// Reset bit 13 + BR13: u1 = 0, + /// Reset bit 14 + BR14: u1 = 0, + /// Reset bit 15 + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1063,25 +1204,43 @@ pub const GPIOA = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 Port configuration lock register + + /// Port configuration lock register pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port A Lock bit 0 - LCK1: u1, // bit offset: 1 desc: Port A Lock bit 1 - LCK2: u1, // bit offset: 2 desc: Port A Lock bit 2 - LCK3: u1, // bit offset: 3 desc: Port A Lock bit 3 - LCK4: u1, // bit offset: 4 desc: Port A Lock bit 4 - LCK5: u1, // bit offset: 5 desc: Port A Lock bit 5 - LCK6: u1, // bit offset: 6 desc: Port A Lock bit 6 - LCK7: u1, // bit offset: 7 desc: Port A Lock bit 7 - LCK8: u1, // bit offset: 8 desc: Port A Lock bit 8 - LCK9: u1, // bit offset: 9 desc: Port A Lock bit 9 - LCK10: u1, // bit offset: 10 desc: Port A Lock bit 10 - LCK11: u1, // bit offset: 11 desc: Port A Lock bit 11 - LCK12: u1, // bit offset: 12 desc: Port A Lock bit 12 - LCK13: u1, // bit offset: 13 desc: Port A Lock bit 13 - LCK14: u1, // bit offset: 14 desc: Port A Lock bit 14 - LCK15: u1, // bit offset: 15 desc: Port A Lock bit 15 - LCKK: u1, // bit offset: 16 desc: Lock key + /// Port A Lock bit 0 + LCK0: u1 = 0, + /// Port A Lock bit 1 + LCK1: u1 = 0, + /// Port A Lock bit 2 + LCK2: u1 = 0, + /// Port A Lock bit 3 + LCK3: u1 = 0, + /// Port A Lock bit 4 + LCK4: u1 = 0, + /// Port A Lock bit 5 + LCK5: u1 = 0, + /// Port A Lock bit 6 + LCK6: u1 = 0, + /// Port A Lock bit 7 + LCK7: u1 = 0, + /// Port A Lock bit 8 + LCK8: u1 = 0, + /// Port A Lock bit 9 + LCK9: u1 = 0, + /// Port A Lock bit 10 + LCK10: u1 = 0, + /// Port A Lock bit 11 + LCK11: u1 = 0, + /// Port A Lock bit 12 + LCK12: u1 = 0, + /// Port A Lock bit 13 + LCK13: u1 = 0, + /// Port A Lock bit 14 + LCK14: u1 = 0, + /// Port A Lock bit 15 + LCK15: u1 = 0, + /// Lock key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -1099,64 +1258,117 @@ pub const GPIOA = extern struct { padding1: u1 = 0, }); }; + +/// General purpose I/O pub const GPIOB = extern struct { pub const Address: u32 = 0x40010c00; - // byte offset: 0 Port configuration register low (GPIOn_CRL) + + /// Port configuration register low (GPIOn_CRL) pub const CRL = mmio(Address + 0x00000000, 32, packed struct { - MODE0: u2, // bit offset: 0 desc: Port n.0 mode bits - CNF0: u2, // bit offset: 2 desc: Port n.0 configuration bits - MODE1: u2, // bit offset: 4 desc: Port n.1 mode bits - CNF1: u2, // bit offset: 6 desc: Port n.1 configuration bits - MODE2: u2, // bit offset: 8 desc: Port n.2 mode bits - CNF2: u2, // bit offset: 10 desc: Port n.2 configuration bits - MODE3: u2, // bit offset: 12 desc: Port n.3 mode bits - CNF3: u2, // bit offset: 14 desc: Port n.3 configuration bits - MODE4: u2, // bit offset: 16 desc: Port n.4 mode bits - CNF4: u2, // bit offset: 18 desc: Port n.4 configuration bits - MODE5: u2, // bit offset: 20 desc: Port n.5 mode bits - CNF5: u2, // bit offset: 22 desc: Port n.5 configuration bits - MODE6: u2, // bit offset: 24 desc: Port n.6 mode bits - CNF6: u2, // bit offset: 26 desc: Port n.6 configuration bits - MODE7: u2, // bit offset: 28 desc: Port n.7 mode bits - CNF7: u2, // bit offset: 30 desc: Port n.7 configuration bits - }); - // byte offset: 4 Port configuration register high (GPIOn_CRL) + /// Port n.0 mode bits + MODE0: u2 = 0, + /// Port n.0 configuration bits + CNF0: u2 = 0, + /// Port n.1 mode bits + MODE1: u2 = 0, + /// Port n.1 configuration bits + CNF1: u2 = 0, + /// Port n.2 mode bits + MODE2: u2 = 0, + /// Port n.2 configuration bits + CNF2: u2 = 0, + /// Port n.3 mode bits + MODE3: u2 = 0, + /// Port n.3 configuration bits + CNF3: u2 = 0, + /// Port n.4 mode bits + MODE4: u2 = 0, + /// Port n.4 configuration bits + CNF4: u2 = 0, + /// Port n.5 mode bits + MODE5: u2 = 0, + /// Port n.5 configuration bits + CNF5: u2 = 0, + /// Port n.6 mode bits + MODE6: u2 = 0, + /// Port n.6 configuration bits + CNF6: u2 = 0, + /// Port n.7 mode bits + MODE7: u2 = 0, + /// Port n.7 configuration bits + CNF7: u2 = 0, + }); + + /// Port configuration register high (GPIOn_CRL) pub const CRH = mmio(Address + 0x00000004, 32, packed struct { - MODE8: u2, // bit offset: 0 desc: Port n.8 mode bits - CNF8: u2, // bit offset: 2 desc: Port n.8 configuration bits - MODE9: u2, // bit offset: 4 desc: Port n.9 mode bits - CNF9: u2, // bit offset: 6 desc: Port n.9 configuration bits - MODE10: u2, // bit offset: 8 desc: Port n.10 mode bits - CNF10: u2, // bit offset: 10 desc: Port n.10 configuration bits - MODE11: u2, // bit offset: 12 desc: Port n.11 mode bits - CNF11: u2, // bit offset: 14 desc: Port n.11 configuration bits - MODE12: u2, // bit offset: 16 desc: Port n.12 mode bits - CNF12: u2, // bit offset: 18 desc: Port n.12 configuration bits - MODE13: u2, // bit offset: 20 desc: Port n.13 mode bits - CNF13: u2, // bit offset: 22 desc: Port n.13 configuration bits - MODE14: u2, // bit offset: 24 desc: Port n.14 mode bits - CNF14: u2, // bit offset: 26 desc: Port n.14 configuration bits - MODE15: u2, // bit offset: 28 desc: Port n.15 mode bits - CNF15: u2, // bit offset: 30 desc: Port n.15 configuration bits - }); - // byte offset: 8 Port input data register (GPIOn_IDR) + /// Port n.8 mode bits + MODE8: u2 = 0, + /// Port n.8 configuration bits + CNF8: u2 = 0, + /// Port n.9 mode bits + MODE9: u2 = 0, + /// Port n.9 configuration bits + CNF9: u2 = 0, + /// Port n.10 mode bits + MODE10: u2 = 0, + /// Port n.10 configuration bits + CNF10: u2 = 0, + /// Port n.11 mode bits + MODE11: u2 = 0, + /// Port n.11 configuration bits + CNF11: u2 = 0, + /// Port n.12 mode bits + MODE12: u2 = 0, + /// Port n.12 configuration bits + CNF12: u2 = 0, + /// Port n.13 mode bits + MODE13: u2 = 0, + /// Port n.13 configuration bits + CNF13: u2 = 0, + /// Port n.14 mode bits + MODE14: u2 = 0, + /// Port n.14 configuration bits + CNF14: u2 = 0, + /// Port n.15 mode bits + MODE15: u2 = 0, + /// Port n.15 configuration bits + CNF15: u2 = 0, + }); + + /// Port input data register (GPIOn_IDR) pub const IDR = mmio(Address + 0x00000008, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data - IDR1: u1, // bit offset: 1 desc: Port input data - IDR2: u1, // bit offset: 2 desc: Port input data - IDR3: u1, // bit offset: 3 desc: Port input data - IDR4: u1, // bit offset: 4 desc: Port input data - IDR5: u1, // bit offset: 5 desc: Port input data - IDR6: u1, // bit offset: 6 desc: Port input data - IDR7: u1, // bit offset: 7 desc: Port input data - IDR8: u1, // bit offset: 8 desc: Port input data - IDR9: u1, // bit offset: 9 desc: Port input data - IDR10: u1, // bit offset: 10 desc: Port input data - IDR11: u1, // bit offset: 11 desc: Port input data - IDR12: u1, // bit offset: 12 desc: Port input data - IDR13: u1, // bit offset: 13 desc: Port input data - IDR14: u1, // bit offset: 14 desc: Port input data - IDR15: u1, // bit offset: 15 desc: Port input data + /// Port input data + IDR0: u1 = 0, + /// Port input data + IDR1: u1 = 0, + /// Port input data + IDR2: u1 = 0, + /// Port input data + IDR3: u1 = 0, + /// Port input data + IDR4: u1 = 0, + /// Port input data + IDR5: u1 = 0, + /// Port input data + IDR6: u1 = 0, + /// Port input data + IDR7: u1 = 0, + /// Port input data + IDR8: u1 = 0, + /// Port input data + IDR9: u1 = 0, + /// Port input data + IDR10: u1 = 0, + /// Port input data + IDR11: u1 = 0, + /// Port input data + IDR12: u1 = 0, + /// Port input data + IDR13: u1 = 0, + /// Port input data + IDR14: u1 = 0, + /// Port input data + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1174,24 +1386,41 @@ pub const GPIOB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Port output data register (GPIOn_ODR) + + /// Port output data register (GPIOn_ODR) pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data - ODR1: u1, // bit offset: 1 desc: Port output data - ODR2: u1, // bit offset: 2 desc: Port output data - ODR3: u1, // bit offset: 3 desc: Port output data - ODR4: u1, // bit offset: 4 desc: Port output data - ODR5: u1, // bit offset: 5 desc: Port output data - ODR6: u1, // bit offset: 6 desc: Port output data - ODR7: u1, // bit offset: 7 desc: Port output data - ODR8: u1, // bit offset: 8 desc: Port output data - ODR9: u1, // bit offset: 9 desc: Port output data - ODR10: u1, // bit offset: 10 desc: Port output data - ODR11: u1, // bit offset: 11 desc: Port output data - ODR12: u1, // bit offset: 12 desc: Port output data - ODR13: u1, // bit offset: 13 desc: Port output data - ODR14: u1, // bit offset: 14 desc: Port output data - ODR15: u1, // bit offset: 15 desc: Port output data + /// Port output data + ODR0: u1 = 0, + /// Port output data + ODR1: u1 = 0, + /// Port output data + ODR2: u1 = 0, + /// Port output data + ODR3: u1 = 0, + /// Port output data + ODR4: u1 = 0, + /// Port output data + ODR5: u1 = 0, + /// Port output data + ODR6: u1 = 0, + /// Port output data + ODR7: u1 = 0, + /// Port output data + ODR8: u1 = 0, + /// Port output data + ODR9: u1 = 0, + /// Port output data + ODR10: u1 = 0, + /// Port output data + ODR11: u1 = 0, + /// Port output data + ODR12: u1 = 0, + /// Port output data + ODR13: u1 = 0, + /// Port output data + ODR14: u1 = 0, + /// Port output data + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1209,59 +1438,109 @@ pub const GPIOB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Port bit set/reset register (GPIOn_BSRR) + + /// Port bit set/reset register (GPIOn_BSRR) pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Set bit 0 - BS1: u1, // bit offset: 1 desc: Set bit 1 - BS2: u1, // bit offset: 2 desc: Set bit 1 - BS3: u1, // bit offset: 3 desc: Set bit 3 - BS4: u1, // bit offset: 4 desc: Set bit 4 - BS5: u1, // bit offset: 5 desc: Set bit 5 - BS6: u1, // bit offset: 6 desc: Set bit 6 - BS7: u1, // bit offset: 7 desc: Set bit 7 - BS8: u1, // bit offset: 8 desc: Set bit 8 - BS9: u1, // bit offset: 9 desc: Set bit 9 - BS10: u1, // bit offset: 10 desc: Set bit 10 - BS11: u1, // bit offset: 11 desc: Set bit 11 - BS12: u1, // bit offset: 12 desc: Set bit 12 - BS13: u1, // bit offset: 13 desc: Set bit 13 - BS14: u1, // bit offset: 14 desc: Set bit 14 - BS15: u1, // bit offset: 15 desc: Set bit 15 - BR0: u1, // bit offset: 16 desc: Reset bit 0 - BR1: u1, // bit offset: 17 desc: Reset bit 1 - BR2: u1, // bit offset: 18 desc: Reset bit 2 - BR3: u1, // bit offset: 19 desc: Reset bit 3 - BR4: u1, // bit offset: 20 desc: Reset bit 4 - BR5: u1, // bit offset: 21 desc: Reset bit 5 - BR6: u1, // bit offset: 22 desc: Reset bit 6 - BR7: u1, // bit offset: 23 desc: Reset bit 7 - BR8: u1, // bit offset: 24 desc: Reset bit 8 - BR9: u1, // bit offset: 25 desc: Reset bit 9 - BR10: u1, // bit offset: 26 desc: Reset bit 10 - BR11: u1, // bit offset: 27 desc: Reset bit 11 - BR12: u1, // bit offset: 28 desc: Reset bit 12 - BR13: u1, // bit offset: 29 desc: Reset bit 13 - BR14: u1, // bit offset: 30 desc: Reset bit 14 - BR15: u1, // bit offset: 31 desc: Reset bit 15 - }); - // byte offset: 20 Port bit reset register (GPIOn_BRR) + /// Set bit 0 + BS0: u1 = 0, + /// Set bit 1 + BS1: u1 = 0, + /// Set bit 1 + BS2: u1 = 0, + /// Set bit 3 + BS3: u1 = 0, + /// Set bit 4 + BS4: u1 = 0, + /// Set bit 5 + BS5: u1 = 0, + /// Set bit 6 + BS6: u1 = 0, + /// Set bit 7 + BS7: u1 = 0, + /// Set bit 8 + BS8: u1 = 0, + /// Set bit 9 + BS9: u1 = 0, + /// Set bit 10 + BS10: u1 = 0, + /// Set bit 11 + BS11: u1 = 0, + /// Set bit 12 + BS12: u1 = 0, + /// Set bit 13 + BS13: u1 = 0, + /// Set bit 14 + BS14: u1 = 0, + /// Set bit 15 + BS15: u1 = 0, + /// Reset bit 0 + BR0: u1 = 0, + /// Reset bit 1 + BR1: u1 = 0, + /// Reset bit 2 + BR2: u1 = 0, + /// Reset bit 3 + BR3: u1 = 0, + /// Reset bit 4 + BR4: u1 = 0, + /// Reset bit 5 + BR5: u1 = 0, + /// Reset bit 6 + BR6: u1 = 0, + /// Reset bit 7 + BR7: u1 = 0, + /// Reset bit 8 + BR8: u1 = 0, + /// Reset bit 9 + BR9: u1 = 0, + /// Reset bit 10 + BR10: u1 = 0, + /// Reset bit 11 + BR11: u1 = 0, + /// Reset bit 12 + BR12: u1 = 0, + /// Reset bit 13 + BR13: u1 = 0, + /// Reset bit 14 + BR14: u1 = 0, + /// Reset bit 15 + BR15: u1 = 0, + }); + + /// Port bit reset register (GPIOn_BRR) pub const BRR = mmio(Address + 0x00000014, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Reset bit 0 - BR1: u1, // bit offset: 1 desc: Reset bit 1 - BR2: u1, // bit offset: 2 desc: Reset bit 1 - BR3: u1, // bit offset: 3 desc: Reset bit 3 - BR4: u1, // bit offset: 4 desc: Reset bit 4 - BR5: u1, // bit offset: 5 desc: Reset bit 5 - BR6: u1, // bit offset: 6 desc: Reset bit 6 - BR7: u1, // bit offset: 7 desc: Reset bit 7 - BR8: u1, // bit offset: 8 desc: Reset bit 8 - BR9: u1, // bit offset: 9 desc: Reset bit 9 - BR10: u1, // bit offset: 10 desc: Reset bit 10 - BR11: u1, // bit offset: 11 desc: Reset bit 11 - BR12: u1, // bit offset: 12 desc: Reset bit 12 - BR13: u1, // bit offset: 13 desc: Reset bit 13 - BR14: u1, // bit offset: 14 desc: Reset bit 14 - BR15: u1, // bit offset: 15 desc: Reset bit 15 + /// Reset bit 0 + BR0: u1 = 0, + /// Reset bit 1 + BR1: u1 = 0, + /// Reset bit 1 + BR2: u1 = 0, + /// Reset bit 3 + BR3: u1 = 0, + /// Reset bit 4 + BR4: u1 = 0, + /// Reset bit 5 + BR5: u1 = 0, + /// Reset bit 6 + BR6: u1 = 0, + /// Reset bit 7 + BR7: u1 = 0, + /// Reset bit 8 + BR8: u1 = 0, + /// Reset bit 9 + BR9: u1 = 0, + /// Reset bit 10 + BR10: u1 = 0, + /// Reset bit 11 + BR11: u1 = 0, + /// Reset bit 12 + BR12: u1 = 0, + /// Reset bit 13 + BR13: u1 = 0, + /// Reset bit 14 + BR14: u1 = 0, + /// Reset bit 15 + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1279,25 +1558,43 @@ pub const GPIOB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 Port configuration lock register + + /// Port configuration lock register pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port A Lock bit 0 - LCK1: u1, // bit offset: 1 desc: Port A Lock bit 1 - LCK2: u1, // bit offset: 2 desc: Port A Lock bit 2 - LCK3: u1, // bit offset: 3 desc: Port A Lock bit 3 - LCK4: u1, // bit offset: 4 desc: Port A Lock bit 4 - LCK5: u1, // bit offset: 5 desc: Port A Lock bit 5 - LCK6: u1, // bit offset: 6 desc: Port A Lock bit 6 - LCK7: u1, // bit offset: 7 desc: Port A Lock bit 7 - LCK8: u1, // bit offset: 8 desc: Port A Lock bit 8 - LCK9: u1, // bit offset: 9 desc: Port A Lock bit 9 - LCK10: u1, // bit offset: 10 desc: Port A Lock bit 10 - LCK11: u1, // bit offset: 11 desc: Port A Lock bit 11 - LCK12: u1, // bit offset: 12 desc: Port A Lock bit 12 - LCK13: u1, // bit offset: 13 desc: Port A Lock bit 13 - LCK14: u1, // bit offset: 14 desc: Port A Lock bit 14 - LCK15: u1, // bit offset: 15 desc: Port A Lock bit 15 - LCKK: u1, // bit offset: 16 desc: Lock key + /// Port A Lock bit 0 + LCK0: u1 = 0, + /// Port A Lock bit 1 + LCK1: u1 = 0, + /// Port A Lock bit 2 + LCK2: u1 = 0, + /// Port A Lock bit 3 + LCK3: u1 = 0, + /// Port A Lock bit 4 + LCK4: u1 = 0, + /// Port A Lock bit 5 + LCK5: u1 = 0, + /// Port A Lock bit 6 + LCK6: u1 = 0, + /// Port A Lock bit 7 + LCK7: u1 = 0, + /// Port A Lock bit 8 + LCK8: u1 = 0, + /// Port A Lock bit 9 + LCK9: u1 = 0, + /// Port A Lock bit 10 + LCK10: u1 = 0, + /// Port A Lock bit 11 + LCK11: u1 = 0, + /// Port A Lock bit 12 + LCK12: u1 = 0, + /// Port A Lock bit 13 + LCK13: u1 = 0, + /// Port A Lock bit 14 + LCK14: u1 = 0, + /// Port A Lock bit 15 + LCK15: u1 = 0, + /// Lock key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -1315,64 +1612,117 @@ pub const GPIOB = extern struct { padding1: u1 = 0, }); }; + +/// General purpose I/O pub const GPIOC = extern struct { pub const Address: u32 = 0x40011000; - // byte offset: 0 Port configuration register low (GPIOn_CRL) + + /// Port configuration register low (GPIOn_CRL) pub const CRL = mmio(Address + 0x00000000, 32, packed struct { - MODE0: u2, // bit offset: 0 desc: Port n.0 mode bits - CNF0: u2, // bit offset: 2 desc: Port n.0 configuration bits - MODE1: u2, // bit offset: 4 desc: Port n.1 mode bits - CNF1: u2, // bit offset: 6 desc: Port n.1 configuration bits - MODE2: u2, // bit offset: 8 desc: Port n.2 mode bits - CNF2: u2, // bit offset: 10 desc: Port n.2 configuration bits - MODE3: u2, // bit offset: 12 desc: Port n.3 mode bits - CNF3: u2, // bit offset: 14 desc: Port n.3 configuration bits - MODE4: u2, // bit offset: 16 desc: Port n.4 mode bits - CNF4: u2, // bit offset: 18 desc: Port n.4 configuration bits - MODE5: u2, // bit offset: 20 desc: Port n.5 mode bits - CNF5: u2, // bit offset: 22 desc: Port n.5 configuration bits - MODE6: u2, // bit offset: 24 desc: Port n.6 mode bits - CNF6: u2, // bit offset: 26 desc: Port n.6 configuration bits - MODE7: u2, // bit offset: 28 desc: Port n.7 mode bits - CNF7: u2, // bit offset: 30 desc: Port n.7 configuration bits - }); - // byte offset: 4 Port configuration register high (GPIOn_CRL) + /// Port n.0 mode bits + MODE0: u2 = 0, + /// Port n.0 configuration bits + CNF0: u2 = 0, + /// Port n.1 mode bits + MODE1: u2 = 0, + /// Port n.1 configuration bits + CNF1: u2 = 0, + /// Port n.2 mode bits + MODE2: u2 = 0, + /// Port n.2 configuration bits + CNF2: u2 = 0, + /// Port n.3 mode bits + MODE3: u2 = 0, + /// Port n.3 configuration bits + CNF3: u2 = 0, + /// Port n.4 mode bits + MODE4: u2 = 0, + /// Port n.4 configuration bits + CNF4: u2 = 0, + /// Port n.5 mode bits + MODE5: u2 = 0, + /// Port n.5 configuration bits + CNF5: u2 = 0, + /// Port n.6 mode bits + MODE6: u2 = 0, + /// Port n.6 configuration bits + CNF6: u2 = 0, + /// Port n.7 mode bits + MODE7: u2 = 0, + /// Port n.7 configuration bits + CNF7: u2 = 0, + }); + + /// Port configuration register high (GPIOn_CRL) pub const CRH = mmio(Address + 0x00000004, 32, packed struct { - MODE8: u2, // bit offset: 0 desc: Port n.8 mode bits - CNF8: u2, // bit offset: 2 desc: Port n.8 configuration bits - MODE9: u2, // bit offset: 4 desc: Port n.9 mode bits - CNF9: u2, // bit offset: 6 desc: Port n.9 configuration bits - MODE10: u2, // bit offset: 8 desc: Port n.10 mode bits - CNF10: u2, // bit offset: 10 desc: Port n.10 configuration bits - MODE11: u2, // bit offset: 12 desc: Port n.11 mode bits - CNF11: u2, // bit offset: 14 desc: Port n.11 configuration bits - MODE12: u2, // bit offset: 16 desc: Port n.12 mode bits - CNF12: u2, // bit offset: 18 desc: Port n.12 configuration bits - MODE13: u2, // bit offset: 20 desc: Port n.13 mode bits - CNF13: u2, // bit offset: 22 desc: Port n.13 configuration bits - MODE14: u2, // bit offset: 24 desc: Port n.14 mode bits - CNF14: u2, // bit offset: 26 desc: Port n.14 configuration bits - MODE15: u2, // bit offset: 28 desc: Port n.15 mode bits - CNF15: u2, // bit offset: 30 desc: Port n.15 configuration bits - }); - // byte offset: 8 Port input data register (GPIOn_IDR) + /// Port n.8 mode bits + MODE8: u2 = 0, + /// Port n.8 configuration bits + CNF8: u2 = 0, + /// Port n.9 mode bits + MODE9: u2 = 0, + /// Port n.9 configuration bits + CNF9: u2 = 0, + /// Port n.10 mode bits + MODE10: u2 = 0, + /// Port n.10 configuration bits + CNF10: u2 = 0, + /// Port n.11 mode bits + MODE11: u2 = 0, + /// Port n.11 configuration bits + CNF11: u2 = 0, + /// Port n.12 mode bits + MODE12: u2 = 0, + /// Port n.12 configuration bits + CNF12: u2 = 0, + /// Port n.13 mode bits + MODE13: u2 = 0, + /// Port n.13 configuration bits + CNF13: u2 = 0, + /// Port n.14 mode bits + MODE14: u2 = 0, + /// Port n.14 configuration bits + CNF14: u2 = 0, + /// Port n.15 mode bits + MODE15: u2 = 0, + /// Port n.15 configuration bits + CNF15: u2 = 0, + }); + + /// Port input data register (GPIOn_IDR) pub const IDR = mmio(Address + 0x00000008, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data - IDR1: u1, // bit offset: 1 desc: Port input data - IDR2: u1, // bit offset: 2 desc: Port input data - IDR3: u1, // bit offset: 3 desc: Port input data - IDR4: u1, // bit offset: 4 desc: Port input data - IDR5: u1, // bit offset: 5 desc: Port input data - IDR6: u1, // bit offset: 6 desc: Port input data - IDR7: u1, // bit offset: 7 desc: Port input data - IDR8: u1, // bit offset: 8 desc: Port input data - IDR9: u1, // bit offset: 9 desc: Port input data - IDR10: u1, // bit offset: 10 desc: Port input data - IDR11: u1, // bit offset: 11 desc: Port input data - IDR12: u1, // bit offset: 12 desc: Port input data - IDR13: u1, // bit offset: 13 desc: Port input data - IDR14: u1, // bit offset: 14 desc: Port input data - IDR15: u1, // bit offset: 15 desc: Port input data + /// Port input data + IDR0: u1 = 0, + /// Port input data + IDR1: u1 = 0, + /// Port input data + IDR2: u1 = 0, + /// Port input data + IDR3: u1 = 0, + /// Port input data + IDR4: u1 = 0, + /// Port input data + IDR5: u1 = 0, + /// Port input data + IDR6: u1 = 0, + /// Port input data + IDR7: u1 = 0, + /// Port input data + IDR8: u1 = 0, + /// Port input data + IDR9: u1 = 0, + /// Port input data + IDR10: u1 = 0, + /// Port input data + IDR11: u1 = 0, + /// Port input data + IDR12: u1 = 0, + /// Port input data + IDR13: u1 = 0, + /// Port input data + IDR14: u1 = 0, + /// Port input data + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1390,24 +1740,41 @@ pub const GPIOC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Port output data register (GPIOn_ODR) + + /// Port output data register (GPIOn_ODR) pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data - ODR1: u1, // bit offset: 1 desc: Port output data - ODR2: u1, // bit offset: 2 desc: Port output data - ODR3: u1, // bit offset: 3 desc: Port output data - ODR4: u1, // bit offset: 4 desc: Port output data - ODR5: u1, // bit offset: 5 desc: Port output data - ODR6: u1, // bit offset: 6 desc: Port output data - ODR7: u1, // bit offset: 7 desc: Port output data - ODR8: u1, // bit offset: 8 desc: Port output data - ODR9: u1, // bit offset: 9 desc: Port output data - ODR10: u1, // bit offset: 10 desc: Port output data - ODR11: u1, // bit offset: 11 desc: Port output data - ODR12: u1, // bit offset: 12 desc: Port output data - ODR13: u1, // bit offset: 13 desc: Port output data - ODR14: u1, // bit offset: 14 desc: Port output data - ODR15: u1, // bit offset: 15 desc: Port output data + /// Port output data + ODR0: u1 = 0, + /// Port output data + ODR1: u1 = 0, + /// Port output data + ODR2: u1 = 0, + /// Port output data + ODR3: u1 = 0, + /// Port output data + ODR4: u1 = 0, + /// Port output data + ODR5: u1 = 0, + /// Port output data + ODR6: u1 = 0, + /// Port output data + ODR7: u1 = 0, + /// Port output data + ODR8: u1 = 0, + /// Port output data + ODR9: u1 = 0, + /// Port output data + ODR10: u1 = 0, + /// Port output data + ODR11: u1 = 0, + /// Port output data + ODR12: u1 = 0, + /// Port output data + ODR13: u1 = 0, + /// Port output data + ODR14: u1 = 0, + /// Port output data + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1425,59 +1792,109 @@ pub const GPIOC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Port bit set/reset register (GPIOn_BSRR) + + /// Port bit set/reset register (GPIOn_BSRR) pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Set bit 0 - BS1: u1, // bit offset: 1 desc: Set bit 1 - BS2: u1, // bit offset: 2 desc: Set bit 1 - BS3: u1, // bit offset: 3 desc: Set bit 3 - BS4: u1, // bit offset: 4 desc: Set bit 4 - BS5: u1, // bit offset: 5 desc: Set bit 5 - BS6: u1, // bit offset: 6 desc: Set bit 6 - BS7: u1, // bit offset: 7 desc: Set bit 7 - BS8: u1, // bit offset: 8 desc: Set bit 8 - BS9: u1, // bit offset: 9 desc: Set bit 9 - BS10: u1, // bit offset: 10 desc: Set bit 10 - BS11: u1, // bit offset: 11 desc: Set bit 11 - BS12: u1, // bit offset: 12 desc: Set bit 12 - BS13: u1, // bit offset: 13 desc: Set bit 13 - BS14: u1, // bit offset: 14 desc: Set bit 14 - BS15: u1, // bit offset: 15 desc: Set bit 15 - BR0: u1, // bit offset: 16 desc: Reset bit 0 - BR1: u1, // bit offset: 17 desc: Reset bit 1 - BR2: u1, // bit offset: 18 desc: Reset bit 2 - BR3: u1, // bit offset: 19 desc: Reset bit 3 - BR4: u1, // bit offset: 20 desc: Reset bit 4 - BR5: u1, // bit offset: 21 desc: Reset bit 5 - BR6: u1, // bit offset: 22 desc: Reset bit 6 - BR7: u1, // bit offset: 23 desc: Reset bit 7 - BR8: u1, // bit offset: 24 desc: Reset bit 8 - BR9: u1, // bit offset: 25 desc: Reset bit 9 - BR10: u1, // bit offset: 26 desc: Reset bit 10 - BR11: u1, // bit offset: 27 desc: Reset bit 11 - BR12: u1, // bit offset: 28 desc: Reset bit 12 - BR13: u1, // bit offset: 29 desc: Reset bit 13 - BR14: u1, // bit offset: 30 desc: Reset bit 14 - BR15: u1, // bit offset: 31 desc: Reset bit 15 - }); - // byte offset: 20 Port bit reset register (GPIOn_BRR) + /// Set bit 0 + BS0: u1 = 0, + /// Set bit 1 + BS1: u1 = 0, + /// Set bit 1 + BS2: u1 = 0, + /// Set bit 3 + BS3: u1 = 0, + /// Set bit 4 + BS4: u1 = 0, + /// Set bit 5 + BS5: u1 = 0, + /// Set bit 6 + BS6: u1 = 0, + /// Set bit 7 + BS7: u1 = 0, + /// Set bit 8 + BS8: u1 = 0, + /// Set bit 9 + BS9: u1 = 0, + /// Set bit 10 + BS10: u1 = 0, + /// Set bit 11 + BS11: u1 = 0, + /// Set bit 12 + BS12: u1 = 0, + /// Set bit 13 + BS13: u1 = 0, + /// Set bit 14 + BS14: u1 = 0, + /// Set bit 15 + BS15: u1 = 0, + /// Reset bit 0 + BR0: u1 = 0, + /// Reset bit 1 + BR1: u1 = 0, + /// Reset bit 2 + BR2: u1 = 0, + /// Reset bit 3 + BR3: u1 = 0, + /// Reset bit 4 + BR4: u1 = 0, + /// Reset bit 5 + BR5: u1 = 0, + /// Reset bit 6 + BR6: u1 = 0, + /// Reset bit 7 + BR7: u1 = 0, + /// Reset bit 8 + BR8: u1 = 0, + /// Reset bit 9 + BR9: u1 = 0, + /// Reset bit 10 + BR10: u1 = 0, + /// Reset bit 11 + BR11: u1 = 0, + /// Reset bit 12 + BR12: u1 = 0, + /// Reset bit 13 + BR13: u1 = 0, + /// Reset bit 14 + BR14: u1 = 0, + /// Reset bit 15 + BR15: u1 = 0, + }); + + /// Port bit reset register (GPIOn_BRR) pub const BRR = mmio(Address + 0x00000014, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Reset bit 0 - BR1: u1, // bit offset: 1 desc: Reset bit 1 - BR2: u1, // bit offset: 2 desc: Reset bit 1 - BR3: u1, // bit offset: 3 desc: Reset bit 3 - BR4: u1, // bit offset: 4 desc: Reset bit 4 - BR5: u1, // bit offset: 5 desc: Reset bit 5 - BR6: u1, // bit offset: 6 desc: Reset bit 6 - BR7: u1, // bit offset: 7 desc: Reset bit 7 - BR8: u1, // bit offset: 8 desc: Reset bit 8 - BR9: u1, // bit offset: 9 desc: Reset bit 9 - BR10: u1, // bit offset: 10 desc: Reset bit 10 - BR11: u1, // bit offset: 11 desc: Reset bit 11 - BR12: u1, // bit offset: 12 desc: Reset bit 12 - BR13: u1, // bit offset: 13 desc: Reset bit 13 - BR14: u1, // bit offset: 14 desc: Reset bit 14 - BR15: u1, // bit offset: 15 desc: Reset bit 15 + /// Reset bit 0 + BR0: u1 = 0, + /// Reset bit 1 + BR1: u1 = 0, + /// Reset bit 1 + BR2: u1 = 0, + /// Reset bit 3 + BR3: u1 = 0, + /// Reset bit 4 + BR4: u1 = 0, + /// Reset bit 5 + BR5: u1 = 0, + /// Reset bit 6 + BR6: u1 = 0, + /// Reset bit 7 + BR7: u1 = 0, + /// Reset bit 8 + BR8: u1 = 0, + /// Reset bit 9 + BR9: u1 = 0, + /// Reset bit 10 + BR10: u1 = 0, + /// Reset bit 11 + BR11: u1 = 0, + /// Reset bit 12 + BR12: u1 = 0, + /// Reset bit 13 + BR13: u1 = 0, + /// Reset bit 14 + BR14: u1 = 0, + /// Reset bit 15 + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1495,25 +1912,43 @@ pub const GPIOC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 Port configuration lock register + + /// Port configuration lock register pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port A Lock bit 0 - LCK1: u1, // bit offset: 1 desc: Port A Lock bit 1 - LCK2: u1, // bit offset: 2 desc: Port A Lock bit 2 - LCK3: u1, // bit offset: 3 desc: Port A Lock bit 3 - LCK4: u1, // bit offset: 4 desc: Port A Lock bit 4 - LCK5: u1, // bit offset: 5 desc: Port A Lock bit 5 - LCK6: u1, // bit offset: 6 desc: Port A Lock bit 6 - LCK7: u1, // bit offset: 7 desc: Port A Lock bit 7 - LCK8: u1, // bit offset: 8 desc: Port A Lock bit 8 - LCK9: u1, // bit offset: 9 desc: Port A Lock bit 9 - LCK10: u1, // bit offset: 10 desc: Port A Lock bit 10 - LCK11: u1, // bit offset: 11 desc: Port A Lock bit 11 - LCK12: u1, // bit offset: 12 desc: Port A Lock bit 12 - LCK13: u1, // bit offset: 13 desc: Port A Lock bit 13 - LCK14: u1, // bit offset: 14 desc: Port A Lock bit 14 - LCK15: u1, // bit offset: 15 desc: Port A Lock bit 15 - LCKK: u1, // bit offset: 16 desc: Lock key + /// Port A Lock bit 0 + LCK0: u1 = 0, + /// Port A Lock bit 1 + LCK1: u1 = 0, + /// Port A Lock bit 2 + LCK2: u1 = 0, + /// Port A Lock bit 3 + LCK3: u1 = 0, + /// Port A Lock bit 4 + LCK4: u1 = 0, + /// Port A Lock bit 5 + LCK5: u1 = 0, + /// Port A Lock bit 6 + LCK6: u1 = 0, + /// Port A Lock bit 7 + LCK7: u1 = 0, + /// Port A Lock bit 8 + LCK8: u1 = 0, + /// Port A Lock bit 9 + LCK9: u1 = 0, + /// Port A Lock bit 10 + LCK10: u1 = 0, + /// Port A Lock bit 11 + LCK11: u1 = 0, + /// Port A Lock bit 12 + LCK12: u1 = 0, + /// Port A Lock bit 13 + LCK13: u1 = 0, + /// Port A Lock bit 14 + LCK14: u1 = 0, + /// Port A Lock bit 15 + LCK15: u1 = 0, + /// Lock key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -1531,64 +1966,117 @@ pub const GPIOC = extern struct { padding1: u1 = 0, }); }; + +/// General purpose I/O pub const GPIOD = extern struct { pub const Address: u32 = 0x40011400; - // byte offset: 0 Port configuration register low (GPIOn_CRL) + + /// Port configuration register low (GPIOn_CRL) pub const CRL = mmio(Address + 0x00000000, 32, packed struct { - MODE0: u2, // bit offset: 0 desc: Port n.0 mode bits - CNF0: u2, // bit offset: 2 desc: Port n.0 configuration bits - MODE1: u2, // bit offset: 4 desc: Port n.1 mode bits - CNF1: u2, // bit offset: 6 desc: Port n.1 configuration bits - MODE2: u2, // bit offset: 8 desc: Port n.2 mode bits - CNF2: u2, // bit offset: 10 desc: Port n.2 configuration bits - MODE3: u2, // bit offset: 12 desc: Port n.3 mode bits - CNF3: u2, // bit offset: 14 desc: Port n.3 configuration bits - MODE4: u2, // bit offset: 16 desc: Port n.4 mode bits - CNF4: u2, // bit offset: 18 desc: Port n.4 configuration bits - MODE5: u2, // bit offset: 20 desc: Port n.5 mode bits - CNF5: u2, // bit offset: 22 desc: Port n.5 configuration bits - MODE6: u2, // bit offset: 24 desc: Port n.6 mode bits - CNF6: u2, // bit offset: 26 desc: Port n.6 configuration bits - MODE7: u2, // bit offset: 28 desc: Port n.7 mode bits - CNF7: u2, // bit offset: 30 desc: Port n.7 configuration bits - }); - // byte offset: 4 Port configuration register high (GPIOn_CRL) + /// Port n.0 mode bits + MODE0: u2 = 0, + /// Port n.0 configuration bits + CNF0: u2 = 0, + /// Port n.1 mode bits + MODE1: u2 = 0, + /// Port n.1 configuration bits + CNF1: u2 = 0, + /// Port n.2 mode bits + MODE2: u2 = 0, + /// Port n.2 configuration bits + CNF2: u2 = 0, + /// Port n.3 mode bits + MODE3: u2 = 0, + /// Port n.3 configuration bits + CNF3: u2 = 0, + /// Port n.4 mode bits + MODE4: u2 = 0, + /// Port n.4 configuration bits + CNF4: u2 = 0, + /// Port n.5 mode bits + MODE5: u2 = 0, + /// Port n.5 configuration bits + CNF5: u2 = 0, + /// Port n.6 mode bits + MODE6: u2 = 0, + /// Port n.6 configuration bits + CNF6: u2 = 0, + /// Port n.7 mode bits + MODE7: u2 = 0, + /// Port n.7 configuration bits + CNF7: u2 = 0, + }); + + /// Port configuration register high (GPIOn_CRL) pub const CRH = mmio(Address + 0x00000004, 32, packed struct { - MODE8: u2, // bit offset: 0 desc: Port n.8 mode bits - CNF8: u2, // bit offset: 2 desc: Port n.8 configuration bits - MODE9: u2, // bit offset: 4 desc: Port n.9 mode bits - CNF9: u2, // bit offset: 6 desc: Port n.9 configuration bits - MODE10: u2, // bit offset: 8 desc: Port n.10 mode bits - CNF10: u2, // bit offset: 10 desc: Port n.10 configuration bits - MODE11: u2, // bit offset: 12 desc: Port n.11 mode bits - CNF11: u2, // bit offset: 14 desc: Port n.11 configuration bits - MODE12: u2, // bit offset: 16 desc: Port n.12 mode bits - CNF12: u2, // bit offset: 18 desc: Port n.12 configuration bits - MODE13: u2, // bit offset: 20 desc: Port n.13 mode bits - CNF13: u2, // bit offset: 22 desc: Port n.13 configuration bits - MODE14: u2, // bit offset: 24 desc: Port n.14 mode bits - CNF14: u2, // bit offset: 26 desc: Port n.14 configuration bits - MODE15: u2, // bit offset: 28 desc: Port n.15 mode bits - CNF15: u2, // bit offset: 30 desc: Port n.15 configuration bits - }); - // byte offset: 8 Port input data register (GPIOn_IDR) + /// Port n.8 mode bits + MODE8: u2 = 0, + /// Port n.8 configuration bits + CNF8: u2 = 0, + /// Port n.9 mode bits + MODE9: u2 = 0, + /// Port n.9 configuration bits + CNF9: u2 = 0, + /// Port n.10 mode bits + MODE10: u2 = 0, + /// Port n.10 configuration bits + CNF10: u2 = 0, + /// Port n.11 mode bits + MODE11: u2 = 0, + /// Port n.11 configuration bits + CNF11: u2 = 0, + /// Port n.12 mode bits + MODE12: u2 = 0, + /// Port n.12 configuration bits + CNF12: u2 = 0, + /// Port n.13 mode bits + MODE13: u2 = 0, + /// Port n.13 configuration bits + CNF13: u2 = 0, + /// Port n.14 mode bits + MODE14: u2 = 0, + /// Port n.14 configuration bits + CNF14: u2 = 0, + /// Port n.15 mode bits + MODE15: u2 = 0, + /// Port n.15 configuration bits + CNF15: u2 = 0, + }); + + /// Port input data register (GPIOn_IDR) pub const IDR = mmio(Address + 0x00000008, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data - IDR1: u1, // bit offset: 1 desc: Port input data - IDR2: u1, // bit offset: 2 desc: Port input data - IDR3: u1, // bit offset: 3 desc: Port input data - IDR4: u1, // bit offset: 4 desc: Port input data - IDR5: u1, // bit offset: 5 desc: Port input data - IDR6: u1, // bit offset: 6 desc: Port input data - IDR7: u1, // bit offset: 7 desc: Port input data - IDR8: u1, // bit offset: 8 desc: Port input data - IDR9: u1, // bit offset: 9 desc: Port input data - IDR10: u1, // bit offset: 10 desc: Port input data - IDR11: u1, // bit offset: 11 desc: Port input data - IDR12: u1, // bit offset: 12 desc: Port input data - IDR13: u1, // bit offset: 13 desc: Port input data - IDR14: u1, // bit offset: 14 desc: Port input data - IDR15: u1, // bit offset: 15 desc: Port input data + /// Port input data + IDR0: u1 = 0, + /// Port input data + IDR1: u1 = 0, + /// Port input data + IDR2: u1 = 0, + /// Port input data + IDR3: u1 = 0, + /// Port input data + IDR4: u1 = 0, + /// Port input data + IDR5: u1 = 0, + /// Port input data + IDR6: u1 = 0, + /// Port input data + IDR7: u1 = 0, + /// Port input data + IDR8: u1 = 0, + /// Port input data + IDR9: u1 = 0, + /// Port input data + IDR10: u1 = 0, + /// Port input data + IDR11: u1 = 0, + /// Port input data + IDR12: u1 = 0, + /// Port input data + IDR13: u1 = 0, + /// Port input data + IDR14: u1 = 0, + /// Port input data + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1606,24 +2094,41 @@ pub const GPIOD = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Port output data register (GPIOn_ODR) + + /// Port output data register (GPIOn_ODR) pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data - ODR1: u1, // bit offset: 1 desc: Port output data - ODR2: u1, // bit offset: 2 desc: Port output data - ODR3: u1, // bit offset: 3 desc: Port output data - ODR4: u1, // bit offset: 4 desc: Port output data - ODR5: u1, // bit offset: 5 desc: Port output data - ODR6: u1, // bit offset: 6 desc: Port output data - ODR7: u1, // bit offset: 7 desc: Port output data - ODR8: u1, // bit offset: 8 desc: Port output data - ODR9: u1, // bit offset: 9 desc: Port output data - ODR10: u1, // bit offset: 10 desc: Port output data - ODR11: u1, // bit offset: 11 desc: Port output data - ODR12: u1, // bit offset: 12 desc: Port output data - ODR13: u1, // bit offset: 13 desc: Port output data - ODR14: u1, // bit offset: 14 desc: Port output data - ODR15: u1, // bit offset: 15 desc: Port output data + /// Port output data + ODR0: u1 = 0, + /// Port output data + ODR1: u1 = 0, + /// Port output data + ODR2: u1 = 0, + /// Port output data + ODR3: u1 = 0, + /// Port output data + ODR4: u1 = 0, + /// Port output data + ODR5: u1 = 0, + /// Port output data + ODR6: u1 = 0, + /// Port output data + ODR7: u1 = 0, + /// Port output data + ODR8: u1 = 0, + /// Port output data + ODR9: u1 = 0, + /// Port output data + ODR10: u1 = 0, + /// Port output data + ODR11: u1 = 0, + /// Port output data + ODR12: u1 = 0, + /// Port output data + ODR13: u1 = 0, + /// Port output data + ODR14: u1 = 0, + /// Port output data + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1641,59 +2146,109 @@ pub const GPIOD = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Port bit set/reset register (GPIOn_BSRR) + + /// Port bit set/reset register (GPIOn_BSRR) pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Set bit 0 - BS1: u1, // bit offset: 1 desc: Set bit 1 - BS2: u1, // bit offset: 2 desc: Set bit 1 - BS3: u1, // bit offset: 3 desc: Set bit 3 - BS4: u1, // bit offset: 4 desc: Set bit 4 - BS5: u1, // bit offset: 5 desc: Set bit 5 - BS6: u1, // bit offset: 6 desc: Set bit 6 - BS7: u1, // bit offset: 7 desc: Set bit 7 - BS8: u1, // bit offset: 8 desc: Set bit 8 - BS9: u1, // bit offset: 9 desc: Set bit 9 - BS10: u1, // bit offset: 10 desc: Set bit 10 - BS11: u1, // bit offset: 11 desc: Set bit 11 - BS12: u1, // bit offset: 12 desc: Set bit 12 - BS13: u1, // bit offset: 13 desc: Set bit 13 - BS14: u1, // bit offset: 14 desc: Set bit 14 - BS15: u1, // bit offset: 15 desc: Set bit 15 - BR0: u1, // bit offset: 16 desc: Reset bit 0 - BR1: u1, // bit offset: 17 desc: Reset bit 1 - BR2: u1, // bit offset: 18 desc: Reset bit 2 - BR3: u1, // bit offset: 19 desc: Reset bit 3 - BR4: u1, // bit offset: 20 desc: Reset bit 4 - BR5: u1, // bit offset: 21 desc: Reset bit 5 - BR6: u1, // bit offset: 22 desc: Reset bit 6 - BR7: u1, // bit offset: 23 desc: Reset bit 7 - BR8: u1, // bit offset: 24 desc: Reset bit 8 - BR9: u1, // bit offset: 25 desc: Reset bit 9 - BR10: u1, // bit offset: 26 desc: Reset bit 10 - BR11: u1, // bit offset: 27 desc: Reset bit 11 - BR12: u1, // bit offset: 28 desc: Reset bit 12 - BR13: u1, // bit offset: 29 desc: Reset bit 13 - BR14: u1, // bit offset: 30 desc: Reset bit 14 - BR15: u1, // bit offset: 31 desc: Reset bit 15 - }); - // byte offset: 20 Port bit reset register (GPIOn_BRR) + /// Set bit 0 + BS0: u1 = 0, + /// Set bit 1 + BS1: u1 = 0, + /// Set bit 1 + BS2: u1 = 0, + /// Set bit 3 + BS3: u1 = 0, + /// Set bit 4 + BS4: u1 = 0, + /// Set bit 5 + BS5: u1 = 0, + /// Set bit 6 + BS6: u1 = 0, + /// Set bit 7 + BS7: u1 = 0, + /// Set bit 8 + BS8: u1 = 0, + /// Set bit 9 + BS9: u1 = 0, + /// Set bit 10 + BS10: u1 = 0, + /// Set bit 11 + BS11: u1 = 0, + /// Set bit 12 + BS12: u1 = 0, + /// Set bit 13 + BS13: u1 = 0, + /// Set bit 14 + BS14: u1 = 0, + /// Set bit 15 + BS15: u1 = 0, + /// Reset bit 0 + BR0: u1 = 0, + /// Reset bit 1 + BR1: u1 = 0, + /// Reset bit 2 + BR2: u1 = 0, + /// Reset bit 3 + BR3: u1 = 0, + /// Reset bit 4 + BR4: u1 = 0, + /// Reset bit 5 + BR5: u1 = 0, + /// Reset bit 6 + BR6: u1 = 0, + /// Reset bit 7 + BR7: u1 = 0, + /// Reset bit 8 + BR8: u1 = 0, + /// Reset bit 9 + BR9: u1 = 0, + /// Reset bit 10 + BR10: u1 = 0, + /// Reset bit 11 + BR11: u1 = 0, + /// Reset bit 12 + BR12: u1 = 0, + /// Reset bit 13 + BR13: u1 = 0, + /// Reset bit 14 + BR14: u1 = 0, + /// Reset bit 15 + BR15: u1 = 0, + }); + + /// Port bit reset register (GPIOn_BRR) pub const BRR = mmio(Address + 0x00000014, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Reset bit 0 - BR1: u1, // bit offset: 1 desc: Reset bit 1 - BR2: u1, // bit offset: 2 desc: Reset bit 1 - BR3: u1, // bit offset: 3 desc: Reset bit 3 - BR4: u1, // bit offset: 4 desc: Reset bit 4 - BR5: u1, // bit offset: 5 desc: Reset bit 5 - BR6: u1, // bit offset: 6 desc: Reset bit 6 - BR7: u1, // bit offset: 7 desc: Reset bit 7 - BR8: u1, // bit offset: 8 desc: Reset bit 8 - BR9: u1, // bit offset: 9 desc: Reset bit 9 - BR10: u1, // bit offset: 10 desc: Reset bit 10 - BR11: u1, // bit offset: 11 desc: Reset bit 11 - BR12: u1, // bit offset: 12 desc: Reset bit 12 - BR13: u1, // bit offset: 13 desc: Reset bit 13 - BR14: u1, // bit offset: 14 desc: Reset bit 14 - BR15: u1, // bit offset: 15 desc: Reset bit 15 + /// Reset bit 0 + BR0: u1 = 0, + /// Reset bit 1 + BR1: u1 = 0, + /// Reset bit 1 + BR2: u1 = 0, + /// Reset bit 3 + BR3: u1 = 0, + /// Reset bit 4 + BR4: u1 = 0, + /// Reset bit 5 + BR5: u1 = 0, + /// Reset bit 6 + BR6: u1 = 0, + /// Reset bit 7 + BR7: u1 = 0, + /// Reset bit 8 + BR8: u1 = 0, + /// Reset bit 9 + BR9: u1 = 0, + /// Reset bit 10 + BR10: u1 = 0, + /// Reset bit 11 + BR11: u1 = 0, + /// Reset bit 12 + BR12: u1 = 0, + /// Reset bit 13 + BR13: u1 = 0, + /// Reset bit 14 + BR14: u1 = 0, + /// Reset bit 15 + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1711,25 +2266,43 @@ pub const GPIOD = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 Port configuration lock register + + /// Port configuration lock register pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port A Lock bit 0 - LCK1: u1, // bit offset: 1 desc: Port A Lock bit 1 - LCK2: u1, // bit offset: 2 desc: Port A Lock bit 2 - LCK3: u1, // bit offset: 3 desc: Port A Lock bit 3 - LCK4: u1, // bit offset: 4 desc: Port A Lock bit 4 - LCK5: u1, // bit offset: 5 desc: Port A Lock bit 5 - LCK6: u1, // bit offset: 6 desc: Port A Lock bit 6 - LCK7: u1, // bit offset: 7 desc: Port A Lock bit 7 - LCK8: u1, // bit offset: 8 desc: Port A Lock bit 8 - LCK9: u1, // bit offset: 9 desc: Port A Lock bit 9 - LCK10: u1, // bit offset: 10 desc: Port A Lock bit 10 - LCK11: u1, // bit offset: 11 desc: Port A Lock bit 11 - LCK12: u1, // bit offset: 12 desc: Port A Lock bit 12 - LCK13: u1, // bit offset: 13 desc: Port A Lock bit 13 - LCK14: u1, // bit offset: 14 desc: Port A Lock bit 14 - LCK15: u1, // bit offset: 15 desc: Port A Lock bit 15 - LCKK: u1, // bit offset: 16 desc: Lock key + /// Port A Lock bit 0 + LCK0: u1 = 0, + /// Port A Lock bit 1 + LCK1: u1 = 0, + /// Port A Lock bit 2 + LCK2: u1 = 0, + /// Port A Lock bit 3 + LCK3: u1 = 0, + /// Port A Lock bit 4 + LCK4: u1 = 0, + /// Port A Lock bit 5 + LCK5: u1 = 0, + /// Port A Lock bit 6 + LCK6: u1 = 0, + /// Port A Lock bit 7 + LCK7: u1 = 0, + /// Port A Lock bit 8 + LCK8: u1 = 0, + /// Port A Lock bit 9 + LCK9: u1 = 0, + /// Port A Lock bit 10 + LCK10: u1 = 0, + /// Port A Lock bit 11 + LCK11: u1 = 0, + /// Port A Lock bit 12 + LCK12: u1 = 0, + /// Port A Lock bit 13 + LCK13: u1 = 0, + /// Port A Lock bit 14 + LCK14: u1 = 0, + /// Port A Lock bit 15 + LCK15: u1 = 0, + /// Lock key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -1747,64 +2320,117 @@ pub const GPIOD = extern struct { padding1: u1 = 0, }); }; + +/// General purpose I/O pub const GPIOE = extern struct { pub const Address: u32 = 0x40011800; - // byte offset: 0 Port configuration register low (GPIOn_CRL) + + /// Port configuration register low (GPIOn_CRL) pub const CRL = mmio(Address + 0x00000000, 32, packed struct { - MODE0: u2, // bit offset: 0 desc: Port n.0 mode bits - CNF0: u2, // bit offset: 2 desc: Port n.0 configuration bits - MODE1: u2, // bit offset: 4 desc: Port n.1 mode bits - CNF1: u2, // bit offset: 6 desc: Port n.1 configuration bits - MODE2: u2, // bit offset: 8 desc: Port n.2 mode bits - CNF2: u2, // bit offset: 10 desc: Port n.2 configuration bits - MODE3: u2, // bit offset: 12 desc: Port n.3 mode bits - CNF3: u2, // bit offset: 14 desc: Port n.3 configuration bits - MODE4: u2, // bit offset: 16 desc: Port n.4 mode bits - CNF4: u2, // bit offset: 18 desc: Port n.4 configuration bits - MODE5: u2, // bit offset: 20 desc: Port n.5 mode bits - CNF5: u2, // bit offset: 22 desc: Port n.5 configuration bits - MODE6: u2, // bit offset: 24 desc: Port n.6 mode bits - CNF6: u2, // bit offset: 26 desc: Port n.6 configuration bits - MODE7: u2, // bit offset: 28 desc: Port n.7 mode bits - CNF7: u2, // bit offset: 30 desc: Port n.7 configuration bits - }); - // byte offset: 4 Port configuration register high (GPIOn_CRL) + /// Port n.0 mode bits + MODE0: u2 = 0, + /// Port n.0 configuration bits + CNF0: u2 = 0, + /// Port n.1 mode bits + MODE1: u2 = 0, + /// Port n.1 configuration bits + CNF1: u2 = 0, + /// Port n.2 mode bits + MODE2: u2 = 0, + /// Port n.2 configuration bits + CNF2: u2 = 0, + /// Port n.3 mode bits + MODE3: u2 = 0, + /// Port n.3 configuration bits + CNF3: u2 = 0, + /// Port n.4 mode bits + MODE4: u2 = 0, + /// Port n.4 configuration bits + CNF4: u2 = 0, + /// Port n.5 mode bits + MODE5: u2 = 0, + /// Port n.5 configuration bits + CNF5: u2 = 0, + /// Port n.6 mode bits + MODE6: u2 = 0, + /// Port n.6 configuration bits + CNF6: u2 = 0, + /// Port n.7 mode bits + MODE7: u2 = 0, + /// Port n.7 configuration bits + CNF7: u2 = 0, + }); + + /// Port configuration register high (GPIOn_CRL) pub const CRH = mmio(Address + 0x00000004, 32, packed struct { - MODE8: u2, // bit offset: 0 desc: Port n.8 mode bits - CNF8: u2, // bit offset: 2 desc: Port n.8 configuration bits - MODE9: u2, // bit offset: 4 desc: Port n.9 mode bits - CNF9: u2, // bit offset: 6 desc: Port n.9 configuration bits - MODE10: u2, // bit offset: 8 desc: Port n.10 mode bits - CNF10: u2, // bit offset: 10 desc: Port n.10 configuration bits - MODE11: u2, // bit offset: 12 desc: Port n.11 mode bits - CNF11: u2, // bit offset: 14 desc: Port n.11 configuration bits - MODE12: u2, // bit offset: 16 desc: Port n.12 mode bits - CNF12: u2, // bit offset: 18 desc: Port n.12 configuration bits - MODE13: u2, // bit offset: 20 desc: Port n.13 mode bits - CNF13: u2, // bit offset: 22 desc: Port n.13 configuration bits - MODE14: u2, // bit offset: 24 desc: Port n.14 mode bits - CNF14: u2, // bit offset: 26 desc: Port n.14 configuration bits - MODE15: u2, // bit offset: 28 desc: Port n.15 mode bits - CNF15: u2, // bit offset: 30 desc: Port n.15 configuration bits - }); - // byte offset: 8 Port input data register (GPIOn_IDR) + /// Port n.8 mode bits + MODE8: u2 = 0, + /// Port n.8 configuration bits + CNF8: u2 = 0, + /// Port n.9 mode bits + MODE9: u2 = 0, + /// Port n.9 configuration bits + CNF9: u2 = 0, + /// Port n.10 mode bits + MODE10: u2 = 0, + /// Port n.10 configuration bits + CNF10: u2 = 0, + /// Port n.11 mode bits + MODE11: u2 = 0, + /// Port n.11 configuration bits + CNF11: u2 = 0, + /// Port n.12 mode bits + MODE12: u2 = 0, + /// Port n.12 configuration bits + CNF12: u2 = 0, + /// Port n.13 mode bits + MODE13: u2 = 0, + /// Port n.13 configuration bits + CNF13: u2 = 0, + /// Port n.14 mode bits + MODE14: u2 = 0, + /// Port n.14 configuration bits + CNF14: u2 = 0, + /// Port n.15 mode bits + MODE15: u2 = 0, + /// Port n.15 configuration bits + CNF15: u2 = 0, + }); + + /// Port input data register (GPIOn_IDR) pub const IDR = mmio(Address + 0x00000008, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data - IDR1: u1, // bit offset: 1 desc: Port input data - IDR2: u1, // bit offset: 2 desc: Port input data - IDR3: u1, // bit offset: 3 desc: Port input data - IDR4: u1, // bit offset: 4 desc: Port input data - IDR5: u1, // bit offset: 5 desc: Port input data - IDR6: u1, // bit offset: 6 desc: Port input data - IDR7: u1, // bit offset: 7 desc: Port input data - IDR8: u1, // bit offset: 8 desc: Port input data - IDR9: u1, // bit offset: 9 desc: Port input data - IDR10: u1, // bit offset: 10 desc: Port input data - IDR11: u1, // bit offset: 11 desc: Port input data - IDR12: u1, // bit offset: 12 desc: Port input data - IDR13: u1, // bit offset: 13 desc: Port input data - IDR14: u1, // bit offset: 14 desc: Port input data - IDR15: u1, // bit offset: 15 desc: Port input data + /// Port input data + IDR0: u1 = 0, + /// Port input data + IDR1: u1 = 0, + /// Port input data + IDR2: u1 = 0, + /// Port input data + IDR3: u1 = 0, + /// Port input data + IDR4: u1 = 0, + /// Port input data + IDR5: u1 = 0, + /// Port input data + IDR6: u1 = 0, + /// Port input data + IDR7: u1 = 0, + /// Port input data + IDR8: u1 = 0, + /// Port input data + IDR9: u1 = 0, + /// Port input data + IDR10: u1 = 0, + /// Port input data + IDR11: u1 = 0, + /// Port input data + IDR12: u1 = 0, + /// Port input data + IDR13: u1 = 0, + /// Port input data + IDR14: u1 = 0, + /// Port input data + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1822,24 +2448,41 @@ pub const GPIOE = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Port output data register (GPIOn_ODR) + + /// Port output data register (GPIOn_ODR) pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data - ODR1: u1, // bit offset: 1 desc: Port output data - ODR2: u1, // bit offset: 2 desc: Port output data - ODR3: u1, // bit offset: 3 desc: Port output data - ODR4: u1, // bit offset: 4 desc: Port output data - ODR5: u1, // bit offset: 5 desc: Port output data - ODR6: u1, // bit offset: 6 desc: Port output data - ODR7: u1, // bit offset: 7 desc: Port output data - ODR8: u1, // bit offset: 8 desc: Port output data - ODR9: u1, // bit offset: 9 desc: Port output data - ODR10: u1, // bit offset: 10 desc: Port output data - ODR11: u1, // bit offset: 11 desc: Port output data - ODR12: u1, // bit offset: 12 desc: Port output data - ODR13: u1, // bit offset: 13 desc: Port output data - ODR14: u1, // bit offset: 14 desc: Port output data - ODR15: u1, // bit offset: 15 desc: Port output data + /// Port output data + ODR0: u1 = 0, + /// Port output data + ODR1: u1 = 0, + /// Port output data + ODR2: u1 = 0, + /// Port output data + ODR3: u1 = 0, + /// Port output data + ODR4: u1 = 0, + /// Port output data + ODR5: u1 = 0, + /// Port output data + ODR6: u1 = 0, + /// Port output data + ODR7: u1 = 0, + /// Port output data + ODR8: u1 = 0, + /// Port output data + ODR9: u1 = 0, + /// Port output data + ODR10: u1 = 0, + /// Port output data + ODR11: u1 = 0, + /// Port output data + ODR12: u1 = 0, + /// Port output data + ODR13: u1 = 0, + /// Port output data + ODR14: u1 = 0, + /// Port output data + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1857,59 +2500,109 @@ pub const GPIOE = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Port bit set/reset register (GPIOn_BSRR) + + /// Port bit set/reset register (GPIOn_BSRR) pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Set bit 0 - BS1: u1, // bit offset: 1 desc: Set bit 1 - BS2: u1, // bit offset: 2 desc: Set bit 1 - BS3: u1, // bit offset: 3 desc: Set bit 3 - BS4: u1, // bit offset: 4 desc: Set bit 4 - BS5: u1, // bit offset: 5 desc: Set bit 5 - BS6: u1, // bit offset: 6 desc: Set bit 6 - BS7: u1, // bit offset: 7 desc: Set bit 7 - BS8: u1, // bit offset: 8 desc: Set bit 8 - BS9: u1, // bit offset: 9 desc: Set bit 9 - BS10: u1, // bit offset: 10 desc: Set bit 10 - BS11: u1, // bit offset: 11 desc: Set bit 11 - BS12: u1, // bit offset: 12 desc: Set bit 12 - BS13: u1, // bit offset: 13 desc: Set bit 13 - BS14: u1, // bit offset: 14 desc: Set bit 14 - BS15: u1, // bit offset: 15 desc: Set bit 15 - BR0: u1, // bit offset: 16 desc: Reset bit 0 - BR1: u1, // bit offset: 17 desc: Reset bit 1 - BR2: u1, // bit offset: 18 desc: Reset bit 2 - BR3: u1, // bit offset: 19 desc: Reset bit 3 - BR4: u1, // bit offset: 20 desc: Reset bit 4 - BR5: u1, // bit offset: 21 desc: Reset bit 5 - BR6: u1, // bit offset: 22 desc: Reset bit 6 - BR7: u1, // bit offset: 23 desc: Reset bit 7 - BR8: u1, // bit offset: 24 desc: Reset bit 8 - BR9: u1, // bit offset: 25 desc: Reset bit 9 - BR10: u1, // bit offset: 26 desc: Reset bit 10 - BR11: u1, // bit offset: 27 desc: Reset bit 11 - BR12: u1, // bit offset: 28 desc: Reset bit 12 - BR13: u1, // bit offset: 29 desc: Reset bit 13 - BR14: u1, // bit offset: 30 desc: Reset bit 14 - BR15: u1, // bit offset: 31 desc: Reset bit 15 - }); - // byte offset: 20 Port bit reset register (GPIOn_BRR) + /// Set bit 0 + BS0: u1 = 0, + /// Set bit 1 + BS1: u1 = 0, + /// Set bit 1 + BS2: u1 = 0, + /// Set bit 3 + BS3: u1 = 0, + /// Set bit 4 + BS4: u1 = 0, + /// Set bit 5 + BS5: u1 = 0, + /// Set bit 6 + BS6: u1 = 0, + /// Set bit 7 + BS7: u1 = 0, + /// Set bit 8 + BS8: u1 = 0, + /// Set bit 9 + BS9: u1 = 0, + /// Set bit 10 + BS10: u1 = 0, + /// Set bit 11 + BS11: u1 = 0, + /// Set bit 12 + BS12: u1 = 0, + /// Set bit 13 + BS13: u1 = 0, + /// Set bit 14 + BS14: u1 = 0, + /// Set bit 15 + BS15: u1 = 0, + /// Reset bit 0 + BR0: u1 = 0, + /// Reset bit 1 + BR1: u1 = 0, + /// Reset bit 2 + BR2: u1 = 0, + /// Reset bit 3 + BR3: u1 = 0, + /// Reset bit 4 + BR4: u1 = 0, + /// Reset bit 5 + BR5: u1 = 0, + /// Reset bit 6 + BR6: u1 = 0, + /// Reset bit 7 + BR7: u1 = 0, + /// Reset bit 8 + BR8: u1 = 0, + /// Reset bit 9 + BR9: u1 = 0, + /// Reset bit 10 + BR10: u1 = 0, + /// Reset bit 11 + BR11: u1 = 0, + /// Reset bit 12 + BR12: u1 = 0, + /// Reset bit 13 + BR13: u1 = 0, + /// Reset bit 14 + BR14: u1 = 0, + /// Reset bit 15 + BR15: u1 = 0, + }); + + /// Port bit reset register (GPIOn_BRR) pub const BRR = mmio(Address + 0x00000014, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Reset bit 0 - BR1: u1, // bit offset: 1 desc: Reset bit 1 - BR2: u1, // bit offset: 2 desc: Reset bit 1 - BR3: u1, // bit offset: 3 desc: Reset bit 3 - BR4: u1, // bit offset: 4 desc: Reset bit 4 - BR5: u1, // bit offset: 5 desc: Reset bit 5 - BR6: u1, // bit offset: 6 desc: Reset bit 6 - BR7: u1, // bit offset: 7 desc: Reset bit 7 - BR8: u1, // bit offset: 8 desc: Reset bit 8 - BR9: u1, // bit offset: 9 desc: Reset bit 9 - BR10: u1, // bit offset: 10 desc: Reset bit 10 - BR11: u1, // bit offset: 11 desc: Reset bit 11 - BR12: u1, // bit offset: 12 desc: Reset bit 12 - BR13: u1, // bit offset: 13 desc: Reset bit 13 - BR14: u1, // bit offset: 14 desc: Reset bit 14 - BR15: u1, // bit offset: 15 desc: Reset bit 15 + /// Reset bit 0 + BR0: u1 = 0, + /// Reset bit 1 + BR1: u1 = 0, + /// Reset bit 1 + BR2: u1 = 0, + /// Reset bit 3 + BR3: u1 = 0, + /// Reset bit 4 + BR4: u1 = 0, + /// Reset bit 5 + BR5: u1 = 0, + /// Reset bit 6 + BR6: u1 = 0, + /// Reset bit 7 + BR7: u1 = 0, + /// Reset bit 8 + BR8: u1 = 0, + /// Reset bit 9 + BR9: u1 = 0, + /// Reset bit 10 + BR10: u1 = 0, + /// Reset bit 11 + BR11: u1 = 0, + /// Reset bit 12 + BR12: u1 = 0, + /// Reset bit 13 + BR13: u1 = 0, + /// Reset bit 14 + BR14: u1 = 0, + /// Reset bit 15 + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1927,25 +2620,43 @@ pub const GPIOE = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 Port configuration lock register + + /// Port configuration lock register pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port A Lock bit 0 - LCK1: u1, // bit offset: 1 desc: Port A Lock bit 1 - LCK2: u1, // bit offset: 2 desc: Port A Lock bit 2 - LCK3: u1, // bit offset: 3 desc: Port A Lock bit 3 - LCK4: u1, // bit offset: 4 desc: Port A Lock bit 4 - LCK5: u1, // bit offset: 5 desc: Port A Lock bit 5 - LCK6: u1, // bit offset: 6 desc: Port A Lock bit 6 - LCK7: u1, // bit offset: 7 desc: Port A Lock bit 7 - LCK8: u1, // bit offset: 8 desc: Port A Lock bit 8 - LCK9: u1, // bit offset: 9 desc: Port A Lock bit 9 - LCK10: u1, // bit offset: 10 desc: Port A Lock bit 10 - LCK11: u1, // bit offset: 11 desc: Port A Lock bit 11 - LCK12: u1, // bit offset: 12 desc: Port A Lock bit 12 - LCK13: u1, // bit offset: 13 desc: Port A Lock bit 13 - LCK14: u1, // bit offset: 14 desc: Port A Lock bit 14 - LCK15: u1, // bit offset: 15 desc: Port A Lock bit 15 - LCKK: u1, // bit offset: 16 desc: Lock key + /// Port A Lock bit 0 + LCK0: u1 = 0, + /// Port A Lock bit 1 + LCK1: u1 = 0, + /// Port A Lock bit 2 + LCK2: u1 = 0, + /// Port A Lock bit 3 + LCK3: u1 = 0, + /// Port A Lock bit 4 + LCK4: u1 = 0, + /// Port A Lock bit 5 + LCK5: u1 = 0, + /// Port A Lock bit 6 + LCK6: u1 = 0, + /// Port A Lock bit 7 + LCK7: u1 = 0, + /// Port A Lock bit 8 + LCK8: u1 = 0, + /// Port A Lock bit 9 + LCK9: u1 = 0, + /// Port A Lock bit 10 + LCK10: u1 = 0, + /// Port A Lock bit 11 + LCK11: u1 = 0, + /// Port A Lock bit 12 + LCK12: u1 = 0, + /// Port A Lock bit 13 + LCK13: u1 = 0, + /// Port A Lock bit 14 + LCK14: u1 = 0, + /// Port A Lock bit 15 + LCK15: u1 = 0, + /// Lock key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -1963,64 +2674,117 @@ pub const GPIOE = extern struct { padding1: u1 = 0, }); }; + +/// General purpose I/O pub const GPIOF = extern struct { pub const Address: u32 = 0x40011c00; - // byte offset: 0 Port configuration register low (GPIOn_CRL) + + /// Port configuration register low (GPIOn_CRL) pub const CRL = mmio(Address + 0x00000000, 32, packed struct { - MODE0: u2, // bit offset: 0 desc: Port n.0 mode bits - CNF0: u2, // bit offset: 2 desc: Port n.0 configuration bits - MODE1: u2, // bit offset: 4 desc: Port n.1 mode bits - CNF1: u2, // bit offset: 6 desc: Port n.1 configuration bits - MODE2: u2, // bit offset: 8 desc: Port n.2 mode bits - CNF2: u2, // bit offset: 10 desc: Port n.2 configuration bits - MODE3: u2, // bit offset: 12 desc: Port n.3 mode bits - CNF3: u2, // bit offset: 14 desc: Port n.3 configuration bits - MODE4: u2, // bit offset: 16 desc: Port n.4 mode bits - CNF4: u2, // bit offset: 18 desc: Port n.4 configuration bits - MODE5: u2, // bit offset: 20 desc: Port n.5 mode bits - CNF5: u2, // bit offset: 22 desc: Port n.5 configuration bits - MODE6: u2, // bit offset: 24 desc: Port n.6 mode bits - CNF6: u2, // bit offset: 26 desc: Port n.6 configuration bits - MODE7: u2, // bit offset: 28 desc: Port n.7 mode bits - CNF7: u2, // bit offset: 30 desc: Port n.7 configuration bits - }); - // byte offset: 4 Port configuration register high (GPIOn_CRL) + /// Port n.0 mode bits + MODE0: u2 = 0, + /// Port n.0 configuration bits + CNF0: u2 = 0, + /// Port n.1 mode bits + MODE1: u2 = 0, + /// Port n.1 configuration bits + CNF1: u2 = 0, + /// Port n.2 mode bits + MODE2: u2 = 0, + /// Port n.2 configuration bits + CNF2: u2 = 0, + /// Port n.3 mode bits + MODE3: u2 = 0, + /// Port n.3 configuration bits + CNF3: u2 = 0, + /// Port n.4 mode bits + MODE4: u2 = 0, + /// Port n.4 configuration bits + CNF4: u2 = 0, + /// Port n.5 mode bits + MODE5: u2 = 0, + /// Port n.5 configuration bits + CNF5: u2 = 0, + /// Port n.6 mode bits + MODE6: u2 = 0, + /// Port n.6 configuration bits + CNF6: u2 = 0, + /// Port n.7 mode bits + MODE7: u2 = 0, + /// Port n.7 configuration bits + CNF7: u2 = 0, + }); + + /// Port configuration register high (GPIOn_CRL) pub const CRH = mmio(Address + 0x00000004, 32, packed struct { - MODE8: u2, // bit offset: 0 desc: Port n.8 mode bits - CNF8: u2, // bit offset: 2 desc: Port n.8 configuration bits - MODE9: u2, // bit offset: 4 desc: Port n.9 mode bits - CNF9: u2, // bit offset: 6 desc: Port n.9 configuration bits - MODE10: u2, // bit offset: 8 desc: Port n.10 mode bits - CNF10: u2, // bit offset: 10 desc: Port n.10 configuration bits - MODE11: u2, // bit offset: 12 desc: Port n.11 mode bits - CNF11: u2, // bit offset: 14 desc: Port n.11 configuration bits - MODE12: u2, // bit offset: 16 desc: Port n.12 mode bits - CNF12: u2, // bit offset: 18 desc: Port n.12 configuration bits - MODE13: u2, // bit offset: 20 desc: Port n.13 mode bits - CNF13: u2, // bit offset: 22 desc: Port n.13 configuration bits - MODE14: u2, // bit offset: 24 desc: Port n.14 mode bits - CNF14: u2, // bit offset: 26 desc: Port n.14 configuration bits - MODE15: u2, // bit offset: 28 desc: Port n.15 mode bits - CNF15: u2, // bit offset: 30 desc: Port n.15 configuration bits - }); - // byte offset: 8 Port input data register (GPIOn_IDR) + /// Port n.8 mode bits + MODE8: u2 = 0, + /// Port n.8 configuration bits + CNF8: u2 = 0, + /// Port n.9 mode bits + MODE9: u2 = 0, + /// Port n.9 configuration bits + CNF9: u2 = 0, + /// Port n.10 mode bits + MODE10: u2 = 0, + /// Port n.10 configuration bits + CNF10: u2 = 0, + /// Port n.11 mode bits + MODE11: u2 = 0, + /// Port n.11 configuration bits + CNF11: u2 = 0, + /// Port n.12 mode bits + MODE12: u2 = 0, + /// Port n.12 configuration bits + CNF12: u2 = 0, + /// Port n.13 mode bits + MODE13: u2 = 0, + /// Port n.13 configuration bits + CNF13: u2 = 0, + /// Port n.14 mode bits + MODE14: u2 = 0, + /// Port n.14 configuration bits + CNF14: u2 = 0, + /// Port n.15 mode bits + MODE15: u2 = 0, + /// Port n.15 configuration bits + CNF15: u2 = 0, + }); + + /// Port input data register (GPIOn_IDR) pub const IDR = mmio(Address + 0x00000008, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data - IDR1: u1, // bit offset: 1 desc: Port input data - IDR2: u1, // bit offset: 2 desc: Port input data - IDR3: u1, // bit offset: 3 desc: Port input data - IDR4: u1, // bit offset: 4 desc: Port input data - IDR5: u1, // bit offset: 5 desc: Port input data - IDR6: u1, // bit offset: 6 desc: Port input data - IDR7: u1, // bit offset: 7 desc: Port input data - IDR8: u1, // bit offset: 8 desc: Port input data - IDR9: u1, // bit offset: 9 desc: Port input data - IDR10: u1, // bit offset: 10 desc: Port input data - IDR11: u1, // bit offset: 11 desc: Port input data - IDR12: u1, // bit offset: 12 desc: Port input data - IDR13: u1, // bit offset: 13 desc: Port input data - IDR14: u1, // bit offset: 14 desc: Port input data - IDR15: u1, // bit offset: 15 desc: Port input data + /// Port input data + IDR0: u1 = 0, + /// Port input data + IDR1: u1 = 0, + /// Port input data + IDR2: u1 = 0, + /// Port input data + IDR3: u1 = 0, + /// Port input data + IDR4: u1 = 0, + /// Port input data + IDR5: u1 = 0, + /// Port input data + IDR6: u1 = 0, + /// Port input data + IDR7: u1 = 0, + /// Port input data + IDR8: u1 = 0, + /// Port input data + IDR9: u1 = 0, + /// Port input data + IDR10: u1 = 0, + /// Port input data + IDR11: u1 = 0, + /// Port input data + IDR12: u1 = 0, + /// Port input data + IDR13: u1 = 0, + /// Port input data + IDR14: u1 = 0, + /// Port input data + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2038,24 +2802,41 @@ pub const GPIOF = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Port output data register (GPIOn_ODR) + + /// Port output data register (GPIOn_ODR) pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data - ODR1: u1, // bit offset: 1 desc: Port output data - ODR2: u1, // bit offset: 2 desc: Port output data - ODR3: u1, // bit offset: 3 desc: Port output data - ODR4: u1, // bit offset: 4 desc: Port output data - ODR5: u1, // bit offset: 5 desc: Port output data - ODR6: u1, // bit offset: 6 desc: Port output data - ODR7: u1, // bit offset: 7 desc: Port output data - ODR8: u1, // bit offset: 8 desc: Port output data - ODR9: u1, // bit offset: 9 desc: Port output data - ODR10: u1, // bit offset: 10 desc: Port output data - ODR11: u1, // bit offset: 11 desc: Port output data - ODR12: u1, // bit offset: 12 desc: Port output data - ODR13: u1, // bit offset: 13 desc: Port output data - ODR14: u1, // bit offset: 14 desc: Port output data - ODR15: u1, // bit offset: 15 desc: Port output data + /// Port output data + ODR0: u1 = 0, + /// Port output data + ODR1: u1 = 0, + /// Port output data + ODR2: u1 = 0, + /// Port output data + ODR3: u1 = 0, + /// Port output data + ODR4: u1 = 0, + /// Port output data + ODR5: u1 = 0, + /// Port output data + ODR6: u1 = 0, + /// Port output data + ODR7: u1 = 0, + /// Port output data + ODR8: u1 = 0, + /// Port output data + ODR9: u1 = 0, + /// Port output data + ODR10: u1 = 0, + /// Port output data + ODR11: u1 = 0, + /// Port output data + ODR12: u1 = 0, + /// Port output data + ODR13: u1 = 0, + /// Port output data + ODR14: u1 = 0, + /// Port output data + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2073,59 +2854,109 @@ pub const GPIOF = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Port bit set/reset register (GPIOn_BSRR) + + /// Port bit set/reset register (GPIOn_BSRR) pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Set bit 0 - BS1: u1, // bit offset: 1 desc: Set bit 1 - BS2: u1, // bit offset: 2 desc: Set bit 1 - BS3: u1, // bit offset: 3 desc: Set bit 3 - BS4: u1, // bit offset: 4 desc: Set bit 4 - BS5: u1, // bit offset: 5 desc: Set bit 5 - BS6: u1, // bit offset: 6 desc: Set bit 6 - BS7: u1, // bit offset: 7 desc: Set bit 7 - BS8: u1, // bit offset: 8 desc: Set bit 8 - BS9: u1, // bit offset: 9 desc: Set bit 9 - BS10: u1, // bit offset: 10 desc: Set bit 10 - BS11: u1, // bit offset: 11 desc: Set bit 11 - BS12: u1, // bit offset: 12 desc: Set bit 12 - BS13: u1, // bit offset: 13 desc: Set bit 13 - BS14: u1, // bit offset: 14 desc: Set bit 14 - BS15: u1, // bit offset: 15 desc: Set bit 15 - BR0: u1, // bit offset: 16 desc: Reset bit 0 - BR1: u1, // bit offset: 17 desc: Reset bit 1 - BR2: u1, // bit offset: 18 desc: Reset bit 2 - BR3: u1, // bit offset: 19 desc: Reset bit 3 - BR4: u1, // bit offset: 20 desc: Reset bit 4 - BR5: u1, // bit offset: 21 desc: Reset bit 5 - BR6: u1, // bit offset: 22 desc: Reset bit 6 - BR7: u1, // bit offset: 23 desc: Reset bit 7 - BR8: u1, // bit offset: 24 desc: Reset bit 8 - BR9: u1, // bit offset: 25 desc: Reset bit 9 - BR10: u1, // bit offset: 26 desc: Reset bit 10 - BR11: u1, // bit offset: 27 desc: Reset bit 11 - BR12: u1, // bit offset: 28 desc: Reset bit 12 - BR13: u1, // bit offset: 29 desc: Reset bit 13 - BR14: u1, // bit offset: 30 desc: Reset bit 14 - BR15: u1, // bit offset: 31 desc: Reset bit 15 - }); - // byte offset: 20 Port bit reset register (GPIOn_BRR) + /// Set bit 0 + BS0: u1 = 0, + /// Set bit 1 + BS1: u1 = 0, + /// Set bit 1 + BS2: u1 = 0, + /// Set bit 3 + BS3: u1 = 0, + /// Set bit 4 + BS4: u1 = 0, + /// Set bit 5 + BS5: u1 = 0, + /// Set bit 6 + BS6: u1 = 0, + /// Set bit 7 + BS7: u1 = 0, + /// Set bit 8 + BS8: u1 = 0, + /// Set bit 9 + BS9: u1 = 0, + /// Set bit 10 + BS10: u1 = 0, + /// Set bit 11 + BS11: u1 = 0, + /// Set bit 12 + BS12: u1 = 0, + /// Set bit 13 + BS13: u1 = 0, + /// Set bit 14 + BS14: u1 = 0, + /// Set bit 15 + BS15: u1 = 0, + /// Reset bit 0 + BR0: u1 = 0, + /// Reset bit 1 + BR1: u1 = 0, + /// Reset bit 2 + BR2: u1 = 0, + /// Reset bit 3 + BR3: u1 = 0, + /// Reset bit 4 + BR4: u1 = 0, + /// Reset bit 5 + BR5: u1 = 0, + /// Reset bit 6 + BR6: u1 = 0, + /// Reset bit 7 + BR7: u1 = 0, + /// Reset bit 8 + BR8: u1 = 0, + /// Reset bit 9 + BR9: u1 = 0, + /// Reset bit 10 + BR10: u1 = 0, + /// Reset bit 11 + BR11: u1 = 0, + /// Reset bit 12 + BR12: u1 = 0, + /// Reset bit 13 + BR13: u1 = 0, + /// Reset bit 14 + BR14: u1 = 0, + /// Reset bit 15 + BR15: u1 = 0, + }); + + /// Port bit reset register (GPIOn_BRR) pub const BRR = mmio(Address + 0x00000014, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Reset bit 0 - BR1: u1, // bit offset: 1 desc: Reset bit 1 - BR2: u1, // bit offset: 2 desc: Reset bit 1 - BR3: u1, // bit offset: 3 desc: Reset bit 3 - BR4: u1, // bit offset: 4 desc: Reset bit 4 - BR5: u1, // bit offset: 5 desc: Reset bit 5 - BR6: u1, // bit offset: 6 desc: Reset bit 6 - BR7: u1, // bit offset: 7 desc: Reset bit 7 - BR8: u1, // bit offset: 8 desc: Reset bit 8 - BR9: u1, // bit offset: 9 desc: Reset bit 9 - BR10: u1, // bit offset: 10 desc: Reset bit 10 - BR11: u1, // bit offset: 11 desc: Reset bit 11 - BR12: u1, // bit offset: 12 desc: Reset bit 12 - BR13: u1, // bit offset: 13 desc: Reset bit 13 - BR14: u1, // bit offset: 14 desc: Reset bit 14 - BR15: u1, // bit offset: 15 desc: Reset bit 15 + /// Reset bit 0 + BR0: u1 = 0, + /// Reset bit 1 + BR1: u1 = 0, + /// Reset bit 1 + BR2: u1 = 0, + /// Reset bit 3 + BR3: u1 = 0, + /// Reset bit 4 + BR4: u1 = 0, + /// Reset bit 5 + BR5: u1 = 0, + /// Reset bit 6 + BR6: u1 = 0, + /// Reset bit 7 + BR7: u1 = 0, + /// Reset bit 8 + BR8: u1 = 0, + /// Reset bit 9 + BR9: u1 = 0, + /// Reset bit 10 + BR10: u1 = 0, + /// Reset bit 11 + BR11: u1 = 0, + /// Reset bit 12 + BR12: u1 = 0, + /// Reset bit 13 + BR13: u1 = 0, + /// Reset bit 14 + BR14: u1 = 0, + /// Reset bit 15 + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2143,25 +2974,43 @@ pub const GPIOF = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 Port configuration lock register + + /// Port configuration lock register pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port A Lock bit 0 - LCK1: u1, // bit offset: 1 desc: Port A Lock bit 1 - LCK2: u1, // bit offset: 2 desc: Port A Lock bit 2 - LCK3: u1, // bit offset: 3 desc: Port A Lock bit 3 - LCK4: u1, // bit offset: 4 desc: Port A Lock bit 4 - LCK5: u1, // bit offset: 5 desc: Port A Lock bit 5 - LCK6: u1, // bit offset: 6 desc: Port A Lock bit 6 - LCK7: u1, // bit offset: 7 desc: Port A Lock bit 7 - LCK8: u1, // bit offset: 8 desc: Port A Lock bit 8 - LCK9: u1, // bit offset: 9 desc: Port A Lock bit 9 - LCK10: u1, // bit offset: 10 desc: Port A Lock bit 10 - LCK11: u1, // bit offset: 11 desc: Port A Lock bit 11 - LCK12: u1, // bit offset: 12 desc: Port A Lock bit 12 - LCK13: u1, // bit offset: 13 desc: Port A Lock bit 13 - LCK14: u1, // bit offset: 14 desc: Port A Lock bit 14 - LCK15: u1, // bit offset: 15 desc: Port A Lock bit 15 - LCKK: u1, // bit offset: 16 desc: Lock key + /// Port A Lock bit 0 + LCK0: u1 = 0, + /// Port A Lock bit 1 + LCK1: u1 = 0, + /// Port A Lock bit 2 + LCK2: u1 = 0, + /// Port A Lock bit 3 + LCK3: u1 = 0, + /// Port A Lock bit 4 + LCK4: u1 = 0, + /// Port A Lock bit 5 + LCK5: u1 = 0, + /// Port A Lock bit 6 + LCK6: u1 = 0, + /// Port A Lock bit 7 + LCK7: u1 = 0, + /// Port A Lock bit 8 + LCK8: u1 = 0, + /// Port A Lock bit 9 + LCK9: u1 = 0, + /// Port A Lock bit 10 + LCK10: u1 = 0, + /// Port A Lock bit 11 + LCK11: u1 = 0, + /// Port A Lock bit 12 + LCK12: u1 = 0, + /// Port A Lock bit 13 + LCK13: u1 = 0, + /// Port A Lock bit 14 + LCK14: u1 = 0, + /// Port A Lock bit 15 + LCK15: u1 = 0, + /// Lock key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -2179,64 +3028,117 @@ pub const GPIOF = extern struct { padding1: u1 = 0, }); }; + +/// General purpose I/O pub const GPIOG = extern struct { pub const Address: u32 = 0x40012000; - // byte offset: 0 Port configuration register low (GPIOn_CRL) + + /// Port configuration register low (GPIOn_CRL) pub const CRL = mmio(Address + 0x00000000, 32, packed struct { - MODE0: u2, // bit offset: 0 desc: Port n.0 mode bits - CNF0: u2, // bit offset: 2 desc: Port n.0 configuration bits - MODE1: u2, // bit offset: 4 desc: Port n.1 mode bits - CNF1: u2, // bit offset: 6 desc: Port n.1 configuration bits - MODE2: u2, // bit offset: 8 desc: Port n.2 mode bits - CNF2: u2, // bit offset: 10 desc: Port n.2 configuration bits - MODE3: u2, // bit offset: 12 desc: Port n.3 mode bits - CNF3: u2, // bit offset: 14 desc: Port n.3 configuration bits - MODE4: u2, // bit offset: 16 desc: Port n.4 mode bits - CNF4: u2, // bit offset: 18 desc: Port n.4 configuration bits - MODE5: u2, // bit offset: 20 desc: Port n.5 mode bits - CNF5: u2, // bit offset: 22 desc: Port n.5 configuration bits - MODE6: u2, // bit offset: 24 desc: Port n.6 mode bits - CNF6: u2, // bit offset: 26 desc: Port n.6 configuration bits - MODE7: u2, // bit offset: 28 desc: Port n.7 mode bits - CNF7: u2, // bit offset: 30 desc: Port n.7 configuration bits - }); - // byte offset: 4 Port configuration register high (GPIOn_CRL) + /// Port n.0 mode bits + MODE0: u2 = 0, + /// Port n.0 configuration bits + CNF0: u2 = 0, + /// Port n.1 mode bits + MODE1: u2 = 0, + /// Port n.1 configuration bits + CNF1: u2 = 0, + /// Port n.2 mode bits + MODE2: u2 = 0, + /// Port n.2 configuration bits + CNF2: u2 = 0, + /// Port n.3 mode bits + MODE3: u2 = 0, + /// Port n.3 configuration bits + CNF3: u2 = 0, + /// Port n.4 mode bits + MODE4: u2 = 0, + /// Port n.4 configuration bits + CNF4: u2 = 0, + /// Port n.5 mode bits + MODE5: u2 = 0, + /// Port n.5 configuration bits + CNF5: u2 = 0, + /// Port n.6 mode bits + MODE6: u2 = 0, + /// Port n.6 configuration bits + CNF6: u2 = 0, + /// Port n.7 mode bits + MODE7: u2 = 0, + /// Port n.7 configuration bits + CNF7: u2 = 0, + }); + + /// Port configuration register high (GPIOn_CRL) pub const CRH = mmio(Address + 0x00000004, 32, packed struct { - MODE8: u2, // bit offset: 0 desc: Port n.8 mode bits - CNF8: u2, // bit offset: 2 desc: Port n.8 configuration bits - MODE9: u2, // bit offset: 4 desc: Port n.9 mode bits - CNF9: u2, // bit offset: 6 desc: Port n.9 configuration bits - MODE10: u2, // bit offset: 8 desc: Port n.10 mode bits - CNF10: u2, // bit offset: 10 desc: Port n.10 configuration bits - MODE11: u2, // bit offset: 12 desc: Port n.11 mode bits - CNF11: u2, // bit offset: 14 desc: Port n.11 configuration bits - MODE12: u2, // bit offset: 16 desc: Port n.12 mode bits - CNF12: u2, // bit offset: 18 desc: Port n.12 configuration bits - MODE13: u2, // bit offset: 20 desc: Port n.13 mode bits - CNF13: u2, // bit offset: 22 desc: Port n.13 configuration bits - MODE14: u2, // bit offset: 24 desc: Port n.14 mode bits - CNF14: u2, // bit offset: 26 desc: Port n.14 configuration bits - MODE15: u2, // bit offset: 28 desc: Port n.15 mode bits - CNF15: u2, // bit offset: 30 desc: Port n.15 configuration bits - }); - // byte offset: 8 Port input data register (GPIOn_IDR) + /// Port n.8 mode bits + MODE8: u2 = 0, + /// Port n.8 configuration bits + CNF8: u2 = 0, + /// Port n.9 mode bits + MODE9: u2 = 0, + /// Port n.9 configuration bits + CNF9: u2 = 0, + /// Port n.10 mode bits + MODE10: u2 = 0, + /// Port n.10 configuration bits + CNF10: u2 = 0, + /// Port n.11 mode bits + MODE11: u2 = 0, + /// Port n.11 configuration bits + CNF11: u2 = 0, + /// Port n.12 mode bits + MODE12: u2 = 0, + /// Port n.12 configuration bits + CNF12: u2 = 0, + /// Port n.13 mode bits + MODE13: u2 = 0, + /// Port n.13 configuration bits + CNF13: u2 = 0, + /// Port n.14 mode bits + MODE14: u2 = 0, + /// Port n.14 configuration bits + CNF14: u2 = 0, + /// Port n.15 mode bits + MODE15: u2 = 0, + /// Port n.15 configuration bits + CNF15: u2 = 0, + }); + + /// Port input data register (GPIOn_IDR) pub const IDR = mmio(Address + 0x00000008, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data - IDR1: u1, // bit offset: 1 desc: Port input data - IDR2: u1, // bit offset: 2 desc: Port input data - IDR3: u1, // bit offset: 3 desc: Port input data - IDR4: u1, // bit offset: 4 desc: Port input data - IDR5: u1, // bit offset: 5 desc: Port input data - IDR6: u1, // bit offset: 6 desc: Port input data - IDR7: u1, // bit offset: 7 desc: Port input data - IDR8: u1, // bit offset: 8 desc: Port input data - IDR9: u1, // bit offset: 9 desc: Port input data - IDR10: u1, // bit offset: 10 desc: Port input data - IDR11: u1, // bit offset: 11 desc: Port input data - IDR12: u1, // bit offset: 12 desc: Port input data - IDR13: u1, // bit offset: 13 desc: Port input data - IDR14: u1, // bit offset: 14 desc: Port input data - IDR15: u1, // bit offset: 15 desc: Port input data + /// Port input data + IDR0: u1 = 0, + /// Port input data + IDR1: u1 = 0, + /// Port input data + IDR2: u1 = 0, + /// Port input data + IDR3: u1 = 0, + /// Port input data + IDR4: u1 = 0, + /// Port input data + IDR5: u1 = 0, + /// Port input data + IDR6: u1 = 0, + /// Port input data + IDR7: u1 = 0, + /// Port input data + IDR8: u1 = 0, + /// Port input data + IDR9: u1 = 0, + /// Port input data + IDR10: u1 = 0, + /// Port input data + IDR11: u1 = 0, + /// Port input data + IDR12: u1 = 0, + /// Port input data + IDR13: u1 = 0, + /// Port input data + IDR14: u1 = 0, + /// Port input data + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2254,24 +3156,41 @@ pub const GPIOG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Port output data register (GPIOn_ODR) + + /// Port output data register (GPIOn_ODR) pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data - ODR1: u1, // bit offset: 1 desc: Port output data - ODR2: u1, // bit offset: 2 desc: Port output data - ODR3: u1, // bit offset: 3 desc: Port output data - ODR4: u1, // bit offset: 4 desc: Port output data - ODR5: u1, // bit offset: 5 desc: Port output data - ODR6: u1, // bit offset: 6 desc: Port output data - ODR7: u1, // bit offset: 7 desc: Port output data - ODR8: u1, // bit offset: 8 desc: Port output data - ODR9: u1, // bit offset: 9 desc: Port output data - ODR10: u1, // bit offset: 10 desc: Port output data - ODR11: u1, // bit offset: 11 desc: Port output data - ODR12: u1, // bit offset: 12 desc: Port output data - ODR13: u1, // bit offset: 13 desc: Port output data - ODR14: u1, // bit offset: 14 desc: Port output data - ODR15: u1, // bit offset: 15 desc: Port output data + /// Port output data + ODR0: u1 = 0, + /// Port output data + ODR1: u1 = 0, + /// Port output data + ODR2: u1 = 0, + /// Port output data + ODR3: u1 = 0, + /// Port output data + ODR4: u1 = 0, + /// Port output data + ODR5: u1 = 0, + /// Port output data + ODR6: u1 = 0, + /// Port output data + ODR7: u1 = 0, + /// Port output data + ODR8: u1 = 0, + /// Port output data + ODR9: u1 = 0, + /// Port output data + ODR10: u1 = 0, + /// Port output data + ODR11: u1 = 0, + /// Port output data + ODR12: u1 = 0, + /// Port output data + ODR13: u1 = 0, + /// Port output data + ODR14: u1 = 0, + /// Port output data + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2289,59 +3208,109 @@ pub const GPIOG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Port bit set/reset register (GPIOn_BSRR) + + /// Port bit set/reset register (GPIOn_BSRR) pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Set bit 0 - BS1: u1, // bit offset: 1 desc: Set bit 1 - BS2: u1, // bit offset: 2 desc: Set bit 1 - BS3: u1, // bit offset: 3 desc: Set bit 3 - BS4: u1, // bit offset: 4 desc: Set bit 4 - BS5: u1, // bit offset: 5 desc: Set bit 5 - BS6: u1, // bit offset: 6 desc: Set bit 6 - BS7: u1, // bit offset: 7 desc: Set bit 7 - BS8: u1, // bit offset: 8 desc: Set bit 8 - BS9: u1, // bit offset: 9 desc: Set bit 9 - BS10: u1, // bit offset: 10 desc: Set bit 10 - BS11: u1, // bit offset: 11 desc: Set bit 11 - BS12: u1, // bit offset: 12 desc: Set bit 12 - BS13: u1, // bit offset: 13 desc: Set bit 13 - BS14: u1, // bit offset: 14 desc: Set bit 14 - BS15: u1, // bit offset: 15 desc: Set bit 15 - BR0: u1, // bit offset: 16 desc: Reset bit 0 - BR1: u1, // bit offset: 17 desc: Reset bit 1 - BR2: u1, // bit offset: 18 desc: Reset bit 2 - BR3: u1, // bit offset: 19 desc: Reset bit 3 - BR4: u1, // bit offset: 20 desc: Reset bit 4 - BR5: u1, // bit offset: 21 desc: Reset bit 5 - BR6: u1, // bit offset: 22 desc: Reset bit 6 - BR7: u1, // bit offset: 23 desc: Reset bit 7 - BR8: u1, // bit offset: 24 desc: Reset bit 8 - BR9: u1, // bit offset: 25 desc: Reset bit 9 - BR10: u1, // bit offset: 26 desc: Reset bit 10 - BR11: u1, // bit offset: 27 desc: Reset bit 11 - BR12: u1, // bit offset: 28 desc: Reset bit 12 - BR13: u1, // bit offset: 29 desc: Reset bit 13 - BR14: u1, // bit offset: 30 desc: Reset bit 14 - BR15: u1, // bit offset: 31 desc: Reset bit 15 - }); - // byte offset: 20 Port bit reset register (GPIOn_BRR) + /// Set bit 0 + BS0: u1 = 0, + /// Set bit 1 + BS1: u1 = 0, + /// Set bit 1 + BS2: u1 = 0, + /// Set bit 3 + BS3: u1 = 0, + /// Set bit 4 + BS4: u1 = 0, + /// Set bit 5 + BS5: u1 = 0, + /// Set bit 6 + BS6: u1 = 0, + /// Set bit 7 + BS7: u1 = 0, + /// Set bit 8 + BS8: u1 = 0, + /// Set bit 9 + BS9: u1 = 0, + /// Set bit 10 + BS10: u1 = 0, + /// Set bit 11 + BS11: u1 = 0, + /// Set bit 12 + BS12: u1 = 0, + /// Set bit 13 + BS13: u1 = 0, + /// Set bit 14 + BS14: u1 = 0, + /// Set bit 15 + BS15: u1 = 0, + /// Reset bit 0 + BR0: u1 = 0, + /// Reset bit 1 + BR1: u1 = 0, + /// Reset bit 2 + BR2: u1 = 0, + /// Reset bit 3 + BR3: u1 = 0, + /// Reset bit 4 + BR4: u1 = 0, + /// Reset bit 5 + BR5: u1 = 0, + /// Reset bit 6 + BR6: u1 = 0, + /// Reset bit 7 + BR7: u1 = 0, + /// Reset bit 8 + BR8: u1 = 0, + /// Reset bit 9 + BR9: u1 = 0, + /// Reset bit 10 + BR10: u1 = 0, + /// Reset bit 11 + BR11: u1 = 0, + /// Reset bit 12 + BR12: u1 = 0, + /// Reset bit 13 + BR13: u1 = 0, + /// Reset bit 14 + BR14: u1 = 0, + /// Reset bit 15 + BR15: u1 = 0, + }); + + /// Port bit reset register (GPIOn_BRR) pub const BRR = mmio(Address + 0x00000014, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Reset bit 0 - BR1: u1, // bit offset: 1 desc: Reset bit 1 - BR2: u1, // bit offset: 2 desc: Reset bit 1 - BR3: u1, // bit offset: 3 desc: Reset bit 3 - BR4: u1, // bit offset: 4 desc: Reset bit 4 - BR5: u1, // bit offset: 5 desc: Reset bit 5 - BR6: u1, // bit offset: 6 desc: Reset bit 6 - BR7: u1, // bit offset: 7 desc: Reset bit 7 - BR8: u1, // bit offset: 8 desc: Reset bit 8 - BR9: u1, // bit offset: 9 desc: Reset bit 9 - BR10: u1, // bit offset: 10 desc: Reset bit 10 - BR11: u1, // bit offset: 11 desc: Reset bit 11 - BR12: u1, // bit offset: 12 desc: Reset bit 12 - BR13: u1, // bit offset: 13 desc: Reset bit 13 - BR14: u1, // bit offset: 14 desc: Reset bit 14 - BR15: u1, // bit offset: 15 desc: Reset bit 15 + /// Reset bit 0 + BR0: u1 = 0, + /// Reset bit 1 + BR1: u1 = 0, + /// Reset bit 1 + BR2: u1 = 0, + /// Reset bit 3 + BR3: u1 = 0, + /// Reset bit 4 + BR4: u1 = 0, + /// Reset bit 5 + BR5: u1 = 0, + /// Reset bit 6 + BR6: u1 = 0, + /// Reset bit 7 + BR7: u1 = 0, + /// Reset bit 8 + BR8: u1 = 0, + /// Reset bit 9 + BR9: u1 = 0, + /// Reset bit 10 + BR10: u1 = 0, + /// Reset bit 11 + BR11: u1 = 0, + /// Reset bit 12 + BR12: u1 = 0, + /// Reset bit 13 + BR13: u1 = 0, + /// Reset bit 14 + BR14: u1 = 0, + /// Reset bit 15 + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2359,25 +3328,43 @@ pub const GPIOG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 Port configuration lock register + + /// Port configuration lock register pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port A Lock bit 0 - LCK1: u1, // bit offset: 1 desc: Port A Lock bit 1 - LCK2: u1, // bit offset: 2 desc: Port A Lock bit 2 - LCK3: u1, // bit offset: 3 desc: Port A Lock bit 3 - LCK4: u1, // bit offset: 4 desc: Port A Lock bit 4 - LCK5: u1, // bit offset: 5 desc: Port A Lock bit 5 - LCK6: u1, // bit offset: 6 desc: Port A Lock bit 6 - LCK7: u1, // bit offset: 7 desc: Port A Lock bit 7 - LCK8: u1, // bit offset: 8 desc: Port A Lock bit 8 - LCK9: u1, // bit offset: 9 desc: Port A Lock bit 9 - LCK10: u1, // bit offset: 10 desc: Port A Lock bit 10 - LCK11: u1, // bit offset: 11 desc: Port A Lock bit 11 - LCK12: u1, // bit offset: 12 desc: Port A Lock bit 12 - LCK13: u1, // bit offset: 13 desc: Port A Lock bit 13 - LCK14: u1, // bit offset: 14 desc: Port A Lock bit 14 - LCK15: u1, // bit offset: 15 desc: Port A Lock bit 15 - LCKK: u1, // bit offset: 16 desc: Lock key + /// Port A Lock bit 0 + LCK0: u1 = 0, + /// Port A Lock bit 1 + LCK1: u1 = 0, + /// Port A Lock bit 2 + LCK2: u1 = 0, + /// Port A Lock bit 3 + LCK3: u1 = 0, + /// Port A Lock bit 4 + LCK4: u1 = 0, + /// Port A Lock bit 5 + LCK5: u1 = 0, + /// Port A Lock bit 6 + LCK6: u1 = 0, + /// Port A Lock bit 7 + LCK7: u1 = 0, + /// Port A Lock bit 8 + LCK8: u1 = 0, + /// Port A Lock bit 9 + LCK9: u1 = 0, + /// Port A Lock bit 10 + LCK10: u1 = 0, + /// Port A Lock bit 11 + LCK11: u1 = 0, + /// Port A Lock bit 12 + LCK12: u1 = 0, + /// Port A Lock bit 13 + LCK13: u1 = 0, + /// Port A Lock bit 14 + LCK14: u1 = 0, + /// Port A Lock bit 15 + LCK15: u1 = 0, + /// Lock key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -2395,13 +3382,19 @@ pub const GPIOG = extern struct { padding1: u1 = 0, }); }; + +/// Alternate function I/O pub const AFIO = extern struct { pub const Address: u32 = 0x40010000; - // byte offset: 0 Event Control Register (AFIO_EVCR) + + /// Event Control Register (AFIO_EVCR) pub const EVCR = mmio(Address + 0x00000000, 32, packed struct { - PIN: u4, // bit offset: 0 desc: Pin selection - PORT: u3, // bit offset: 4 desc: Port selection - EVOE: u1, // bit offset: 7 desc: Event Output Enable + /// Pin selection + PIN: u4 = 0, + /// Port selection + PORT: u3 = 0, + /// Event Output Enable + EVOE: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -2427,40 +3420,63 @@ pub const AFIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 AF remap and debug I/O configuration register (AFIO_MAPR) + + /// AF remap and debug I/O configuration register (AFIO_MAPR) pub const MAPR = mmio(Address + 0x00000004, 32, packed struct { - SPI1_REMAP: u1, // bit offset: 0 desc: SPI1 remapping - I2C1_REMAP: u1, // bit offset: 1 desc: I2C1 remapping - USART1_REMAP: u1, // bit offset: 2 desc: USART1 remapping - USART2_REMAP: u1, // bit offset: 3 desc: USART2 remapping - USART3_REMAP: u2, // bit offset: 4 desc: USART3 remapping - TIM1_REMAP: u2, // bit offset: 6 desc: TIM1 remapping - TIM2_REMAP: u2, // bit offset: 8 desc: TIM2 remapping - TIM3_REMAP: u2, // bit offset: 10 desc: TIM3 remapping - TIM4_REMAP: u1, // bit offset: 12 desc: TIM4 remapping - CAN_REMAP: u2, // bit offset: 13 desc: CAN1 remapping - PD01_REMAP: u1, // bit offset: 15 desc: Port D0/Port D1 mapping on OSCIN/OSCOUT - TIM5CH4_IREMAP: u1, // bit offset: 16 desc: Set and cleared by software - ADC1_ETRGINJ_REMAP: u1, // bit offset: 17 desc: ADC 1 External trigger injected conversion remapping - ADC1_ETRGREG_REMAP: u1, // bit offset: 18 desc: ADC 1 external trigger regular conversion remapping - ADC2_ETRGINJ_REMAP: u1, // bit offset: 19 desc: ADC 2 external trigger injected conversion remapping - ADC2_ETRGREG_REMAP: u1, // bit offset: 20 desc: ADC 2 external trigger regular conversion remapping + /// SPI1 remapping + SPI1_REMAP: u1 = 0, + /// I2C1 remapping + I2C1_REMAP: u1 = 0, + /// USART1 remapping + USART1_REMAP: u1 = 0, + /// USART2 remapping + USART2_REMAP: u1 = 0, + /// USART3 remapping + USART3_REMAP: u2 = 0, + /// TIM1 remapping + TIM1_REMAP: u2 = 0, + /// TIM2 remapping + TIM2_REMAP: u2 = 0, + /// TIM3 remapping + TIM3_REMAP: u2 = 0, + /// TIM4 remapping + TIM4_REMAP: u1 = 0, + /// CAN1 remapping + CAN_REMAP: u2 = 0, + /// Port D0/Port D1 mapping on OSCIN/OSCOUT + PD01_REMAP: u1 = 0, + /// Set and cleared by software + TIM5CH4_IREMAP: u1 = 0, + /// ADC 1 External trigger injected conversion remapping + ADC1_ETRGINJ_REMAP: u1 = 0, + /// ADC 1 external trigger regular conversion remapping + ADC1_ETRGREG_REMAP: u1 = 0, + /// ADC 2 external trigger injected conversion remapping + ADC2_ETRGINJ_REMAP: u1 = 0, + /// ADC 2 external trigger regular conversion remapping + ADC2_ETRGREG_REMAP: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - SWJ_CFG: u3, // bit offset: 24 desc: Serial wire JTAG configuration + /// Serial wire JTAG configuration + SWJ_CFG: u3 = 0, padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 External interrupt configuration register 1 (AFIO_EXTICR1) + + /// External interrupt configuration register 1 (AFIO_EXTICR1) pub const EXTICR1 = mmio(Address + 0x00000008, 32, packed struct { - EXTI0: u4, // bit offset: 0 desc: EXTI0 configuration - EXTI1: u4, // bit offset: 4 desc: EXTI1 configuration - EXTI2: u4, // bit offset: 8 desc: EXTI2 configuration - EXTI3: u4, // bit offset: 12 desc: EXTI3 configuration + /// EXTI0 configuration + EXTI0: u4 = 0, + /// EXTI1 configuration + EXTI1: u4 = 0, + /// EXTI2 configuration + EXTI2: u4 = 0, + /// EXTI3 configuration + EXTI3: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2478,12 +3494,17 @@ pub const AFIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 External interrupt configuration register 2 (AFIO_EXTICR2) + + /// External interrupt configuration register 2 (AFIO_EXTICR2) pub const EXTICR2 = mmio(Address + 0x0000000c, 32, packed struct { - EXTI4: u4, // bit offset: 0 desc: EXTI4 configuration - EXTI5: u4, // bit offset: 4 desc: EXTI5 configuration - EXTI6: u4, // bit offset: 8 desc: EXTI6 configuration - EXTI7: u4, // bit offset: 12 desc: EXTI7 configuration + /// EXTI4 configuration + EXTI4: u4 = 0, + /// EXTI5 configuration + EXTI5: u4 = 0, + /// EXTI6 configuration + EXTI6: u4 = 0, + /// EXTI7 configuration + EXTI7: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2501,12 +3522,17 @@ pub const AFIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 External interrupt configuration register 3 (AFIO_EXTICR3) + + /// External interrupt configuration register 3 (AFIO_EXTICR3) pub const EXTICR3 = mmio(Address + 0x00000010, 32, packed struct { - EXTI8: u4, // bit offset: 0 desc: EXTI8 configuration - EXTI9: u4, // bit offset: 4 desc: EXTI9 configuration - EXTI10: u4, // bit offset: 8 desc: EXTI10 configuration - EXTI11: u4, // bit offset: 12 desc: EXTI11 configuration + /// EXTI8 configuration + EXTI8: u4 = 0, + /// EXTI9 configuration + EXTI9: u4 = 0, + /// EXTI10 configuration + EXTI10: u4 = 0, + /// EXTI11 configuration + EXTI11: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2524,12 +3550,17 @@ pub const AFIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 External interrupt configuration register 4 (AFIO_EXTICR4) + + /// External interrupt configuration register 4 (AFIO_EXTICR4) pub const EXTICR4 = mmio(Address + 0x00000014, 32, packed struct { - EXTI12: u4, // bit offset: 0 desc: EXTI12 configuration - EXTI13: u4, // bit offset: 4 desc: EXTI13 configuration - EXTI14: u4, // bit offset: 8 desc: EXTI14 configuration - EXTI15: u4, // bit offset: 12 desc: EXTI15 configuration + /// EXTI12 configuration + EXTI12: u4 = 0, + /// EXTI13 configuration + EXTI13: u4 = 0, + /// EXTI14 configuration + EXTI14: u4 = 0, + /// EXTI15 configuration + EXTI15: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2547,19 +3578,26 @@ pub const AFIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 AF remap and debug I/O configuration register + + /// AF remap and debug I/O configuration register pub const MAPR2 = mmio(Address + 0x0000001c, 32, packed struct { reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TIM9_REMAP: u1, // bit offset: 5 desc: TIM9 remapping - TIM10_REMAP: u1, // bit offset: 6 desc: TIM10 remapping - TIM11_REMAP: u1, // bit offset: 7 desc: TIM11 remapping - TIM13_REMAP: u1, // bit offset: 8 desc: TIM13 remapping - TIM14_REMAP: u1, // bit offset: 9 desc: TIM14 remapping - FSMC_NADV: u1, // bit offset: 10 desc: NADV connect/disconnect + /// TIM9 remapping + TIM9_REMAP: u1 = 0, + /// TIM10 remapping + TIM10_REMAP: u1 = 0, + /// TIM11 remapping + TIM11_REMAP: u1 = 0, + /// TIM13 remapping + TIM13_REMAP: u1 = 0, + /// TIM14 remapping + TIM14_REMAP: u1 = 0, + /// NADV connect/disconnect + FSMC_NADV: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -2583,29 +3621,51 @@ pub const AFIO = extern struct { padding1: u1 = 0, }); }; + +/// EXTI pub const EXTI = extern struct { pub const Address: u32 = 0x40010400; - // byte offset: 0 Interrupt mask register (EXTI_IMR) + + /// Interrupt mask register (EXTI_IMR) pub const IMR = mmio(Address + 0x00000000, 32, packed struct { - MR0: u1, // bit offset: 0 desc: Interrupt Mask on line 0 - MR1: u1, // bit offset: 1 desc: Interrupt Mask on line 1 - MR2: u1, // bit offset: 2 desc: Interrupt Mask on line 2 - MR3: u1, // bit offset: 3 desc: Interrupt Mask on line 3 - MR4: u1, // bit offset: 4 desc: Interrupt Mask on line 4 - MR5: u1, // bit offset: 5 desc: Interrupt Mask on line 5 - MR6: u1, // bit offset: 6 desc: Interrupt Mask on line 6 - MR7: u1, // bit offset: 7 desc: Interrupt Mask on line 7 - MR8: u1, // bit offset: 8 desc: Interrupt Mask on line 8 - MR9: u1, // bit offset: 9 desc: Interrupt Mask on line 9 - MR10: u1, // bit offset: 10 desc: Interrupt Mask on line 10 - MR11: u1, // bit offset: 11 desc: Interrupt Mask on line 11 - MR12: u1, // bit offset: 12 desc: Interrupt Mask on line 12 - MR13: u1, // bit offset: 13 desc: Interrupt Mask on line 13 - MR14: u1, // bit offset: 14 desc: Interrupt Mask on line 14 - MR15: u1, // bit offset: 15 desc: Interrupt Mask on line 15 - MR16: u1, // bit offset: 16 desc: Interrupt Mask on line 16 - MR17: u1, // bit offset: 17 desc: Interrupt Mask on line 17 - MR18: u1, // bit offset: 18 desc: Interrupt Mask on line 18 + /// Interrupt Mask on line 0 + MR0: u1 = 0, + /// Interrupt Mask on line 1 + MR1: u1 = 0, + /// Interrupt Mask on line 2 + MR2: u1 = 0, + /// Interrupt Mask on line 3 + MR3: u1 = 0, + /// Interrupt Mask on line 4 + MR4: u1 = 0, + /// Interrupt Mask on line 5 + MR5: u1 = 0, + /// Interrupt Mask on line 6 + MR6: u1 = 0, + /// Interrupt Mask on line 7 + MR7: u1 = 0, + /// Interrupt Mask on line 8 + MR8: u1 = 0, + /// Interrupt Mask on line 9 + MR9: u1 = 0, + /// Interrupt Mask on line 10 + MR10: u1 = 0, + /// Interrupt Mask on line 11 + MR11: u1 = 0, + /// Interrupt Mask on line 12 + MR12: u1 = 0, + /// Interrupt Mask on line 13 + MR13: u1 = 0, + /// Interrupt Mask on line 14 + MR14: u1 = 0, + /// Interrupt Mask on line 15 + MR15: u1 = 0, + /// Interrupt Mask on line 16 + MR16: u1 = 0, + /// Interrupt Mask on line 17 + MR17: u1 = 0, + /// Interrupt Mask on line 18 + MR18: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -2620,27 +3680,47 @@ pub const EXTI = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Event mask register (EXTI_EMR) + + /// Event mask register (EXTI_EMR) pub const EMR = mmio(Address + 0x00000004, 32, packed struct { - MR0: u1, // bit offset: 0 desc: Event Mask on line 0 - MR1: u1, // bit offset: 1 desc: Event Mask on line 1 - MR2: u1, // bit offset: 2 desc: Event Mask on line 2 - MR3: u1, // bit offset: 3 desc: Event Mask on line 3 - MR4: u1, // bit offset: 4 desc: Event Mask on line 4 - MR5: u1, // bit offset: 5 desc: Event Mask on line 5 - MR6: u1, // bit offset: 6 desc: Event Mask on line 6 - MR7: u1, // bit offset: 7 desc: Event Mask on line 7 - MR8: u1, // bit offset: 8 desc: Event Mask on line 8 - MR9: u1, // bit offset: 9 desc: Event Mask on line 9 - MR10: u1, // bit offset: 10 desc: Event Mask on line 10 - MR11: u1, // bit offset: 11 desc: Event Mask on line 11 - MR12: u1, // bit offset: 12 desc: Event Mask on line 12 - MR13: u1, // bit offset: 13 desc: Event Mask on line 13 - MR14: u1, // bit offset: 14 desc: Event Mask on line 14 - MR15: u1, // bit offset: 15 desc: Event Mask on line 15 - MR16: u1, // bit offset: 16 desc: Event Mask on line 16 - MR17: u1, // bit offset: 17 desc: Event Mask on line 17 - MR18: u1, // bit offset: 18 desc: Event Mask on line 18 + /// Event Mask on line 0 + MR0: u1 = 0, + /// Event Mask on line 1 + MR1: u1 = 0, + /// Event Mask on line 2 + MR2: u1 = 0, + /// Event Mask on line 3 + MR3: u1 = 0, + /// Event Mask on line 4 + MR4: u1 = 0, + /// Event Mask on line 5 + MR5: u1 = 0, + /// Event Mask on line 6 + MR6: u1 = 0, + /// Event Mask on line 7 + MR7: u1 = 0, + /// Event Mask on line 8 + MR8: u1 = 0, + /// Event Mask on line 9 + MR9: u1 = 0, + /// Event Mask on line 10 + MR10: u1 = 0, + /// Event Mask on line 11 + MR11: u1 = 0, + /// Event Mask on line 12 + MR12: u1 = 0, + /// Event Mask on line 13 + MR13: u1 = 0, + /// Event Mask on line 14 + MR14: u1 = 0, + /// Event Mask on line 15 + MR15: u1 = 0, + /// Event Mask on line 16 + MR16: u1 = 0, + /// Event Mask on line 17 + MR17: u1 = 0, + /// Event Mask on line 18 + MR18: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -2655,27 +3735,47 @@ pub const EXTI = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Rising Trigger selection register (EXTI_RTSR) + + /// Rising Trigger selection register (EXTI_RTSR) pub const RTSR = mmio(Address + 0x00000008, 32, packed struct { - TR0: u1, // bit offset: 0 desc: Rising trigger event configuration of line 0 - TR1: u1, // bit offset: 1 desc: Rising trigger event configuration of line 1 - TR2: u1, // bit offset: 2 desc: Rising trigger event configuration of line 2 - TR3: u1, // bit offset: 3 desc: Rising trigger event configuration of line 3 - TR4: u1, // bit offset: 4 desc: Rising trigger event configuration of line 4 - TR5: u1, // bit offset: 5 desc: Rising trigger event configuration of line 5 - TR6: u1, // bit offset: 6 desc: Rising trigger event configuration of line 6 - TR7: u1, // bit offset: 7 desc: Rising trigger event configuration of line 7 - TR8: u1, // bit offset: 8 desc: Rising trigger event configuration of line 8 - TR9: u1, // bit offset: 9 desc: Rising trigger event configuration of line 9 - TR10: u1, // bit offset: 10 desc: Rising trigger event configuration of line 10 - TR11: u1, // bit offset: 11 desc: Rising trigger event configuration of line 11 - TR12: u1, // bit offset: 12 desc: Rising trigger event configuration of line 12 - TR13: u1, // bit offset: 13 desc: Rising trigger event configuration of line 13 - TR14: u1, // bit offset: 14 desc: Rising trigger event configuration of line 14 - TR15: u1, // bit offset: 15 desc: Rising trigger event configuration of line 15 - TR16: u1, // bit offset: 16 desc: Rising trigger event configuration of line 16 - TR17: u1, // bit offset: 17 desc: Rising trigger event configuration of line 17 - TR18: u1, // bit offset: 18 desc: Rising trigger event configuration of line 18 + /// Rising trigger event configuration of line 0 + TR0: u1 = 0, + /// Rising trigger event configuration of line 1 + TR1: u1 = 0, + /// Rising trigger event configuration of line 2 + TR2: u1 = 0, + /// Rising trigger event configuration of line 3 + TR3: u1 = 0, + /// Rising trigger event configuration of line 4 + TR4: u1 = 0, + /// Rising trigger event configuration of line 5 + TR5: u1 = 0, + /// Rising trigger event configuration of line 6 + TR6: u1 = 0, + /// Rising trigger event configuration of line 7 + TR7: u1 = 0, + /// Rising trigger event configuration of line 8 + TR8: u1 = 0, + /// Rising trigger event configuration of line 9 + TR9: u1 = 0, + /// Rising trigger event configuration of line 10 + TR10: u1 = 0, + /// Rising trigger event configuration of line 11 + TR11: u1 = 0, + /// Rising trigger event configuration of line 12 + TR12: u1 = 0, + /// Rising trigger event configuration of line 13 + TR13: u1 = 0, + /// Rising trigger event configuration of line 14 + TR14: u1 = 0, + /// Rising trigger event configuration of line 15 + TR15: u1 = 0, + /// Rising trigger event configuration of line 16 + TR16: u1 = 0, + /// Rising trigger event configuration of line 17 + TR17: u1 = 0, + /// Rising trigger event configuration of line 18 + TR18: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -2690,27 +3790,47 @@ pub const EXTI = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Falling Trigger selection register (EXTI_FTSR) + + /// Falling Trigger selection register (EXTI_FTSR) pub const FTSR = mmio(Address + 0x0000000c, 32, packed struct { - TR0: u1, // bit offset: 0 desc: Falling trigger event configuration of line 0 - TR1: u1, // bit offset: 1 desc: Falling trigger event configuration of line 1 - TR2: u1, // bit offset: 2 desc: Falling trigger event configuration of line 2 - TR3: u1, // bit offset: 3 desc: Falling trigger event configuration of line 3 - TR4: u1, // bit offset: 4 desc: Falling trigger event configuration of line 4 - TR5: u1, // bit offset: 5 desc: Falling trigger event configuration of line 5 - TR6: u1, // bit offset: 6 desc: Falling trigger event configuration of line 6 - TR7: u1, // bit offset: 7 desc: Falling trigger event configuration of line 7 - TR8: u1, // bit offset: 8 desc: Falling trigger event configuration of line 8 - TR9: u1, // bit offset: 9 desc: Falling trigger event configuration of line 9 - TR10: u1, // bit offset: 10 desc: Falling trigger event configuration of line 10 - TR11: u1, // bit offset: 11 desc: Falling trigger event configuration of line 11 - TR12: u1, // bit offset: 12 desc: Falling trigger event configuration of line 12 - TR13: u1, // bit offset: 13 desc: Falling trigger event configuration of line 13 - TR14: u1, // bit offset: 14 desc: Falling trigger event configuration of line 14 - TR15: u1, // bit offset: 15 desc: Falling trigger event configuration of line 15 - TR16: u1, // bit offset: 16 desc: Falling trigger event configuration of line 16 - TR17: u1, // bit offset: 17 desc: Falling trigger event configuration of line 17 - TR18: u1, // bit offset: 18 desc: Falling trigger event configuration of line 18 + /// Falling trigger event configuration of line 0 + TR0: u1 = 0, + /// Falling trigger event configuration of line 1 + TR1: u1 = 0, + /// Falling trigger event configuration of line 2 + TR2: u1 = 0, + /// Falling trigger event configuration of line 3 + TR3: u1 = 0, + /// Falling trigger event configuration of line 4 + TR4: u1 = 0, + /// Falling trigger event configuration of line 5 + TR5: u1 = 0, + /// Falling trigger event configuration of line 6 + TR6: u1 = 0, + /// Falling trigger event configuration of line 7 + TR7: u1 = 0, + /// Falling trigger event configuration of line 8 + TR8: u1 = 0, + /// Falling trigger event configuration of line 9 + TR9: u1 = 0, + /// Falling trigger event configuration of line 10 + TR10: u1 = 0, + /// Falling trigger event configuration of line 11 + TR11: u1 = 0, + /// Falling trigger event configuration of line 12 + TR12: u1 = 0, + /// Falling trigger event configuration of line 13 + TR13: u1 = 0, + /// Falling trigger event configuration of line 14 + TR14: u1 = 0, + /// Falling trigger event configuration of line 15 + TR15: u1 = 0, + /// Falling trigger event configuration of line 16 + TR16: u1 = 0, + /// Falling trigger event configuration of line 17 + TR17: u1 = 0, + /// Falling trigger event configuration of line 18 + TR18: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -2725,27 +3845,47 @@ pub const EXTI = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Software interrupt event register (EXTI_SWIER) + + /// Software interrupt event register (EXTI_SWIER) pub const SWIER = mmio(Address + 0x00000010, 32, packed struct { - SWIER0: u1, // bit offset: 0 desc: Software Interrupt on line 0 - SWIER1: u1, // bit offset: 1 desc: Software Interrupt on line 1 - SWIER2: u1, // bit offset: 2 desc: Software Interrupt on line 2 - SWIER3: u1, // bit offset: 3 desc: Software Interrupt on line 3 - SWIER4: u1, // bit offset: 4 desc: Software Interrupt on line 4 - SWIER5: u1, // bit offset: 5 desc: Software Interrupt on line 5 - SWIER6: u1, // bit offset: 6 desc: Software Interrupt on line 6 - SWIER7: u1, // bit offset: 7 desc: Software Interrupt on line 7 - SWIER8: u1, // bit offset: 8 desc: Software Interrupt on line 8 - SWIER9: u1, // bit offset: 9 desc: Software Interrupt on line 9 - SWIER10: u1, // bit offset: 10 desc: Software Interrupt on line 10 - SWIER11: u1, // bit offset: 11 desc: Software Interrupt on line 11 - SWIER12: u1, // bit offset: 12 desc: Software Interrupt on line 12 - SWIER13: u1, // bit offset: 13 desc: Software Interrupt on line 13 - SWIER14: u1, // bit offset: 14 desc: Software Interrupt on line 14 - SWIER15: u1, // bit offset: 15 desc: Software Interrupt on line 15 - SWIER16: u1, // bit offset: 16 desc: Software Interrupt on line 16 - SWIER17: u1, // bit offset: 17 desc: Software Interrupt on line 17 - SWIER18: u1, // bit offset: 18 desc: Software Interrupt on line 18 + /// Software Interrupt on line 0 + SWIER0: u1 = 0, + /// Software Interrupt on line 1 + SWIER1: u1 = 0, + /// Software Interrupt on line 2 + SWIER2: u1 = 0, + /// Software Interrupt on line 3 + SWIER3: u1 = 0, + /// Software Interrupt on line 4 + SWIER4: u1 = 0, + /// Software Interrupt on line 5 + SWIER5: u1 = 0, + /// Software Interrupt on line 6 + SWIER6: u1 = 0, + /// Software Interrupt on line 7 + SWIER7: u1 = 0, + /// Software Interrupt on line 8 + SWIER8: u1 = 0, + /// Software Interrupt on line 9 + SWIER9: u1 = 0, + /// Software Interrupt on line 10 + SWIER10: u1 = 0, + /// Software Interrupt on line 11 + SWIER11: u1 = 0, + /// Software Interrupt on line 12 + SWIER12: u1 = 0, + /// Software Interrupt on line 13 + SWIER13: u1 = 0, + /// Software Interrupt on line 14 + SWIER14: u1 = 0, + /// Software Interrupt on line 15 + SWIER15: u1 = 0, + /// Software Interrupt on line 16 + SWIER16: u1 = 0, + /// Software Interrupt on line 17 + SWIER17: u1 = 0, + /// Software Interrupt on line 18 + SWIER18: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -2760,27 +3900,47 @@ pub const EXTI = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Pending register (EXTI_PR) + + /// Pending register (EXTI_PR) pub const PR = mmio(Address + 0x00000014, 32, packed struct { - PR0: u1, // bit offset: 0 desc: Pending bit 0 - PR1: u1, // bit offset: 1 desc: Pending bit 1 - PR2: u1, // bit offset: 2 desc: Pending bit 2 - PR3: u1, // bit offset: 3 desc: Pending bit 3 - PR4: u1, // bit offset: 4 desc: Pending bit 4 - PR5: u1, // bit offset: 5 desc: Pending bit 5 - PR6: u1, // bit offset: 6 desc: Pending bit 6 - PR7: u1, // bit offset: 7 desc: Pending bit 7 - PR8: u1, // bit offset: 8 desc: Pending bit 8 - PR9: u1, // bit offset: 9 desc: Pending bit 9 - PR10: u1, // bit offset: 10 desc: Pending bit 10 - PR11: u1, // bit offset: 11 desc: Pending bit 11 - PR12: u1, // bit offset: 12 desc: Pending bit 12 - PR13: u1, // bit offset: 13 desc: Pending bit 13 - PR14: u1, // bit offset: 14 desc: Pending bit 14 - PR15: u1, // bit offset: 15 desc: Pending bit 15 - PR16: u1, // bit offset: 16 desc: Pending bit 16 - PR17: u1, // bit offset: 17 desc: Pending bit 17 - PR18: u1, // bit offset: 18 desc: Pending bit 18 + /// Pending bit 0 + PR0: u1 = 0, + /// Pending bit 1 + PR1: u1 = 0, + /// Pending bit 2 + PR2: u1 = 0, + /// Pending bit 3 + PR3: u1 = 0, + /// Pending bit 4 + PR4: u1 = 0, + /// Pending bit 5 + PR5: u1 = 0, + /// Pending bit 6 + PR6: u1 = 0, + /// Pending bit 7 + PR7: u1 = 0, + /// Pending bit 8 + PR8: u1 = 0, + /// Pending bit 9 + PR9: u1 = 0, + /// Pending bit 10 + PR10: u1 = 0, + /// Pending bit 11 + PR11: u1 = 0, + /// Pending bit 12 + PR12: u1 = 0, + /// Pending bit 13 + PR13: u1 = 0, + /// Pending bit 14 + PR14: u1 = 0, + /// Pending bit 15 + PR15: u1 = 0, + /// Pending bit 16 + PR16: u1 = 0, + /// Pending bit 17 + PR17: u1 = 0, + /// Pending bit 18 + PR18: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -2796,92 +3956,165 @@ pub const EXTI = extern struct { padding1: u1 = 0, }); }; + +/// DMA controller pub const DMA1 = extern struct { pub const Address: u32 = 0x40020000; - // byte offset: 0 DMA interrupt status register (DMA_ISR) + + /// DMA interrupt status register (DMA_ISR) pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - GIF1: u1, // bit offset: 0 desc: Channel 1 Global interrupt flag - TCIF1: u1, // bit offset: 1 desc: Channel 1 Transfer Complete flag - HTIF1: u1, // bit offset: 2 desc: Channel 1 Half Transfer Complete flag - TEIF1: u1, // bit offset: 3 desc: Channel 1 Transfer Error flag - GIF2: u1, // bit offset: 4 desc: Channel 2 Global interrupt flag - TCIF2: u1, // bit offset: 5 desc: Channel 2 Transfer Complete flag - HTIF2: u1, // bit offset: 6 desc: Channel 2 Half Transfer Complete flag - TEIF2: u1, // bit offset: 7 desc: Channel 2 Transfer Error flag - GIF3: u1, // bit offset: 8 desc: Channel 3 Global interrupt flag - TCIF3: u1, // bit offset: 9 desc: Channel 3 Transfer Complete flag - HTIF3: u1, // bit offset: 10 desc: Channel 3 Half Transfer Complete flag - TEIF3: u1, // bit offset: 11 desc: Channel 3 Transfer Error flag - GIF4: u1, // bit offset: 12 desc: Channel 4 Global interrupt flag - TCIF4: u1, // bit offset: 13 desc: Channel 4 Transfer Complete flag - HTIF4: u1, // bit offset: 14 desc: Channel 4 Half Transfer Complete flag - TEIF4: u1, // bit offset: 15 desc: Channel 4 Transfer Error flag - GIF5: u1, // bit offset: 16 desc: Channel 5 Global interrupt flag - TCIF5: u1, // bit offset: 17 desc: Channel 5 Transfer Complete flag - HTIF5: u1, // bit offset: 18 desc: Channel 5 Half Transfer Complete flag - TEIF5: u1, // bit offset: 19 desc: Channel 5 Transfer Error flag - GIF6: u1, // bit offset: 20 desc: Channel 6 Global interrupt flag - TCIF6: u1, // bit offset: 21 desc: Channel 6 Transfer Complete flag - HTIF6: u1, // bit offset: 22 desc: Channel 6 Half Transfer Complete flag - TEIF6: u1, // bit offset: 23 desc: Channel 6 Transfer Error flag - GIF7: u1, // bit offset: 24 desc: Channel 7 Global interrupt flag - TCIF7: u1, // bit offset: 25 desc: Channel 7 Transfer Complete flag - HTIF7: u1, // bit offset: 26 desc: Channel 7 Half Transfer Complete flag - TEIF7: u1, // bit offset: 27 desc: Channel 7 Transfer Error flag - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 DMA interrupt flag clear register (DMA_IFCR) + /// Channel 1 Global interrupt flag + GIF1: u1 = 0, + /// Channel 1 Transfer Complete flag + TCIF1: u1 = 0, + /// Channel 1 Half Transfer Complete flag + HTIF1: u1 = 0, + /// Channel 1 Transfer Error flag + TEIF1: u1 = 0, + /// Channel 2 Global interrupt flag + GIF2: u1 = 0, + /// Channel 2 Transfer Complete flag + TCIF2: u1 = 0, + /// Channel 2 Half Transfer Complete flag + HTIF2: u1 = 0, + /// Channel 2 Transfer Error flag + TEIF2: u1 = 0, + /// Channel 3 Global interrupt flag + GIF3: u1 = 0, + /// Channel 3 Transfer Complete flag + TCIF3: u1 = 0, + /// Channel 3 Half Transfer Complete flag + HTIF3: u1 = 0, + /// Channel 3 Transfer Error flag + TEIF3: u1 = 0, + /// Channel 4 Global interrupt flag + GIF4: u1 = 0, + /// Channel 4 Transfer Complete flag + TCIF4: u1 = 0, + /// Channel 4 Half Transfer Complete flag + HTIF4: u1 = 0, + /// Channel 4 Transfer Error flag + TEIF4: u1 = 0, + /// Channel 5 Global interrupt flag + GIF5: u1 = 0, + /// Channel 5 Transfer Complete flag + TCIF5: u1 = 0, + /// Channel 5 Half Transfer Complete flag + HTIF5: u1 = 0, + /// Channel 5 Transfer Error flag + TEIF5: u1 = 0, + /// Channel 6 Global interrupt flag + GIF6: u1 = 0, + /// Channel 6 Transfer Complete flag + TCIF6: u1 = 0, + /// Channel 6 Half Transfer Complete flag + HTIF6: u1 = 0, + /// Channel 6 Transfer Error flag + TEIF6: u1 = 0, + /// Channel 7 Global interrupt flag + GIF7: u1 = 0, + /// Channel 7 Transfer Complete flag + TCIF7: u1 = 0, + /// Channel 7 Half Transfer Complete flag + HTIF7: u1 = 0, + /// Channel 7 Transfer Error flag + TEIF7: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// DMA interrupt flag clear register (DMA_IFCR) pub const IFCR = mmio(Address + 0x00000004, 32, packed struct { - CGIF1: u1, // bit offset: 0 desc: Channel 1 Global interrupt clear - CTCIF1: u1, // bit offset: 1 desc: Channel 1 Transfer Complete clear - CHTIF1: u1, // bit offset: 2 desc: Channel 1 Half Transfer clear - CTEIF1: u1, // bit offset: 3 desc: Channel 1 Transfer Error clear - CGIF2: u1, // bit offset: 4 desc: Channel 2 Global interrupt clear - CTCIF2: u1, // bit offset: 5 desc: Channel 2 Transfer Complete clear - CHTIF2: u1, // bit offset: 6 desc: Channel 2 Half Transfer clear - CTEIF2: u1, // bit offset: 7 desc: Channel 2 Transfer Error clear - CGIF3: u1, // bit offset: 8 desc: Channel 3 Global interrupt clear - CTCIF3: u1, // bit offset: 9 desc: Channel 3 Transfer Complete clear - CHTIF3: u1, // bit offset: 10 desc: Channel 3 Half Transfer clear - CTEIF3: u1, // bit offset: 11 desc: Channel 3 Transfer Error clear - CGIF4: u1, // bit offset: 12 desc: Channel 4 Global interrupt clear - CTCIF4: u1, // bit offset: 13 desc: Channel 4 Transfer Complete clear - CHTIF4: u1, // bit offset: 14 desc: Channel 4 Half Transfer clear - CTEIF4: u1, // bit offset: 15 desc: Channel 4 Transfer Error clear - CGIF5: u1, // bit offset: 16 desc: Channel 5 Global interrupt clear - CTCIF5: u1, // bit offset: 17 desc: Channel 5 Transfer Complete clear - CHTIF5: u1, // bit offset: 18 desc: Channel 5 Half Transfer clear - CTEIF5: u1, // bit offset: 19 desc: Channel 5 Transfer Error clear - CGIF6: u1, // bit offset: 20 desc: Channel 6 Global interrupt clear - CTCIF6: u1, // bit offset: 21 desc: Channel 6 Transfer Complete clear - CHTIF6: u1, // bit offset: 22 desc: Channel 6 Half Transfer clear - CTEIF6: u1, // bit offset: 23 desc: Channel 6 Transfer Error clear - CGIF7: u1, // bit offset: 24 desc: Channel 7 Global interrupt clear - CTCIF7: u1, // bit offset: 25 desc: Channel 7 Transfer Complete clear - CHTIF7: u1, // bit offset: 26 desc: Channel 7 Half Transfer clear - CTEIF7: u1, // bit offset: 27 desc: Channel 7 Transfer Error clear - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 DMA channel configuration register (DMA_CCR) + /// Channel 1 Global interrupt clear + CGIF1: u1 = 0, + /// Channel 1 Transfer Complete clear + CTCIF1: u1 = 0, + /// Channel 1 Half Transfer clear + CHTIF1: u1 = 0, + /// Channel 1 Transfer Error clear + CTEIF1: u1 = 0, + /// Channel 2 Global interrupt clear + CGIF2: u1 = 0, + /// Channel 2 Transfer Complete clear + CTCIF2: u1 = 0, + /// Channel 2 Half Transfer clear + CHTIF2: u1 = 0, + /// Channel 2 Transfer Error clear + CTEIF2: u1 = 0, + /// Channel 3 Global interrupt clear + CGIF3: u1 = 0, + /// Channel 3 Transfer Complete clear + CTCIF3: u1 = 0, + /// Channel 3 Half Transfer clear + CHTIF3: u1 = 0, + /// Channel 3 Transfer Error clear + CTEIF3: u1 = 0, + /// Channel 4 Global interrupt clear + CGIF4: u1 = 0, + /// Channel 4 Transfer Complete clear + CTCIF4: u1 = 0, + /// Channel 4 Half Transfer clear + CHTIF4: u1 = 0, + /// Channel 4 Transfer Error clear + CTEIF4: u1 = 0, + /// Channel 5 Global interrupt clear + CGIF5: u1 = 0, + /// Channel 5 Transfer Complete clear + CTCIF5: u1 = 0, + /// Channel 5 Half Transfer clear + CHTIF5: u1 = 0, + /// Channel 5 Transfer Error clear + CTEIF5: u1 = 0, + /// Channel 6 Global interrupt clear + CGIF6: u1 = 0, + /// Channel 6 Transfer Complete clear + CTCIF6: u1 = 0, + /// Channel 6 Half Transfer clear + CHTIF6: u1 = 0, + /// Channel 6 Transfer Error clear + CTEIF6: u1 = 0, + /// Channel 7 Global interrupt clear + CGIF7: u1 = 0, + /// Channel 7 Transfer Complete clear + CTCIF7: u1 = 0, + /// Channel 7 Half Transfer clear + CHTIF7: u1 = 0, + /// Channel 7 Transfer Error clear + CTEIF7: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// DMA channel configuration register (DMA_CCR) pub const CCR1 = mmio(Address + 0x00000008, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -2900,9 +4133,11 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA channel 1 number of data register + + /// DMA channel 1 number of data register pub const CNDTR1 = mmio(Address + 0x0000000c, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2920,28 +4155,45 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 DMA channel 1 peripheral address register + + /// DMA channel 1 peripheral address register pub const CPAR1 = mmio(Address + 0x00000010, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 20 DMA channel 1 memory address register + + /// DMA channel 1 memory address register pub const CMAR1 = mmio(Address + 0x00000014, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 28 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR2 = mmio(Address + 0x0000001c, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -2960,9 +4212,11 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 DMA channel 2 number of data register + + /// DMA channel 2 number of data register pub const CNDTR2 = mmio(Address + 0x00000020, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2980,28 +4234,45 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 DMA channel 2 peripheral address register + + /// DMA channel 2 peripheral address register pub const CPAR2 = mmio(Address + 0x00000024, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 40 DMA channel 2 memory address register + + /// DMA channel 2 memory address register pub const CMAR2 = mmio(Address + 0x00000028, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 48 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR3 = mmio(Address + 0x00000030, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3020,9 +4291,11 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 DMA channel 3 number of data register + + /// DMA channel 3 number of data register pub const CNDTR3 = mmio(Address + 0x00000034, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3040,28 +4313,45 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 DMA channel 3 peripheral address register + + /// DMA channel 3 peripheral address register pub const CPAR3 = mmio(Address + 0x00000038, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 60 DMA channel 3 memory address register + + /// DMA channel 3 memory address register pub const CMAR3 = mmio(Address + 0x0000003c, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 68 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR4 = mmio(Address + 0x00000044, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3080,9 +4370,11 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA channel 4 number of data register + + /// DMA channel 4 number of data register pub const CNDTR4 = mmio(Address + 0x00000048, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3100,28 +4392,45 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA channel 4 peripheral address register + + /// DMA channel 4 peripheral address register pub const CPAR4 = mmio(Address + 0x0000004c, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 80 DMA channel 4 memory address register + + /// DMA channel 4 memory address register pub const CMAR4 = mmio(Address + 0x00000050, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 88 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3140,9 +4449,11 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 92 DMA channel 5 number of data register + + /// DMA channel 5 number of data register pub const CNDTR5 = mmio(Address + 0x0000005c, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3160,28 +4471,45 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 96 DMA channel 5 peripheral address register + + /// DMA channel 5 peripheral address register pub const CPAR5 = mmio(Address + 0x00000060, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 100 DMA channel 5 memory address register + + /// DMA channel 5 memory address register pub const CMAR5 = mmio(Address + 0x00000064, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 108 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR6 = mmio(Address + 0x0000006c, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3200,9 +4528,11 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 112 DMA channel 6 number of data register + + /// DMA channel 6 number of data register pub const CNDTR6 = mmio(Address + 0x00000070, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3220,28 +4550,45 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 116 DMA channel 6 peripheral address register + + /// DMA channel 6 peripheral address register pub const CPAR6 = mmio(Address + 0x00000074, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 120 DMA channel 6 memory address register + + /// DMA channel 6 memory address register pub const CMAR6 = mmio(Address + 0x00000078, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 128 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR7 = mmio(Address + 0x00000080, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3260,9 +4607,11 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 132 DMA channel 7 number of data register + + /// DMA channel 7 number of data register pub const CNDTR7 = mmio(Address + 0x00000084, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3280,101 +4629,178 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 136 DMA channel 7 peripheral address register + + /// DMA channel 7 peripheral address register pub const CPAR7 = mmio(Address + 0x00000088, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 140 DMA channel 7 memory address register + + /// DMA channel 7 memory address register pub const CMAR7 = mmio(Address + 0x0000008c, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); }; + +/// DMA controller pub const DMA2 = extern struct { pub const Address: u32 = 0x40020400; - // byte offset: 0 DMA interrupt status register (DMA_ISR) + + /// DMA interrupt status register (DMA_ISR) pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - GIF1: u1, // bit offset: 0 desc: Channel 1 Global interrupt flag - TCIF1: u1, // bit offset: 1 desc: Channel 1 Transfer Complete flag - HTIF1: u1, // bit offset: 2 desc: Channel 1 Half Transfer Complete flag - TEIF1: u1, // bit offset: 3 desc: Channel 1 Transfer Error flag - GIF2: u1, // bit offset: 4 desc: Channel 2 Global interrupt flag - TCIF2: u1, // bit offset: 5 desc: Channel 2 Transfer Complete flag - HTIF2: u1, // bit offset: 6 desc: Channel 2 Half Transfer Complete flag - TEIF2: u1, // bit offset: 7 desc: Channel 2 Transfer Error flag - GIF3: u1, // bit offset: 8 desc: Channel 3 Global interrupt flag - TCIF3: u1, // bit offset: 9 desc: Channel 3 Transfer Complete flag - HTIF3: u1, // bit offset: 10 desc: Channel 3 Half Transfer Complete flag - TEIF3: u1, // bit offset: 11 desc: Channel 3 Transfer Error flag - GIF4: u1, // bit offset: 12 desc: Channel 4 Global interrupt flag - TCIF4: u1, // bit offset: 13 desc: Channel 4 Transfer Complete flag - HTIF4: u1, // bit offset: 14 desc: Channel 4 Half Transfer Complete flag - TEIF4: u1, // bit offset: 15 desc: Channel 4 Transfer Error flag - GIF5: u1, // bit offset: 16 desc: Channel 5 Global interrupt flag - TCIF5: u1, // bit offset: 17 desc: Channel 5 Transfer Complete flag - HTIF5: u1, // bit offset: 18 desc: Channel 5 Half Transfer Complete flag - TEIF5: u1, // bit offset: 19 desc: Channel 5 Transfer Error flag - GIF6: u1, // bit offset: 20 desc: Channel 6 Global interrupt flag - TCIF6: u1, // bit offset: 21 desc: Channel 6 Transfer Complete flag - HTIF6: u1, // bit offset: 22 desc: Channel 6 Half Transfer Complete flag - TEIF6: u1, // bit offset: 23 desc: Channel 6 Transfer Error flag - GIF7: u1, // bit offset: 24 desc: Channel 7 Global interrupt flag - TCIF7: u1, // bit offset: 25 desc: Channel 7 Transfer Complete flag - HTIF7: u1, // bit offset: 26 desc: Channel 7 Half Transfer Complete flag - TEIF7: u1, // bit offset: 27 desc: Channel 7 Transfer Error flag - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 DMA interrupt flag clear register (DMA_IFCR) + /// Channel 1 Global interrupt flag + GIF1: u1 = 0, + /// Channel 1 Transfer Complete flag + TCIF1: u1 = 0, + /// Channel 1 Half Transfer Complete flag + HTIF1: u1 = 0, + /// Channel 1 Transfer Error flag + TEIF1: u1 = 0, + /// Channel 2 Global interrupt flag + GIF2: u1 = 0, + /// Channel 2 Transfer Complete flag + TCIF2: u1 = 0, + /// Channel 2 Half Transfer Complete flag + HTIF2: u1 = 0, + /// Channel 2 Transfer Error flag + TEIF2: u1 = 0, + /// Channel 3 Global interrupt flag + GIF3: u1 = 0, + /// Channel 3 Transfer Complete flag + TCIF3: u1 = 0, + /// Channel 3 Half Transfer Complete flag + HTIF3: u1 = 0, + /// Channel 3 Transfer Error flag + TEIF3: u1 = 0, + /// Channel 4 Global interrupt flag + GIF4: u1 = 0, + /// Channel 4 Transfer Complete flag + TCIF4: u1 = 0, + /// Channel 4 Half Transfer Complete flag + HTIF4: u1 = 0, + /// Channel 4 Transfer Error flag + TEIF4: u1 = 0, + /// Channel 5 Global interrupt flag + GIF5: u1 = 0, + /// Channel 5 Transfer Complete flag + TCIF5: u1 = 0, + /// Channel 5 Half Transfer Complete flag + HTIF5: u1 = 0, + /// Channel 5 Transfer Error flag + TEIF5: u1 = 0, + /// Channel 6 Global interrupt flag + GIF6: u1 = 0, + /// Channel 6 Transfer Complete flag + TCIF6: u1 = 0, + /// Channel 6 Half Transfer Complete flag + HTIF6: u1 = 0, + /// Channel 6 Transfer Error flag + TEIF6: u1 = 0, + /// Channel 7 Global interrupt flag + GIF7: u1 = 0, + /// Channel 7 Transfer Complete flag + TCIF7: u1 = 0, + /// Channel 7 Half Transfer Complete flag + HTIF7: u1 = 0, + /// Channel 7 Transfer Error flag + TEIF7: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// DMA interrupt flag clear register (DMA_IFCR) pub const IFCR = mmio(Address + 0x00000004, 32, packed struct { - CGIF1: u1, // bit offset: 0 desc: Channel 1 Global interrupt clear - CTCIF1: u1, // bit offset: 1 desc: Channel 1 Transfer Complete clear - CHTIF1: u1, // bit offset: 2 desc: Channel 1 Half Transfer clear - CTEIF1: u1, // bit offset: 3 desc: Channel 1 Transfer Error clear - CGIF2: u1, // bit offset: 4 desc: Channel 2 Global interrupt clear - CTCIF2: u1, // bit offset: 5 desc: Channel 2 Transfer Complete clear - CHTIF2: u1, // bit offset: 6 desc: Channel 2 Half Transfer clear - CTEIF2: u1, // bit offset: 7 desc: Channel 2 Transfer Error clear - CGIF3: u1, // bit offset: 8 desc: Channel 3 Global interrupt clear - CTCIF3: u1, // bit offset: 9 desc: Channel 3 Transfer Complete clear - CHTIF3: u1, // bit offset: 10 desc: Channel 3 Half Transfer clear - CTEIF3: u1, // bit offset: 11 desc: Channel 3 Transfer Error clear - CGIF4: u1, // bit offset: 12 desc: Channel 4 Global interrupt clear - CTCIF4: u1, // bit offset: 13 desc: Channel 4 Transfer Complete clear - CHTIF4: u1, // bit offset: 14 desc: Channel 4 Half Transfer clear - CTEIF4: u1, // bit offset: 15 desc: Channel 4 Transfer Error clear - CGIF5: u1, // bit offset: 16 desc: Channel 5 Global interrupt clear - CTCIF5: u1, // bit offset: 17 desc: Channel 5 Transfer Complete clear - CHTIF5: u1, // bit offset: 18 desc: Channel 5 Half Transfer clear - CTEIF5: u1, // bit offset: 19 desc: Channel 5 Transfer Error clear - CGIF6: u1, // bit offset: 20 desc: Channel 6 Global interrupt clear - CTCIF6: u1, // bit offset: 21 desc: Channel 6 Transfer Complete clear - CHTIF6: u1, // bit offset: 22 desc: Channel 6 Half Transfer clear - CTEIF6: u1, // bit offset: 23 desc: Channel 6 Transfer Error clear - CGIF7: u1, // bit offset: 24 desc: Channel 7 Global interrupt clear - CTCIF7: u1, // bit offset: 25 desc: Channel 7 Transfer Complete clear - CHTIF7: u1, // bit offset: 26 desc: Channel 7 Half Transfer clear - CTEIF7: u1, // bit offset: 27 desc: Channel 7 Transfer Error clear - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 DMA channel configuration register (DMA_CCR) + /// Channel 1 Global interrupt clear + CGIF1: u1 = 0, + /// Channel 1 Transfer Complete clear + CTCIF1: u1 = 0, + /// Channel 1 Half Transfer clear + CHTIF1: u1 = 0, + /// Channel 1 Transfer Error clear + CTEIF1: u1 = 0, + /// Channel 2 Global interrupt clear + CGIF2: u1 = 0, + /// Channel 2 Transfer Complete clear + CTCIF2: u1 = 0, + /// Channel 2 Half Transfer clear + CHTIF2: u1 = 0, + /// Channel 2 Transfer Error clear + CTEIF2: u1 = 0, + /// Channel 3 Global interrupt clear + CGIF3: u1 = 0, + /// Channel 3 Transfer Complete clear + CTCIF3: u1 = 0, + /// Channel 3 Half Transfer clear + CHTIF3: u1 = 0, + /// Channel 3 Transfer Error clear + CTEIF3: u1 = 0, + /// Channel 4 Global interrupt clear + CGIF4: u1 = 0, + /// Channel 4 Transfer Complete clear + CTCIF4: u1 = 0, + /// Channel 4 Half Transfer clear + CHTIF4: u1 = 0, + /// Channel 4 Transfer Error clear + CTEIF4: u1 = 0, + /// Channel 5 Global interrupt clear + CGIF5: u1 = 0, + /// Channel 5 Transfer Complete clear + CTCIF5: u1 = 0, + /// Channel 5 Half Transfer clear + CHTIF5: u1 = 0, + /// Channel 5 Transfer Error clear + CTEIF5: u1 = 0, + /// Channel 6 Global interrupt clear + CGIF6: u1 = 0, + /// Channel 6 Transfer Complete clear + CTCIF6: u1 = 0, + /// Channel 6 Half Transfer clear + CHTIF6: u1 = 0, + /// Channel 6 Transfer Error clear + CTEIF6: u1 = 0, + /// Channel 7 Global interrupt clear + CGIF7: u1 = 0, + /// Channel 7 Transfer Complete clear + CTCIF7: u1 = 0, + /// Channel 7 Half Transfer clear + CHTIF7: u1 = 0, + /// Channel 7 Transfer Error clear + CTEIF7: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// DMA channel configuration register (DMA_CCR) pub const CCR1 = mmio(Address + 0x00000008, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3393,9 +4819,11 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA channel 1 number of data register + + /// DMA channel 1 number of data register pub const CNDTR1 = mmio(Address + 0x0000000c, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3413,28 +4841,45 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 DMA channel 1 peripheral address register + + /// DMA channel 1 peripheral address register pub const CPAR1 = mmio(Address + 0x00000010, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 20 DMA channel 1 memory address register + + /// DMA channel 1 memory address register pub const CMAR1 = mmio(Address + 0x00000014, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 28 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR2 = mmio(Address + 0x0000001c, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3453,9 +4898,11 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 DMA channel 2 number of data register + + /// DMA channel 2 number of data register pub const CNDTR2 = mmio(Address + 0x00000020, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3473,28 +4920,45 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 DMA channel 2 peripheral address register + + /// DMA channel 2 peripheral address register pub const CPAR2 = mmio(Address + 0x00000024, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 40 DMA channel 2 memory address register + + /// DMA channel 2 memory address register pub const CMAR2 = mmio(Address + 0x00000028, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 48 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR3 = mmio(Address + 0x00000030, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3513,9 +4977,11 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 DMA channel 3 number of data register + + /// DMA channel 3 number of data register pub const CNDTR3 = mmio(Address + 0x00000034, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3533,28 +4999,45 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 DMA channel 3 peripheral address register + + /// DMA channel 3 peripheral address register pub const CPAR3 = mmio(Address + 0x00000038, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 60 DMA channel 3 memory address register + + /// DMA channel 3 memory address register pub const CMAR3 = mmio(Address + 0x0000003c, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 68 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR4 = mmio(Address + 0x00000044, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3573,9 +5056,11 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA channel 4 number of data register + + /// DMA channel 4 number of data register pub const CNDTR4 = mmio(Address + 0x00000048, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3593,28 +5078,45 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA channel 4 peripheral address register + + /// DMA channel 4 peripheral address register pub const CPAR4 = mmio(Address + 0x0000004c, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 80 DMA channel 4 memory address register + + /// DMA channel 4 memory address register pub const CMAR4 = mmio(Address + 0x00000050, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 88 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3633,9 +5135,11 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 92 DMA channel 5 number of data register + + /// DMA channel 5 number of data register pub const CNDTR5 = mmio(Address + 0x0000005c, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3653,28 +5157,45 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 96 DMA channel 5 peripheral address register + + /// DMA channel 5 peripheral address register pub const CPAR5 = mmio(Address + 0x00000060, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 100 DMA channel 5 memory address register + + /// DMA channel 5 memory address register pub const CMAR5 = mmio(Address + 0x00000064, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 108 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR6 = mmio(Address + 0x0000006c, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3693,9 +5214,11 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 112 DMA channel 6 number of data register + + /// DMA channel 6 number of data register pub const CNDTR6 = mmio(Address + 0x00000070, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3713,28 +5236,45 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 116 DMA channel 6 peripheral address register + + /// DMA channel 6 peripheral address register pub const CPAR6 = mmio(Address + 0x00000074, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 120 DMA channel 6 memory address register + + /// DMA channel 6 memory address register pub const CMAR6 = mmio(Address + 0x00000078, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 128 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR7 = mmio(Address + 0x00000080, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3753,9 +5293,11 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 132 DMA channel 7 number of data register + + /// DMA channel 7 number of data register pub const CNDTR7 = mmio(Address + 0x00000084, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3773,20 +5315,26 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 136 DMA channel 7 peripheral address register + + /// DMA channel 7 peripheral address register pub const CPAR7 = mmio(Address + 0x00000088, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 140 DMA channel 7 memory address register + + /// DMA channel 7 memory address register pub const CMAR7 = mmio(Address + 0x0000008c, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); }; + +/// Secure digital input/output interface pub const SDIO = extern struct { pub const Address: u32 = 0x40018000; - // byte offset: 0 Bits 1:0 = PWRCTRL: Power supply control bits + + /// Bits 1:0 = PWRCTRL: Power supply control bits pub const POWER = mmio(Address + 0x00000000, 32, packed struct { - PWRCTRL: u2, // bit offset: 0 desc: PWRCTRL padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -3818,15 +5366,23 @@ pub const SDIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 SDI clock control register (SDIO_CLKCR) + + /// SDI clock control register (SDIO_CLKCR) pub const CLKCR = mmio(Address + 0x00000004, 32, packed struct { - CLKDIV: u8, // bit offset: 0 desc: Clock divide factor - CLKEN: u1, // bit offset: 8 desc: Clock enable bit - PWRSAV: u1, // bit offset: 9 desc: Power saving configuration bit - BYPASS: u1, // bit offset: 10 desc: Clock divider bypass enable bit - WIDBUS: u2, // bit offset: 11 desc: Wide bus mode enable bit - NEGEDGE: u1, // bit offset: 13 desc: SDIO_CK dephasing selection bit - HWFC_EN: u1, // bit offset: 14 desc: HW Flow Control enable + /// Clock divide factor + CLKDIV: u8 = 0, + /// Clock enable bit + CLKEN: u1 = 0, + /// Power saving configuration bit + PWRSAV: u1 = 0, + /// Clock divider bypass enable bit + BYPASS: u1 = 0, + /// Wide bus mode enable bit + WIDBUS: u2 = 0, + /// SDIO_CK dephasing selection bit + NEGEDGE: u1 = 0, + /// HW Flow Control enable + HWFC_EN: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3845,21 +5401,15 @@ pub const SDIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Bits 31:0 = : Command argument + + /// Bits 31:0 = : Command argument pub const ARG = mmio(Address + 0x00000008, 32, packed struct { - CMDARG: u32, // bit offset: 0 desc: Command argument + /// Command argument + CMDARG: u32 = 0, }); - // byte offset: 12 SDIO command register (SDIO_CMD) + + /// SDIO command register (SDIO_CMD) pub const CMD = mmio(Address + 0x0000000c, 32, packed struct { - CMDINDEX: u6, // bit offset: 0 desc: CMDINDEX - WAITRESP: u2, // bit offset: 6 desc: WAITRESP - WAITINT: u1, // bit offset: 8 desc: WAITINT - WAITPEND: u1, // bit offset: 9 desc: WAITPEND - CPSMEN: u1, // bit offset: 10 desc: CPSMEN - SDIOSuspend: u1, // bit offset: 11 desc: SDIOSuspend - ENCMDcompl: u1, // bit offset: 12 desc: ENCMDcompl - nIEN: u1, // bit offset: 13 desc: nIEN - CE_ATACMD: u1, // bit offset: 14 desc: CE_ATACMD padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3878,9 +5428,9 @@ pub const SDIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 SDIO command register + + /// SDIO command register pub const RESPCMD = mmio(Address + 0x00000010, 32, packed struct { - RESPCMD: u6, // bit offset: 0 desc: RESPCMD padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -3908,29 +5458,29 @@ pub const SDIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Bits 31:0 = CARDSTATUS1 - pub const RESPI1 = mmio(Address + 0x00000014, 32, packed struct { - CARDSTATUS1: u32, // bit offset: 0 desc: CARDSTATUS1 - }); - // byte offset: 24 Bits 31:0 = CARDSTATUS2 - pub const RESP2 = mmio(Address + 0x00000018, 32, packed struct { - CARDSTATUS2: u32, // bit offset: 0 desc: CARDSTATUS2 - }); - // byte offset: 28 Bits 31:0 = CARDSTATUS3 - pub const RESP3 = mmio(Address + 0x0000001c, 32, packed struct { - CARDSTATUS3: u32, // bit offset: 0 desc: CARDSTATUS3 - }); - // byte offset: 32 Bits 31:0 = CARDSTATUS4 - pub const RESP4 = mmio(Address + 0x00000020, 32, packed struct { - CARDSTATUS4: u32, // bit offset: 0 desc: CARDSTATUS4 - }); - // byte offset: 36 Bits 31:0 = DATATIME: Data timeout period + + /// Bits 31:0 = CARDSTATUS1 + pub const RESPI1 = mmio(Address + 0x00000014, 32, packed struct {}); + + /// Bits 31:0 = CARDSTATUS2 + pub const RESP2 = mmio(Address + 0x00000018, 32, packed struct {}); + + /// Bits 31:0 = CARDSTATUS3 + pub const RESP3 = mmio(Address + 0x0000001c, 32, packed struct {}); + + /// Bits 31:0 = CARDSTATUS4 + pub const RESP4 = mmio(Address + 0x00000020, 32, packed struct {}); + + /// Bits 31:0 = DATATIME: Data timeout period pub const DTIMER = mmio(Address + 0x00000024, 32, packed struct { - DATATIME: u32, // bit offset: 0 desc: Data timeout period + /// Data timeout period + DATATIME: u32 = 0, }); - // byte offset: 40 Bits 24:0 = DATALENGTH: Data length value + + /// Bits 24:0 = DATALENGTH: Data length value pub const DLEN = mmio(Address + 0x00000028, 32, packed struct { - DATALENGTH: u25, // bit offset: 0 desc: Data length value + /// Data length value + DATALENGTH: u25 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -3939,17 +5489,9 @@ pub const SDIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 SDIO data control register (SDIO_DCTRL) + + /// SDIO data control register (SDIO_DCTRL) pub const DCTRL = mmio(Address + 0x0000002c, 32, packed struct { - DTEN: u1, // bit offset: 0 desc: DTEN - DTDIR: u1, // bit offset: 1 desc: DTDIR - DTMODE: u1, // bit offset: 2 desc: DTMODE - DMAEN: u1, // bit offset: 3 desc: DMAEN - DBLOCKSIZE: u4, // bit offset: 4 desc: DBLOCKSIZE - PWSTART: u1, // bit offset: 8 desc: PWSTART - PWSTOP: u1, // bit offset: 9 desc: PWSTOP - RWMOD: u1, // bit offset: 10 desc: RWMOD - SDIOEN: u1, // bit offset: 11 desc: SDIOEN padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -3971,9 +5513,11 @@ pub const SDIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 Bits 24:0 = DATACOUNT: Data count value + + /// Bits 24:0 = DATACOUNT: Data count value pub const DCOUNT = mmio(Address + 0x00000030, 32, packed struct { - DATACOUNT: u25, // bit offset: 0 desc: Data count value + /// Data count value + DATACOUNT: u25 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -3982,32 +5526,9 @@ pub const SDIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 SDIO status register (SDIO_STA) + + /// SDIO status register (SDIO_STA) pub const STA = mmio(Address + 0x00000034, 32, packed struct { - CCRCFAIL: u1, // bit offset: 0 desc: CCRCFAIL - DCRCFAIL: u1, // bit offset: 1 desc: DCRCFAIL - CTIMEOUT: u1, // bit offset: 2 desc: CTIMEOUT - DTIMEOUT: u1, // bit offset: 3 desc: DTIMEOUT - TXUNDERR: u1, // bit offset: 4 desc: TXUNDERR - RXOVERR: u1, // bit offset: 5 desc: RXOVERR - CMDREND: u1, // bit offset: 6 desc: CMDREND - CMDSENT: u1, // bit offset: 7 desc: CMDSENT - DATAEND: u1, // bit offset: 8 desc: DATAEND - STBITERR: u1, // bit offset: 9 desc: STBITERR - DBCKEND: u1, // bit offset: 10 desc: DBCKEND - CMDACT: u1, // bit offset: 11 desc: CMDACT - TXACT: u1, // bit offset: 12 desc: TXACT - RXACT: u1, // bit offset: 13 desc: RXACT - TXFIFOHE: u1, // bit offset: 14 desc: TXFIFOHE - RXFIFOHF: u1, // bit offset: 15 desc: RXFIFOHF - TXFIFOF: u1, // bit offset: 16 desc: TXFIFOF - RXFIFOF: u1, // bit offset: 17 desc: RXFIFOF - TXFIFOE: u1, // bit offset: 18 desc: TXFIFOE - RXFIFOE: u1, // bit offset: 19 desc: RXFIFOE - TXDAVL: u1, // bit offset: 20 desc: TXDAVL - RXDAVL: u1, // bit offset: 21 desc: RXDAVL - SDIOIT: u1, // bit offset: 22 desc: SDIOIT - CEATAEND: u1, // bit offset: 23 desc: CEATAEND padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -4017,19 +5538,9 @@ pub const SDIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 SDIO interrupt clear register (SDIO_ICR) + + /// SDIO interrupt clear register (SDIO_ICR) pub const ICR = mmio(Address + 0x00000038, 32, packed struct { - CCRCFAILC: u1, // bit offset: 0 desc: CCRCFAILC - DCRCFAILC: u1, // bit offset: 1 desc: DCRCFAILC - CTIMEOUTC: u1, // bit offset: 2 desc: CTIMEOUTC - DTIMEOUTC: u1, // bit offset: 3 desc: DTIMEOUTC - TXUNDERRC: u1, // bit offset: 4 desc: TXUNDERRC - RXOVERRC: u1, // bit offset: 5 desc: RXOVERRC - CMDRENDC: u1, // bit offset: 6 desc: CMDRENDC - CMDSENTC: u1, // bit offset: 7 desc: CMDSENTC - DATAENDC: u1, // bit offset: 8 desc: DATAENDC - STBITERRC: u1, // bit offset: 9 desc: STBITERRC - DBCKENDC: u1, // bit offset: 10 desc: DBCKENDC reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -4041,8 +5552,6 @@ pub const SDIO = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - SDIOITC: u1, // bit offset: 22 desc: SDIOITC - CEATAENDC: u1, // bit offset: 23 desc: CEATAENDC padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -4052,32 +5561,9 @@ pub const SDIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 SDIO mask register (SDIO_MASK) + + /// SDIO mask register (SDIO_MASK) pub const MASK = mmio(Address + 0x0000003c, 32, packed struct { - CCRCFAILIE: u1, // bit offset: 0 desc: CCRCFAILIE - DCRCFAILIE: u1, // bit offset: 1 desc: DCRCFAILIE - CTIMEOUTIE: u1, // bit offset: 2 desc: CTIMEOUTIE - DTIMEOUTIE: u1, // bit offset: 3 desc: DTIMEOUTIE - TXUNDERRIE: u1, // bit offset: 4 desc: TXUNDERRIE - RXOVERRIE: u1, // bit offset: 5 desc: RXOVERRIE - CMDRENDIE: u1, // bit offset: 6 desc: CMDRENDIE - CMDSENTIE: u1, // bit offset: 7 desc: CMDSENTIE - DATAENDIE: u1, // bit offset: 8 desc: DATAENDIE - STBITERRIE: u1, // bit offset: 9 desc: STBITERRIE - DBACKENDIE: u1, // bit offset: 10 desc: DBACKENDIE - CMDACTIE: u1, // bit offset: 11 desc: CMDACTIE - TXACTIE: u1, // bit offset: 12 desc: TXACTIE - RXACTIE: u1, // bit offset: 13 desc: RXACTIE - TXFIFOHEIE: u1, // bit offset: 14 desc: TXFIFOHEIE - RXFIFOHFIE: u1, // bit offset: 15 desc: RXFIFOHFIE - TXFIFOFIE: u1, // bit offset: 16 desc: TXFIFOFIE - RXFIFOFIE: u1, // bit offset: 17 desc: RXFIFOFIE - TXFIFOEIE: u1, // bit offset: 18 desc: TXFIFOEIE - RXFIFOEIE: u1, // bit offset: 19 desc: RXFIFOEIE - TXDAVLIE: u1, // bit offset: 20 desc: TXDAVLIE - RXDAVLIE: u1, // bit offset: 21 desc: RXDAVLIE - SDIOITIE: u1, // bit offset: 22 desc: SDIOITIE - CEATENDIE: u1, // bit offset: 23 desc: CEATENDIE padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -4087,9 +5573,10 @@ pub const SDIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 Bits 23:0 = FIFOCOUNT: Remaining number of words to be written to or read from the FIFO + + /// Bits 23:0 = FIFOCOUNT: Remaining number of words to be written to or read + /// from the FIFO pub const FIFOCNT = mmio(Address + 0x00000048, 32, packed struct { - FIF0COUNT: u24, // bit offset: 0 desc: FIF0COUNT padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -4099,18 +5586,23 @@ pub const SDIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 128 bits 31:0 = FIFOData: Receive and transmit FIFO data - pub const FIFO = mmio(Address + 0x00000080, 32, packed struct { - FIFOData: u32, // bit offset: 0 desc: FIFOData - }); + + /// bits 31:0 = FIFOData: Receive and transmit FIFO data + pub const FIFO = mmio(Address + 0x00000080, 32, packed struct {}); }; + +/// Real time clock pub const RTC = extern struct { pub const Address: u32 = 0x40002800; - // byte offset: 0 RTC Control Register High + + /// RTC Control Register High pub const CRH = mmio(Address + 0x00000000, 32, packed struct { - SECIE: u1, // bit offset: 0 desc: Second interrupt Enable - ALRIE: u1, // bit offset: 1 desc: Alarm interrupt Enable - OWIE: u1, // bit offset: 2 desc: Overflow interrupt Enable + /// Second interrupt Enable + SECIE: u1 = 0, + /// Alarm interrupt Enable + ALRIE: u1 = 0, + /// Overflow interrupt Enable + OWIE: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, @@ -4141,14 +5633,21 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 RTC Control Register Low + + /// RTC Control Register Low pub const CRL = mmio(Address + 0x00000004, 32, packed struct { - SECF: u1, // bit offset: 0 desc: Second Flag - ALRF: u1, // bit offset: 1 desc: Alarm Flag - OWF: u1, // bit offset: 2 desc: Overflow Flag - RSF: u1, // bit offset: 3 desc: Registers Synchronized Flag - CNF: u1, // bit offset: 4 desc: Configuration Flag - RTOFF: u1, // bit offset: 5 desc: RTC operation OFF + /// Second Flag + SECF: u1 = 0, + /// Alarm Flag + ALRF: u1 = 0, + /// Overflow Flag + OWF: u1 = 0, + /// Registers Synchronized Flag + RSF: u1 = 0, + /// Configuration Flag + CNF: u1 = 0, + /// RTC operation OFF + RTOFF: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -4176,9 +5675,11 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 RTC Prescaler Load Register High + + /// RTC Prescaler Load Register High pub const PRLH = mmio(Address + 0x00000008, 32, packed struct { - PRLH: u4, // bit offset: 0 desc: RTC Prescaler Load Register High + /// RTC Prescaler Load Register High + PRLH: u4 = 0, padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -4208,9 +5709,11 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 RTC Prescaler Load Register Low + + /// RTC Prescaler Load Register Low pub const PRLL = mmio(Address + 0x0000000c, 32, packed struct { - PRLL: u16, // bit offset: 0 desc: RTC Prescaler Divider Register Low + /// RTC Prescaler Divider Register Low + PRLL: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4228,9 +5731,11 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 RTC Prescaler Divider Register High + + /// RTC Prescaler Divider Register High pub const DIVH = mmio(Address + 0x00000010, 32, packed struct { - DIVH: u4, // bit offset: 0 desc: RTC prescaler divider register high + /// RTC prescaler divider register high + DIVH: u4 = 0, padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -4260,9 +5765,11 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 RTC Prescaler Divider Register Low + + /// RTC Prescaler Divider Register Low pub const DIVL = mmio(Address + 0x00000014, 32, packed struct { - DIVL: u16, // bit offset: 0 desc: RTC prescaler divider register Low + /// RTC prescaler divider register Low + DIVL: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4280,9 +5787,11 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 RTC Counter Register High + + /// RTC Counter Register High pub const CNTH = mmio(Address + 0x00000018, 32, packed struct { - CNTH: u16, // bit offset: 0 desc: RTC counter register high + /// RTC counter register high + CNTH: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4300,9 +5809,11 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 RTC Counter Register Low + + /// RTC Counter Register Low pub const CNTL = mmio(Address + 0x0000001c, 32, packed struct { - CNTL: u16, // bit offset: 0 desc: RTC counter register Low + /// RTC counter register Low + CNTL: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4320,9 +5831,11 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 RTC Alarm Register High + + /// RTC Alarm Register High pub const ALRH = mmio(Address + 0x00000020, 32, packed struct { - ALRH: u16, // bit offset: 0 desc: RTC alarm register high + /// RTC alarm register high + ALRH: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4340,9 +5853,11 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 RTC Alarm Register Low + + /// RTC Alarm Register Low pub const ALRL = mmio(Address + 0x00000024, 32, packed struct { - ALRL: u16, // bit offset: 0 desc: RTC alarm register low + /// RTC alarm register low + ALRL: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4361,11 +5876,15 @@ pub const RTC = extern struct { padding1: u1 = 0, }); }; + +/// Backup registers pub const BKP = extern struct { pub const Address: u32 = 0x40006c04; - // byte offset: 0 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR1 = mmio(Address + 0x00000000, 32, packed struct { - D1: u16, // bit offset: 0 desc: Backup data + /// Backup data + D1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4383,9 +5902,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR2 = mmio(Address + 0x00000004, 32, packed struct { - D2: u16, // bit offset: 0 desc: Backup data + /// Backup data + D2: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4403,9 +5924,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR3 = mmio(Address + 0x00000008, 32, packed struct { - D3: u16, // bit offset: 0 desc: Backup data + /// Backup data + D3: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4423,9 +5946,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR4 = mmio(Address + 0x0000000c, 32, packed struct { - D4: u16, // bit offset: 0 desc: Backup data + /// Backup data + D4: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4443,9 +5968,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR5 = mmio(Address + 0x00000010, 32, packed struct { - D5: u16, // bit offset: 0 desc: Backup data + /// Backup data + D5: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4463,9 +5990,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR6 = mmio(Address + 0x00000014, 32, packed struct { - D6: u16, // bit offset: 0 desc: Backup data + /// Backup data + D6: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4483,9 +6012,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR7 = mmio(Address + 0x00000018, 32, packed struct { - D7: u16, // bit offset: 0 desc: Backup data + /// Backup data + D7: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4503,9 +6034,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR8 = mmio(Address + 0x0000001c, 32, packed struct { - D8: u16, // bit offset: 0 desc: Backup data + /// Backup data + D8: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4523,9 +6056,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR9 = mmio(Address + 0x00000020, 32, packed struct { - D9: u16, // bit offset: 0 desc: Backup data + /// Backup data + D9: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4543,9 +6078,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR10 = mmio(Address + 0x00000024, 32, packed struct { - D10: u16, // bit offset: 0 desc: Backup data + /// Backup data + D10: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4563,12 +6100,17 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 RTC clock calibration register (BKP_RTCCR) + + /// RTC clock calibration register (BKP_RTCCR) pub const RTCCR = mmio(Address + 0x00000028, 32, packed struct { - CAL: u7, // bit offset: 0 desc: Calibration value - CCO: u1, // bit offset: 7 desc: Calibration Clock Output - ASOE: u1, // bit offset: 8 desc: Alarm or second output enable - ASOS: u1, // bit offset: 9 desc: Alarm or second output selection + /// Calibration value + CAL: u7 = 0, + /// Calibration Clock Output + CCO: u1 = 0, + /// Alarm or second output enable + ASOE: u1 = 0, + /// Alarm or second output selection + ASOS: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -4592,10 +6134,13 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 Backup control register (BKP_CR) + + /// Backup control register (BKP_CR) pub const CR = mmio(Address + 0x0000002c, 32, packed struct { - TPE: u1, // bit offset: 0 desc: Tamper pin enable - TPAL: u1, // bit offset: 1 desc: Tamper pin active level + /// Tamper pin enable + TPE: u1 = 0, + /// Tamper pin active level + TPAL: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -4627,18 +6172,24 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 BKP_CSR control/status register (BKP_CSR) + + /// BKP_CSR control/status register (BKP_CSR) pub const CSR = mmio(Address + 0x00000030, 32, packed struct { - CTE: u1, // bit offset: 0 desc: Clear Tamper event - CTI: u1, // bit offset: 1 desc: Clear Tamper Interrupt - TPIE: u1, // bit offset: 2 desc: Tamper Pin interrupt enable + /// Clear Tamper event + CTE: u1 = 0, + /// Clear Tamper Interrupt + CTI: u1 = 0, + /// Tamper Pin interrupt enable + TPIE: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TEF: u1, // bit offset: 8 desc: Tamper Event Flag - TIF: u1, // bit offset: 9 desc: Tamper Interrupt Flag + /// Tamper Event Flag + TEF: u1 = 0, + /// Tamper Interrupt Flag + TIF: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -4662,9 +6213,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR11 = mmio(Address + 0x0000003c, 32, packed struct { - DR11: u16, // bit offset: 0 desc: Backup data + /// Backup data + DR11: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4682,9 +6235,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR12 = mmio(Address + 0x00000040, 32, packed struct { - DR12: u16, // bit offset: 0 desc: Backup data + /// Backup data + DR12: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4702,9 +6257,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR13 = mmio(Address + 0x00000044, 32, packed struct { - DR13: u16, // bit offset: 0 desc: Backup data + /// Backup data + DR13: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4722,9 +6279,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR14 = mmio(Address + 0x00000048, 32, packed struct { - D14: u16, // bit offset: 0 desc: Backup data + /// Backup data + D14: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4742,9 +6301,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR15 = mmio(Address + 0x0000004c, 32, packed struct { - D15: u16, // bit offset: 0 desc: Backup data + /// Backup data + D15: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4762,9 +6323,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 80 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR16 = mmio(Address + 0x00000050, 32, packed struct { - D16: u16, // bit offset: 0 desc: Backup data + /// Backup data + D16: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4782,9 +6345,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 84 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR17 = mmio(Address + 0x00000054, 32, packed struct { - D17: u16, // bit offset: 0 desc: Backup data + /// Backup data + D17: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4802,9 +6367,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 88 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR18 = mmio(Address + 0x00000058, 32, packed struct { - D18: u16, // bit offset: 0 desc: Backup data + /// Backup data + D18: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4822,9 +6389,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 92 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR19 = mmio(Address + 0x0000005c, 32, packed struct { - D19: u16, // bit offset: 0 desc: Backup data + /// Backup data + D19: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4842,9 +6411,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 96 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR20 = mmio(Address + 0x00000060, 32, packed struct { - D20: u16, // bit offset: 0 desc: Backup data + /// Backup data + D20: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4862,9 +6433,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 100 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR21 = mmio(Address + 0x00000064, 32, packed struct { - D21: u16, // bit offset: 0 desc: Backup data + /// Backup data + D21: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4882,9 +6455,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 104 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR22 = mmio(Address + 0x00000068, 32, packed struct { - D22: u16, // bit offset: 0 desc: Backup data + /// Backup data + D22: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4902,9 +6477,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 108 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR23 = mmio(Address + 0x0000006c, 32, packed struct { - D23: u16, // bit offset: 0 desc: Backup data + /// Backup data + D23: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4922,9 +6499,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 112 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR24 = mmio(Address + 0x00000070, 32, packed struct { - D24: u16, // bit offset: 0 desc: Backup data + /// Backup data + D24: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4942,9 +6521,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 116 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR25 = mmio(Address + 0x00000074, 32, packed struct { - D25: u16, // bit offset: 0 desc: Backup data + /// Backup data + D25: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4962,9 +6543,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 120 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR26 = mmio(Address + 0x00000078, 32, packed struct { - D26: u16, // bit offset: 0 desc: Backup data + /// Backup data + D26: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4982,9 +6565,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 124 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR27 = mmio(Address + 0x0000007c, 32, packed struct { - D27: u16, // bit offset: 0 desc: Backup data + /// Backup data + D27: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5002,9 +6587,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 128 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR28 = mmio(Address + 0x00000080, 32, packed struct { - D28: u16, // bit offset: 0 desc: Backup data + /// Backup data + D28: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5022,9 +6609,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 132 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR29 = mmio(Address + 0x00000084, 32, packed struct { - D29: u16, // bit offset: 0 desc: Backup data + /// Backup data + D29: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5042,9 +6631,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 136 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR30 = mmio(Address + 0x00000088, 32, packed struct { - D30: u16, // bit offset: 0 desc: Backup data + /// Backup data + D30: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5062,9 +6653,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 140 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR31 = mmio(Address + 0x0000008c, 32, packed struct { - D31: u16, // bit offset: 0 desc: Backup data + /// Backup data + D31: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5082,9 +6675,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 144 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR32 = mmio(Address + 0x00000090, 32, packed struct { - D32: u16, // bit offset: 0 desc: Backup data + /// Backup data + D32: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5102,9 +6697,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 148 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR33 = mmio(Address + 0x00000094, 32, packed struct { - D33: u16, // bit offset: 0 desc: Backup data + /// Backup data + D33: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5122,9 +6719,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 152 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR34 = mmio(Address + 0x00000098, 32, packed struct { - D34: u16, // bit offset: 0 desc: Backup data + /// Backup data + D34: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5142,9 +6741,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 156 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR35 = mmio(Address + 0x0000009c, 32, packed struct { - D35: u16, // bit offset: 0 desc: Backup data + /// Backup data + D35: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5162,9 +6763,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 160 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR36 = mmio(Address + 0x000000a0, 32, packed struct { - D36: u16, // bit offset: 0 desc: Backup data + /// Backup data + D36: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5182,9 +6785,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 164 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR37 = mmio(Address + 0x000000a4, 32, packed struct { - D37: u16, // bit offset: 0 desc: Backup data + /// Backup data + D37: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5202,9 +6807,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 168 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR38 = mmio(Address + 0x000000a8, 32, packed struct { - D38: u16, // bit offset: 0 desc: Backup data + /// Backup data + D38: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5222,9 +6829,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 172 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR39 = mmio(Address + 0x000000ac, 32, packed struct { - D39: u16, // bit offset: 0 desc: Backup data + /// Backup data + D39: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5242,9 +6851,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 176 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR40 = mmio(Address + 0x000000b0, 32, packed struct { - D40: u16, // bit offset: 0 desc: Backup data + /// Backup data + D40: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5262,9 +6873,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 180 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR41 = mmio(Address + 0x000000b4, 32, packed struct { - D41: u16, // bit offset: 0 desc: Backup data + /// Backup data + D41: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5282,9 +6895,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 184 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR42 = mmio(Address + 0x000000b8, 32, packed struct { - D42: u16, // bit offset: 0 desc: Backup data + /// Backup data + D42: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5303,11 +6918,15 @@ pub const BKP = extern struct { padding1: u1 = 0, }); }; + +/// Independent watchdog pub const IWDG = extern struct { pub const Address: u32 = 0x40003000; - // byte offset: 0 Key register (IWDG_KR) + + /// Key register (IWDG_KR) pub const KR = mmio(Address + 0x00000000, 32, packed struct { - KEY: u16, // bit offset: 0 desc: Key value + /// Key value + KEY: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5325,9 +6944,11 @@ pub const IWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Prescaler register (IWDG_PR) + + /// Prescaler register (IWDG_PR) pub const PR = mmio(Address + 0x00000004, 32, packed struct { - PR: u3, // bit offset: 0 desc: Prescaler divider + /// Prescaler divider + PR: u3 = 0, padding29: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, @@ -5358,9 +6979,11 @@ pub const IWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Reload register (IWDG_RLR) + + /// Reload register (IWDG_RLR) pub const RLR = mmio(Address + 0x00000008, 32, packed struct { - RL: u12, // bit offset: 0 desc: Watchdog counter reload value + /// Watchdog counter reload value + RL: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -5382,10 +7005,13 @@ pub const IWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Status register (IWDG_SR) + + /// Status register (IWDG_SR) pub const SR = mmio(Address + 0x0000000c, 32, packed struct { - PVU: u1, // bit offset: 0 desc: Watchdog prescaler value update - RVU: u1, // bit offset: 1 desc: Watchdog counter reload value update + /// Watchdog prescaler value update + PVU: u1 = 0, + /// Watchdog counter reload value update + RVU: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -5418,12 +7044,17 @@ pub const IWDG = extern struct { padding1: u1 = 0, }); }; + +/// Window watchdog pub const WWDG = extern struct { pub const Address: u32 = 0x40002c00; - // byte offset: 0 Control register (WWDG_CR) + + /// Control register (WWDG_CR) pub const CR = mmio(Address + 0x00000000, 32, packed struct { - T: u7, // bit offset: 0 desc: 7-bit counter (MSB to LSB) - WDGA: u1, // bit offset: 7 desc: Activation bit + /// 7-bit counter (MSB to LSB) + T: u7 = 0, + /// Activation bit + WDGA: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -5449,11 +7080,15 @@ pub const WWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Configuration register (WWDG_CFR) + + /// Configuration register (WWDG_CFR) pub const CFR = mmio(Address + 0x00000004, 32, packed struct { - W: u7, // bit offset: 0 desc: 7-bit window value - WDGTB: u2, // bit offset: 7 desc: Timer Base - EWI: u1, // bit offset: 9 desc: Early Wakeup Interrupt + /// 7-bit window value + W: u7 = 0, + /// Timer Base + WDGTB: u2 = 0, + /// Early Wakeup Interrupt + EWI: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -5477,9 +7112,11 @@ pub const WWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Status register (WWDG_SR) + + /// Status register (WWDG_SR) pub const SR = mmio(Address + 0x00000008, 32, packed struct { - EWI: u1, // bit offset: 0 desc: Early Wakeup Interrupt + /// Early Wakeup Interrupt + EWI: u1 = 0, padding31: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, @@ -5513,18 +7150,29 @@ pub const WWDG = extern struct { padding1: u1 = 0, }); }; + +/// Advanced timer pub const TIM1 = extern struct { pub const Address: u32 = 0x40012c00; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode - DIR: u1, // bit offset: 4 desc: Direction - CMS: u2, // bit offset: 5 desc: Center-aligned mode selection - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, + /// Direction + DIR: u1 = 0, + /// Center-aligned mode selection + CMS: u2 = 0, + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -5548,21 +7196,34 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - CCPC: u1, // bit offset: 0 desc: Capture/compare preloaded control + /// Capture/compare preloaded control + CCPC: u1 = 0, reserved1: u1 = 0, - CCUS: u1, // bit offset: 2 desc: Capture/compare control update selection - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection - MMS: u3, // bit offset: 4 desc: Master mode selection - TI1S: u1, // bit offset: 7 desc: TI1 selection - OIS1: u1, // bit offset: 8 desc: Output Idle state 1 - OIS1N: u1, // bit offset: 9 desc: Output Idle state 1 - OIS2: u1, // bit offset: 10 desc: Output Idle state 2 - OIS2N: u1, // bit offset: 11 desc: Output Idle state 2 - OIS3: u1, // bit offset: 12 desc: Output Idle state 3 - OIS3N: u1, // bit offset: 13 desc: Output Idle state 3 - OIS4: u1, // bit offset: 14 desc: Output Idle state 4 + /// Capture/compare control update selection + CCUS: u1 = 0, + /// Capture/compare DMA selection + CCDS: u1 = 0, + /// Master mode selection + MMS: u3 = 0, + /// TI1 selection + TI1S: u1 = 0, + /// Output Idle state 1 + OIS1: u1 = 0, + /// Output Idle state 1 + OIS1N: u1 = 0, + /// Output Idle state 2 + OIS2: u1 = 0, + /// Output Idle state 2 + OIS2N: u1 = 0, + /// Output Idle state 3 + OIS3: u1 = 0, + /// Output Idle state 3 + OIS3N: u1 = 0, + /// Output Idle state 4 + OIS4: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -5581,16 +7242,24 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection + /// Slave mode selection + SMS: u3 = 0, reserved1: u1 = 0, - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode - ETF: u4, // bit offset: 8 desc: External trigger filter - ETPS: u2, // bit offset: 12 desc: External trigger prescaler - ECE: u1, // bit offset: 14 desc: External clock enable - ETP: u1, // bit offset: 15 desc: External trigger polarity + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, + /// External trigger filter + ETF: u4 = 0, + /// External trigger prescaler + ETPS: u2 = 0, + /// External clock enable + ECE: u1 = 0, + /// External trigger polarity + ETP: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5608,23 +7277,39 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable - CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable - CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable - COMIE: u1, // bit offset: 5 desc: COM interrupt enable - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable - BIE: u1, // bit offset: 7 desc: Break interrupt enable - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable - CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable - CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable - CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable - COMDE: u1, // bit offset: 13 desc: COM DMA request enable - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, + /// Capture/Compare 3 interrupt enable + CC3IE: u1 = 0, + /// Capture/Compare 4 interrupt enable + CC4IE: u1 = 0, + /// COM interrupt enable + COMIE: u1 = 0, + /// Trigger interrupt enable + TIE: u1 = 0, + /// Break interrupt enable + BIE: u1 = 0, + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, + /// Capture/Compare 2 DMA request enable + CC2DE: u1 = 0, + /// Capture/Compare 3 DMA request enable + CC3DE: u1 = 0, + /// Capture/Compare 4 DMA request enable + CC4DE: u1 = 0, + /// COM DMA request enable + COMDE: u1 = 0, + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -5643,21 +7328,34 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag - CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag - CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag - COMIF: u1, // bit offset: 5 desc: COM interrupt flag - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag - BIF: u1, // bit offset: 7 desc: Break interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, + /// Capture/Compare 3 interrupt flag + CC3IF: u1 = 0, + /// Capture/Compare 4 interrupt flag + CC4IF: u1 = 0, + /// COM interrupt flag + COMIF: u1 = 0, + /// Trigger interrupt flag + TIF: u1 = 0, + /// Break interrupt flag + BIF: u1 = 0, reserved1: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag - CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag - CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, + /// Capture/Compare 3 overcapture flag + CC3OF: u1 = 0, + /// Capture/Compare 4 overcapture flag + CC4OF: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -5678,16 +7376,25 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation - CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation - CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation - COMG: u1, // bit offset: 5 desc: Capture/Compare control update generation - TG: u1, // bit offset: 6 desc: Trigger generation - BG: u1, // bit offset: 7 desc: Break generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, + /// Capture/compare 3 generation + CC3G: u1 = 0, + /// Capture/compare 4 generation + CC4G: u1 = 0, + /// Capture/Compare control update generation + COMG: u1 = 0, + /// Trigger generation + TG: u1 = 0, + /// Break generation + BG: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -5713,18 +7420,29 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode - OC1CE: u1, // bit offset: 7 desc: Output Compare 1 clear enable - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output Compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output Compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output Compare 2 mode - OC2CE: u1, // bit offset: 15 desc: Output Compare 2 clear enable + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output Compare 1 fast enable + OC1FE: u1 = 0, + /// Output Compare 1 preload enable + OC1PE: u1 = 0, + /// Output Compare 1 mode + OC1M: u3 = 0, + /// Output Compare 1 clear enable + OC1CE: u1 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output Compare 2 fast enable + OC2FE: u1 = 0, + /// Output Compare 2 preload enable + OC2PE: u1 = 0, + /// Output Compare 2 mode + OC2M: u3 = 0, + /// Output Compare 2 clear enable + OC2CE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5742,14 +7460,21 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - ICPCS: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - IC2PCS: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + ICPCS: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PCS: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5767,18 +7492,29 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable - OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable - OC3M: u3, // bit offset: 4 desc: Output compare 3 mode - OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable - OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable - OC4M: u3, // bit offset: 12 desc: Output compare 4 mode - OC4CE: u1, // bit offset: 15 desc: Output compare 4 clear enable + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Output compare 3 fast enable + OC3FE: u1 = 0, + /// Output compare 3 preload enable + OC3PE: u1 = 0, + /// Output compare 3 mode + OC3M: u3 = 0, + /// Output compare 3 clear enable + OC3CE: u1 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Output compare 4 fast enable + OC4FE: u1 = 0, + /// Output compare 4 preload enable + OC4PE: u1 = 0, + /// Output compare 4 mode + OC4M: u3 = 0, + /// Output compare 4 clear enable + OC4CE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5796,14 +7532,21 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (input mode) + + /// capture/compare mode register 2 (input mode) pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/compare 3 selection - IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler - IC3F: u4, // bit offset: 4 desc: Input capture 3 filter - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler - IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + /// Capture/compare 3 selection + CC3S: u2 = 0, + /// Input capture 3 prescaler + IC3PSC: u2 = 0, + /// Input capture 3 filter + IC3F: u4 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Input capture 4 prescaler + IC4PSC: u2 = 0, + /// Input capture 4 filter + IC4F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5821,22 +7564,37 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity - CC1NE: u1, // bit offset: 2 desc: Capture/Compare 1 complementary output enable - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity - CC2NE: u1, // bit offset: 6 desc: Capture/Compare 2 complementary output enable - CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity - CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable - CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity - CC3NE: u1, // bit offset: 10 desc: Capture/Compare 3 complementary output enable - CC3NP: u1, // bit offset: 11 desc: Capture/Compare 3 output Polarity - CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable - CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, + /// Capture/Compare 1 complementary output enable + CC1NE: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, + /// Capture/Compare 2 complementary output enable + CC2NE: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2NP: u1 = 0, + /// Capture/Compare 3 output enable + CC3E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3P: u1 = 0, + /// Capture/Compare 3 complementary output enable + CC3NE: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3NP: u1 = 0, + /// Capture/Compare 4 output enable + CC4E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC4P: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -5856,9 +7614,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5876,9 +7636,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5896,9 +7658,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5916,9 +7680,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 repetition counter register + + /// repetition counter register pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - REP: u8, // bit offset: 0 desc: Repetition counter value + /// Repetition counter value + REP: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -5944,9 +7710,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5964,9 +7732,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + /// Capture/Compare 2 value + CCR2: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5984,9 +7754,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 capture/compare register 3 + + /// capture/compare register 3 pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - CCR3: u16, // bit offset: 0 desc: Capture/Compare value + /// Capture/Compare value + CCR3: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6004,9 +7776,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 capture/compare register 4 + + /// capture/compare register 4 pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - CCR4: u16, // bit offset: 0 desc: Capture/Compare value + /// Capture/Compare value + CCR4: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6024,16 +7798,25 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 break and dead-time register + + /// break and dead-time register pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - DTG: u8, // bit offset: 0 desc: Dead-time generator setup - LOCK: u2, // bit offset: 8 desc: Lock configuration - OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode - OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode - BKE: u1, // bit offset: 12 desc: Break enable - BKP: u1, // bit offset: 13 desc: Break polarity - AOE: u1, // bit offset: 14 desc: Automatic output enable - MOE: u1, // bit offset: 15 desc: Main output enable + /// Dead-time generator setup + DTG: u8 = 0, + /// Lock configuration + LOCK: u2 = 0, + /// Off-state selection for Idle mode + OSSI: u1 = 0, + /// Off-state selection for Run mode + OSSR: u1 = 0, + /// Break enable + BKE: u1 = 0, + /// Break polarity + BKP: u1 = 0, + /// Automatic output enable + AOE: u1 = 0, + /// Main output enable + MOE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6051,13 +7834,16 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -6078,9 +7864,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6099,18 +7887,29 @@ pub const TIM1 = extern struct { padding1: u1 = 0, }); }; + +/// Advanced timer pub const TIM8 = extern struct { pub const Address: u32 = 0x40013400; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode - DIR: u1, // bit offset: 4 desc: Direction - CMS: u2, // bit offset: 5 desc: Center-aligned mode selection - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, + /// Direction + DIR: u1 = 0, + /// Center-aligned mode selection + CMS: u2 = 0, + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -6134,21 +7933,34 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - CCPC: u1, // bit offset: 0 desc: Capture/compare preloaded control + /// Capture/compare preloaded control + CCPC: u1 = 0, reserved1: u1 = 0, - CCUS: u1, // bit offset: 2 desc: Capture/compare control update selection - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection - MMS: u3, // bit offset: 4 desc: Master mode selection - TI1S: u1, // bit offset: 7 desc: TI1 selection - OIS1: u1, // bit offset: 8 desc: Output Idle state 1 - OIS1N: u1, // bit offset: 9 desc: Output Idle state 1 - OIS2: u1, // bit offset: 10 desc: Output Idle state 2 - OIS2N: u1, // bit offset: 11 desc: Output Idle state 2 - OIS3: u1, // bit offset: 12 desc: Output Idle state 3 - OIS3N: u1, // bit offset: 13 desc: Output Idle state 3 - OIS4: u1, // bit offset: 14 desc: Output Idle state 4 + /// Capture/compare control update selection + CCUS: u1 = 0, + /// Capture/compare DMA selection + CCDS: u1 = 0, + /// Master mode selection + MMS: u3 = 0, + /// TI1 selection + TI1S: u1 = 0, + /// Output Idle state 1 + OIS1: u1 = 0, + /// Output Idle state 1 + OIS1N: u1 = 0, + /// Output Idle state 2 + OIS2: u1 = 0, + /// Output Idle state 2 + OIS2N: u1 = 0, + /// Output Idle state 3 + OIS3: u1 = 0, + /// Output Idle state 3 + OIS3N: u1 = 0, + /// Output Idle state 4 + OIS4: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -6167,16 +7979,24 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection + /// Slave mode selection + SMS: u3 = 0, reserved1: u1 = 0, - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode - ETF: u4, // bit offset: 8 desc: External trigger filter - ETPS: u2, // bit offset: 12 desc: External trigger prescaler - ECE: u1, // bit offset: 14 desc: External clock enable - ETP: u1, // bit offset: 15 desc: External trigger polarity + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, + /// External trigger filter + ETF: u4 = 0, + /// External trigger prescaler + ETPS: u2 = 0, + /// External clock enable + ECE: u1 = 0, + /// External trigger polarity + ETP: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6194,23 +8014,39 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable - CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable - CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable - COMIE: u1, // bit offset: 5 desc: COM interrupt enable - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable - BIE: u1, // bit offset: 7 desc: Break interrupt enable - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable - CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable - CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable - CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable - COMDE: u1, // bit offset: 13 desc: COM DMA request enable - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, + /// Capture/Compare 3 interrupt enable + CC3IE: u1 = 0, + /// Capture/Compare 4 interrupt enable + CC4IE: u1 = 0, + /// COM interrupt enable + COMIE: u1 = 0, + /// Trigger interrupt enable + TIE: u1 = 0, + /// Break interrupt enable + BIE: u1 = 0, + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, + /// Capture/Compare 2 DMA request enable + CC2DE: u1 = 0, + /// Capture/Compare 3 DMA request enable + CC3DE: u1 = 0, + /// Capture/Compare 4 DMA request enable + CC4DE: u1 = 0, + /// COM DMA request enable + COMDE: u1 = 0, + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -6229,21 +8065,34 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag - CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag - CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag - COMIF: u1, // bit offset: 5 desc: COM interrupt flag - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag - BIF: u1, // bit offset: 7 desc: Break interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, + /// Capture/Compare 3 interrupt flag + CC3IF: u1 = 0, + /// Capture/Compare 4 interrupt flag + CC4IF: u1 = 0, + /// COM interrupt flag + COMIF: u1 = 0, + /// Trigger interrupt flag + TIF: u1 = 0, + /// Break interrupt flag + BIF: u1 = 0, reserved1: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag - CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag - CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, + /// Capture/Compare 3 overcapture flag + CC3OF: u1 = 0, + /// Capture/Compare 4 overcapture flag + CC4OF: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -6264,16 +8113,25 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation - CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation - CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation - COMG: u1, // bit offset: 5 desc: Capture/Compare control update generation - TG: u1, // bit offset: 6 desc: Trigger generation - BG: u1, // bit offset: 7 desc: Break generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, + /// Capture/compare 3 generation + CC3G: u1 = 0, + /// Capture/compare 4 generation + CC4G: u1 = 0, + /// Capture/Compare control update generation + COMG: u1 = 0, + /// Trigger generation + TG: u1 = 0, + /// Break generation + BG: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -6299,18 +8157,29 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode - OC1CE: u1, // bit offset: 7 desc: Output Compare 1 clear enable - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output Compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output Compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output Compare 2 mode - OC2CE: u1, // bit offset: 15 desc: Output Compare 2 clear enable + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output Compare 1 fast enable + OC1FE: u1 = 0, + /// Output Compare 1 preload enable + OC1PE: u1 = 0, + /// Output Compare 1 mode + OC1M: u3 = 0, + /// Output Compare 1 clear enable + OC1CE: u1 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output Compare 2 fast enable + OC2FE: u1 = 0, + /// Output Compare 2 preload enable + OC2PE: u1 = 0, + /// Output Compare 2 mode + OC2M: u3 = 0, + /// Output Compare 2 clear enable + OC2CE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6328,14 +8197,21 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - ICPCS: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - IC2PCS: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + ICPCS: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PCS: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6353,18 +8229,29 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable - OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable - OC3M: u3, // bit offset: 4 desc: Output compare 3 mode - OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable - OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable - OC4M: u3, // bit offset: 12 desc: Output compare 4 mode - OC4CE: u1, // bit offset: 15 desc: Output compare 4 clear enable + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Output compare 3 fast enable + OC3FE: u1 = 0, + /// Output compare 3 preload enable + OC3PE: u1 = 0, + /// Output compare 3 mode + OC3M: u3 = 0, + /// Output compare 3 clear enable + OC3CE: u1 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Output compare 4 fast enable + OC4FE: u1 = 0, + /// Output compare 4 preload enable + OC4PE: u1 = 0, + /// Output compare 4 mode + OC4M: u3 = 0, + /// Output compare 4 clear enable + OC4CE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6382,14 +8269,21 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (input mode) + + /// capture/compare mode register 2 (input mode) pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/compare 3 selection - IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler - IC3F: u4, // bit offset: 4 desc: Input capture 3 filter - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler - IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + /// Capture/compare 3 selection + CC3S: u2 = 0, + /// Input capture 3 prescaler + IC3PSC: u2 = 0, + /// Input capture 3 filter + IC3F: u4 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Input capture 4 prescaler + IC4PSC: u2 = 0, + /// Input capture 4 filter + IC4F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6407,22 +8301,37 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity - CC1NE: u1, // bit offset: 2 desc: Capture/Compare 1 complementary output enable - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity - CC2NE: u1, // bit offset: 6 desc: Capture/Compare 2 complementary output enable - CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity - CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable - CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity - CC3NE: u1, // bit offset: 10 desc: Capture/Compare 3 complementary output enable - CC3NP: u1, // bit offset: 11 desc: Capture/Compare 3 output Polarity - CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable - CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, + /// Capture/Compare 1 complementary output enable + CC1NE: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, + /// Capture/Compare 2 complementary output enable + CC2NE: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2NP: u1 = 0, + /// Capture/Compare 3 output enable + CC3E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3P: u1 = 0, + /// Capture/Compare 3 complementary output enable + CC3NE: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3NP: u1 = 0, + /// Capture/Compare 4 output enable + CC4E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC4P: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -6442,9 +8351,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6462,9 +8373,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6482,9 +8395,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6502,9 +8417,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 repetition counter register + + /// repetition counter register pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - REP: u8, // bit offset: 0 desc: Repetition counter value + /// Repetition counter value + REP: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -6530,9 +8447,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6550,9 +8469,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + /// Capture/Compare 2 value + CCR2: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6570,9 +8491,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 capture/compare register 3 + + /// capture/compare register 3 pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - CCR3: u16, // bit offset: 0 desc: Capture/Compare value + /// Capture/Compare value + CCR3: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6590,9 +8513,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 capture/compare register 4 + + /// capture/compare register 4 pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - CCR4: u16, // bit offset: 0 desc: Capture/Compare value + /// Capture/Compare value + CCR4: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6610,16 +8535,25 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 break and dead-time register + + /// break and dead-time register pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - DTG: u8, // bit offset: 0 desc: Dead-time generator setup - LOCK: u2, // bit offset: 8 desc: Lock configuration - OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode - OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode - BKE: u1, // bit offset: 12 desc: Break enable - BKP: u1, // bit offset: 13 desc: Break polarity - AOE: u1, // bit offset: 14 desc: Automatic output enable - MOE: u1, // bit offset: 15 desc: Main output enable + /// Dead-time generator setup + DTG: u8 = 0, + /// Lock configuration + LOCK: u2 = 0, + /// Off-state selection for Idle mode + OSSI: u1 = 0, + /// Off-state selection for Run mode + OSSR: u1 = 0, + /// Break enable + BKE: u1 = 0, + /// Break polarity + BKP: u1 = 0, + /// Automatic output enable + AOE: u1 = 0, + /// Main output enable + MOE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6637,13 +8571,16 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -6664,9 +8601,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6685,18 +8624,29 @@ pub const TIM8 = extern struct { padding1: u1 = 0, }); }; + +/// General purpose timer pub const TIM2 = extern struct { pub const Address: u32 = 0x40000000; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode - DIR: u1, // bit offset: 4 desc: Direction - CMS: u2, // bit offset: 5 desc: Center-aligned mode selection - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, + /// Direction + DIR: u1 = 0, + /// Center-aligned mode selection + CMS: u2 = 0, + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -6720,14 +8670,18 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection - MMS: u3, // bit offset: 4 desc: Master mode selection - TI1S: u1, // bit offset: 7 desc: TI1 selection + /// Capture/compare DMA selection + CCDS: u1 = 0, + /// Master mode selection + MMS: u3 = 0, + /// TI1 selection + TI1S: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -6753,16 +8707,24 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection + /// Slave mode selection + SMS: u3 = 0, reserved1: u1 = 0, - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode - ETF: u4, // bit offset: 8 desc: External trigger filter - ETPS: u2, // bit offset: 12 desc: External trigger prescaler - ECE: u1, // bit offset: 14 desc: External clock enable - ETP: u1, // bit offset: 15 desc: External trigger polarity + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, + /// External trigger filter + ETF: u4 = 0, + /// External trigger prescaler + ETPS: u2 = 0, + /// External clock enable + ECE: u1 = 0, + /// External trigger polarity + ETP: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6780,23 +8742,36 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable - CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable - CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, + /// Capture/Compare 3 interrupt enable + CC3IE: u1 = 0, + /// Capture/Compare 4 interrupt enable + CC4IE: u1 = 0, reserved1: u1 = 0, - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + /// Trigger interrupt enable + TIE: u1 = 0, reserved2: u1 = 0, - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable - CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable - CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable - CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, + /// Capture/Compare 2 DMA request enable + CC2DE: u1 = 0, + /// Capture/Compare 3 DMA request enable + CC3DE: u1 = 0, + /// Capture/Compare 4 DMA request enable + CC4DE: u1 = 0, reserved3: u1 = 0, - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -6815,21 +8790,32 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag - CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag - CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, + /// Capture/Compare 3 interrupt flag + CC3IF: u1 = 0, + /// Capture/Compare 4 interrupt flag + CC4IF: u1 = 0, reserved1: u1 = 0, - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + /// Trigger interrupt flag + TIF: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag - CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag - CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, + /// Capture/Compare 3 overcapture flag + CC3OF: u1 = 0, + /// Capture/Compare 4 overcapture flag + CC4OF: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -6850,15 +8836,22 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation - CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation - CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, + /// Capture/compare 3 generation + CC3G: u1 = 0, + /// Capture/compare 4 generation + CC4G: u1 = 0, reserved1: u1 = 0, - TG: u1, // bit offset: 6 desc: Trigger generation + /// Trigger generation + TG: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -6885,18 +8878,29 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (output mode) + + /// capture/compare mode register 1 (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output compare 1 mode - OC1CE: u1, // bit offset: 7 desc: Output compare 1 clear enable - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output compare 2 mode - OC2CE: u1, // bit offset: 15 desc: Output compare 2 clear enable + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output compare 1 fast enable + OC1FE: u1 = 0, + /// Output compare 1 preload enable + OC1PE: u1 = 0, + /// Output compare 1 mode + OC1M: u3 = 0, + /// Output compare 1 clear enable + OC1CE: u1 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output compare 2 fast enable + OC2FE: u1 = 0, + /// Output compare 2 preload enable + OC2PE: u1 = 0, + /// Output compare 2 mode + OC2M: u3 = 0, + /// Output compare 2 clear enable + OC2CE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6914,14 +8918,21 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/compare 2 selection - IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PSC: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6939,18 +8950,29 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (output mode) + + /// capture/compare mode register 2 (output mode) pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable - OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable - OC3M: u3, // bit offset: 4 desc: Output compare 3 mode - OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable - OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable - OC4M: u3, // bit offset: 12 desc: Output compare 4 mode - O24CE: u1, // bit offset: 15 desc: Output compare 4 clear enable + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Output compare 3 fast enable + OC3FE: u1 = 0, + /// Output compare 3 preload enable + OC3PE: u1 = 0, + /// Output compare 3 mode + OC3M: u3 = 0, + /// Output compare 3 clear enable + OC3CE: u1 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Output compare 4 fast enable + OC4FE: u1 = 0, + /// Output compare 4 preload enable + OC4PE: u1 = 0, + /// Output compare 4 mode + OC4M: u3 = 0, + /// Output compare 4 clear enable + O24CE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6968,14 +8990,21 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (input mode) + + /// capture/compare mode register 2 (input mode) pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler - IC3F: u4, // bit offset: 4 desc: Input capture 3 filter - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler - IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Input capture 3 prescaler + IC3PSC: u2 = 0, + /// Input capture 3 filter + IC3F: u4 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Input capture 4 prescaler + IC4PSC: u2 = 0, + /// Input capture 4 filter + IC4F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6993,22 +9022,31 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable - CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 3 output enable + CC3E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3P: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable - CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 4 output enable + CC4E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC4P: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -7028,9 +9066,11 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7048,9 +9088,11 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7068,9 +9110,11 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7088,9 +9132,11 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7108,9 +9154,11 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + /// Capture/Compare 2 value + CCR2: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7128,9 +9176,11 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 capture/compare register 3 + + /// capture/compare register 3 pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - CCR3: u16, // bit offset: 0 desc: Capture/Compare value + /// Capture/Compare value + CCR3: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7148,9 +9198,11 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 capture/compare register 4 + + /// capture/compare register 4 pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - CCR4: u16, // bit offset: 0 desc: Capture/Compare value + /// Capture/Compare value + CCR4: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7168,13 +9220,16 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -7195,9 +9250,11 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7216,18 +9273,29 @@ pub const TIM2 = extern struct { padding1: u1 = 0, }); }; + +/// General purpose timer pub const TIM3 = extern struct { pub const Address: u32 = 0x40000400; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode - DIR: u1, // bit offset: 4 desc: Direction - CMS: u2, // bit offset: 5 desc: Center-aligned mode selection - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, + /// Direction + DIR: u1 = 0, + /// Center-aligned mode selection + CMS: u2 = 0, + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -7251,14 +9319,18 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection - MMS: u3, // bit offset: 4 desc: Master mode selection - TI1S: u1, // bit offset: 7 desc: TI1 selection + /// Capture/compare DMA selection + CCDS: u1 = 0, + /// Master mode selection + MMS: u3 = 0, + /// TI1 selection + TI1S: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -7284,16 +9356,24 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection + /// Slave mode selection + SMS: u3 = 0, reserved1: u1 = 0, - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode - ETF: u4, // bit offset: 8 desc: External trigger filter - ETPS: u2, // bit offset: 12 desc: External trigger prescaler - ECE: u1, // bit offset: 14 desc: External clock enable - ETP: u1, // bit offset: 15 desc: External trigger polarity + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, + /// External trigger filter + ETF: u4 = 0, + /// External trigger prescaler + ETPS: u2 = 0, + /// External clock enable + ECE: u1 = 0, + /// External trigger polarity + ETP: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7311,23 +9391,36 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable - CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable - CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, + /// Capture/Compare 3 interrupt enable + CC3IE: u1 = 0, + /// Capture/Compare 4 interrupt enable + CC4IE: u1 = 0, reserved1: u1 = 0, - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + /// Trigger interrupt enable + TIE: u1 = 0, reserved2: u1 = 0, - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable - CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable - CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable - CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, + /// Capture/Compare 2 DMA request enable + CC2DE: u1 = 0, + /// Capture/Compare 3 DMA request enable + CC3DE: u1 = 0, + /// Capture/Compare 4 DMA request enable + CC4DE: u1 = 0, reserved3: u1 = 0, - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -7346,21 +9439,32 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag - CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag - CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, + /// Capture/Compare 3 interrupt flag + CC3IF: u1 = 0, + /// Capture/Compare 4 interrupt flag + CC4IF: u1 = 0, reserved1: u1 = 0, - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + /// Trigger interrupt flag + TIF: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag - CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag - CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, + /// Capture/Compare 3 overcapture flag + CC3OF: u1 = 0, + /// Capture/Compare 4 overcapture flag + CC4OF: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -7381,15 +9485,22 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation - CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation - CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, + /// Capture/compare 3 generation + CC3G: u1 = 0, + /// Capture/compare 4 generation + CC4G: u1 = 0, reserved1: u1 = 0, - TG: u1, // bit offset: 6 desc: Trigger generation + /// Trigger generation + TG: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -7416,18 +9527,29 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (output mode) + + /// capture/compare mode register 1 (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output compare 1 mode - OC1CE: u1, // bit offset: 7 desc: Output compare 1 clear enable - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output compare 2 mode - OC2CE: u1, // bit offset: 15 desc: Output compare 2 clear enable + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output compare 1 fast enable + OC1FE: u1 = 0, + /// Output compare 1 preload enable + OC1PE: u1 = 0, + /// Output compare 1 mode + OC1M: u3 = 0, + /// Output compare 1 clear enable + OC1CE: u1 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output compare 2 fast enable + OC2FE: u1 = 0, + /// Output compare 2 preload enable + OC2PE: u1 = 0, + /// Output compare 2 mode + OC2M: u3 = 0, + /// Output compare 2 clear enable + OC2CE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7445,14 +9567,21 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/compare 2 selection - IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PSC: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7470,18 +9599,29 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (output mode) + + /// capture/compare mode register 2 (output mode) pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable - OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable - OC3M: u3, // bit offset: 4 desc: Output compare 3 mode - OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable - OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable - OC4M: u3, // bit offset: 12 desc: Output compare 4 mode - O24CE: u1, // bit offset: 15 desc: Output compare 4 clear enable + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Output compare 3 fast enable + OC3FE: u1 = 0, + /// Output compare 3 preload enable + OC3PE: u1 = 0, + /// Output compare 3 mode + OC3M: u3 = 0, + /// Output compare 3 clear enable + OC3CE: u1 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Output compare 4 fast enable + OC4FE: u1 = 0, + /// Output compare 4 preload enable + OC4PE: u1 = 0, + /// Output compare 4 mode + OC4M: u3 = 0, + /// Output compare 4 clear enable + O24CE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7499,14 +9639,21 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (input mode) + + /// capture/compare mode register 2 (input mode) pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler - IC3F: u4, // bit offset: 4 desc: Input capture 3 filter - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler - IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Input capture 3 prescaler + IC3PSC: u2 = 0, + /// Input capture 3 filter + IC3F: u4 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Input capture 4 prescaler + IC4PSC: u2 = 0, + /// Input capture 4 filter + IC4F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7524,22 +9671,31 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable - CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 3 output enable + CC3E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3P: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable - CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 4 output enable + CC4E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC4P: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -7559,9 +9715,11 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7579,9 +9737,11 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7599,9 +9759,11 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7619,9 +9781,11 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7639,9 +9803,11 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + /// Capture/Compare 2 value + CCR2: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7659,9 +9825,11 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 capture/compare register 3 + + /// capture/compare register 3 pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - CCR3: u16, // bit offset: 0 desc: Capture/Compare value + /// Capture/Compare value + CCR3: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7679,9 +9847,11 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 capture/compare register 4 + + /// capture/compare register 4 pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - CCR4: u16, // bit offset: 0 desc: Capture/Compare value + /// Capture/Compare value + CCR4: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7699,13 +9869,16 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -7726,9 +9899,11 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7747,18 +9922,29 @@ pub const TIM3 = extern struct { padding1: u1 = 0, }); }; + +/// General purpose timer pub const TIM4 = extern struct { pub const Address: u32 = 0x40000800; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode - DIR: u1, // bit offset: 4 desc: Direction - CMS: u2, // bit offset: 5 desc: Center-aligned mode selection - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, + /// Direction + DIR: u1 = 0, + /// Center-aligned mode selection + CMS: u2 = 0, + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -7782,14 +9968,18 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection - MMS: u3, // bit offset: 4 desc: Master mode selection - TI1S: u1, // bit offset: 7 desc: TI1 selection + /// Capture/compare DMA selection + CCDS: u1 = 0, + /// Master mode selection + MMS: u3 = 0, + /// TI1 selection + TI1S: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -7815,16 +10005,24 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection + /// Slave mode selection + SMS: u3 = 0, reserved1: u1 = 0, - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode - ETF: u4, // bit offset: 8 desc: External trigger filter - ETPS: u2, // bit offset: 12 desc: External trigger prescaler - ECE: u1, // bit offset: 14 desc: External clock enable - ETP: u1, // bit offset: 15 desc: External trigger polarity + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, + /// External trigger filter + ETF: u4 = 0, + /// External trigger prescaler + ETPS: u2 = 0, + /// External clock enable + ECE: u1 = 0, + /// External trigger polarity + ETP: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7842,23 +10040,36 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable - CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable - CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, + /// Capture/Compare 3 interrupt enable + CC3IE: u1 = 0, + /// Capture/Compare 4 interrupt enable + CC4IE: u1 = 0, reserved1: u1 = 0, - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + /// Trigger interrupt enable + TIE: u1 = 0, reserved2: u1 = 0, - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable - CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable - CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable - CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, + /// Capture/Compare 2 DMA request enable + CC2DE: u1 = 0, + /// Capture/Compare 3 DMA request enable + CC3DE: u1 = 0, + /// Capture/Compare 4 DMA request enable + CC4DE: u1 = 0, reserved3: u1 = 0, - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -7877,21 +10088,32 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag - CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag - CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, + /// Capture/Compare 3 interrupt flag + CC3IF: u1 = 0, + /// Capture/Compare 4 interrupt flag + CC4IF: u1 = 0, reserved1: u1 = 0, - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + /// Trigger interrupt flag + TIF: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag - CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag - CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, + /// Capture/Compare 3 overcapture flag + CC3OF: u1 = 0, + /// Capture/Compare 4 overcapture flag + CC4OF: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -7912,15 +10134,22 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation - CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation - CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, + /// Capture/compare 3 generation + CC3G: u1 = 0, + /// Capture/compare 4 generation + CC4G: u1 = 0, reserved1: u1 = 0, - TG: u1, // bit offset: 6 desc: Trigger generation + /// Trigger generation + TG: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -7947,18 +10176,29 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (output mode) + + /// capture/compare mode register 1 (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output compare 1 mode - OC1CE: u1, // bit offset: 7 desc: Output compare 1 clear enable - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output compare 2 mode - OC2CE: u1, // bit offset: 15 desc: Output compare 2 clear enable + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output compare 1 fast enable + OC1FE: u1 = 0, + /// Output compare 1 preload enable + OC1PE: u1 = 0, + /// Output compare 1 mode + OC1M: u3 = 0, + /// Output compare 1 clear enable + OC1CE: u1 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output compare 2 fast enable + OC2FE: u1 = 0, + /// Output compare 2 preload enable + OC2PE: u1 = 0, + /// Output compare 2 mode + OC2M: u3 = 0, + /// Output compare 2 clear enable + OC2CE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7976,14 +10216,21 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/compare 2 selection - IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PSC: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8001,18 +10248,29 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (output mode) + + /// capture/compare mode register 2 (output mode) pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable - OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable - OC3M: u3, // bit offset: 4 desc: Output compare 3 mode - OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable - OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable - OC4M: u3, // bit offset: 12 desc: Output compare 4 mode - O24CE: u1, // bit offset: 15 desc: Output compare 4 clear enable + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Output compare 3 fast enable + OC3FE: u1 = 0, + /// Output compare 3 preload enable + OC3PE: u1 = 0, + /// Output compare 3 mode + OC3M: u3 = 0, + /// Output compare 3 clear enable + OC3CE: u1 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Output compare 4 fast enable + OC4FE: u1 = 0, + /// Output compare 4 preload enable + OC4PE: u1 = 0, + /// Output compare 4 mode + OC4M: u3 = 0, + /// Output compare 4 clear enable + O24CE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8030,14 +10288,21 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (input mode) + + /// capture/compare mode register 2 (input mode) pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler - IC3F: u4, // bit offset: 4 desc: Input capture 3 filter - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler - IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Input capture 3 prescaler + IC3PSC: u2 = 0, + /// Input capture 3 filter + IC3F: u4 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Input capture 4 prescaler + IC4PSC: u2 = 0, + /// Input capture 4 filter + IC4F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8055,22 +10320,31 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable - CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 3 output enable + CC3E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3P: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable - CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 4 output enable + CC4E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC4P: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -8090,9 +10364,11 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8110,9 +10386,11 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8130,9 +10408,11 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8150,9 +10430,11 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8170,9 +10452,11 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + /// Capture/Compare 2 value + CCR2: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8190,9 +10474,11 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 capture/compare register 3 + + /// capture/compare register 3 pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - CCR3: u16, // bit offset: 0 desc: Capture/Compare value + /// Capture/Compare value + CCR3: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8210,9 +10496,11 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 capture/compare register 4 + + /// capture/compare register 4 pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - CCR4: u16, // bit offset: 0 desc: Capture/Compare value + /// Capture/Compare value + CCR4: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8230,13 +10518,16 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -8257,9 +10548,11 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8278,18 +10571,29 @@ pub const TIM4 = extern struct { padding1: u1 = 0, }); }; + +/// General purpose timer pub const TIM5 = extern struct { pub const Address: u32 = 0x40000c00; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode - DIR: u1, // bit offset: 4 desc: Direction - CMS: u2, // bit offset: 5 desc: Center-aligned mode selection - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, + /// Direction + DIR: u1 = 0, + /// Center-aligned mode selection + CMS: u2 = 0, + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -8313,14 +10617,18 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection - MMS: u3, // bit offset: 4 desc: Master mode selection - TI1S: u1, // bit offset: 7 desc: TI1 selection + /// Capture/compare DMA selection + CCDS: u1 = 0, + /// Master mode selection + MMS: u3 = 0, + /// TI1 selection + TI1S: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -8346,16 +10654,24 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection + /// Slave mode selection + SMS: u3 = 0, reserved1: u1 = 0, - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode - ETF: u4, // bit offset: 8 desc: External trigger filter - ETPS: u2, // bit offset: 12 desc: External trigger prescaler - ECE: u1, // bit offset: 14 desc: External clock enable - ETP: u1, // bit offset: 15 desc: External trigger polarity + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, + /// External trigger filter + ETF: u4 = 0, + /// External trigger prescaler + ETPS: u2 = 0, + /// External clock enable + ECE: u1 = 0, + /// External trigger polarity + ETP: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8373,23 +10689,36 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable - CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable - CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, + /// Capture/Compare 3 interrupt enable + CC3IE: u1 = 0, + /// Capture/Compare 4 interrupt enable + CC4IE: u1 = 0, reserved1: u1 = 0, - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + /// Trigger interrupt enable + TIE: u1 = 0, reserved2: u1 = 0, - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable - CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable - CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable - CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, + /// Capture/Compare 2 DMA request enable + CC2DE: u1 = 0, + /// Capture/Compare 3 DMA request enable + CC3DE: u1 = 0, + /// Capture/Compare 4 DMA request enable + CC4DE: u1 = 0, reserved3: u1 = 0, - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -8408,21 +10737,32 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag - CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag - CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, + /// Capture/Compare 3 interrupt flag + CC3IF: u1 = 0, + /// Capture/Compare 4 interrupt flag + CC4IF: u1 = 0, reserved1: u1 = 0, - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + /// Trigger interrupt flag + TIF: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag - CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag - CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, + /// Capture/Compare 3 overcapture flag + CC3OF: u1 = 0, + /// Capture/Compare 4 overcapture flag + CC4OF: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -8443,15 +10783,22 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation - CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation - CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, + /// Capture/compare 3 generation + CC3G: u1 = 0, + /// Capture/compare 4 generation + CC4G: u1 = 0, reserved1: u1 = 0, - TG: u1, // bit offset: 6 desc: Trigger generation + /// Trigger generation + TG: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -8478,18 +10825,29 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (output mode) + + /// capture/compare mode register 1 (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output compare 1 mode - OC1CE: u1, // bit offset: 7 desc: Output compare 1 clear enable - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output compare 2 mode - OC2CE: u1, // bit offset: 15 desc: Output compare 2 clear enable + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output compare 1 fast enable + OC1FE: u1 = 0, + /// Output compare 1 preload enable + OC1PE: u1 = 0, + /// Output compare 1 mode + OC1M: u3 = 0, + /// Output compare 1 clear enable + OC1CE: u1 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output compare 2 fast enable + OC2FE: u1 = 0, + /// Output compare 2 preload enable + OC2PE: u1 = 0, + /// Output compare 2 mode + OC2M: u3 = 0, + /// Output compare 2 clear enable + OC2CE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8507,14 +10865,21 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/compare 2 selection - IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PSC: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8532,18 +10897,29 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (output mode) + + /// capture/compare mode register 2 (output mode) pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable - OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable - OC3M: u3, // bit offset: 4 desc: Output compare 3 mode - OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable - OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable - OC4M: u3, // bit offset: 12 desc: Output compare 4 mode - O24CE: u1, // bit offset: 15 desc: Output compare 4 clear enable + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Output compare 3 fast enable + OC3FE: u1 = 0, + /// Output compare 3 preload enable + OC3PE: u1 = 0, + /// Output compare 3 mode + OC3M: u3 = 0, + /// Output compare 3 clear enable + OC3CE: u1 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Output compare 4 fast enable + OC4FE: u1 = 0, + /// Output compare 4 preload enable + OC4PE: u1 = 0, + /// Output compare 4 mode + OC4M: u3 = 0, + /// Output compare 4 clear enable + O24CE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8561,14 +10937,21 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (input mode) + + /// capture/compare mode register 2 (input mode) pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler - IC3F: u4, // bit offset: 4 desc: Input capture 3 filter - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler - IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Input capture 3 prescaler + IC3PSC: u2 = 0, + /// Input capture 3 filter + IC3F: u4 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Input capture 4 prescaler + IC4PSC: u2 = 0, + /// Input capture 4 filter + IC4F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8586,22 +10969,31 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable - CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 3 output enable + CC3E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3P: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable - CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 4 output enable + CC4E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC4P: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -8621,9 +11013,11 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8641,9 +11035,11 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8661,9 +11057,11 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8681,9 +11079,11 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8701,9 +11101,11 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + /// Capture/Compare 2 value + CCR2: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8721,9 +11123,11 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 capture/compare register 3 + + /// capture/compare register 3 pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - CCR3: u16, // bit offset: 0 desc: Capture/Compare value + /// Capture/Compare value + CCR3: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8741,9 +11145,11 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 capture/compare register 4 + + /// capture/compare register 4 pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - CCR4: u16, // bit offset: 0 desc: Capture/Compare value + /// Capture/Compare value + CCR4: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8761,13 +11167,16 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -8788,9 +11197,11 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8809,19 +11220,28 @@ pub const TIM5 = extern struct { padding1: u1 = 0, }); }; + +/// General purpose timer pub const TIM9 = extern struct { pub const Address: u32 = 0x40014c00; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -8845,13 +11265,15 @@ pub const TIM9 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MMS: u3, // bit offset: 4 desc: Master mode selection + /// Master mode selection + MMS: u3 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -8878,12 +11300,16 @@ pub const TIM9 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection + /// Slave mode selection + SMS: u3 = 0, reserved1: u1 = 0, - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -8909,15 +11335,20 @@ pub const TIM9 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + /// Trigger interrupt enable + TIE: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -8944,19 +11375,26 @@ pub const TIM9 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + /// Trigger interrupt flag + TIF: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -8979,15 +11417,20 @@ pub const TIM9 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TG: u1, // bit offset: 6 desc: Trigger generation + /// Trigger generation + TG: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -9014,17 +11457,26 @@ pub const TIM9 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (output mode) + + /// capture/compare mode register 1 (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output Compare 1 fast enable + OC1FE: u1 = 0, + /// Output Compare 1 preload enable + OC1PE: u1 = 0, + /// Output Compare 1 mode + OC1M: u3 = 0, reserved1: u1 = 0, - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output Compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output Compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output Compare 2 mode + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output Compare 2 fast enable + OC2FE: u1 = 0, + /// Output Compare 2 preload enable + OC2PE: u1 = 0, + /// Output Compare 2 mode + OC2M: u3 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -9043,14 +11495,21 @@ pub const TIM9 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PSC: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9068,16 +11527,23 @@ pub const TIM9 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, reserved1: u1 = 0, - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, reserved2: u1 = 0, - CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity + /// Capture/Compare 2 output Polarity + CC2NP: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -9103,9 +11569,11 @@ pub const TIM9 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9123,9 +11591,11 @@ pub const TIM9 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9143,9 +11613,11 @@ pub const TIM9 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9163,9 +11635,11 @@ pub const TIM9 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9183,9 +11657,11 @@ pub const TIM9 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + /// Capture/Compare 2 value + CCR2: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9204,19 +11680,28 @@ pub const TIM9 = extern struct { padding1: u1 = 0, }); }; + +/// General purpose timer pub const TIM12 = extern struct { pub const Address: u32 = 0x40001800; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -9240,13 +11725,15 @@ pub const TIM12 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MMS: u3, // bit offset: 4 desc: Master mode selection + /// Master mode selection + MMS: u3 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -9273,12 +11760,16 @@ pub const TIM12 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection + /// Slave mode selection + SMS: u3 = 0, reserved1: u1 = 0, - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -9304,15 +11795,20 @@ pub const TIM12 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + /// Trigger interrupt enable + TIE: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -9339,19 +11835,26 @@ pub const TIM12 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + /// Trigger interrupt flag + TIF: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -9374,15 +11877,20 @@ pub const TIM12 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TG: u1, // bit offset: 6 desc: Trigger generation + /// Trigger generation + TG: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -9409,17 +11917,26 @@ pub const TIM12 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (output mode) + + /// capture/compare mode register 1 (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output Compare 1 fast enable + OC1FE: u1 = 0, + /// Output Compare 1 preload enable + OC1PE: u1 = 0, + /// Output Compare 1 mode + OC1M: u3 = 0, reserved1: u1 = 0, - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output Compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output Compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output Compare 2 mode + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output Compare 2 fast enable + OC2FE: u1 = 0, + /// Output Compare 2 preload enable + OC2PE: u1 = 0, + /// Output Compare 2 mode + OC2M: u3 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -9438,14 +11955,21 @@ pub const TIM12 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PSC: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9463,16 +11987,23 @@ pub const TIM12 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, reserved1: u1 = 0, - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, reserved2: u1 = 0, - CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity + /// Capture/Compare 2 output Polarity + CC2NP: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -9498,9 +12029,11 @@ pub const TIM12 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9518,9 +12051,11 @@ pub const TIM12 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9538,9 +12073,11 @@ pub const TIM12 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9558,9 +12095,11 @@ pub const TIM12 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9578,9 +12117,11 @@ pub const TIM12 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + /// Capture/Compare 2 value + CCR2: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9599,19 +12140,27 @@ pub const TIM12 = extern struct { padding1: u1 = 0, }); }; + +/// General purpose timer pub const TIM10 = extern struct { pub const Address: u32 = 0x40015000; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -9635,13 +12184,15 @@ pub const TIM10 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MMS: u3, // bit offset: 4 desc: Master mode selection + /// Master mode selection + MMS: u3 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -9668,10 +12219,13 @@ pub const TIM10 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -9703,10 +12257,13 @@ pub const TIM10 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -9714,7 +12271,8 @@ pub const TIM10 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -9738,10 +12296,13 @@ pub const TIM10 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -9773,12 +12334,16 @@ pub const TIM10 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + /// Capture/Compare 1 selection + CC1S: u2 = 0, reserved1: u1 = 0, - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + /// Output Compare 1 preload enable + OC1PE: u1 = 0, + /// Output Compare 1 mode + OC1M: u3 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -9805,11 +12370,15 @@ pub const TIM10 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (input mode) + + /// capture/compare mode register (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -9835,12 +12404,16 @@ pub const TIM10 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, reserved1: u1 = 0, - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -9870,9 +12443,11 @@ pub const TIM10 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9890,9 +12465,11 @@ pub const TIM10 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9910,9 +12487,11 @@ pub const TIM10 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9930,9 +12509,11 @@ pub const TIM10 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9951,19 +12532,27 @@ pub const TIM10 = extern struct { padding1: u1 = 0, }); }; + +/// General purpose timer pub const TIM11 = extern struct { pub const Address: u32 = 0x40015400; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -9987,13 +12576,15 @@ pub const TIM11 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MMS: u3, // bit offset: 4 desc: Master mode selection + /// Master mode selection + MMS: u3 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -10020,10 +12611,13 @@ pub const TIM11 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -10055,10 +12649,13 @@ pub const TIM11 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -10066,7 +12663,8 @@ pub const TIM11 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -10090,10 +12688,13 @@ pub const TIM11 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -10125,12 +12726,16 @@ pub const TIM11 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + /// Capture/Compare 1 selection + CC1S: u2 = 0, reserved1: u1 = 0, - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + /// Output Compare 1 preload enable + OC1PE: u1 = 0, + /// Output Compare 1 mode + OC1M: u3 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -10157,11 +12762,15 @@ pub const TIM11 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (input mode) + + /// capture/compare mode register (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -10187,12 +12796,16 @@ pub const TIM11 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, reserved1: u1 = 0, - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -10222,9 +12835,11 @@ pub const TIM11 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10242,9 +12857,11 @@ pub const TIM11 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10262,9 +12879,11 @@ pub const TIM11 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10282,9 +12901,11 @@ pub const TIM11 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10303,19 +12924,27 @@ pub const TIM11 = extern struct { padding1: u1 = 0, }); }; + +/// General purpose timer pub const TIM13 = extern struct { pub const Address: u32 = 0x40001c00; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -10339,13 +12968,15 @@ pub const TIM13 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MMS: u3, // bit offset: 4 desc: Master mode selection + /// Master mode selection + MMS: u3 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -10372,10 +13003,13 @@ pub const TIM13 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -10407,10 +13041,13 @@ pub const TIM13 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -10418,7 +13055,8 @@ pub const TIM13 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -10442,10 +13080,13 @@ pub const TIM13 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -10477,12 +13118,16 @@ pub const TIM13 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + /// Capture/Compare 1 selection + CC1S: u2 = 0, reserved1: u1 = 0, - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + /// Output Compare 1 preload enable + OC1PE: u1 = 0, + /// Output Compare 1 mode + OC1M: u3 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -10509,11 +13154,15 @@ pub const TIM13 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (input mode) + + /// capture/compare mode register (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -10539,12 +13188,16 @@ pub const TIM13 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, reserved1: u1 = 0, - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -10574,9 +13227,11 @@ pub const TIM13 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10594,9 +13249,11 @@ pub const TIM13 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10614,9 +13271,11 @@ pub const TIM13 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10634,9 +13293,11 @@ pub const TIM13 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10655,19 +13316,27 @@ pub const TIM13 = extern struct { padding1: u1 = 0, }); }; + +/// General purpose timer pub const TIM14 = extern struct { pub const Address: u32 = 0x40002000; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -10691,13 +13360,15 @@ pub const TIM14 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MMS: u3, // bit offset: 4 desc: Master mode selection + /// Master mode selection + MMS: u3 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -10724,10 +13395,13 @@ pub const TIM14 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -10759,10 +13433,13 @@ pub const TIM14 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -10770,7 +13447,8 @@ pub const TIM14 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -10794,10 +13472,13 @@ pub const TIM14 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -10829,12 +13510,16 @@ pub const TIM14 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + /// Capture/Compare 1 selection + CC1S: u2 = 0, reserved1: u1 = 0, - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + /// Output Compare 1 preload enable + OC1PE: u1 = 0, + /// Output Compare 1 mode + OC1M: u3 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -10861,11 +13546,15 @@ pub const TIM14 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (input mode) + + /// capture/compare mode register (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -10891,12 +13580,16 @@ pub const TIM14 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, reserved1: u1 = 0, - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -10926,9 +13619,11 @@ pub const TIM14 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10946,9 +13641,11 @@ pub const TIM14 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10966,9 +13663,11 @@ pub const TIM14 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10986,9 +13685,11 @@ pub const TIM14 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11007,18 +13708,26 @@ pub const TIM14 = extern struct { padding1: u1 = 0, }); }; + +/// Basic timer pub const TIM6 = extern struct { pub const Address: u32 = 0x40001000; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + /// Auto-reload preload enable + ARPE: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -11044,13 +13753,15 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MMS: u3, // bit offset: 4 desc: Master mode selection + /// Master mode selection + MMS: u3 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -11077,9 +13788,11 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable + /// Update interrupt enable + UIE: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -11087,7 +13800,8 @@ pub const TIM6 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UDE: u1, // bit offset: 8 desc: Update DMA request enable + /// Update DMA request enable + UDE: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -11112,9 +13826,11 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag + /// Update interrupt flag + UIF: u1 = 0, padding31: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, @@ -11147,9 +13863,11 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation + /// Update generation + UG: u1 = 0, padding31: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, @@ -11182,9 +13900,11 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: Low counter value + /// Low counter value + CNT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11202,9 +13922,11 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11222,9 +13944,11 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Low Auto-reload value + /// Low Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11243,18 +13967,26 @@ pub const TIM6 = extern struct { padding1: u1 = 0, }); }; + +/// Basic timer pub const TIM7 = extern struct { pub const Address: u32 = 0x40001400; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + /// Auto-reload preload enable + ARPE: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -11280,13 +14012,15 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MMS: u3, // bit offset: 4 desc: Master mode selection + /// Master mode selection + MMS: u3 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -11313,9 +14047,11 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable + /// Update interrupt enable + UIE: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -11323,7 +14059,8 @@ pub const TIM7 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UDE: u1, // bit offset: 8 desc: Update DMA request enable + /// Update DMA request enable + UDE: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -11348,9 +14085,11 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag + /// Update interrupt flag + UIF: u1 = 0, padding31: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, @@ -11383,9 +14122,11 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation + /// Update generation + UG: u1 = 0, padding31: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, @@ -11418,9 +14159,11 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: Low counter value + /// Low counter value + CNT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11438,9 +14181,11 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11458,9 +14203,11 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Low Auto-reload value + /// Low Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11479,26 +14226,43 @@ pub const TIM7 = extern struct { padding1: u1 = 0, }); }; + +/// Inter integrated circuit pub const I2C1 = extern struct { pub const Address: u32 = 0x40005400; - // byte offset: 0 Control register 1 + + /// Control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - PE: u1, // bit offset: 0 desc: Peripheral enable - SMBUS: u1, // bit offset: 1 desc: SMBus mode + /// Peripheral enable + PE: u1 = 0, + /// SMBus mode + SMBUS: u1 = 0, reserved1: u1 = 0, - SMBTYPE: u1, // bit offset: 3 desc: SMBus type - ENARP: u1, // bit offset: 4 desc: ARP enable - ENPEC: u1, // bit offset: 5 desc: PEC enable - ENGC: u1, // bit offset: 6 desc: General call enable - NOSTRETCH: u1, // bit offset: 7 desc: Clock stretching disable (Slave mode) - START: u1, // bit offset: 8 desc: Start generation - STOP: u1, // bit offset: 9 desc: Stop generation - ACK: u1, // bit offset: 10 desc: Acknowledge enable - POS: u1, // bit offset: 11 desc: Acknowledge/PEC Position (for data reception) - PEC: u1, // bit offset: 12 desc: Packet error checking - ALERT: u1, // bit offset: 13 desc: SMBus alert + /// SMBus type + SMBTYPE: u1 = 0, + /// ARP enable + ENARP: u1 = 0, + /// PEC enable + ENPEC: u1 = 0, + /// General call enable + ENGC: u1 = 0, + /// Clock stretching disable (Slave mode) + NOSTRETCH: u1 = 0, + /// Start generation + START: u1 = 0, + /// Stop generation + STOP: u1 = 0, + /// Acknowledge enable + ACK: u1 = 0, + /// Acknowledge/PEC Position (for data reception) + POS: u1 = 0, + /// Packet error checking + PEC: u1 = 0, + /// SMBus alert + ALERT: u1 = 0, reserved2: u1 = 0, - SWRST: u1, // bit offset: 15 desc: Software reset + /// Software reset + SWRST: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11516,16 +14280,23 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Control register 2 + + /// Control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - FREQ: u6, // bit offset: 0 desc: Peripheral clock frequency + /// Peripheral clock frequency + FREQ: u6 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ITERREN: u1, // bit offset: 8 desc: Error interrupt enable - ITEVTEN: u1, // bit offset: 9 desc: Event interrupt enable - ITBUFEN: u1, // bit offset: 10 desc: Buffer interrupt enable - DMAEN: u1, // bit offset: 11 desc: DMA requests enable - LAST: u1, // bit offset: 12 desc: DMA last transfer + /// Error interrupt enable + ITERREN: u1 = 0, + /// Event interrupt enable + ITEVTEN: u1 = 0, + /// Buffer interrupt enable + ITBUFEN: u1 = 0, + /// DMA requests enable + DMAEN: u1 = 0, + /// DMA last transfer + LAST: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -11546,17 +14317,22 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Own address register 1 + + /// Own address register 1 pub const OAR1 = mmio(Address + 0x00000008, 32, packed struct { - ADD0: u1, // bit offset: 0 desc: Interface address - ADD7: u7, // bit offset: 1 desc: Interface address - ADD10: u2, // bit offset: 8 desc: Interface address + /// Interface address + ADD0: u1 = 0, + /// Interface address + ADD7: u7 = 0, + /// Interface address + ADD10: u2 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADDMODE: u1, // bit offset: 15 desc: Addressing mode (slave mode) + /// Addressing mode (slave mode) + ADDMODE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11574,10 +14350,13 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Own address register 2 + + /// Own address register 2 pub const OAR2 = mmio(Address + 0x0000000c, 32, packed struct { - ENDUAL: u1, // bit offset: 0 desc: Dual addressing mode enable - ADD2: u7, // bit offset: 1 desc: Interface address + /// Dual addressing mode enable + ENDUAL: u1 = 0, + /// Interface address + ADD2: u7 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -11603,9 +14382,11 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Data register + + /// Data register pub const DR = mmio(Address + 0x00000010, 32, packed struct { - DR: u8, // bit offset: 0 desc: 8-bit data register + /// 8-bit data register + DR: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -11631,24 +14412,39 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Status register 1 + + /// Status register 1 pub const SR1 = mmio(Address + 0x00000014, 32, packed struct { - SB: u1, // bit offset: 0 desc: Start bit (Master mode) - ADDR: u1, // bit offset: 1 desc: Address sent (master mode)/matched (slave mode) - BTF: u1, // bit offset: 2 desc: Byte transfer finished - ADD10: u1, // bit offset: 3 desc: 10-bit header sent (Master mode) - STOPF: u1, // bit offset: 4 desc: Stop detection (slave mode) + /// Start bit (Master mode) + SB: u1 = 0, + /// Address sent (master mode)/matched (slave mode) + ADDR: u1 = 0, + /// Byte transfer finished + BTF: u1 = 0, + /// 10-bit header sent (Master mode) + ADD10: u1 = 0, + /// Stop detection (slave mode) + STOPF: u1 = 0, reserved1: u1 = 0, - RxNE: u1, // bit offset: 6 desc: Data register not empty (receivers) - TxE: u1, // bit offset: 7 desc: Data register empty (transmitters) - BERR: u1, // bit offset: 8 desc: Bus error - ARLO: u1, // bit offset: 9 desc: Arbitration lost (master mode) - AF: u1, // bit offset: 10 desc: Acknowledge failure - OVR: u1, // bit offset: 11 desc: Overrun/Underrun - PECERR: u1, // bit offset: 12 desc: PEC Error in reception + /// Data register not empty (receivers) + RxNE: u1 = 0, + /// Data register empty (transmitters) + TxE: u1 = 0, + /// Bus error + BERR: u1 = 0, + /// Arbitration lost (master mode) + ARLO: u1 = 0, + /// Acknowledge failure + AF: u1 = 0, + /// Overrun/Underrun + OVR: u1 = 0, + /// PEC Error in reception + PECERR: u1 = 0, reserved2: u1 = 0, - TIMEOUT: u1, // bit offset: 14 desc: Timeout or Tlow error - SMBALERT: u1, // bit offset: 15 desc: SMBus alert + /// Timeout or Tlow error + TIMEOUT: u1 = 0, + /// SMBus alert + SMBALERT: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11666,17 +14462,26 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 Status register 2 + + /// Status register 2 pub const SR2 = mmio(Address + 0x00000018, 32, packed struct { - MSL: u1, // bit offset: 0 desc: Master/slave - BUSY: u1, // bit offset: 1 desc: Bus busy - TRA: u1, // bit offset: 2 desc: Transmitter/receiver + /// Master/slave + MSL: u1 = 0, + /// Bus busy + BUSY: u1 = 0, + /// Transmitter/receiver + TRA: u1 = 0, reserved1: u1 = 0, - GENCALL: u1, // bit offset: 4 desc: General call address (Slave mode) - SMBDEFAULT: u1, // bit offset: 5 desc: SMBus device default address (Slave mode) - SMBHOST: u1, // bit offset: 6 desc: SMBus host header (Slave mode) - DUALF: u1, // bit offset: 7 desc: Dual flag (Slave mode) - PEC: u8, // bit offset: 8 desc: acket error checking register + /// General call address (Slave mode) + GENCALL: u1 = 0, + /// SMBus device default address (Slave mode) + SMBDEFAULT: u1 = 0, + /// SMBus host header (Slave mode) + SMBHOST: u1 = 0, + /// Dual flag (Slave mode) + DUALF: u1 = 0, + /// acket error checking register + PEC: u8 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11694,13 +14499,17 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 Clock control register + + /// Clock control register pub const CCR = mmio(Address + 0x0000001c, 32, packed struct { - CCR: u12, // bit offset: 0 desc: Clock control register in Fast/Standard mode (Master mode) + /// Clock control register in Fast/Standard mode (Master mode) + CCR: u12 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DUTY: u1, // bit offset: 14 desc: Fast mode duty cycle - F_S: u1, // bit offset: 15 desc: I2C master mode selection + /// Fast mode duty cycle + DUTY: u1 = 0, + /// I2C master mode selection + F_S: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11718,9 +14527,11 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 TRISE register + + /// TRISE register pub const TRISE = mmio(Address + 0x00000020, 32, packed struct { - TRISE: u6, // bit offset: 0 desc: Maximum rise time in Fast/Standard mode (Master mode) + /// Maximum rise time in Fast/Standard mode (Master mode) + TRISE: u6 = 0, padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -11749,26 +14560,43 @@ pub const I2C1 = extern struct { padding1: u1 = 0, }); }; + +/// Inter integrated circuit pub const I2C2 = extern struct { pub const Address: u32 = 0x40005800; - // byte offset: 0 Control register 1 + + /// Control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - PE: u1, // bit offset: 0 desc: Peripheral enable - SMBUS: u1, // bit offset: 1 desc: SMBus mode + /// Peripheral enable + PE: u1 = 0, + /// SMBus mode + SMBUS: u1 = 0, reserved1: u1 = 0, - SMBTYPE: u1, // bit offset: 3 desc: SMBus type - ENARP: u1, // bit offset: 4 desc: ARP enable - ENPEC: u1, // bit offset: 5 desc: PEC enable - ENGC: u1, // bit offset: 6 desc: General call enable - NOSTRETCH: u1, // bit offset: 7 desc: Clock stretching disable (Slave mode) - START: u1, // bit offset: 8 desc: Start generation - STOP: u1, // bit offset: 9 desc: Stop generation - ACK: u1, // bit offset: 10 desc: Acknowledge enable - POS: u1, // bit offset: 11 desc: Acknowledge/PEC Position (for data reception) - PEC: u1, // bit offset: 12 desc: Packet error checking - ALERT: u1, // bit offset: 13 desc: SMBus alert + /// SMBus type + SMBTYPE: u1 = 0, + /// ARP enable + ENARP: u1 = 0, + /// PEC enable + ENPEC: u1 = 0, + /// General call enable + ENGC: u1 = 0, + /// Clock stretching disable (Slave mode) + NOSTRETCH: u1 = 0, + /// Start generation + START: u1 = 0, + /// Stop generation + STOP: u1 = 0, + /// Acknowledge enable + ACK: u1 = 0, + /// Acknowledge/PEC Position (for data reception) + POS: u1 = 0, + /// Packet error checking + PEC: u1 = 0, + /// SMBus alert + ALERT: u1 = 0, reserved2: u1 = 0, - SWRST: u1, // bit offset: 15 desc: Software reset + /// Software reset + SWRST: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11786,16 +14614,23 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Control register 2 + + /// Control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - FREQ: u6, // bit offset: 0 desc: Peripheral clock frequency + /// Peripheral clock frequency + FREQ: u6 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ITERREN: u1, // bit offset: 8 desc: Error interrupt enable - ITEVTEN: u1, // bit offset: 9 desc: Event interrupt enable - ITBUFEN: u1, // bit offset: 10 desc: Buffer interrupt enable - DMAEN: u1, // bit offset: 11 desc: DMA requests enable - LAST: u1, // bit offset: 12 desc: DMA last transfer + /// Error interrupt enable + ITERREN: u1 = 0, + /// Event interrupt enable + ITEVTEN: u1 = 0, + /// Buffer interrupt enable + ITBUFEN: u1 = 0, + /// DMA requests enable + DMAEN: u1 = 0, + /// DMA last transfer + LAST: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -11816,17 +14651,22 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Own address register 1 + + /// Own address register 1 pub const OAR1 = mmio(Address + 0x00000008, 32, packed struct { - ADD0: u1, // bit offset: 0 desc: Interface address - ADD7: u7, // bit offset: 1 desc: Interface address - ADD10: u2, // bit offset: 8 desc: Interface address + /// Interface address + ADD0: u1 = 0, + /// Interface address + ADD7: u7 = 0, + /// Interface address + ADD10: u2 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADDMODE: u1, // bit offset: 15 desc: Addressing mode (slave mode) + /// Addressing mode (slave mode) + ADDMODE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11844,10 +14684,13 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Own address register 2 + + /// Own address register 2 pub const OAR2 = mmio(Address + 0x0000000c, 32, packed struct { - ENDUAL: u1, // bit offset: 0 desc: Dual addressing mode enable - ADD2: u7, // bit offset: 1 desc: Interface address + /// Dual addressing mode enable + ENDUAL: u1 = 0, + /// Interface address + ADD2: u7 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -11873,9 +14716,11 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Data register + + /// Data register pub const DR = mmio(Address + 0x00000010, 32, packed struct { - DR: u8, // bit offset: 0 desc: 8-bit data register + /// 8-bit data register + DR: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -11901,24 +14746,39 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Status register 1 + + /// Status register 1 pub const SR1 = mmio(Address + 0x00000014, 32, packed struct { - SB: u1, // bit offset: 0 desc: Start bit (Master mode) - ADDR: u1, // bit offset: 1 desc: Address sent (master mode)/matched (slave mode) - BTF: u1, // bit offset: 2 desc: Byte transfer finished - ADD10: u1, // bit offset: 3 desc: 10-bit header sent (Master mode) - STOPF: u1, // bit offset: 4 desc: Stop detection (slave mode) + /// Start bit (Master mode) + SB: u1 = 0, + /// Address sent (master mode)/matched (slave mode) + ADDR: u1 = 0, + /// Byte transfer finished + BTF: u1 = 0, + /// 10-bit header sent (Master mode) + ADD10: u1 = 0, + /// Stop detection (slave mode) + STOPF: u1 = 0, reserved1: u1 = 0, - RxNE: u1, // bit offset: 6 desc: Data register not empty (receivers) - TxE: u1, // bit offset: 7 desc: Data register empty (transmitters) - BERR: u1, // bit offset: 8 desc: Bus error - ARLO: u1, // bit offset: 9 desc: Arbitration lost (master mode) - AF: u1, // bit offset: 10 desc: Acknowledge failure - OVR: u1, // bit offset: 11 desc: Overrun/Underrun - PECERR: u1, // bit offset: 12 desc: PEC Error in reception + /// Data register not empty (receivers) + RxNE: u1 = 0, + /// Data register empty (transmitters) + TxE: u1 = 0, + /// Bus error + BERR: u1 = 0, + /// Arbitration lost (master mode) + ARLO: u1 = 0, + /// Acknowledge failure + AF: u1 = 0, + /// Overrun/Underrun + OVR: u1 = 0, + /// PEC Error in reception + PECERR: u1 = 0, reserved2: u1 = 0, - TIMEOUT: u1, // bit offset: 14 desc: Timeout or Tlow error - SMBALERT: u1, // bit offset: 15 desc: SMBus alert + /// Timeout or Tlow error + TIMEOUT: u1 = 0, + /// SMBus alert + SMBALERT: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11936,17 +14796,26 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 Status register 2 + + /// Status register 2 pub const SR2 = mmio(Address + 0x00000018, 32, packed struct { - MSL: u1, // bit offset: 0 desc: Master/slave - BUSY: u1, // bit offset: 1 desc: Bus busy - TRA: u1, // bit offset: 2 desc: Transmitter/receiver + /// Master/slave + MSL: u1 = 0, + /// Bus busy + BUSY: u1 = 0, + /// Transmitter/receiver + TRA: u1 = 0, reserved1: u1 = 0, - GENCALL: u1, // bit offset: 4 desc: General call address (Slave mode) - SMBDEFAULT: u1, // bit offset: 5 desc: SMBus device default address (Slave mode) - SMBHOST: u1, // bit offset: 6 desc: SMBus host header (Slave mode) - DUALF: u1, // bit offset: 7 desc: Dual flag (Slave mode) - PEC: u8, // bit offset: 8 desc: acket error checking register + /// General call address (Slave mode) + GENCALL: u1 = 0, + /// SMBus device default address (Slave mode) + SMBDEFAULT: u1 = 0, + /// SMBus host header (Slave mode) + SMBHOST: u1 = 0, + /// Dual flag (Slave mode) + DUALF: u1 = 0, + /// acket error checking register + PEC: u8 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11964,13 +14833,17 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 Clock control register + + /// Clock control register pub const CCR = mmio(Address + 0x0000001c, 32, packed struct { - CCR: u12, // bit offset: 0 desc: Clock control register in Fast/Standard mode (Master mode) + /// Clock control register in Fast/Standard mode (Master mode) + CCR: u12 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DUTY: u1, // bit offset: 14 desc: Fast mode duty cycle - F_S: u1, // bit offset: 15 desc: I2C master mode selection + /// Fast mode duty cycle + DUTY: u1 = 0, + /// I2C master mode selection + F_S: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11988,9 +14861,11 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 TRISE register + + /// TRISE register pub const TRISE = mmio(Address + 0x00000020, 32, packed struct { - TRISE: u6, // bit offset: 0 desc: Maximum rise time in Fast/Standard mode (Master mode) + /// Maximum rise time in Fast/Standard mode (Master mode) + TRISE: u6 = 0, padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -12019,24 +14894,41 @@ pub const I2C2 = extern struct { padding1: u1 = 0, }); }; + +/// Serial peripheral interface pub const SPI1 = extern struct { pub const Address: u32 = 0x40013000; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CPHA: u1, // bit offset: 0 desc: Clock phase - CPOL: u1, // bit offset: 1 desc: Clock polarity - MSTR: u1, // bit offset: 2 desc: Master selection - BR: u3, // bit offset: 3 desc: Baud rate control - SPE: u1, // bit offset: 6 desc: SPI enable - LSBFIRST: u1, // bit offset: 7 desc: Frame format - SSI: u1, // bit offset: 8 desc: Internal slave select - SSM: u1, // bit offset: 9 desc: Software slave management - RXONLY: u1, // bit offset: 10 desc: Receive only - DFF: u1, // bit offset: 11 desc: Data frame format - CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next - CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable - BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode - BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Master selection + MSTR: u1 = 0, + /// Baud rate control + BR: u3 = 0, + /// SPI enable + SPE: u1 = 0, + /// Frame format + LSBFIRST: u1 = 0, + /// Internal slave select + SSI: u1 = 0, + /// Software slave management + SSM: u1 = 0, + /// Receive only + RXONLY: u1 = 0, + /// Data frame format + DFF: u1 = 0, + /// CRC transfer next + CRCNEXT: u1 = 0, + /// Hardware CRC calculation enable + CRCEN: u1 = 0, + /// Output enable in bidirectional mode + BIDIOE: u1 = 0, + /// Bidirectional data mode enable + BIDIMODE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12054,16 +14946,23 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable - TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable - SSOE: u1, // bit offset: 2 desc: SS output enable + /// Rx buffer DMA enable + RXDMAEN: u1 = 0, + /// Tx buffer DMA enable + TXDMAEN: u1 = 0, + /// SS output enable + SSOE: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ERRIE: u1, // bit offset: 5 desc: Error interrupt enable - RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable - TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable + /// Error interrupt enable + ERRIE: u1 = 0, + /// RX buffer not empty interrupt enable + RXNEIE: u1 = 0, + /// Tx buffer empty interrupt enable + TXEIE: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -12089,16 +14988,25 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 status register + + /// status register pub const SR = mmio(Address + 0x00000008, 32, packed struct { - RXNE: u1, // bit offset: 0 desc: Receive buffer not empty - TXE: u1, // bit offset: 1 desc: Transmit buffer empty - CHSIDE: u1, // bit offset: 2 desc: Channel side - UDR: u1, // bit offset: 3 desc: Underrun flag - CRCERR: u1, // bit offset: 4 desc: CRC error flag - MODF: u1, // bit offset: 5 desc: Mode fault - OVR: u1, // bit offset: 6 desc: Overrun flag - BSY: u1, // bit offset: 7 desc: Busy flag + /// Receive buffer not empty + RXNE: u1 = 0, + /// Transmit buffer empty + TXE: u1 = 0, + /// Channel side + CHSIDE: u1 = 0, + /// Underrun flag + UDR: u1 = 0, + /// CRC error flag + CRCERR: u1 = 0, + /// Mode fault + MODF: u1 = 0, + /// Overrun flag + OVR: u1 = 0, + /// Busy flag + BSY: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -12124,9 +15032,11 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 data register + + /// data register pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - DR: u16, // bit offset: 0 desc: Data register + /// Data register + DR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12144,9 +15054,11 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 CRC polynomial register + + /// CRC polynomial register pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + /// CRC polynomial register + CRCPOLY: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12164,9 +15076,11 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 RX CRC register + + /// RX CRC register pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - RxCRC: u16, // bit offset: 0 desc: Rx CRC register + /// Rx CRC register + RxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12184,9 +15098,11 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 TX CRC register + + /// TX CRC register pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - TxCRC: u16, // bit offset: 0 desc: Tx CRC register + /// Tx CRC register + TxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12204,17 +15120,26 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 I2S configuration register + + /// I2S configuration register pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) - DATLEN: u2, // bit offset: 1 desc: Data length to be transferred - CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity - I2SSTD: u2, // bit offset: 4 desc: I2S standard selection + /// Channel length (number of bits per audio channel) + CHLEN: u1 = 0, + /// Data length to be transferred + DATLEN: u2 = 0, + /// Steady state clock polarity + CKPOL: u1 = 0, + /// I2S standard selection + I2SSTD: u2 = 0, reserved1: u1 = 0, - PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization - I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode - I2SE: u1, // bit offset: 10 desc: I2S Enable - I2SMOD: u1, // bit offset: 11 desc: I2S mode selection + /// PCM frame synchronization + PCMSYNC: u1 = 0, + /// I2S configuration mode + I2SCFG: u2 = 0, + /// I2S Enable + I2SE: u1 = 0, + /// I2S mode selection + I2SMOD: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -12236,11 +15161,15 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 I2S prescaler register + + /// I2S prescaler register pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler - ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler - MCKOE: u1, // bit offset: 9 desc: Master clock output enable + /// I2S Linear prescaler + I2SDIV: u8 = 0, + /// Odd factor for the prescaler + ODD: u1 = 0, + /// Master clock output enable + MCKOE: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -12265,24 +15194,41 @@ pub const SPI1 = extern struct { padding1: u1 = 0, }); }; + +/// Serial peripheral interface pub const SPI2 = extern struct { pub const Address: u32 = 0x40003800; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CPHA: u1, // bit offset: 0 desc: Clock phase - CPOL: u1, // bit offset: 1 desc: Clock polarity - MSTR: u1, // bit offset: 2 desc: Master selection - BR: u3, // bit offset: 3 desc: Baud rate control - SPE: u1, // bit offset: 6 desc: SPI enable - LSBFIRST: u1, // bit offset: 7 desc: Frame format - SSI: u1, // bit offset: 8 desc: Internal slave select - SSM: u1, // bit offset: 9 desc: Software slave management - RXONLY: u1, // bit offset: 10 desc: Receive only - DFF: u1, // bit offset: 11 desc: Data frame format - CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next - CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable - BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode - BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Master selection + MSTR: u1 = 0, + /// Baud rate control + BR: u3 = 0, + /// SPI enable + SPE: u1 = 0, + /// Frame format + LSBFIRST: u1 = 0, + /// Internal slave select + SSI: u1 = 0, + /// Software slave management + SSM: u1 = 0, + /// Receive only + RXONLY: u1 = 0, + /// Data frame format + DFF: u1 = 0, + /// CRC transfer next + CRCNEXT: u1 = 0, + /// Hardware CRC calculation enable + CRCEN: u1 = 0, + /// Output enable in bidirectional mode + BIDIOE: u1 = 0, + /// Bidirectional data mode enable + BIDIMODE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12300,16 +15246,23 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable - TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable - SSOE: u1, // bit offset: 2 desc: SS output enable + /// Rx buffer DMA enable + RXDMAEN: u1 = 0, + /// Tx buffer DMA enable + TXDMAEN: u1 = 0, + /// SS output enable + SSOE: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ERRIE: u1, // bit offset: 5 desc: Error interrupt enable - RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable - TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable + /// Error interrupt enable + ERRIE: u1 = 0, + /// RX buffer not empty interrupt enable + RXNEIE: u1 = 0, + /// Tx buffer empty interrupt enable + TXEIE: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -12335,16 +15288,25 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 status register + + /// status register pub const SR = mmio(Address + 0x00000008, 32, packed struct { - RXNE: u1, // bit offset: 0 desc: Receive buffer not empty - TXE: u1, // bit offset: 1 desc: Transmit buffer empty - CHSIDE: u1, // bit offset: 2 desc: Channel side - UDR: u1, // bit offset: 3 desc: Underrun flag - CRCERR: u1, // bit offset: 4 desc: CRC error flag - MODF: u1, // bit offset: 5 desc: Mode fault - OVR: u1, // bit offset: 6 desc: Overrun flag - BSY: u1, // bit offset: 7 desc: Busy flag + /// Receive buffer not empty + RXNE: u1 = 0, + /// Transmit buffer empty + TXE: u1 = 0, + /// Channel side + CHSIDE: u1 = 0, + /// Underrun flag + UDR: u1 = 0, + /// CRC error flag + CRCERR: u1 = 0, + /// Mode fault + MODF: u1 = 0, + /// Overrun flag + OVR: u1 = 0, + /// Busy flag + BSY: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -12370,9 +15332,11 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 data register + + /// data register pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - DR: u16, // bit offset: 0 desc: Data register + /// Data register + DR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12390,9 +15354,11 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 CRC polynomial register + + /// CRC polynomial register pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + /// CRC polynomial register + CRCPOLY: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12410,9 +15376,11 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 RX CRC register + + /// RX CRC register pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - RxCRC: u16, // bit offset: 0 desc: Rx CRC register + /// Rx CRC register + RxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12430,9 +15398,11 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 TX CRC register + + /// TX CRC register pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - TxCRC: u16, // bit offset: 0 desc: Tx CRC register + /// Tx CRC register + TxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12450,17 +15420,26 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 I2S configuration register + + /// I2S configuration register pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) - DATLEN: u2, // bit offset: 1 desc: Data length to be transferred - CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity - I2SSTD: u2, // bit offset: 4 desc: I2S standard selection + /// Channel length (number of bits per audio channel) + CHLEN: u1 = 0, + /// Data length to be transferred + DATLEN: u2 = 0, + /// Steady state clock polarity + CKPOL: u1 = 0, + /// I2S standard selection + I2SSTD: u2 = 0, reserved1: u1 = 0, - PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization - I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode - I2SE: u1, // bit offset: 10 desc: I2S Enable - I2SMOD: u1, // bit offset: 11 desc: I2S mode selection + /// PCM frame synchronization + PCMSYNC: u1 = 0, + /// I2S configuration mode + I2SCFG: u2 = 0, + /// I2S Enable + I2SE: u1 = 0, + /// I2S mode selection + I2SMOD: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -12482,11 +15461,15 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 I2S prescaler register + + /// I2S prescaler register pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler - ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler - MCKOE: u1, // bit offset: 9 desc: Master clock output enable + /// I2S Linear prescaler + I2SDIV: u8 = 0, + /// Odd factor for the prescaler + ODD: u1 = 0, + /// Master clock output enable + MCKOE: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -12511,24 +15494,41 @@ pub const SPI2 = extern struct { padding1: u1 = 0, }); }; + +/// Serial peripheral interface pub const SPI3 = extern struct { pub const Address: u32 = 0x40003c00; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CPHA: u1, // bit offset: 0 desc: Clock phase - CPOL: u1, // bit offset: 1 desc: Clock polarity - MSTR: u1, // bit offset: 2 desc: Master selection - BR: u3, // bit offset: 3 desc: Baud rate control - SPE: u1, // bit offset: 6 desc: SPI enable - LSBFIRST: u1, // bit offset: 7 desc: Frame format - SSI: u1, // bit offset: 8 desc: Internal slave select - SSM: u1, // bit offset: 9 desc: Software slave management - RXONLY: u1, // bit offset: 10 desc: Receive only - DFF: u1, // bit offset: 11 desc: Data frame format - CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next - CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable - BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode - BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Master selection + MSTR: u1 = 0, + /// Baud rate control + BR: u3 = 0, + /// SPI enable + SPE: u1 = 0, + /// Frame format + LSBFIRST: u1 = 0, + /// Internal slave select + SSI: u1 = 0, + /// Software slave management + SSM: u1 = 0, + /// Receive only + RXONLY: u1 = 0, + /// Data frame format + DFF: u1 = 0, + /// CRC transfer next + CRCNEXT: u1 = 0, + /// Hardware CRC calculation enable + CRCEN: u1 = 0, + /// Output enable in bidirectional mode + BIDIOE: u1 = 0, + /// Bidirectional data mode enable + BIDIMODE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12546,16 +15546,23 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable - TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable - SSOE: u1, // bit offset: 2 desc: SS output enable + /// Rx buffer DMA enable + RXDMAEN: u1 = 0, + /// Tx buffer DMA enable + TXDMAEN: u1 = 0, + /// SS output enable + SSOE: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ERRIE: u1, // bit offset: 5 desc: Error interrupt enable - RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable - TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable + /// Error interrupt enable + ERRIE: u1 = 0, + /// RX buffer not empty interrupt enable + RXNEIE: u1 = 0, + /// Tx buffer empty interrupt enable + TXEIE: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -12581,16 +15588,25 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 status register + + /// status register pub const SR = mmio(Address + 0x00000008, 32, packed struct { - RXNE: u1, // bit offset: 0 desc: Receive buffer not empty - TXE: u1, // bit offset: 1 desc: Transmit buffer empty - CHSIDE: u1, // bit offset: 2 desc: Channel side - UDR: u1, // bit offset: 3 desc: Underrun flag - CRCERR: u1, // bit offset: 4 desc: CRC error flag - MODF: u1, // bit offset: 5 desc: Mode fault - OVR: u1, // bit offset: 6 desc: Overrun flag - BSY: u1, // bit offset: 7 desc: Busy flag + /// Receive buffer not empty + RXNE: u1 = 0, + /// Transmit buffer empty + TXE: u1 = 0, + /// Channel side + CHSIDE: u1 = 0, + /// Underrun flag + UDR: u1 = 0, + /// CRC error flag + CRCERR: u1 = 0, + /// Mode fault + MODF: u1 = 0, + /// Overrun flag + OVR: u1 = 0, + /// Busy flag + BSY: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -12616,9 +15632,11 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 data register + + /// data register pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - DR: u16, // bit offset: 0 desc: Data register + /// Data register + DR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12636,9 +15654,11 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 CRC polynomial register + + /// CRC polynomial register pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + /// CRC polynomial register + CRCPOLY: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12656,9 +15676,11 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 RX CRC register + + /// RX CRC register pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - RxCRC: u16, // bit offset: 0 desc: Rx CRC register + /// Rx CRC register + RxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12676,9 +15698,11 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 TX CRC register + + /// TX CRC register pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - TxCRC: u16, // bit offset: 0 desc: Tx CRC register + /// Tx CRC register + TxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12696,17 +15720,26 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 I2S configuration register + + /// I2S configuration register pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) - DATLEN: u2, // bit offset: 1 desc: Data length to be transferred - CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity - I2SSTD: u2, // bit offset: 4 desc: I2S standard selection + /// Channel length (number of bits per audio channel) + CHLEN: u1 = 0, + /// Data length to be transferred + DATLEN: u2 = 0, + /// Steady state clock polarity + CKPOL: u1 = 0, + /// I2S standard selection + I2SSTD: u2 = 0, reserved1: u1 = 0, - PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization - I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode - I2SE: u1, // bit offset: 10 desc: I2S Enable - I2SMOD: u1, // bit offset: 11 desc: I2S mode selection + /// PCM frame synchronization + PCMSYNC: u1 = 0, + /// I2S configuration mode + I2SCFG: u2 = 0, + /// I2S Enable + I2SE: u1 = 0, + /// I2S mode selection + I2SMOD: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -12728,11 +15761,15 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 I2S prescaler register + + /// I2S prescaler register pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler - ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler - MCKOE: u1, // bit offset: 9 desc: Master clock output enable + /// I2S Linear prescaler + I2SDIV: u8 = 0, + /// Odd factor for the prescaler + ODD: u1 = 0, + /// Master clock output enable + MCKOE: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -12757,20 +15794,33 @@ pub const SPI3 = extern struct { padding1: u1 = 0, }); }; + +/// Universal synchronous asynchronous receiver transmitter pub const USART1 = extern struct { pub const Address: u32 = 0x40013800; - // byte offset: 0 Status register + + /// Status register pub const SR = mmio(Address + 0x00000000, 32, packed struct { - PE: u1, // bit offset: 0 desc: Parity error - FE: u1, // bit offset: 1 desc: Framing error - NE: u1, // bit offset: 2 desc: Noise error flag - ORE: u1, // bit offset: 3 desc: Overrun error - IDLE: u1, // bit offset: 4 desc: IDLE line detected - RXNE: u1, // bit offset: 5 desc: Read data register not empty - TC: u1, // bit offset: 6 desc: Transmission complete - TXE: u1, // bit offset: 7 desc: Transmit data register empty - LBD: u1, // bit offset: 8 desc: LIN break detection flag - CTS: u1, // bit offset: 9 desc: CTS flag + /// Parity error + PE: u1 = 0, + /// Framing error + FE: u1 = 0, + /// Noise error flag + NE: u1 = 0, + /// Overrun error + ORE: u1 = 0, + /// IDLE line detected + IDLE: u1 = 0, + /// Read data register not empty + RXNE: u1 = 0, + /// Transmission complete + TC: u1 = 0, + /// Transmit data register empty + TXE: u1 = 0, + /// LIN break detection flag + LBD: u1 = 0, + /// CTS flag + CTS: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -12794,9 +15844,11 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Data register + + /// Data register pub const DR = mmio(Address + 0x00000004, 32, packed struct { - DR: u9, // bit offset: 0 desc: Data value + /// Data value + DR: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -12821,10 +15873,13 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Baud rate register + + /// Baud rate register pub const BRR = mmio(Address + 0x00000008, 32, packed struct { - DIV_Fraction: u4, // bit offset: 0 desc: fraction of USARTDIV - DIV_Mantissa: u12, // bit offset: 4 desc: mantissa of USARTDIV + /// fraction of USARTDIV + DIV_Fraction: u4 = 0, + /// mantissa of USARTDIV + DIV_Mantissa: u12 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12842,22 +15897,37 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Control register 1 + + /// Control register 1 pub const CR1 = mmio(Address + 0x0000000c, 32, packed struct { - SBK: u1, // bit offset: 0 desc: Send break - RWU: u1, // bit offset: 1 desc: Receiver wakeup - RE: u1, // bit offset: 2 desc: Receiver enable - TE: u1, // bit offset: 3 desc: Transmitter enable - IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable - RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable - TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable - TXEIE: u1, // bit offset: 7 desc: TXE interrupt enable - PEIE: u1, // bit offset: 8 desc: PE interrupt enable - PS: u1, // bit offset: 9 desc: Parity selection - PCE: u1, // bit offset: 10 desc: Parity control enable - WAKE: u1, // bit offset: 11 desc: Wakeup method - M: u1, // bit offset: 12 desc: Word length - UE: u1, // bit offset: 13 desc: USART enable + /// Send break + SBK: u1 = 0, + /// Receiver wakeup + RWU: u1 = 0, + /// Receiver enable + RE: u1 = 0, + /// Transmitter enable + TE: u1 = 0, + /// IDLE interrupt enable + IDLEIE: u1 = 0, + /// RXNE interrupt enable + RXNEIE: u1 = 0, + /// Transmission complete interrupt enable + TCIE: u1 = 0, + /// TXE interrupt enable + TXEIE: u1 = 0, + /// PE interrupt enable + PEIE: u1 = 0, + /// Parity selection + PS: u1 = 0, + /// Parity control enable + PCE: u1 = 0, + /// Wakeup method + WAKE: u1 = 0, + /// Word length + M: u1 = 0, + /// USART enable + UE: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -12877,19 +15947,29 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Control register 2 + + /// Control register 2 pub const CR2 = mmio(Address + 0x00000010, 32, packed struct { - ADD: u4, // bit offset: 0 desc: Address of the USART node + /// Address of the USART node + ADD: u4 = 0, reserved1: u1 = 0, - LBDL: u1, // bit offset: 5 desc: lin break detection length - LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable + /// lin break detection length + LBDL: u1 = 0, + /// LIN break detection interrupt enable + LBDIE: u1 = 0, reserved2: u1 = 0, - LBCL: u1, // bit offset: 8 desc: Last bit clock pulse - CPHA: u1, // bit offset: 9 desc: Clock phase - CPOL: u1, // bit offset: 10 desc: Clock polarity - CLKEN: u1, // bit offset: 11 desc: Clock enable - STOP: u2, // bit offset: 12 desc: STOP bits - LINEN: u1, // bit offset: 14 desc: LIN mode enable + /// Last bit clock pulse + LBCL: u1 = 0, + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Clock enable + CLKEN: u1 = 0, + /// STOP bits + STOP: u2 = 0, + /// LIN mode enable + LINEN: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -12908,19 +15988,31 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Control register 3 + + /// Control register 3 pub const CR3 = mmio(Address + 0x00000014, 32, packed struct { - EIE: u1, // bit offset: 0 desc: Error interrupt enable - IREN: u1, // bit offset: 1 desc: IrDA mode enable - IRLP: u1, // bit offset: 2 desc: IrDA low-power - HDSEL: u1, // bit offset: 3 desc: Half-duplex selection - NACK: u1, // bit offset: 4 desc: Smartcard NACK enable - SCEN: u1, // bit offset: 5 desc: Smartcard mode enable - DMAR: u1, // bit offset: 6 desc: DMA enable receiver - DMAT: u1, // bit offset: 7 desc: DMA enable transmitter - RTSE: u1, // bit offset: 8 desc: RTS enable - CTSE: u1, // bit offset: 9 desc: CTS enable - CTSIE: u1, // bit offset: 10 desc: CTS interrupt enable + /// Error interrupt enable + EIE: u1 = 0, + /// IrDA mode enable + IREN: u1 = 0, + /// IrDA low-power + IRLP: u1 = 0, + /// Half-duplex selection + HDSEL: u1 = 0, + /// Smartcard NACK enable + NACK: u1 = 0, + /// Smartcard mode enable + SCEN: u1 = 0, + /// DMA enable receiver + DMAR: u1 = 0, + /// DMA enable transmitter + DMAT: u1 = 0, + /// RTS enable + RTSE: u1 = 0, + /// CTS enable + CTSE: u1 = 0, + /// CTS interrupt enable + CTSIE: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -12943,10 +16035,13 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 Guard time and prescaler register + + /// Guard time and prescaler register pub const GTPR = mmio(Address + 0x00000018, 32, packed struct { - PSC: u8, // bit offset: 0 desc: Prescaler value - GT: u8, // bit offset: 8 desc: Guard time value + /// Prescaler value + PSC: u8 = 0, + /// Guard time value + GT: u8 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12965,20 +16060,33 @@ pub const USART1 = extern struct { padding1: u1 = 0, }); }; + +/// Universal synchronous asynchronous receiver transmitter pub const USART2 = extern struct { pub const Address: u32 = 0x40004400; - // byte offset: 0 Status register + + /// Status register pub const SR = mmio(Address + 0x00000000, 32, packed struct { - PE: u1, // bit offset: 0 desc: Parity error - FE: u1, // bit offset: 1 desc: Framing error - NE: u1, // bit offset: 2 desc: Noise error flag - ORE: u1, // bit offset: 3 desc: Overrun error - IDLE: u1, // bit offset: 4 desc: IDLE line detected - RXNE: u1, // bit offset: 5 desc: Read data register not empty - TC: u1, // bit offset: 6 desc: Transmission complete - TXE: u1, // bit offset: 7 desc: Transmit data register empty - LBD: u1, // bit offset: 8 desc: LIN break detection flag - CTS: u1, // bit offset: 9 desc: CTS flag + /// Parity error + PE: u1 = 0, + /// Framing error + FE: u1 = 0, + /// Noise error flag + NE: u1 = 0, + /// Overrun error + ORE: u1 = 0, + /// IDLE line detected + IDLE: u1 = 0, + /// Read data register not empty + RXNE: u1 = 0, + /// Transmission complete + TC: u1 = 0, + /// Transmit data register empty + TXE: u1 = 0, + /// LIN break detection flag + LBD: u1 = 0, + /// CTS flag + CTS: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -13002,9 +16110,11 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Data register + + /// Data register pub const DR = mmio(Address + 0x00000004, 32, packed struct { - DR: u9, // bit offset: 0 desc: Data value + /// Data value + DR: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -13029,10 +16139,13 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Baud rate register + + /// Baud rate register pub const BRR = mmio(Address + 0x00000008, 32, packed struct { - DIV_Fraction: u4, // bit offset: 0 desc: fraction of USARTDIV - DIV_Mantissa: u12, // bit offset: 4 desc: mantissa of USARTDIV + /// fraction of USARTDIV + DIV_Fraction: u4 = 0, + /// mantissa of USARTDIV + DIV_Mantissa: u12 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13050,22 +16163,37 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Control register 1 + + /// Control register 1 pub const CR1 = mmio(Address + 0x0000000c, 32, packed struct { - SBK: u1, // bit offset: 0 desc: Send break - RWU: u1, // bit offset: 1 desc: Receiver wakeup - RE: u1, // bit offset: 2 desc: Receiver enable - TE: u1, // bit offset: 3 desc: Transmitter enable - IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable - RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable - TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable - TXEIE: u1, // bit offset: 7 desc: TXE interrupt enable - PEIE: u1, // bit offset: 8 desc: PE interrupt enable - PS: u1, // bit offset: 9 desc: Parity selection - PCE: u1, // bit offset: 10 desc: Parity control enable - WAKE: u1, // bit offset: 11 desc: Wakeup method - M: u1, // bit offset: 12 desc: Word length - UE: u1, // bit offset: 13 desc: USART enable + /// Send break + SBK: u1 = 0, + /// Receiver wakeup + RWU: u1 = 0, + /// Receiver enable + RE: u1 = 0, + /// Transmitter enable + TE: u1 = 0, + /// IDLE interrupt enable + IDLEIE: u1 = 0, + /// RXNE interrupt enable + RXNEIE: u1 = 0, + /// Transmission complete interrupt enable + TCIE: u1 = 0, + /// TXE interrupt enable + TXEIE: u1 = 0, + /// PE interrupt enable + PEIE: u1 = 0, + /// Parity selection + PS: u1 = 0, + /// Parity control enable + PCE: u1 = 0, + /// Wakeup method + WAKE: u1 = 0, + /// Word length + M: u1 = 0, + /// USART enable + UE: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -13085,19 +16213,29 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Control register 2 + + /// Control register 2 pub const CR2 = mmio(Address + 0x00000010, 32, packed struct { - ADD: u4, // bit offset: 0 desc: Address of the USART node + /// Address of the USART node + ADD: u4 = 0, reserved1: u1 = 0, - LBDL: u1, // bit offset: 5 desc: lin break detection length - LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable + /// lin break detection length + LBDL: u1 = 0, + /// LIN break detection interrupt enable + LBDIE: u1 = 0, reserved2: u1 = 0, - LBCL: u1, // bit offset: 8 desc: Last bit clock pulse - CPHA: u1, // bit offset: 9 desc: Clock phase - CPOL: u1, // bit offset: 10 desc: Clock polarity - CLKEN: u1, // bit offset: 11 desc: Clock enable - STOP: u2, // bit offset: 12 desc: STOP bits - LINEN: u1, // bit offset: 14 desc: LIN mode enable + /// Last bit clock pulse + LBCL: u1 = 0, + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Clock enable + CLKEN: u1 = 0, + /// STOP bits + STOP: u2 = 0, + /// LIN mode enable + LINEN: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -13116,19 +16254,31 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Control register 3 + + /// Control register 3 pub const CR3 = mmio(Address + 0x00000014, 32, packed struct { - EIE: u1, // bit offset: 0 desc: Error interrupt enable - IREN: u1, // bit offset: 1 desc: IrDA mode enable - IRLP: u1, // bit offset: 2 desc: IrDA low-power - HDSEL: u1, // bit offset: 3 desc: Half-duplex selection - NACK: u1, // bit offset: 4 desc: Smartcard NACK enable - SCEN: u1, // bit offset: 5 desc: Smartcard mode enable - DMAR: u1, // bit offset: 6 desc: DMA enable receiver - DMAT: u1, // bit offset: 7 desc: DMA enable transmitter - RTSE: u1, // bit offset: 8 desc: RTS enable - CTSE: u1, // bit offset: 9 desc: CTS enable - CTSIE: u1, // bit offset: 10 desc: CTS interrupt enable + /// Error interrupt enable + EIE: u1 = 0, + /// IrDA mode enable + IREN: u1 = 0, + /// IrDA low-power + IRLP: u1 = 0, + /// Half-duplex selection + HDSEL: u1 = 0, + /// Smartcard NACK enable + NACK: u1 = 0, + /// Smartcard mode enable + SCEN: u1 = 0, + /// DMA enable receiver + DMAR: u1 = 0, + /// DMA enable transmitter + DMAT: u1 = 0, + /// RTS enable + RTSE: u1 = 0, + /// CTS enable + CTSE: u1 = 0, + /// CTS interrupt enable + CTSIE: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -13151,10 +16301,13 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 Guard time and prescaler register + + /// Guard time and prescaler register pub const GTPR = mmio(Address + 0x00000018, 32, packed struct { - PSC: u8, // bit offset: 0 desc: Prescaler value - GT: u8, // bit offset: 8 desc: Guard time value + /// Prescaler value + PSC: u8 = 0, + /// Guard time value + GT: u8 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13173,20 +16326,33 @@ pub const USART2 = extern struct { padding1: u1 = 0, }); }; + +/// Universal synchronous asynchronous receiver transmitter pub const USART3 = extern struct { pub const Address: u32 = 0x40004800; - // byte offset: 0 Status register + + /// Status register pub const SR = mmio(Address + 0x00000000, 32, packed struct { - PE: u1, // bit offset: 0 desc: Parity error - FE: u1, // bit offset: 1 desc: Framing error - NE: u1, // bit offset: 2 desc: Noise error flag - ORE: u1, // bit offset: 3 desc: Overrun error - IDLE: u1, // bit offset: 4 desc: IDLE line detected - RXNE: u1, // bit offset: 5 desc: Read data register not empty - TC: u1, // bit offset: 6 desc: Transmission complete - TXE: u1, // bit offset: 7 desc: Transmit data register empty - LBD: u1, // bit offset: 8 desc: LIN break detection flag - CTS: u1, // bit offset: 9 desc: CTS flag + /// Parity error + PE: u1 = 0, + /// Framing error + FE: u1 = 0, + /// Noise error flag + NE: u1 = 0, + /// Overrun error + ORE: u1 = 0, + /// IDLE line detected + IDLE: u1 = 0, + /// Read data register not empty + RXNE: u1 = 0, + /// Transmission complete + TC: u1 = 0, + /// Transmit data register empty + TXE: u1 = 0, + /// LIN break detection flag + LBD: u1 = 0, + /// CTS flag + CTS: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -13210,9 +16376,11 @@ pub const USART3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Data register + + /// Data register pub const DR = mmio(Address + 0x00000004, 32, packed struct { - DR: u9, // bit offset: 0 desc: Data value + /// Data value + DR: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -13237,10 +16405,13 @@ pub const USART3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Baud rate register + + /// Baud rate register pub const BRR = mmio(Address + 0x00000008, 32, packed struct { - DIV_Fraction: u4, // bit offset: 0 desc: fraction of USARTDIV - DIV_Mantissa: u12, // bit offset: 4 desc: mantissa of USARTDIV + /// fraction of USARTDIV + DIV_Fraction: u4 = 0, + /// mantissa of USARTDIV + DIV_Mantissa: u12 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13258,22 +16429,37 @@ pub const USART3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Control register 1 + + /// Control register 1 pub const CR1 = mmio(Address + 0x0000000c, 32, packed struct { - SBK: u1, // bit offset: 0 desc: Send break - RWU: u1, // bit offset: 1 desc: Receiver wakeup - RE: u1, // bit offset: 2 desc: Receiver enable - TE: u1, // bit offset: 3 desc: Transmitter enable - IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable - RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable - TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable - TXEIE: u1, // bit offset: 7 desc: TXE interrupt enable - PEIE: u1, // bit offset: 8 desc: PE interrupt enable - PS: u1, // bit offset: 9 desc: Parity selection - PCE: u1, // bit offset: 10 desc: Parity control enable - WAKE: u1, // bit offset: 11 desc: Wakeup method - M: u1, // bit offset: 12 desc: Word length - UE: u1, // bit offset: 13 desc: USART enable + /// Send break + SBK: u1 = 0, + /// Receiver wakeup + RWU: u1 = 0, + /// Receiver enable + RE: u1 = 0, + /// Transmitter enable + TE: u1 = 0, + /// IDLE interrupt enable + IDLEIE: u1 = 0, + /// RXNE interrupt enable + RXNEIE: u1 = 0, + /// Transmission complete interrupt enable + TCIE: u1 = 0, + /// TXE interrupt enable + TXEIE: u1 = 0, + /// PE interrupt enable + PEIE: u1 = 0, + /// Parity selection + PS: u1 = 0, + /// Parity control enable + PCE: u1 = 0, + /// Wakeup method + WAKE: u1 = 0, + /// Word length + M: u1 = 0, + /// USART enable + UE: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -13293,19 +16479,29 @@ pub const USART3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Control register 2 + + /// Control register 2 pub const CR2 = mmio(Address + 0x00000010, 32, packed struct { - ADD: u4, // bit offset: 0 desc: Address of the USART node + /// Address of the USART node + ADD: u4 = 0, reserved1: u1 = 0, - LBDL: u1, // bit offset: 5 desc: lin break detection length - LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable + /// lin break detection length + LBDL: u1 = 0, + /// LIN break detection interrupt enable + LBDIE: u1 = 0, reserved2: u1 = 0, - LBCL: u1, // bit offset: 8 desc: Last bit clock pulse - CPHA: u1, // bit offset: 9 desc: Clock phase - CPOL: u1, // bit offset: 10 desc: Clock polarity - CLKEN: u1, // bit offset: 11 desc: Clock enable - STOP: u2, // bit offset: 12 desc: STOP bits - LINEN: u1, // bit offset: 14 desc: LIN mode enable + /// Last bit clock pulse + LBCL: u1 = 0, + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Clock enable + CLKEN: u1 = 0, + /// STOP bits + STOP: u2 = 0, + /// LIN mode enable + LINEN: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -13324,19 +16520,31 @@ pub const USART3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Control register 3 + + /// Control register 3 pub const CR3 = mmio(Address + 0x00000014, 32, packed struct { - EIE: u1, // bit offset: 0 desc: Error interrupt enable - IREN: u1, // bit offset: 1 desc: IrDA mode enable - IRLP: u1, // bit offset: 2 desc: IrDA low-power - HDSEL: u1, // bit offset: 3 desc: Half-duplex selection - NACK: u1, // bit offset: 4 desc: Smartcard NACK enable - SCEN: u1, // bit offset: 5 desc: Smartcard mode enable - DMAR: u1, // bit offset: 6 desc: DMA enable receiver - DMAT: u1, // bit offset: 7 desc: DMA enable transmitter - RTSE: u1, // bit offset: 8 desc: RTS enable - CTSE: u1, // bit offset: 9 desc: CTS enable - CTSIE: u1, // bit offset: 10 desc: CTS interrupt enable + /// Error interrupt enable + EIE: u1 = 0, + /// IrDA mode enable + IREN: u1 = 0, + /// IrDA low-power + IRLP: u1 = 0, + /// Half-duplex selection + HDSEL: u1 = 0, + /// Smartcard NACK enable + NACK: u1 = 0, + /// Smartcard mode enable + SCEN: u1 = 0, + /// DMA enable receiver + DMAR: u1 = 0, + /// DMA enable transmitter + DMAT: u1 = 0, + /// RTS enable + RTSE: u1 = 0, + /// CTS enable + CTSE: u1 = 0, + /// CTS interrupt enable + CTSIE: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -13359,10 +16567,13 @@ pub const USART3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 Guard time and prescaler register + + /// Guard time and prescaler register pub const GTPR = mmio(Address + 0x00000018, 32, packed struct { - PSC: u8, // bit offset: 0 desc: Prescaler value - GT: u8, // bit offset: 8 desc: Guard time value + /// Prescaler value + PSC: u8 = 0, + /// Guard time value + GT: u8 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13381,15 +16592,23 @@ pub const USART3 = extern struct { padding1: u1 = 0, }); }; + +/// Analog to digital converter pub const ADC1 = extern struct { pub const Address: u32 = 0x40012400; - // byte offset: 0 status register + + /// status register pub const SR = mmio(Address + 0x00000000, 32, packed struct { - AWD: u1, // bit offset: 0 desc: Analog watchdog flag - EOC: u1, // bit offset: 1 desc: Regular channel end of conversion - JEOC: u1, // bit offset: 2 desc: Injected channel end of conversion - JSTRT: u1, // bit offset: 3 desc: Injected channel start flag - STRT: u1, // bit offset: 4 desc: Regular channel start flag + /// Analog watchdog flag + AWD: u1 = 0, + /// Regular channel end of conversion + EOC: u1 = 0, + /// Injected channel end of conversion + JEOC: u1 = 0, + /// Injected channel start flag + JSTRT: u1 = 0, + /// Regular channel start flag + STRT: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -13418,23 +16637,37 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000004, 32, packed struct { - AWDCH: u5, // bit offset: 0 desc: Analog watchdog channel select bits - EOCIE: u1, // bit offset: 5 desc: Interrupt enable for EOC - AWDIE: u1, // bit offset: 6 desc: Analog watchdog interrupt enable - JEOCIE: u1, // bit offset: 7 desc: Interrupt enable for injected channels - SCAN: u1, // bit offset: 8 desc: Scan mode - AWDSGL: u1, // bit offset: 9 desc: Enable the watchdog on a single channel in scan mode - JAUTO: u1, // bit offset: 10 desc: Automatic injected group conversion - DISCEN: u1, // bit offset: 11 desc: Discontinuous mode on regular channels - JDISCEN: u1, // bit offset: 12 desc: Discontinuous mode on injected channels - DISCNUM: u3, // bit offset: 13 desc: Discontinuous mode channel count - DUALMOD: u4, // bit offset: 16 desc: Dual mode selection + /// Analog watchdog channel select bits + AWDCH: u5 = 0, + /// Interrupt enable for EOC + EOCIE: u1 = 0, + /// Analog watchdog interrupt enable + AWDIE: u1 = 0, + /// Interrupt enable for injected channels + JEOCIE: u1 = 0, + /// Scan mode + SCAN: u1 = 0, + /// Enable the watchdog on a single channel in scan mode + AWDSGL: u1 = 0, + /// Automatic injected group conversion + JAUTO: u1 = 0, + /// Discontinuous mode on regular channels + DISCEN: u1 = 0, + /// Discontinuous mode on injected channels + JDISCEN: u1 = 0, + /// Discontinuous mode channel count + DISCNUM: u3 = 0, + /// Dual mode selection + DUALMOD: u4 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - JAWDEN: u1, // bit offset: 22 desc: Analog watchdog enable on injected channels - AWDEN: u1, // bit offset: 23 desc: Analog watchdog enable on regular channels + /// Analog watchdog enable on injected channels + JAWDEN: u1 = 0, + /// Analog watchdog enable on regular channels + AWDEN: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -13444,28 +16677,42 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000008, 32, packed struct { - ADON: u1, // bit offset: 0 desc: A/D converter ON / OFF - CONT: u1, // bit offset: 1 desc: Continuous conversion - CAL: u1, // bit offset: 2 desc: A/D calibration - RSTCAL: u1, // bit offset: 3 desc: Reset calibration + /// A/D converter ON / OFF + ADON: u1 = 0, + /// Continuous conversion + CONT: u1 = 0, + /// A/D calibration + CAL: u1 = 0, + /// Reset calibration + RSTCAL: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DMA: u1, // bit offset: 8 desc: Direct memory access mode + /// Direct memory access mode + DMA: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - ALIGN: u1, // bit offset: 11 desc: Data alignment - JEXTSEL: u3, // bit offset: 12 desc: External event select for injected group - JEXTTRIG: u1, // bit offset: 15 desc: External trigger conversion mode for injected channels + /// Data alignment + ALIGN: u1 = 0, + /// External event select for injected group + JEXTSEL: u3 = 0, + /// External trigger conversion mode for injected channels + JEXTTRIG: u1 = 0, reserved7: u1 = 0, - EXTSEL: u3, // bit offset: 17 desc: External event select for regular group - EXTTRIG: u1, // bit offset: 20 desc: External trigger conversion mode for regular channels - JSWSTART: u1, // bit offset: 21 desc: Start conversion of injected channels - SWSTART: u1, // bit offset: 22 desc: Start conversion of regular channels - TSVREFE: u1, // bit offset: 23 desc: Temperature sensor and VREFINT enable + /// External event select for regular group + EXTSEL: u3 = 0, + /// External trigger conversion mode for regular channels + EXTTRIG: u1 = 0, + /// Start conversion of injected channels + JSWSTART: u1 = 0, + /// Start conversion of regular channels + SWSTART: u1 = 0, + /// Temperature sensor and VREFINT enable + TSVREFE: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -13475,16 +16722,25 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 sample time register 1 + + /// sample time register 1 pub const SMPR1 = mmio(Address + 0x0000000c, 32, packed struct { - SMP10: u3, // bit offset: 0 desc: Channel 10 sample time selection - SMP11: u3, // bit offset: 3 desc: Channel 11 sample time selection - SMP12: u3, // bit offset: 6 desc: Channel 12 sample time selection - SMP13: u3, // bit offset: 9 desc: Channel 13 sample time selection - SMP14: u3, // bit offset: 12 desc: Channel 14 sample time selection - SMP15: u3, // bit offset: 15 desc: Channel 15 sample time selection - SMP16: u3, // bit offset: 18 desc: Channel 16 sample time selection - SMP17: u3, // bit offset: 21 desc: Channel 17 sample time selection + /// Channel 10 sample time selection + SMP10: u3 = 0, + /// Channel 11 sample time selection + SMP11: u3 = 0, + /// Channel 12 sample time selection + SMP12: u3 = 0, + /// Channel 13 sample time selection + SMP13: u3 = 0, + /// Channel 14 sample time selection + SMP14: u3 = 0, + /// Channel 15 sample time selection + SMP15: u3 = 0, + /// Channel 16 sample time selection + SMP16: u3 = 0, + /// Channel 17 sample time selection + SMP17: u3 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -13494,24 +16750,37 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 sample time register 2 + + /// sample time register 2 pub const SMPR2 = mmio(Address + 0x00000010, 32, packed struct { - SMP0: u3, // bit offset: 0 desc: Channel 0 sample time selection - SMP1: u3, // bit offset: 3 desc: Channel 1 sample time selection - SMP2: u3, // bit offset: 6 desc: Channel 2 sample time selection - SMP3: u3, // bit offset: 9 desc: Channel 3 sample time selection - SMP4: u3, // bit offset: 12 desc: Channel 4 sample time selection - SMP5: u3, // bit offset: 15 desc: Channel 5 sample time selection - SMP6: u3, // bit offset: 18 desc: Channel 6 sample time selection - SMP7: u3, // bit offset: 21 desc: Channel 7 sample time selection - SMP8: u3, // bit offset: 24 desc: Channel 8 sample time selection - SMP9: u3, // bit offset: 27 desc: Channel 9 sample time selection + /// Channel 0 sample time selection + SMP0: u3 = 0, + /// Channel 1 sample time selection + SMP1: u3 = 0, + /// Channel 2 sample time selection + SMP2: u3 = 0, + /// Channel 3 sample time selection + SMP3: u3 = 0, + /// Channel 4 sample time selection + SMP4: u3 = 0, + /// Channel 5 sample time selection + SMP5: u3 = 0, + /// Channel 6 sample time selection + SMP6: u3 = 0, + /// Channel 7 sample time selection + SMP7: u3 = 0, + /// Channel 8 sample time selection + SMP8: u3 = 0, + /// Channel 9 sample time selection + SMP9: u3 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 injected channel data offset register x + + /// injected channel data offset register x pub const JOFR1 = mmio(Address + 0x00000014, 32, packed struct { - JOFFSET1: u12, // bit offset: 0 desc: Data offset for injected channel x + /// Data offset for injected channel x + JOFFSET1: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -13533,9 +16802,11 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 injected channel data offset register x + + /// injected channel data offset register x pub const JOFR2 = mmio(Address + 0x00000018, 32, packed struct { - JOFFSET2: u12, // bit offset: 0 desc: Data offset for injected channel x + /// Data offset for injected channel x + JOFFSET2: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -13557,9 +16828,11 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 injected channel data offset register x + + /// injected channel data offset register x pub const JOFR3 = mmio(Address + 0x0000001c, 32, packed struct { - JOFFSET3: u12, // bit offset: 0 desc: Data offset for injected channel x + /// Data offset for injected channel x + JOFFSET3: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -13581,9 +16854,11 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 injected channel data offset register x + + /// injected channel data offset register x pub const JOFR4 = mmio(Address + 0x00000020, 32, packed struct { - JOFFSET4: u12, // bit offset: 0 desc: Data offset for injected channel x + /// Data offset for injected channel x + JOFFSET4: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -13605,9 +16880,11 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 watchdog higher threshold register + + /// watchdog higher threshold register pub const HTR = mmio(Address + 0x00000024, 32, packed struct { - HT: u12, // bit offset: 0 desc: Analog watchdog higher threshold + /// Analog watchdog higher threshold + HT: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -13629,9 +16906,11 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 watchdog lower threshold register + + /// watchdog lower threshold register pub const LTR = mmio(Address + 0x00000028, 32, packed struct { - LT: u12, // bit offset: 0 desc: Analog watchdog lower threshold + /// Analog watchdog lower threshold + LT: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -13653,13 +16932,19 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 regular sequence register 1 + + /// regular sequence register 1 pub const SQR1 = mmio(Address + 0x0000002c, 32, packed struct { - SQ13: u5, // bit offset: 0 desc: 13th conversion in regular sequence - SQ14: u5, // bit offset: 5 desc: 14th conversion in regular sequence - SQ15: u5, // bit offset: 10 desc: 15th conversion in regular sequence - SQ16: u5, // bit offset: 15 desc: 16th conversion in regular sequence - L: u4, // bit offset: 20 desc: Regular channel sequence length + /// 13th conversion in regular sequence + SQ13: u5 = 0, + /// 14th conversion in regular sequence + SQ14: u5 = 0, + /// 15th conversion in regular sequence + SQ15: u5 = 0, + /// 16th conversion in regular sequence + SQ16: u5 = 0, + /// Regular channel sequence length + L: u4 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -13669,35 +16954,55 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 regular sequence register 2 + + /// regular sequence register 2 pub const SQR2 = mmio(Address + 0x00000030, 32, packed struct { - SQ7: u5, // bit offset: 0 desc: 7th conversion in regular sequence - SQ8: u5, // bit offset: 5 desc: 8th conversion in regular sequence - SQ9: u5, // bit offset: 10 desc: 9th conversion in regular sequence - SQ10: u5, // bit offset: 15 desc: 10th conversion in regular sequence - SQ11: u5, // bit offset: 20 desc: 11th conversion in regular sequence - SQ12: u5, // bit offset: 25 desc: 12th conversion in regular sequence + /// 7th conversion in regular sequence + SQ7: u5 = 0, + /// 8th conversion in regular sequence + SQ8: u5 = 0, + /// 9th conversion in regular sequence + SQ9: u5 = 0, + /// 10th conversion in regular sequence + SQ10: u5 = 0, + /// 11th conversion in regular sequence + SQ11: u5 = 0, + /// 12th conversion in regular sequence + SQ12: u5 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 regular sequence register 3 + + /// regular sequence register 3 pub const SQR3 = mmio(Address + 0x00000034, 32, packed struct { - SQ1: u5, // bit offset: 0 desc: 1st conversion in regular sequence - SQ2: u5, // bit offset: 5 desc: 2nd conversion in regular sequence - SQ3: u5, // bit offset: 10 desc: 3rd conversion in regular sequence - SQ4: u5, // bit offset: 15 desc: 4th conversion in regular sequence - SQ5: u5, // bit offset: 20 desc: 5th conversion in regular sequence - SQ6: u5, // bit offset: 25 desc: 6th conversion in regular sequence + /// 1st conversion in regular sequence + SQ1: u5 = 0, + /// 2nd conversion in regular sequence + SQ2: u5 = 0, + /// 3rd conversion in regular sequence + SQ3: u5 = 0, + /// 4th conversion in regular sequence + SQ4: u5 = 0, + /// 5th conversion in regular sequence + SQ5: u5 = 0, + /// 6th conversion in regular sequence + SQ6: u5 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 injected sequence register + + /// injected sequence register pub const JSQR = mmio(Address + 0x00000038, 32, packed struct { - JSQ1: u5, // bit offset: 0 desc: 1st conversion in injected sequence - JSQ2: u5, // bit offset: 5 desc: 2nd conversion in injected sequence - JSQ3: u5, // bit offset: 10 desc: 3rd conversion in injected sequence - JSQ4: u5, // bit offset: 15 desc: 4th conversion in injected sequence - JL: u2, // bit offset: 20 desc: Injected sequence length + /// 1st conversion in injected sequence + JSQ1: u5 = 0, + /// 2nd conversion in injected sequence + JSQ2: u5 = 0, + /// 3rd conversion in injected sequence + JSQ3: u5 = 0, + /// 4th conversion in injected sequence + JSQ4: u5 = 0, + /// Injected sequence length + JL: u2 = 0, padding10: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, @@ -13709,9 +17014,11 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 injected data register x + + /// injected data register x pub const JDR1 = mmio(Address + 0x0000003c, 32, packed struct { - JDATA: u16, // bit offset: 0 desc: Injected data + /// Injected data + JDATA: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13729,9 +17036,11 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 injected data register x + + /// injected data register x pub const JDR2 = mmio(Address + 0x00000040, 32, packed struct { - JDATA: u16, // bit offset: 0 desc: Injected data + /// Injected data + JDATA: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13749,9 +17058,11 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 injected data register x + + /// injected data register x pub const JDR3 = mmio(Address + 0x00000044, 32, packed struct { - JDATA: u16, // bit offset: 0 desc: Injected data + /// Injected data + JDATA: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13769,9 +17080,11 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 injected data register x + + /// injected data register x pub const JDR4 = mmio(Address + 0x00000048, 32, packed struct { - JDATA: u16, // bit offset: 0 desc: Injected data + /// Injected data + JDATA: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13789,21 +17102,32 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 regular data register + + /// regular data register pub const DR = mmio(Address + 0x0000004c, 32, packed struct { - DATA: u16, // bit offset: 0 desc: Regular data - ADC2DATA: u16, // bit offset: 16 desc: ADC2 data + /// Regular data + DATA: u16 = 0, + /// ADC2 data + ADC2DATA: u16 = 0, }); }; + +/// Analog to digital converter pub const ADC2 = extern struct { pub const Address: u32 = 0x40012800; - // byte offset: 0 status register + + /// status register pub const SR = mmio(Address + 0x00000000, 32, packed struct { - AWD: u1, // bit offset: 0 desc: Analog watchdog flag - EOC: u1, // bit offset: 1 desc: Regular channel end of conversion - JEOC: u1, // bit offset: 2 desc: Injected channel end of conversion - JSTRT: u1, // bit offset: 3 desc: Injected channel start flag - STRT: u1, // bit offset: 4 desc: Regular channel start flag + /// Analog watchdog flag + AWD: u1 = 0, + /// Regular channel end of conversion + EOC: u1 = 0, + /// Injected channel end of conversion + JEOC: u1 = 0, + /// Injected channel start flag + JSTRT: u1 = 0, + /// Regular channel start flag + STRT: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -13832,26 +17156,39 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000004, 32, packed struct { - AWDCH: u5, // bit offset: 0 desc: Analog watchdog channel select bits - EOCIE: u1, // bit offset: 5 desc: Interrupt enable for EOC - AWDIE: u1, // bit offset: 6 desc: Analog watchdog interrupt enable - JEOCIE: u1, // bit offset: 7 desc: Interrupt enable for injected channels - SCAN: u1, // bit offset: 8 desc: Scan mode - AWDSGL: u1, // bit offset: 9 desc: Enable the watchdog on a single channel in scan mode - JAUTO: u1, // bit offset: 10 desc: Automatic injected group conversion - DISCEN: u1, // bit offset: 11 desc: Discontinuous mode on regular channels - JDISCEN: u1, // bit offset: 12 desc: Discontinuous mode on injected channels - DISCNUM: u3, // bit offset: 13 desc: Discontinuous mode channel count + /// Analog watchdog channel select bits + AWDCH: u5 = 0, + /// Interrupt enable for EOC + EOCIE: u1 = 0, + /// Analog watchdog interrupt enable + AWDIE: u1 = 0, + /// Interrupt enable for injected channels + JEOCIE: u1 = 0, + /// Scan mode + SCAN: u1 = 0, + /// Enable the watchdog on a single channel in scan mode + AWDSGL: u1 = 0, + /// Automatic injected group conversion + JAUTO: u1 = 0, + /// Discontinuous mode on regular channels + DISCEN: u1 = 0, + /// Discontinuous mode on injected channels + JDISCEN: u1 = 0, + /// Discontinuous mode channel count + DISCNUM: u3 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - JAWDEN: u1, // bit offset: 22 desc: Analog watchdog enable on injected channels - AWDEN: u1, // bit offset: 23 desc: Analog watchdog enable on regular channels + /// Analog watchdog enable on injected channels + JAWDEN: u1 = 0, + /// Analog watchdog enable on regular channels + AWDEN: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -13861,28 +17198,42 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000008, 32, packed struct { - ADON: u1, // bit offset: 0 desc: A/D converter ON / OFF - CONT: u1, // bit offset: 1 desc: Continuous conversion - CAL: u1, // bit offset: 2 desc: A/D calibration - RSTCAL: u1, // bit offset: 3 desc: Reset calibration + /// A/D converter ON / OFF + ADON: u1 = 0, + /// Continuous conversion + CONT: u1 = 0, + /// A/D calibration + CAL: u1 = 0, + /// Reset calibration + RSTCAL: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DMA: u1, // bit offset: 8 desc: Direct memory access mode + /// Direct memory access mode + DMA: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - ALIGN: u1, // bit offset: 11 desc: Data alignment - JEXTSEL: u3, // bit offset: 12 desc: External event select for injected group - JEXTTRIG: u1, // bit offset: 15 desc: External trigger conversion mode for injected channels + /// Data alignment + ALIGN: u1 = 0, + /// External event select for injected group + JEXTSEL: u3 = 0, + /// External trigger conversion mode for injected channels + JEXTTRIG: u1 = 0, reserved7: u1 = 0, - EXTSEL: u3, // bit offset: 17 desc: External event select for regular group - EXTTRIG: u1, // bit offset: 20 desc: External trigger conversion mode for regular channels - JSWSTART: u1, // bit offset: 21 desc: Start conversion of injected channels - SWSTART: u1, // bit offset: 22 desc: Start conversion of regular channels - TSVREFE: u1, // bit offset: 23 desc: Temperature sensor and VREFINT enable + /// External event select for regular group + EXTSEL: u3 = 0, + /// External trigger conversion mode for regular channels + EXTTRIG: u1 = 0, + /// Start conversion of injected channels + JSWSTART: u1 = 0, + /// Start conversion of regular channels + SWSTART: u1 = 0, + /// Temperature sensor and VREFINT enable + TSVREFE: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -13892,16 +17243,25 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 sample time register 1 + + /// sample time register 1 pub const SMPR1 = mmio(Address + 0x0000000c, 32, packed struct { - SMP10: u3, // bit offset: 0 desc: Channel 10 sample time selection - SMP11: u3, // bit offset: 3 desc: Channel 11 sample time selection - SMP12: u3, // bit offset: 6 desc: Channel 12 sample time selection - SMP13: u3, // bit offset: 9 desc: Channel 13 sample time selection - SMP14: u3, // bit offset: 12 desc: Channel 14 sample time selection - SMP15: u3, // bit offset: 15 desc: Channel 15 sample time selection - SMP16: u3, // bit offset: 18 desc: Channel 16 sample time selection - SMP17: u3, // bit offset: 21 desc: Channel 17 sample time selection + /// Channel 10 sample time selection + SMP10: u3 = 0, + /// Channel 11 sample time selection + SMP11: u3 = 0, + /// Channel 12 sample time selection + SMP12: u3 = 0, + /// Channel 13 sample time selection + SMP13: u3 = 0, + /// Channel 14 sample time selection + SMP14: u3 = 0, + /// Channel 15 sample time selection + SMP15: u3 = 0, + /// Channel 16 sample time selection + SMP16: u3 = 0, + /// Channel 17 sample time selection + SMP17: u3 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -13911,24 +17271,37 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 sample time register 2 + + /// sample time register 2 pub const SMPR2 = mmio(Address + 0x00000010, 32, packed struct { - SMP0: u3, // bit offset: 0 desc: Channel 0 sample time selection - SMP1: u3, // bit offset: 3 desc: Channel 1 sample time selection - SMP2: u3, // bit offset: 6 desc: Channel 2 sample time selection - SMP3: u3, // bit offset: 9 desc: Channel 3 sample time selection - SMP4: u3, // bit offset: 12 desc: Channel 4 sample time selection - SMP5: u3, // bit offset: 15 desc: Channel 5 sample time selection - SMP6: u3, // bit offset: 18 desc: Channel 6 sample time selection - SMP7: u3, // bit offset: 21 desc: Channel 7 sample time selection - SMP8: u3, // bit offset: 24 desc: Channel 8 sample time selection - SMP9: u3, // bit offset: 27 desc: Channel 9 sample time selection + /// Channel 0 sample time selection + SMP0: u3 = 0, + /// Channel 1 sample time selection + SMP1: u3 = 0, + /// Channel 2 sample time selection + SMP2: u3 = 0, + /// Channel 3 sample time selection + SMP3: u3 = 0, + /// Channel 4 sample time selection + SMP4: u3 = 0, + /// Channel 5 sample time selection + SMP5: u3 = 0, + /// Channel 6 sample time selection + SMP6: u3 = 0, + /// Channel 7 sample time selection + SMP7: u3 = 0, + /// Channel 8 sample time selection + SMP8: u3 = 0, + /// Channel 9 sample time selection + SMP9: u3 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 injected channel data offset register x + + /// injected channel data offset register x pub const JOFR1 = mmio(Address + 0x00000014, 32, packed struct { - JOFFSET1: u12, // bit offset: 0 desc: Data offset for injected channel x + /// Data offset for injected channel x + JOFFSET1: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -13950,9 +17323,11 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 injected channel data offset register x + + /// injected channel data offset register x pub const JOFR2 = mmio(Address + 0x00000018, 32, packed struct { - JOFFSET2: u12, // bit offset: 0 desc: Data offset for injected channel x + /// Data offset for injected channel x + JOFFSET2: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -13974,9 +17349,11 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 injected channel data offset register x + + /// injected channel data offset register x pub const JOFR3 = mmio(Address + 0x0000001c, 32, packed struct { - JOFFSET3: u12, // bit offset: 0 desc: Data offset for injected channel x + /// Data offset for injected channel x + JOFFSET3: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -13998,9 +17375,11 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 injected channel data offset register x + + /// injected channel data offset register x pub const JOFR4 = mmio(Address + 0x00000020, 32, packed struct { - JOFFSET4: u12, // bit offset: 0 desc: Data offset for injected channel x + /// Data offset for injected channel x + JOFFSET4: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -14022,9 +17401,11 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 watchdog higher threshold register + + /// watchdog higher threshold register pub const HTR = mmio(Address + 0x00000024, 32, packed struct { - HT: u12, // bit offset: 0 desc: Analog watchdog higher threshold + /// Analog watchdog higher threshold + HT: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -14046,9 +17427,11 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 watchdog lower threshold register + + /// watchdog lower threshold register pub const LTR = mmio(Address + 0x00000028, 32, packed struct { - LT: u12, // bit offset: 0 desc: Analog watchdog lower threshold + /// Analog watchdog lower threshold + LT: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -14070,13 +17453,19 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 regular sequence register 1 + + /// regular sequence register 1 pub const SQR1 = mmio(Address + 0x0000002c, 32, packed struct { - SQ13: u5, // bit offset: 0 desc: 13th conversion in regular sequence - SQ14: u5, // bit offset: 5 desc: 14th conversion in regular sequence - SQ15: u5, // bit offset: 10 desc: 15th conversion in regular sequence - SQ16: u5, // bit offset: 15 desc: 16th conversion in regular sequence - L: u4, // bit offset: 20 desc: Regular channel sequence length + /// 13th conversion in regular sequence + SQ13: u5 = 0, + /// 14th conversion in regular sequence + SQ14: u5 = 0, + /// 15th conversion in regular sequence + SQ15: u5 = 0, + /// 16th conversion in regular sequence + SQ16: u5 = 0, + /// Regular channel sequence length + L: u4 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -14086,35 +17475,55 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 regular sequence register 2 + + /// regular sequence register 2 pub const SQR2 = mmio(Address + 0x00000030, 32, packed struct { - SQ7: u5, // bit offset: 0 desc: 7th conversion in regular sequence - SQ8: u5, // bit offset: 5 desc: 8th conversion in regular sequence - SQ9: u5, // bit offset: 10 desc: 9th conversion in regular sequence - SQ10: u5, // bit offset: 15 desc: 10th conversion in regular sequence - SQ11: u5, // bit offset: 20 desc: 11th conversion in regular sequence - SQ12: u5, // bit offset: 25 desc: 12th conversion in regular sequence + /// 7th conversion in regular sequence + SQ7: u5 = 0, + /// 8th conversion in regular sequence + SQ8: u5 = 0, + /// 9th conversion in regular sequence + SQ9: u5 = 0, + /// 10th conversion in regular sequence + SQ10: u5 = 0, + /// 11th conversion in regular sequence + SQ11: u5 = 0, + /// 12th conversion in regular sequence + SQ12: u5 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 regular sequence register 3 + + /// regular sequence register 3 pub const SQR3 = mmio(Address + 0x00000034, 32, packed struct { - SQ1: u5, // bit offset: 0 desc: 1st conversion in regular sequence - SQ2: u5, // bit offset: 5 desc: 2nd conversion in regular sequence - SQ3: u5, // bit offset: 10 desc: 3rd conversion in regular sequence - SQ4: u5, // bit offset: 15 desc: 4th conversion in regular sequence - SQ5: u5, // bit offset: 20 desc: 5th conversion in regular sequence - SQ6: u5, // bit offset: 25 desc: 6th conversion in regular sequence + /// 1st conversion in regular sequence + SQ1: u5 = 0, + /// 2nd conversion in regular sequence + SQ2: u5 = 0, + /// 3rd conversion in regular sequence + SQ3: u5 = 0, + /// 4th conversion in regular sequence + SQ4: u5 = 0, + /// 5th conversion in regular sequence + SQ5: u5 = 0, + /// 6th conversion in regular sequence + SQ6: u5 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 injected sequence register + + /// injected sequence register pub const JSQR = mmio(Address + 0x00000038, 32, packed struct { - JSQ1: u5, // bit offset: 0 desc: 1st conversion in injected sequence - JSQ2: u5, // bit offset: 5 desc: 2nd conversion in injected sequence - JSQ3: u5, // bit offset: 10 desc: 3rd conversion in injected sequence - JSQ4: u5, // bit offset: 15 desc: 4th conversion in injected sequence - JL: u2, // bit offset: 20 desc: Injected sequence length + /// 1st conversion in injected sequence + JSQ1: u5 = 0, + /// 2nd conversion in injected sequence + JSQ2: u5 = 0, + /// 3rd conversion in injected sequence + JSQ3: u5 = 0, + /// 4th conversion in injected sequence + JSQ4: u5 = 0, + /// Injected sequence length + JL: u2 = 0, padding10: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, @@ -14126,9 +17535,11 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 injected data register x + + /// injected data register x pub const JDR1 = mmio(Address + 0x0000003c, 32, packed struct { - JDATA: u16, // bit offset: 0 desc: Injected data + /// Injected data + JDATA: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14146,9 +17557,11 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 injected data register x + + /// injected data register x pub const JDR2 = mmio(Address + 0x00000040, 32, packed struct { - JDATA: u16, // bit offset: 0 desc: Injected data + /// Injected data + JDATA: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14166,9 +17579,11 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 injected data register x + + /// injected data register x pub const JDR3 = mmio(Address + 0x00000044, 32, packed struct { - JDATA: u16, // bit offset: 0 desc: Injected data + /// Injected data + JDATA: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14186,9 +17601,11 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 injected data register x + + /// injected data register x pub const JDR4 = mmio(Address + 0x00000048, 32, packed struct { - JDATA: u16, // bit offset: 0 desc: Injected data + /// Injected data + JDATA: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14206,9 +17623,11 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 regular data register + + /// regular data register pub const DR = mmio(Address + 0x0000004c, 32, packed struct { - DATA: u16, // bit offset: 0 desc: Regular data + /// Regular data + DATA: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14227,15 +17646,23 @@ pub const ADC2 = extern struct { padding1: u1 = 0, }); }; + +/// Analog to digital converter pub const ADC3 = extern struct { pub const Address: u32 = 0x40013c00; - // byte offset: 0 status register + + /// status register pub const SR = mmio(Address + 0x00000000, 32, packed struct { - AWD: u1, // bit offset: 0 desc: Analog watchdog flag - EOC: u1, // bit offset: 1 desc: Regular channel end of conversion - JEOC: u1, // bit offset: 2 desc: Injected channel end of conversion - JSTRT: u1, // bit offset: 3 desc: Injected channel start flag - STRT: u1, // bit offset: 4 desc: Regular channel start flag + /// Analog watchdog flag + AWD: u1 = 0, + /// Regular channel end of conversion + EOC: u1 = 0, + /// Injected channel end of conversion + JEOC: u1 = 0, + /// Injected channel start flag + JSTRT: u1 = 0, + /// Regular channel start flag + STRT: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -14264,26 +17691,39 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000004, 32, packed struct { - AWDCH: u5, // bit offset: 0 desc: Analog watchdog channel select bits - EOCIE: u1, // bit offset: 5 desc: Interrupt enable for EOC - AWDIE: u1, // bit offset: 6 desc: Analog watchdog interrupt enable - JEOCIE: u1, // bit offset: 7 desc: Interrupt enable for injected channels - SCAN: u1, // bit offset: 8 desc: Scan mode - AWDSGL: u1, // bit offset: 9 desc: Enable the watchdog on a single channel in scan mode - JAUTO: u1, // bit offset: 10 desc: Automatic injected group conversion - DISCEN: u1, // bit offset: 11 desc: Discontinuous mode on regular channels - JDISCEN: u1, // bit offset: 12 desc: Discontinuous mode on injected channels - DISCNUM: u3, // bit offset: 13 desc: Discontinuous mode channel count + /// Analog watchdog channel select bits + AWDCH: u5 = 0, + /// Interrupt enable for EOC + EOCIE: u1 = 0, + /// Analog watchdog interrupt enable + AWDIE: u1 = 0, + /// Interrupt enable for injected channels + JEOCIE: u1 = 0, + /// Scan mode + SCAN: u1 = 0, + /// Enable the watchdog on a single channel in scan mode + AWDSGL: u1 = 0, + /// Automatic injected group conversion + JAUTO: u1 = 0, + /// Discontinuous mode on regular channels + DISCEN: u1 = 0, + /// Discontinuous mode on injected channels + JDISCEN: u1 = 0, + /// Discontinuous mode channel count + DISCNUM: u3 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - JAWDEN: u1, // bit offset: 22 desc: Analog watchdog enable on injected channels - AWDEN: u1, // bit offset: 23 desc: Analog watchdog enable on regular channels + /// Analog watchdog enable on injected channels + JAWDEN: u1 = 0, + /// Analog watchdog enable on regular channels + AWDEN: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -14293,28 +17733,42 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000008, 32, packed struct { - ADON: u1, // bit offset: 0 desc: A/D converter ON / OFF - CONT: u1, // bit offset: 1 desc: Continuous conversion - CAL: u1, // bit offset: 2 desc: A/D calibration - RSTCAL: u1, // bit offset: 3 desc: Reset calibration + /// A/D converter ON / OFF + ADON: u1 = 0, + /// Continuous conversion + CONT: u1 = 0, + /// A/D calibration + CAL: u1 = 0, + /// Reset calibration + RSTCAL: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DMA: u1, // bit offset: 8 desc: Direct memory access mode + /// Direct memory access mode + DMA: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - ALIGN: u1, // bit offset: 11 desc: Data alignment - JEXTSEL: u3, // bit offset: 12 desc: External event select for injected group - JEXTTRIG: u1, // bit offset: 15 desc: External trigger conversion mode for injected channels + /// Data alignment + ALIGN: u1 = 0, + /// External event select for injected group + JEXTSEL: u3 = 0, + /// External trigger conversion mode for injected channels + JEXTTRIG: u1 = 0, reserved7: u1 = 0, - EXTSEL: u3, // bit offset: 17 desc: External event select for regular group - EXTTRIG: u1, // bit offset: 20 desc: External trigger conversion mode for regular channels - JSWSTART: u1, // bit offset: 21 desc: Start conversion of injected channels - SWSTART: u1, // bit offset: 22 desc: Start conversion of regular channels - TSVREFE: u1, // bit offset: 23 desc: Temperature sensor and VREFINT enable + /// External event select for regular group + EXTSEL: u3 = 0, + /// External trigger conversion mode for regular channels + EXTTRIG: u1 = 0, + /// Start conversion of injected channels + JSWSTART: u1 = 0, + /// Start conversion of regular channels + SWSTART: u1 = 0, + /// Temperature sensor and VREFINT enable + TSVREFE: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -14324,16 +17778,25 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 sample time register 1 + + /// sample time register 1 pub const SMPR1 = mmio(Address + 0x0000000c, 32, packed struct { - SMP10: u3, // bit offset: 0 desc: Channel 10 sample time selection - SMP11: u3, // bit offset: 3 desc: Channel 11 sample time selection - SMP12: u3, // bit offset: 6 desc: Channel 12 sample time selection - SMP13: u3, // bit offset: 9 desc: Channel 13 sample time selection - SMP14: u3, // bit offset: 12 desc: Channel 14 sample time selection - SMP15: u3, // bit offset: 15 desc: Channel 15 sample time selection - SMP16: u3, // bit offset: 18 desc: Channel 16 sample time selection - SMP17: u3, // bit offset: 21 desc: Channel 17 sample time selection + /// Channel 10 sample time selection + SMP10: u3 = 0, + /// Channel 11 sample time selection + SMP11: u3 = 0, + /// Channel 12 sample time selection + SMP12: u3 = 0, + /// Channel 13 sample time selection + SMP13: u3 = 0, + /// Channel 14 sample time selection + SMP14: u3 = 0, + /// Channel 15 sample time selection + SMP15: u3 = 0, + /// Channel 16 sample time selection + SMP16: u3 = 0, + /// Channel 17 sample time selection + SMP17: u3 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -14343,24 +17806,37 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 sample time register 2 + + /// sample time register 2 pub const SMPR2 = mmio(Address + 0x00000010, 32, packed struct { - SMP0: u3, // bit offset: 0 desc: Channel 0 sample time selection - SMP1: u3, // bit offset: 3 desc: Channel 1 sample time selection - SMP2: u3, // bit offset: 6 desc: Channel 2 sample time selection - SMP3: u3, // bit offset: 9 desc: Channel 3 sample time selection - SMP4: u3, // bit offset: 12 desc: Channel 4 sample time selection - SMP5: u3, // bit offset: 15 desc: Channel 5 sample time selection - SMP6: u3, // bit offset: 18 desc: Channel 6 sample time selection - SMP7: u3, // bit offset: 21 desc: Channel 7 sample time selection - SMP8: u3, // bit offset: 24 desc: Channel 8 sample time selection - SMP9: u3, // bit offset: 27 desc: Channel 9 sample time selection + /// Channel 0 sample time selection + SMP0: u3 = 0, + /// Channel 1 sample time selection + SMP1: u3 = 0, + /// Channel 2 sample time selection + SMP2: u3 = 0, + /// Channel 3 sample time selection + SMP3: u3 = 0, + /// Channel 4 sample time selection + SMP4: u3 = 0, + /// Channel 5 sample time selection + SMP5: u3 = 0, + /// Channel 6 sample time selection + SMP6: u3 = 0, + /// Channel 7 sample time selection + SMP7: u3 = 0, + /// Channel 8 sample time selection + SMP8: u3 = 0, + /// Channel 9 sample time selection + SMP9: u3 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 injected channel data offset register x + + /// injected channel data offset register x pub const JOFR1 = mmio(Address + 0x00000014, 32, packed struct { - JOFFSET1: u12, // bit offset: 0 desc: Data offset for injected channel x + /// Data offset for injected channel x + JOFFSET1: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -14382,9 +17858,11 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 injected channel data offset register x + + /// injected channel data offset register x pub const JOFR2 = mmio(Address + 0x00000018, 32, packed struct { - JOFFSET2: u12, // bit offset: 0 desc: Data offset for injected channel x + /// Data offset for injected channel x + JOFFSET2: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -14406,9 +17884,11 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 injected channel data offset register x + + /// injected channel data offset register x pub const JOFR3 = mmio(Address + 0x0000001c, 32, packed struct { - JOFFSET3: u12, // bit offset: 0 desc: Data offset for injected channel x + /// Data offset for injected channel x + JOFFSET3: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -14430,9 +17910,11 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 injected channel data offset register x + + /// injected channel data offset register x pub const JOFR4 = mmio(Address + 0x00000020, 32, packed struct { - JOFFSET4: u12, // bit offset: 0 desc: Data offset for injected channel x + /// Data offset for injected channel x + JOFFSET4: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -14454,9 +17936,11 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 watchdog higher threshold register + + /// watchdog higher threshold register pub const HTR = mmio(Address + 0x00000024, 32, packed struct { - HT: u12, // bit offset: 0 desc: Analog watchdog higher threshold + /// Analog watchdog higher threshold + HT: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -14478,9 +17962,11 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 watchdog lower threshold register + + /// watchdog lower threshold register pub const LTR = mmio(Address + 0x00000028, 32, packed struct { - LT: u12, // bit offset: 0 desc: Analog watchdog lower threshold + /// Analog watchdog lower threshold + LT: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -14502,13 +17988,19 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 regular sequence register 1 + + /// regular sequence register 1 pub const SQR1 = mmio(Address + 0x0000002c, 32, packed struct { - SQ13: u5, // bit offset: 0 desc: 13th conversion in regular sequence - SQ14: u5, // bit offset: 5 desc: 14th conversion in regular sequence - SQ15: u5, // bit offset: 10 desc: 15th conversion in regular sequence - SQ16: u5, // bit offset: 15 desc: 16th conversion in regular sequence - L: u4, // bit offset: 20 desc: Regular channel sequence length + /// 13th conversion in regular sequence + SQ13: u5 = 0, + /// 14th conversion in regular sequence + SQ14: u5 = 0, + /// 15th conversion in regular sequence + SQ15: u5 = 0, + /// 16th conversion in regular sequence + SQ16: u5 = 0, + /// Regular channel sequence length + L: u4 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -14518,35 +18010,55 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 regular sequence register 2 + + /// regular sequence register 2 pub const SQR2 = mmio(Address + 0x00000030, 32, packed struct { - SQ7: u5, // bit offset: 0 desc: 7th conversion in regular sequence - SQ8: u5, // bit offset: 5 desc: 8th conversion in regular sequence - SQ9: u5, // bit offset: 10 desc: 9th conversion in regular sequence - SQ10: u5, // bit offset: 15 desc: 10th conversion in regular sequence - SQ11: u5, // bit offset: 20 desc: 11th conversion in regular sequence - SQ12: u5, // bit offset: 25 desc: 12th conversion in regular sequence + /// 7th conversion in regular sequence + SQ7: u5 = 0, + /// 8th conversion in regular sequence + SQ8: u5 = 0, + /// 9th conversion in regular sequence + SQ9: u5 = 0, + /// 10th conversion in regular sequence + SQ10: u5 = 0, + /// 11th conversion in regular sequence + SQ11: u5 = 0, + /// 12th conversion in regular sequence + SQ12: u5 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 regular sequence register 3 + + /// regular sequence register 3 pub const SQR3 = mmio(Address + 0x00000034, 32, packed struct { - SQ1: u5, // bit offset: 0 desc: 1st conversion in regular sequence - SQ2: u5, // bit offset: 5 desc: 2nd conversion in regular sequence - SQ3: u5, // bit offset: 10 desc: 3rd conversion in regular sequence - SQ4: u5, // bit offset: 15 desc: 4th conversion in regular sequence - SQ5: u5, // bit offset: 20 desc: 5th conversion in regular sequence - SQ6: u5, // bit offset: 25 desc: 6th conversion in regular sequence + /// 1st conversion in regular sequence + SQ1: u5 = 0, + /// 2nd conversion in regular sequence + SQ2: u5 = 0, + /// 3rd conversion in regular sequence + SQ3: u5 = 0, + /// 4th conversion in regular sequence + SQ4: u5 = 0, + /// 5th conversion in regular sequence + SQ5: u5 = 0, + /// 6th conversion in regular sequence + SQ6: u5 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 injected sequence register + + /// injected sequence register pub const JSQR = mmio(Address + 0x00000038, 32, packed struct { - JSQ1: u5, // bit offset: 0 desc: 1st conversion in injected sequence - JSQ2: u5, // bit offset: 5 desc: 2nd conversion in injected sequence - JSQ3: u5, // bit offset: 10 desc: 3rd conversion in injected sequence - JSQ4: u5, // bit offset: 15 desc: 4th conversion in injected sequence - JL: u2, // bit offset: 20 desc: Injected sequence length + /// 1st conversion in injected sequence + JSQ1: u5 = 0, + /// 2nd conversion in injected sequence + JSQ2: u5 = 0, + /// 3rd conversion in injected sequence + JSQ3: u5 = 0, + /// 4th conversion in injected sequence + JSQ4: u5 = 0, + /// Injected sequence length + JL: u2 = 0, padding10: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, @@ -14558,9 +18070,11 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 injected data register x + + /// injected data register x pub const JDR1 = mmio(Address + 0x0000003c, 32, packed struct { - JDATA: u16, // bit offset: 0 desc: Injected data + /// Injected data + JDATA: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14578,9 +18092,11 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 injected data register x + + /// injected data register x pub const JDR2 = mmio(Address + 0x00000040, 32, packed struct { - JDATA: u16, // bit offset: 0 desc: Injected data + /// Injected data + JDATA: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14598,9 +18114,11 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 injected data register x + + /// injected data register x pub const JDR3 = mmio(Address + 0x00000044, 32, packed struct { - JDATA: u16, // bit offset: 0 desc: Injected data + /// Injected data + JDATA: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14618,9 +18136,11 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 injected data register x + + /// injected data register x pub const JDR4 = mmio(Address + 0x00000048, 32, packed struct { - JDATA: u16, // bit offset: 0 desc: Injected data + /// Injected data + JDATA: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14638,9 +18158,11 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 regular data register + + /// regular data register pub const DR = mmio(Address + 0x0000004c, 32, packed struct { - DATA: u16, // bit offset: 0 desc: Regular data + /// Regular data + DATA: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14659,18 +18181,13 @@ pub const ADC3 = extern struct { padding1: u1 = 0, }); }; + +/// Controller area network pub const CAN = extern struct { pub const Address: u32 = 0x40006400; - // byte offset: 0 CAN_MCR + + /// CAN_MCR pub const CAN_MCR = mmio(Address + 0x00000000, 32, packed struct { - INRQ: u1, // bit offset: 0 desc: INRQ - SLEEP: u1, // bit offset: 1 desc: SLEEP - TXFP: u1, // bit offset: 2 desc: TXFP - RFLM: u1, // bit offset: 3 desc: RFLM - NART: u1, // bit offset: 4 desc: NART - AWUM: u1, // bit offset: 5 desc: AWUM - ABOM: u1, // bit offset: 6 desc: ABOM - TTCM: u1, // bit offset: 7 desc: TTCM reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -14678,8 +18195,6 @@ pub const CAN = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - RESET: u1, // bit offset: 15 desc: RESET - DBF: u1, // bit offset: 16 desc: DBF padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -14696,20 +18211,12 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 CAN_MSR + + /// CAN_MSR pub const CAN_MSR = mmio(Address + 0x00000004, 32, packed struct { - INAK: u1, // bit offset: 0 desc: INAK - SLAK: u1, // bit offset: 1 desc: SLAK - ERRI: u1, // bit offset: 2 desc: ERRI - WKUI: u1, // bit offset: 3 desc: WKUI - SLAKI: u1, // bit offset: 4 desc: SLAKI reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TXM: u1, // bit offset: 8 desc: TXM - RXM: u1, // bit offset: 9 desc: RXM - SAMP: u1, // bit offset: 10 desc: SAMP - RX: u1, // bit offset: 11 desc: RX padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -14731,47 +18238,35 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 CAN_TSR + + /// CAN_TSR pub const CAN_TSR = mmio(Address + 0x00000008, 32, packed struct { - RQCP0: u1, // bit offset: 0 desc: RQCP0 - TXOK0: u1, // bit offset: 1 desc: TXOK0 - ALST0: u1, // bit offset: 2 desc: ALST0 - TERR0: u1, // bit offset: 3 desc: TERR0 reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ABRQ0: u1, // bit offset: 7 desc: ABRQ0 - RQCP1: u1, // bit offset: 8 desc: RQCP1 - TXOK1: u1, // bit offset: 9 desc: TXOK1 - ALST1: u1, // bit offset: 10 desc: ALST1 - TERR1: u1, // bit offset: 11 desc: TERR1 reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - ABRQ1: u1, // bit offset: 15 desc: ABRQ1 - RQCP2: u1, // bit offset: 16 desc: RQCP2 - TXOK2: u1, // bit offset: 17 desc: TXOK2 - ALST2: u1, // bit offset: 18 desc: ALST2 - TERR2: u1, // bit offset: 19 desc: TERR2 reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, - ABRQ2: u1, // bit offset: 23 desc: ABRQ2 - CODE: u2, // bit offset: 24 desc: CODE - TME0: u1, // bit offset: 26 desc: Lowest priority flag for mailbox 0 - TME1: u1, // bit offset: 27 desc: Lowest priority flag for mailbox 1 - TME2: u1, // bit offset: 28 desc: Lowest priority flag for mailbox 2 - LOW0: u1, // bit offset: 29 desc: Lowest priority flag for mailbox 0 - LOW1: u1, // bit offset: 30 desc: Lowest priority flag for mailbox 1 - LOW2: u1, // bit offset: 31 desc: Lowest priority flag for mailbox 2 - }); - // byte offset: 12 CAN_RF0R + /// Lowest priority flag for mailbox 0 + TME0: u1 = 0, + /// Lowest priority flag for mailbox 1 + TME1: u1 = 0, + /// Lowest priority flag for mailbox 2 + TME2: u1 = 0, + /// Lowest priority flag for mailbox 0 + LOW0: u1 = 0, + /// Lowest priority flag for mailbox 1 + LOW1: u1 = 0, + /// Lowest priority flag for mailbox 2 + LOW2: u1 = 0, + }); + + /// CAN_RF0R pub const CAN_RF0R = mmio(Address + 0x0000000c, 32, packed struct { - FMP0: u2, // bit offset: 0 desc: FMP0 reserved1: u1 = 0, - FULL0: u1, // bit offset: 3 desc: FULL0 - FOVR0: u1, // bit offset: 4 desc: FOVR0 - RFOM0: u1, // bit offset: 5 desc: RFOM0 padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -14799,13 +18294,10 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 CAN_RF1R + + /// CAN_RF1R pub const CAN_RF1R = mmio(Address + 0x00000010, 32, packed struct { - FMP1: u2, // bit offset: 0 desc: FMP1 reserved1: u1 = 0, - FULL1: u1, // bit offset: 3 desc: FULL1 - FOVR1: u1, // bit offset: 4 desc: FOVR1 - RFOM1: u1, // bit offset: 5 desc: RFOM1 padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -14833,26 +18325,13 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 CAN_IER + + /// CAN_IER pub const CAN_IER = mmio(Address + 0x00000014, 32, packed struct { - TMEIE: u1, // bit offset: 0 desc: TMEIE - FMPIE0: u1, // bit offset: 1 desc: FMPIE0 - FFIE0: u1, // bit offset: 2 desc: FFIE0 - FOVIE0: u1, // bit offset: 3 desc: FOVIE0 - FMPIE1: u1, // bit offset: 4 desc: FMPIE1 - FFIE1: u1, // bit offset: 5 desc: FFIE1 - FOVIE1: u1, // bit offset: 6 desc: FOVIE1 reserved1: u1 = 0, - EWGIE: u1, // bit offset: 8 desc: EWGIE - EPVIE: u1, // bit offset: 9 desc: EPVIE - BOFIE: u1, // bit offset: 10 desc: BOFIE - LECIE: u1, // bit offset: 11 desc: LECIE reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - ERRIE: u1, // bit offset: 15 desc: ERRIE - WKUIE: u1, // bit offset: 16 desc: WKUIE - SLKIE: u1, // bit offset: 17 desc: SLKIE padding14: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, @@ -14868,13 +18347,10 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 CAN_ESR + + /// CAN_ESR pub const CAN_ESR = mmio(Address + 0x00000018, 32, packed struct { - EWGF: u1, // bit offset: 0 desc: EWGF - EPVF: u1, // bit offset: 1 desc: EPVF - BOFF: u1, // bit offset: 2 desc: BOFF reserved1: u1 = 0, - LEC: u3, // bit offset: 4 desc: LEC reserved10: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, @@ -14884,45 +18360,32 @@ pub const CAN = extern struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - TEC: u8, // bit offset: 16 desc: TEC - REC: u8, // bit offset: 24 desc: REC }); - // byte offset: 28 CAN_BTR + + /// CAN_BTR pub const CAN_BTR = mmio(Address + 0x0000001c, 32, packed struct { - BRP: u10, // bit offset: 0 desc: BRP reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TS1: u4, // bit offset: 16 desc: TS1 - TS2: u3, // bit offset: 20 desc: TS2 reserved7: u1 = 0, - SJW: u2, // bit offset: 24 desc: SJW reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, - LBKM: u1, // bit offset: 30 desc: LBKM - SILM: u1, // bit offset: 31 desc: SILM - }); - // byte offset: 384 CAN_TI0R - pub const CAN_TI0R = mmio(Address + 0x00000180, 32, packed struct { - TXRQ: u1, // bit offset: 0 desc: TXRQ - RTR: u1, // bit offset: 1 desc: RTR - IDE: u1, // bit offset: 2 desc: IDE - EXID: u18, // bit offset: 3 desc: EXID - STID: u11, // bit offset: 21 desc: STID - }); - // byte offset: 388 CAN_TDT0R + }); + + /// CAN_TI0R + pub const CAN_TI0R = mmio(Address + 0x00000180, 32, packed struct {}); + + /// CAN_TDT0R pub const CAN_TDT0R = mmio(Address + 0x00000184, 32, packed struct { - DLC: u4, // bit offset: 0 desc: DLC reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TGT: u1, // bit offset: 8 desc: TGT reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -14930,38 +18393,23 @@ pub const CAN = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - TIME: u16, // bit offset: 16 desc: TIME - }); - // byte offset: 392 CAN_TDL0R - pub const CAN_TDL0R = mmio(Address + 0x00000188, 32, packed struct { - DATA0: u8, // bit offset: 0 desc: DATA0 - DATA1: u8, // bit offset: 8 desc: DATA1 - DATA2: u8, // bit offset: 16 desc: DATA2 - DATA3: u8, // bit offset: 24 desc: DATA3 - }); - // byte offset: 396 CAN_TDH0R - pub const CAN_TDH0R = mmio(Address + 0x0000018c, 32, packed struct { - DATA4: u8, // bit offset: 0 desc: DATA4 - DATA5: u8, // bit offset: 8 desc: DATA5 - DATA6: u8, // bit offset: 16 desc: DATA6 - DATA7: u8, // bit offset: 24 desc: DATA7 - }); - // byte offset: 400 CAN_TI1R - pub const CAN_TI1R = mmio(Address + 0x00000190, 32, packed struct { - TXRQ: u1, // bit offset: 0 desc: TXRQ - RTR: u1, // bit offset: 1 desc: RTR - IDE: u1, // bit offset: 2 desc: IDE - EXID: u18, // bit offset: 3 desc: EXID - STID: u11, // bit offset: 21 desc: STID - }); - // byte offset: 404 CAN_TDT1R + }); + + /// CAN_TDL0R + pub const CAN_TDL0R = mmio(Address + 0x00000188, 32, packed struct {}); + + /// CAN_TDH0R + pub const CAN_TDH0R = mmio(Address + 0x0000018c, 32, packed struct {}); + + /// CAN_TI1R + pub const CAN_TI1R = mmio(Address + 0x00000190, 32, packed struct {}); + + /// CAN_TDT1R pub const CAN_TDT1R = mmio(Address + 0x00000194, 32, packed struct { - DLC: u4, // bit offset: 0 desc: DLC reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TGT: u1, // bit offset: 8 desc: TGT reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -14969,38 +18417,23 @@ pub const CAN = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - TIME: u16, // bit offset: 16 desc: TIME - }); - // byte offset: 408 CAN_TDL1R - pub const CAN_TDL1R = mmio(Address + 0x00000198, 32, packed struct { - DATA0: u8, // bit offset: 0 desc: DATA0 - DATA1: u8, // bit offset: 8 desc: DATA1 - DATA2: u8, // bit offset: 16 desc: DATA2 - DATA3: u8, // bit offset: 24 desc: DATA3 - }); - // byte offset: 412 CAN_TDH1R - pub const CAN_TDH1R = mmio(Address + 0x0000019c, 32, packed struct { - DATA4: u8, // bit offset: 0 desc: DATA4 - DATA5: u8, // bit offset: 8 desc: DATA5 - DATA6: u8, // bit offset: 16 desc: DATA6 - DATA7: u8, // bit offset: 24 desc: DATA7 - }); - // byte offset: 416 CAN_TI2R - pub const CAN_TI2R = mmio(Address + 0x000001a0, 32, packed struct { - TXRQ: u1, // bit offset: 0 desc: TXRQ - RTR: u1, // bit offset: 1 desc: RTR - IDE: u1, // bit offset: 2 desc: IDE - EXID: u18, // bit offset: 3 desc: EXID - STID: u11, // bit offset: 21 desc: STID - }); - // byte offset: 420 CAN_TDT2R + }); + + /// CAN_TDL1R + pub const CAN_TDL1R = mmio(Address + 0x00000198, 32, packed struct {}); + + /// CAN_TDH1R + pub const CAN_TDH1R = mmio(Address + 0x0000019c, 32, packed struct {}); + + /// CAN_TI2R + pub const CAN_TI2R = mmio(Address + 0x000001a0, 32, packed struct {}); + + /// CAN_TDT2R pub const CAN_TDT2R = mmio(Address + 0x000001a4, 32, packed struct { - DLC: u4, // bit offset: 0 desc: DLC reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TGT: u1, // bit offset: 8 desc: TGT reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -15008,89 +18441,54 @@ pub const CAN = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - TIME: u16, // bit offset: 16 desc: TIME - }); - // byte offset: 424 CAN_TDL2R - pub const CAN_TDL2R = mmio(Address + 0x000001a8, 32, packed struct { - DATA0: u8, // bit offset: 0 desc: DATA0 - DATA1: u8, // bit offset: 8 desc: DATA1 - DATA2: u8, // bit offset: 16 desc: DATA2 - DATA3: u8, // bit offset: 24 desc: DATA3 - }); - // byte offset: 428 CAN_TDH2R - pub const CAN_TDH2R = mmio(Address + 0x000001ac, 32, packed struct { - DATA4: u8, // bit offset: 0 desc: DATA4 - DATA5: u8, // bit offset: 8 desc: DATA5 - DATA6: u8, // bit offset: 16 desc: DATA6 - DATA7: u8, // bit offset: 24 desc: DATA7 - }); - // byte offset: 432 CAN_RI0R + }); + + /// CAN_TDL2R + pub const CAN_TDL2R = mmio(Address + 0x000001a8, 32, packed struct {}); + + /// CAN_TDH2R + pub const CAN_TDH2R = mmio(Address + 0x000001ac, 32, packed struct {}); + + /// CAN_RI0R pub const CAN_RI0R = mmio(Address + 0x000001b0, 32, packed struct { reserved1: u1 = 0, - RTR: u1, // bit offset: 1 desc: RTR - IDE: u1, // bit offset: 2 desc: IDE - EXID: u18, // bit offset: 3 desc: EXID - STID: u11, // bit offset: 21 desc: STID }); - // byte offset: 436 CAN_RDT0R + + /// CAN_RDT0R pub const CAN_RDT0R = mmio(Address + 0x000001b4, 32, packed struct { - DLC: u4, // bit offset: 0 desc: DLC reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - FMI: u8, // bit offset: 8 desc: FMI - TIME: u16, // bit offset: 16 desc: TIME - }); - // byte offset: 440 CAN_RDL0R - pub const CAN_RDL0R = mmio(Address + 0x000001b8, 32, packed struct { - DATA0: u8, // bit offset: 0 desc: DATA0 - DATA1: u8, // bit offset: 8 desc: DATA1 - DATA2: u8, // bit offset: 16 desc: DATA2 - DATA3: u8, // bit offset: 24 desc: DATA3 - }); - // byte offset: 444 CAN_RDH0R - pub const CAN_RDH0R = mmio(Address + 0x000001bc, 32, packed struct { - DATA4: u8, // bit offset: 0 desc: DATA4 - DATA5: u8, // bit offset: 8 desc: DATA5 - DATA6: u8, // bit offset: 16 desc: DATA6 - DATA7: u8, // bit offset: 24 desc: DATA7 - }); - // byte offset: 448 CAN_RI1R + }); + + /// CAN_RDL0R + pub const CAN_RDL0R = mmio(Address + 0x000001b8, 32, packed struct {}); + + /// CAN_RDH0R + pub const CAN_RDH0R = mmio(Address + 0x000001bc, 32, packed struct {}); + + /// CAN_RI1R pub const CAN_RI1R = mmio(Address + 0x000001c0, 32, packed struct { reserved1: u1 = 0, - RTR: u1, // bit offset: 1 desc: RTR - IDE: u1, // bit offset: 2 desc: IDE - EXID: u18, // bit offset: 3 desc: EXID - STID: u11, // bit offset: 21 desc: STID }); - // byte offset: 452 CAN_RDT1R + + /// CAN_RDT1R pub const CAN_RDT1R = mmio(Address + 0x000001c4, 32, packed struct { - DLC: u4, // bit offset: 0 desc: DLC reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - FMI: u8, // bit offset: 8 desc: FMI - TIME: u16, // bit offset: 16 desc: TIME - }); - // byte offset: 456 CAN_RDL1R - pub const CAN_RDL1R = mmio(Address + 0x000001c8, 32, packed struct { - DATA0: u8, // bit offset: 0 desc: DATA0 - DATA1: u8, // bit offset: 8 desc: DATA1 - DATA2: u8, // bit offset: 16 desc: DATA2 - DATA3: u8, // bit offset: 24 desc: DATA3 - }); - // byte offset: 460 CAN_RDH1R - pub const CAN_RDH1R = mmio(Address + 0x000001cc, 32, packed struct { - DATA4: u8, // bit offset: 0 desc: DATA4 - DATA5: u8, // bit offset: 8 desc: DATA5 - DATA6: u8, // bit offset: 16 desc: DATA6 - DATA7: u8, // bit offset: 24 desc: DATA7 - }); - // byte offset: 512 CAN_FMR + }); + + /// CAN_RDL1R + pub const CAN_RDL1R = mmio(Address + 0x000001c8, 32, packed struct {}); + + /// CAN_RDH1R + pub const CAN_RDH1R = mmio(Address + 0x000001cc, 32, packed struct {}); + + /// CAN_FMR pub const CAN_FMR = mmio(Address + 0x00000200, 32, packed struct { - FINIT: u1, // bit offset: 0 desc: FINIT padding31: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, @@ -15123,22 +18521,37 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 516 CAN_FM1R + + /// CAN_FM1R pub const CAN_FM1R = mmio(Address + 0x00000204, 32, packed struct { - FBM0: u1, // bit offset: 0 desc: Filter mode - FBM1: u1, // bit offset: 1 desc: Filter mode - FBM2: u1, // bit offset: 2 desc: Filter mode - FBM3: u1, // bit offset: 3 desc: Filter mode - FBM4: u1, // bit offset: 4 desc: Filter mode - FBM5: u1, // bit offset: 5 desc: Filter mode - FBM6: u1, // bit offset: 6 desc: Filter mode - FBM7: u1, // bit offset: 7 desc: Filter mode - FBM8: u1, // bit offset: 8 desc: Filter mode - FBM9: u1, // bit offset: 9 desc: Filter mode - FBM10: u1, // bit offset: 10 desc: Filter mode - FBM11: u1, // bit offset: 11 desc: Filter mode - FBM12: u1, // bit offset: 12 desc: Filter mode - FBM13: u1, // bit offset: 13 desc: Filter mode + /// Filter mode + FBM0: u1 = 0, + /// Filter mode + FBM1: u1 = 0, + /// Filter mode + FBM2: u1 = 0, + /// Filter mode + FBM3: u1 = 0, + /// Filter mode + FBM4: u1 = 0, + /// Filter mode + FBM5: u1 = 0, + /// Filter mode + FBM6: u1 = 0, + /// Filter mode + FBM7: u1 = 0, + /// Filter mode + FBM8: u1 = 0, + /// Filter mode + FBM9: u1 = 0, + /// Filter mode + FBM10: u1 = 0, + /// Filter mode + FBM11: u1 = 0, + /// Filter mode + FBM12: u1 = 0, + /// Filter mode + FBM13: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -15158,22 +18571,37 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 524 CAN_FS1R + + /// CAN_FS1R pub const CAN_FS1R = mmio(Address + 0x0000020c, 32, packed struct { - FSC0: u1, // bit offset: 0 desc: Filter scale configuration - FSC1: u1, // bit offset: 1 desc: Filter scale configuration - FSC2: u1, // bit offset: 2 desc: Filter scale configuration - FSC3: u1, // bit offset: 3 desc: Filter scale configuration - FSC4: u1, // bit offset: 4 desc: Filter scale configuration - FSC5: u1, // bit offset: 5 desc: Filter scale configuration - FSC6: u1, // bit offset: 6 desc: Filter scale configuration - FSC7: u1, // bit offset: 7 desc: Filter scale configuration - FSC8: u1, // bit offset: 8 desc: Filter scale configuration - FSC9: u1, // bit offset: 9 desc: Filter scale configuration - FSC10: u1, // bit offset: 10 desc: Filter scale configuration - FSC11: u1, // bit offset: 11 desc: Filter scale configuration - FSC12: u1, // bit offset: 12 desc: Filter scale configuration - FSC13: u1, // bit offset: 13 desc: Filter scale configuration + /// Filter scale configuration + FSC0: u1 = 0, + /// Filter scale configuration + FSC1: u1 = 0, + /// Filter scale configuration + FSC2: u1 = 0, + /// Filter scale configuration + FSC3: u1 = 0, + /// Filter scale configuration + FSC4: u1 = 0, + /// Filter scale configuration + FSC5: u1 = 0, + /// Filter scale configuration + FSC6: u1 = 0, + /// Filter scale configuration + FSC7: u1 = 0, + /// Filter scale configuration + FSC8: u1 = 0, + /// Filter scale configuration + FSC9: u1 = 0, + /// Filter scale configuration + FSC10: u1 = 0, + /// Filter scale configuration + FSC11: u1 = 0, + /// Filter scale configuration + FSC12: u1 = 0, + /// Filter scale configuration + FSC13: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -15193,22 +18621,37 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 532 CAN_FFA1R + + /// CAN_FFA1R pub const CAN_FFA1R = mmio(Address + 0x00000214, 32, packed struct { - FFA0: u1, // bit offset: 0 desc: Filter FIFO assignment for filter 0 - FFA1: u1, // bit offset: 1 desc: Filter FIFO assignment for filter 1 - FFA2: u1, // bit offset: 2 desc: Filter FIFO assignment for filter 2 - FFA3: u1, // bit offset: 3 desc: Filter FIFO assignment for filter 3 - FFA4: u1, // bit offset: 4 desc: Filter FIFO assignment for filter 4 - FFA5: u1, // bit offset: 5 desc: Filter FIFO assignment for filter 5 - FFA6: u1, // bit offset: 6 desc: Filter FIFO assignment for filter 6 - FFA7: u1, // bit offset: 7 desc: Filter FIFO assignment for filter 7 - FFA8: u1, // bit offset: 8 desc: Filter FIFO assignment for filter 8 - FFA9: u1, // bit offset: 9 desc: Filter FIFO assignment for filter 9 - FFA10: u1, // bit offset: 10 desc: Filter FIFO assignment for filter 10 - FFA11: u1, // bit offset: 11 desc: Filter FIFO assignment for filter 11 - FFA12: u1, // bit offset: 12 desc: Filter FIFO assignment for filter 12 - FFA13: u1, // bit offset: 13 desc: Filter FIFO assignment for filter 13 + /// Filter FIFO assignment for filter 0 + FFA0: u1 = 0, + /// Filter FIFO assignment for filter 1 + FFA1: u1 = 0, + /// Filter FIFO assignment for filter 2 + FFA2: u1 = 0, + /// Filter FIFO assignment for filter 3 + FFA3: u1 = 0, + /// Filter FIFO assignment for filter 4 + FFA4: u1 = 0, + /// Filter FIFO assignment for filter 5 + FFA5: u1 = 0, + /// Filter FIFO assignment for filter 6 + FFA6: u1 = 0, + /// Filter FIFO assignment for filter 7 + FFA7: u1 = 0, + /// Filter FIFO assignment for filter 8 + FFA8: u1 = 0, + /// Filter FIFO assignment for filter 9 + FFA9: u1 = 0, + /// Filter FIFO assignment for filter 10 + FFA10: u1 = 0, + /// Filter FIFO assignment for filter 11 + FFA11: u1 = 0, + /// Filter FIFO assignment for filter 12 + FFA12: u1 = 0, + /// Filter FIFO assignment for filter 13 + FFA13: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -15228,22 +18671,37 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 540 CAN_FA1R + + /// CAN_FA1R pub const CAN_FA1R = mmio(Address + 0x0000021c, 32, packed struct { - FACT0: u1, // bit offset: 0 desc: Filter active - FACT1: u1, // bit offset: 1 desc: Filter active - FACT2: u1, // bit offset: 2 desc: Filter active - FACT3: u1, // bit offset: 3 desc: Filter active - FACT4: u1, // bit offset: 4 desc: Filter active - FACT5: u1, // bit offset: 5 desc: Filter active - FACT6: u1, // bit offset: 6 desc: Filter active - FACT7: u1, // bit offset: 7 desc: Filter active - FACT8: u1, // bit offset: 8 desc: Filter active - FACT9: u1, // bit offset: 9 desc: Filter active - FACT10: u1, // bit offset: 10 desc: Filter active - FACT11: u1, // bit offset: 11 desc: Filter active - FACT12: u1, // bit offset: 12 desc: Filter active - FACT13: u1, // bit offset: 13 desc: Filter active + /// Filter active + FACT0: u1 = 0, + /// Filter active + FACT1: u1 = 0, + /// Filter active + FACT2: u1 = 0, + /// Filter active + FACT3: u1 = 0, + /// Filter active + FACT4: u1 = 0, + /// Filter active + FACT5: u1 = 0, + /// Filter active + FACT6: u1 = 0, + /// Filter active + FACT7: u1 = 0, + /// Filter active + FACT8: u1 = 0, + /// Filter active + FACT9: u1 = 0, + /// Filter active + FACT10: u1 = 0, + /// Filter active + FACT11: u1 = 0, + /// Filter active + FACT12: u1 = 0, + /// Filter active + FACT13: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -15263,1016 +18721,1960 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 576 Filter bank 0 register 1 + + /// Filter bank 0 register 1 pub const F0R1 = mmio(Address + 0x00000240, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 580 Filter bank 0 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 0 register 2 pub const F0R2 = mmio(Address + 0x00000244, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 584 Filter bank 1 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 1 register 1 pub const F1R1 = mmio(Address + 0x00000248, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 588 Filter bank 1 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 1 register 2 pub const F1R2 = mmio(Address + 0x0000024c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 592 Filter bank 2 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 2 register 1 pub const F2R1 = mmio(Address + 0x00000250, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 596 Filter bank 2 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 2 register 2 pub const F2R2 = mmio(Address + 0x00000254, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 600 Filter bank 3 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 3 register 1 pub const F3R1 = mmio(Address + 0x00000258, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 604 Filter bank 3 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 3 register 2 pub const F3R2 = mmio(Address + 0x0000025c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 608 Filter bank 4 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 4 register 1 pub const F4R1 = mmio(Address + 0x00000260, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 612 Filter bank 4 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 4 register 2 pub const F4R2 = mmio(Address + 0x00000264, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 616 Filter bank 5 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 5 register 1 pub const F5R1 = mmio(Address + 0x00000268, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 620 Filter bank 5 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 5 register 2 pub const F5R2 = mmio(Address + 0x0000026c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 624 Filter bank 6 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 6 register 1 pub const F6R1 = mmio(Address + 0x00000270, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 628 Filter bank 6 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 6 register 2 pub const F6R2 = mmio(Address + 0x00000274, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 632 Filter bank 7 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 7 register 1 pub const F7R1 = mmio(Address + 0x00000278, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 636 Filter bank 7 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 7 register 2 pub const F7R2 = mmio(Address + 0x0000027c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 640 Filter bank 8 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 8 register 1 pub const F8R1 = mmio(Address + 0x00000280, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 644 Filter bank 8 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 8 register 2 pub const F8R2 = mmio(Address + 0x00000284, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 648 Filter bank 9 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 9 register 1 pub const F9R1 = mmio(Address + 0x00000288, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 652 Filter bank 9 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 9 register 2 pub const F9R2 = mmio(Address + 0x0000028c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 656 Filter bank 10 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 10 register 1 pub const F10R1 = mmio(Address + 0x00000290, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 660 Filter bank 10 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 10 register 2 pub const F10R2 = mmio(Address + 0x00000294, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 664 Filter bank 11 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 11 register 1 pub const F11R1 = mmio(Address + 0x00000298, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 668 Filter bank 11 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 11 register 2 pub const F11R2 = mmio(Address + 0x0000029c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 672 Filter bank 4 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 4 register 1 pub const F12R1 = mmio(Address + 0x000002a0, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 676 Filter bank 12 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 12 register 2 pub const F12R2 = mmio(Address + 0x000002a4, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 680 Filter bank 13 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 13 register 1 pub const F13R1 = mmio(Address + 0x000002a8, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 684 Filter bank 13 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 13 register 2 pub const F13R2 = mmio(Address + 0x000002ac, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, }); }; + +/// Digital to analog converter pub const DAC = extern struct { pub const Address: u32 = 0x40007400; - // byte offset: 0 Control register (DAC_CR) + + /// Control register (DAC_CR) pub const CR = mmio(Address + 0x00000000, 32, packed struct { - EN1: u1, // bit offset: 0 desc: DAC channel1 enable - BOFF1: u1, // bit offset: 1 desc: DAC channel1 output buffer disable - TEN1: u1, // bit offset: 2 desc: DAC channel1 trigger enable - TSEL1: u3, // bit offset: 3 desc: DAC channel1 trigger selection - WAVE1: u2, // bit offset: 6 desc: DAC channel1 noise/triangle wave generation enable - MAMP1: u4, // bit offset: 8 desc: DAC channel1 mask/amplitude selector - DMAEN1: u1, // bit offset: 12 desc: DAC channel1 DMA enable + /// DAC channel1 enable + EN1: u1 = 0, + /// DAC channel1 output buffer disable + BOFF1: u1 = 0, + /// DAC channel1 trigger enable + TEN1: u1 = 0, + /// DAC channel1 trigger selection + TSEL1: u3 = 0, + /// DAC channel1 noise/triangle wave generation enable + WAVE1: u2 = 0, + /// DAC channel1 mask/amplitude selector + MAMP1: u4 = 0, + /// DAC channel1 DMA enable + DMAEN1: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - EN2: u1, // bit offset: 16 desc: DAC channel2 enable - BOFF2: u1, // bit offset: 17 desc: DAC channel2 output buffer disable - TEN2: u1, // bit offset: 18 desc: DAC channel2 trigger enable - TSEL2: u3, // bit offset: 19 desc: DAC channel2 trigger selection - WAVE2: u2, // bit offset: 22 desc: DAC channel2 noise/triangle wave generation enable - MAMP2: u4, // bit offset: 24 desc: DAC channel2 mask/amplitude selector - DMAEN2: u1, // bit offset: 28 desc: DAC channel2 DMA enable + /// DAC channel2 enable + EN2: u1 = 0, + /// DAC channel2 output buffer disable + BOFF2: u1 = 0, + /// DAC channel2 trigger enable + TEN2: u1 = 0, + /// DAC channel2 trigger selection + TSEL2: u3 = 0, + /// DAC channel2 noise/triangle wave generation enable + WAVE2: u2 = 0, + /// DAC channel2 mask/amplitude selector + MAMP2: u4 = 0, + /// DAC channel2 DMA enable + DMAEN2: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 DAC software trigger register (DAC_SWTRIGR) + + /// DAC software trigger register (DAC_SWTRIGR) pub const SWTRIGR = mmio(Address + 0x00000004, 32, packed struct { - SWTRIG1: u1, // bit offset: 0 desc: DAC channel1 software trigger - SWTRIG2: u1, // bit offset: 1 desc: DAC channel2 software trigger + /// DAC channel1 software trigger + SWTRIG1: u1 = 0, + /// DAC channel2 software trigger + SWTRIG2: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -16304,9 +20706,11 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1) + + /// DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1) pub const DHR12R1 = mmio(Address + 0x00000008, 32, packed struct { - DACC1DHR: u12, // bit offset: 0 desc: DAC channel1 12-bit right-aligned data + /// DAC channel1 12-bit right-aligned data + DACC1DHR: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -16328,13 +20732,15 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) + + /// DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) pub const DHR12L1 = mmio(Address + 0x0000000c, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DACC1DHR: u12, // bit offset: 4 desc: DAC channel1 12-bit left-aligned data + /// DAC channel1 12-bit left-aligned data + DACC1DHR: u12 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16352,9 +20758,11 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) + + /// DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) pub const DHR8R1 = mmio(Address + 0x00000010, 32, packed struct { - DACC1DHR: u8, // bit offset: 0 desc: DAC channel1 8-bit right-aligned data + /// DAC channel1 8-bit right-aligned data + DACC1DHR: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -16380,9 +20788,11 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) + + /// DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) pub const DHR12R2 = mmio(Address + 0x00000014, 32, packed struct { - DACC2DHR: u12, // bit offset: 0 desc: DAC channel2 12-bit right-aligned data + /// DAC channel2 12-bit right-aligned data + DACC2DHR: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -16404,13 +20814,15 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) + + /// DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) pub const DHR12L2 = mmio(Address + 0x00000018, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DACC2DHR: u12, // bit offset: 4 desc: DAC channel2 12-bit left-aligned data + /// DAC channel2 12-bit left-aligned data + DACC2DHR: u12 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16428,9 +20840,11 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) + + /// DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) pub const DHR8R2 = mmio(Address + 0x0000001c, 32, packed struct { - DACC2DHR: u8, // bit offset: 0 desc: DAC channel2 8-bit right-aligned data + /// DAC channel2 8-bit right-aligned data + DACC2DHR: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -16456,36 +20870,48 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved + + /// Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits + /// 31:28 Reserved, Bits 15:12 Reserved pub const DHR12RD = mmio(Address + 0x00000020, 32, packed struct { - DACC1DHR: u12, // bit offset: 0 desc: DAC channel1 12-bit right-aligned data + /// DAC channel1 12-bit right-aligned data + DACC1DHR: u12 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DACC2DHR: u12, // bit offset: 16 desc: DAC channel2 12-bit right-aligned data + /// DAC channel2 12-bit right-aligned data + DACC2DHR: u12 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved + + /// DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 + /// Reserved, Bits 3:0 Reserved pub const DHR12LD = mmio(Address + 0x00000024, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DACC1DHR: u12, // bit offset: 4 desc: DAC channel1 12-bit left-aligned data + /// DAC channel1 12-bit left-aligned data + DACC1DHR: u12 = 0, reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - DACC2DHR: u12, // bit offset: 20 desc: DAC channel2 12-bit right-aligned data + /// DAC channel2 12-bit right-aligned data + DACC2DHR: u12 = 0, }); - // byte offset: 40 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved + + /// DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 + /// Reserved pub const DHR8RD = mmio(Address + 0x00000028, 32, packed struct { - DACC1DHR: u8, // bit offset: 0 desc: DAC channel1 8-bit right-aligned data - DACC2DHR: u8, // bit offset: 8 desc: DAC channel2 8-bit right-aligned data + /// DAC channel1 8-bit right-aligned data + DACC1DHR: u8 = 0, + /// DAC channel2 8-bit right-aligned data + DACC2DHR: u8 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16503,9 +20929,11 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 DAC channel1 data output register (DAC_DOR1) + + /// DAC channel1 data output register (DAC_DOR1) pub const DOR1 = mmio(Address + 0x0000002c, 32, packed struct { - DACC1DOR: u12, // bit offset: 0 desc: DAC channel1 data output + /// DAC channel1 data output + DACC1DOR: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -16527,9 +20955,11 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 DAC channel2 data output register (DAC_DOR2) + + /// DAC channel2 data output register (DAC_DOR2) pub const DOR2 = mmio(Address + 0x00000030, 32, packed struct { - DACC2DOR: u12, // bit offset: 0 desc: DAC channel2 data output + /// DAC channel2 data output + DACC2DOR: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -16552,40 +20982,23 @@ pub const DAC = extern struct { padding1: u1 = 0, }); }; + +/// Debug support pub const DBG = extern struct { pub const Address: u32 = 0xe0042000; - // byte offset: 0 DBGMCU_IDCODE + + /// DBGMCU_IDCODE pub const IDCODE = mmio(Address + 0x00000000, 32, packed struct { - DEV_ID: u12, // bit offset: 0 desc: DEV_ID reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - REV_ID: u16, // bit offset: 16 desc: REV_ID }); - // byte offset: 4 DBGMCU_CR + + /// DBGMCU_CR pub const CR = mmio(Address + 0x00000004, 32, packed struct { - DBG_SLEEP: u1, // bit offset: 0 desc: DBG_SLEEP - DBG_STOP: u1, // bit offset: 1 desc: DBG_STOP - DBG_STANDBY: u1, // bit offset: 2 desc: DBG_STANDBY reserved2: u1 = 0, reserved1: u1 = 0, - TRACE_IOEN: u1, // bit offset: 5 desc: TRACE_IOEN - TRACE_MODE: u2, // bit offset: 6 desc: TRACE_MODE - DBG_IWDG_STOP: u1, // bit offset: 8 desc: DBG_IWDG_STOP - DBG_WWDG_STOP: u1, // bit offset: 9 desc: DBG_WWDG_STOP - DBG_TIM1_STOP: u1, // bit offset: 10 desc: DBG_TIM1_STOP - DBG_TIM2_STOP: u1, // bit offset: 11 desc: DBG_TIM2_STOP - DBG_TIM3_STOP: u1, // bit offset: 12 desc: DBG_TIM3_STOP - DBG_TIM4_STOP: u1, // bit offset: 13 desc: DBG_TIM4_STOP - DBG_CAN1_STOP: u1, // bit offset: 14 desc: DBG_CAN1_STOP - DBG_I2C1_SMBUS_TIMEOUT: u1, // bit offset: 15 desc: DBG_I2C1_SMBUS_TIMEOUT - DBG_I2C2_SMBUS_TIMEOUT: u1, // bit offset: 16 desc: DBG_I2C2_SMBUS_TIMEOUT - DBG_TIM8_STOP: u1, // bit offset: 17 desc: DBG_TIM8_STOP - DBG_TIM5_STOP: u1, // bit offset: 18 desc: DBG_TIM5_STOP - DBG_TIM6_STOP: u1, // bit offset: 19 desc: DBG_TIM6_STOP - DBG_TIM7_STOP: u1, // bit offset: 20 desc: DBG_TIM7_STOP - DBG_CAN2_STOP: u1, // bit offset: 21 desc: DBG_CAN2_STOP padding10: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, @@ -16598,19 +21011,31 @@ pub const DBG = extern struct { padding1: u1 = 0, }); }; + +/// Universal asynchronous receiver transmitter pub const UART4 = extern struct { pub const Address: u32 = 0x40004c00; - // byte offset: 0 UART4_SR + + /// UART4_SR pub const SR = mmio(Address + 0x00000000, 32, packed struct { - PE: u1, // bit offset: 0 desc: Parity error - FE: u1, // bit offset: 1 desc: Framing error - NE: u1, // bit offset: 2 desc: Noise error flag - ORE: u1, // bit offset: 3 desc: Overrun error - IDLE: u1, // bit offset: 4 desc: IDLE line detected - RXNE: u1, // bit offset: 5 desc: Read data register not empty - TC: u1, // bit offset: 6 desc: Transmission complete - TXE: u1, // bit offset: 7 desc: Transmit data register empty - LBD: u1, // bit offset: 8 desc: LIN break detection flag + /// Parity error + PE: u1 = 0, + /// Framing error + FE: u1 = 0, + /// Noise error flag + NE: u1 = 0, + /// Overrun error + ORE: u1 = 0, + /// IDLE line detected + IDLE: u1 = 0, + /// Read data register not empty + RXNE: u1 = 0, + /// Transmission complete + TC: u1 = 0, + /// Transmit data register empty + TXE: u1 = 0, + /// LIN break detection flag + LBD: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -16635,9 +21060,9 @@ pub const UART4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 UART4_DR + + /// UART4_DR pub const DR = mmio(Address + 0x00000004, 32, packed struct { - DR: u9, // bit offset: 0 desc: DR padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -16662,10 +21087,9 @@ pub const UART4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 UART4_BRR + + /// UART4_BRR pub const BRR = mmio(Address + 0x00000008, 32, packed struct { - DIV_Fraction: u4, // bit offset: 0 desc: DIV_Fraction - DIV_Mantissa: u12, // bit offset: 4 desc: DIV_Mantissa padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16683,22 +21107,37 @@ pub const UART4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 UART4_CR1 + + /// UART4_CR1 pub const CR1 = mmio(Address + 0x0000000c, 32, packed struct { - SBK: u1, // bit offset: 0 desc: Send break - RWU: u1, // bit offset: 1 desc: Receiver wakeup - RE: u1, // bit offset: 2 desc: Receiver enable - TE: u1, // bit offset: 3 desc: Transmitter enable - IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable - RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable - TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable - TXEIE: u1, // bit offset: 7 desc: TXE interrupt enable - PEIE: u1, // bit offset: 8 desc: PE interrupt enable - PS: u1, // bit offset: 9 desc: Parity selection - PCE: u1, // bit offset: 10 desc: Parity control enable - WAKE: u1, // bit offset: 11 desc: Wakeup method - M: u1, // bit offset: 12 desc: Word length - UE: u1, // bit offset: 13 desc: USART enable + /// Send break + SBK: u1 = 0, + /// Receiver wakeup + RWU: u1 = 0, + /// Receiver enable + RE: u1 = 0, + /// Transmitter enable + TE: u1 = 0, + /// IDLE interrupt enable + IDLEIE: u1 = 0, + /// RXNE interrupt enable + RXNEIE: u1 = 0, + /// Transmission complete interrupt enable + TCIE: u1 = 0, + /// TXE interrupt enable + TXEIE: u1 = 0, + /// PE interrupt enable + PEIE: u1 = 0, + /// Parity selection + PS: u1 = 0, + /// Parity control enable + PCE: u1 = 0, + /// Wakeup method + WAKE: u1 = 0, + /// Word length + M: u1 = 0, + /// USART enable + UE: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -16718,19 +21157,25 @@ pub const UART4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 UART4_CR2 + + /// UART4_CR2 pub const CR2 = mmio(Address + 0x00000010, 32, packed struct { - ADD: u4, // bit offset: 0 desc: Address of the USART node + /// Address of the USART node + ADD: u4 = 0, reserved1: u1 = 0, - LBDL: u1, // bit offset: 5 desc: lin break detection length - LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable + /// lin break detection length + LBDL: u1 = 0, + /// LIN break detection interrupt enable + LBDIE: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - STOP: u2, // bit offset: 12 desc: STOP bits - LINEN: u1, // bit offset: 14 desc: LIN mode enable + /// STOP bits + STOP: u2 = 0, + /// LIN mode enable + LINEN: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -16749,16 +21194,23 @@ pub const UART4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 UART4_CR3 + + /// UART4_CR3 pub const CR3 = mmio(Address + 0x00000014, 32, packed struct { - EIE: u1, // bit offset: 0 desc: Error interrupt enable - IREN: u1, // bit offset: 1 desc: IrDA mode enable - IRLP: u1, // bit offset: 2 desc: IrDA low-power - HDSEL: u1, // bit offset: 3 desc: Half-duplex selection + /// Error interrupt enable + EIE: u1 = 0, + /// IrDA mode enable + IREN: u1 = 0, + /// IrDA low-power + IRLP: u1 = 0, + /// Half-duplex selection + HDSEL: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DMAR: u1, // bit offset: 6 desc: DMA enable receiver - DMAT: u1, // bit offset: 7 desc: DMA enable transmitter + /// DMA enable receiver + DMAR: u1 = 0, + /// DMA enable transmitter + DMAT: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -16785,19 +21237,13 @@ pub const UART4 = extern struct { padding1: u1 = 0, }); }; + +/// Universal asynchronous receiver transmitter pub const UART5 = extern struct { pub const Address: u32 = 0x40005000; - // byte offset: 0 UART4_SR + + /// UART4_SR pub const SR = mmio(Address + 0x00000000, 32, packed struct { - PE: u1, // bit offset: 0 desc: PE - FE: u1, // bit offset: 1 desc: FE - NE: u1, // bit offset: 2 desc: NE - ORE: u1, // bit offset: 3 desc: ORE - IDLE: u1, // bit offset: 4 desc: IDLE - RXNE: u1, // bit offset: 5 desc: RXNE - TC: u1, // bit offset: 6 desc: TC - TXE: u1, // bit offset: 7 desc: TXE - LBD: u1, // bit offset: 8 desc: LBD padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -16822,9 +21268,9 @@ pub const UART5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 UART4_DR + + /// UART4_DR pub const DR = mmio(Address + 0x00000004, 32, packed struct { - DR: u9, // bit offset: 0 desc: DR padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -16849,10 +21295,9 @@ pub const UART5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 UART4_BRR + + /// UART4_BRR pub const BRR = mmio(Address + 0x00000008, 32, packed struct { - DIV_Fraction: u4, // bit offset: 0 desc: DIV_Fraction - DIV_Mantissa: u12, // bit offset: 4 desc: DIV_Mantissa padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16870,22 +21315,9 @@ pub const UART5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 UART4_CR1 + + /// UART4_CR1 pub const CR1 = mmio(Address + 0x0000000c, 32, packed struct { - SBK: u1, // bit offset: 0 desc: SBK - RWU: u1, // bit offset: 1 desc: RWU - RE: u1, // bit offset: 2 desc: RE - TE: u1, // bit offset: 3 desc: TE - IDLEIE: u1, // bit offset: 4 desc: IDLEIE - RXNEIE: u1, // bit offset: 5 desc: RXNEIE - TCIE: u1, // bit offset: 6 desc: TCIE - TXEIE: u1, // bit offset: 7 desc: TXEIE - PEIE: u1, // bit offset: 8 desc: PEIE - PS: u1, // bit offset: 9 desc: PS - PCE: u1, // bit offset: 10 desc: PCE - WAKE: u1, // bit offset: 11 desc: WAKE - M: u1, // bit offset: 12 desc: M - UE: u1, // bit offset: 13 desc: UE padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -16905,19 +21337,15 @@ pub const UART5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 UART4_CR2 + + /// UART4_CR2 pub const CR2 = mmio(Address + 0x00000010, 32, packed struct { - ADD: u4, // bit offset: 0 desc: ADD reserved1: u1 = 0, - LBDL: u1, // bit offset: 5 desc: LBDL - LBDIE: u1, // bit offset: 6 desc: LBDIE reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - STOP: u2, // bit offset: 12 desc: STOP - LINEN: u1, // bit offset: 14 desc: LINEN padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -16936,16 +21364,22 @@ pub const UART5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 UART4_CR3 + + /// UART4_CR3 pub const CR3 = mmio(Address + 0x00000014, 32, packed struct { - EIE: u1, // bit offset: 0 desc: Error interrupt enable - IREN: u1, // bit offset: 1 desc: IrDA mode enable - IRLP: u1, // bit offset: 2 desc: IrDA low-power - HDSEL: u1, // bit offset: 3 desc: Half-duplex selection + /// Error interrupt enable + EIE: u1 = 0, + /// IrDA mode enable + IREN: u1 = 0, + /// IrDA low-power + IRLP: u1 = 0, + /// Half-duplex selection + HDSEL: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DMAT: u1, // bit offset: 7 desc: DMA enable transmitter + /// DMA enable transmitter + DMAT: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -16972,15 +21406,18 @@ pub const UART5 = extern struct { padding1: u1 = 0, }); }; + +/// CRC calculation unit pub const CRC = extern struct { pub const Address: u32 = 0x40023000; - // byte offset: 0 Data register - pub const DR = mmio(Address + 0x00000000, 32, packed struct { - DR: u32, // bit offset: 0 desc: Data Register - }); - // byte offset: 4 Independent Data register + + /// Data register + pub const DR = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Independent Data register pub const IDR = mmio(Address + 0x00000004, 32, packed struct { - IDR: u8, // bit offset: 0 desc: Independent Data register + /// Independent Data register + IDR: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -17006,9 +21443,11 @@ pub const CRC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Control register + + /// Control register pub const CR = mmio(Address + 0x00000008, 32, packed struct { - RESET: u1, // bit offset: 0 desc: Reset bit + /// Reset bit + RESET: u1 = 0, padding31: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, @@ -17042,14 +21481,21 @@ pub const CRC = extern struct { padding1: u1 = 0, }); }; + +/// FLASH pub const FLASH = extern struct { pub const Address: u32 = 0x40022000; - // byte offset: 0 Flash access control register + + /// Flash access control register pub const ACR = mmio(Address + 0x00000000, 32, packed struct { - LATENCY: u3, // bit offset: 0 desc: Latency - HLFCYA: u1, // bit offset: 3 desc: Flash half cycle access enable - PRFTBE: u1, // bit offset: 4 desc: Prefetch buffer enable - PRFTBS: u1, // bit offset: 5 desc: Prefetch buffer status + /// Latency + LATENCY: u3 = 0, + /// Flash half cycle access enable + HLFCYA: u1 = 0, + /// Prefetch buffer enable + PRFTBE: u1 = 0, + /// Prefetch buffer status + PRFTBS: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -17077,22 +21523,31 @@ pub const FLASH = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Flash key register + + /// Flash key register pub const KEYR = mmio(Address + 0x00000004, 32, packed struct { - KEY: u32, // bit offset: 0 desc: FPEC key + /// FPEC key + KEY: u32 = 0, }); - // byte offset: 8 Flash option key register + + /// Flash option key register pub const OPTKEYR = mmio(Address + 0x00000008, 32, packed struct { - OPTKEY: u32, // bit offset: 0 desc: Option byte key + /// Option byte key + OPTKEY: u32 = 0, }); - // byte offset: 12 Status register + + /// Status register pub const SR = mmio(Address + 0x0000000c, 32, packed struct { - BSY: u1, // bit offset: 0 desc: Busy + /// Busy + BSY: u1 = 0, reserved1: u1 = 0, - PGERR: u1, // bit offset: 2 desc: Programming error + /// Programming error + PGERR: u1 = 0, reserved2: u1 = 0, - WRPRTERR: u1, // bit offset: 4 desc: Write protection error - EOP: u1, // bit offset: 5 desc: End of operation + /// Write protection error + WRPRTERR: u1 = 0, + /// End of operation + EOP: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -17120,21 +21575,32 @@ pub const FLASH = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Control register + + /// Control register pub const CR = mmio(Address + 0x00000010, 32, packed struct { - PG: u1, // bit offset: 0 desc: Programming - PER: u1, // bit offset: 1 desc: Page Erase - MER: u1, // bit offset: 2 desc: Mass Erase + /// Programming + PG: u1 = 0, + /// Page Erase + PER: u1 = 0, + /// Mass Erase + MER: u1 = 0, reserved1: u1 = 0, - OPTPG: u1, // bit offset: 4 desc: Option byte programming - OPTER: u1, // bit offset: 5 desc: Option byte erase - STRT: u1, // bit offset: 6 desc: Start - LOCK: u1, // bit offset: 7 desc: Lock + /// Option byte programming + OPTPG: u1 = 0, + /// Option byte erase + OPTER: u1 = 0, + /// Start + STRT: u1 = 0, + /// Lock + LOCK: u1 = 0, reserved2: u1 = 0, - OPTWRE: u1, // bit offset: 9 desc: Option bytes write enable - ERRIE: u1, // bit offset: 10 desc: Error interrupt enable + /// Option bytes write enable + OPTWRE: u1 = 0, + /// Error interrupt enable + ERRIE: u1 = 0, reserved3: u1 = 0, - EOPIE: u1, // bit offset: 12 desc: End of operation interrupt enable + /// End of operation interrupt enable + EOPIE: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -17155,24 +21621,24 @@ pub const FLASH = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Flash address register + + /// Flash address register pub const AR = mmio(Address + 0x00000014, 32, packed struct { - FAR: u32, // bit offset: 0 desc: Flash Address + /// Flash Address + FAR: u32 = 0, }); - // byte offset: 28 Option byte register + + /// Option byte register pub const OBR = mmio(Address + 0x0000001c, 32, packed struct { - OPTERR: u1, // bit offset: 0 desc: Option byte error - RDPRT: u1, // bit offset: 1 desc: Read protection - WDG_SW: u1, // bit offset: 2 desc: WDG_SW - nRST_STOP: u1, // bit offset: 3 desc: nRST_STOP - nRST_STDBY: u1, // bit offset: 4 desc: nRST_STDBY + /// Option byte error + OPTERR: u1 = 0, + /// Read protection + RDPRT: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - Data0: u8, // bit offset: 10 desc: Data0 - Data1: u8, // bit offset: 18 desc: Data1 padding6: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, @@ -17180,16 +21646,22 @@ pub const FLASH = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 Write protection register + + /// Write protection register pub const WRPR = mmio(Address + 0x00000020, 32, packed struct { - WRP: u32, // bit offset: 0 desc: Write protect + /// Write protect + WRP: u32 = 0, }); }; + +/// Nested Vectored Interrupt Controller pub const NVIC = extern struct { pub const Address: u32 = 0xe000e000; - // byte offset: 4 Interrupt Controller Type Register + + /// Interrupt Controller Type Register pub const ICTR = mmio(Address + 0x00000004, 32, packed struct { - INTLINESNUM: u4, // bit offset: 0 desc: Total number of interrupt lines in groups + /// Total number of interrupt lines in groups + INTLINESNUM: u4 = 0, padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -17219,154 +21691,86 @@ pub const NVIC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 256 Interrupt Set-Enable Register - pub const ISER0 = mmio(Address + 0x00000100, 32, packed struct { - SETENA: u32, // bit offset: 0 desc: SETENA - }); - // byte offset: 260 Interrupt Set-Enable Register - pub const ISER1 = mmio(Address + 0x00000104, 32, packed struct { - SETENA: u32, // bit offset: 0 desc: SETENA - }); - // byte offset: 384 Interrupt Clear-Enable Register - pub const ICER0 = mmio(Address + 0x00000180, 32, packed struct { - CLRENA: u32, // bit offset: 0 desc: CLRENA - }); - // byte offset: 388 Interrupt Clear-Enable Register - pub const ICER1 = mmio(Address + 0x00000184, 32, packed struct { - CLRENA: u32, // bit offset: 0 desc: CLRENA - }); - // byte offset: 512 Interrupt Set-Pending Register - pub const ISPR0 = mmio(Address + 0x00000200, 32, packed struct { - SETPEND: u32, // bit offset: 0 desc: SETPEND - }); - // byte offset: 516 Interrupt Set-Pending Register - pub const ISPR1 = mmio(Address + 0x00000204, 32, packed struct { - SETPEND: u32, // bit offset: 0 desc: SETPEND - }); - // byte offset: 640 Interrupt Clear-Pending Register - pub const ICPR0 = mmio(Address + 0x00000280, 32, packed struct { - CLRPEND: u32, // bit offset: 0 desc: CLRPEND - }); - // byte offset: 644 Interrupt Clear-Pending Register - pub const ICPR1 = mmio(Address + 0x00000284, 32, packed struct { - CLRPEND: u32, // bit offset: 0 desc: CLRPEND - }); - // byte offset: 768 Interrupt Active Bit Register - pub const IABR0 = mmio(Address + 0x00000300, 32, packed struct { - ACTIVE: u32, // bit offset: 0 desc: ACTIVE - }); - // byte offset: 772 Interrupt Active Bit Register - pub const IABR1 = mmio(Address + 0x00000304, 32, packed struct { - ACTIVE: u32, // bit offset: 0 desc: ACTIVE - }); - // byte offset: 1024 Interrupt Priority Register - pub const IPR0 = mmio(Address + 0x00000400, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1028 Interrupt Priority Register - pub const IPR1 = mmio(Address + 0x00000404, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1032 Interrupt Priority Register - pub const IPR2 = mmio(Address + 0x00000408, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1036 Interrupt Priority Register - pub const IPR3 = mmio(Address + 0x0000040c, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1040 Interrupt Priority Register - pub const IPR4 = mmio(Address + 0x00000410, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1044 Interrupt Priority Register - pub const IPR5 = mmio(Address + 0x00000414, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1048 Interrupt Priority Register - pub const IPR6 = mmio(Address + 0x00000418, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1052 Interrupt Priority Register - pub const IPR7 = mmio(Address + 0x0000041c, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1056 Interrupt Priority Register - pub const IPR8 = mmio(Address + 0x00000420, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1060 Interrupt Priority Register - pub const IPR9 = mmio(Address + 0x00000424, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1064 Interrupt Priority Register - pub const IPR10 = mmio(Address + 0x00000428, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1068 Interrupt Priority Register - pub const IPR11 = mmio(Address + 0x0000042c, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1072 Interrupt Priority Register - pub const IPR12 = mmio(Address + 0x00000430, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1076 Interrupt Priority Register - pub const IPR13 = mmio(Address + 0x00000434, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1080 Interrupt Priority Register - pub const IPR14 = mmio(Address + 0x00000438, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 3840 Software Triggered Interrupt Register + + /// Interrupt Set-Enable Register + pub const ISER0 = mmio(Address + 0x00000100, 32, packed struct {}); + + /// Interrupt Set-Enable Register + pub const ISER1 = mmio(Address + 0x00000104, 32, packed struct {}); + + /// Interrupt Clear-Enable Register + pub const ICER0 = mmio(Address + 0x00000180, 32, packed struct {}); + + /// Interrupt Clear-Enable Register + pub const ICER1 = mmio(Address + 0x00000184, 32, packed struct {}); + + /// Interrupt Set-Pending Register + pub const ISPR0 = mmio(Address + 0x00000200, 32, packed struct {}); + + /// Interrupt Set-Pending Register + pub const ISPR1 = mmio(Address + 0x00000204, 32, packed struct {}); + + /// Interrupt Clear-Pending Register + pub const ICPR0 = mmio(Address + 0x00000280, 32, packed struct {}); + + /// Interrupt Clear-Pending Register + pub const ICPR1 = mmio(Address + 0x00000284, 32, packed struct {}); + + /// Interrupt Active Bit Register + pub const IABR0 = mmio(Address + 0x00000300, 32, packed struct {}); + + /// Interrupt Active Bit Register + pub const IABR1 = mmio(Address + 0x00000304, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR0 = mmio(Address + 0x00000400, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR1 = mmio(Address + 0x00000404, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR2 = mmio(Address + 0x00000408, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR3 = mmio(Address + 0x0000040c, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR4 = mmio(Address + 0x00000410, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR5 = mmio(Address + 0x00000414, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR6 = mmio(Address + 0x00000418, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR7 = mmio(Address + 0x0000041c, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR8 = mmio(Address + 0x00000420, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR9 = mmio(Address + 0x00000424, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR10 = mmio(Address + 0x00000428, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR11 = mmio(Address + 0x0000042c, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR12 = mmio(Address + 0x00000430, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR13 = mmio(Address + 0x00000434, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR14 = mmio(Address + 0x00000438, 32, packed struct {}); + + /// Software Triggered Interrupt Register pub const STIR = mmio(Address + 0x00000f00, 32, packed struct { - INTID: u9, // bit offset: 0 desc: interrupt to be triggered + /// interrupt to be triggered + INTID: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -17392,20 +21796,33 @@ pub const NVIC = extern struct { padding1: u1 = 0, }); }; + +/// Universal serial bus full-speed device interface pub const USB = extern struct { pub const Address: u32 = 0x40005c00; - // byte offset: 0 endpoint 0 register + + /// endpoint 0 register pub const EP0R = mmio(Address + 0x00000000, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17423,18 +21840,29 @@ pub const USB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 endpoint 1 register + + /// endpoint 1 register pub const EP1R = mmio(Address + 0x00000004, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17452,18 +21880,29 @@ pub const USB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 endpoint 2 register + + /// endpoint 2 register pub const EP2R = mmio(Address + 0x00000008, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17481,18 +21920,29 @@ pub const USB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 endpoint 3 register + + /// endpoint 3 register pub const EP3R = mmio(Address + 0x0000000c, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17510,18 +21960,29 @@ pub const USB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 endpoint 4 register + + /// endpoint 4 register pub const EP4R = mmio(Address + 0x00000010, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17539,18 +22000,29 @@ pub const USB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 endpoint 5 register + + /// endpoint 5 register pub const EP5R = mmio(Address + 0x00000014, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17568,18 +22040,29 @@ pub const USB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 endpoint 6 register + + /// endpoint 6 register pub const EP6R = mmio(Address + 0x00000018, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17597,18 +22080,29 @@ pub const USB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 endpoint 7 register + + /// endpoint 7 register pub const EP7R = mmio(Address + 0x0000001c, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17626,24 +22120,38 @@ pub const USB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 control register + + /// control register pub const CNTR = mmio(Address + 0x00000040, 32, packed struct { - FRES: u1, // bit offset: 0 desc: Force USB Reset - PDWN: u1, // bit offset: 1 desc: Power down - LPMODE: u1, // bit offset: 2 desc: Low-power mode - FSUSP: u1, // bit offset: 3 desc: Force suspend - RESUME: u1, // bit offset: 4 desc: Resume request + /// Force USB Reset + FRES: u1 = 0, + /// Power down + PDWN: u1 = 0, + /// Low-power mode + LPMODE: u1 = 0, + /// Force suspend + FSUSP: u1 = 0, + /// Resume request + RESUME: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ESOFM: u1, // bit offset: 8 desc: Expected start of frame interrupt mask - SOFM: u1, // bit offset: 9 desc: Start of frame interrupt mask - RESETM: u1, // bit offset: 10 desc: USB reset interrupt mask - SUSPM: u1, // bit offset: 11 desc: Suspend mode interrupt mask - WKUPM: u1, // bit offset: 12 desc: Wakeup interrupt mask - ERRM: u1, // bit offset: 13 desc: Error interrupt mask - PMAOVRM: u1, // bit offset: 14 desc: Packet memory area over / underrun interrupt mask - CTRM: u1, // bit offset: 15 desc: Correct transfer interrupt mask + /// Expected start of frame interrupt mask + ESOFM: u1 = 0, + /// Start of frame interrupt mask + SOFM: u1 = 0, + /// USB reset interrupt mask + RESETM: u1 = 0, + /// Suspend mode interrupt mask + SUSPM: u1 = 0, + /// Wakeup interrupt mask + WKUPM: u1 = 0, + /// Error interrupt mask + ERRM: u1 = 0, + /// Packet memory area over / underrun interrupt mask + PMAOVRM: u1 = 0, + /// Correct transfer interrupt mask + CTRM: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17661,21 +22169,32 @@ pub const USB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 interrupt status register + + /// interrupt status register pub const ISTR = mmio(Address + 0x00000044, 32, packed struct { - EP_ID: u4, // bit offset: 0 desc: Endpoint Identifier - DIR: u1, // bit offset: 4 desc: Direction of transaction + /// Endpoint Identifier + EP_ID: u4 = 0, + /// Direction of transaction + DIR: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ESOF: u1, // bit offset: 8 desc: Expected start frame - SOF: u1, // bit offset: 9 desc: start of frame - RESET: u1, // bit offset: 10 desc: reset request - SUSP: u1, // bit offset: 11 desc: Suspend mode request - WKUP: u1, // bit offset: 12 desc: Wakeup - ERR: u1, // bit offset: 13 desc: Error - PMAOVR: u1, // bit offset: 14 desc: Packet memory area over / underrun - CTR: u1, // bit offset: 15 desc: Correct transfer + /// Expected start frame + ESOF: u1 = 0, + /// start of frame + SOF: u1 = 0, + /// reset request + RESET: u1 = 0, + /// Suspend mode request + SUSP: u1 = 0, + /// Wakeup + WKUP: u1 = 0, + /// Error + ERR: u1 = 0, + /// Packet memory area over / underrun + PMAOVR: u1 = 0, + /// Correct transfer + CTR: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17693,13 +22212,19 @@ pub const USB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 frame number register + + /// frame number register pub const FNR = mmio(Address + 0x00000048, 32, packed struct { - FN: u11, // bit offset: 0 desc: Frame number - LSOF: u2, // bit offset: 11 desc: Lost SOF - LCK: u1, // bit offset: 13 desc: Locked - RXDM: u1, // bit offset: 14 desc: Receive data - line status - RXDP: u1, // bit offset: 15 desc: Receive data + line status + /// Frame number + FN: u11 = 0, + /// Lost SOF + LSOF: u2 = 0, + /// Locked + LCK: u1 = 0, + /// Receive data - line status + RXDM: u1 = 0, + /// Receive data + line status + RXDP: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17717,10 +22242,13 @@ pub const USB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 device address + + /// device address pub const DADDR = mmio(Address + 0x0000004c, 32, packed struct { - ADD: u7, // bit offset: 0 desc: Device address - EF: u1, // bit offset: 7 desc: Enable function + /// Device address + ADD: u7 = 0, + /// Enable function + EF: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -17746,12 +22274,14 @@ pub const USB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 80 Buffer table address + + /// Buffer table address pub const BTABLE = mmio(Address + 0x00000050, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - BTABLE: u13, // bit offset: 3 desc: Buffer table + /// Buffer table + BTABLE: u13 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17810,181 +22340,122 @@ pub const VectorTable = extern struct { /// Window Watchdog interrupt WWDG: InterruptVector = makeUnhandledHandler("WWDG"), - /// PVD through EXTI line detection interrupt PVD: InterruptVector = makeUnhandledHandler("PVD"), - /// Tamper interrupt TAMPER: InterruptVector = makeUnhandledHandler("TAMPER"), - /// RTC global interrupt RTC: InterruptVector = makeUnhandledHandler("RTC"), - /// Flash global interrupt FLASH: InterruptVector = makeUnhandledHandler("FLASH"), - /// RCC global interrupt RCC: InterruptVector = makeUnhandledHandler("RCC"), - /// EXTI Line0 interrupt EXTI0: InterruptVector = makeUnhandledHandler("EXTI0"), - /// EXTI Line1 interrupt EXTI1: InterruptVector = makeUnhandledHandler("EXTI1"), - /// EXTI Line2 interrupt EXTI2: InterruptVector = makeUnhandledHandler("EXTI2"), - /// EXTI Line3 interrupt EXTI3: InterruptVector = makeUnhandledHandler("EXTI3"), - /// EXTI Line4 interrupt EXTI4: InterruptVector = makeUnhandledHandler("EXTI4"), - /// DMA1 Channel1 global interrupt DMA1_Channel1: InterruptVector = makeUnhandledHandler("DMA1_Channel1"), - /// DMA1 Channel2 global interrupt DMA1_Channel2: InterruptVector = makeUnhandledHandler("DMA1_Channel2"), - /// DMA1 Channel3 global interrupt DMA1_Channel3: InterruptVector = makeUnhandledHandler("DMA1_Channel3"), - /// DMA1 Channel4 global interrupt DMA1_Channel4: InterruptVector = makeUnhandledHandler("DMA1_Channel4"), - /// DMA1 Channel5 global interrupt DMA1_Channel5: InterruptVector = makeUnhandledHandler("DMA1_Channel5"), - /// DMA1 Channel6 global interrupt DMA1_Channel6: InterruptVector = makeUnhandledHandler("DMA1_Channel6"), - /// DMA1 Channel7 global interrupt DMA1_Channel7: InterruptVector = makeUnhandledHandler("DMA1_Channel7"), - /// ADC1 global interrupt; ADC2 global interrupt ADC: InterruptVector = makeUnhandledHandler("ADC"), - /// CAN1 TX interrupts CAN1_TX: InterruptVector = makeUnhandledHandler("CAN1_TX"), - /// CAN1 RX0 interrupts CAN1_RX0: InterruptVector = makeUnhandledHandler("CAN1_RX0"), - /// CAN1 RX1 interrupt CAN1_RX1: InterruptVector = makeUnhandledHandler("CAN1_RX1"), - /// CAN1 SCE interrupt CAN1_SCE: InterruptVector = makeUnhandledHandler("CAN1_SCE"), - /// EXTI Line[9:5] interrupts EXTI9_5: InterruptVector = makeUnhandledHandler("EXTI9_5"), - /// TIM1 Break interrupt and TIM9 global interrupt TIM1_BRK_TIM9: InterruptVector = makeUnhandledHandler("TIM1_BRK_TIM9"), - /// TIM1 Update interrupt and TIM10 global interrupt TIM1_UP_TIM10: InterruptVector = makeUnhandledHandler("TIM1_UP_TIM10"), - /// TIM1 Trigger and Commutation interrupts and TIM11 global interrupt TIM1_TRG_COM_TIM11: InterruptVector = makeUnhandledHandler("TIM1_TRG_COM_TIM11"), - /// TIM1 Capture Compare interrupt TIM1_CC: InterruptVector = makeUnhandledHandler("TIM1_CC"), - /// TIM2 global interrupt TIM2: InterruptVector = makeUnhandledHandler("TIM2"), - /// TIM3 global interrupt TIM3: InterruptVector = makeUnhandledHandler("TIM3"), - /// TIM4 global interrupt TIM4: InterruptVector = makeUnhandledHandler("TIM4"), - /// I2C1 event interrupt I2C1_EV: InterruptVector = makeUnhandledHandler("I2C1_EV"), - /// I2C1 error interrupt I2C1_ER: InterruptVector = makeUnhandledHandler("I2C1_ER"), - /// I2C2 event interrupt I2C2_EV: InterruptVector = makeUnhandledHandler("I2C2_EV"), - /// I2C2 error interrupt I2C2_ER: InterruptVector = makeUnhandledHandler("I2C2_ER"), - /// SPI1 global interrupt SPI1: InterruptVector = makeUnhandledHandler("SPI1"), - /// SPI2 global interrupt SPI2: InterruptVector = makeUnhandledHandler("SPI2"), - /// USART1 global interrupt USART1: InterruptVector = makeUnhandledHandler("USART1"), - /// USART2 global interrupt USART2: InterruptVector = makeUnhandledHandler("USART2"), - /// USART3 global interrupt USART3: InterruptVector = makeUnhandledHandler("USART3"), - /// EXTI Line[15:10] interrupts EXTI15_10: InterruptVector = makeUnhandledHandler("EXTI15_10"), - /// RTC Alarms through EXTI line interrupt RTCAlarm: InterruptVector = makeUnhandledHandler("RTCAlarm"), - /// USB Device FS Wakeup through EXTI line interrupt USB_FS_WKUP: InterruptVector = makeUnhandledHandler("USB_FS_WKUP"), - /// TIM8 Break interrupt and TIM12 global interrupt TIM8_BRK_TIM12: InterruptVector = makeUnhandledHandler("TIM8_BRK_TIM12"), - /// TIM8 Update interrupt and TIM13 global interrupt TIM8_UP_TIM13: InterruptVector = makeUnhandledHandler("TIM8_UP_TIM13"), - /// TIM8 Trigger and Commutation interrupts and TIM14 global interrupt TIM8_TRG_COM_TIM14: InterruptVector = makeUnhandledHandler("TIM8_TRG_COM_TIM14"), - /// TIM8 Capture Compare interrupt TIM8_CC: InterruptVector = makeUnhandledHandler("TIM8_CC"), - /// ADC3 global interrupt ADC3: InterruptVector = makeUnhandledHandler("ADC3"), - /// FSMC global interrupt FSMC: InterruptVector = makeUnhandledHandler("FSMC"), - /// SDIO global interrupt SDIO: InterruptVector = makeUnhandledHandler("SDIO"), - /// TIM5 global interrupt TIM5: InterruptVector = makeUnhandledHandler("TIM5"), - /// SPI3 global interrupt SPI3: InterruptVector = makeUnhandledHandler("SPI3"), - /// UART4 global interrupt UART4: InterruptVector = makeUnhandledHandler("UART4"), - /// UART5 global interrupt UART5: InterruptVector = makeUnhandledHandler("UART5"), - /// TIM6 global interrupt TIM6: InterruptVector = makeUnhandledHandler("TIM6"), - /// TIM7 global interrupt TIM7: InterruptVector = makeUnhandledHandler("TIM7"), - /// DMA2 Channel1 global interrupt DMA2_Channel1: InterruptVector = makeUnhandledHandler("DMA2_Channel1"), - /// DMA2 Channel2 global interrupt DMA2_Channel2: InterruptVector = makeUnhandledHandler("DMA2_Channel2"), - /// DMA2 Channel3 global interrupt DMA2_Channel3: InterruptVector = makeUnhandledHandler("DMA2_Channel3"), - /// DMA2 Channel4 and DMA2 Channel5 global interrupt DMA2_Channel4_5: InterruptVector = makeUnhandledHandler("DMA2_Channel4_5"), }; @@ -18039,4 +22510,3 @@ export const vectors: VectorTable linksection("microzig_flash_start") = blk: { } break :blk temp; }; - diff --git a/src/modules/chips/stm32f303/registers.zig b/src/modules/chips/stm32f303/registers.zig index fb286b3..88c3635 100644 --- a/src/modules/chips/stm32f303/registers.zig +++ b/src/modules/chips/stm32f303/registers.zig @@ -1,47 +1,85 @@ // generated using svd2zig.py // DO NOT EDIT // based on STM32F303 version 1.4 -const mmio = @import("microzig-mmio").mmio; +const microzig_mmio = @import("microzig-mmio"); +const mmio = microzig_mmio.mmio; +const MMIO = microzig_mmio.MMIO; const Name = "STM32F303"; + +/// General-purpose I/Os pub const GPIOA = extern struct { pub const Address: u32 = 0x48000000; - // byte offset: 0 GPIO port mode register + + /// GPIO port mode register pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - MODER0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - MODER1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - MODER2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - MODER3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - MODER4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - MODER5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - MODER6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - MODER7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - MODER8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - MODER9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - MODER10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - MODER11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - MODER12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - MODER13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - MODER14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - MODER15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 4 GPIO port output type register + /// Port x configuration bits (y = 0..15) + MODER0: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER1: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER2: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER3: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER4: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER5: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER6: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER7: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER8: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER9: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER10: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER11: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER12: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER13: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER14: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER15: u2 = 0, + }); + + /// GPIO port output type register pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - OT0: u1, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - OT1: u1, // bit offset: 1 desc: Port x configuration bits (y = 0..15) - OT2: u1, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - OT3: u1, // bit offset: 3 desc: Port x configuration bits (y = 0..15) - OT4: u1, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - OT5: u1, // bit offset: 5 desc: Port x configuration bits (y = 0..15) - OT6: u1, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - OT7: u1, // bit offset: 7 desc: Port x configuration bits (y = 0..15) - OT8: u1, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - OT9: u1, // bit offset: 9 desc: Port x configuration bits (y = 0..15) - OT10: u1, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - OT11: u1, // bit offset: 11 desc: Port x configuration bits (y = 0..15) - OT12: u1, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - OT13: u1, // bit offset: 13 desc: Port x configuration bits (y = 0..15) - OT14: u1, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - OT15: u1, // bit offset: 15 desc: Port x configuration bits (y = 0..15) + /// Port x configuration bits (y = 0..15) + OT0: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT1: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT2: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT3: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT4: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT5: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT6: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT7: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT8: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT9: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT10: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT11: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT12: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT13: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT14: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -59,62 +97,113 @@ pub const GPIOA = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 GPIO port output speed register + + /// GPIO port output speed register pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - OSPEEDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - OSPEEDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - OSPEEDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - OSPEEDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - OSPEEDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - OSPEEDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - OSPEEDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - OSPEEDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - OSPEEDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - OSPEEDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - OSPEEDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - OSPEEDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - OSPEEDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - OSPEEDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - OSPEEDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - OSPEEDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 12 GPIO port pull-up/pull-down register + /// Port x configuration bits (y = 0..15) + OSPEEDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR15: u2 = 0, + }); + + /// GPIO port pull-up/pull-down register pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - PUPDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - PUPDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - PUPDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - PUPDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - PUPDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - PUPDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - PUPDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - PUPDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - PUPDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - PUPDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - PUPDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - PUPDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - PUPDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - PUPDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - PUPDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - PUPDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 16 GPIO port input data register + /// Port x configuration bits (y = 0..15) + PUPDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR15: u2 = 0, + }); + + /// GPIO port input data register pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data (y = 0..15) - IDR1: u1, // bit offset: 1 desc: Port input data (y = 0..15) - IDR2: u1, // bit offset: 2 desc: Port input data (y = 0..15) - IDR3: u1, // bit offset: 3 desc: Port input data (y = 0..15) - IDR4: u1, // bit offset: 4 desc: Port input data (y = 0..15) - IDR5: u1, // bit offset: 5 desc: Port input data (y = 0..15) - IDR6: u1, // bit offset: 6 desc: Port input data (y = 0..15) - IDR7: u1, // bit offset: 7 desc: Port input data (y = 0..15) - IDR8: u1, // bit offset: 8 desc: Port input data (y = 0..15) - IDR9: u1, // bit offset: 9 desc: Port input data (y = 0..15) - IDR10: u1, // bit offset: 10 desc: Port input data (y = 0..15) - IDR11: u1, // bit offset: 11 desc: Port input data (y = 0..15) - IDR12: u1, // bit offset: 12 desc: Port input data (y = 0..15) - IDR13: u1, // bit offset: 13 desc: Port input data (y = 0..15) - IDR14: u1, // bit offset: 14 desc: Port input data (y = 0..15) - IDR15: u1, // bit offset: 15 desc: Port input data (y = 0..15) + /// Port input data (y = 0..15) + IDR0: u1 = 0, + /// Port input data (y = 0..15) + IDR1: u1 = 0, + /// Port input data (y = 0..15) + IDR2: u1 = 0, + /// Port input data (y = 0..15) + IDR3: u1 = 0, + /// Port input data (y = 0..15) + IDR4: u1 = 0, + /// Port input data (y = 0..15) + IDR5: u1 = 0, + /// Port input data (y = 0..15) + IDR6: u1 = 0, + /// Port input data (y = 0..15) + IDR7: u1 = 0, + /// Port input data (y = 0..15) + IDR8: u1 = 0, + /// Port input data (y = 0..15) + IDR9: u1 = 0, + /// Port input data (y = 0..15) + IDR10: u1 = 0, + /// Port input data (y = 0..15) + IDR11: u1 = 0, + /// Port input data (y = 0..15) + IDR12: u1 = 0, + /// Port input data (y = 0..15) + IDR13: u1 = 0, + /// Port input data (y = 0..15) + IDR14: u1 = 0, + /// Port input data (y = 0..15) + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -132,24 +221,41 @@ pub const GPIOA = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 GPIO port output data register + + /// GPIO port output data register pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data (y = 0..15) - ODR1: u1, // bit offset: 1 desc: Port output data (y = 0..15) - ODR2: u1, // bit offset: 2 desc: Port output data (y = 0..15) - ODR3: u1, // bit offset: 3 desc: Port output data (y = 0..15) - ODR4: u1, // bit offset: 4 desc: Port output data (y = 0..15) - ODR5: u1, // bit offset: 5 desc: Port output data (y = 0..15) - ODR6: u1, // bit offset: 6 desc: Port output data (y = 0..15) - ODR7: u1, // bit offset: 7 desc: Port output data (y = 0..15) - ODR8: u1, // bit offset: 8 desc: Port output data (y = 0..15) - ODR9: u1, // bit offset: 9 desc: Port output data (y = 0..15) - ODR10: u1, // bit offset: 10 desc: Port output data (y = 0..15) - ODR11: u1, // bit offset: 11 desc: Port output data (y = 0..15) - ODR12: u1, // bit offset: 12 desc: Port output data (y = 0..15) - ODR13: u1, // bit offset: 13 desc: Port output data (y = 0..15) - ODR14: u1, // bit offset: 14 desc: Port output data (y = 0..15) - ODR15: u1, // bit offset: 15 desc: Port output data (y = 0..15) + /// Port output data (y = 0..15) + ODR0: u1 = 0, + /// Port output data (y = 0..15) + ODR1: u1 = 0, + /// Port output data (y = 0..15) + ODR2: u1 = 0, + /// Port output data (y = 0..15) + ODR3: u1 = 0, + /// Port output data (y = 0..15) + ODR4: u1 = 0, + /// Port output data (y = 0..15) + ODR5: u1 = 0, + /// Port output data (y = 0..15) + ODR6: u1 = 0, + /// Port output data (y = 0..15) + ODR7: u1 = 0, + /// Port output data (y = 0..15) + ODR8: u1 = 0, + /// Port output data (y = 0..15) + ODR9: u1 = 0, + /// Port output data (y = 0..15) + ODR10: u1 = 0, + /// Port output data (y = 0..15) + ODR11: u1 = 0, + /// Port output data (y = 0..15) + ODR12: u1 = 0, + /// Port output data (y = 0..15) + ODR13: u1 = 0, + /// Port output data (y = 0..15) + ODR14: u1 = 0, + /// Port output data (y = 0..15) + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -167,60 +273,111 @@ pub const GPIOA = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 GPIO port bit set/reset register + + /// GPIO port bit set/reset register pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Port x set bit y (y= 0..15) - BS1: u1, // bit offset: 1 desc: Port x set bit y (y= 0..15) - BS2: u1, // bit offset: 2 desc: Port x set bit y (y= 0..15) - BS3: u1, // bit offset: 3 desc: Port x set bit y (y= 0..15) - BS4: u1, // bit offset: 4 desc: Port x set bit y (y= 0..15) - BS5: u1, // bit offset: 5 desc: Port x set bit y (y= 0..15) - BS6: u1, // bit offset: 6 desc: Port x set bit y (y= 0..15) - BS7: u1, // bit offset: 7 desc: Port x set bit y (y= 0..15) - BS8: u1, // bit offset: 8 desc: Port x set bit y (y= 0..15) - BS9: u1, // bit offset: 9 desc: Port x set bit y (y= 0..15) - BS10: u1, // bit offset: 10 desc: Port x set bit y (y= 0..15) - BS11: u1, // bit offset: 11 desc: Port x set bit y (y= 0..15) - BS12: u1, // bit offset: 12 desc: Port x set bit y (y= 0..15) - BS13: u1, // bit offset: 13 desc: Port x set bit y (y= 0..15) - BS14: u1, // bit offset: 14 desc: Port x set bit y (y= 0..15) - BS15: u1, // bit offset: 15 desc: Port x set bit y (y= 0..15) - BR0: u1, // bit offset: 16 desc: Port x set bit y (y= 0..15) - BR1: u1, // bit offset: 17 desc: Port x reset bit y (y = 0..15) - BR2: u1, // bit offset: 18 desc: Port x reset bit y (y = 0..15) - BR3: u1, // bit offset: 19 desc: Port x reset bit y (y = 0..15) - BR4: u1, // bit offset: 20 desc: Port x reset bit y (y = 0..15) - BR5: u1, // bit offset: 21 desc: Port x reset bit y (y = 0..15) - BR6: u1, // bit offset: 22 desc: Port x reset bit y (y = 0..15) - BR7: u1, // bit offset: 23 desc: Port x reset bit y (y = 0..15) - BR8: u1, // bit offset: 24 desc: Port x reset bit y (y = 0..15) - BR9: u1, // bit offset: 25 desc: Port x reset bit y (y = 0..15) - BR10: u1, // bit offset: 26 desc: Port x reset bit y (y = 0..15) - BR11: u1, // bit offset: 27 desc: Port x reset bit y (y = 0..15) - BR12: u1, // bit offset: 28 desc: Port x reset bit y (y = 0..15) - BR13: u1, // bit offset: 29 desc: Port x reset bit y (y = 0..15) - BR14: u1, // bit offset: 30 desc: Port x reset bit y (y = 0..15) - BR15: u1, // bit offset: 31 desc: Port x reset bit y (y = 0..15) - }); - // byte offset: 28 GPIO port configuration lock register + /// Port x set bit y (y= 0..15) + BS0: u1 = 0, + /// Port x set bit y (y= 0..15) + BS1: u1 = 0, + /// Port x set bit y (y= 0..15) + BS2: u1 = 0, + /// Port x set bit y (y= 0..15) + BS3: u1 = 0, + /// Port x set bit y (y= 0..15) + BS4: u1 = 0, + /// Port x set bit y (y= 0..15) + BS5: u1 = 0, + /// Port x set bit y (y= 0..15) + BS6: u1 = 0, + /// Port x set bit y (y= 0..15) + BS7: u1 = 0, + /// Port x set bit y (y= 0..15) + BS8: u1 = 0, + /// Port x set bit y (y= 0..15) + BS9: u1 = 0, + /// Port x set bit y (y= 0..15) + BS10: u1 = 0, + /// Port x set bit y (y= 0..15) + BS11: u1 = 0, + /// Port x set bit y (y= 0..15) + BS12: u1 = 0, + /// Port x set bit y (y= 0..15) + BS13: u1 = 0, + /// Port x set bit y (y= 0..15) + BS14: u1 = 0, + /// Port x set bit y (y= 0..15) + BS15: u1 = 0, + /// Port x set bit y (y= 0..15) + BR0: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR1: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR2: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR3: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR4: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR5: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR6: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR7: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR8: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR9: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR10: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR11: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR12: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR13: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR14: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR15: u1 = 0, + }); + + /// GPIO port configuration lock register pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port x lock bit y (y= 0..15) - LCK1: u1, // bit offset: 1 desc: Port x lock bit y (y= 0..15) - LCK2: u1, // bit offset: 2 desc: Port x lock bit y (y= 0..15) - LCK3: u1, // bit offset: 3 desc: Port x lock bit y (y= 0..15) - LCK4: u1, // bit offset: 4 desc: Port x lock bit y (y= 0..15) - LCK5: u1, // bit offset: 5 desc: Port x lock bit y (y= 0..15) - LCK6: u1, // bit offset: 6 desc: Port x lock bit y (y= 0..15) - LCK7: u1, // bit offset: 7 desc: Port x lock bit y (y= 0..15) - LCK8: u1, // bit offset: 8 desc: Port x lock bit y (y= 0..15) - LCK9: u1, // bit offset: 9 desc: Port x lock bit y (y= 0..15) - LCK10: u1, // bit offset: 10 desc: Port x lock bit y (y= 0..15) - LCK11: u1, // bit offset: 11 desc: Port x lock bit y (y= 0..15) - LCK12: u1, // bit offset: 12 desc: Port x lock bit y (y= 0..15) - LCK13: u1, // bit offset: 13 desc: Port x lock bit y (y= 0..15) - LCK14: u1, // bit offset: 14 desc: Port x lock bit y (y= 0..15) - LCK15: u1, // bit offset: 15 desc: Port x lock bit y (y= 0..15) - LCKK: u1, // bit offset: 16 desc: Lok Key + /// Port x lock bit y (y= 0..15) + LCK0: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK1: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK2: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK3: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK4: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK5: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK6: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK7: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK8: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK9: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK10: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK11: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK12: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK13: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK14: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK15: u1 = 0, + /// Lok Key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -237,46 +394,81 @@ pub const GPIOA = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 GPIO alternate function low register + + /// GPIO alternate function low register pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - AFRL0: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 0..7) - }); - // byte offset: 36 GPIO alternate function high register + /// Alternate function selection for port x bit y (y = 0..7) + AFRL0: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4 = 0, + }); + + /// GPIO alternate function high register pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - AFRH8: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 8..15) - }); - // byte offset: 40 Port bit reset register + /// Alternate function selection for port x bit y (y = 8..15) + AFRH8: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4 = 0, + }); + + /// Port bit reset register pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Port x Reset bit y - BR1: u1, // bit offset: 1 desc: Port x Reset bit y - BR2: u1, // bit offset: 2 desc: Port x Reset bit y - BR3: u1, // bit offset: 3 desc: Port x Reset bit y - BR4: u1, // bit offset: 4 desc: Port x Reset bit y - BR5: u1, // bit offset: 5 desc: Port x Reset bit y - BR6: u1, // bit offset: 6 desc: Port x Reset bit y - BR7: u1, // bit offset: 7 desc: Port x Reset bit y - BR8: u1, // bit offset: 8 desc: Port x Reset bit y - BR9: u1, // bit offset: 9 desc: Port x Reset bit y - BR10: u1, // bit offset: 10 desc: Port x Reset bit y - BR11: u1, // bit offset: 11 desc: Port x Reset bit y - BR12: u1, // bit offset: 12 desc: Port x Reset bit y - BR13: u1, // bit offset: 13 desc: Port x Reset bit y - BR14: u1, // bit offset: 14 desc: Port x Reset bit y - BR15: u1, // bit offset: 15 desc: Port x Reset bit y + /// Port x Reset bit y + BR0: u1 = 0, + /// Port x Reset bit y + BR1: u1 = 0, + /// Port x Reset bit y + BR2: u1 = 0, + /// Port x Reset bit y + BR3: u1 = 0, + /// Port x Reset bit y + BR4: u1 = 0, + /// Port x Reset bit y + BR5: u1 = 0, + /// Port x Reset bit y + BR6: u1 = 0, + /// Port x Reset bit y + BR7: u1 = 0, + /// Port x Reset bit y + BR8: u1 = 0, + /// Port x Reset bit y + BR9: u1 = 0, + /// Port x Reset bit y + BR10: u1 = 0, + /// Port x Reset bit y + BR11: u1 = 0, + /// Port x Reset bit y + BR12: u1 = 0, + /// Port x Reset bit y + BR13: u1 = 0, + /// Port x Reset bit y + BR14: u1 = 0, + /// Port x Reset bit y + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -295,45 +487,81 @@ pub const GPIOA = extern struct { padding1: u1 = 0, }); }; + +/// General-purpose I/Os pub const GPIOB = extern struct { pub const Address: u32 = 0x48000400; - // byte offset: 0 GPIO port mode register + + /// GPIO port mode register pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - MODER0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - MODER1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - MODER2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - MODER3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - MODER4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - MODER5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - MODER6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - MODER7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - MODER8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - MODER9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - MODER10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - MODER11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - MODER12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - MODER13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - MODER14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - MODER15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 4 GPIO port output type register + /// Port x configuration bits (y = 0..15) + MODER0: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER1: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER2: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER3: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER4: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER5: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER6: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER7: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER8: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER9: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER10: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER11: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER12: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER13: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER14: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER15: u2 = 0, + }); + + /// GPIO port output type register pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - OT0: u1, // bit offset: 0 desc: Port x configuration bit 0 - OT1: u1, // bit offset: 1 desc: Port x configuration bit 1 - OT2: u1, // bit offset: 2 desc: Port x configuration bit 2 - OT3: u1, // bit offset: 3 desc: Port x configuration bit 3 - OT4: u1, // bit offset: 4 desc: Port x configuration bit 4 - OT5: u1, // bit offset: 5 desc: Port x configuration bit 5 - OT6: u1, // bit offset: 6 desc: Port x configuration bit 6 - OT7: u1, // bit offset: 7 desc: Port x configuration bit 7 - OT8: u1, // bit offset: 8 desc: Port x configuration bit 8 - OT9: u1, // bit offset: 9 desc: Port x configuration bit 9 - OT10: u1, // bit offset: 10 desc: Port x configuration bit 10 - OT11: u1, // bit offset: 11 desc: Port x configuration bit 11 - OT12: u1, // bit offset: 12 desc: Port x configuration bit 12 - OT13: u1, // bit offset: 13 desc: Port x configuration bit 13 - OT14: u1, // bit offset: 14 desc: Port x configuration bit 14 - OT15: u1, // bit offset: 15 desc: Port x configuration bit 15 + /// Port x configuration bit 0 + OT0: u1 = 0, + /// Port x configuration bit 1 + OT1: u1 = 0, + /// Port x configuration bit 2 + OT2: u1 = 0, + /// Port x configuration bit 3 + OT3: u1 = 0, + /// Port x configuration bit 4 + OT4: u1 = 0, + /// Port x configuration bit 5 + OT5: u1 = 0, + /// Port x configuration bit 6 + OT6: u1 = 0, + /// Port x configuration bit 7 + OT7: u1 = 0, + /// Port x configuration bit 8 + OT8: u1 = 0, + /// Port x configuration bit 9 + OT9: u1 = 0, + /// Port x configuration bit 10 + OT10: u1 = 0, + /// Port x configuration bit 11 + OT11: u1 = 0, + /// Port x configuration bit 12 + OT12: u1 = 0, + /// Port x configuration bit 13 + OT13: u1 = 0, + /// Port x configuration bit 14 + OT14: u1 = 0, + /// Port x configuration bit 15 + OT15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -351,62 +579,113 @@ pub const GPIOB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 GPIO port output speed register + + /// GPIO port output speed register pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - OSPEEDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - OSPEEDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - OSPEEDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - OSPEEDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - OSPEEDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - OSPEEDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - OSPEEDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - OSPEEDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - OSPEEDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - OSPEEDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - OSPEEDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - OSPEEDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - OSPEEDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - OSPEEDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - OSPEEDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - OSPEEDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 12 GPIO port pull-up/pull-down register + /// Port x configuration bits (y = 0..15) + OSPEEDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR15: u2 = 0, + }); + + /// GPIO port pull-up/pull-down register pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - PUPDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - PUPDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - PUPDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - PUPDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - PUPDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - PUPDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - PUPDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - PUPDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - PUPDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - PUPDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - PUPDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - PUPDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - PUPDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - PUPDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - PUPDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - PUPDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 16 GPIO port input data register + /// Port x configuration bits (y = 0..15) + PUPDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR15: u2 = 0, + }); + + /// GPIO port input data register pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data (y = 0..15) - IDR1: u1, // bit offset: 1 desc: Port input data (y = 0..15) - IDR2: u1, // bit offset: 2 desc: Port input data (y = 0..15) - IDR3: u1, // bit offset: 3 desc: Port input data (y = 0..15) - IDR4: u1, // bit offset: 4 desc: Port input data (y = 0..15) - IDR5: u1, // bit offset: 5 desc: Port input data (y = 0..15) - IDR6: u1, // bit offset: 6 desc: Port input data (y = 0..15) - IDR7: u1, // bit offset: 7 desc: Port input data (y = 0..15) - IDR8: u1, // bit offset: 8 desc: Port input data (y = 0..15) - IDR9: u1, // bit offset: 9 desc: Port input data (y = 0..15) - IDR10: u1, // bit offset: 10 desc: Port input data (y = 0..15) - IDR11: u1, // bit offset: 11 desc: Port input data (y = 0..15) - IDR12: u1, // bit offset: 12 desc: Port input data (y = 0..15) - IDR13: u1, // bit offset: 13 desc: Port input data (y = 0..15) - IDR14: u1, // bit offset: 14 desc: Port input data (y = 0..15) - IDR15: u1, // bit offset: 15 desc: Port input data (y = 0..15) + /// Port input data (y = 0..15) + IDR0: u1 = 0, + /// Port input data (y = 0..15) + IDR1: u1 = 0, + /// Port input data (y = 0..15) + IDR2: u1 = 0, + /// Port input data (y = 0..15) + IDR3: u1 = 0, + /// Port input data (y = 0..15) + IDR4: u1 = 0, + /// Port input data (y = 0..15) + IDR5: u1 = 0, + /// Port input data (y = 0..15) + IDR6: u1 = 0, + /// Port input data (y = 0..15) + IDR7: u1 = 0, + /// Port input data (y = 0..15) + IDR8: u1 = 0, + /// Port input data (y = 0..15) + IDR9: u1 = 0, + /// Port input data (y = 0..15) + IDR10: u1 = 0, + /// Port input data (y = 0..15) + IDR11: u1 = 0, + /// Port input data (y = 0..15) + IDR12: u1 = 0, + /// Port input data (y = 0..15) + IDR13: u1 = 0, + /// Port input data (y = 0..15) + IDR14: u1 = 0, + /// Port input data (y = 0..15) + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -424,24 +703,41 @@ pub const GPIOB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 GPIO port output data register + + /// GPIO port output data register pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data (y = 0..15) - ODR1: u1, // bit offset: 1 desc: Port output data (y = 0..15) - ODR2: u1, // bit offset: 2 desc: Port output data (y = 0..15) - ODR3: u1, // bit offset: 3 desc: Port output data (y = 0..15) - ODR4: u1, // bit offset: 4 desc: Port output data (y = 0..15) - ODR5: u1, // bit offset: 5 desc: Port output data (y = 0..15) - ODR6: u1, // bit offset: 6 desc: Port output data (y = 0..15) - ODR7: u1, // bit offset: 7 desc: Port output data (y = 0..15) - ODR8: u1, // bit offset: 8 desc: Port output data (y = 0..15) - ODR9: u1, // bit offset: 9 desc: Port output data (y = 0..15) - ODR10: u1, // bit offset: 10 desc: Port output data (y = 0..15) - ODR11: u1, // bit offset: 11 desc: Port output data (y = 0..15) - ODR12: u1, // bit offset: 12 desc: Port output data (y = 0..15) - ODR13: u1, // bit offset: 13 desc: Port output data (y = 0..15) - ODR14: u1, // bit offset: 14 desc: Port output data (y = 0..15) - ODR15: u1, // bit offset: 15 desc: Port output data (y = 0..15) + /// Port output data (y = 0..15) + ODR0: u1 = 0, + /// Port output data (y = 0..15) + ODR1: u1 = 0, + /// Port output data (y = 0..15) + ODR2: u1 = 0, + /// Port output data (y = 0..15) + ODR3: u1 = 0, + /// Port output data (y = 0..15) + ODR4: u1 = 0, + /// Port output data (y = 0..15) + ODR5: u1 = 0, + /// Port output data (y = 0..15) + ODR6: u1 = 0, + /// Port output data (y = 0..15) + ODR7: u1 = 0, + /// Port output data (y = 0..15) + ODR8: u1 = 0, + /// Port output data (y = 0..15) + ODR9: u1 = 0, + /// Port output data (y = 0..15) + ODR10: u1 = 0, + /// Port output data (y = 0..15) + ODR11: u1 = 0, + /// Port output data (y = 0..15) + ODR12: u1 = 0, + /// Port output data (y = 0..15) + ODR13: u1 = 0, + /// Port output data (y = 0..15) + ODR14: u1 = 0, + /// Port output data (y = 0..15) + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -459,60 +755,111 @@ pub const GPIOB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 GPIO port bit set/reset register + + /// GPIO port bit set/reset register pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Port x set bit y (y= 0..15) - BS1: u1, // bit offset: 1 desc: Port x set bit y (y= 0..15) - BS2: u1, // bit offset: 2 desc: Port x set bit y (y= 0..15) - BS3: u1, // bit offset: 3 desc: Port x set bit y (y= 0..15) - BS4: u1, // bit offset: 4 desc: Port x set bit y (y= 0..15) - BS5: u1, // bit offset: 5 desc: Port x set bit y (y= 0..15) - BS6: u1, // bit offset: 6 desc: Port x set bit y (y= 0..15) - BS7: u1, // bit offset: 7 desc: Port x set bit y (y= 0..15) - BS8: u1, // bit offset: 8 desc: Port x set bit y (y= 0..15) - BS9: u1, // bit offset: 9 desc: Port x set bit y (y= 0..15) - BS10: u1, // bit offset: 10 desc: Port x set bit y (y= 0..15) - BS11: u1, // bit offset: 11 desc: Port x set bit y (y= 0..15) - BS12: u1, // bit offset: 12 desc: Port x set bit y (y= 0..15) - BS13: u1, // bit offset: 13 desc: Port x set bit y (y= 0..15) - BS14: u1, // bit offset: 14 desc: Port x set bit y (y= 0..15) - BS15: u1, // bit offset: 15 desc: Port x set bit y (y= 0..15) - BR0: u1, // bit offset: 16 desc: Port x set bit y (y= 0..15) - BR1: u1, // bit offset: 17 desc: Port x reset bit y (y = 0..15) - BR2: u1, // bit offset: 18 desc: Port x reset bit y (y = 0..15) - BR3: u1, // bit offset: 19 desc: Port x reset bit y (y = 0..15) - BR4: u1, // bit offset: 20 desc: Port x reset bit y (y = 0..15) - BR5: u1, // bit offset: 21 desc: Port x reset bit y (y = 0..15) - BR6: u1, // bit offset: 22 desc: Port x reset bit y (y = 0..15) - BR7: u1, // bit offset: 23 desc: Port x reset bit y (y = 0..15) - BR8: u1, // bit offset: 24 desc: Port x reset bit y (y = 0..15) - BR9: u1, // bit offset: 25 desc: Port x reset bit y (y = 0..15) - BR10: u1, // bit offset: 26 desc: Port x reset bit y (y = 0..15) - BR11: u1, // bit offset: 27 desc: Port x reset bit y (y = 0..15) - BR12: u1, // bit offset: 28 desc: Port x reset bit y (y = 0..15) - BR13: u1, // bit offset: 29 desc: Port x reset bit y (y = 0..15) - BR14: u1, // bit offset: 30 desc: Port x reset bit y (y = 0..15) - BR15: u1, // bit offset: 31 desc: Port x reset bit y (y = 0..15) - }); - // byte offset: 28 GPIO port configuration lock register + /// Port x set bit y (y= 0..15) + BS0: u1 = 0, + /// Port x set bit y (y= 0..15) + BS1: u1 = 0, + /// Port x set bit y (y= 0..15) + BS2: u1 = 0, + /// Port x set bit y (y= 0..15) + BS3: u1 = 0, + /// Port x set bit y (y= 0..15) + BS4: u1 = 0, + /// Port x set bit y (y= 0..15) + BS5: u1 = 0, + /// Port x set bit y (y= 0..15) + BS6: u1 = 0, + /// Port x set bit y (y= 0..15) + BS7: u1 = 0, + /// Port x set bit y (y= 0..15) + BS8: u1 = 0, + /// Port x set bit y (y= 0..15) + BS9: u1 = 0, + /// Port x set bit y (y= 0..15) + BS10: u1 = 0, + /// Port x set bit y (y= 0..15) + BS11: u1 = 0, + /// Port x set bit y (y= 0..15) + BS12: u1 = 0, + /// Port x set bit y (y= 0..15) + BS13: u1 = 0, + /// Port x set bit y (y= 0..15) + BS14: u1 = 0, + /// Port x set bit y (y= 0..15) + BS15: u1 = 0, + /// Port x set bit y (y= 0..15) + BR0: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR1: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR2: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR3: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR4: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR5: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR6: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR7: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR8: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR9: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR10: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR11: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR12: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR13: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR14: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR15: u1 = 0, + }); + + /// GPIO port configuration lock register pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port x lock bit y (y= 0..15) - LCK1: u1, // bit offset: 1 desc: Port x lock bit y (y= 0..15) - LCK2: u1, // bit offset: 2 desc: Port x lock bit y (y= 0..15) - LCK3: u1, // bit offset: 3 desc: Port x lock bit y (y= 0..15) - LCK4: u1, // bit offset: 4 desc: Port x lock bit y (y= 0..15) - LCK5: u1, // bit offset: 5 desc: Port x lock bit y (y= 0..15) - LCK6: u1, // bit offset: 6 desc: Port x lock bit y (y= 0..15) - LCK7: u1, // bit offset: 7 desc: Port x lock bit y (y= 0..15) - LCK8: u1, // bit offset: 8 desc: Port x lock bit y (y= 0..15) - LCK9: u1, // bit offset: 9 desc: Port x lock bit y (y= 0..15) - LCK10: u1, // bit offset: 10 desc: Port x lock bit y (y= 0..15) - LCK11: u1, // bit offset: 11 desc: Port x lock bit y (y= 0..15) - LCK12: u1, // bit offset: 12 desc: Port x lock bit y (y= 0..15) - LCK13: u1, // bit offset: 13 desc: Port x lock bit y (y= 0..15) - LCK14: u1, // bit offset: 14 desc: Port x lock bit y (y= 0..15) - LCK15: u1, // bit offset: 15 desc: Port x lock bit y (y= 0..15) - LCKK: u1, // bit offset: 16 desc: Lok Key + /// Port x lock bit y (y= 0..15) + LCK0: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK1: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK2: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK3: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK4: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK5: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK6: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK7: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK8: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK9: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK10: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK11: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK12: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK13: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK14: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK15: u1 = 0, + /// Lok Key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -529,46 +876,81 @@ pub const GPIOB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 GPIO alternate function low register + + /// GPIO alternate function low register pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - AFRL0: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 0..7) - }); - // byte offset: 36 GPIO alternate function high register + /// Alternate function selection for port x bit y (y = 0..7) + AFRL0: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4 = 0, + }); + + /// GPIO alternate function high register pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - AFRH8: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 8..15) - }); - // byte offset: 40 Port bit reset register + /// Alternate function selection for port x bit y (y = 8..15) + AFRH8: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4 = 0, + }); + + /// Port bit reset register pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Port x Reset bit y - BR1: u1, // bit offset: 1 desc: Port x Reset bit y - BR2: u1, // bit offset: 2 desc: Port x Reset bit y - BR3: u1, // bit offset: 3 desc: Port x Reset bit y - BR4: u1, // bit offset: 4 desc: Port x Reset bit y - BR5: u1, // bit offset: 5 desc: Port x Reset bit y - BR6: u1, // bit offset: 6 desc: Port x Reset bit y - BR7: u1, // bit offset: 7 desc: Port x Reset bit y - BR8: u1, // bit offset: 8 desc: Port x Reset bit y - BR9: u1, // bit offset: 9 desc: Port x Reset bit y - BR10: u1, // bit offset: 10 desc: Port x Reset bit y - BR11: u1, // bit offset: 11 desc: Port x Reset bit y - BR12: u1, // bit offset: 12 desc: Port x Reset bit y - BR13: u1, // bit offset: 13 desc: Port x Reset bit y - BR14: u1, // bit offset: 14 desc: Port x Reset bit y - BR15: u1, // bit offset: 15 desc: Port x Reset bit y + /// Port x Reset bit y + BR0: u1 = 0, + /// Port x Reset bit y + BR1: u1 = 0, + /// Port x Reset bit y + BR2: u1 = 0, + /// Port x Reset bit y + BR3: u1 = 0, + /// Port x Reset bit y + BR4: u1 = 0, + /// Port x Reset bit y + BR5: u1 = 0, + /// Port x Reset bit y + BR6: u1 = 0, + /// Port x Reset bit y + BR7: u1 = 0, + /// Port x Reset bit y + BR8: u1 = 0, + /// Port x Reset bit y + BR9: u1 = 0, + /// Port x Reset bit y + BR10: u1 = 0, + /// Port x Reset bit y + BR11: u1 = 0, + /// Port x Reset bit y + BR12: u1 = 0, + /// Port x Reset bit y + BR13: u1 = 0, + /// Port x Reset bit y + BR14: u1 = 0, + /// Port x Reset bit y + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -587,45 +969,81 @@ pub const GPIOB = extern struct { padding1: u1 = 0, }); }; + +/// General-purpose I/Os pub const GPIOC = extern struct { pub const Address: u32 = 0x48000800; - // byte offset: 0 GPIO port mode register + + /// GPIO port mode register pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - MODER0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - MODER1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - MODER2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - MODER3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - MODER4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - MODER5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - MODER6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - MODER7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - MODER8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - MODER9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - MODER10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - MODER11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - MODER12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - MODER13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - MODER14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - MODER15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 4 GPIO port output type register + /// Port x configuration bits (y = 0..15) + MODER0: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER1: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER2: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER3: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER4: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER5: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER6: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER7: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER8: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER9: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER10: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER11: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER12: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER13: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER14: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER15: u2 = 0, + }); + + /// GPIO port output type register pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - OT0: u1, // bit offset: 0 desc: Port x configuration bit 0 - OT1: u1, // bit offset: 1 desc: Port x configuration bit 1 - OT2: u1, // bit offset: 2 desc: Port x configuration bit 2 - OT3: u1, // bit offset: 3 desc: Port x configuration bit 3 - OT4: u1, // bit offset: 4 desc: Port x configuration bit 4 - OT5: u1, // bit offset: 5 desc: Port x configuration bit 5 - OT6: u1, // bit offset: 6 desc: Port x configuration bit 6 - OT7: u1, // bit offset: 7 desc: Port x configuration bit 7 - OT8: u1, // bit offset: 8 desc: Port x configuration bit 8 - OT9: u1, // bit offset: 9 desc: Port x configuration bit 9 - OT10: u1, // bit offset: 10 desc: Port x configuration bit 10 - OT11: u1, // bit offset: 11 desc: Port x configuration bit 11 - OT12: u1, // bit offset: 12 desc: Port x configuration bit 12 - OT13: u1, // bit offset: 13 desc: Port x configuration bit 13 - OT14: u1, // bit offset: 14 desc: Port x configuration bit 14 - OT15: u1, // bit offset: 15 desc: Port x configuration bit 15 + /// Port x configuration bit 0 + OT0: u1 = 0, + /// Port x configuration bit 1 + OT1: u1 = 0, + /// Port x configuration bit 2 + OT2: u1 = 0, + /// Port x configuration bit 3 + OT3: u1 = 0, + /// Port x configuration bit 4 + OT4: u1 = 0, + /// Port x configuration bit 5 + OT5: u1 = 0, + /// Port x configuration bit 6 + OT6: u1 = 0, + /// Port x configuration bit 7 + OT7: u1 = 0, + /// Port x configuration bit 8 + OT8: u1 = 0, + /// Port x configuration bit 9 + OT9: u1 = 0, + /// Port x configuration bit 10 + OT10: u1 = 0, + /// Port x configuration bit 11 + OT11: u1 = 0, + /// Port x configuration bit 12 + OT12: u1 = 0, + /// Port x configuration bit 13 + OT13: u1 = 0, + /// Port x configuration bit 14 + OT14: u1 = 0, + /// Port x configuration bit 15 + OT15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -643,62 +1061,113 @@ pub const GPIOC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 GPIO port output speed register + + /// GPIO port output speed register pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - OSPEEDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - OSPEEDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - OSPEEDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - OSPEEDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - OSPEEDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - OSPEEDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - OSPEEDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - OSPEEDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - OSPEEDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - OSPEEDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - OSPEEDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - OSPEEDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - OSPEEDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - OSPEEDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - OSPEEDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - OSPEEDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 12 GPIO port pull-up/pull-down register + /// Port x configuration bits (y = 0..15) + OSPEEDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR15: u2 = 0, + }); + + /// GPIO port pull-up/pull-down register pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - PUPDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - PUPDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - PUPDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - PUPDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - PUPDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - PUPDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - PUPDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - PUPDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - PUPDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - PUPDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - PUPDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - PUPDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - PUPDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - PUPDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - PUPDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - PUPDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 16 GPIO port input data register + /// Port x configuration bits (y = 0..15) + PUPDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR15: u2 = 0, + }); + + /// GPIO port input data register pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data (y = 0..15) - IDR1: u1, // bit offset: 1 desc: Port input data (y = 0..15) - IDR2: u1, // bit offset: 2 desc: Port input data (y = 0..15) - IDR3: u1, // bit offset: 3 desc: Port input data (y = 0..15) - IDR4: u1, // bit offset: 4 desc: Port input data (y = 0..15) - IDR5: u1, // bit offset: 5 desc: Port input data (y = 0..15) - IDR6: u1, // bit offset: 6 desc: Port input data (y = 0..15) - IDR7: u1, // bit offset: 7 desc: Port input data (y = 0..15) - IDR8: u1, // bit offset: 8 desc: Port input data (y = 0..15) - IDR9: u1, // bit offset: 9 desc: Port input data (y = 0..15) - IDR10: u1, // bit offset: 10 desc: Port input data (y = 0..15) - IDR11: u1, // bit offset: 11 desc: Port input data (y = 0..15) - IDR12: u1, // bit offset: 12 desc: Port input data (y = 0..15) - IDR13: u1, // bit offset: 13 desc: Port input data (y = 0..15) - IDR14: u1, // bit offset: 14 desc: Port input data (y = 0..15) - IDR15: u1, // bit offset: 15 desc: Port input data (y = 0..15) + /// Port input data (y = 0..15) + IDR0: u1 = 0, + /// Port input data (y = 0..15) + IDR1: u1 = 0, + /// Port input data (y = 0..15) + IDR2: u1 = 0, + /// Port input data (y = 0..15) + IDR3: u1 = 0, + /// Port input data (y = 0..15) + IDR4: u1 = 0, + /// Port input data (y = 0..15) + IDR5: u1 = 0, + /// Port input data (y = 0..15) + IDR6: u1 = 0, + /// Port input data (y = 0..15) + IDR7: u1 = 0, + /// Port input data (y = 0..15) + IDR8: u1 = 0, + /// Port input data (y = 0..15) + IDR9: u1 = 0, + /// Port input data (y = 0..15) + IDR10: u1 = 0, + /// Port input data (y = 0..15) + IDR11: u1 = 0, + /// Port input data (y = 0..15) + IDR12: u1 = 0, + /// Port input data (y = 0..15) + IDR13: u1 = 0, + /// Port input data (y = 0..15) + IDR14: u1 = 0, + /// Port input data (y = 0..15) + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -716,24 +1185,41 @@ pub const GPIOC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 GPIO port output data register + + /// GPIO port output data register pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data (y = 0..15) - ODR1: u1, // bit offset: 1 desc: Port output data (y = 0..15) - ODR2: u1, // bit offset: 2 desc: Port output data (y = 0..15) - ODR3: u1, // bit offset: 3 desc: Port output data (y = 0..15) - ODR4: u1, // bit offset: 4 desc: Port output data (y = 0..15) - ODR5: u1, // bit offset: 5 desc: Port output data (y = 0..15) - ODR6: u1, // bit offset: 6 desc: Port output data (y = 0..15) - ODR7: u1, // bit offset: 7 desc: Port output data (y = 0..15) - ODR8: u1, // bit offset: 8 desc: Port output data (y = 0..15) - ODR9: u1, // bit offset: 9 desc: Port output data (y = 0..15) - ODR10: u1, // bit offset: 10 desc: Port output data (y = 0..15) - ODR11: u1, // bit offset: 11 desc: Port output data (y = 0..15) - ODR12: u1, // bit offset: 12 desc: Port output data (y = 0..15) - ODR13: u1, // bit offset: 13 desc: Port output data (y = 0..15) - ODR14: u1, // bit offset: 14 desc: Port output data (y = 0..15) - ODR15: u1, // bit offset: 15 desc: Port output data (y = 0..15) + /// Port output data (y = 0..15) + ODR0: u1 = 0, + /// Port output data (y = 0..15) + ODR1: u1 = 0, + /// Port output data (y = 0..15) + ODR2: u1 = 0, + /// Port output data (y = 0..15) + ODR3: u1 = 0, + /// Port output data (y = 0..15) + ODR4: u1 = 0, + /// Port output data (y = 0..15) + ODR5: u1 = 0, + /// Port output data (y = 0..15) + ODR6: u1 = 0, + /// Port output data (y = 0..15) + ODR7: u1 = 0, + /// Port output data (y = 0..15) + ODR8: u1 = 0, + /// Port output data (y = 0..15) + ODR9: u1 = 0, + /// Port output data (y = 0..15) + ODR10: u1 = 0, + /// Port output data (y = 0..15) + ODR11: u1 = 0, + /// Port output data (y = 0..15) + ODR12: u1 = 0, + /// Port output data (y = 0..15) + ODR13: u1 = 0, + /// Port output data (y = 0..15) + ODR14: u1 = 0, + /// Port output data (y = 0..15) + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -751,60 +1237,111 @@ pub const GPIOC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 GPIO port bit set/reset register + + /// GPIO port bit set/reset register pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Port x set bit y (y= 0..15) - BS1: u1, // bit offset: 1 desc: Port x set bit y (y= 0..15) - BS2: u1, // bit offset: 2 desc: Port x set bit y (y= 0..15) - BS3: u1, // bit offset: 3 desc: Port x set bit y (y= 0..15) - BS4: u1, // bit offset: 4 desc: Port x set bit y (y= 0..15) - BS5: u1, // bit offset: 5 desc: Port x set bit y (y= 0..15) - BS6: u1, // bit offset: 6 desc: Port x set bit y (y= 0..15) - BS7: u1, // bit offset: 7 desc: Port x set bit y (y= 0..15) - BS8: u1, // bit offset: 8 desc: Port x set bit y (y= 0..15) - BS9: u1, // bit offset: 9 desc: Port x set bit y (y= 0..15) - BS10: u1, // bit offset: 10 desc: Port x set bit y (y= 0..15) - BS11: u1, // bit offset: 11 desc: Port x set bit y (y= 0..15) - BS12: u1, // bit offset: 12 desc: Port x set bit y (y= 0..15) - BS13: u1, // bit offset: 13 desc: Port x set bit y (y= 0..15) - BS14: u1, // bit offset: 14 desc: Port x set bit y (y= 0..15) - BS15: u1, // bit offset: 15 desc: Port x set bit y (y= 0..15) - BR0: u1, // bit offset: 16 desc: Port x set bit y (y= 0..15) - BR1: u1, // bit offset: 17 desc: Port x reset bit y (y = 0..15) - BR2: u1, // bit offset: 18 desc: Port x reset bit y (y = 0..15) - BR3: u1, // bit offset: 19 desc: Port x reset bit y (y = 0..15) - BR4: u1, // bit offset: 20 desc: Port x reset bit y (y = 0..15) - BR5: u1, // bit offset: 21 desc: Port x reset bit y (y = 0..15) - BR6: u1, // bit offset: 22 desc: Port x reset bit y (y = 0..15) - BR7: u1, // bit offset: 23 desc: Port x reset bit y (y = 0..15) - BR8: u1, // bit offset: 24 desc: Port x reset bit y (y = 0..15) - BR9: u1, // bit offset: 25 desc: Port x reset bit y (y = 0..15) - BR10: u1, // bit offset: 26 desc: Port x reset bit y (y = 0..15) - BR11: u1, // bit offset: 27 desc: Port x reset bit y (y = 0..15) - BR12: u1, // bit offset: 28 desc: Port x reset bit y (y = 0..15) - BR13: u1, // bit offset: 29 desc: Port x reset bit y (y = 0..15) - BR14: u1, // bit offset: 30 desc: Port x reset bit y (y = 0..15) - BR15: u1, // bit offset: 31 desc: Port x reset bit y (y = 0..15) - }); - // byte offset: 28 GPIO port configuration lock register + /// Port x set bit y (y= 0..15) + BS0: u1 = 0, + /// Port x set bit y (y= 0..15) + BS1: u1 = 0, + /// Port x set bit y (y= 0..15) + BS2: u1 = 0, + /// Port x set bit y (y= 0..15) + BS3: u1 = 0, + /// Port x set bit y (y= 0..15) + BS4: u1 = 0, + /// Port x set bit y (y= 0..15) + BS5: u1 = 0, + /// Port x set bit y (y= 0..15) + BS6: u1 = 0, + /// Port x set bit y (y= 0..15) + BS7: u1 = 0, + /// Port x set bit y (y= 0..15) + BS8: u1 = 0, + /// Port x set bit y (y= 0..15) + BS9: u1 = 0, + /// Port x set bit y (y= 0..15) + BS10: u1 = 0, + /// Port x set bit y (y= 0..15) + BS11: u1 = 0, + /// Port x set bit y (y= 0..15) + BS12: u1 = 0, + /// Port x set bit y (y= 0..15) + BS13: u1 = 0, + /// Port x set bit y (y= 0..15) + BS14: u1 = 0, + /// Port x set bit y (y= 0..15) + BS15: u1 = 0, + /// Port x set bit y (y= 0..15) + BR0: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR1: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR2: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR3: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR4: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR5: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR6: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR7: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR8: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR9: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR10: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR11: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR12: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR13: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR14: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR15: u1 = 0, + }); + + /// GPIO port configuration lock register pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port x lock bit y (y= 0..15) - LCK1: u1, // bit offset: 1 desc: Port x lock bit y (y= 0..15) - LCK2: u1, // bit offset: 2 desc: Port x lock bit y (y= 0..15) - LCK3: u1, // bit offset: 3 desc: Port x lock bit y (y= 0..15) - LCK4: u1, // bit offset: 4 desc: Port x lock bit y (y= 0..15) - LCK5: u1, // bit offset: 5 desc: Port x lock bit y (y= 0..15) - LCK6: u1, // bit offset: 6 desc: Port x lock bit y (y= 0..15) - LCK7: u1, // bit offset: 7 desc: Port x lock bit y (y= 0..15) - LCK8: u1, // bit offset: 8 desc: Port x lock bit y (y= 0..15) - LCK9: u1, // bit offset: 9 desc: Port x lock bit y (y= 0..15) - LCK10: u1, // bit offset: 10 desc: Port x lock bit y (y= 0..15) - LCK11: u1, // bit offset: 11 desc: Port x lock bit y (y= 0..15) - LCK12: u1, // bit offset: 12 desc: Port x lock bit y (y= 0..15) - LCK13: u1, // bit offset: 13 desc: Port x lock bit y (y= 0..15) - LCK14: u1, // bit offset: 14 desc: Port x lock bit y (y= 0..15) - LCK15: u1, // bit offset: 15 desc: Port x lock bit y (y= 0..15) - LCKK: u1, // bit offset: 16 desc: Lok Key + /// Port x lock bit y (y= 0..15) + LCK0: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK1: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK2: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK3: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK4: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK5: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK6: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK7: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK8: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK9: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK10: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK11: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK12: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK13: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK14: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK15: u1 = 0, + /// Lok Key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -821,46 +1358,81 @@ pub const GPIOC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 GPIO alternate function low register + + /// GPIO alternate function low register pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - AFRL0: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 0..7) - }); - // byte offset: 36 GPIO alternate function high register + /// Alternate function selection for port x bit y (y = 0..7) + AFRL0: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4 = 0, + }); + + /// GPIO alternate function high register pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - AFRH8: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 8..15) - }); - // byte offset: 40 Port bit reset register + /// Alternate function selection for port x bit y (y = 8..15) + AFRH8: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4 = 0, + }); + + /// Port bit reset register pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Port x Reset bit y - BR1: u1, // bit offset: 1 desc: Port x Reset bit y - BR2: u1, // bit offset: 2 desc: Port x Reset bit y - BR3: u1, // bit offset: 3 desc: Port x Reset bit y - BR4: u1, // bit offset: 4 desc: Port x Reset bit y - BR5: u1, // bit offset: 5 desc: Port x Reset bit y - BR6: u1, // bit offset: 6 desc: Port x Reset bit y - BR7: u1, // bit offset: 7 desc: Port x Reset bit y - BR8: u1, // bit offset: 8 desc: Port x Reset bit y - BR9: u1, // bit offset: 9 desc: Port x Reset bit y - BR10: u1, // bit offset: 10 desc: Port x Reset bit y - BR11: u1, // bit offset: 11 desc: Port x Reset bit y - BR12: u1, // bit offset: 12 desc: Port x Reset bit y - BR13: u1, // bit offset: 13 desc: Port x Reset bit y - BR14: u1, // bit offset: 14 desc: Port x Reset bit y - BR15: u1, // bit offset: 15 desc: Port x Reset bit y + /// Port x Reset bit y + BR0: u1 = 0, + /// Port x Reset bit y + BR1: u1 = 0, + /// Port x Reset bit y + BR2: u1 = 0, + /// Port x Reset bit y + BR3: u1 = 0, + /// Port x Reset bit y + BR4: u1 = 0, + /// Port x Reset bit y + BR5: u1 = 0, + /// Port x Reset bit y + BR6: u1 = 0, + /// Port x Reset bit y + BR7: u1 = 0, + /// Port x Reset bit y + BR8: u1 = 0, + /// Port x Reset bit y + BR9: u1 = 0, + /// Port x Reset bit y + BR10: u1 = 0, + /// Port x Reset bit y + BR11: u1 = 0, + /// Port x Reset bit y + BR12: u1 = 0, + /// Port x Reset bit y + BR13: u1 = 0, + /// Port x Reset bit y + BR14: u1 = 0, + /// Port x Reset bit y + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -879,45 +1451,81 @@ pub const GPIOC = extern struct { padding1: u1 = 0, }); }; + +/// General-purpose I/Os pub const GPIOD = extern struct { pub const Address: u32 = 0x48000c00; - // byte offset: 0 GPIO port mode register + + /// GPIO port mode register pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - MODER0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - MODER1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - MODER2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - MODER3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - MODER4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - MODER5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - MODER6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - MODER7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - MODER8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - MODER9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - MODER10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - MODER11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - MODER12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - MODER13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - MODER14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - MODER15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 4 GPIO port output type register + /// Port x configuration bits (y = 0..15) + MODER0: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER1: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER2: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER3: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER4: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER5: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER6: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER7: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER8: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER9: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER10: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER11: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER12: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER13: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER14: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER15: u2 = 0, + }); + + /// GPIO port output type register pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - OT0: u1, // bit offset: 0 desc: Port x configuration bit 0 - OT1: u1, // bit offset: 1 desc: Port x configuration bit 1 - OT2: u1, // bit offset: 2 desc: Port x configuration bit 2 - OT3: u1, // bit offset: 3 desc: Port x configuration bit 3 - OT4: u1, // bit offset: 4 desc: Port x configuration bit 4 - OT5: u1, // bit offset: 5 desc: Port x configuration bit 5 - OT6: u1, // bit offset: 6 desc: Port x configuration bit 6 - OT7: u1, // bit offset: 7 desc: Port x configuration bit 7 - OT8: u1, // bit offset: 8 desc: Port x configuration bit 8 - OT9: u1, // bit offset: 9 desc: Port x configuration bit 9 - OT10: u1, // bit offset: 10 desc: Port x configuration bit 10 - OT11: u1, // bit offset: 11 desc: Port x configuration bit 11 - OT12: u1, // bit offset: 12 desc: Port x configuration bit 12 - OT13: u1, // bit offset: 13 desc: Port x configuration bit 13 - OT14: u1, // bit offset: 14 desc: Port x configuration bit 14 - OT15: u1, // bit offset: 15 desc: Port x configuration bit 15 + /// Port x configuration bit 0 + OT0: u1 = 0, + /// Port x configuration bit 1 + OT1: u1 = 0, + /// Port x configuration bit 2 + OT2: u1 = 0, + /// Port x configuration bit 3 + OT3: u1 = 0, + /// Port x configuration bit 4 + OT4: u1 = 0, + /// Port x configuration bit 5 + OT5: u1 = 0, + /// Port x configuration bit 6 + OT6: u1 = 0, + /// Port x configuration bit 7 + OT7: u1 = 0, + /// Port x configuration bit 8 + OT8: u1 = 0, + /// Port x configuration bit 9 + OT9: u1 = 0, + /// Port x configuration bit 10 + OT10: u1 = 0, + /// Port x configuration bit 11 + OT11: u1 = 0, + /// Port x configuration bit 12 + OT12: u1 = 0, + /// Port x configuration bit 13 + OT13: u1 = 0, + /// Port x configuration bit 14 + OT14: u1 = 0, + /// Port x configuration bit 15 + OT15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -935,62 +1543,113 @@ pub const GPIOD = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 GPIO port output speed register + + /// GPIO port output speed register pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - OSPEEDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - OSPEEDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - OSPEEDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - OSPEEDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - OSPEEDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - OSPEEDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - OSPEEDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - OSPEEDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - OSPEEDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - OSPEEDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - OSPEEDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - OSPEEDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - OSPEEDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - OSPEEDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - OSPEEDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - OSPEEDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 12 GPIO port pull-up/pull-down register + /// Port x configuration bits (y = 0..15) + OSPEEDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR15: u2 = 0, + }); + + /// GPIO port pull-up/pull-down register pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - PUPDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - PUPDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - PUPDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - PUPDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - PUPDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - PUPDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - PUPDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - PUPDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - PUPDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - PUPDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - PUPDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - PUPDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - PUPDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - PUPDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - PUPDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - PUPDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 16 GPIO port input data register + /// Port x configuration bits (y = 0..15) + PUPDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR15: u2 = 0, + }); + + /// GPIO port input data register pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data (y = 0..15) - IDR1: u1, // bit offset: 1 desc: Port input data (y = 0..15) - IDR2: u1, // bit offset: 2 desc: Port input data (y = 0..15) - IDR3: u1, // bit offset: 3 desc: Port input data (y = 0..15) - IDR4: u1, // bit offset: 4 desc: Port input data (y = 0..15) - IDR5: u1, // bit offset: 5 desc: Port input data (y = 0..15) - IDR6: u1, // bit offset: 6 desc: Port input data (y = 0..15) - IDR7: u1, // bit offset: 7 desc: Port input data (y = 0..15) - IDR8: u1, // bit offset: 8 desc: Port input data (y = 0..15) - IDR9: u1, // bit offset: 9 desc: Port input data (y = 0..15) - IDR10: u1, // bit offset: 10 desc: Port input data (y = 0..15) - IDR11: u1, // bit offset: 11 desc: Port input data (y = 0..15) - IDR12: u1, // bit offset: 12 desc: Port input data (y = 0..15) - IDR13: u1, // bit offset: 13 desc: Port input data (y = 0..15) - IDR14: u1, // bit offset: 14 desc: Port input data (y = 0..15) - IDR15: u1, // bit offset: 15 desc: Port input data (y = 0..15) + /// Port input data (y = 0..15) + IDR0: u1 = 0, + /// Port input data (y = 0..15) + IDR1: u1 = 0, + /// Port input data (y = 0..15) + IDR2: u1 = 0, + /// Port input data (y = 0..15) + IDR3: u1 = 0, + /// Port input data (y = 0..15) + IDR4: u1 = 0, + /// Port input data (y = 0..15) + IDR5: u1 = 0, + /// Port input data (y = 0..15) + IDR6: u1 = 0, + /// Port input data (y = 0..15) + IDR7: u1 = 0, + /// Port input data (y = 0..15) + IDR8: u1 = 0, + /// Port input data (y = 0..15) + IDR9: u1 = 0, + /// Port input data (y = 0..15) + IDR10: u1 = 0, + /// Port input data (y = 0..15) + IDR11: u1 = 0, + /// Port input data (y = 0..15) + IDR12: u1 = 0, + /// Port input data (y = 0..15) + IDR13: u1 = 0, + /// Port input data (y = 0..15) + IDR14: u1 = 0, + /// Port input data (y = 0..15) + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1008,24 +1667,41 @@ pub const GPIOD = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 GPIO port output data register + + /// GPIO port output data register pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data (y = 0..15) - ODR1: u1, // bit offset: 1 desc: Port output data (y = 0..15) - ODR2: u1, // bit offset: 2 desc: Port output data (y = 0..15) - ODR3: u1, // bit offset: 3 desc: Port output data (y = 0..15) - ODR4: u1, // bit offset: 4 desc: Port output data (y = 0..15) - ODR5: u1, // bit offset: 5 desc: Port output data (y = 0..15) - ODR6: u1, // bit offset: 6 desc: Port output data (y = 0..15) - ODR7: u1, // bit offset: 7 desc: Port output data (y = 0..15) - ODR8: u1, // bit offset: 8 desc: Port output data (y = 0..15) - ODR9: u1, // bit offset: 9 desc: Port output data (y = 0..15) - ODR10: u1, // bit offset: 10 desc: Port output data (y = 0..15) - ODR11: u1, // bit offset: 11 desc: Port output data (y = 0..15) - ODR12: u1, // bit offset: 12 desc: Port output data (y = 0..15) - ODR13: u1, // bit offset: 13 desc: Port output data (y = 0..15) - ODR14: u1, // bit offset: 14 desc: Port output data (y = 0..15) - ODR15: u1, // bit offset: 15 desc: Port output data (y = 0..15) + /// Port output data (y = 0..15) + ODR0: u1 = 0, + /// Port output data (y = 0..15) + ODR1: u1 = 0, + /// Port output data (y = 0..15) + ODR2: u1 = 0, + /// Port output data (y = 0..15) + ODR3: u1 = 0, + /// Port output data (y = 0..15) + ODR4: u1 = 0, + /// Port output data (y = 0..15) + ODR5: u1 = 0, + /// Port output data (y = 0..15) + ODR6: u1 = 0, + /// Port output data (y = 0..15) + ODR7: u1 = 0, + /// Port output data (y = 0..15) + ODR8: u1 = 0, + /// Port output data (y = 0..15) + ODR9: u1 = 0, + /// Port output data (y = 0..15) + ODR10: u1 = 0, + /// Port output data (y = 0..15) + ODR11: u1 = 0, + /// Port output data (y = 0..15) + ODR12: u1 = 0, + /// Port output data (y = 0..15) + ODR13: u1 = 0, + /// Port output data (y = 0..15) + ODR14: u1 = 0, + /// Port output data (y = 0..15) + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1043,60 +1719,111 @@ pub const GPIOD = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 GPIO port bit set/reset register + + /// GPIO port bit set/reset register pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Port x set bit y (y= 0..15) - BS1: u1, // bit offset: 1 desc: Port x set bit y (y= 0..15) - BS2: u1, // bit offset: 2 desc: Port x set bit y (y= 0..15) - BS3: u1, // bit offset: 3 desc: Port x set bit y (y= 0..15) - BS4: u1, // bit offset: 4 desc: Port x set bit y (y= 0..15) - BS5: u1, // bit offset: 5 desc: Port x set bit y (y= 0..15) - BS6: u1, // bit offset: 6 desc: Port x set bit y (y= 0..15) - BS7: u1, // bit offset: 7 desc: Port x set bit y (y= 0..15) - BS8: u1, // bit offset: 8 desc: Port x set bit y (y= 0..15) - BS9: u1, // bit offset: 9 desc: Port x set bit y (y= 0..15) - BS10: u1, // bit offset: 10 desc: Port x set bit y (y= 0..15) - BS11: u1, // bit offset: 11 desc: Port x set bit y (y= 0..15) - BS12: u1, // bit offset: 12 desc: Port x set bit y (y= 0..15) - BS13: u1, // bit offset: 13 desc: Port x set bit y (y= 0..15) - BS14: u1, // bit offset: 14 desc: Port x set bit y (y= 0..15) - BS15: u1, // bit offset: 15 desc: Port x set bit y (y= 0..15) - BR0: u1, // bit offset: 16 desc: Port x set bit y (y= 0..15) - BR1: u1, // bit offset: 17 desc: Port x reset bit y (y = 0..15) - BR2: u1, // bit offset: 18 desc: Port x reset bit y (y = 0..15) - BR3: u1, // bit offset: 19 desc: Port x reset bit y (y = 0..15) - BR4: u1, // bit offset: 20 desc: Port x reset bit y (y = 0..15) - BR5: u1, // bit offset: 21 desc: Port x reset bit y (y = 0..15) - BR6: u1, // bit offset: 22 desc: Port x reset bit y (y = 0..15) - BR7: u1, // bit offset: 23 desc: Port x reset bit y (y = 0..15) - BR8: u1, // bit offset: 24 desc: Port x reset bit y (y = 0..15) - BR9: u1, // bit offset: 25 desc: Port x reset bit y (y = 0..15) - BR10: u1, // bit offset: 26 desc: Port x reset bit y (y = 0..15) - BR11: u1, // bit offset: 27 desc: Port x reset bit y (y = 0..15) - BR12: u1, // bit offset: 28 desc: Port x reset bit y (y = 0..15) - BR13: u1, // bit offset: 29 desc: Port x reset bit y (y = 0..15) - BR14: u1, // bit offset: 30 desc: Port x reset bit y (y = 0..15) - BR15: u1, // bit offset: 31 desc: Port x reset bit y (y = 0..15) - }); - // byte offset: 28 GPIO port configuration lock register + /// Port x set bit y (y= 0..15) + BS0: u1 = 0, + /// Port x set bit y (y= 0..15) + BS1: u1 = 0, + /// Port x set bit y (y= 0..15) + BS2: u1 = 0, + /// Port x set bit y (y= 0..15) + BS3: u1 = 0, + /// Port x set bit y (y= 0..15) + BS4: u1 = 0, + /// Port x set bit y (y= 0..15) + BS5: u1 = 0, + /// Port x set bit y (y= 0..15) + BS6: u1 = 0, + /// Port x set bit y (y= 0..15) + BS7: u1 = 0, + /// Port x set bit y (y= 0..15) + BS8: u1 = 0, + /// Port x set bit y (y= 0..15) + BS9: u1 = 0, + /// Port x set bit y (y= 0..15) + BS10: u1 = 0, + /// Port x set bit y (y= 0..15) + BS11: u1 = 0, + /// Port x set bit y (y= 0..15) + BS12: u1 = 0, + /// Port x set bit y (y= 0..15) + BS13: u1 = 0, + /// Port x set bit y (y= 0..15) + BS14: u1 = 0, + /// Port x set bit y (y= 0..15) + BS15: u1 = 0, + /// Port x set bit y (y= 0..15) + BR0: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR1: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR2: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR3: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR4: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR5: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR6: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR7: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR8: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR9: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR10: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR11: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR12: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR13: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR14: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR15: u1 = 0, + }); + + /// GPIO port configuration lock register pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port x lock bit y (y= 0..15) - LCK1: u1, // bit offset: 1 desc: Port x lock bit y (y= 0..15) - LCK2: u1, // bit offset: 2 desc: Port x lock bit y (y= 0..15) - LCK3: u1, // bit offset: 3 desc: Port x lock bit y (y= 0..15) - LCK4: u1, // bit offset: 4 desc: Port x lock bit y (y= 0..15) - LCK5: u1, // bit offset: 5 desc: Port x lock bit y (y= 0..15) - LCK6: u1, // bit offset: 6 desc: Port x lock bit y (y= 0..15) - LCK7: u1, // bit offset: 7 desc: Port x lock bit y (y= 0..15) - LCK8: u1, // bit offset: 8 desc: Port x lock bit y (y= 0..15) - LCK9: u1, // bit offset: 9 desc: Port x lock bit y (y= 0..15) - LCK10: u1, // bit offset: 10 desc: Port x lock bit y (y= 0..15) - LCK11: u1, // bit offset: 11 desc: Port x lock bit y (y= 0..15) - LCK12: u1, // bit offset: 12 desc: Port x lock bit y (y= 0..15) - LCK13: u1, // bit offset: 13 desc: Port x lock bit y (y= 0..15) - LCK14: u1, // bit offset: 14 desc: Port x lock bit y (y= 0..15) - LCK15: u1, // bit offset: 15 desc: Port x lock bit y (y= 0..15) - LCKK: u1, // bit offset: 16 desc: Lok Key + /// Port x lock bit y (y= 0..15) + LCK0: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK1: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK2: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK3: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK4: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK5: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK6: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK7: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK8: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK9: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK10: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK11: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK12: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK13: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK14: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK15: u1 = 0, + /// Lok Key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -1113,46 +1840,81 @@ pub const GPIOD = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 GPIO alternate function low register + + /// GPIO alternate function low register pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - AFRL0: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 0..7) - }); - // byte offset: 36 GPIO alternate function high register + /// Alternate function selection for port x bit y (y = 0..7) + AFRL0: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4 = 0, + }); + + /// GPIO alternate function high register pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - AFRH8: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 8..15) - }); - // byte offset: 40 Port bit reset register + /// Alternate function selection for port x bit y (y = 8..15) + AFRH8: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4 = 0, + }); + + /// Port bit reset register pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Port x Reset bit y - BR1: u1, // bit offset: 1 desc: Port x Reset bit y - BR2: u1, // bit offset: 2 desc: Port x Reset bit y - BR3: u1, // bit offset: 3 desc: Port x Reset bit y - BR4: u1, // bit offset: 4 desc: Port x Reset bit y - BR5: u1, // bit offset: 5 desc: Port x Reset bit y - BR6: u1, // bit offset: 6 desc: Port x Reset bit y - BR7: u1, // bit offset: 7 desc: Port x Reset bit y - BR8: u1, // bit offset: 8 desc: Port x Reset bit y - BR9: u1, // bit offset: 9 desc: Port x Reset bit y - BR10: u1, // bit offset: 10 desc: Port x Reset bit y - BR11: u1, // bit offset: 11 desc: Port x Reset bit y - BR12: u1, // bit offset: 12 desc: Port x Reset bit y - BR13: u1, // bit offset: 13 desc: Port x Reset bit y - BR14: u1, // bit offset: 14 desc: Port x Reset bit y - BR15: u1, // bit offset: 15 desc: Port x Reset bit y + /// Port x Reset bit y + BR0: u1 = 0, + /// Port x Reset bit y + BR1: u1 = 0, + /// Port x Reset bit y + BR2: u1 = 0, + /// Port x Reset bit y + BR3: u1 = 0, + /// Port x Reset bit y + BR4: u1 = 0, + /// Port x Reset bit y + BR5: u1 = 0, + /// Port x Reset bit y + BR6: u1 = 0, + /// Port x Reset bit y + BR7: u1 = 0, + /// Port x Reset bit y + BR8: u1 = 0, + /// Port x Reset bit y + BR9: u1 = 0, + /// Port x Reset bit y + BR10: u1 = 0, + /// Port x Reset bit y + BR11: u1 = 0, + /// Port x Reset bit y + BR12: u1 = 0, + /// Port x Reset bit y + BR13: u1 = 0, + /// Port x Reset bit y + BR14: u1 = 0, + /// Port x Reset bit y + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1171,45 +1933,81 @@ pub const GPIOD = extern struct { padding1: u1 = 0, }); }; + +/// General-purpose I/Os pub const GPIOE = extern struct { pub const Address: u32 = 0x48001000; - // byte offset: 0 GPIO port mode register + + /// GPIO port mode register pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - MODER0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - MODER1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - MODER2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - MODER3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - MODER4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - MODER5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - MODER6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - MODER7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - MODER8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - MODER9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - MODER10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - MODER11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - MODER12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - MODER13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - MODER14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - MODER15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 4 GPIO port output type register + /// Port x configuration bits (y = 0..15) + MODER0: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER1: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER2: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER3: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER4: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER5: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER6: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER7: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER8: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER9: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER10: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER11: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER12: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER13: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER14: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER15: u2 = 0, + }); + + /// GPIO port output type register pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - OT0: u1, // bit offset: 0 desc: Port x configuration bit 0 - OT1: u1, // bit offset: 1 desc: Port x configuration bit 1 - OT2: u1, // bit offset: 2 desc: Port x configuration bit 2 - OT3: u1, // bit offset: 3 desc: Port x configuration bit 3 - OT4: u1, // bit offset: 4 desc: Port x configuration bit 4 - OT5: u1, // bit offset: 5 desc: Port x configuration bit 5 - OT6: u1, // bit offset: 6 desc: Port x configuration bit 6 - OT7: u1, // bit offset: 7 desc: Port x configuration bit 7 - OT8: u1, // bit offset: 8 desc: Port x configuration bit 8 - OT9: u1, // bit offset: 9 desc: Port x configuration bit 9 - OT10: u1, // bit offset: 10 desc: Port x configuration bit 10 - OT11: u1, // bit offset: 11 desc: Port x configuration bit 11 - OT12: u1, // bit offset: 12 desc: Port x configuration bit 12 - OT13: u1, // bit offset: 13 desc: Port x configuration bit 13 - OT14: u1, // bit offset: 14 desc: Port x configuration bit 14 - OT15: u1, // bit offset: 15 desc: Port x configuration bit 15 + /// Port x configuration bit 0 + OT0: u1 = 0, + /// Port x configuration bit 1 + OT1: u1 = 0, + /// Port x configuration bit 2 + OT2: u1 = 0, + /// Port x configuration bit 3 + OT3: u1 = 0, + /// Port x configuration bit 4 + OT4: u1 = 0, + /// Port x configuration bit 5 + OT5: u1 = 0, + /// Port x configuration bit 6 + OT6: u1 = 0, + /// Port x configuration bit 7 + OT7: u1 = 0, + /// Port x configuration bit 8 + OT8: u1 = 0, + /// Port x configuration bit 9 + OT9: u1 = 0, + /// Port x configuration bit 10 + OT10: u1 = 0, + /// Port x configuration bit 11 + OT11: u1 = 0, + /// Port x configuration bit 12 + OT12: u1 = 0, + /// Port x configuration bit 13 + OT13: u1 = 0, + /// Port x configuration bit 14 + OT14: u1 = 0, + /// Port x configuration bit 15 + OT15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1227,62 +2025,113 @@ pub const GPIOE = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 GPIO port output speed register + + /// GPIO port output speed register pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - OSPEEDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - OSPEEDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - OSPEEDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - OSPEEDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - OSPEEDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - OSPEEDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - OSPEEDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - OSPEEDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - OSPEEDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - OSPEEDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - OSPEEDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - OSPEEDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - OSPEEDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - OSPEEDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - OSPEEDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - OSPEEDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 12 GPIO port pull-up/pull-down register + /// Port x configuration bits (y = 0..15) + OSPEEDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR15: u2 = 0, + }); + + /// GPIO port pull-up/pull-down register pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - PUPDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - PUPDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - PUPDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - PUPDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - PUPDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - PUPDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - PUPDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - PUPDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - PUPDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - PUPDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - PUPDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - PUPDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - PUPDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - PUPDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - PUPDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - PUPDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 16 GPIO port input data register + /// Port x configuration bits (y = 0..15) + PUPDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR15: u2 = 0, + }); + + /// GPIO port input data register pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data (y = 0..15) - IDR1: u1, // bit offset: 1 desc: Port input data (y = 0..15) - IDR2: u1, // bit offset: 2 desc: Port input data (y = 0..15) - IDR3: u1, // bit offset: 3 desc: Port input data (y = 0..15) - IDR4: u1, // bit offset: 4 desc: Port input data (y = 0..15) - IDR5: u1, // bit offset: 5 desc: Port input data (y = 0..15) - IDR6: u1, // bit offset: 6 desc: Port input data (y = 0..15) - IDR7: u1, // bit offset: 7 desc: Port input data (y = 0..15) - IDR8: u1, // bit offset: 8 desc: Port input data (y = 0..15) - IDR9: u1, // bit offset: 9 desc: Port input data (y = 0..15) - IDR10: u1, // bit offset: 10 desc: Port input data (y = 0..15) - IDR11: u1, // bit offset: 11 desc: Port input data (y = 0..15) - IDR12: u1, // bit offset: 12 desc: Port input data (y = 0..15) - IDR13: u1, // bit offset: 13 desc: Port input data (y = 0..15) - IDR14: u1, // bit offset: 14 desc: Port input data (y = 0..15) - IDR15: u1, // bit offset: 15 desc: Port input data (y = 0..15) + /// Port input data (y = 0..15) + IDR0: u1 = 0, + /// Port input data (y = 0..15) + IDR1: u1 = 0, + /// Port input data (y = 0..15) + IDR2: u1 = 0, + /// Port input data (y = 0..15) + IDR3: u1 = 0, + /// Port input data (y = 0..15) + IDR4: u1 = 0, + /// Port input data (y = 0..15) + IDR5: u1 = 0, + /// Port input data (y = 0..15) + IDR6: u1 = 0, + /// Port input data (y = 0..15) + IDR7: u1 = 0, + /// Port input data (y = 0..15) + IDR8: u1 = 0, + /// Port input data (y = 0..15) + IDR9: u1 = 0, + /// Port input data (y = 0..15) + IDR10: u1 = 0, + /// Port input data (y = 0..15) + IDR11: u1 = 0, + /// Port input data (y = 0..15) + IDR12: u1 = 0, + /// Port input data (y = 0..15) + IDR13: u1 = 0, + /// Port input data (y = 0..15) + IDR14: u1 = 0, + /// Port input data (y = 0..15) + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1300,24 +2149,41 @@ pub const GPIOE = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 GPIO port output data register + + /// GPIO port output data register pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data (y = 0..15) - ODR1: u1, // bit offset: 1 desc: Port output data (y = 0..15) - ODR2: u1, // bit offset: 2 desc: Port output data (y = 0..15) - ODR3: u1, // bit offset: 3 desc: Port output data (y = 0..15) - ODR4: u1, // bit offset: 4 desc: Port output data (y = 0..15) - ODR5: u1, // bit offset: 5 desc: Port output data (y = 0..15) - ODR6: u1, // bit offset: 6 desc: Port output data (y = 0..15) - ODR7: u1, // bit offset: 7 desc: Port output data (y = 0..15) - ODR8: u1, // bit offset: 8 desc: Port output data (y = 0..15) - ODR9: u1, // bit offset: 9 desc: Port output data (y = 0..15) - ODR10: u1, // bit offset: 10 desc: Port output data (y = 0..15) - ODR11: u1, // bit offset: 11 desc: Port output data (y = 0..15) - ODR12: u1, // bit offset: 12 desc: Port output data (y = 0..15) - ODR13: u1, // bit offset: 13 desc: Port output data (y = 0..15) - ODR14: u1, // bit offset: 14 desc: Port output data (y = 0..15) - ODR15: u1, // bit offset: 15 desc: Port output data (y = 0..15) + /// Port output data (y = 0..15) + ODR0: u1 = 0, + /// Port output data (y = 0..15) + ODR1: u1 = 0, + /// Port output data (y = 0..15) + ODR2: u1 = 0, + /// Port output data (y = 0..15) + ODR3: u1 = 0, + /// Port output data (y = 0..15) + ODR4: u1 = 0, + /// Port output data (y = 0..15) + ODR5: u1 = 0, + /// Port output data (y = 0..15) + ODR6: u1 = 0, + /// Port output data (y = 0..15) + ODR7: u1 = 0, + /// Port output data (y = 0..15) + ODR8: u1 = 0, + /// Port output data (y = 0..15) + ODR9: u1 = 0, + /// Port output data (y = 0..15) + ODR10: u1 = 0, + /// Port output data (y = 0..15) + ODR11: u1 = 0, + /// Port output data (y = 0..15) + ODR12: u1 = 0, + /// Port output data (y = 0..15) + ODR13: u1 = 0, + /// Port output data (y = 0..15) + ODR14: u1 = 0, + /// Port output data (y = 0..15) + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1335,60 +2201,111 @@ pub const GPIOE = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 GPIO port bit set/reset register + + /// GPIO port bit set/reset register pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Port x set bit y (y= 0..15) - BS1: u1, // bit offset: 1 desc: Port x set bit y (y= 0..15) - BS2: u1, // bit offset: 2 desc: Port x set bit y (y= 0..15) - BS3: u1, // bit offset: 3 desc: Port x set bit y (y= 0..15) - BS4: u1, // bit offset: 4 desc: Port x set bit y (y= 0..15) - BS5: u1, // bit offset: 5 desc: Port x set bit y (y= 0..15) - BS6: u1, // bit offset: 6 desc: Port x set bit y (y= 0..15) - BS7: u1, // bit offset: 7 desc: Port x set bit y (y= 0..15) - BS8: u1, // bit offset: 8 desc: Port x set bit y (y= 0..15) - BS9: u1, // bit offset: 9 desc: Port x set bit y (y= 0..15) - BS10: u1, // bit offset: 10 desc: Port x set bit y (y= 0..15) - BS11: u1, // bit offset: 11 desc: Port x set bit y (y= 0..15) - BS12: u1, // bit offset: 12 desc: Port x set bit y (y= 0..15) - BS13: u1, // bit offset: 13 desc: Port x set bit y (y= 0..15) - BS14: u1, // bit offset: 14 desc: Port x set bit y (y= 0..15) - BS15: u1, // bit offset: 15 desc: Port x set bit y (y= 0..15) - BR0: u1, // bit offset: 16 desc: Port x set bit y (y= 0..15) - BR1: u1, // bit offset: 17 desc: Port x reset bit y (y = 0..15) - BR2: u1, // bit offset: 18 desc: Port x reset bit y (y = 0..15) - BR3: u1, // bit offset: 19 desc: Port x reset bit y (y = 0..15) - BR4: u1, // bit offset: 20 desc: Port x reset bit y (y = 0..15) - BR5: u1, // bit offset: 21 desc: Port x reset bit y (y = 0..15) - BR6: u1, // bit offset: 22 desc: Port x reset bit y (y = 0..15) - BR7: u1, // bit offset: 23 desc: Port x reset bit y (y = 0..15) - BR8: u1, // bit offset: 24 desc: Port x reset bit y (y = 0..15) - BR9: u1, // bit offset: 25 desc: Port x reset bit y (y = 0..15) - BR10: u1, // bit offset: 26 desc: Port x reset bit y (y = 0..15) - BR11: u1, // bit offset: 27 desc: Port x reset bit y (y = 0..15) - BR12: u1, // bit offset: 28 desc: Port x reset bit y (y = 0..15) - BR13: u1, // bit offset: 29 desc: Port x reset bit y (y = 0..15) - BR14: u1, // bit offset: 30 desc: Port x reset bit y (y = 0..15) - BR15: u1, // bit offset: 31 desc: Port x reset bit y (y = 0..15) - }); - // byte offset: 28 GPIO port configuration lock register + /// Port x set bit y (y= 0..15) + BS0: u1 = 0, + /// Port x set bit y (y= 0..15) + BS1: u1 = 0, + /// Port x set bit y (y= 0..15) + BS2: u1 = 0, + /// Port x set bit y (y= 0..15) + BS3: u1 = 0, + /// Port x set bit y (y= 0..15) + BS4: u1 = 0, + /// Port x set bit y (y= 0..15) + BS5: u1 = 0, + /// Port x set bit y (y= 0..15) + BS6: u1 = 0, + /// Port x set bit y (y= 0..15) + BS7: u1 = 0, + /// Port x set bit y (y= 0..15) + BS8: u1 = 0, + /// Port x set bit y (y= 0..15) + BS9: u1 = 0, + /// Port x set bit y (y= 0..15) + BS10: u1 = 0, + /// Port x set bit y (y= 0..15) + BS11: u1 = 0, + /// Port x set bit y (y= 0..15) + BS12: u1 = 0, + /// Port x set bit y (y= 0..15) + BS13: u1 = 0, + /// Port x set bit y (y= 0..15) + BS14: u1 = 0, + /// Port x set bit y (y= 0..15) + BS15: u1 = 0, + /// Port x set bit y (y= 0..15) + BR0: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR1: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR2: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR3: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR4: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR5: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR6: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR7: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR8: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR9: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR10: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR11: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR12: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR13: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR14: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR15: u1 = 0, + }); + + /// GPIO port configuration lock register pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port x lock bit y (y= 0..15) - LCK1: u1, // bit offset: 1 desc: Port x lock bit y (y= 0..15) - LCK2: u1, // bit offset: 2 desc: Port x lock bit y (y= 0..15) - LCK3: u1, // bit offset: 3 desc: Port x lock bit y (y= 0..15) - LCK4: u1, // bit offset: 4 desc: Port x lock bit y (y= 0..15) - LCK5: u1, // bit offset: 5 desc: Port x lock bit y (y= 0..15) - LCK6: u1, // bit offset: 6 desc: Port x lock bit y (y= 0..15) - LCK7: u1, // bit offset: 7 desc: Port x lock bit y (y= 0..15) - LCK8: u1, // bit offset: 8 desc: Port x lock bit y (y= 0..15) - LCK9: u1, // bit offset: 9 desc: Port x lock bit y (y= 0..15) - LCK10: u1, // bit offset: 10 desc: Port x lock bit y (y= 0..15) - LCK11: u1, // bit offset: 11 desc: Port x lock bit y (y= 0..15) - LCK12: u1, // bit offset: 12 desc: Port x lock bit y (y= 0..15) - LCK13: u1, // bit offset: 13 desc: Port x lock bit y (y= 0..15) - LCK14: u1, // bit offset: 14 desc: Port x lock bit y (y= 0..15) - LCK15: u1, // bit offset: 15 desc: Port x lock bit y (y= 0..15) - LCKK: u1, // bit offset: 16 desc: Lok Key + /// Port x lock bit y (y= 0..15) + LCK0: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK1: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK2: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK3: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK4: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK5: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK6: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK7: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK8: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK9: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK10: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK11: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK12: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK13: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK14: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK15: u1 = 0, + /// Lok Key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -1405,46 +2322,81 @@ pub const GPIOE = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 GPIO alternate function low register + + /// GPIO alternate function low register pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - AFRL0: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 0..7) - }); - // byte offset: 36 GPIO alternate function high register + /// Alternate function selection for port x bit y (y = 0..7) + AFRL0: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4 = 0, + }); + + /// GPIO alternate function high register pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - AFRH8: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 8..15) - }); - // byte offset: 40 Port bit reset register + /// Alternate function selection for port x bit y (y = 8..15) + AFRH8: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4 = 0, + }); + + /// Port bit reset register pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Port x Reset bit y - BR1: u1, // bit offset: 1 desc: Port x Reset bit y - BR2: u1, // bit offset: 2 desc: Port x Reset bit y - BR3: u1, // bit offset: 3 desc: Port x Reset bit y - BR4: u1, // bit offset: 4 desc: Port x Reset bit y - BR5: u1, // bit offset: 5 desc: Port x Reset bit y - BR6: u1, // bit offset: 6 desc: Port x Reset bit y - BR7: u1, // bit offset: 7 desc: Port x Reset bit y - BR8: u1, // bit offset: 8 desc: Port x Reset bit y - BR9: u1, // bit offset: 9 desc: Port x Reset bit y - BR10: u1, // bit offset: 10 desc: Port x Reset bit y - BR11: u1, // bit offset: 11 desc: Port x Reset bit y - BR12: u1, // bit offset: 12 desc: Port x Reset bit y - BR13: u1, // bit offset: 13 desc: Port x Reset bit y - BR14: u1, // bit offset: 14 desc: Port x Reset bit y - BR15: u1, // bit offset: 15 desc: Port x Reset bit y + /// Port x Reset bit y + BR0: u1 = 0, + /// Port x Reset bit y + BR1: u1 = 0, + /// Port x Reset bit y + BR2: u1 = 0, + /// Port x Reset bit y + BR3: u1 = 0, + /// Port x Reset bit y + BR4: u1 = 0, + /// Port x Reset bit y + BR5: u1 = 0, + /// Port x Reset bit y + BR6: u1 = 0, + /// Port x Reset bit y + BR7: u1 = 0, + /// Port x Reset bit y + BR8: u1 = 0, + /// Port x Reset bit y + BR9: u1 = 0, + /// Port x Reset bit y + BR10: u1 = 0, + /// Port x Reset bit y + BR11: u1 = 0, + /// Port x Reset bit y + BR12: u1 = 0, + /// Port x Reset bit y + BR13: u1 = 0, + /// Port x Reset bit y + BR14: u1 = 0, + /// Port x Reset bit y + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1463,45 +2415,81 @@ pub const GPIOE = extern struct { padding1: u1 = 0, }); }; + +/// General-purpose I/Os pub const GPIOF = extern struct { pub const Address: u32 = 0x48001400; - // byte offset: 0 GPIO port mode register + + /// GPIO port mode register pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - MODER0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - MODER1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - MODER2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - MODER3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - MODER4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - MODER5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - MODER6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - MODER7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - MODER8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - MODER9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - MODER10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - MODER11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - MODER12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - MODER13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - MODER14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - MODER15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 4 GPIO port output type register + /// Port x configuration bits (y = 0..15) + MODER0: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER1: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER2: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER3: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER4: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER5: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER6: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER7: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER8: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER9: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER10: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER11: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER12: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER13: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER14: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER15: u2 = 0, + }); + + /// GPIO port output type register pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - OT0: u1, // bit offset: 0 desc: Port x configuration bit 0 - OT1: u1, // bit offset: 1 desc: Port x configuration bit 1 - OT2: u1, // bit offset: 2 desc: Port x configuration bit 2 - OT3: u1, // bit offset: 3 desc: Port x configuration bit 3 - OT4: u1, // bit offset: 4 desc: Port x configuration bit 4 - OT5: u1, // bit offset: 5 desc: Port x configuration bit 5 - OT6: u1, // bit offset: 6 desc: Port x configuration bit 6 - OT7: u1, // bit offset: 7 desc: Port x configuration bit 7 - OT8: u1, // bit offset: 8 desc: Port x configuration bit 8 - OT9: u1, // bit offset: 9 desc: Port x configuration bit 9 - OT10: u1, // bit offset: 10 desc: Port x configuration bit 10 - OT11: u1, // bit offset: 11 desc: Port x configuration bit 11 - OT12: u1, // bit offset: 12 desc: Port x configuration bit 12 - OT13: u1, // bit offset: 13 desc: Port x configuration bit 13 - OT14: u1, // bit offset: 14 desc: Port x configuration bit 14 - OT15: u1, // bit offset: 15 desc: Port x configuration bit 15 + /// Port x configuration bit 0 + OT0: u1 = 0, + /// Port x configuration bit 1 + OT1: u1 = 0, + /// Port x configuration bit 2 + OT2: u1 = 0, + /// Port x configuration bit 3 + OT3: u1 = 0, + /// Port x configuration bit 4 + OT4: u1 = 0, + /// Port x configuration bit 5 + OT5: u1 = 0, + /// Port x configuration bit 6 + OT6: u1 = 0, + /// Port x configuration bit 7 + OT7: u1 = 0, + /// Port x configuration bit 8 + OT8: u1 = 0, + /// Port x configuration bit 9 + OT9: u1 = 0, + /// Port x configuration bit 10 + OT10: u1 = 0, + /// Port x configuration bit 11 + OT11: u1 = 0, + /// Port x configuration bit 12 + OT12: u1 = 0, + /// Port x configuration bit 13 + OT13: u1 = 0, + /// Port x configuration bit 14 + OT14: u1 = 0, + /// Port x configuration bit 15 + OT15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1519,62 +2507,113 @@ pub const GPIOF = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 GPIO port output speed register + + /// GPIO port output speed register pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - OSPEEDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - OSPEEDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - OSPEEDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - OSPEEDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - OSPEEDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - OSPEEDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - OSPEEDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - OSPEEDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - OSPEEDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - OSPEEDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - OSPEEDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - OSPEEDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - OSPEEDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - OSPEEDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - OSPEEDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - OSPEEDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 12 GPIO port pull-up/pull-down register + /// Port x configuration bits (y = 0..15) + OSPEEDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR15: u2 = 0, + }); + + /// GPIO port pull-up/pull-down register pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - PUPDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - PUPDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - PUPDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - PUPDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - PUPDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - PUPDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - PUPDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - PUPDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - PUPDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - PUPDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - PUPDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - PUPDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - PUPDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - PUPDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - PUPDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - PUPDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 16 GPIO port input data register + /// Port x configuration bits (y = 0..15) + PUPDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR15: u2 = 0, + }); + + /// GPIO port input data register pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data (y = 0..15) - IDR1: u1, // bit offset: 1 desc: Port input data (y = 0..15) - IDR2: u1, // bit offset: 2 desc: Port input data (y = 0..15) - IDR3: u1, // bit offset: 3 desc: Port input data (y = 0..15) - IDR4: u1, // bit offset: 4 desc: Port input data (y = 0..15) - IDR5: u1, // bit offset: 5 desc: Port input data (y = 0..15) - IDR6: u1, // bit offset: 6 desc: Port input data (y = 0..15) - IDR7: u1, // bit offset: 7 desc: Port input data (y = 0..15) - IDR8: u1, // bit offset: 8 desc: Port input data (y = 0..15) - IDR9: u1, // bit offset: 9 desc: Port input data (y = 0..15) - IDR10: u1, // bit offset: 10 desc: Port input data (y = 0..15) - IDR11: u1, // bit offset: 11 desc: Port input data (y = 0..15) - IDR12: u1, // bit offset: 12 desc: Port input data (y = 0..15) - IDR13: u1, // bit offset: 13 desc: Port input data (y = 0..15) - IDR14: u1, // bit offset: 14 desc: Port input data (y = 0..15) - IDR15: u1, // bit offset: 15 desc: Port input data (y = 0..15) + /// Port input data (y = 0..15) + IDR0: u1 = 0, + /// Port input data (y = 0..15) + IDR1: u1 = 0, + /// Port input data (y = 0..15) + IDR2: u1 = 0, + /// Port input data (y = 0..15) + IDR3: u1 = 0, + /// Port input data (y = 0..15) + IDR4: u1 = 0, + /// Port input data (y = 0..15) + IDR5: u1 = 0, + /// Port input data (y = 0..15) + IDR6: u1 = 0, + /// Port input data (y = 0..15) + IDR7: u1 = 0, + /// Port input data (y = 0..15) + IDR8: u1 = 0, + /// Port input data (y = 0..15) + IDR9: u1 = 0, + /// Port input data (y = 0..15) + IDR10: u1 = 0, + /// Port input data (y = 0..15) + IDR11: u1 = 0, + /// Port input data (y = 0..15) + IDR12: u1 = 0, + /// Port input data (y = 0..15) + IDR13: u1 = 0, + /// Port input data (y = 0..15) + IDR14: u1 = 0, + /// Port input data (y = 0..15) + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1592,24 +2631,41 @@ pub const GPIOF = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 GPIO port output data register + + /// GPIO port output data register pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data (y = 0..15) - ODR1: u1, // bit offset: 1 desc: Port output data (y = 0..15) - ODR2: u1, // bit offset: 2 desc: Port output data (y = 0..15) - ODR3: u1, // bit offset: 3 desc: Port output data (y = 0..15) - ODR4: u1, // bit offset: 4 desc: Port output data (y = 0..15) - ODR5: u1, // bit offset: 5 desc: Port output data (y = 0..15) - ODR6: u1, // bit offset: 6 desc: Port output data (y = 0..15) - ODR7: u1, // bit offset: 7 desc: Port output data (y = 0..15) - ODR8: u1, // bit offset: 8 desc: Port output data (y = 0..15) - ODR9: u1, // bit offset: 9 desc: Port output data (y = 0..15) - ODR10: u1, // bit offset: 10 desc: Port output data (y = 0..15) - ODR11: u1, // bit offset: 11 desc: Port output data (y = 0..15) - ODR12: u1, // bit offset: 12 desc: Port output data (y = 0..15) - ODR13: u1, // bit offset: 13 desc: Port output data (y = 0..15) - ODR14: u1, // bit offset: 14 desc: Port output data (y = 0..15) - ODR15: u1, // bit offset: 15 desc: Port output data (y = 0..15) + /// Port output data (y = 0..15) + ODR0: u1 = 0, + /// Port output data (y = 0..15) + ODR1: u1 = 0, + /// Port output data (y = 0..15) + ODR2: u1 = 0, + /// Port output data (y = 0..15) + ODR3: u1 = 0, + /// Port output data (y = 0..15) + ODR4: u1 = 0, + /// Port output data (y = 0..15) + ODR5: u1 = 0, + /// Port output data (y = 0..15) + ODR6: u1 = 0, + /// Port output data (y = 0..15) + ODR7: u1 = 0, + /// Port output data (y = 0..15) + ODR8: u1 = 0, + /// Port output data (y = 0..15) + ODR9: u1 = 0, + /// Port output data (y = 0..15) + ODR10: u1 = 0, + /// Port output data (y = 0..15) + ODR11: u1 = 0, + /// Port output data (y = 0..15) + ODR12: u1 = 0, + /// Port output data (y = 0..15) + ODR13: u1 = 0, + /// Port output data (y = 0..15) + ODR14: u1 = 0, + /// Port output data (y = 0..15) + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1627,60 +2683,111 @@ pub const GPIOF = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 GPIO port bit set/reset register + + /// GPIO port bit set/reset register pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Port x set bit y (y= 0..15) - BS1: u1, // bit offset: 1 desc: Port x set bit y (y= 0..15) - BS2: u1, // bit offset: 2 desc: Port x set bit y (y= 0..15) - BS3: u1, // bit offset: 3 desc: Port x set bit y (y= 0..15) - BS4: u1, // bit offset: 4 desc: Port x set bit y (y= 0..15) - BS5: u1, // bit offset: 5 desc: Port x set bit y (y= 0..15) - BS6: u1, // bit offset: 6 desc: Port x set bit y (y= 0..15) - BS7: u1, // bit offset: 7 desc: Port x set bit y (y= 0..15) - BS8: u1, // bit offset: 8 desc: Port x set bit y (y= 0..15) - BS9: u1, // bit offset: 9 desc: Port x set bit y (y= 0..15) - BS10: u1, // bit offset: 10 desc: Port x set bit y (y= 0..15) - BS11: u1, // bit offset: 11 desc: Port x set bit y (y= 0..15) - BS12: u1, // bit offset: 12 desc: Port x set bit y (y= 0..15) - BS13: u1, // bit offset: 13 desc: Port x set bit y (y= 0..15) - BS14: u1, // bit offset: 14 desc: Port x set bit y (y= 0..15) - BS15: u1, // bit offset: 15 desc: Port x set bit y (y= 0..15) - BR0: u1, // bit offset: 16 desc: Port x set bit y (y= 0..15) - BR1: u1, // bit offset: 17 desc: Port x reset bit y (y = 0..15) - BR2: u1, // bit offset: 18 desc: Port x reset bit y (y = 0..15) - BR3: u1, // bit offset: 19 desc: Port x reset bit y (y = 0..15) - BR4: u1, // bit offset: 20 desc: Port x reset bit y (y = 0..15) - BR5: u1, // bit offset: 21 desc: Port x reset bit y (y = 0..15) - BR6: u1, // bit offset: 22 desc: Port x reset bit y (y = 0..15) - BR7: u1, // bit offset: 23 desc: Port x reset bit y (y = 0..15) - BR8: u1, // bit offset: 24 desc: Port x reset bit y (y = 0..15) - BR9: u1, // bit offset: 25 desc: Port x reset bit y (y = 0..15) - BR10: u1, // bit offset: 26 desc: Port x reset bit y (y = 0..15) - BR11: u1, // bit offset: 27 desc: Port x reset bit y (y = 0..15) - BR12: u1, // bit offset: 28 desc: Port x reset bit y (y = 0..15) - BR13: u1, // bit offset: 29 desc: Port x reset bit y (y = 0..15) - BR14: u1, // bit offset: 30 desc: Port x reset bit y (y = 0..15) - BR15: u1, // bit offset: 31 desc: Port x reset bit y (y = 0..15) - }); - // byte offset: 28 GPIO port configuration lock register + /// Port x set bit y (y= 0..15) + BS0: u1 = 0, + /// Port x set bit y (y= 0..15) + BS1: u1 = 0, + /// Port x set bit y (y= 0..15) + BS2: u1 = 0, + /// Port x set bit y (y= 0..15) + BS3: u1 = 0, + /// Port x set bit y (y= 0..15) + BS4: u1 = 0, + /// Port x set bit y (y= 0..15) + BS5: u1 = 0, + /// Port x set bit y (y= 0..15) + BS6: u1 = 0, + /// Port x set bit y (y= 0..15) + BS7: u1 = 0, + /// Port x set bit y (y= 0..15) + BS8: u1 = 0, + /// Port x set bit y (y= 0..15) + BS9: u1 = 0, + /// Port x set bit y (y= 0..15) + BS10: u1 = 0, + /// Port x set bit y (y= 0..15) + BS11: u1 = 0, + /// Port x set bit y (y= 0..15) + BS12: u1 = 0, + /// Port x set bit y (y= 0..15) + BS13: u1 = 0, + /// Port x set bit y (y= 0..15) + BS14: u1 = 0, + /// Port x set bit y (y= 0..15) + BS15: u1 = 0, + /// Port x set bit y (y= 0..15) + BR0: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR1: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR2: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR3: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR4: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR5: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR6: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR7: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR8: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR9: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR10: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR11: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR12: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR13: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR14: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR15: u1 = 0, + }); + + /// GPIO port configuration lock register pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port x lock bit y (y= 0..15) - LCK1: u1, // bit offset: 1 desc: Port x lock bit y (y= 0..15) - LCK2: u1, // bit offset: 2 desc: Port x lock bit y (y= 0..15) - LCK3: u1, // bit offset: 3 desc: Port x lock bit y (y= 0..15) - LCK4: u1, // bit offset: 4 desc: Port x lock bit y (y= 0..15) - LCK5: u1, // bit offset: 5 desc: Port x lock bit y (y= 0..15) - LCK6: u1, // bit offset: 6 desc: Port x lock bit y (y= 0..15) - LCK7: u1, // bit offset: 7 desc: Port x lock bit y (y= 0..15) - LCK8: u1, // bit offset: 8 desc: Port x lock bit y (y= 0..15) - LCK9: u1, // bit offset: 9 desc: Port x lock bit y (y= 0..15) - LCK10: u1, // bit offset: 10 desc: Port x lock bit y (y= 0..15) - LCK11: u1, // bit offset: 11 desc: Port x lock bit y (y= 0..15) - LCK12: u1, // bit offset: 12 desc: Port x lock bit y (y= 0..15) - LCK13: u1, // bit offset: 13 desc: Port x lock bit y (y= 0..15) - LCK14: u1, // bit offset: 14 desc: Port x lock bit y (y= 0..15) - LCK15: u1, // bit offset: 15 desc: Port x lock bit y (y= 0..15) - LCKK: u1, // bit offset: 16 desc: Lok Key + /// Port x lock bit y (y= 0..15) + LCK0: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK1: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK2: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK3: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK4: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK5: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK6: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK7: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK8: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK9: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK10: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK11: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK12: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK13: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK14: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK15: u1 = 0, + /// Lok Key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -1697,46 +2804,81 @@ pub const GPIOF = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 GPIO alternate function low register + + /// GPIO alternate function low register pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - AFRL0: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 0..7) - }); - // byte offset: 36 GPIO alternate function high register + /// Alternate function selection for port x bit y (y = 0..7) + AFRL0: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4 = 0, + }); + + /// GPIO alternate function high register pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - AFRH8: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 8..15) - }); - // byte offset: 40 Port bit reset register + /// Alternate function selection for port x bit y (y = 8..15) + AFRH8: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4 = 0, + }); + + /// Port bit reset register pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Port x Reset bit y - BR1: u1, // bit offset: 1 desc: Port x Reset bit y - BR2: u1, // bit offset: 2 desc: Port x Reset bit y - BR3: u1, // bit offset: 3 desc: Port x Reset bit y - BR4: u1, // bit offset: 4 desc: Port x Reset bit y - BR5: u1, // bit offset: 5 desc: Port x Reset bit y - BR6: u1, // bit offset: 6 desc: Port x Reset bit y - BR7: u1, // bit offset: 7 desc: Port x Reset bit y - BR8: u1, // bit offset: 8 desc: Port x Reset bit y - BR9: u1, // bit offset: 9 desc: Port x Reset bit y - BR10: u1, // bit offset: 10 desc: Port x Reset bit y - BR11: u1, // bit offset: 11 desc: Port x Reset bit y - BR12: u1, // bit offset: 12 desc: Port x Reset bit y - BR13: u1, // bit offset: 13 desc: Port x Reset bit y - BR14: u1, // bit offset: 14 desc: Port x Reset bit y - BR15: u1, // bit offset: 15 desc: Port x Reset bit y + /// Port x Reset bit y + BR0: u1 = 0, + /// Port x Reset bit y + BR1: u1 = 0, + /// Port x Reset bit y + BR2: u1 = 0, + /// Port x Reset bit y + BR3: u1 = 0, + /// Port x Reset bit y + BR4: u1 = 0, + /// Port x Reset bit y + BR5: u1 = 0, + /// Port x Reset bit y + BR6: u1 = 0, + /// Port x Reset bit y + BR7: u1 = 0, + /// Port x Reset bit y + BR8: u1 = 0, + /// Port x Reset bit y + BR9: u1 = 0, + /// Port x Reset bit y + BR10: u1 = 0, + /// Port x Reset bit y + BR11: u1 = 0, + /// Port x Reset bit y + BR12: u1 = 0, + /// Port x Reset bit y + BR13: u1 = 0, + /// Port x Reset bit y + BR14: u1 = 0, + /// Port x Reset bit y + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1755,45 +2897,81 @@ pub const GPIOF = extern struct { padding1: u1 = 0, }); }; + +/// General-purpose I/Os pub const GPIOG = extern struct { pub const Address: u32 = 0x48001800; - // byte offset: 0 GPIO port mode register + + /// GPIO port mode register pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - MODER0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - MODER1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - MODER2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - MODER3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - MODER4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - MODER5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - MODER6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - MODER7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - MODER8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - MODER9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - MODER10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - MODER11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - MODER12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - MODER13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - MODER14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - MODER15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 4 GPIO port output type register + /// Port x configuration bits (y = 0..15) + MODER0: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER1: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER2: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER3: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER4: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER5: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER6: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER7: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER8: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER9: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER10: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER11: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER12: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER13: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER14: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER15: u2 = 0, + }); + + /// GPIO port output type register pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - OT0: u1, // bit offset: 0 desc: Port x configuration bit 0 - OT1: u1, // bit offset: 1 desc: Port x configuration bit 1 - OT2: u1, // bit offset: 2 desc: Port x configuration bit 2 - OT3: u1, // bit offset: 3 desc: Port x configuration bit 3 - OT4: u1, // bit offset: 4 desc: Port x configuration bit 4 - OT5: u1, // bit offset: 5 desc: Port x configuration bit 5 - OT6: u1, // bit offset: 6 desc: Port x configuration bit 6 - OT7: u1, // bit offset: 7 desc: Port x configuration bit 7 - OT8: u1, // bit offset: 8 desc: Port x configuration bit 8 - OT9: u1, // bit offset: 9 desc: Port x configuration bit 9 - OT10: u1, // bit offset: 10 desc: Port x configuration bit 10 - OT11: u1, // bit offset: 11 desc: Port x configuration bit 11 - OT12: u1, // bit offset: 12 desc: Port x configuration bit 12 - OT13: u1, // bit offset: 13 desc: Port x configuration bit 13 - OT14: u1, // bit offset: 14 desc: Port x configuration bit 14 - OT15: u1, // bit offset: 15 desc: Port x configuration bit 15 + /// Port x configuration bit 0 + OT0: u1 = 0, + /// Port x configuration bit 1 + OT1: u1 = 0, + /// Port x configuration bit 2 + OT2: u1 = 0, + /// Port x configuration bit 3 + OT3: u1 = 0, + /// Port x configuration bit 4 + OT4: u1 = 0, + /// Port x configuration bit 5 + OT5: u1 = 0, + /// Port x configuration bit 6 + OT6: u1 = 0, + /// Port x configuration bit 7 + OT7: u1 = 0, + /// Port x configuration bit 8 + OT8: u1 = 0, + /// Port x configuration bit 9 + OT9: u1 = 0, + /// Port x configuration bit 10 + OT10: u1 = 0, + /// Port x configuration bit 11 + OT11: u1 = 0, + /// Port x configuration bit 12 + OT12: u1 = 0, + /// Port x configuration bit 13 + OT13: u1 = 0, + /// Port x configuration bit 14 + OT14: u1 = 0, + /// Port x configuration bit 15 + OT15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1811,62 +2989,113 @@ pub const GPIOG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 GPIO port output speed register + + /// GPIO port output speed register pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - OSPEEDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - OSPEEDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - OSPEEDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - OSPEEDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - OSPEEDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - OSPEEDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - OSPEEDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - OSPEEDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - OSPEEDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - OSPEEDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - OSPEEDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - OSPEEDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - OSPEEDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - OSPEEDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - OSPEEDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - OSPEEDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 12 GPIO port pull-up/pull-down register + /// Port x configuration bits (y = 0..15) + OSPEEDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR15: u2 = 0, + }); + + /// GPIO port pull-up/pull-down register pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - PUPDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - PUPDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - PUPDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - PUPDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - PUPDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - PUPDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - PUPDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - PUPDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - PUPDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - PUPDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - PUPDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - PUPDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - PUPDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - PUPDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - PUPDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - PUPDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 16 GPIO port input data register + /// Port x configuration bits (y = 0..15) + PUPDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR15: u2 = 0, + }); + + /// GPIO port input data register pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data (y = 0..15) - IDR1: u1, // bit offset: 1 desc: Port input data (y = 0..15) - IDR2: u1, // bit offset: 2 desc: Port input data (y = 0..15) - IDR3: u1, // bit offset: 3 desc: Port input data (y = 0..15) - IDR4: u1, // bit offset: 4 desc: Port input data (y = 0..15) - IDR5: u1, // bit offset: 5 desc: Port input data (y = 0..15) - IDR6: u1, // bit offset: 6 desc: Port input data (y = 0..15) - IDR7: u1, // bit offset: 7 desc: Port input data (y = 0..15) - IDR8: u1, // bit offset: 8 desc: Port input data (y = 0..15) - IDR9: u1, // bit offset: 9 desc: Port input data (y = 0..15) - IDR10: u1, // bit offset: 10 desc: Port input data (y = 0..15) - IDR11: u1, // bit offset: 11 desc: Port input data (y = 0..15) - IDR12: u1, // bit offset: 12 desc: Port input data (y = 0..15) - IDR13: u1, // bit offset: 13 desc: Port input data (y = 0..15) - IDR14: u1, // bit offset: 14 desc: Port input data (y = 0..15) - IDR15: u1, // bit offset: 15 desc: Port input data (y = 0..15) + /// Port input data (y = 0..15) + IDR0: u1 = 0, + /// Port input data (y = 0..15) + IDR1: u1 = 0, + /// Port input data (y = 0..15) + IDR2: u1 = 0, + /// Port input data (y = 0..15) + IDR3: u1 = 0, + /// Port input data (y = 0..15) + IDR4: u1 = 0, + /// Port input data (y = 0..15) + IDR5: u1 = 0, + /// Port input data (y = 0..15) + IDR6: u1 = 0, + /// Port input data (y = 0..15) + IDR7: u1 = 0, + /// Port input data (y = 0..15) + IDR8: u1 = 0, + /// Port input data (y = 0..15) + IDR9: u1 = 0, + /// Port input data (y = 0..15) + IDR10: u1 = 0, + /// Port input data (y = 0..15) + IDR11: u1 = 0, + /// Port input data (y = 0..15) + IDR12: u1 = 0, + /// Port input data (y = 0..15) + IDR13: u1 = 0, + /// Port input data (y = 0..15) + IDR14: u1 = 0, + /// Port input data (y = 0..15) + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1884,24 +3113,41 @@ pub const GPIOG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 GPIO port output data register + + /// GPIO port output data register pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data (y = 0..15) - ODR1: u1, // bit offset: 1 desc: Port output data (y = 0..15) - ODR2: u1, // bit offset: 2 desc: Port output data (y = 0..15) - ODR3: u1, // bit offset: 3 desc: Port output data (y = 0..15) - ODR4: u1, // bit offset: 4 desc: Port output data (y = 0..15) - ODR5: u1, // bit offset: 5 desc: Port output data (y = 0..15) - ODR6: u1, // bit offset: 6 desc: Port output data (y = 0..15) - ODR7: u1, // bit offset: 7 desc: Port output data (y = 0..15) - ODR8: u1, // bit offset: 8 desc: Port output data (y = 0..15) - ODR9: u1, // bit offset: 9 desc: Port output data (y = 0..15) - ODR10: u1, // bit offset: 10 desc: Port output data (y = 0..15) - ODR11: u1, // bit offset: 11 desc: Port output data (y = 0..15) - ODR12: u1, // bit offset: 12 desc: Port output data (y = 0..15) - ODR13: u1, // bit offset: 13 desc: Port output data (y = 0..15) - ODR14: u1, // bit offset: 14 desc: Port output data (y = 0..15) - ODR15: u1, // bit offset: 15 desc: Port output data (y = 0..15) + /// Port output data (y = 0..15) + ODR0: u1 = 0, + /// Port output data (y = 0..15) + ODR1: u1 = 0, + /// Port output data (y = 0..15) + ODR2: u1 = 0, + /// Port output data (y = 0..15) + ODR3: u1 = 0, + /// Port output data (y = 0..15) + ODR4: u1 = 0, + /// Port output data (y = 0..15) + ODR5: u1 = 0, + /// Port output data (y = 0..15) + ODR6: u1 = 0, + /// Port output data (y = 0..15) + ODR7: u1 = 0, + /// Port output data (y = 0..15) + ODR8: u1 = 0, + /// Port output data (y = 0..15) + ODR9: u1 = 0, + /// Port output data (y = 0..15) + ODR10: u1 = 0, + /// Port output data (y = 0..15) + ODR11: u1 = 0, + /// Port output data (y = 0..15) + ODR12: u1 = 0, + /// Port output data (y = 0..15) + ODR13: u1 = 0, + /// Port output data (y = 0..15) + ODR14: u1 = 0, + /// Port output data (y = 0..15) + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1919,60 +3165,111 @@ pub const GPIOG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 GPIO port bit set/reset register + + /// GPIO port bit set/reset register pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Port x set bit y (y= 0..15) - BS1: u1, // bit offset: 1 desc: Port x set bit y (y= 0..15) - BS2: u1, // bit offset: 2 desc: Port x set bit y (y= 0..15) - BS3: u1, // bit offset: 3 desc: Port x set bit y (y= 0..15) - BS4: u1, // bit offset: 4 desc: Port x set bit y (y= 0..15) - BS5: u1, // bit offset: 5 desc: Port x set bit y (y= 0..15) - BS6: u1, // bit offset: 6 desc: Port x set bit y (y= 0..15) - BS7: u1, // bit offset: 7 desc: Port x set bit y (y= 0..15) - BS8: u1, // bit offset: 8 desc: Port x set bit y (y= 0..15) - BS9: u1, // bit offset: 9 desc: Port x set bit y (y= 0..15) - BS10: u1, // bit offset: 10 desc: Port x set bit y (y= 0..15) - BS11: u1, // bit offset: 11 desc: Port x set bit y (y= 0..15) - BS12: u1, // bit offset: 12 desc: Port x set bit y (y= 0..15) - BS13: u1, // bit offset: 13 desc: Port x set bit y (y= 0..15) - BS14: u1, // bit offset: 14 desc: Port x set bit y (y= 0..15) - BS15: u1, // bit offset: 15 desc: Port x set bit y (y= 0..15) - BR0: u1, // bit offset: 16 desc: Port x set bit y (y= 0..15) - BR1: u1, // bit offset: 17 desc: Port x reset bit y (y = 0..15) - BR2: u1, // bit offset: 18 desc: Port x reset bit y (y = 0..15) - BR3: u1, // bit offset: 19 desc: Port x reset bit y (y = 0..15) - BR4: u1, // bit offset: 20 desc: Port x reset bit y (y = 0..15) - BR5: u1, // bit offset: 21 desc: Port x reset bit y (y = 0..15) - BR6: u1, // bit offset: 22 desc: Port x reset bit y (y = 0..15) - BR7: u1, // bit offset: 23 desc: Port x reset bit y (y = 0..15) - BR8: u1, // bit offset: 24 desc: Port x reset bit y (y = 0..15) - BR9: u1, // bit offset: 25 desc: Port x reset bit y (y = 0..15) - BR10: u1, // bit offset: 26 desc: Port x reset bit y (y = 0..15) - BR11: u1, // bit offset: 27 desc: Port x reset bit y (y = 0..15) - BR12: u1, // bit offset: 28 desc: Port x reset bit y (y = 0..15) - BR13: u1, // bit offset: 29 desc: Port x reset bit y (y = 0..15) - BR14: u1, // bit offset: 30 desc: Port x reset bit y (y = 0..15) - BR15: u1, // bit offset: 31 desc: Port x reset bit y (y = 0..15) - }); - // byte offset: 28 GPIO port configuration lock register + /// Port x set bit y (y= 0..15) + BS0: u1 = 0, + /// Port x set bit y (y= 0..15) + BS1: u1 = 0, + /// Port x set bit y (y= 0..15) + BS2: u1 = 0, + /// Port x set bit y (y= 0..15) + BS3: u1 = 0, + /// Port x set bit y (y= 0..15) + BS4: u1 = 0, + /// Port x set bit y (y= 0..15) + BS5: u1 = 0, + /// Port x set bit y (y= 0..15) + BS6: u1 = 0, + /// Port x set bit y (y= 0..15) + BS7: u1 = 0, + /// Port x set bit y (y= 0..15) + BS8: u1 = 0, + /// Port x set bit y (y= 0..15) + BS9: u1 = 0, + /// Port x set bit y (y= 0..15) + BS10: u1 = 0, + /// Port x set bit y (y= 0..15) + BS11: u1 = 0, + /// Port x set bit y (y= 0..15) + BS12: u1 = 0, + /// Port x set bit y (y= 0..15) + BS13: u1 = 0, + /// Port x set bit y (y= 0..15) + BS14: u1 = 0, + /// Port x set bit y (y= 0..15) + BS15: u1 = 0, + /// Port x set bit y (y= 0..15) + BR0: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR1: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR2: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR3: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR4: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR5: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR6: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR7: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR8: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR9: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR10: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR11: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR12: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR13: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR14: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR15: u1 = 0, + }); + + /// GPIO port configuration lock register pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port x lock bit y (y= 0..15) - LCK1: u1, // bit offset: 1 desc: Port x lock bit y (y= 0..15) - LCK2: u1, // bit offset: 2 desc: Port x lock bit y (y= 0..15) - LCK3: u1, // bit offset: 3 desc: Port x lock bit y (y= 0..15) - LCK4: u1, // bit offset: 4 desc: Port x lock bit y (y= 0..15) - LCK5: u1, // bit offset: 5 desc: Port x lock bit y (y= 0..15) - LCK6: u1, // bit offset: 6 desc: Port x lock bit y (y= 0..15) - LCK7: u1, // bit offset: 7 desc: Port x lock bit y (y= 0..15) - LCK8: u1, // bit offset: 8 desc: Port x lock bit y (y= 0..15) - LCK9: u1, // bit offset: 9 desc: Port x lock bit y (y= 0..15) - LCK10: u1, // bit offset: 10 desc: Port x lock bit y (y= 0..15) - LCK11: u1, // bit offset: 11 desc: Port x lock bit y (y= 0..15) - LCK12: u1, // bit offset: 12 desc: Port x lock bit y (y= 0..15) - LCK13: u1, // bit offset: 13 desc: Port x lock bit y (y= 0..15) - LCK14: u1, // bit offset: 14 desc: Port x lock bit y (y= 0..15) - LCK15: u1, // bit offset: 15 desc: Port x lock bit y (y= 0..15) - LCKK: u1, // bit offset: 16 desc: Lok Key + /// Port x lock bit y (y= 0..15) + LCK0: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK1: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK2: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK3: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK4: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK5: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK6: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK7: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK8: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK9: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK10: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK11: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK12: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK13: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK14: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK15: u1 = 0, + /// Lok Key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -1989,46 +3286,81 @@ pub const GPIOG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 GPIO alternate function low register + + /// GPIO alternate function low register pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - AFRL0: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 0..7) - }); - // byte offset: 36 GPIO alternate function high register + /// Alternate function selection for port x bit y (y = 0..7) + AFRL0: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4 = 0, + }); + + /// GPIO alternate function high register pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - AFRH8: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 8..15) - }); - // byte offset: 40 Port bit reset register + /// Alternate function selection for port x bit y (y = 8..15) + AFRH8: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4 = 0, + }); + + /// Port bit reset register pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Port x Reset bit y - BR1: u1, // bit offset: 1 desc: Port x Reset bit y - BR2: u1, // bit offset: 2 desc: Port x Reset bit y - BR3: u1, // bit offset: 3 desc: Port x Reset bit y - BR4: u1, // bit offset: 4 desc: Port x Reset bit y - BR5: u1, // bit offset: 5 desc: Port x Reset bit y - BR6: u1, // bit offset: 6 desc: Port x Reset bit y - BR7: u1, // bit offset: 7 desc: Port x Reset bit y - BR8: u1, // bit offset: 8 desc: Port x Reset bit y - BR9: u1, // bit offset: 9 desc: Port x Reset bit y - BR10: u1, // bit offset: 10 desc: Port x Reset bit y - BR11: u1, // bit offset: 11 desc: Port x Reset bit y - BR12: u1, // bit offset: 12 desc: Port x Reset bit y - BR13: u1, // bit offset: 13 desc: Port x Reset bit y - BR14: u1, // bit offset: 14 desc: Port x Reset bit y - BR15: u1, // bit offset: 15 desc: Port x Reset bit y + /// Port x Reset bit y + BR0: u1 = 0, + /// Port x Reset bit y + BR1: u1 = 0, + /// Port x Reset bit y + BR2: u1 = 0, + /// Port x Reset bit y + BR3: u1 = 0, + /// Port x Reset bit y + BR4: u1 = 0, + /// Port x Reset bit y + BR5: u1 = 0, + /// Port x Reset bit y + BR6: u1 = 0, + /// Port x Reset bit y + BR7: u1 = 0, + /// Port x Reset bit y + BR8: u1 = 0, + /// Port x Reset bit y + BR9: u1 = 0, + /// Port x Reset bit y + BR10: u1 = 0, + /// Port x Reset bit y + BR11: u1 = 0, + /// Port x Reset bit y + BR12: u1 = 0, + /// Port x Reset bit y + BR13: u1 = 0, + /// Port x Reset bit y + BR14: u1 = 0, + /// Port x Reset bit y + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2047,45 +3379,81 @@ pub const GPIOG = extern struct { padding1: u1 = 0, }); }; + +/// General-purpose I/Os pub const GPIOH = extern struct { pub const Address: u32 = 0x48001c00; - // byte offset: 0 GPIO port mode register + + /// GPIO port mode register pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - MODER0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - MODER1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - MODER2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - MODER3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - MODER4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - MODER5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - MODER6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - MODER7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - MODER8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - MODER9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - MODER10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - MODER11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - MODER12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - MODER13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - MODER14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - MODER15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 4 GPIO port output type register + /// Port x configuration bits (y = 0..15) + MODER0: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER1: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER2: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER3: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER4: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER5: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER6: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER7: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER8: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER9: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER10: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER11: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER12: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER13: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER14: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER15: u2 = 0, + }); + + /// GPIO port output type register pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - OT0: u1, // bit offset: 0 desc: Port x configuration bit 0 - OT1: u1, // bit offset: 1 desc: Port x configuration bit 1 - OT2: u1, // bit offset: 2 desc: Port x configuration bit 2 - OT3: u1, // bit offset: 3 desc: Port x configuration bit 3 - OT4: u1, // bit offset: 4 desc: Port x configuration bit 4 - OT5: u1, // bit offset: 5 desc: Port x configuration bit 5 - OT6: u1, // bit offset: 6 desc: Port x configuration bit 6 - OT7: u1, // bit offset: 7 desc: Port x configuration bit 7 - OT8: u1, // bit offset: 8 desc: Port x configuration bit 8 - OT9: u1, // bit offset: 9 desc: Port x configuration bit 9 - OT10: u1, // bit offset: 10 desc: Port x configuration bit 10 - OT11: u1, // bit offset: 11 desc: Port x configuration bit 11 - OT12: u1, // bit offset: 12 desc: Port x configuration bit 12 - OT13: u1, // bit offset: 13 desc: Port x configuration bit 13 - OT14: u1, // bit offset: 14 desc: Port x configuration bit 14 - OT15: u1, // bit offset: 15 desc: Port x configuration bit 15 + /// Port x configuration bit 0 + OT0: u1 = 0, + /// Port x configuration bit 1 + OT1: u1 = 0, + /// Port x configuration bit 2 + OT2: u1 = 0, + /// Port x configuration bit 3 + OT3: u1 = 0, + /// Port x configuration bit 4 + OT4: u1 = 0, + /// Port x configuration bit 5 + OT5: u1 = 0, + /// Port x configuration bit 6 + OT6: u1 = 0, + /// Port x configuration bit 7 + OT7: u1 = 0, + /// Port x configuration bit 8 + OT8: u1 = 0, + /// Port x configuration bit 9 + OT9: u1 = 0, + /// Port x configuration bit 10 + OT10: u1 = 0, + /// Port x configuration bit 11 + OT11: u1 = 0, + /// Port x configuration bit 12 + OT12: u1 = 0, + /// Port x configuration bit 13 + OT13: u1 = 0, + /// Port x configuration bit 14 + OT14: u1 = 0, + /// Port x configuration bit 15 + OT15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2103,62 +3471,113 @@ pub const GPIOH = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 GPIO port output speed register + + /// GPIO port output speed register pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - OSPEEDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - OSPEEDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - OSPEEDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - OSPEEDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - OSPEEDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - OSPEEDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - OSPEEDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - OSPEEDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - OSPEEDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - OSPEEDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - OSPEEDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - OSPEEDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - OSPEEDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - OSPEEDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - OSPEEDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - OSPEEDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 12 GPIO port pull-up/pull-down register + /// Port x configuration bits (y = 0..15) + OSPEEDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR15: u2 = 0, + }); + + /// GPIO port pull-up/pull-down register pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - PUPDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - PUPDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - PUPDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - PUPDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - PUPDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - PUPDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - PUPDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - PUPDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - PUPDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - PUPDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - PUPDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - PUPDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - PUPDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - PUPDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - PUPDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - PUPDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 16 GPIO port input data register + /// Port x configuration bits (y = 0..15) + PUPDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR15: u2 = 0, + }); + + /// GPIO port input data register pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data (y = 0..15) - IDR1: u1, // bit offset: 1 desc: Port input data (y = 0..15) - IDR2: u1, // bit offset: 2 desc: Port input data (y = 0..15) - IDR3: u1, // bit offset: 3 desc: Port input data (y = 0..15) - IDR4: u1, // bit offset: 4 desc: Port input data (y = 0..15) - IDR5: u1, // bit offset: 5 desc: Port input data (y = 0..15) - IDR6: u1, // bit offset: 6 desc: Port input data (y = 0..15) - IDR7: u1, // bit offset: 7 desc: Port input data (y = 0..15) - IDR8: u1, // bit offset: 8 desc: Port input data (y = 0..15) - IDR9: u1, // bit offset: 9 desc: Port input data (y = 0..15) - IDR10: u1, // bit offset: 10 desc: Port input data (y = 0..15) - IDR11: u1, // bit offset: 11 desc: Port input data (y = 0..15) - IDR12: u1, // bit offset: 12 desc: Port input data (y = 0..15) - IDR13: u1, // bit offset: 13 desc: Port input data (y = 0..15) - IDR14: u1, // bit offset: 14 desc: Port input data (y = 0..15) - IDR15: u1, // bit offset: 15 desc: Port input data (y = 0..15) + /// Port input data (y = 0..15) + IDR0: u1 = 0, + /// Port input data (y = 0..15) + IDR1: u1 = 0, + /// Port input data (y = 0..15) + IDR2: u1 = 0, + /// Port input data (y = 0..15) + IDR3: u1 = 0, + /// Port input data (y = 0..15) + IDR4: u1 = 0, + /// Port input data (y = 0..15) + IDR5: u1 = 0, + /// Port input data (y = 0..15) + IDR6: u1 = 0, + /// Port input data (y = 0..15) + IDR7: u1 = 0, + /// Port input data (y = 0..15) + IDR8: u1 = 0, + /// Port input data (y = 0..15) + IDR9: u1 = 0, + /// Port input data (y = 0..15) + IDR10: u1 = 0, + /// Port input data (y = 0..15) + IDR11: u1 = 0, + /// Port input data (y = 0..15) + IDR12: u1 = 0, + /// Port input data (y = 0..15) + IDR13: u1 = 0, + /// Port input data (y = 0..15) + IDR14: u1 = 0, + /// Port input data (y = 0..15) + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2176,24 +3595,41 @@ pub const GPIOH = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 GPIO port output data register + + /// GPIO port output data register pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data (y = 0..15) - ODR1: u1, // bit offset: 1 desc: Port output data (y = 0..15) - ODR2: u1, // bit offset: 2 desc: Port output data (y = 0..15) - ODR3: u1, // bit offset: 3 desc: Port output data (y = 0..15) - ODR4: u1, // bit offset: 4 desc: Port output data (y = 0..15) - ODR5: u1, // bit offset: 5 desc: Port output data (y = 0..15) - ODR6: u1, // bit offset: 6 desc: Port output data (y = 0..15) - ODR7: u1, // bit offset: 7 desc: Port output data (y = 0..15) - ODR8: u1, // bit offset: 8 desc: Port output data (y = 0..15) - ODR9: u1, // bit offset: 9 desc: Port output data (y = 0..15) - ODR10: u1, // bit offset: 10 desc: Port output data (y = 0..15) - ODR11: u1, // bit offset: 11 desc: Port output data (y = 0..15) - ODR12: u1, // bit offset: 12 desc: Port output data (y = 0..15) - ODR13: u1, // bit offset: 13 desc: Port output data (y = 0..15) - ODR14: u1, // bit offset: 14 desc: Port output data (y = 0..15) - ODR15: u1, // bit offset: 15 desc: Port output data (y = 0..15) + /// Port output data (y = 0..15) + ODR0: u1 = 0, + /// Port output data (y = 0..15) + ODR1: u1 = 0, + /// Port output data (y = 0..15) + ODR2: u1 = 0, + /// Port output data (y = 0..15) + ODR3: u1 = 0, + /// Port output data (y = 0..15) + ODR4: u1 = 0, + /// Port output data (y = 0..15) + ODR5: u1 = 0, + /// Port output data (y = 0..15) + ODR6: u1 = 0, + /// Port output data (y = 0..15) + ODR7: u1 = 0, + /// Port output data (y = 0..15) + ODR8: u1 = 0, + /// Port output data (y = 0..15) + ODR9: u1 = 0, + /// Port output data (y = 0..15) + ODR10: u1 = 0, + /// Port output data (y = 0..15) + ODR11: u1 = 0, + /// Port output data (y = 0..15) + ODR12: u1 = 0, + /// Port output data (y = 0..15) + ODR13: u1 = 0, + /// Port output data (y = 0..15) + ODR14: u1 = 0, + /// Port output data (y = 0..15) + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2211,60 +3647,111 @@ pub const GPIOH = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 GPIO port bit set/reset register + + /// GPIO port bit set/reset register pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Port x set bit y (y= 0..15) - BS1: u1, // bit offset: 1 desc: Port x set bit y (y= 0..15) - BS2: u1, // bit offset: 2 desc: Port x set bit y (y= 0..15) - BS3: u1, // bit offset: 3 desc: Port x set bit y (y= 0..15) - BS4: u1, // bit offset: 4 desc: Port x set bit y (y= 0..15) - BS5: u1, // bit offset: 5 desc: Port x set bit y (y= 0..15) - BS6: u1, // bit offset: 6 desc: Port x set bit y (y= 0..15) - BS7: u1, // bit offset: 7 desc: Port x set bit y (y= 0..15) - BS8: u1, // bit offset: 8 desc: Port x set bit y (y= 0..15) - BS9: u1, // bit offset: 9 desc: Port x set bit y (y= 0..15) - BS10: u1, // bit offset: 10 desc: Port x set bit y (y= 0..15) - BS11: u1, // bit offset: 11 desc: Port x set bit y (y= 0..15) - BS12: u1, // bit offset: 12 desc: Port x set bit y (y= 0..15) - BS13: u1, // bit offset: 13 desc: Port x set bit y (y= 0..15) - BS14: u1, // bit offset: 14 desc: Port x set bit y (y= 0..15) - BS15: u1, // bit offset: 15 desc: Port x set bit y (y= 0..15) - BR0: u1, // bit offset: 16 desc: Port x set bit y (y= 0..15) - BR1: u1, // bit offset: 17 desc: Port x reset bit y (y = 0..15) - BR2: u1, // bit offset: 18 desc: Port x reset bit y (y = 0..15) - BR3: u1, // bit offset: 19 desc: Port x reset bit y (y = 0..15) - BR4: u1, // bit offset: 20 desc: Port x reset bit y (y = 0..15) - BR5: u1, // bit offset: 21 desc: Port x reset bit y (y = 0..15) - BR6: u1, // bit offset: 22 desc: Port x reset bit y (y = 0..15) - BR7: u1, // bit offset: 23 desc: Port x reset bit y (y = 0..15) - BR8: u1, // bit offset: 24 desc: Port x reset bit y (y = 0..15) - BR9: u1, // bit offset: 25 desc: Port x reset bit y (y = 0..15) - BR10: u1, // bit offset: 26 desc: Port x reset bit y (y = 0..15) - BR11: u1, // bit offset: 27 desc: Port x reset bit y (y = 0..15) - BR12: u1, // bit offset: 28 desc: Port x reset bit y (y = 0..15) - BR13: u1, // bit offset: 29 desc: Port x reset bit y (y = 0..15) - BR14: u1, // bit offset: 30 desc: Port x reset bit y (y = 0..15) - BR15: u1, // bit offset: 31 desc: Port x reset bit y (y = 0..15) - }); - // byte offset: 28 GPIO port configuration lock register + /// Port x set bit y (y= 0..15) + BS0: u1 = 0, + /// Port x set bit y (y= 0..15) + BS1: u1 = 0, + /// Port x set bit y (y= 0..15) + BS2: u1 = 0, + /// Port x set bit y (y= 0..15) + BS3: u1 = 0, + /// Port x set bit y (y= 0..15) + BS4: u1 = 0, + /// Port x set bit y (y= 0..15) + BS5: u1 = 0, + /// Port x set bit y (y= 0..15) + BS6: u1 = 0, + /// Port x set bit y (y= 0..15) + BS7: u1 = 0, + /// Port x set bit y (y= 0..15) + BS8: u1 = 0, + /// Port x set bit y (y= 0..15) + BS9: u1 = 0, + /// Port x set bit y (y= 0..15) + BS10: u1 = 0, + /// Port x set bit y (y= 0..15) + BS11: u1 = 0, + /// Port x set bit y (y= 0..15) + BS12: u1 = 0, + /// Port x set bit y (y= 0..15) + BS13: u1 = 0, + /// Port x set bit y (y= 0..15) + BS14: u1 = 0, + /// Port x set bit y (y= 0..15) + BS15: u1 = 0, + /// Port x set bit y (y= 0..15) + BR0: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR1: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR2: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR3: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR4: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR5: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR6: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR7: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR8: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR9: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR10: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR11: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR12: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR13: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR14: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR15: u1 = 0, + }); + + /// GPIO port configuration lock register pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port x lock bit y (y= 0..15) - LCK1: u1, // bit offset: 1 desc: Port x lock bit y (y= 0..15) - LCK2: u1, // bit offset: 2 desc: Port x lock bit y (y= 0..15) - LCK3: u1, // bit offset: 3 desc: Port x lock bit y (y= 0..15) - LCK4: u1, // bit offset: 4 desc: Port x lock bit y (y= 0..15) - LCK5: u1, // bit offset: 5 desc: Port x lock bit y (y= 0..15) - LCK6: u1, // bit offset: 6 desc: Port x lock bit y (y= 0..15) - LCK7: u1, // bit offset: 7 desc: Port x lock bit y (y= 0..15) - LCK8: u1, // bit offset: 8 desc: Port x lock bit y (y= 0..15) - LCK9: u1, // bit offset: 9 desc: Port x lock bit y (y= 0..15) - LCK10: u1, // bit offset: 10 desc: Port x lock bit y (y= 0..15) - LCK11: u1, // bit offset: 11 desc: Port x lock bit y (y= 0..15) - LCK12: u1, // bit offset: 12 desc: Port x lock bit y (y= 0..15) - LCK13: u1, // bit offset: 13 desc: Port x lock bit y (y= 0..15) - LCK14: u1, // bit offset: 14 desc: Port x lock bit y (y= 0..15) - LCK15: u1, // bit offset: 15 desc: Port x lock bit y (y= 0..15) - LCKK: u1, // bit offset: 16 desc: Lok Key + /// Port x lock bit y (y= 0..15) + LCK0: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK1: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK2: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK3: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK4: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK5: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK6: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK7: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK8: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK9: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK10: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK11: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK12: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK13: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK14: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK15: u1 = 0, + /// Lok Key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -2281,46 +3768,81 @@ pub const GPIOH = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 GPIO alternate function low register + + /// GPIO alternate function low register pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - AFRL0: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 0..7) - }); - // byte offset: 36 GPIO alternate function high register + /// Alternate function selection for port x bit y (y = 0..7) + AFRL0: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4 = 0, + }); + + /// GPIO alternate function high register pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - AFRH8: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 8..15) - }); - // byte offset: 40 Port bit reset register + /// Alternate function selection for port x bit y (y = 8..15) + AFRH8: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4 = 0, + }); + + /// Port bit reset register pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Port x Reset bit y - BR1: u1, // bit offset: 1 desc: Port x Reset bit y - BR2: u1, // bit offset: 2 desc: Port x Reset bit y - BR3: u1, // bit offset: 3 desc: Port x Reset bit y - BR4: u1, // bit offset: 4 desc: Port x Reset bit y - BR5: u1, // bit offset: 5 desc: Port x Reset bit y - BR6: u1, // bit offset: 6 desc: Port x Reset bit y - BR7: u1, // bit offset: 7 desc: Port x Reset bit y - BR8: u1, // bit offset: 8 desc: Port x Reset bit y - BR9: u1, // bit offset: 9 desc: Port x Reset bit y - BR10: u1, // bit offset: 10 desc: Port x Reset bit y - BR11: u1, // bit offset: 11 desc: Port x Reset bit y - BR12: u1, // bit offset: 12 desc: Port x Reset bit y - BR13: u1, // bit offset: 13 desc: Port x Reset bit y - BR14: u1, // bit offset: 14 desc: Port x Reset bit y - BR15: u1, // bit offset: 15 desc: Port x Reset bit y + /// Port x Reset bit y + BR0: u1 = 0, + /// Port x Reset bit y + BR1: u1 = 0, + /// Port x Reset bit y + BR2: u1 = 0, + /// Port x Reset bit y + BR3: u1 = 0, + /// Port x Reset bit y + BR4: u1 = 0, + /// Port x Reset bit y + BR5: u1 = 0, + /// Port x Reset bit y + BR6: u1 = 0, + /// Port x Reset bit y + BR7: u1 = 0, + /// Port x Reset bit y + BR8: u1 = 0, + /// Port x Reset bit y + BR9: u1 = 0, + /// Port x Reset bit y + BR10: u1 = 0, + /// Port x Reset bit y + BR11: u1 = 0, + /// Port x Reset bit y + BR12: u1 = 0, + /// Port x Reset bit y + BR13: u1 = 0, + /// Port x Reset bit y + BR14: u1 = 0, + /// Port x Reset bit y + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2339,31 +3861,49 @@ pub const GPIOH = extern struct { padding1: u1 = 0, }); }; + +/// Touch sensing controller pub const TSC = extern struct { pub const Address: u32 = 0x40024000; - // byte offset: 0 control register + + /// control register pub const CR = mmio(Address + 0x00000000, 32, packed struct { - TSCE: u1, // bit offset: 0 desc: Touch sensing controller enable - START: u1, // bit offset: 1 desc: Start a new acquisition - AM: u1, // bit offset: 2 desc: Acquisition mode - SYNCPOL: u1, // bit offset: 3 desc: Synchronization pin polarity - IODEF: u1, // bit offset: 4 desc: I/O Default mode - MCV: u3, // bit offset: 5 desc: Max count value + /// Touch sensing controller enable + TSCE: u1 = 0, + /// Start a new acquisition + START: u1 = 0, + /// Acquisition mode + AM: u1 = 0, + /// Synchronization pin polarity + SYNCPOL: u1 = 0, + /// I/O Default mode + IODEF: u1 = 0, + /// Max count value + MCV: u3 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - PGPSC: u3, // bit offset: 12 desc: pulse generator prescaler - SSPSC: u1, // bit offset: 15 desc: Spread spectrum prescaler - SSE: u1, // bit offset: 16 desc: Spread spectrum enable - SSD: u7, // bit offset: 17 desc: Spread spectrum deviation - CTPL: u4, // bit offset: 24 desc: Charge transfer pulse low - CTPH: u4, // bit offset: 28 desc: Charge transfer pulse high + /// pulse generator prescaler + PGPSC: u3 = 0, + /// Spread spectrum prescaler + SSPSC: u1 = 0, + /// Spread spectrum enable + SSE: u1 = 0, + /// Spread spectrum deviation + SSD: u7 = 0, + /// Charge transfer pulse low + CTPL: u4 = 0, + /// Charge transfer pulse high + CTPH: u4 = 0, }); - // byte offset: 4 interrupt enable register + + /// interrupt enable register pub const IER = mmio(Address + 0x00000004, 32, packed struct { - EOAIE: u1, // bit offset: 0 desc: End of acquisition interrupt enable - MCEIE: u1, // bit offset: 1 desc: Max count error interrupt enable + /// End of acquisition interrupt enable + EOAIE: u1 = 0, + /// Max count error interrupt enable + MCEIE: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -2395,10 +3935,13 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 interrupt clear register + + /// interrupt clear register pub const ICR = mmio(Address + 0x00000008, 32, packed struct { - EOAIC: u1, // bit offset: 0 desc: End of acquisition interrupt clear - MCEIC: u1, // bit offset: 1 desc: Max count error interrupt clear + /// End of acquisition interrupt clear + EOAIC: u1 = 0, + /// Max count error interrupt clear + MCEIC: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -2430,10 +3973,13 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 interrupt status register + + /// interrupt status register pub const ISR = mmio(Address + 0x0000000c, 32, packed struct { - EOAF: u1, // bit offset: 0 desc: End of acquisition flag - MCEF: u1, // bit offset: 1 desc: Max count error flag + /// End of acquisition flag + EOAF: u1 = 0, + /// Max count error flag + MCEF: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -2465,156 +4011,297 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 I/O hysteresis control register + + /// I/O hysteresis control register pub const IOHCR = mmio(Address + 0x00000010, 32, packed struct { - G1_IO1: u1, // bit offset: 0 desc: G1_IO1 Schmitt trigger hysteresis mode - G1_IO2: u1, // bit offset: 1 desc: G1_IO2 Schmitt trigger hysteresis mode - G1_IO3: u1, // bit offset: 2 desc: G1_IO3 Schmitt trigger hysteresis mode - G1_IO4: u1, // bit offset: 3 desc: G1_IO4 Schmitt trigger hysteresis mode - G2_IO1: u1, // bit offset: 4 desc: G2_IO1 Schmitt trigger hysteresis mode - G2_IO2: u1, // bit offset: 5 desc: G2_IO2 Schmitt trigger hysteresis mode - G2_IO3: u1, // bit offset: 6 desc: G2_IO3 Schmitt trigger hysteresis mode - G2_IO4: u1, // bit offset: 7 desc: G2_IO4 Schmitt trigger hysteresis mode - G3_IO1: u1, // bit offset: 8 desc: G3_IO1 Schmitt trigger hysteresis mode - G3_IO2: u1, // bit offset: 9 desc: G3_IO2 Schmitt trigger hysteresis mode - G3_IO3: u1, // bit offset: 10 desc: G3_IO3 Schmitt trigger hysteresis mode - G3_IO4: u1, // bit offset: 11 desc: G3_IO4 Schmitt trigger hysteresis mode - G4_IO1: u1, // bit offset: 12 desc: G4_IO1 Schmitt trigger hysteresis mode - G4_IO2: u1, // bit offset: 13 desc: G4_IO2 Schmitt trigger hysteresis mode - G4_IO3: u1, // bit offset: 14 desc: G4_IO3 Schmitt trigger hysteresis mode - G4_IO4: u1, // bit offset: 15 desc: G4_IO4 Schmitt trigger hysteresis mode - G5_IO1: u1, // bit offset: 16 desc: G5_IO1 Schmitt trigger hysteresis mode - G5_IO2: u1, // bit offset: 17 desc: G5_IO2 Schmitt trigger hysteresis mode - G5_IO3: u1, // bit offset: 18 desc: G5_IO3 Schmitt trigger hysteresis mode - G5_IO4: u1, // bit offset: 19 desc: G5_IO4 Schmitt trigger hysteresis mode - G6_IO1: u1, // bit offset: 20 desc: G6_IO1 Schmitt trigger hysteresis mode - G6_IO2: u1, // bit offset: 21 desc: G6_IO2 Schmitt trigger hysteresis mode - G6_IO3: u1, // bit offset: 22 desc: G6_IO3 Schmitt trigger hysteresis mode - G6_IO4: u1, // bit offset: 23 desc: G6_IO4 Schmitt trigger hysteresis mode - G7_IO1: u1, // bit offset: 24 desc: G7_IO1 Schmitt trigger hysteresis mode - G7_IO2: u1, // bit offset: 25 desc: G7_IO2 Schmitt trigger hysteresis mode - G7_IO3: u1, // bit offset: 26 desc: G7_IO3 Schmitt trigger hysteresis mode - G7_IO4: u1, // bit offset: 27 desc: G7_IO4 Schmitt trigger hysteresis mode - G8_IO1: u1, // bit offset: 28 desc: G8_IO1 Schmitt trigger hysteresis mode - G8_IO2: u1, // bit offset: 29 desc: G8_IO2 Schmitt trigger hysteresis mode - G8_IO3: u1, // bit offset: 30 desc: G8_IO3 Schmitt trigger hysteresis mode - G8_IO4: u1, // bit offset: 31 desc: G8_IO4 Schmitt trigger hysteresis mode - }); - // byte offset: 24 I/O analog switch control register + /// G1_IO1 Schmitt trigger hysteresis mode + G1_IO1: u1 = 0, + /// G1_IO2 Schmitt trigger hysteresis mode + G1_IO2: u1 = 0, + /// G1_IO3 Schmitt trigger hysteresis mode + G1_IO3: u1 = 0, + /// G1_IO4 Schmitt trigger hysteresis mode + G1_IO4: u1 = 0, + /// G2_IO1 Schmitt trigger hysteresis mode + G2_IO1: u1 = 0, + /// G2_IO2 Schmitt trigger hysteresis mode + G2_IO2: u1 = 0, + /// G2_IO3 Schmitt trigger hysteresis mode + G2_IO3: u1 = 0, + /// G2_IO4 Schmitt trigger hysteresis mode + G2_IO4: u1 = 0, + /// G3_IO1 Schmitt trigger hysteresis mode + G3_IO1: u1 = 0, + /// G3_IO2 Schmitt trigger hysteresis mode + G3_IO2: u1 = 0, + /// G3_IO3 Schmitt trigger hysteresis mode + G3_IO3: u1 = 0, + /// G3_IO4 Schmitt trigger hysteresis mode + G3_IO4: u1 = 0, + /// G4_IO1 Schmitt trigger hysteresis mode + G4_IO1: u1 = 0, + /// G4_IO2 Schmitt trigger hysteresis mode + G4_IO2: u1 = 0, + /// G4_IO3 Schmitt trigger hysteresis mode + G4_IO3: u1 = 0, + /// G4_IO4 Schmitt trigger hysteresis mode + G4_IO4: u1 = 0, + /// G5_IO1 Schmitt trigger hysteresis mode + G5_IO1: u1 = 0, + /// G5_IO2 Schmitt trigger hysteresis mode + G5_IO2: u1 = 0, + /// G5_IO3 Schmitt trigger hysteresis mode + G5_IO3: u1 = 0, + /// G5_IO4 Schmitt trigger hysteresis mode + G5_IO4: u1 = 0, + /// G6_IO1 Schmitt trigger hysteresis mode + G6_IO1: u1 = 0, + /// G6_IO2 Schmitt trigger hysteresis mode + G6_IO2: u1 = 0, + /// G6_IO3 Schmitt trigger hysteresis mode + G6_IO3: u1 = 0, + /// G6_IO4 Schmitt trigger hysteresis mode + G6_IO4: u1 = 0, + /// G7_IO1 Schmitt trigger hysteresis mode + G7_IO1: u1 = 0, + /// G7_IO2 Schmitt trigger hysteresis mode + G7_IO2: u1 = 0, + /// G7_IO3 Schmitt trigger hysteresis mode + G7_IO3: u1 = 0, + /// G7_IO4 Schmitt trigger hysteresis mode + G7_IO4: u1 = 0, + /// G8_IO1 Schmitt trigger hysteresis mode + G8_IO1: u1 = 0, + /// G8_IO2 Schmitt trigger hysteresis mode + G8_IO2: u1 = 0, + /// G8_IO3 Schmitt trigger hysteresis mode + G8_IO3: u1 = 0, + /// G8_IO4 Schmitt trigger hysteresis mode + G8_IO4: u1 = 0, + }); + + /// I/O analog switch control register pub const IOASCR = mmio(Address + 0x00000018, 32, packed struct { - G1_IO1: u1, // bit offset: 0 desc: G1_IO1 analog switch enable - G1_IO2: u1, // bit offset: 1 desc: G1_IO2 analog switch enable - G1_IO3: u1, // bit offset: 2 desc: G1_IO3 analog switch enable - G1_IO4: u1, // bit offset: 3 desc: G1_IO4 analog switch enable - G2_IO1: u1, // bit offset: 4 desc: G2_IO1 analog switch enable - G2_IO2: u1, // bit offset: 5 desc: G2_IO2 analog switch enable - G2_IO3: u1, // bit offset: 6 desc: G2_IO3 analog switch enable - G2_IO4: u1, // bit offset: 7 desc: G2_IO4 analog switch enable - G3_IO1: u1, // bit offset: 8 desc: G3_IO1 analog switch enable - G3_IO2: u1, // bit offset: 9 desc: G3_IO2 analog switch enable - G3_IO3: u1, // bit offset: 10 desc: G3_IO3 analog switch enable - G3_IO4: u1, // bit offset: 11 desc: G3_IO4 analog switch enable - G4_IO1: u1, // bit offset: 12 desc: G4_IO1 analog switch enable - G4_IO2: u1, // bit offset: 13 desc: G4_IO2 analog switch enable - G4_IO3: u1, // bit offset: 14 desc: G4_IO3 analog switch enable - G4_IO4: u1, // bit offset: 15 desc: G4_IO4 analog switch enable - G5_IO1: u1, // bit offset: 16 desc: G5_IO1 analog switch enable - G5_IO2: u1, // bit offset: 17 desc: G5_IO2 analog switch enable - G5_IO3: u1, // bit offset: 18 desc: G5_IO3 analog switch enable - G5_IO4: u1, // bit offset: 19 desc: G5_IO4 analog switch enable - G6_IO1: u1, // bit offset: 20 desc: G6_IO1 analog switch enable - G6_IO2: u1, // bit offset: 21 desc: G6_IO2 analog switch enable - G6_IO3: u1, // bit offset: 22 desc: G6_IO3 analog switch enable - G6_IO4: u1, // bit offset: 23 desc: G6_IO4 analog switch enable - G7_IO1: u1, // bit offset: 24 desc: G7_IO1 analog switch enable - G7_IO2: u1, // bit offset: 25 desc: G7_IO2 analog switch enable - G7_IO3: u1, // bit offset: 26 desc: G7_IO3 analog switch enable - G7_IO4: u1, // bit offset: 27 desc: G7_IO4 analog switch enable - G8_IO1: u1, // bit offset: 28 desc: G8_IO1 analog switch enable - G8_IO2: u1, // bit offset: 29 desc: G8_IO2 analog switch enable - G8_IO3: u1, // bit offset: 30 desc: G8_IO3 analog switch enable - G8_IO4: u1, // bit offset: 31 desc: G8_IO4 analog switch enable - }); - // byte offset: 32 I/O sampling control register + /// G1_IO1 analog switch enable + G1_IO1: u1 = 0, + /// G1_IO2 analog switch enable + G1_IO2: u1 = 0, + /// G1_IO3 analog switch enable + G1_IO3: u1 = 0, + /// G1_IO4 analog switch enable + G1_IO4: u1 = 0, + /// G2_IO1 analog switch enable + G2_IO1: u1 = 0, + /// G2_IO2 analog switch enable + G2_IO2: u1 = 0, + /// G2_IO3 analog switch enable + G2_IO3: u1 = 0, + /// G2_IO4 analog switch enable + G2_IO4: u1 = 0, + /// G3_IO1 analog switch enable + G3_IO1: u1 = 0, + /// G3_IO2 analog switch enable + G3_IO2: u1 = 0, + /// G3_IO3 analog switch enable + G3_IO3: u1 = 0, + /// G3_IO4 analog switch enable + G3_IO4: u1 = 0, + /// G4_IO1 analog switch enable + G4_IO1: u1 = 0, + /// G4_IO2 analog switch enable + G4_IO2: u1 = 0, + /// G4_IO3 analog switch enable + G4_IO3: u1 = 0, + /// G4_IO4 analog switch enable + G4_IO4: u1 = 0, + /// G5_IO1 analog switch enable + G5_IO1: u1 = 0, + /// G5_IO2 analog switch enable + G5_IO2: u1 = 0, + /// G5_IO3 analog switch enable + G5_IO3: u1 = 0, + /// G5_IO4 analog switch enable + G5_IO4: u1 = 0, + /// G6_IO1 analog switch enable + G6_IO1: u1 = 0, + /// G6_IO2 analog switch enable + G6_IO2: u1 = 0, + /// G6_IO3 analog switch enable + G6_IO3: u1 = 0, + /// G6_IO4 analog switch enable + G6_IO4: u1 = 0, + /// G7_IO1 analog switch enable + G7_IO1: u1 = 0, + /// G7_IO2 analog switch enable + G7_IO2: u1 = 0, + /// G7_IO3 analog switch enable + G7_IO3: u1 = 0, + /// G7_IO4 analog switch enable + G7_IO4: u1 = 0, + /// G8_IO1 analog switch enable + G8_IO1: u1 = 0, + /// G8_IO2 analog switch enable + G8_IO2: u1 = 0, + /// G8_IO3 analog switch enable + G8_IO3: u1 = 0, + /// G8_IO4 analog switch enable + G8_IO4: u1 = 0, + }); + + /// I/O sampling control register pub const IOSCR = mmio(Address + 0x00000020, 32, packed struct { - G1_IO1: u1, // bit offset: 0 desc: G1_IO1 sampling mode - G1_IO2: u1, // bit offset: 1 desc: G1_IO2 sampling mode - G1_IO3: u1, // bit offset: 2 desc: G1_IO3 sampling mode - G1_IO4: u1, // bit offset: 3 desc: G1_IO4 sampling mode - G2_IO1: u1, // bit offset: 4 desc: G2_IO1 sampling mode - G2_IO2: u1, // bit offset: 5 desc: G2_IO2 sampling mode - G2_IO3: u1, // bit offset: 6 desc: G2_IO3 sampling mode - G2_IO4: u1, // bit offset: 7 desc: G2_IO4 sampling mode - G3_IO1: u1, // bit offset: 8 desc: G3_IO1 sampling mode - G3_IO2: u1, // bit offset: 9 desc: G3_IO2 sampling mode - G3_IO3: u1, // bit offset: 10 desc: G3_IO3 sampling mode - G3_IO4: u1, // bit offset: 11 desc: G3_IO4 sampling mode - G4_IO1: u1, // bit offset: 12 desc: G4_IO1 sampling mode - G4_IO2: u1, // bit offset: 13 desc: G4_IO2 sampling mode - G4_IO3: u1, // bit offset: 14 desc: G4_IO3 sampling mode - G4_IO4: u1, // bit offset: 15 desc: G4_IO4 sampling mode - G5_IO1: u1, // bit offset: 16 desc: G5_IO1 sampling mode - G5_IO2: u1, // bit offset: 17 desc: G5_IO2 sampling mode - G5_IO3: u1, // bit offset: 18 desc: G5_IO3 sampling mode - G5_IO4: u1, // bit offset: 19 desc: G5_IO4 sampling mode - G6_IO1: u1, // bit offset: 20 desc: G6_IO1 sampling mode - G6_IO2: u1, // bit offset: 21 desc: G6_IO2 sampling mode - G6_IO3: u1, // bit offset: 22 desc: G6_IO3 sampling mode - G6_IO4: u1, // bit offset: 23 desc: G6_IO4 sampling mode - G7_IO1: u1, // bit offset: 24 desc: G7_IO1 sampling mode - G7_IO2: u1, // bit offset: 25 desc: G7_IO2 sampling mode - G7_IO3: u1, // bit offset: 26 desc: G7_IO3 sampling mode - G7_IO4: u1, // bit offset: 27 desc: G7_IO4 sampling mode - G8_IO1: u1, // bit offset: 28 desc: G8_IO1 sampling mode - G8_IO2: u1, // bit offset: 29 desc: G8_IO2 sampling mode - G8_IO3: u1, // bit offset: 30 desc: G8_IO3 sampling mode - G8_IO4: u1, // bit offset: 31 desc: G8_IO4 sampling mode - }); - // byte offset: 40 I/O channel control register + /// G1_IO1 sampling mode + G1_IO1: u1 = 0, + /// G1_IO2 sampling mode + G1_IO2: u1 = 0, + /// G1_IO3 sampling mode + G1_IO3: u1 = 0, + /// G1_IO4 sampling mode + G1_IO4: u1 = 0, + /// G2_IO1 sampling mode + G2_IO1: u1 = 0, + /// G2_IO2 sampling mode + G2_IO2: u1 = 0, + /// G2_IO3 sampling mode + G2_IO3: u1 = 0, + /// G2_IO4 sampling mode + G2_IO4: u1 = 0, + /// G3_IO1 sampling mode + G3_IO1: u1 = 0, + /// G3_IO2 sampling mode + G3_IO2: u1 = 0, + /// G3_IO3 sampling mode + G3_IO3: u1 = 0, + /// G3_IO4 sampling mode + G3_IO4: u1 = 0, + /// G4_IO1 sampling mode + G4_IO1: u1 = 0, + /// G4_IO2 sampling mode + G4_IO2: u1 = 0, + /// G4_IO3 sampling mode + G4_IO3: u1 = 0, + /// G4_IO4 sampling mode + G4_IO4: u1 = 0, + /// G5_IO1 sampling mode + G5_IO1: u1 = 0, + /// G5_IO2 sampling mode + G5_IO2: u1 = 0, + /// G5_IO3 sampling mode + G5_IO3: u1 = 0, + /// G5_IO4 sampling mode + G5_IO4: u1 = 0, + /// G6_IO1 sampling mode + G6_IO1: u1 = 0, + /// G6_IO2 sampling mode + G6_IO2: u1 = 0, + /// G6_IO3 sampling mode + G6_IO3: u1 = 0, + /// G6_IO4 sampling mode + G6_IO4: u1 = 0, + /// G7_IO1 sampling mode + G7_IO1: u1 = 0, + /// G7_IO2 sampling mode + G7_IO2: u1 = 0, + /// G7_IO3 sampling mode + G7_IO3: u1 = 0, + /// G7_IO4 sampling mode + G7_IO4: u1 = 0, + /// G8_IO1 sampling mode + G8_IO1: u1 = 0, + /// G8_IO2 sampling mode + G8_IO2: u1 = 0, + /// G8_IO3 sampling mode + G8_IO3: u1 = 0, + /// G8_IO4 sampling mode + G8_IO4: u1 = 0, + }); + + /// I/O channel control register pub const IOCCR = mmio(Address + 0x00000028, 32, packed struct { - G1_IO1: u1, // bit offset: 0 desc: G1_IO1 channel mode - G1_IO2: u1, // bit offset: 1 desc: G1_IO2 channel mode - G1_IO3: u1, // bit offset: 2 desc: G1_IO3 channel mode - G1_IO4: u1, // bit offset: 3 desc: G1_IO4 channel mode - G2_IO1: u1, // bit offset: 4 desc: G2_IO1 channel mode - G2_IO2: u1, // bit offset: 5 desc: G2_IO2 channel mode - G2_IO3: u1, // bit offset: 6 desc: G2_IO3 channel mode - G2_IO4: u1, // bit offset: 7 desc: G2_IO4 channel mode - G3_IO1: u1, // bit offset: 8 desc: G3_IO1 channel mode - G3_IO2: u1, // bit offset: 9 desc: G3_IO2 channel mode - G3_IO3: u1, // bit offset: 10 desc: G3_IO3 channel mode - G3_IO4: u1, // bit offset: 11 desc: G3_IO4 channel mode - G4_IO1: u1, // bit offset: 12 desc: G4_IO1 channel mode - G4_IO2: u1, // bit offset: 13 desc: G4_IO2 channel mode - G4_IO3: u1, // bit offset: 14 desc: G4_IO3 channel mode - G4_IO4: u1, // bit offset: 15 desc: G4_IO4 channel mode - G5_IO1: u1, // bit offset: 16 desc: G5_IO1 channel mode - G5_IO2: u1, // bit offset: 17 desc: G5_IO2 channel mode - G5_IO3: u1, // bit offset: 18 desc: G5_IO3 channel mode - G5_IO4: u1, // bit offset: 19 desc: G5_IO4 channel mode - G6_IO1: u1, // bit offset: 20 desc: G6_IO1 channel mode - G6_IO2: u1, // bit offset: 21 desc: G6_IO2 channel mode - G6_IO3: u1, // bit offset: 22 desc: G6_IO3 channel mode - G6_IO4: u1, // bit offset: 23 desc: G6_IO4 channel mode - G7_IO1: u1, // bit offset: 24 desc: G7_IO1 channel mode - G7_IO2: u1, // bit offset: 25 desc: G7_IO2 channel mode - G7_IO3: u1, // bit offset: 26 desc: G7_IO3 channel mode - G7_IO4: u1, // bit offset: 27 desc: G7_IO4 channel mode - G8_IO1: u1, // bit offset: 28 desc: G8_IO1 channel mode - G8_IO2: u1, // bit offset: 29 desc: G8_IO2 channel mode - G8_IO3: u1, // bit offset: 30 desc: G8_IO3 channel mode - G8_IO4: u1, // bit offset: 31 desc: G8_IO4 channel mode - }); - // byte offset: 48 I/O group control status register + /// G1_IO1 channel mode + G1_IO1: u1 = 0, + /// G1_IO2 channel mode + G1_IO2: u1 = 0, + /// G1_IO3 channel mode + G1_IO3: u1 = 0, + /// G1_IO4 channel mode + G1_IO4: u1 = 0, + /// G2_IO1 channel mode + G2_IO1: u1 = 0, + /// G2_IO2 channel mode + G2_IO2: u1 = 0, + /// G2_IO3 channel mode + G2_IO3: u1 = 0, + /// G2_IO4 channel mode + G2_IO4: u1 = 0, + /// G3_IO1 channel mode + G3_IO1: u1 = 0, + /// G3_IO2 channel mode + G3_IO2: u1 = 0, + /// G3_IO3 channel mode + G3_IO3: u1 = 0, + /// G3_IO4 channel mode + G3_IO4: u1 = 0, + /// G4_IO1 channel mode + G4_IO1: u1 = 0, + /// G4_IO2 channel mode + G4_IO2: u1 = 0, + /// G4_IO3 channel mode + G4_IO3: u1 = 0, + /// G4_IO4 channel mode + G4_IO4: u1 = 0, + /// G5_IO1 channel mode + G5_IO1: u1 = 0, + /// G5_IO2 channel mode + G5_IO2: u1 = 0, + /// G5_IO3 channel mode + G5_IO3: u1 = 0, + /// G5_IO4 channel mode + G5_IO4: u1 = 0, + /// G6_IO1 channel mode + G6_IO1: u1 = 0, + /// G6_IO2 channel mode + G6_IO2: u1 = 0, + /// G6_IO3 channel mode + G6_IO3: u1 = 0, + /// G6_IO4 channel mode + G6_IO4: u1 = 0, + /// G7_IO1 channel mode + G7_IO1: u1 = 0, + /// G7_IO2 channel mode + G7_IO2: u1 = 0, + /// G7_IO3 channel mode + G7_IO3: u1 = 0, + /// G7_IO4 channel mode + G7_IO4: u1 = 0, + /// G8_IO1 channel mode + G8_IO1: u1 = 0, + /// G8_IO2 channel mode + G8_IO2: u1 = 0, + /// G8_IO3 channel mode + G8_IO3: u1 = 0, + /// G8_IO4 channel mode + G8_IO4: u1 = 0, + }); + + /// I/O group control status register pub const IOGCSR = mmio(Address + 0x00000030, 32, packed struct { - G1E: u1, // bit offset: 0 desc: Analog I/O group x enable - G2E: u1, // bit offset: 1 desc: Analog I/O group x enable - G3E: u1, // bit offset: 2 desc: Analog I/O group x enable - G4E: u1, // bit offset: 3 desc: Analog I/O group x enable - G5E: u1, // bit offset: 4 desc: Analog I/O group x enable - G6E: u1, // bit offset: 5 desc: Analog I/O group x enable - G7E: u1, // bit offset: 6 desc: Analog I/O group x enable - G8E: u1, // bit offset: 7 desc: Analog I/O group x enable + /// Analog I/O group x enable + G1E: u1 = 0, + /// Analog I/O group x enable + G2E: u1 = 0, + /// Analog I/O group x enable + G3E: u1 = 0, + /// Analog I/O group x enable + G4E: u1 = 0, + /// Analog I/O group x enable + G5E: u1 = 0, + /// Analog I/O group x enable + G6E: u1 = 0, + /// Analog I/O group x enable + G7E: u1 = 0, + /// Analog I/O group x enable + G8E: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -2623,14 +4310,22 @@ pub const TSC = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - G1S: u1, // bit offset: 16 desc: Analog I/O group x status - G2S: u1, // bit offset: 17 desc: Analog I/O group x status - G3S: u1, // bit offset: 18 desc: Analog I/O group x status - G4S: u1, // bit offset: 19 desc: Analog I/O group x status - G5S: u1, // bit offset: 20 desc: Analog I/O group x status - G6S: u1, // bit offset: 21 desc: Analog I/O group x status - G7S: u1, // bit offset: 22 desc: Analog I/O group x status - G8S: u1, // bit offset: 23 desc: Analog I/O group x status + /// Analog I/O group x status + G1S: u1 = 0, + /// Analog I/O group x status + G2S: u1 = 0, + /// Analog I/O group x status + G3S: u1 = 0, + /// Analog I/O group x status + G4S: u1 = 0, + /// Analog I/O group x status + G5S: u1 = 0, + /// Analog I/O group x status + G6S: u1 = 0, + /// Analog I/O group x status + G7S: u1 = 0, + /// Analog I/O group x status + G8S: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -2640,9 +4335,11 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 I/O group x counter register + + /// I/O group x counter register pub const IOG1CR = mmio(Address + 0x00000034, 32, packed struct { - CNT: u14, // bit offset: 0 desc: Counter value + /// Counter value + CNT: u14 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -2662,9 +4359,11 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 I/O group x counter register + + /// I/O group x counter register pub const IOG2CR = mmio(Address + 0x00000038, 32, packed struct { - CNT: u14, // bit offset: 0 desc: Counter value + /// Counter value + CNT: u14 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -2684,9 +4383,11 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 I/O group x counter register + + /// I/O group x counter register pub const IOG3CR = mmio(Address + 0x0000003c, 32, packed struct { - CNT: u14, // bit offset: 0 desc: Counter value + /// Counter value + CNT: u14 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -2706,9 +4407,11 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 I/O group x counter register + + /// I/O group x counter register pub const IOG4CR = mmio(Address + 0x00000040, 32, packed struct { - CNT: u14, // bit offset: 0 desc: Counter value + /// Counter value + CNT: u14 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -2728,9 +4431,11 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 I/O group x counter register + + /// I/O group x counter register pub const IOG5CR = mmio(Address + 0x00000044, 32, packed struct { - CNT: u14, // bit offset: 0 desc: Counter value + /// Counter value + CNT: u14 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -2750,9 +4455,11 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 I/O group x counter register + + /// I/O group x counter register pub const IOG6CR = mmio(Address + 0x00000048, 32, packed struct { - CNT: u14, // bit offset: 0 desc: Counter value + /// Counter value + CNT: u14 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -2772,9 +4479,11 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 I/O group x counter register + + /// I/O group x counter register pub const IOG7CR = mmio(Address + 0x0000004c, 32, packed struct { - CNT: u14, // bit offset: 0 desc: Counter value + /// Counter value + CNT: u14 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -2794,9 +4503,11 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 80 I/O group x counter register + + /// I/O group x counter register pub const IOG8CR = mmio(Address + 0x00000050, 32, packed struct { - CNT: u14, // bit offset: 0 desc: Counter value + /// Counter value + CNT: u14 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -2817,15 +4528,18 @@ pub const TSC = extern struct { padding1: u1 = 0, }); }; + +/// cyclic redundancy check calculation unit pub const CRC = extern struct { pub const Address: u32 = 0x40023000; - // byte offset: 0 Data register - pub const DR = mmio(Address + 0x00000000, 32, packed struct { - DR: u32, // bit offset: 0 desc: Data register bits - }); - // byte offset: 4 Independent data register + + /// Data register + pub const DR = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Independent data register pub const IDR = mmio(Address + 0x00000004, 32, packed struct { - IDR: u8, // bit offset: 0 desc: General-purpose 8-bit data register bits + /// General-purpose 8-bit data register bits + IDR: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -2851,14 +4565,19 @@ pub const CRC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Control register + + /// Control register pub const CR = mmio(Address + 0x00000008, 32, packed struct { - RESET: u1, // bit offset: 0 desc: reset bit + /// reset bit + RESET: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - POLYSIZE: u2, // bit offset: 3 desc: Polynomial size - REV_IN: u2, // bit offset: 5 desc: Reverse input data - REV_OUT: u1, // bit offset: 7 desc: Reverse output data + /// Polynomial size + POLYSIZE: u2 = 0, + /// Reverse input data + REV_IN: u2 = 0, + /// Reverse output data + REV_OUT: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -2884,23 +4603,21 @@ pub const CRC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Initial CRC value - pub const INIT = mmio(Address + 0x00000010, 32, packed struct { - INIT: u32, // bit offset: 0 desc: Programmable initial CRC value - }); - // byte offset: 20 CRC polynomial - pub const POL = mmio(Address + 0x00000014, 32, packed struct { - POL: u32, // bit offset: 0 desc: Programmable polynomial - }); + + /// Initial CRC value + pub const INIT = @intToPtr(*volatile u32, Address + 0x00000010); + + /// CRC polynomial + pub const POL = @intToPtr(*volatile u32, Address + 0x00000014); }; + +/// Flash pub const Flash = extern struct { pub const Address: u32 = 0x40022000; - // byte offset: 0 Flash access control register + + /// Flash access control register pub const ACR = mmio(Address + 0x00000000, 32, packed struct { - LATENCY: u3, // bit offset: 0 desc: LATENCY reserved1: u1 = 0, - PRFTBE: u1, // bit offset: 4 desc: PRFTBE - PRFTBS: u1, // bit offset: 5 desc: PRFTBS padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -2928,22 +4645,28 @@ pub const Flash = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Flash key register + + /// Flash key register pub const KEYR = mmio(Address + 0x00000004, 32, packed struct { - FKEYR: u32, // bit offset: 0 desc: Flash Key + /// Flash Key + FKEYR: u32 = 0, }); - // byte offset: 8 Flash option key register - pub const OPTKEYR = mmio(Address + 0x00000008, 32, packed struct { - OPTKEYR: u32, // bit offset: 0 desc: Option byte key - }); - // byte offset: 12 Flash status register + + /// Flash option key register + pub const OPTKEYR = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Flash status register pub const SR = mmio(Address + 0x0000000c, 32, packed struct { - BSY: u1, // bit offset: 0 desc: Busy + /// Busy + BSY: u1 = 0, reserved1: u1 = 0, - PGERR: u1, // bit offset: 2 desc: Programming error + /// Programming error + PGERR: u1 = 0, reserved2: u1 = 0, - WRPRT: u1, // bit offset: 4 desc: Write protection error - EOP: u1, // bit offset: 5 desc: End of operation + /// Write protection error + WRPRT: u1 = 0, + /// End of operation + EOP: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -2971,22 +4694,34 @@ pub const Flash = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Flash control register + + /// Flash control register pub const CR = mmio(Address + 0x00000010, 32, packed struct { - PG: u1, // bit offset: 0 desc: Programming - PER: u1, // bit offset: 1 desc: Page erase - MER: u1, // bit offset: 2 desc: Mass erase - reserved1: u1 = 0, - OPTPG: u1, // bit offset: 4 desc: Option byte programming - OPTER: u1, // bit offset: 5 desc: Option byte erase - STRT: u1, // bit offset: 6 desc: Start - LOCK: u1, // bit offset: 7 desc: Lock - reserved2: u1 = 0, - OPTWRE: u1, // bit offset: 9 desc: Option bytes write enable - ERRIE: u1, // bit offset: 10 desc: Error interrupt enable + /// Programming + PG: u1 = 0, + /// Page erase + PER: u1 = 0, + /// Mass erase + MER: u1 = 0, + reserved1: u1 = 0, + /// Option byte programming + OPTPG: u1 = 0, + /// Option byte erase + OPTER: u1 = 0, + /// Start + STRT: u1 = 0, + /// Lock + LOCK: u1 = 0, + reserved2: u1 = 0, + /// Option bytes write enable + OPTWRE: u1 = 0, + /// Error interrupt enable + ERRIE: u1 = 0, reserved3: u1 = 0, - EOPIE: u1, // bit offset: 12 desc: End of operation interrupt enable - FORCE_OPTLOAD: u1, // bit offset: 13 desc: Force option byte loading + /// End of operation interrupt enable + EOPIE: u1 = 0, + /// Force option byte loading + FORCE_OPTLOAD: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -3006,55 +4741,68 @@ pub const Flash = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Flash address register + + /// Flash address register pub const AR = mmio(Address + 0x00000014, 32, packed struct { - FAR: u32, // bit offset: 0 desc: Flash address + /// Flash address + FAR: u32 = 0, }); - // byte offset: 28 Option byte register + + /// Option byte register pub const OBR = mmio(Address + 0x0000001c, 32, packed struct { - OPTERR: u1, // bit offset: 0 desc: Option byte error - LEVEL1_PROT: u1, // bit offset: 1 desc: Level 1 protection status - LEVEL2_PROT: u1, // bit offset: 2 desc: Level 2 protection status + /// Option byte error + OPTERR: u1 = 0, + /// Level 1 protection status + LEVEL1_PROT: u1 = 0, + /// Level 2 protection status + LEVEL2_PROT: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - WDG_SW: u1, // bit offset: 8 desc: WDG_SW - nRST_STOP: u1, // bit offset: 9 desc: nRST_STOP - nRST_STDBY: u1, // bit offset: 10 desc: nRST_STDBY reserved6: u1 = 0, - BOOT1: u1, // bit offset: 12 desc: BOOT1 - VDDA_MONITOR: u1, // bit offset: 13 desc: VDDA_MONITOR - SRAM_PARITY_CHECK: u1, // bit offset: 14 desc: SRAM_PARITY_CHECK reserved7: u1 = 0, - Data0: u8, // bit offset: 16 desc: Data0 - Data1: u8, // bit offset: 24 desc: Data1 }); - // byte offset: 32 Write protection register + + /// Write protection register pub const WRPR = mmio(Address + 0x00000020, 32, packed struct { - WRP: u32, // bit offset: 0 desc: Write protect + /// Write protect + WRP: u32 = 0, }); }; + +/// Reset and clock control pub const RCC = extern struct { pub const Address: u32 = 0x40021000; - // byte offset: 0 Clock control register + + /// Clock control register pub const CR = mmio(Address + 0x00000000, 32, packed struct { - HSION: u1, // bit offset: 0 desc: Internal High Speed clock enable - HSIRDY: u1, // bit offset: 1 desc: Internal High Speed clock ready flag - reserved1: u1 = 0, - HSITRIM: u5, // bit offset: 3 desc: Internal High Speed clock trimming - HSICAL: u8, // bit offset: 8 desc: Internal High Speed clock Calibration - HSEON: u1, // bit offset: 16 desc: External High Speed clock enable - HSERDY: u1, // bit offset: 17 desc: External High Speed clock ready flag - HSEBYP: u1, // bit offset: 18 desc: External High Speed clock Bypass - CSSON: u1, // bit offset: 19 desc: Clock Security System enable + /// Internal High Speed clock enable + HSION: u1 = 0, + /// Internal High Speed clock ready flag + HSIRDY: u1 = 0, + reserved1: u1 = 0, + /// Internal High Speed clock trimming + HSITRIM: u5 = 0, + /// Internal High Speed clock Calibration + HSICAL: u8 = 0, + /// External High Speed clock enable + HSEON: u1 = 0, + /// External High Speed clock ready flag + HSERDY: u1 = 0, + /// External High Speed clock Bypass + HSEBYP: u1 = 0, + /// Clock Security System enable + CSSON: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - PLLON: u1, // bit offset: 24 desc: PLL enable - PLLRDY: u1, // bit offset: 25 desc: PLL clock ready flag + /// PLL enable + PLLON: u1 = 0, + /// PLL clock ready flag + PLLRDY: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, @@ -3062,52 +4810,83 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Clock configuration register (RCC_CFGR) + + /// Clock configuration register (RCC_CFGR) pub const CFGR = mmio(Address + 0x00000004, 32, packed struct { - SW: u2, // bit offset: 0 desc: System clock Switch - SWS: u2, // bit offset: 2 desc: System Clock Switch Status - HPRE: u4, // bit offset: 4 desc: AHB prescaler - PPRE1: u3, // bit offset: 8 desc: APB Low speed prescaler (APB1) - PPRE2: u3, // bit offset: 11 desc: APB high speed prescaler (APB2) - reserved1: u1 = 0, - PLLSRC: u2, // bit offset: 15 desc: PLL entry clock source - PLLXTPRE: u1, // bit offset: 17 desc: HSE divider for PLL entry - PLLMUL: u4, // bit offset: 18 desc: PLL Multiplication Factor - USBPRES: u1, // bit offset: 22 desc: USB prescaler - I2SSRC: u1, // bit offset: 23 desc: I2S external clock source selection - MCO: u3, // bit offset: 24 desc: Microcontroller clock output - reserved2: u1 = 0, - MCOF: u1, // bit offset: 28 desc: Microcontroller Clock Output Flag + /// System clock Switch + SW: u2 = 0, + /// System Clock Switch Status + SWS: u2 = 0, + /// AHB prescaler + HPRE: u4 = 0, + /// APB Low speed prescaler (APB1) + PPRE1: u3 = 0, + /// APB high speed prescaler (APB2) + PPRE2: u3 = 0, + reserved1: u1 = 0, + /// PLL entry clock source + PLLSRC: u2 = 0, + /// HSE divider for PLL entry + PLLXTPRE: u1 = 0, + /// PLL Multiplication Factor + PLLMUL: u4 = 0, + /// USB prescaler + USBPRES: u1 = 0, + /// I2S external clock source selection + I2SSRC: u1 = 0, + /// Microcontroller clock output + MCO: u3 = 0, + reserved2: u1 = 0, + /// Microcontroller Clock Output Flag + MCOF: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Clock interrupt register (RCC_CIR) + + /// Clock interrupt register (RCC_CIR) pub const CIR = mmio(Address + 0x00000008, 32, packed struct { - LSIRDYF: u1, // bit offset: 0 desc: LSI Ready Interrupt flag - LSERDYF: u1, // bit offset: 1 desc: LSE Ready Interrupt flag - HSIRDYF: u1, // bit offset: 2 desc: HSI Ready Interrupt flag - HSERDYF: u1, // bit offset: 3 desc: HSE Ready Interrupt flag - PLLRDYF: u1, // bit offset: 4 desc: PLL Ready Interrupt flag - reserved2: u1 = 0, - reserved1: u1 = 0, - CSSF: u1, // bit offset: 7 desc: Clock Security System Interrupt flag - LSIRDYIE: u1, // bit offset: 8 desc: LSI Ready Interrupt Enable - LSERDYIE: u1, // bit offset: 9 desc: LSE Ready Interrupt Enable - HSIRDYIE: u1, // bit offset: 10 desc: HSI Ready Interrupt Enable - HSERDYIE: u1, // bit offset: 11 desc: HSE Ready Interrupt Enable - PLLRDYIE: u1, // bit offset: 12 desc: PLL Ready Interrupt Enable + /// LSI Ready Interrupt flag + LSIRDYF: u1 = 0, + /// LSE Ready Interrupt flag + LSERDYF: u1 = 0, + /// HSI Ready Interrupt flag + HSIRDYF: u1 = 0, + /// HSE Ready Interrupt flag + HSERDYF: u1 = 0, + /// PLL Ready Interrupt flag + PLLRDYF: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Clock Security System Interrupt flag + CSSF: u1 = 0, + /// LSI Ready Interrupt Enable + LSIRDYIE: u1 = 0, + /// LSE Ready Interrupt Enable + LSERDYIE: u1 = 0, + /// HSI Ready Interrupt Enable + HSIRDYIE: u1 = 0, + /// HSE Ready Interrupt Enable + HSERDYIE: u1 = 0, + /// PLL Ready Interrupt Enable + PLLRDYIE: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - LSIRDYC: u1, // bit offset: 16 desc: LSI Ready Interrupt Clear - LSERDYC: u1, // bit offset: 17 desc: LSE Ready Interrupt Clear - HSIRDYC: u1, // bit offset: 18 desc: HSI Ready Interrupt Clear - HSERDYC: u1, // bit offset: 19 desc: HSE Ready Interrupt Clear - PLLRDYC: u1, // bit offset: 20 desc: PLL Ready Interrupt Clear + /// LSI Ready Interrupt Clear + LSIRDYC: u1 = 0, + /// LSE Ready Interrupt Clear + LSERDYC: u1 = 0, + /// HSI Ready Interrupt Clear + HSIRDYC: u1 = 0, + /// HSE Ready Interrupt Clear + HSERDYC: u1 = 0, + /// PLL Ready Interrupt Clear + PLLRDYC: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, - CSSC: u1, // bit offset: 23 desc: Clock security system interrupt clear + /// Clock security system interrupt clear + CSSC: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -3117,9 +4896,11 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 APB2 peripheral reset register (RCC_APB2RSTR) + + /// APB2 peripheral reset register (RCC_APB2RSTR) pub const APB2RSTR = mmio(Address + 0x0000000c, 32, packed struct { - SYSCFGRST: u1, // bit offset: 0 desc: SYSCFG and COMP reset + /// SYSCFG and COMP reset + SYSCFGRST: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, @@ -3130,14 +4911,21 @@ pub const RCC = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TIM1RST: u1, // bit offset: 11 desc: TIM1 timer reset - SPI1RST: u1, // bit offset: 12 desc: SPI 1 reset - TIM8RST: u1, // bit offset: 13 desc: TIM8 timer reset - USART1RST: u1, // bit offset: 14 desc: USART1 reset + /// TIM1 timer reset + TIM1RST: u1 = 0, + /// SPI 1 reset + SPI1RST: u1 = 0, + /// TIM8 timer reset + TIM8RST: u1 = 0, + /// USART1 reset + USART1RST: u1 = 0, reserved11: u1 = 0, - TIM15RST: u1, // bit offset: 16 desc: TIM15 timer reset - TIM16RST: u1, // bit offset: 17 desc: TIM16 timer reset - TIM17RST: u1, // bit offset: 18 desc: TIM17 timer reset + /// TIM15 timer reset + TIM15RST: u1 = 0, + /// TIM16 timer reset + TIM16RST: u1 = 0, + /// TIM17 timer reset + TIM17RST: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -3152,50 +4940,77 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 APB1 peripheral reset register (RCC_APB1RSTR) + + /// APB1 peripheral reset register (RCC_APB1RSTR) pub const APB1RSTR = mmio(Address + 0x00000010, 32, packed struct { - TIM2RST: u1, // bit offset: 0 desc: Timer 2 reset - TIM3RST: u1, // bit offset: 1 desc: Timer 3 reset - TIM4RST: u1, // bit offset: 2 desc: Timer 14 reset - reserved1: u1 = 0, - TIM6RST: u1, // bit offset: 4 desc: Timer 6 reset - TIM7RST: u1, // bit offset: 5 desc: Timer 7 reset + /// Timer 2 reset + TIM2RST: u1 = 0, + /// Timer 3 reset + TIM3RST: u1 = 0, + /// Timer 14 reset + TIM4RST: u1 = 0, + reserved1: u1 = 0, + /// Timer 6 reset + TIM6RST: u1 = 0, + /// Timer 7 reset + TIM7RST: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - WWDGRST: u1, // bit offset: 11 desc: Window watchdog reset + /// Window watchdog reset + WWDGRST: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, - SPI2RST: u1, // bit offset: 14 desc: SPI2 reset - SPI3RST: u1, // bit offset: 15 desc: SPI3 reset + /// SPI2 reset + SPI2RST: u1 = 0, + /// SPI3 reset + SPI3RST: u1 = 0, reserved9: u1 = 0, - USART2RST: u1, // bit offset: 17 desc: USART 2 reset - USART3RST: u1, // bit offset: 18 desc: USART3 reset - UART4RST: u1, // bit offset: 19 desc: UART 4 reset - UART5RST: u1, // bit offset: 20 desc: UART 5 reset - I2C1RST: u1, // bit offset: 21 desc: I2C1 reset - I2C2RST: u1, // bit offset: 22 desc: I2C2 reset - USBRST: u1, // bit offset: 23 desc: USB reset + /// USART 2 reset + USART2RST: u1 = 0, + /// USART3 reset + USART3RST: u1 = 0, + /// UART 4 reset + UART4RST: u1 = 0, + /// UART 5 reset + UART5RST: u1 = 0, + /// I2C1 reset + I2C1RST: u1 = 0, + /// I2C2 reset + I2C2RST: u1 = 0, + /// USB reset + USBRST: u1 = 0, reserved10: u1 = 0, - CANRST: u1, // bit offset: 25 desc: CAN reset + /// CAN reset + CANRST: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, - PWRRST: u1, // bit offset: 28 desc: Power interface reset - DACRST: u1, // bit offset: 29 desc: DAC interface reset - I2C3RST: u1, // bit offset: 30 desc: I2C3 reset + /// Power interface reset + PWRRST: u1 = 0, + /// DAC interface reset + DACRST: u1 = 0, + /// I2C3 reset + I2C3RST: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 AHB Peripheral Clock enable register (RCC_AHBENR) + + /// AHB Peripheral Clock enable register (RCC_AHBENR) pub const AHBENR = mmio(Address + 0x00000014, 32, packed struct { - DMAEN: u1, // bit offset: 0 desc: DMA1 clock enable - DMA2EN: u1, // bit offset: 1 desc: DMA2 clock enable - SRAMEN: u1, // bit offset: 2 desc: SRAM interface clock enable - reserved1: u1 = 0, - FLITFEN: u1, // bit offset: 4 desc: FLITF clock enable - FMCEN: u1, // bit offset: 5 desc: FMC clock enable - CRCEN: u1, // bit offset: 6 desc: CRC clock enable + /// DMA1 clock enable + DMAEN: u1 = 0, + /// DMA2 clock enable + DMA2EN: u1 = 0, + /// SRAM interface clock enable + SRAMEN: u1 = 0, + reserved1: u1 = 0, + /// FLITF clock enable + FLITFEN: u1 = 0, + /// FMC clock enable + FMCEN: u1 = 0, + /// CRC clock enable + CRCEN: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, @@ -3205,26 +5020,39 @@ pub const RCC = extern struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - IOPHEN: u1, // bit offset: 16 desc: IO port H clock enable - IOPAEN: u1, // bit offset: 17 desc: I/O port A clock enable - IOPBEN: u1, // bit offset: 18 desc: I/O port B clock enable - IOPCEN: u1, // bit offset: 19 desc: I/O port C clock enable - IOPDEN: u1, // bit offset: 20 desc: I/O port D clock enable - IOPEEN: u1, // bit offset: 21 desc: I/O port E clock enable - IOPFEN: u1, // bit offset: 22 desc: I/O port F clock enable - IOPGEN: u1, // bit offset: 23 desc: I/O port G clock enable - TSCEN: u1, // bit offset: 24 desc: Touch sensing controller clock enable + /// IO port H clock enable + IOPHEN: u1 = 0, + /// I/O port A clock enable + IOPAEN: u1 = 0, + /// I/O port B clock enable + IOPBEN: u1 = 0, + /// I/O port C clock enable + IOPCEN: u1 = 0, + /// I/O port D clock enable + IOPDEN: u1 = 0, + /// I/O port E clock enable + IOPEEN: u1 = 0, + /// I/O port F clock enable + IOPFEN: u1 = 0, + /// I/O port G clock enable + IOPGEN: u1 = 0, + /// Touch sensing controller clock enable + TSCEN: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, - ADC12EN: u1, // bit offset: 28 desc: ADC1 and ADC2 clock enable - ADC34EN: u1, // bit offset: 29 desc: ADC3 and ADC4 clock enable + /// ADC1 and ADC2 clock enable + ADC12EN: u1 = 0, + /// ADC3 and ADC4 clock enable + ADC34EN: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 APB2 peripheral clock enable register (RCC_APB2ENR) + + /// APB2 peripheral clock enable register (RCC_APB2ENR) pub const APB2ENR = mmio(Address + 0x00000018, 32, packed struct { - SYSCFGEN: u1, // bit offset: 0 desc: SYSCFG clock enable + /// SYSCFG clock enable + SYSCFGEN: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, @@ -3235,14 +5063,21 @@ pub const RCC = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TIM1EN: u1, // bit offset: 11 desc: TIM1 Timer clock enable - SPI1EN: u1, // bit offset: 12 desc: SPI 1 clock enable - TIM8EN: u1, // bit offset: 13 desc: TIM8 Timer clock enable - USART1EN: u1, // bit offset: 14 desc: USART1 clock enable + /// TIM1 Timer clock enable + TIM1EN: u1 = 0, + /// SPI 1 clock enable + SPI1EN: u1 = 0, + /// TIM8 Timer clock enable + TIM8EN: u1 = 0, + /// USART1 clock enable + USART1EN: u1 = 0, reserved11: u1 = 0, - TIM15EN: u1, // bit offset: 16 desc: TIM15 timer clock enable - TIM16EN: u1, // bit offset: 17 desc: TIM16 timer clock enable - TIM17EN: u1, // bit offset: 18 desc: TIM17 timer clock enable + /// TIM15 timer clock enable + TIM15EN: u1 = 0, + /// TIM16 timer clock enable + TIM16EN: u1 = 0, + /// TIM17 timer clock enable + TIM17EN: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -3257,58 +5092,87 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 APB1 peripheral clock enable register (RCC_APB1ENR) + + /// APB1 peripheral clock enable register (RCC_APB1ENR) pub const APB1ENR = mmio(Address + 0x0000001c, 32, packed struct { - TIM2EN: u1, // bit offset: 0 desc: Timer 2 clock enable - TIM3EN: u1, // bit offset: 1 desc: Timer 3 clock enable - TIM4EN: u1, // bit offset: 2 desc: Timer 4 clock enable - reserved1: u1 = 0, - TIM6EN: u1, // bit offset: 4 desc: Timer 6 clock enable - TIM7EN: u1, // bit offset: 5 desc: Timer 7 clock enable + /// Timer 2 clock enable + TIM2EN: u1 = 0, + /// Timer 3 clock enable + TIM3EN: u1 = 0, + /// Timer 4 clock enable + TIM4EN: u1 = 0, + reserved1: u1 = 0, + /// Timer 6 clock enable + TIM6EN: u1 = 0, + /// Timer 7 clock enable + TIM7EN: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - WWDGEN: u1, // bit offset: 11 desc: Window watchdog clock enable + /// Window watchdog clock enable + WWDGEN: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, - SPI2EN: u1, // bit offset: 14 desc: SPI 2 clock enable - SPI3EN: u1, // bit offset: 15 desc: SPI 3 clock enable + /// SPI 2 clock enable + SPI2EN: u1 = 0, + /// SPI 3 clock enable + SPI3EN: u1 = 0, reserved9: u1 = 0, - USART2EN: u1, // bit offset: 17 desc: USART 2 clock enable - USART3EN: u1, // bit offset: 18 desc: USART 3 clock enable - USART4EN: u1, // bit offset: 19 desc: USART 4 clock enable - USART5EN: u1, // bit offset: 20 desc: USART 5 clock enable - I2C1EN: u1, // bit offset: 21 desc: I2C 1 clock enable - I2C2EN: u1, // bit offset: 22 desc: I2C 2 clock enable - USBEN: u1, // bit offset: 23 desc: USB clock enable + /// USART 2 clock enable + USART2EN: u1 = 0, + /// USART 3 clock enable + USART3EN: u1 = 0, + /// USART 4 clock enable + USART4EN: u1 = 0, + /// USART 5 clock enable + USART5EN: u1 = 0, + /// I2C 1 clock enable + I2C1EN: u1 = 0, + /// I2C 2 clock enable + I2C2EN: u1 = 0, + /// USB clock enable + USBEN: u1 = 0, reserved10: u1 = 0, - CANEN: u1, // bit offset: 25 desc: CAN clock enable - DAC2EN: u1, // bit offset: 26 desc: DAC2 interface clock enable + /// CAN clock enable + CANEN: u1 = 0, + /// DAC2 interface clock enable + DAC2EN: u1 = 0, reserved11: u1 = 0, - PWREN: u1, // bit offset: 28 desc: Power interface clock enable - DACEN: u1, // bit offset: 29 desc: DAC interface clock enable - I2C3EN: u1, // bit offset: 30 desc: I2C3 clock enable + /// Power interface clock enable + PWREN: u1 = 0, + /// DAC interface clock enable + DACEN: u1 = 0, + /// I2C3 clock enable + I2C3EN: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 Backup domain control register (RCC_BDCR) + + /// Backup domain control register (RCC_BDCR) pub const BDCR = mmio(Address + 0x00000020, 32, packed struct { - LSEON: u1, // bit offset: 0 desc: External Low Speed oscillator enable - LSERDY: u1, // bit offset: 1 desc: External Low Speed oscillator ready - LSEBYP: u1, // bit offset: 2 desc: External Low Speed oscillator bypass - LSEDRV: u2, // bit offset: 3 desc: LSE oscillator drive capability + /// External Low Speed oscillator enable + LSEON: u1 = 0, + /// External Low Speed oscillator ready + LSERDY: u1 = 0, + /// External Low Speed oscillator bypass + LSEBYP: u1 = 0, + /// LSE oscillator drive capability + LSEDRV: u2 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - RTCSEL: u2, // bit offset: 8 desc: RTC clock source selection + /// RTC clock source selection + RTCSEL: u2 = 0, reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - RTCEN: u1, // bit offset: 15 desc: RTC clock enable - BDRST: u1, // bit offset: 16 desc: Backup domain software reset + /// RTC clock enable + RTCEN: u1 = 0, + /// Backup domain software reset + BDRST: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -3325,10 +5189,13 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 Control/status register (RCC_CSR) + + /// Control/status register (RCC_CSR) pub const CSR = mmio(Address + 0x00000024, 32, packed struct { - LSION: u1, // bit offset: 0 desc: Internal low speed oscillator enable - LSIRDY: u1, // bit offset: 1 desc: Internal low speed oscillator ready + /// Internal low speed oscillator enable + LSION: u1 = 0, + /// Internal low speed oscillator ready + LSIRDY: u1 = 0, reserved22: u1 = 0, reserved21: u1 = 0, reserved20: u1 = 0, @@ -3351,23 +5218,33 @@ pub const RCC = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - RMVF: u1, // bit offset: 24 desc: Remove reset flag - OBLRSTF: u1, // bit offset: 25 desc: Option byte loader reset flag - PINRSTF: u1, // bit offset: 26 desc: PIN reset flag - PORRSTF: u1, // bit offset: 27 desc: POR/PDR reset flag - SFTRSTF: u1, // bit offset: 28 desc: Software reset flag - IWDGRSTF: u1, // bit offset: 29 desc: Independent watchdog reset flag - WWDGRSTF: u1, // bit offset: 30 desc: Window watchdog reset flag - LPWRRSTF: u1, // bit offset: 31 desc: Low-power reset flag + /// Remove reset flag + RMVF: u1 = 0, + /// Option byte loader reset flag + OBLRSTF: u1 = 0, + /// PIN reset flag + PINRSTF: u1 = 0, + /// POR/PDR reset flag + PORRSTF: u1 = 0, + /// Software reset flag + SFTRSTF: u1 = 0, + /// Independent watchdog reset flag + IWDGRSTF: u1 = 0, + /// Window watchdog reset flag + WWDGRSTF: u1 = 0, + /// Low-power reset flag + LPWRRSTF: u1 = 0, }); - // byte offset: 40 AHB peripheral reset register + + /// AHB peripheral reset register pub const AHBRSTR = mmio(Address + 0x00000028, 32, packed struct { reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - FMCRST: u1, // bit offset: 5 desc: FMC reset + /// FMC reset + FMCRST: u1 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, @@ -3378,28 +5255,43 @@ pub const RCC = extern struct { reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, - IOPHRST: u1, // bit offset: 16 desc: I/O port H reset - IOPARST: u1, // bit offset: 17 desc: I/O port A reset - IOPBRST: u1, // bit offset: 18 desc: I/O port B reset - IOPCRST: u1, // bit offset: 19 desc: I/O port C reset - IOPDRST: u1, // bit offset: 20 desc: I/O port D reset - IOPERST: u1, // bit offset: 21 desc: I/O port E reset - IOPFRST: u1, // bit offset: 22 desc: I/O port F reset - IOPGRST: u1, // bit offset: 23 desc: Touch sensing controller reset - TSCRST: u1, // bit offset: 24 desc: Touch sensing controller reset + /// I/O port H reset + IOPHRST: u1 = 0, + /// I/O port A reset + IOPARST: u1 = 0, + /// I/O port B reset + IOPBRST: u1 = 0, + /// I/O port C reset + IOPCRST: u1 = 0, + /// I/O port D reset + IOPDRST: u1 = 0, + /// I/O port E reset + IOPERST: u1 = 0, + /// I/O port F reset + IOPFRST: u1 = 0, + /// Touch sensing controller reset + IOPGRST: u1 = 0, + /// Touch sensing controller reset + TSCRST: u1 = 0, reserved18: u1 = 0, reserved17: u1 = 0, reserved16: u1 = 0, - ADC12RST: u1, // bit offset: 28 desc: ADC1 and ADC2 reset - ADC34RST: u1, // bit offset: 29 desc: ADC3 and ADC4 reset + /// ADC1 and ADC2 reset + ADC12RST: u1 = 0, + /// ADC3 and ADC4 reset + ADC34RST: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 Clock configuration register 2 + + /// Clock configuration register 2 pub const CFGR2 = mmio(Address + 0x0000002c, 32, packed struct { - PREDIV: u4, // bit offset: 0 desc: PREDIV division factor - ADC12PRES: u5, // bit offset: 4 desc: ADC1 and ADC2 prescaler - ADC34PRES: u5, // bit offset: 9 desc: ADC3 and ADC4 prescaler + /// PREDIV division factor + PREDIV: u4 = 0, + /// ADC1 and ADC2 prescaler + ADC12PRES: u5 = 0, + /// ADC3 and ADC4 prescaler + ADC34PRES: u5 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -3419,27 +5311,38 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 Clock configuration register 3 + + /// Clock configuration register 3 pub const CFGR3 = mmio(Address + 0x00000030, 32, packed struct { - USART1SW: u2, // bit offset: 0 desc: USART1 clock source selection + /// USART1 clock source selection + USART1SW: u2 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - I2C1SW: u1, // bit offset: 4 desc: I2C1 clock source selection - I2C2SW: u1, // bit offset: 5 desc: I2C2 clock source selection - I2C3SW: u1, // bit offset: 6 desc: I2C3 clock source selection + /// I2C1 clock source selection + I2C1SW: u1 = 0, + /// I2C2 clock source selection + I2C2SW: u1 = 0, + /// I2C3 clock source selection + I2C3SW: u1 = 0, reserved3: u1 = 0, - TIM1SW: u1, // bit offset: 8 desc: Timer1 clock source selection - TIM8SW: u1, // bit offset: 9 desc: Timer8 clock source selection + /// Timer1 clock source selection + TIM1SW: u1 = 0, + /// Timer8 clock source selection + TIM8SW: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - USART2SW: u2, // bit offset: 16 desc: USART2 clock source selection - USART3SW: u2, // bit offset: 18 desc: USART3 clock source selection - UART4SW: u2, // bit offset: 20 desc: UART4 clock source selection - UART5SW: u2, // bit offset: 22 desc: UART5 clock source selection + /// USART2 clock source selection + USART2SW: u2 = 0, + /// USART3 clock source selection + USART3SW: u2 = 0, + /// UART4 clock source selection + UART4SW: u2 = 0, + /// UART5 clock source selection + UART5SW: u2 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -3450,92 +5353,165 @@ pub const RCC = extern struct { padding1: u1 = 0, }); }; + +/// DMA controller 1 pub const DMA1 = extern struct { pub const Address: u32 = 0x40020000; - // byte offset: 0 DMA interrupt status register (DMA_ISR) + + /// DMA interrupt status register (DMA_ISR) pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - GIF1: u1, // bit offset: 0 desc: Channel 1 Global interrupt flag - TCIF1: u1, // bit offset: 1 desc: Channel 1 Transfer Complete flag - HTIF1: u1, // bit offset: 2 desc: Channel 1 Half Transfer Complete flag - TEIF1: u1, // bit offset: 3 desc: Channel 1 Transfer Error flag - GIF2: u1, // bit offset: 4 desc: Channel 2 Global interrupt flag - TCIF2: u1, // bit offset: 5 desc: Channel 2 Transfer Complete flag - HTIF2: u1, // bit offset: 6 desc: Channel 2 Half Transfer Complete flag - TEIF2: u1, // bit offset: 7 desc: Channel 2 Transfer Error flag - GIF3: u1, // bit offset: 8 desc: Channel 3 Global interrupt flag - TCIF3: u1, // bit offset: 9 desc: Channel 3 Transfer Complete flag - HTIF3: u1, // bit offset: 10 desc: Channel 3 Half Transfer Complete flag - TEIF3: u1, // bit offset: 11 desc: Channel 3 Transfer Error flag - GIF4: u1, // bit offset: 12 desc: Channel 4 Global interrupt flag - TCIF4: u1, // bit offset: 13 desc: Channel 4 Transfer Complete flag - HTIF4: u1, // bit offset: 14 desc: Channel 4 Half Transfer Complete flag - TEIF4: u1, // bit offset: 15 desc: Channel 4 Transfer Error flag - GIF5: u1, // bit offset: 16 desc: Channel 5 Global interrupt flag - TCIF5: u1, // bit offset: 17 desc: Channel 5 Transfer Complete flag - HTIF5: u1, // bit offset: 18 desc: Channel 5 Half Transfer Complete flag - TEIF5: u1, // bit offset: 19 desc: Channel 5 Transfer Error flag - GIF6: u1, // bit offset: 20 desc: Channel 6 Global interrupt flag - TCIF6: u1, // bit offset: 21 desc: Channel 6 Transfer Complete flag - HTIF6: u1, // bit offset: 22 desc: Channel 6 Half Transfer Complete flag - TEIF6: u1, // bit offset: 23 desc: Channel 6 Transfer Error flag - GIF7: u1, // bit offset: 24 desc: Channel 7 Global interrupt flag - TCIF7: u1, // bit offset: 25 desc: Channel 7 Transfer Complete flag - HTIF7: u1, // bit offset: 26 desc: Channel 7 Half Transfer Complete flag - TEIF7: u1, // bit offset: 27 desc: Channel 7 Transfer Error flag - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 DMA interrupt flag clear register (DMA_IFCR) + /// Channel 1 Global interrupt flag + GIF1: u1 = 0, + /// Channel 1 Transfer Complete flag + TCIF1: u1 = 0, + /// Channel 1 Half Transfer Complete flag + HTIF1: u1 = 0, + /// Channel 1 Transfer Error flag + TEIF1: u1 = 0, + /// Channel 2 Global interrupt flag + GIF2: u1 = 0, + /// Channel 2 Transfer Complete flag + TCIF2: u1 = 0, + /// Channel 2 Half Transfer Complete flag + HTIF2: u1 = 0, + /// Channel 2 Transfer Error flag + TEIF2: u1 = 0, + /// Channel 3 Global interrupt flag + GIF3: u1 = 0, + /// Channel 3 Transfer Complete flag + TCIF3: u1 = 0, + /// Channel 3 Half Transfer Complete flag + HTIF3: u1 = 0, + /// Channel 3 Transfer Error flag + TEIF3: u1 = 0, + /// Channel 4 Global interrupt flag + GIF4: u1 = 0, + /// Channel 4 Transfer Complete flag + TCIF4: u1 = 0, + /// Channel 4 Half Transfer Complete flag + HTIF4: u1 = 0, + /// Channel 4 Transfer Error flag + TEIF4: u1 = 0, + /// Channel 5 Global interrupt flag + GIF5: u1 = 0, + /// Channel 5 Transfer Complete flag + TCIF5: u1 = 0, + /// Channel 5 Half Transfer Complete flag + HTIF5: u1 = 0, + /// Channel 5 Transfer Error flag + TEIF5: u1 = 0, + /// Channel 6 Global interrupt flag + GIF6: u1 = 0, + /// Channel 6 Transfer Complete flag + TCIF6: u1 = 0, + /// Channel 6 Half Transfer Complete flag + HTIF6: u1 = 0, + /// Channel 6 Transfer Error flag + TEIF6: u1 = 0, + /// Channel 7 Global interrupt flag + GIF7: u1 = 0, + /// Channel 7 Transfer Complete flag + TCIF7: u1 = 0, + /// Channel 7 Half Transfer Complete flag + HTIF7: u1 = 0, + /// Channel 7 Transfer Error flag + TEIF7: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// DMA interrupt flag clear register (DMA_IFCR) pub const IFCR = mmio(Address + 0x00000004, 32, packed struct { - CGIF1: u1, // bit offset: 0 desc: Channel 1 Global interrupt clear - CTCIF1: u1, // bit offset: 1 desc: Channel 1 Transfer Complete clear - CHTIF1: u1, // bit offset: 2 desc: Channel 1 Half Transfer clear - CTEIF1: u1, // bit offset: 3 desc: Channel 1 Transfer Error clear - CGIF2: u1, // bit offset: 4 desc: Channel 2 Global interrupt clear - CTCIF2: u1, // bit offset: 5 desc: Channel 2 Transfer Complete clear - CHTIF2: u1, // bit offset: 6 desc: Channel 2 Half Transfer clear - CTEIF2: u1, // bit offset: 7 desc: Channel 2 Transfer Error clear - CGIF3: u1, // bit offset: 8 desc: Channel 3 Global interrupt clear - CTCIF3: u1, // bit offset: 9 desc: Channel 3 Transfer Complete clear - CHTIF3: u1, // bit offset: 10 desc: Channel 3 Half Transfer clear - CTEIF3: u1, // bit offset: 11 desc: Channel 3 Transfer Error clear - CGIF4: u1, // bit offset: 12 desc: Channel 4 Global interrupt clear - CTCIF4: u1, // bit offset: 13 desc: Channel 4 Transfer Complete clear - CHTIF4: u1, // bit offset: 14 desc: Channel 4 Half Transfer clear - CTEIF4: u1, // bit offset: 15 desc: Channel 4 Transfer Error clear - CGIF5: u1, // bit offset: 16 desc: Channel 5 Global interrupt clear - CTCIF5: u1, // bit offset: 17 desc: Channel 5 Transfer Complete clear - CHTIF5: u1, // bit offset: 18 desc: Channel 5 Half Transfer clear - CTEIF5: u1, // bit offset: 19 desc: Channel 5 Transfer Error clear - CGIF6: u1, // bit offset: 20 desc: Channel 6 Global interrupt clear - CTCIF6: u1, // bit offset: 21 desc: Channel 6 Transfer Complete clear - CHTIF6: u1, // bit offset: 22 desc: Channel 6 Half Transfer clear - CTEIF6: u1, // bit offset: 23 desc: Channel 6 Transfer Error clear - CGIF7: u1, // bit offset: 24 desc: Channel 7 Global interrupt clear - CTCIF7: u1, // bit offset: 25 desc: Channel 7 Transfer Complete clear - CHTIF7: u1, // bit offset: 26 desc: Channel 7 Half Transfer clear - CTEIF7: u1, // bit offset: 27 desc: Channel 7 Transfer Error clear - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 DMA channel configuration register (DMA_CCR) + /// Channel 1 Global interrupt clear + CGIF1: u1 = 0, + /// Channel 1 Transfer Complete clear + CTCIF1: u1 = 0, + /// Channel 1 Half Transfer clear + CHTIF1: u1 = 0, + /// Channel 1 Transfer Error clear + CTEIF1: u1 = 0, + /// Channel 2 Global interrupt clear + CGIF2: u1 = 0, + /// Channel 2 Transfer Complete clear + CTCIF2: u1 = 0, + /// Channel 2 Half Transfer clear + CHTIF2: u1 = 0, + /// Channel 2 Transfer Error clear + CTEIF2: u1 = 0, + /// Channel 3 Global interrupt clear + CGIF3: u1 = 0, + /// Channel 3 Transfer Complete clear + CTCIF3: u1 = 0, + /// Channel 3 Half Transfer clear + CHTIF3: u1 = 0, + /// Channel 3 Transfer Error clear + CTEIF3: u1 = 0, + /// Channel 4 Global interrupt clear + CGIF4: u1 = 0, + /// Channel 4 Transfer Complete clear + CTCIF4: u1 = 0, + /// Channel 4 Half Transfer clear + CHTIF4: u1 = 0, + /// Channel 4 Transfer Error clear + CTEIF4: u1 = 0, + /// Channel 5 Global interrupt clear + CGIF5: u1 = 0, + /// Channel 5 Transfer Complete clear + CTCIF5: u1 = 0, + /// Channel 5 Half Transfer clear + CHTIF5: u1 = 0, + /// Channel 5 Transfer Error clear + CTEIF5: u1 = 0, + /// Channel 6 Global interrupt clear + CGIF6: u1 = 0, + /// Channel 6 Transfer Complete clear + CTCIF6: u1 = 0, + /// Channel 6 Half Transfer clear + CHTIF6: u1 = 0, + /// Channel 6 Transfer Error clear + CTEIF6: u1 = 0, + /// Channel 7 Global interrupt clear + CGIF7: u1 = 0, + /// Channel 7 Transfer Complete clear + CTCIF7: u1 = 0, + /// Channel 7 Half Transfer clear + CHTIF7: u1 = 0, + /// Channel 7 Transfer Error clear + CTEIF7: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// DMA channel configuration register (DMA_CCR) pub const CCR1 = mmio(Address + 0x00000008, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3554,9 +5530,11 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA channel 1 number of data register + + /// DMA channel 1 number of data register pub const CNDTR1 = mmio(Address + 0x0000000c, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3574,28 +5552,45 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 DMA channel 1 peripheral address register + + /// DMA channel 1 peripheral address register pub const CPAR1 = mmio(Address + 0x00000010, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 20 DMA channel 1 memory address register + + /// DMA channel 1 memory address register pub const CMAR1 = mmio(Address + 0x00000014, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 28 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR2 = mmio(Address + 0x0000001c, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3614,9 +5609,11 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 DMA channel 2 number of data register + + /// DMA channel 2 number of data register pub const CNDTR2 = mmio(Address + 0x00000020, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3634,28 +5631,45 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 DMA channel 2 peripheral address register + + /// DMA channel 2 peripheral address register pub const CPAR2 = mmio(Address + 0x00000024, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 40 DMA channel 2 memory address register + + /// DMA channel 2 memory address register pub const CMAR2 = mmio(Address + 0x00000028, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 48 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR3 = mmio(Address + 0x00000030, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3674,9 +5688,11 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 DMA channel 3 number of data register + + /// DMA channel 3 number of data register pub const CNDTR3 = mmio(Address + 0x00000034, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3694,28 +5710,45 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 DMA channel 3 peripheral address register + + /// DMA channel 3 peripheral address register pub const CPAR3 = mmio(Address + 0x00000038, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 60 DMA channel 3 memory address register + + /// DMA channel 3 memory address register pub const CMAR3 = mmio(Address + 0x0000003c, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 68 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR4 = mmio(Address + 0x00000044, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3734,9 +5767,11 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA channel 4 number of data register + + /// DMA channel 4 number of data register pub const CNDTR4 = mmio(Address + 0x00000048, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3754,28 +5789,45 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA channel 4 peripheral address register + + /// DMA channel 4 peripheral address register pub const CPAR4 = mmio(Address + 0x0000004c, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 80 DMA channel 4 memory address register + + /// DMA channel 4 memory address register pub const CMAR4 = mmio(Address + 0x00000050, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 88 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3794,9 +5846,11 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 92 DMA channel 5 number of data register + + /// DMA channel 5 number of data register pub const CNDTR5 = mmio(Address + 0x0000005c, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3814,28 +5868,45 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 96 DMA channel 5 peripheral address register + + /// DMA channel 5 peripheral address register pub const CPAR5 = mmio(Address + 0x00000060, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 100 DMA channel 5 memory address register + + /// DMA channel 5 memory address register pub const CMAR5 = mmio(Address + 0x00000064, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 108 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR6 = mmio(Address + 0x0000006c, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3854,9 +5925,11 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 112 DMA channel 6 number of data register + + /// DMA channel 6 number of data register pub const CNDTR6 = mmio(Address + 0x00000070, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3874,28 +5947,45 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 116 DMA channel 6 peripheral address register + + /// DMA channel 6 peripheral address register pub const CPAR6 = mmio(Address + 0x00000074, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 120 DMA channel 6 memory address register + + /// DMA channel 6 memory address register pub const CMAR6 = mmio(Address + 0x00000078, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 128 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR7 = mmio(Address + 0x00000080, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3914,9 +6004,11 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 132 DMA channel 7 number of data register + + /// DMA channel 7 number of data register pub const CNDTR7 = mmio(Address + 0x00000084, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3934,101 +6026,178 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 136 DMA channel 7 peripheral address register + + /// DMA channel 7 peripheral address register pub const CPAR7 = mmio(Address + 0x00000088, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 140 DMA channel 7 memory address register + + /// DMA channel 7 memory address register pub const CMAR7 = mmio(Address + 0x0000008c, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); }; + +/// DMA controller 1 pub const DMA2 = extern struct { pub const Address: u32 = 0x40020400; - // byte offset: 0 DMA interrupt status register (DMA_ISR) + + /// DMA interrupt status register (DMA_ISR) pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - GIF1: u1, // bit offset: 0 desc: Channel 1 Global interrupt flag - TCIF1: u1, // bit offset: 1 desc: Channel 1 Transfer Complete flag - HTIF1: u1, // bit offset: 2 desc: Channel 1 Half Transfer Complete flag - TEIF1: u1, // bit offset: 3 desc: Channel 1 Transfer Error flag - GIF2: u1, // bit offset: 4 desc: Channel 2 Global interrupt flag - TCIF2: u1, // bit offset: 5 desc: Channel 2 Transfer Complete flag - HTIF2: u1, // bit offset: 6 desc: Channel 2 Half Transfer Complete flag - TEIF2: u1, // bit offset: 7 desc: Channel 2 Transfer Error flag - GIF3: u1, // bit offset: 8 desc: Channel 3 Global interrupt flag - TCIF3: u1, // bit offset: 9 desc: Channel 3 Transfer Complete flag - HTIF3: u1, // bit offset: 10 desc: Channel 3 Half Transfer Complete flag - TEIF3: u1, // bit offset: 11 desc: Channel 3 Transfer Error flag - GIF4: u1, // bit offset: 12 desc: Channel 4 Global interrupt flag - TCIF4: u1, // bit offset: 13 desc: Channel 4 Transfer Complete flag - HTIF4: u1, // bit offset: 14 desc: Channel 4 Half Transfer Complete flag - TEIF4: u1, // bit offset: 15 desc: Channel 4 Transfer Error flag - GIF5: u1, // bit offset: 16 desc: Channel 5 Global interrupt flag - TCIF5: u1, // bit offset: 17 desc: Channel 5 Transfer Complete flag - HTIF5: u1, // bit offset: 18 desc: Channel 5 Half Transfer Complete flag - TEIF5: u1, // bit offset: 19 desc: Channel 5 Transfer Error flag - GIF6: u1, // bit offset: 20 desc: Channel 6 Global interrupt flag - TCIF6: u1, // bit offset: 21 desc: Channel 6 Transfer Complete flag - HTIF6: u1, // bit offset: 22 desc: Channel 6 Half Transfer Complete flag - TEIF6: u1, // bit offset: 23 desc: Channel 6 Transfer Error flag - GIF7: u1, // bit offset: 24 desc: Channel 7 Global interrupt flag - TCIF7: u1, // bit offset: 25 desc: Channel 7 Transfer Complete flag - HTIF7: u1, // bit offset: 26 desc: Channel 7 Half Transfer Complete flag - TEIF7: u1, // bit offset: 27 desc: Channel 7 Transfer Error flag - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 DMA interrupt flag clear register (DMA_IFCR) + /// Channel 1 Global interrupt flag + GIF1: u1 = 0, + /// Channel 1 Transfer Complete flag + TCIF1: u1 = 0, + /// Channel 1 Half Transfer Complete flag + HTIF1: u1 = 0, + /// Channel 1 Transfer Error flag + TEIF1: u1 = 0, + /// Channel 2 Global interrupt flag + GIF2: u1 = 0, + /// Channel 2 Transfer Complete flag + TCIF2: u1 = 0, + /// Channel 2 Half Transfer Complete flag + HTIF2: u1 = 0, + /// Channel 2 Transfer Error flag + TEIF2: u1 = 0, + /// Channel 3 Global interrupt flag + GIF3: u1 = 0, + /// Channel 3 Transfer Complete flag + TCIF3: u1 = 0, + /// Channel 3 Half Transfer Complete flag + HTIF3: u1 = 0, + /// Channel 3 Transfer Error flag + TEIF3: u1 = 0, + /// Channel 4 Global interrupt flag + GIF4: u1 = 0, + /// Channel 4 Transfer Complete flag + TCIF4: u1 = 0, + /// Channel 4 Half Transfer Complete flag + HTIF4: u1 = 0, + /// Channel 4 Transfer Error flag + TEIF4: u1 = 0, + /// Channel 5 Global interrupt flag + GIF5: u1 = 0, + /// Channel 5 Transfer Complete flag + TCIF5: u1 = 0, + /// Channel 5 Half Transfer Complete flag + HTIF5: u1 = 0, + /// Channel 5 Transfer Error flag + TEIF5: u1 = 0, + /// Channel 6 Global interrupt flag + GIF6: u1 = 0, + /// Channel 6 Transfer Complete flag + TCIF6: u1 = 0, + /// Channel 6 Half Transfer Complete flag + HTIF6: u1 = 0, + /// Channel 6 Transfer Error flag + TEIF6: u1 = 0, + /// Channel 7 Global interrupt flag + GIF7: u1 = 0, + /// Channel 7 Transfer Complete flag + TCIF7: u1 = 0, + /// Channel 7 Half Transfer Complete flag + HTIF7: u1 = 0, + /// Channel 7 Transfer Error flag + TEIF7: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// DMA interrupt flag clear register (DMA_IFCR) pub const IFCR = mmio(Address + 0x00000004, 32, packed struct { - CGIF1: u1, // bit offset: 0 desc: Channel 1 Global interrupt clear - CTCIF1: u1, // bit offset: 1 desc: Channel 1 Transfer Complete clear - CHTIF1: u1, // bit offset: 2 desc: Channel 1 Half Transfer clear - CTEIF1: u1, // bit offset: 3 desc: Channel 1 Transfer Error clear - CGIF2: u1, // bit offset: 4 desc: Channel 2 Global interrupt clear - CTCIF2: u1, // bit offset: 5 desc: Channel 2 Transfer Complete clear - CHTIF2: u1, // bit offset: 6 desc: Channel 2 Half Transfer clear - CTEIF2: u1, // bit offset: 7 desc: Channel 2 Transfer Error clear - CGIF3: u1, // bit offset: 8 desc: Channel 3 Global interrupt clear - CTCIF3: u1, // bit offset: 9 desc: Channel 3 Transfer Complete clear - CHTIF3: u1, // bit offset: 10 desc: Channel 3 Half Transfer clear - CTEIF3: u1, // bit offset: 11 desc: Channel 3 Transfer Error clear - CGIF4: u1, // bit offset: 12 desc: Channel 4 Global interrupt clear - CTCIF4: u1, // bit offset: 13 desc: Channel 4 Transfer Complete clear - CHTIF4: u1, // bit offset: 14 desc: Channel 4 Half Transfer clear - CTEIF4: u1, // bit offset: 15 desc: Channel 4 Transfer Error clear - CGIF5: u1, // bit offset: 16 desc: Channel 5 Global interrupt clear - CTCIF5: u1, // bit offset: 17 desc: Channel 5 Transfer Complete clear - CHTIF5: u1, // bit offset: 18 desc: Channel 5 Half Transfer clear - CTEIF5: u1, // bit offset: 19 desc: Channel 5 Transfer Error clear - CGIF6: u1, // bit offset: 20 desc: Channel 6 Global interrupt clear - CTCIF6: u1, // bit offset: 21 desc: Channel 6 Transfer Complete clear - CHTIF6: u1, // bit offset: 22 desc: Channel 6 Half Transfer clear - CTEIF6: u1, // bit offset: 23 desc: Channel 6 Transfer Error clear - CGIF7: u1, // bit offset: 24 desc: Channel 7 Global interrupt clear - CTCIF7: u1, // bit offset: 25 desc: Channel 7 Transfer Complete clear - CHTIF7: u1, // bit offset: 26 desc: Channel 7 Half Transfer clear - CTEIF7: u1, // bit offset: 27 desc: Channel 7 Transfer Error clear - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 DMA channel configuration register (DMA_CCR) - pub const CCR1 = mmio(Address + 0x00000008, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel 1 Global interrupt clear + CGIF1: u1 = 0, + /// Channel 1 Transfer Complete clear + CTCIF1: u1 = 0, + /// Channel 1 Half Transfer clear + CHTIF1: u1 = 0, + /// Channel 1 Transfer Error clear + CTEIF1: u1 = 0, + /// Channel 2 Global interrupt clear + CGIF2: u1 = 0, + /// Channel 2 Transfer Complete clear + CTCIF2: u1 = 0, + /// Channel 2 Half Transfer clear + CHTIF2: u1 = 0, + /// Channel 2 Transfer Error clear + CTEIF2: u1 = 0, + /// Channel 3 Global interrupt clear + CGIF3: u1 = 0, + /// Channel 3 Transfer Complete clear + CTCIF3: u1 = 0, + /// Channel 3 Half Transfer clear + CHTIF3: u1 = 0, + /// Channel 3 Transfer Error clear + CTEIF3: u1 = 0, + /// Channel 4 Global interrupt clear + CGIF4: u1 = 0, + /// Channel 4 Transfer Complete clear + CTCIF4: u1 = 0, + /// Channel 4 Half Transfer clear + CHTIF4: u1 = 0, + /// Channel 4 Transfer Error clear + CTEIF4: u1 = 0, + /// Channel 5 Global interrupt clear + CGIF5: u1 = 0, + /// Channel 5 Transfer Complete clear + CTCIF5: u1 = 0, + /// Channel 5 Half Transfer clear + CHTIF5: u1 = 0, + /// Channel 5 Transfer Error clear + CTEIF5: u1 = 0, + /// Channel 6 Global interrupt clear + CGIF6: u1 = 0, + /// Channel 6 Transfer Complete clear + CTCIF6: u1 = 0, + /// Channel 6 Half Transfer clear + CHTIF6: u1 = 0, + /// Channel 6 Transfer Error clear + CTEIF6: u1 = 0, + /// Channel 7 Global interrupt clear + CGIF7: u1 = 0, + /// Channel 7 Transfer Complete clear + CTCIF7: u1 = 0, + /// Channel 7 Half Transfer clear + CHTIF7: u1 = 0, + /// Channel 7 Transfer Error clear + CTEIF7: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// DMA channel configuration register (DMA_CCR) + pub const CCR1 = mmio(Address + 0x00000008, 32, packed struct { + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -4047,9 +6216,11 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA channel 1 number of data register + + /// DMA channel 1 number of data register pub const CNDTR1 = mmio(Address + 0x0000000c, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4067,28 +6238,45 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 DMA channel 1 peripheral address register + + /// DMA channel 1 peripheral address register pub const CPAR1 = mmio(Address + 0x00000010, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 20 DMA channel 1 memory address register + + /// DMA channel 1 memory address register pub const CMAR1 = mmio(Address + 0x00000014, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 28 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR2 = mmio(Address + 0x0000001c, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -4107,9 +6295,11 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 DMA channel 2 number of data register + + /// DMA channel 2 number of data register pub const CNDTR2 = mmio(Address + 0x00000020, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4127,28 +6317,45 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 DMA channel 2 peripheral address register + + /// DMA channel 2 peripheral address register pub const CPAR2 = mmio(Address + 0x00000024, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 40 DMA channel 2 memory address register + + /// DMA channel 2 memory address register pub const CMAR2 = mmio(Address + 0x00000028, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 48 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR3 = mmio(Address + 0x00000030, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -4167,9 +6374,11 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 DMA channel 3 number of data register + + /// DMA channel 3 number of data register pub const CNDTR3 = mmio(Address + 0x00000034, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4187,28 +6396,45 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 DMA channel 3 peripheral address register + + /// DMA channel 3 peripheral address register pub const CPAR3 = mmio(Address + 0x00000038, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 60 DMA channel 3 memory address register + + /// DMA channel 3 memory address register pub const CMAR3 = mmio(Address + 0x0000003c, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 68 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR4 = mmio(Address + 0x00000044, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -4227,9 +6453,11 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA channel 4 number of data register + + /// DMA channel 4 number of data register pub const CNDTR4 = mmio(Address + 0x00000048, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4247,28 +6475,45 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA channel 4 peripheral address register + + /// DMA channel 4 peripheral address register pub const CPAR4 = mmio(Address + 0x0000004c, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 80 DMA channel 4 memory address register + + /// DMA channel 4 memory address register pub const CMAR4 = mmio(Address + 0x00000050, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 88 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -4287,9 +6532,11 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 92 DMA channel 5 number of data register + + /// DMA channel 5 number of data register pub const CNDTR5 = mmio(Address + 0x0000005c, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4307,28 +6554,45 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 96 DMA channel 5 peripheral address register + + /// DMA channel 5 peripheral address register pub const CPAR5 = mmio(Address + 0x00000060, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 100 DMA channel 5 memory address register + + /// DMA channel 5 memory address register pub const CMAR5 = mmio(Address + 0x00000064, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 108 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR6 = mmio(Address + 0x0000006c, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -4347,9 +6611,11 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 112 DMA channel 6 number of data register + + /// DMA channel 6 number of data register pub const CNDTR6 = mmio(Address + 0x00000070, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4367,28 +6633,45 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 116 DMA channel 6 peripheral address register + + /// DMA channel 6 peripheral address register pub const CPAR6 = mmio(Address + 0x00000074, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 120 DMA channel 6 memory address register + + /// DMA channel 6 memory address register pub const CMAR6 = mmio(Address + 0x00000078, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 128 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR7 = mmio(Address + 0x00000080, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -4407,9 +6690,11 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 132 DMA channel 7 number of data register + + /// DMA channel 7 number of data register pub const CNDTR7 = mmio(Address + 0x00000084, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4427,29 +6712,45 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 136 DMA channel 7 peripheral address register + + /// DMA channel 7 peripheral address register pub const CPAR7 = mmio(Address + 0x00000088, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 140 DMA channel 7 memory address register + + /// DMA channel 7 memory address register pub const CMAR7 = mmio(Address + 0x0000008c, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); }; + +/// General purpose timer pub const TIM2 = extern struct { pub const Address: u32 = 0x40000000; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode - DIR: u1, // bit offset: 4 desc: Direction - CMS: u2, // bit offset: 5 desc: Center-aligned mode selection - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division - reserved1: u1 = 0, - UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, + /// Direction + DIR: u1 = 0, + /// Center-aligned mode selection + CMS: u2 = 0, + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, + reserved1: u1 = 0, + /// UIF status bit remapping + UIFREMAP: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -4471,14 +6772,18 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection - MMS: u3, // bit offset: 4 desc: Master mode selection - TI1S: u1, // bit offset: 7 desc: TI1 selection + /// Capture/compare DMA selection + CCDS: u1 = 0, + /// Master mode selection + MMS: u3 = 0, + /// TI1 selection + TI1S: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -4504,17 +6809,27 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection - OCCS: u1, // bit offset: 3 desc: OCREF clear selection - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode - ETF: u4, // bit offset: 8 desc: External trigger filter - ETPS: u2, // bit offset: 12 desc: External trigger prescaler - ECE: u1, // bit offset: 14 desc: External clock enable - ETP: u1, // bit offset: 15 desc: External trigger polarity - SMS_3: u1, // bit offset: 16 desc: Slave mode selection bit3 + /// Slave mode selection + SMS: u3 = 0, + /// OCREF clear selection + OCCS: u1 = 0, + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, + /// External trigger filter + ETF: u4 = 0, + /// External trigger prescaler + ETPS: u2 = 0, + /// External clock enable + ECE: u1 = 0, + /// External trigger polarity + ETP: u1 = 0, + /// Slave mode selection bit3 + SMS_3: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -4531,23 +6846,36 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable - CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable - CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable - reserved1: u1 = 0, - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable - reserved2: u1 = 0, - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable - CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable - CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable - CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, + /// Capture/Compare 3 interrupt enable + CC3IE: u1 = 0, + /// Capture/Compare 4 interrupt enable + CC4IE: u1 = 0, + reserved1: u1 = 0, + /// Trigger interrupt enable + TIE: u1 = 0, + reserved2: u1 = 0, + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, + /// Capture/Compare 2 DMA request enable + CC2DE: u1 = 0, + /// Capture/Compare 3 DMA request enable + CC3DE: u1 = 0, + /// Capture/Compare 4 DMA request enable + CC4DE: u1 = 0, reserved3: u1 = 0, - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -4566,21 +6894,32 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag - CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag - CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag - reserved1: u1 = 0, - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, + /// Capture/Compare 3 interrupt flag + CC3IF: u1 = 0, + /// Capture/Compare 4 interrupt flag + CC4IF: u1 = 0, + reserved1: u1 = 0, + /// Trigger interrupt flag + TIF: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag - CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag - CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, + /// Capture/Compare 3 overcapture flag + CC3OF: u1 = 0, + /// Capture/Compare 4 overcapture flag + CC4OF: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -4601,15 +6940,22 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation - CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation - CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation - reserved1: u1 = 0, - TG: u1, // bit offset: 6 desc: Trigger generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, + /// Capture/compare 3 generation + CC3G: u1 = 0, + /// Capture/compare 4 generation + CC4G: u1 = 0, + reserved1: u1 = 0, + /// Trigger generation + TG: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -4636,19 +6982,31 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (output mode) + + /// capture/compare mode register 1 (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output compare 1 mode - OC1CE: u1, // bit offset: 7 desc: Output compare 1 clear enable - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output compare 2 mode - OC2CE: u1, // bit offset: 15 desc: Output compare 2 clear enable - OC1M_3: u1, // bit offset: 16 desc: Output compare 1 mode bit 3 + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output compare 1 fast enable + OC1FE: u1 = 0, + /// Output compare 1 preload enable + OC1PE: u1 = 0, + /// Output compare 1 mode + OC1M: u3 = 0, + /// Output compare 1 clear enable + OC1CE: u1 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output compare 2 fast enable + OC2FE: u1 = 0, + /// Output compare 2 preload enable + OC2PE: u1 = 0, + /// Output compare 2 mode + OC2M: u3 = 0, + /// Output compare 2 clear enable + OC2CE: u1 = 0, + /// Output compare 1 mode bit 3 + OC1M_3: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -4656,7 +7014,8 @@ pub const TIM2 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC2M_3: u1, // bit offset: 24 desc: Output compare 2 mode bit 3 + /// Output compare 2 mode bit 3 + OC2M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -4665,14 +7024,21 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/compare 2 selection - IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PSC: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4690,19 +7056,31 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (output mode) + + /// capture/compare mode register 2 (output mode) pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable - OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable - OC3M: u3, // bit offset: 4 desc: Output compare 3 mode - OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable - OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable - OC4M: u3, // bit offset: 12 desc: Output compare 4 mode - O24CE: u1, // bit offset: 15 desc: Output compare 4 clear enable - OC3M_3: u1, // bit offset: 16 desc: Output compare 3 mode bit3 + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Output compare 3 fast enable + OC3FE: u1 = 0, + /// Output compare 3 preload enable + OC3PE: u1 = 0, + /// Output compare 3 mode + OC3M: u3 = 0, + /// Output compare 3 clear enable + OC3CE: u1 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Output compare 4 fast enable + OC4FE: u1 = 0, + /// Output compare 4 preload enable + OC4PE: u1 = 0, + /// Output compare 4 mode + OC4M: u3 = 0, + /// Output compare 4 clear enable + O24CE: u1 = 0, + /// Output compare 3 mode bit3 + OC3M_3: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -4710,7 +7088,8 @@ pub const TIM2 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC4M_3: u1, // bit offset: 24 desc: Output compare 4 mode bit3 + /// Output compare 4 mode bit3 + OC4M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -4719,14 +7098,21 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (input mode) + + /// capture/compare mode register 2 (input mode) pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler - IC3F: u4, // bit offset: 4 desc: Input capture 3 filter - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler - IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Input capture 3 prescaler + IC3PSC: u2 = 0, + /// Input capture 3 filter + IC3F: u4 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Input capture 4 prescaler + IC4PSC: u2 = 0, + /// Input capture 4 filter + IC4F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4744,24 +7130,37 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity - reserved1: u1 = 0, - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity - reserved2: u1 = 0, - CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity - CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable - CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, + reserved1: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, + reserved2: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2NP: u1 = 0, + /// Capture/Compare 3 output enable + CC3E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3P: u1 = 0, reserved3: u1 = 0, - CC3NP: u1, // bit offset: 11 desc: Capture/Compare 3 output Polarity - CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable - CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 3 output Polarity + CC3NP: u1 = 0, + /// Capture/Compare 4 output enable + CC4E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC4P: u1 = 0, reserved4: u1 = 0, - CC4NP: u1, // bit offset: 15 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 3 output Polarity + CC4NP: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4779,15 +7178,22 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNTL: u16, // bit offset: 0 desc: Low counter value - CNTH: u15, // bit offset: 16 desc: High counter value - CNT_or_UIFCPY: u1, // bit offset: 31 desc: if IUFREMAP=0 than CNT with read write access else UIFCPY with read only access + /// Low counter value + CNTL: u16 = 0, + /// High counter value + CNTH: u15 = 0, + /// if IUFREMAP=0 than CNT with read write access else UIFCPY with read only + /// access + CNT_or_UIFCPY: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4805,38 +7211,56 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARRL: u16, // bit offset: 0 desc: Low Auto-reload value - ARRH: u16, // bit offset: 16 desc: High Auto-reload value + /// Low Auto-reload value + ARRL: u16 = 0, + /// High Auto-reload value + ARRH: u16 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1L: u16, // bit offset: 0 desc: Low Capture/Compare 1 value - CCR1H: u16, // bit offset: 16 desc: High Capture/Compare 1 value (on TIM2) + /// Low Capture/Compare 1 value + CCR1L: u16 = 0, + /// High Capture/Compare 1 value (on TIM2) + CCR1H: u16 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2L: u16, // bit offset: 0 desc: Low Capture/Compare 2 value - CCR2H: u16, // bit offset: 16 desc: High Capture/Compare 2 value (on TIM2) + /// Low Capture/Compare 2 value + CCR2L: u16 = 0, + /// High Capture/Compare 2 value (on TIM2) + CCR2H: u16 = 0, }); - // byte offset: 60 capture/compare register 3 + + /// capture/compare register 3 pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - CCR3L: u16, // bit offset: 0 desc: Low Capture/Compare value - CCR3H: u16, // bit offset: 16 desc: High Capture/Compare value (on TIM2) + /// Low Capture/Compare value + CCR3L: u16 = 0, + /// High Capture/Compare value (on TIM2) + CCR3H: u16 = 0, }); - // byte offset: 64 capture/compare register 4 + + /// capture/compare register 4 pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - CCR4L: u16, // bit offset: 0 desc: Low Capture/Compare value - CCR4H: u16, // bit offset: 16 desc: High Capture/Compare value (on TIM2) + /// Low Capture/Compare value + CCR4L: u16 = 0, + /// High Capture/Compare value (on TIM2) + CCR4H: u16 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -4857,9 +7281,11 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4878,20 +7304,32 @@ pub const TIM2 = extern struct { padding1: u1 = 0, }); }; + +/// General purpose timer pub const TIM3 = extern struct { pub const Address: u32 = 0x40000400; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode - DIR: u1, // bit offset: 4 desc: Direction - CMS: u2, // bit offset: 5 desc: Center-aligned mode selection - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division - reserved1: u1 = 0, - UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, + /// Direction + DIR: u1 = 0, + /// Center-aligned mode selection + CMS: u2 = 0, + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, + reserved1: u1 = 0, + /// UIF status bit remapping + UIFREMAP: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -4913,14 +7351,18 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection - MMS: u3, // bit offset: 4 desc: Master mode selection - TI1S: u1, // bit offset: 7 desc: TI1 selection + /// Capture/compare DMA selection + CCDS: u1 = 0, + /// Master mode selection + MMS: u3 = 0, + /// TI1 selection + TI1S: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -4946,17 +7388,27 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection - OCCS: u1, // bit offset: 3 desc: OCREF clear selection - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode - ETF: u4, // bit offset: 8 desc: External trigger filter - ETPS: u2, // bit offset: 12 desc: External trigger prescaler - ECE: u1, // bit offset: 14 desc: External clock enable - ETP: u1, // bit offset: 15 desc: External trigger polarity - SMS_3: u1, // bit offset: 16 desc: Slave mode selection bit3 + /// Slave mode selection + SMS: u3 = 0, + /// OCREF clear selection + OCCS: u1 = 0, + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, + /// External trigger filter + ETF: u4 = 0, + /// External trigger prescaler + ETPS: u2 = 0, + /// External clock enable + ECE: u1 = 0, + /// External trigger polarity + ETP: u1 = 0, + /// Slave mode selection bit3 + SMS_3: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -4973,23 +7425,36 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable - CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable - CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable - reserved1: u1 = 0, - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable - reserved2: u1 = 0, - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable - CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable - CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable - CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, + /// Capture/Compare 3 interrupt enable + CC3IE: u1 = 0, + /// Capture/Compare 4 interrupt enable + CC4IE: u1 = 0, + reserved1: u1 = 0, + /// Trigger interrupt enable + TIE: u1 = 0, + reserved2: u1 = 0, + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, + /// Capture/Compare 2 DMA request enable + CC2DE: u1 = 0, + /// Capture/Compare 3 DMA request enable + CC3DE: u1 = 0, + /// Capture/Compare 4 DMA request enable + CC4DE: u1 = 0, reserved3: u1 = 0, - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -5008,21 +7473,32 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag - CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag - CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag - reserved1: u1 = 0, - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, + /// Capture/Compare 3 interrupt flag + CC3IF: u1 = 0, + /// Capture/Compare 4 interrupt flag + CC4IF: u1 = 0, + reserved1: u1 = 0, + /// Trigger interrupt flag + TIF: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag - CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag - CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, + /// Capture/Compare 3 overcapture flag + CC3OF: u1 = 0, + /// Capture/Compare 4 overcapture flag + CC4OF: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -5043,15 +7519,22 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation - CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation - CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation - reserved1: u1 = 0, - TG: u1, // bit offset: 6 desc: Trigger generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, + /// Capture/compare 3 generation + CC3G: u1 = 0, + /// Capture/compare 4 generation + CC4G: u1 = 0, + reserved1: u1 = 0, + /// Trigger generation + TG: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -5078,19 +7561,31 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (output mode) + + /// capture/compare mode register 1 (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output compare 1 mode - OC1CE: u1, // bit offset: 7 desc: Output compare 1 clear enable - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output compare 2 mode - OC2CE: u1, // bit offset: 15 desc: Output compare 2 clear enable - OC1M_3: u1, // bit offset: 16 desc: Output compare 1 mode bit 3 + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output compare 1 fast enable + OC1FE: u1 = 0, + /// Output compare 1 preload enable + OC1PE: u1 = 0, + /// Output compare 1 mode + OC1M: u3 = 0, + /// Output compare 1 clear enable + OC1CE: u1 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output compare 2 fast enable + OC2FE: u1 = 0, + /// Output compare 2 preload enable + OC2PE: u1 = 0, + /// Output compare 2 mode + OC2M: u3 = 0, + /// Output compare 2 clear enable + OC2CE: u1 = 0, + /// Output compare 1 mode bit 3 + OC1M_3: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -5098,7 +7593,8 @@ pub const TIM3 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC2M_3: u1, // bit offset: 24 desc: Output compare 2 mode bit 3 + /// Output compare 2 mode bit 3 + OC2M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -5107,14 +7603,21 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/compare 2 selection - IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PSC: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5132,19 +7635,31 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (output mode) + + /// capture/compare mode register 2 (output mode) pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable - OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable - OC3M: u3, // bit offset: 4 desc: Output compare 3 mode - OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable - OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable - OC4M: u3, // bit offset: 12 desc: Output compare 4 mode - O24CE: u1, // bit offset: 15 desc: Output compare 4 clear enable - OC3M_3: u1, // bit offset: 16 desc: Output compare 3 mode bit3 + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Output compare 3 fast enable + OC3FE: u1 = 0, + /// Output compare 3 preload enable + OC3PE: u1 = 0, + /// Output compare 3 mode + OC3M: u3 = 0, + /// Output compare 3 clear enable + OC3CE: u1 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Output compare 4 fast enable + OC4FE: u1 = 0, + /// Output compare 4 preload enable + OC4PE: u1 = 0, + /// Output compare 4 mode + OC4M: u3 = 0, + /// Output compare 4 clear enable + O24CE: u1 = 0, + /// Output compare 3 mode bit3 + OC3M_3: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -5152,7 +7667,8 @@ pub const TIM3 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC4M_3: u1, // bit offset: 24 desc: Output compare 4 mode bit3 + /// Output compare 4 mode bit3 + OC4M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -5161,14 +7677,21 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (input mode) + + /// capture/compare mode register 2 (input mode) pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler - IC3F: u4, // bit offset: 4 desc: Input capture 3 filter - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler - IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Input capture 3 prescaler + IC3PSC: u2 = 0, + /// Input capture 3 filter + IC3F: u4 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Input capture 4 prescaler + IC4PSC: u2 = 0, + /// Input capture 4 filter + IC4F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5186,24 +7709,37 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity - reserved1: u1 = 0, - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity - reserved2: u1 = 0, - CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity - CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable - CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, + reserved1: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, + reserved2: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2NP: u1 = 0, + /// Capture/Compare 3 output enable + CC3E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3P: u1 = 0, reserved3: u1 = 0, - CC3NP: u1, // bit offset: 11 desc: Capture/Compare 3 output Polarity - CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable - CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 3 output Polarity + CC3NP: u1 = 0, + /// Capture/Compare 4 output enable + CC4E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC4P: u1 = 0, reserved4: u1 = 0, - CC4NP: u1, // bit offset: 15 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 3 output Polarity + CC4NP: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5221,15 +7757,22 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNTL: u16, // bit offset: 0 desc: Low counter value - CNTH: u15, // bit offset: 16 desc: High counter value - CNT_or_UIFCPY: u1, // bit offset: 31 desc: if IUFREMAP=0 than CNT with read write access else UIFCPY with read only access + /// Low counter value + CNTL: u16 = 0, + /// High counter value + CNTH: u15 = 0, + /// if IUFREMAP=0 than CNT with read write access else UIFCPY with read only + /// access + CNT_or_UIFCPY: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5247,38 +7790,56 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARRL: u16, // bit offset: 0 desc: Low Auto-reload value - ARRH: u16, // bit offset: 16 desc: High Auto-reload value + /// Low Auto-reload value + ARRL: u16 = 0, + /// High Auto-reload value + ARRH: u16 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1L: u16, // bit offset: 0 desc: Low Capture/Compare 1 value - CCR1H: u16, // bit offset: 16 desc: High Capture/Compare 1 value (on TIM2) + /// Low Capture/Compare 1 value + CCR1L: u16 = 0, + /// High Capture/Compare 1 value (on TIM2) + CCR1H: u16 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2L: u16, // bit offset: 0 desc: Low Capture/Compare 2 value - CCR2H: u16, // bit offset: 16 desc: High Capture/Compare 2 value (on TIM2) + /// Low Capture/Compare 2 value + CCR2L: u16 = 0, + /// High Capture/Compare 2 value (on TIM2) + CCR2H: u16 = 0, }); - // byte offset: 60 capture/compare register 3 + + /// capture/compare register 3 pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - CCR3L: u16, // bit offset: 0 desc: Low Capture/Compare value - CCR3H: u16, // bit offset: 16 desc: High Capture/Compare value (on TIM2) + /// Low Capture/Compare value + CCR3L: u16 = 0, + /// High Capture/Compare value (on TIM2) + CCR3H: u16 = 0, }); - // byte offset: 64 capture/compare register 4 + + /// capture/compare register 4 pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - CCR4L: u16, // bit offset: 0 desc: Low Capture/Compare value - CCR4H: u16, // bit offset: 16 desc: High Capture/Compare value (on TIM2) + /// Low Capture/Compare value + CCR4L: u16 = 0, + /// High Capture/Compare value (on TIM2) + CCR4H: u16 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -5299,9 +7860,11 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5320,20 +7883,32 @@ pub const TIM3 = extern struct { padding1: u1 = 0, }); }; + +/// General purpose timer pub const TIM4 = extern struct { pub const Address: u32 = 0x40000800; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode - DIR: u1, // bit offset: 4 desc: Direction - CMS: u2, // bit offset: 5 desc: Center-aligned mode selection - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division - reserved1: u1 = 0, - UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, + /// Direction + DIR: u1 = 0, + /// Center-aligned mode selection + CMS: u2 = 0, + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, + reserved1: u1 = 0, + /// UIF status bit remapping + UIFREMAP: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -5355,14 +7930,18 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection - MMS: u3, // bit offset: 4 desc: Master mode selection - TI1S: u1, // bit offset: 7 desc: TI1 selection + /// Capture/compare DMA selection + CCDS: u1 = 0, + /// Master mode selection + MMS: u3 = 0, + /// TI1 selection + TI1S: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -5388,17 +7967,27 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection - OCCS: u1, // bit offset: 3 desc: OCREF clear selection - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode - ETF: u4, // bit offset: 8 desc: External trigger filter - ETPS: u2, // bit offset: 12 desc: External trigger prescaler - ECE: u1, // bit offset: 14 desc: External clock enable - ETP: u1, // bit offset: 15 desc: External trigger polarity - SMS_3: u1, // bit offset: 16 desc: Slave mode selection bit3 + /// Slave mode selection + SMS: u3 = 0, + /// OCREF clear selection + OCCS: u1 = 0, + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, + /// External trigger filter + ETF: u4 = 0, + /// External trigger prescaler + ETPS: u2 = 0, + /// External clock enable + ECE: u1 = 0, + /// External trigger polarity + ETP: u1 = 0, + /// Slave mode selection bit3 + SMS_3: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -5415,23 +8004,36 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable - CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable - CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable - reserved1: u1 = 0, - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable - reserved2: u1 = 0, - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable - CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable - CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable - CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, + /// Capture/Compare 3 interrupt enable + CC3IE: u1 = 0, + /// Capture/Compare 4 interrupt enable + CC4IE: u1 = 0, + reserved1: u1 = 0, + /// Trigger interrupt enable + TIE: u1 = 0, + reserved2: u1 = 0, + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, + /// Capture/Compare 2 DMA request enable + CC2DE: u1 = 0, + /// Capture/Compare 3 DMA request enable + CC3DE: u1 = 0, + /// Capture/Compare 4 DMA request enable + CC4DE: u1 = 0, reserved3: u1 = 0, - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -5450,21 +8052,32 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag - CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag - CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag - reserved1: u1 = 0, - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, + /// Capture/Compare 3 interrupt flag + CC3IF: u1 = 0, + /// Capture/Compare 4 interrupt flag + CC4IF: u1 = 0, + reserved1: u1 = 0, + /// Trigger interrupt flag + TIF: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag - CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag - CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, + /// Capture/Compare 3 overcapture flag + CC3OF: u1 = 0, + /// Capture/Compare 4 overcapture flag + CC4OF: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -5485,15 +8098,22 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation - CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation - CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation - reserved1: u1 = 0, - TG: u1, // bit offset: 6 desc: Trigger generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, + /// Capture/compare 3 generation + CC3G: u1 = 0, + /// Capture/compare 4 generation + CC4G: u1 = 0, + reserved1: u1 = 0, + /// Trigger generation + TG: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -5520,19 +8140,31 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (output mode) + + /// capture/compare mode register 1 (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output compare 1 mode - OC1CE: u1, // bit offset: 7 desc: Output compare 1 clear enable - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output compare 2 mode - OC2CE: u1, // bit offset: 15 desc: Output compare 2 clear enable - OC1M_3: u1, // bit offset: 16 desc: Output compare 1 mode bit 3 + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output compare 1 fast enable + OC1FE: u1 = 0, + /// Output compare 1 preload enable + OC1PE: u1 = 0, + /// Output compare 1 mode + OC1M: u3 = 0, + /// Output compare 1 clear enable + OC1CE: u1 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output compare 2 fast enable + OC2FE: u1 = 0, + /// Output compare 2 preload enable + OC2PE: u1 = 0, + /// Output compare 2 mode + OC2M: u3 = 0, + /// Output compare 2 clear enable + OC2CE: u1 = 0, + /// Output compare 1 mode bit 3 + OC1M_3: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -5540,7 +8172,8 @@ pub const TIM4 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC2M_3: u1, // bit offset: 24 desc: Output compare 2 mode bit 3 + /// Output compare 2 mode bit 3 + OC2M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -5549,14 +8182,21 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/compare 2 selection - IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PSC: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5574,19 +8214,31 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (output mode) + + /// capture/compare mode register 2 (output mode) pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable - OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable - OC3M: u3, // bit offset: 4 desc: Output compare 3 mode - OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable - OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable - OC4M: u3, // bit offset: 12 desc: Output compare 4 mode - O24CE: u1, // bit offset: 15 desc: Output compare 4 clear enable - OC3M_3: u1, // bit offset: 16 desc: Output compare 3 mode bit3 + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Output compare 3 fast enable + OC3FE: u1 = 0, + /// Output compare 3 preload enable + OC3PE: u1 = 0, + /// Output compare 3 mode + OC3M: u3 = 0, + /// Output compare 3 clear enable + OC3CE: u1 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Output compare 4 fast enable + OC4FE: u1 = 0, + /// Output compare 4 preload enable + OC4PE: u1 = 0, + /// Output compare 4 mode + OC4M: u3 = 0, + /// Output compare 4 clear enable + O24CE: u1 = 0, + /// Output compare 3 mode bit3 + OC3M_3: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -5594,7 +8246,8 @@ pub const TIM4 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC4M_3: u1, // bit offset: 24 desc: Output compare 4 mode bit3 + /// Output compare 4 mode bit3 + OC4M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -5603,14 +8256,21 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (input mode) + + /// capture/compare mode register 2 (input mode) pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler - IC3F: u4, // bit offset: 4 desc: Input capture 3 filter - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler - IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Input capture 3 prescaler + IC3PSC: u2 = 0, + /// Input capture 3 filter + IC3F: u4 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Input capture 4 prescaler + IC4PSC: u2 = 0, + /// Input capture 4 filter + IC4F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5628,24 +8288,37 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity - reserved1: u1 = 0, - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity - reserved2: u1 = 0, - CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity - CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable - CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, + reserved1: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, + reserved2: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2NP: u1 = 0, + /// Capture/Compare 3 output enable + CC3E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3P: u1 = 0, reserved3: u1 = 0, - CC3NP: u1, // bit offset: 11 desc: Capture/Compare 3 output Polarity - CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable - CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 3 output Polarity + CC3NP: u1 = 0, + /// Capture/Compare 4 output enable + CC4E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC4P: u1 = 0, reserved4: u1 = 0, - CC4NP: u1, // bit offset: 15 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 3 output Polarity + CC4NP: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5663,15 +8336,22 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNTL: u16, // bit offset: 0 desc: Low counter value - CNTH: u15, // bit offset: 16 desc: High counter value - CNT_or_UIFCPY: u1, // bit offset: 31 desc: if IUFREMAP=0 than CNT with read write access else UIFCPY with read only access + /// Low counter value + CNTL: u16 = 0, + /// High counter value + CNTH: u15 = 0, + /// if IUFREMAP=0 than CNT with read write access else UIFCPY with read only + /// access + CNT_or_UIFCPY: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5689,38 +8369,56 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARRL: u16, // bit offset: 0 desc: Low Auto-reload value - ARRH: u16, // bit offset: 16 desc: High Auto-reload value + /// Low Auto-reload value + ARRL: u16 = 0, + /// High Auto-reload value + ARRH: u16 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1L: u16, // bit offset: 0 desc: Low Capture/Compare 1 value - CCR1H: u16, // bit offset: 16 desc: High Capture/Compare 1 value (on TIM2) + /// Low Capture/Compare 1 value + CCR1L: u16 = 0, + /// High Capture/Compare 1 value (on TIM2) + CCR1H: u16 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2L: u16, // bit offset: 0 desc: Low Capture/Compare 2 value - CCR2H: u16, // bit offset: 16 desc: High Capture/Compare 2 value (on TIM2) + /// Low Capture/Compare 2 value + CCR2L: u16 = 0, + /// High Capture/Compare 2 value (on TIM2) + CCR2H: u16 = 0, }); - // byte offset: 60 capture/compare register 3 + + /// capture/compare register 3 pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - CCR3L: u16, // bit offset: 0 desc: Low Capture/Compare value - CCR3H: u16, // bit offset: 16 desc: High Capture/Compare value (on TIM2) + /// Low Capture/Compare value + CCR3L: u16 = 0, + /// High Capture/Compare value (on TIM2) + CCR3H: u16 = 0, }); - // byte offset: 64 capture/compare register 4 + + /// capture/compare register 4 pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - CCR4L: u16, // bit offset: 0 desc: Low Capture/Compare value - CCR4H: u16, // bit offset: 16 desc: High Capture/Compare value (on TIM2) + /// Low Capture/Compare value + CCR4L: u16 = 0, + /// High Capture/Compare value (on TIM2) + CCR4H: u16 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -5741,9 +8439,11 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5762,21 +8462,31 @@ pub const TIM4 = extern struct { padding1: u1 = 0, }); }; + +/// General purpose timers pub const TIM15 = extern struct { pub const Address: u32 = 0x40014000; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, reserved4: u1 = 0, - UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + /// UIF status bit remapping + UIFREMAP: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -5798,17 +8508,26 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - CCPC: u1, // bit offset: 0 desc: Capture/compare preloaded control - reserved1: u1 = 0, - CCUS: u1, // bit offset: 2 desc: Capture/compare control update selection - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection - MMS: u3, // bit offset: 4 desc: Master mode selection - TI1S: u1, // bit offset: 7 desc: TI1 selection - OIS1: u1, // bit offset: 8 desc: Output Idle state 1 - OIS1N: u1, // bit offset: 9 desc: Output Idle state 1 - OIS2: u1, // bit offset: 10 desc: Output Idle state 2 + /// Capture/compare preloaded control + CCPC: u1 = 0, + reserved1: u1 = 0, + /// Capture/compare control update selection + CCUS: u1 = 0, + /// Capture/compare DMA selection + CCDS: u1 = 0, + /// Master mode selection + MMS: u3 = 0, + /// TI1 selection + TI1S: u1 = 0, + /// Output Idle state 1 + OIS1: u1 = 0, + /// Output Idle state 1 + OIS1N: u1 = 0, + /// Output Idle state 2 + OIS2: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -5831,12 +8550,16 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection + /// Slave mode selection + SMS: u3 = 0, reserved1: u1 = 0, - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, @@ -5845,7 +8568,8 @@ pub const TIM15 = extern struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - SMS_3: u1, // bit offset: 16 desc: Slave mode selection bit 3 + /// Slave mode selection bit 3 + SMS_3: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -5862,23 +8586,35 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable - reserved2: u1 = 0, - reserved1: u1 = 0, - COMIE: u1, // bit offset: 5 desc: COM interrupt enable - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable - BIE: u1, // bit offset: 7 desc: Break interrupt enable - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable - CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// COM interrupt enable + COMIE: u1 = 0, + /// Trigger interrupt enable + TIE: u1 = 0, + /// Break interrupt enable + BIE: u1 = 0, + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, + /// Capture/Compare 2 DMA request enable + CC2DE: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - COMDE: u1, // bit offset: 13 desc: COM DMA request enable - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// COM DMA request enable + COMDE: u1 = 0, + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -5897,19 +8633,28 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag - reserved2: u1 = 0, - reserved1: u1 = 0, - COMIF: u1, // bit offset: 5 desc: COM interrupt flag - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag - BIF: u1, // bit offset: 7 desc: Break interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// COM interrupt flag + COMIF: u1 = 0, + /// Trigger interrupt flag + TIF: u1 = 0, + /// Break interrupt flag + BIF: u1 = 0, reserved3: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -5932,16 +8677,23 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation - reserved2: u1 = 0, - reserved1: u1 = 0, - COMG: u1, // bit offset: 5 desc: Capture/Compare control update generation - TG: u1, // bit offset: 6 desc: Trigger generation - BG: u1, // bit offset: 7 desc: Break generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Capture/Compare control update generation + COMG: u1 = 0, + /// Trigger generation + TG: u1 = 0, + /// Break generation + BG: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -5967,19 +8719,29 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode - reserved1: u1 = 0, - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output Compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output Compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output Compare 2 mode - reserved2: u1 = 0, - OC1M_3: u1, // bit offset: 16 desc: Output Compare 1 mode bit 3 + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output Compare 1 fast enable + OC1FE: u1 = 0, + /// Output Compare 1 preload enable + OC1PE: u1 = 0, + /// Output Compare 1 mode + OC1M: u3 = 0, + reserved1: u1 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output Compare 2 fast enable + OC2FE: u1 = 0, + /// Output Compare 2 preload enable + OC2PE: u1 = 0, + /// Output Compare 2 mode + OC2M: u3 = 0, + reserved2: u1 = 0, + /// Output Compare 1 mode bit 3 + OC1M_3: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, @@ -5987,7 +8749,8 @@ pub const TIM15 = extern struct { reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - OC2M_3: u1, // bit offset: 24 desc: Output Compare 2 mode bit 3 + /// Output Compare 2 mode bit 3 + OC2M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -5996,14 +8759,21 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PSC: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6021,16 +8791,24 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity - CC1NE: u1, // bit offset: 2 desc: Capture/Compare 1 complementary output enable - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity - reserved1: u1 = 0, - CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, + /// Capture/Compare 1 complementary output enable + CC1NE: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, + reserved1: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2NP: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -6056,9 +8834,11 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, @@ -6074,11 +8854,14 @@ pub const TIM15 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UIFCPY: u1, // bit offset: 31 desc: UIF copy + /// UIF copy + UIFCPY: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6096,9 +8879,11 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6116,9 +8901,11 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 repetition counter register + + /// repetition counter register pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - REP: u8, // bit offset: 0 desc: Repetition counter value + /// Repetition counter value + REP: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -6144,9 +8931,11 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6164,9 +8953,11 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + /// Capture/Compare 2 value + CCR2: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6184,17 +8975,27 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 break and dead-time register + + /// break and dead-time register pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - DTG: u8, // bit offset: 0 desc: Dead-time generator setup - LOCK: u2, // bit offset: 8 desc: Lock configuration - OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode - OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode - BKE: u1, // bit offset: 12 desc: Break enable - BKP: u1, // bit offset: 13 desc: Break polarity - AOE: u1, // bit offset: 14 desc: Automatic output enable - MOE: u1, // bit offset: 15 desc: Main output enable - BKF: u4, // bit offset: 16 desc: Break filter + /// Dead-time generator setup + DTG: u8 = 0, + /// Lock configuration + LOCK: u2 = 0, + /// Off-state selection for Idle mode + OSSI: u1 = 0, + /// Off-state selection for Run mode + OSSR: u1 = 0, + /// Break enable + BKE: u1 = 0, + /// Break polarity + BKP: u1 = 0, + /// Automatic output enable + AOE: u1 = 0, + /// Main output enable + MOE: u1 = 0, + /// Break filter + BKF: u4 = 0, padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -6208,13 +9009,16 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -6235,9 +9039,11 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6256,21 +9062,31 @@ pub const TIM15 = extern struct { padding1: u1 = 0, }); }; + +/// General-purpose-timers pub const TIM16 = extern struct { pub const Address: u32 = 0x40014400; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, reserved4: u1 = 0, - UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + /// UIF status bit remapping + UIFREMAP: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -6292,18 +9108,24 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - CCPC: u1, // bit offset: 0 desc: Capture/compare preloaded control + /// Capture/compare preloaded control + CCPC: u1 = 0, reserved1: u1 = 0, - CCUS: u1, // bit offset: 2 desc: Capture/compare control update selection - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection + /// Capture/compare control update selection + CCUS: u1 = 0, + /// Capture/compare DMA selection + CCDS: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - OIS1: u1, // bit offset: 8 desc: Output Idle state 1 - OIS1N: u1, // bit offset: 9 desc: Output Idle state 1 + /// Output Idle state 1 + OIS1: u1 = 0, + /// Output Idle state 1 + OIS1N: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -6327,23 +9149,33 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - COMIE: u1, // bit offset: 5 desc: COM interrupt enable - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable - BIE: u1, // bit offset: 7 desc: Break interrupt enable - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable + /// COM interrupt enable + COMIE: u1 = 0, + /// Trigger interrupt enable + TIE: u1 = 0, + /// Break interrupt enable + BIE: u1 = 0, + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - COMDE: u1, // bit offset: 13 desc: COM DMA request enable - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// COM DMA request enable + COMDE: u1 = 0, + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -6362,18 +9194,25 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - COMIF: u1, // bit offset: 5 desc: COM interrupt flag - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag - BIF: u1, // bit offset: 7 desc: Break interrupt flag + /// COM interrupt flag + COMIF: u1 = 0, + /// Trigger interrupt flag + TIF: u1 = 0, + /// Break interrupt flag + BIF: u1 = 0, reserved4: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -6397,16 +9236,22 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - COMG: u1, // bit offset: 5 desc: Capture/Compare control update generation - TG: u1, // bit offset: 6 desc: Trigger generation - BG: u1, // bit offset: 7 desc: Break generation + /// Capture/Compare control update generation + COMG: u1 = 0, + /// Trigger generation + TG: u1 = 0, + /// Break generation + BG: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -6432,12 +9277,17 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output Compare 1 fast enable + OC1FE: u1 = 0, + /// Output Compare 1 preload enable + OC1PE: u1 = 0, + /// Output Compare 1 mode + OC1M: u3 = 0, reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, @@ -6447,7 +9297,8 @@ pub const TIM16 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC1M_3: u1, // bit offset: 16 desc: Output Compare 1 mode + /// Output Compare 1 mode + OC1M_3: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -6464,11 +9315,15 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -6494,12 +9349,17 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity - CC1NE: u1, // bit offset: 2 desc: Capture/Compare 1 complementary output enable - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, + /// Capture/Compare 1 complementary output enable + CC1NE: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -6529,9 +9389,11 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, @@ -6547,11 +9409,14 @@ pub const TIM16 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UIFCPY: u1, // bit offset: 31 desc: UIF Copy + /// UIF Copy + UIFCPY: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6569,9 +9434,11 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6589,9 +9456,11 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 repetition counter register + + /// repetition counter register pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - REP: u8, // bit offset: 0 desc: Repetition counter value + /// Repetition counter value + REP: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -6617,9 +9486,11 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6637,17 +9508,27 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 break and dead-time register + + /// break and dead-time register pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - DTG: u8, // bit offset: 0 desc: Dead-time generator setup - LOCK: u2, // bit offset: 8 desc: Lock configuration - OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode - OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode - BKE: u1, // bit offset: 12 desc: Break enable - BKP: u1, // bit offset: 13 desc: Break polarity - AOE: u1, // bit offset: 14 desc: Automatic output enable - MOE: u1, // bit offset: 15 desc: Main output enable - BKF: u4, // bit offset: 16 desc: Break filter + /// Dead-time generator setup + DTG: u8 = 0, + /// Lock configuration + LOCK: u2 = 0, + /// Off-state selection for Idle mode + OSSI: u1 = 0, + /// Off-state selection for Run mode + OSSR: u1 = 0, + /// Break enable + BKE: u1 = 0, + /// Break polarity + BKP: u1 = 0, + /// Automatic output enable + AOE: u1 = 0, + /// Main output enable + MOE: u1 = 0, + /// Break filter + BKF: u4 = 0, padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -6661,13 +9542,16 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -6688,9 +9572,11 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6708,26 +9594,35 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 80 option register - pub const OR = mmio(Address + 0x00000050, 32, packed struct { - raw: u32, // placeholder field - }); + + /// option register + pub const OR = @intToPtr(*volatile u32, Address + 0x00000050); }; + +/// General purpose timer pub const TIM17 = extern struct { pub const Address: u32 = 0x40014800; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, reserved4: u1 = 0, - UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + /// UIF status bit remapping + UIFREMAP: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -6749,18 +9644,24 @@ pub const TIM17 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - CCPC: u1, // bit offset: 0 desc: Capture/compare preloaded control + /// Capture/compare preloaded control + CCPC: u1 = 0, reserved1: u1 = 0, - CCUS: u1, // bit offset: 2 desc: Capture/compare control update selection - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection + /// Capture/compare control update selection + CCUS: u1 = 0, + /// Capture/compare DMA selection + CCDS: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - OIS1: u1, // bit offset: 8 desc: Output Idle state 1 - OIS1N: u1, // bit offset: 9 desc: Output Idle state 1 + /// Output Idle state 1 + OIS1: u1 = 0, + /// Output Idle state 1 + OIS1N: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -6784,23 +9685,33 @@ pub const TIM17 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - COMIE: u1, // bit offset: 5 desc: COM interrupt enable - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable - BIE: u1, // bit offset: 7 desc: Break interrupt enable - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable + /// COM interrupt enable + COMIE: u1 = 0, + /// Trigger interrupt enable + TIE: u1 = 0, + /// Break interrupt enable + BIE: u1 = 0, + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - COMDE: u1, // bit offset: 13 desc: COM DMA request enable - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// COM DMA request enable + COMDE: u1 = 0, + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -6819,18 +9730,25 @@ pub const TIM17 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - COMIF: u1, // bit offset: 5 desc: COM interrupt flag - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag - BIF: u1, // bit offset: 7 desc: Break interrupt flag + /// COM interrupt flag + COMIF: u1 = 0, + /// Trigger interrupt flag + TIF: u1 = 0, + /// Break interrupt flag + BIF: u1 = 0, reserved4: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -6854,16 +9772,22 @@ pub const TIM17 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - COMG: u1, // bit offset: 5 desc: Capture/Compare control update generation - TG: u1, // bit offset: 6 desc: Trigger generation - BG: u1, // bit offset: 7 desc: Break generation + /// Capture/Compare control update generation + COMG: u1 = 0, + /// Trigger generation + TG: u1 = 0, + /// Break generation + BG: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -6889,12 +9813,17 @@ pub const TIM17 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output Compare 1 fast enable + OC1FE: u1 = 0, + /// Output Compare 1 preload enable + OC1PE: u1 = 0, + /// Output Compare 1 mode + OC1M: u3 = 0, reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, @@ -6904,7 +9833,8 @@ pub const TIM17 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC1M_3: u1, // bit offset: 16 desc: Output Compare 1 mode + /// Output Compare 1 mode + OC1M_3: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -6921,11 +9851,15 @@ pub const TIM17 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -6951,12 +9885,17 @@ pub const TIM17 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity - CC1NE: u1, // bit offset: 2 desc: Capture/Compare 1 complementary output enable - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, + /// Capture/Compare 1 complementary output enable + CC1NE: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -6986,9 +9925,11 @@ pub const TIM17 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, @@ -7004,11 +9945,14 @@ pub const TIM17 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UIFCPY: u1, // bit offset: 31 desc: UIF Copy + /// UIF Copy + UIFCPY: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7026,9 +9970,11 @@ pub const TIM17 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7046,9 +9992,11 @@ pub const TIM17 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 repetition counter register + + /// repetition counter register pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - REP: u8, // bit offset: 0 desc: Repetition counter value + /// Repetition counter value + REP: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -7074,9 +10022,11 @@ pub const TIM17 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7094,17 +10044,27 @@ pub const TIM17 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 break and dead-time register + + /// break and dead-time register pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - DTG: u8, // bit offset: 0 desc: Dead-time generator setup - LOCK: u2, // bit offset: 8 desc: Lock configuration - OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode - OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode - BKE: u1, // bit offset: 12 desc: Break enable - BKP: u1, // bit offset: 13 desc: Break polarity - AOE: u1, // bit offset: 14 desc: Automatic output enable - MOE: u1, // bit offset: 15 desc: Main output enable - BKF: u4, // bit offset: 16 desc: Break filter + /// Dead-time generator setup + DTG: u8 = 0, + /// Lock configuration + LOCK: u2 = 0, + /// Off-state selection for Idle mode + OSSI: u1 = 0, + /// Off-state selection for Run mode + OSSR: u1 = 0, + /// Break enable + BKE: u1 = 0, + /// Break polarity + BKP: u1 = 0, + /// Automatic output enable + AOE: u1 = 0, + /// Main output enable + MOE: u1 = 0, + /// Break filter + BKF: u4 = 0, padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -7118,13 +10078,16 @@ pub const TIM17 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -7145,9 +10108,11 @@ pub const TIM17 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7166,84 +10131,147 @@ pub const TIM17 = extern struct { padding1: u1 = 0, }); }; + +/// Universal synchronous asynchronous receiver transmitter pub const USART1 = extern struct { pub const Address: u32 = 0x40013800; - // byte offset: 0 Control register 1 + + /// Control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - UE: u1, // bit offset: 0 desc: USART enable - UESM: u1, // bit offset: 1 desc: USART enable in Stop mode - RE: u1, // bit offset: 2 desc: Receiver enable - TE: u1, // bit offset: 3 desc: Transmitter enable - IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable - RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable - TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable - TXEIE: u1, // bit offset: 7 desc: interrupt enable - PEIE: u1, // bit offset: 8 desc: PE interrupt enable - PS: u1, // bit offset: 9 desc: Parity selection - PCE: u1, // bit offset: 10 desc: Parity control enable - WAKE: u1, // bit offset: 11 desc: Receiver wakeup method - M: u1, // bit offset: 12 desc: Word length - MME: u1, // bit offset: 13 desc: Mute mode enable - CMIE: u1, // bit offset: 14 desc: Character match interrupt enable - OVER8: u1, // bit offset: 15 desc: Oversampling mode - DEDT: u5, // bit offset: 16 desc: Driver Enable deassertion time - DEAT: u5, // bit offset: 21 desc: Driver Enable assertion time - RTOIE: u1, // bit offset: 26 desc: Receiver timeout interrupt enable - EOBIE: u1, // bit offset: 27 desc: End of Block interrupt enable - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Control register 2 + /// USART enable + UE: u1 = 0, + /// USART enable in Stop mode + UESM: u1 = 0, + /// Receiver enable + RE: u1 = 0, + /// Transmitter enable + TE: u1 = 0, + /// IDLE interrupt enable + IDLEIE: u1 = 0, + /// RXNE interrupt enable + RXNEIE: u1 = 0, + /// Transmission complete interrupt enable + TCIE: u1 = 0, + /// interrupt enable + TXEIE: u1 = 0, + /// PE interrupt enable + PEIE: u1 = 0, + /// Parity selection + PS: u1 = 0, + /// Parity control enable + PCE: u1 = 0, + /// Receiver wakeup method + WAKE: u1 = 0, + /// Word length + M: u1 = 0, + /// Mute mode enable + MME: u1 = 0, + /// Character match interrupt enable + CMIE: u1 = 0, + /// Oversampling mode + OVER8: u1 = 0, + /// Driver Enable deassertion time + DEDT: u5 = 0, + /// Driver Enable assertion time + DEAT: u5 = 0, + /// Receiver timeout interrupt enable + RTOIE: u1 = 0, + /// End of Block interrupt enable + EOBIE: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADDM7: u1, // bit offset: 4 desc: 7-bit Address Detection/4-bit Address Detection - LBDL: u1, // bit offset: 5 desc: LIN break detection length - LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable + /// 7-bit Address Detection/4-bit Address Detection + ADDM7: u1 = 0, + /// LIN break detection length + LBDL: u1 = 0, + /// LIN break detection interrupt enable + LBDIE: u1 = 0, reserved5: u1 = 0, - LBCL: u1, // bit offset: 8 desc: Last bit clock pulse - CPHA: u1, // bit offset: 9 desc: Clock phase - CPOL: u1, // bit offset: 10 desc: Clock polarity - CLKEN: u1, // bit offset: 11 desc: Clock enable - STOP: u2, // bit offset: 12 desc: STOP bits - LINEN: u1, // bit offset: 14 desc: LIN mode enable - SWAP: u1, // bit offset: 15 desc: Swap TX/RX pins - RXINV: u1, // bit offset: 16 desc: RX pin active level inversion - TXINV: u1, // bit offset: 17 desc: TX pin active level inversion - DATAINV: u1, // bit offset: 18 desc: Binary data inversion - MSBFIRST: u1, // bit offset: 19 desc: Most significant bit first - ABREN: u1, // bit offset: 20 desc: Auto baud rate enable - ABRMOD: u2, // bit offset: 21 desc: Auto baud rate mode - RTOEN: u1, // bit offset: 23 desc: Receiver timeout enable - ADD0: u4, // bit offset: 24 desc: Address of the USART node - ADD4: u4, // bit offset: 28 desc: Address of the USART node - }); - // byte offset: 8 Control register 3 + /// Last bit clock pulse + LBCL: u1 = 0, + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Clock enable + CLKEN: u1 = 0, + /// STOP bits + STOP: u2 = 0, + /// LIN mode enable + LINEN: u1 = 0, + /// Swap TX/RX pins + SWAP: u1 = 0, + /// RX pin active level inversion + RXINV: u1 = 0, + /// TX pin active level inversion + TXINV: u1 = 0, + /// Binary data inversion + DATAINV: u1 = 0, + /// Most significant bit first + MSBFIRST: u1 = 0, + /// Auto baud rate enable + ABREN: u1 = 0, + /// Auto baud rate mode + ABRMOD: u2 = 0, + /// Receiver timeout enable + RTOEN: u1 = 0, + /// Address of the USART node + ADD0: u4 = 0, + /// Address of the USART node + ADD4: u4 = 0, + }); + + /// Control register 3 pub const CR3 = mmio(Address + 0x00000008, 32, packed struct { - EIE: u1, // bit offset: 0 desc: Error interrupt enable - IREN: u1, // bit offset: 1 desc: IrDA mode enable - IRLP: u1, // bit offset: 2 desc: IrDA low-power - HDSEL: u1, // bit offset: 3 desc: Half-duplex selection - NACK: u1, // bit offset: 4 desc: Smartcard NACK enable - SCEN: u1, // bit offset: 5 desc: Smartcard mode enable - DMAR: u1, // bit offset: 6 desc: DMA enable receiver - DMAT: u1, // bit offset: 7 desc: DMA enable transmitter - RTSE: u1, // bit offset: 8 desc: RTS enable - CTSE: u1, // bit offset: 9 desc: CTS enable - CTSIE: u1, // bit offset: 10 desc: CTS interrupt enable - ONEBIT: u1, // bit offset: 11 desc: One sample bit method enable - OVRDIS: u1, // bit offset: 12 desc: Overrun Disable - DDRE: u1, // bit offset: 13 desc: DMA Disable on Reception Error - DEM: u1, // bit offset: 14 desc: Driver enable mode - DEP: u1, // bit offset: 15 desc: Driver enable polarity selection - reserved1: u1 = 0, - SCARCNT: u3, // bit offset: 17 desc: Smartcard auto-retry count - WUS: u2, // bit offset: 20 desc: Wakeup from Stop mode interrupt flag selection - WUFIE: u1, // bit offset: 22 desc: Wakeup from Stop mode interrupt enable + /// Error interrupt enable + EIE: u1 = 0, + /// IrDA mode enable + IREN: u1 = 0, + /// IrDA low-power + IRLP: u1 = 0, + /// Half-duplex selection + HDSEL: u1 = 0, + /// Smartcard NACK enable + NACK: u1 = 0, + /// Smartcard mode enable + SCEN: u1 = 0, + /// DMA enable receiver + DMAR: u1 = 0, + /// DMA enable transmitter + DMAT: u1 = 0, + /// RTS enable + RTSE: u1 = 0, + /// CTS enable + CTSE: u1 = 0, + /// CTS interrupt enable + CTSIE: u1 = 0, + /// One sample bit method enable + ONEBIT: u1 = 0, + /// Overrun Disable + OVRDIS: u1 = 0, + /// DMA Disable on Reception Error + DDRE: u1 = 0, + /// Driver enable mode + DEM: u1 = 0, + /// Driver enable polarity selection + DEP: u1 = 0, + reserved1: u1 = 0, + /// Smartcard auto-retry count + SCARCNT: u3 = 0, + /// Wakeup from Stop mode interrupt flag selection + WUS: u2 = 0, + /// Wakeup from Stop mode interrupt enable + WUFIE: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -7254,10 +10282,13 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Baud rate register + + /// Baud rate register pub const BRR = mmio(Address + 0x0000000c, 32, packed struct { - DIV_Fraction: u4, // bit offset: 0 desc: fraction of USARTDIV - DIV_Mantissa: u12, // bit offset: 4 desc: mantissa of USARTDIV + /// fraction of USARTDIV + DIV_Fraction: u4 = 0, + /// mantissa of USARTDIV + DIV_Mantissa: u12 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7275,10 +10306,13 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Guard time and prescaler register + + /// Guard time and prescaler register pub const GTPR = mmio(Address + 0x00000010, 32, packed struct { - PSC: u8, // bit offset: 0 desc: Prescaler value - GT: u8, // bit offset: 8 desc: Guard time value + /// Prescaler value + PSC: u8 = 0, + /// Guard time value + GT: u8 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7296,18 +10330,27 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Receiver timeout register + + /// Receiver timeout register pub const RTOR = mmio(Address + 0x00000014, 32, packed struct { - RTO: u24, // bit offset: 0 desc: Receiver timeout value - BLEN: u8, // bit offset: 24 desc: Block Length + /// Receiver timeout value + RTO: u24 = 0, + /// Block Length + BLEN: u8 = 0, }); - // byte offset: 24 Request register + + /// Request register pub const RQR = mmio(Address + 0x00000018, 32, packed struct { - ABRRQ: u1, // bit offset: 0 desc: Auto baud rate request - SBKRQ: u1, // bit offset: 1 desc: Send break request - MMRQ: u1, // bit offset: 2 desc: Mute mode request - RXFRQ: u1, // bit offset: 3 desc: Receive data flush request - TXFRQ: u1, // bit offset: 4 desc: Transmit data flush request + /// Auto baud rate request + ABRRQ: u1 = 0, + /// Send break request + SBKRQ: u1 = 0, + /// Mute mode request + MMRQ: u1 = 0, + /// Receive data flush request + RXFRQ: u1 = 0, + /// Transmit data flush request + TXFRQ: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -7336,31 +10379,54 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 Interrupt & status register + + /// Interrupt & status register pub const ISR = mmio(Address + 0x0000001c, 32, packed struct { - PE: u1, // bit offset: 0 desc: Parity error - FE: u1, // bit offset: 1 desc: Framing error - NF: u1, // bit offset: 2 desc: Noise detected flag - ORE: u1, // bit offset: 3 desc: Overrun error - IDLE: u1, // bit offset: 4 desc: Idle line detected - RXNE: u1, // bit offset: 5 desc: Read data register not empty - TC: u1, // bit offset: 6 desc: Transmission complete - TXE: u1, // bit offset: 7 desc: Transmit data register empty - LBDF: u1, // bit offset: 8 desc: LIN break detection flag - CTSIF: u1, // bit offset: 9 desc: CTS interrupt flag - CTS: u1, // bit offset: 10 desc: CTS flag - RTOF: u1, // bit offset: 11 desc: Receiver timeout - EOBF: u1, // bit offset: 12 desc: End of block flag - reserved1: u1 = 0, - ABRE: u1, // bit offset: 14 desc: Auto baud rate error - ABRF: u1, // bit offset: 15 desc: Auto baud rate flag - BUSY: u1, // bit offset: 16 desc: Busy flag - CMF: u1, // bit offset: 17 desc: character match flag - SBKF: u1, // bit offset: 18 desc: Send break flag - RWU: u1, // bit offset: 19 desc: Receiver wakeup from Mute mode - WUF: u1, // bit offset: 20 desc: Wakeup from Stop mode flag - TEACK: u1, // bit offset: 21 desc: Transmit enable acknowledge flag - REACK: u1, // bit offset: 22 desc: Receive enable acknowledge flag + /// Parity error + PE: u1 = 0, + /// Framing error + FE: u1 = 0, + /// Noise detected flag + NF: u1 = 0, + /// Overrun error + ORE: u1 = 0, + /// Idle line detected + IDLE: u1 = 0, + /// Read data register not empty + RXNE: u1 = 0, + /// Transmission complete + TC: u1 = 0, + /// Transmit data register empty + TXE: u1 = 0, + /// LIN break detection flag + LBDF: u1 = 0, + /// CTS interrupt flag + CTSIF: u1 = 0, + /// CTS flag + CTS: u1 = 0, + /// Receiver timeout + RTOF: u1 = 0, + /// End of block flag + EOBF: u1 = 0, + reserved1: u1 = 0, + /// Auto baud rate error + ABRE: u1 = 0, + /// Auto baud rate flag + ABRF: u1 = 0, + /// Busy flag + BUSY: u1 = 0, + /// character match flag + CMF: u1 = 0, + /// Send break flag + SBKF: u1 = 0, + /// Receiver wakeup from Mute mode + RWU: u1 = 0, + /// Wakeup from Stop mode flag + WUF: u1 = 0, + /// Transmit enable acknowledge flag + TEACK: u1 = 0, + /// Receive enable acknowledge flag + REACK: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -7371,29 +10437,42 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 Interrupt flag clear register + + /// Interrupt flag clear register pub const ICR = mmio(Address + 0x00000020, 32, packed struct { - PECF: u1, // bit offset: 0 desc: Parity error clear flag - FECF: u1, // bit offset: 1 desc: Framing error clear flag - NCF: u1, // bit offset: 2 desc: Noise detected clear flag - ORECF: u1, // bit offset: 3 desc: Overrun error clear flag - IDLECF: u1, // bit offset: 4 desc: Idle line detected clear flag - reserved1: u1 = 0, - TCCF: u1, // bit offset: 6 desc: Transmission complete clear flag - reserved2: u1 = 0, - LBDCF: u1, // bit offset: 8 desc: LIN break detection clear flag - CTSCF: u1, // bit offset: 9 desc: CTS clear flag + /// Parity error clear flag + PECF: u1 = 0, + /// Framing error clear flag + FECF: u1 = 0, + /// Noise detected clear flag + NCF: u1 = 0, + /// Overrun error clear flag + ORECF: u1 = 0, + /// Idle line detected clear flag + IDLECF: u1 = 0, + reserved1: u1 = 0, + /// Transmission complete clear flag + TCCF: u1 = 0, + reserved2: u1 = 0, + /// LIN break detection clear flag + LBDCF: u1 = 0, + /// CTS clear flag + CTSCF: u1 = 0, reserved3: u1 = 0, - RTOCF: u1, // bit offset: 11 desc: Receiver timeout clear flag - EOBCF: u1, // bit offset: 12 desc: End of timeout clear flag + /// Receiver timeout clear flag + RTOCF: u1 = 0, + /// End of timeout clear flag + EOBCF: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - CMCF: u1, // bit offset: 17 desc: Character match clear flag + /// Character match clear flag + CMCF: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, - WUCF: u1, // bit offset: 20 desc: Wakeup from Stop mode clear flag + /// Wakeup from Stop mode clear flag + WUCF: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, @@ -7406,9 +10485,11 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 Receive data register + + /// Receive data register pub const RDR = mmio(Address + 0x00000024, 32, packed struct { - RDR: u9, // bit offset: 0 desc: Receive data value + /// Receive data value + RDR: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -7433,9 +10514,11 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 Transmit data register + + /// Transmit data register pub const TDR = mmio(Address + 0x00000028, 32, packed struct { - TDR: u9, // bit offset: 0 desc: Transmit data value + /// Transmit data value + TDR: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -7461,84 +10544,147 @@ pub const USART1 = extern struct { padding1: u1 = 0, }); }; + +/// Universal synchronous asynchronous receiver transmitter pub const USART2 = extern struct { pub const Address: u32 = 0x40004400; - // byte offset: 0 Control register 1 + + /// Control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - UE: u1, // bit offset: 0 desc: USART enable - UESM: u1, // bit offset: 1 desc: USART enable in Stop mode - RE: u1, // bit offset: 2 desc: Receiver enable - TE: u1, // bit offset: 3 desc: Transmitter enable - IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable - RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable - TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable - TXEIE: u1, // bit offset: 7 desc: interrupt enable - PEIE: u1, // bit offset: 8 desc: PE interrupt enable - PS: u1, // bit offset: 9 desc: Parity selection - PCE: u1, // bit offset: 10 desc: Parity control enable - WAKE: u1, // bit offset: 11 desc: Receiver wakeup method - M: u1, // bit offset: 12 desc: Word length - MME: u1, // bit offset: 13 desc: Mute mode enable - CMIE: u1, // bit offset: 14 desc: Character match interrupt enable - OVER8: u1, // bit offset: 15 desc: Oversampling mode - DEDT: u5, // bit offset: 16 desc: Driver Enable deassertion time - DEAT: u5, // bit offset: 21 desc: Driver Enable assertion time - RTOIE: u1, // bit offset: 26 desc: Receiver timeout interrupt enable - EOBIE: u1, // bit offset: 27 desc: End of Block interrupt enable - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Control register 2 + /// USART enable + UE: u1 = 0, + /// USART enable in Stop mode + UESM: u1 = 0, + /// Receiver enable + RE: u1 = 0, + /// Transmitter enable + TE: u1 = 0, + /// IDLE interrupt enable + IDLEIE: u1 = 0, + /// RXNE interrupt enable + RXNEIE: u1 = 0, + /// Transmission complete interrupt enable + TCIE: u1 = 0, + /// interrupt enable + TXEIE: u1 = 0, + /// PE interrupt enable + PEIE: u1 = 0, + /// Parity selection + PS: u1 = 0, + /// Parity control enable + PCE: u1 = 0, + /// Receiver wakeup method + WAKE: u1 = 0, + /// Word length + M: u1 = 0, + /// Mute mode enable + MME: u1 = 0, + /// Character match interrupt enable + CMIE: u1 = 0, + /// Oversampling mode + OVER8: u1 = 0, + /// Driver Enable deassertion time + DEDT: u5 = 0, + /// Driver Enable assertion time + DEAT: u5 = 0, + /// Receiver timeout interrupt enable + RTOIE: u1 = 0, + /// End of Block interrupt enable + EOBIE: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADDM7: u1, // bit offset: 4 desc: 7-bit Address Detection/4-bit Address Detection - LBDL: u1, // bit offset: 5 desc: LIN break detection length - LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable + /// 7-bit Address Detection/4-bit Address Detection + ADDM7: u1 = 0, + /// LIN break detection length + LBDL: u1 = 0, + /// LIN break detection interrupt enable + LBDIE: u1 = 0, reserved5: u1 = 0, - LBCL: u1, // bit offset: 8 desc: Last bit clock pulse - CPHA: u1, // bit offset: 9 desc: Clock phase - CPOL: u1, // bit offset: 10 desc: Clock polarity - CLKEN: u1, // bit offset: 11 desc: Clock enable - STOP: u2, // bit offset: 12 desc: STOP bits - LINEN: u1, // bit offset: 14 desc: LIN mode enable - SWAP: u1, // bit offset: 15 desc: Swap TX/RX pins - RXINV: u1, // bit offset: 16 desc: RX pin active level inversion - TXINV: u1, // bit offset: 17 desc: TX pin active level inversion - DATAINV: u1, // bit offset: 18 desc: Binary data inversion - MSBFIRST: u1, // bit offset: 19 desc: Most significant bit first - ABREN: u1, // bit offset: 20 desc: Auto baud rate enable - ABRMOD: u2, // bit offset: 21 desc: Auto baud rate mode - RTOEN: u1, // bit offset: 23 desc: Receiver timeout enable - ADD0: u4, // bit offset: 24 desc: Address of the USART node - ADD4: u4, // bit offset: 28 desc: Address of the USART node - }); - // byte offset: 8 Control register 3 + /// Last bit clock pulse + LBCL: u1 = 0, + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Clock enable + CLKEN: u1 = 0, + /// STOP bits + STOP: u2 = 0, + /// LIN mode enable + LINEN: u1 = 0, + /// Swap TX/RX pins + SWAP: u1 = 0, + /// RX pin active level inversion + RXINV: u1 = 0, + /// TX pin active level inversion + TXINV: u1 = 0, + /// Binary data inversion + DATAINV: u1 = 0, + /// Most significant bit first + MSBFIRST: u1 = 0, + /// Auto baud rate enable + ABREN: u1 = 0, + /// Auto baud rate mode + ABRMOD: u2 = 0, + /// Receiver timeout enable + RTOEN: u1 = 0, + /// Address of the USART node + ADD0: u4 = 0, + /// Address of the USART node + ADD4: u4 = 0, + }); + + /// Control register 3 pub const CR3 = mmio(Address + 0x00000008, 32, packed struct { - EIE: u1, // bit offset: 0 desc: Error interrupt enable - IREN: u1, // bit offset: 1 desc: IrDA mode enable - IRLP: u1, // bit offset: 2 desc: IrDA low-power - HDSEL: u1, // bit offset: 3 desc: Half-duplex selection - NACK: u1, // bit offset: 4 desc: Smartcard NACK enable - SCEN: u1, // bit offset: 5 desc: Smartcard mode enable - DMAR: u1, // bit offset: 6 desc: DMA enable receiver - DMAT: u1, // bit offset: 7 desc: DMA enable transmitter - RTSE: u1, // bit offset: 8 desc: RTS enable - CTSE: u1, // bit offset: 9 desc: CTS enable - CTSIE: u1, // bit offset: 10 desc: CTS interrupt enable - ONEBIT: u1, // bit offset: 11 desc: One sample bit method enable - OVRDIS: u1, // bit offset: 12 desc: Overrun Disable - DDRE: u1, // bit offset: 13 desc: DMA Disable on Reception Error - DEM: u1, // bit offset: 14 desc: Driver enable mode - DEP: u1, // bit offset: 15 desc: Driver enable polarity selection - reserved1: u1 = 0, - SCARCNT: u3, // bit offset: 17 desc: Smartcard auto-retry count - WUS: u2, // bit offset: 20 desc: Wakeup from Stop mode interrupt flag selection - WUFIE: u1, // bit offset: 22 desc: Wakeup from Stop mode interrupt enable + /// Error interrupt enable + EIE: u1 = 0, + /// IrDA mode enable + IREN: u1 = 0, + /// IrDA low-power + IRLP: u1 = 0, + /// Half-duplex selection + HDSEL: u1 = 0, + /// Smartcard NACK enable + NACK: u1 = 0, + /// Smartcard mode enable + SCEN: u1 = 0, + /// DMA enable receiver + DMAR: u1 = 0, + /// DMA enable transmitter + DMAT: u1 = 0, + /// RTS enable + RTSE: u1 = 0, + /// CTS enable + CTSE: u1 = 0, + /// CTS interrupt enable + CTSIE: u1 = 0, + /// One sample bit method enable + ONEBIT: u1 = 0, + /// Overrun Disable + OVRDIS: u1 = 0, + /// DMA Disable on Reception Error + DDRE: u1 = 0, + /// Driver enable mode + DEM: u1 = 0, + /// Driver enable polarity selection + DEP: u1 = 0, + reserved1: u1 = 0, + /// Smartcard auto-retry count + SCARCNT: u3 = 0, + /// Wakeup from Stop mode interrupt flag selection + WUS: u2 = 0, + /// Wakeup from Stop mode interrupt enable + WUFIE: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -7549,10 +10695,13 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Baud rate register + + /// Baud rate register pub const BRR = mmio(Address + 0x0000000c, 32, packed struct { - DIV_Fraction: u4, // bit offset: 0 desc: fraction of USARTDIV - DIV_Mantissa: u12, // bit offset: 4 desc: mantissa of USARTDIV + /// fraction of USARTDIV + DIV_Fraction: u4 = 0, + /// mantissa of USARTDIV + DIV_Mantissa: u12 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7570,10 +10719,13 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Guard time and prescaler register + + /// Guard time and prescaler register pub const GTPR = mmio(Address + 0x00000010, 32, packed struct { - PSC: u8, // bit offset: 0 desc: Prescaler value - GT: u8, // bit offset: 8 desc: Guard time value + /// Prescaler value + PSC: u8 = 0, + /// Guard time value + GT: u8 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7591,18 +10743,27 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Receiver timeout register + + /// Receiver timeout register pub const RTOR = mmio(Address + 0x00000014, 32, packed struct { - RTO: u24, // bit offset: 0 desc: Receiver timeout value - BLEN: u8, // bit offset: 24 desc: Block Length + /// Receiver timeout value + RTO: u24 = 0, + /// Block Length + BLEN: u8 = 0, }); - // byte offset: 24 Request register + + /// Request register pub const RQR = mmio(Address + 0x00000018, 32, packed struct { - ABRRQ: u1, // bit offset: 0 desc: Auto baud rate request - SBKRQ: u1, // bit offset: 1 desc: Send break request - MMRQ: u1, // bit offset: 2 desc: Mute mode request - RXFRQ: u1, // bit offset: 3 desc: Receive data flush request - TXFRQ: u1, // bit offset: 4 desc: Transmit data flush request + /// Auto baud rate request + ABRRQ: u1 = 0, + /// Send break request + SBKRQ: u1 = 0, + /// Mute mode request + MMRQ: u1 = 0, + /// Receive data flush request + RXFRQ: u1 = 0, + /// Transmit data flush request + TXFRQ: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -7631,31 +10792,54 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 Interrupt & status register + + /// Interrupt & status register pub const ISR = mmio(Address + 0x0000001c, 32, packed struct { - PE: u1, // bit offset: 0 desc: Parity error - FE: u1, // bit offset: 1 desc: Framing error - NF: u1, // bit offset: 2 desc: Noise detected flag - ORE: u1, // bit offset: 3 desc: Overrun error - IDLE: u1, // bit offset: 4 desc: Idle line detected - RXNE: u1, // bit offset: 5 desc: Read data register not empty - TC: u1, // bit offset: 6 desc: Transmission complete - TXE: u1, // bit offset: 7 desc: Transmit data register empty - LBDF: u1, // bit offset: 8 desc: LIN break detection flag - CTSIF: u1, // bit offset: 9 desc: CTS interrupt flag - CTS: u1, // bit offset: 10 desc: CTS flag - RTOF: u1, // bit offset: 11 desc: Receiver timeout - EOBF: u1, // bit offset: 12 desc: End of block flag - reserved1: u1 = 0, - ABRE: u1, // bit offset: 14 desc: Auto baud rate error - ABRF: u1, // bit offset: 15 desc: Auto baud rate flag - BUSY: u1, // bit offset: 16 desc: Busy flag - CMF: u1, // bit offset: 17 desc: character match flag - SBKF: u1, // bit offset: 18 desc: Send break flag - RWU: u1, // bit offset: 19 desc: Receiver wakeup from Mute mode - WUF: u1, // bit offset: 20 desc: Wakeup from Stop mode flag - TEACK: u1, // bit offset: 21 desc: Transmit enable acknowledge flag - REACK: u1, // bit offset: 22 desc: Receive enable acknowledge flag + /// Parity error + PE: u1 = 0, + /// Framing error + FE: u1 = 0, + /// Noise detected flag + NF: u1 = 0, + /// Overrun error + ORE: u1 = 0, + /// Idle line detected + IDLE: u1 = 0, + /// Read data register not empty + RXNE: u1 = 0, + /// Transmission complete + TC: u1 = 0, + /// Transmit data register empty + TXE: u1 = 0, + /// LIN break detection flag + LBDF: u1 = 0, + /// CTS interrupt flag + CTSIF: u1 = 0, + /// CTS flag + CTS: u1 = 0, + /// Receiver timeout + RTOF: u1 = 0, + /// End of block flag + EOBF: u1 = 0, + reserved1: u1 = 0, + /// Auto baud rate error + ABRE: u1 = 0, + /// Auto baud rate flag + ABRF: u1 = 0, + /// Busy flag + BUSY: u1 = 0, + /// character match flag + CMF: u1 = 0, + /// Send break flag + SBKF: u1 = 0, + /// Receiver wakeup from Mute mode + RWU: u1 = 0, + /// Wakeup from Stop mode flag + WUF: u1 = 0, + /// Transmit enable acknowledge flag + TEACK: u1 = 0, + /// Receive enable acknowledge flag + REACK: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -7666,29 +10850,42 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 Interrupt flag clear register + + /// Interrupt flag clear register pub const ICR = mmio(Address + 0x00000020, 32, packed struct { - PECF: u1, // bit offset: 0 desc: Parity error clear flag - FECF: u1, // bit offset: 1 desc: Framing error clear flag - NCF: u1, // bit offset: 2 desc: Noise detected clear flag - ORECF: u1, // bit offset: 3 desc: Overrun error clear flag - IDLECF: u1, // bit offset: 4 desc: Idle line detected clear flag - reserved1: u1 = 0, - TCCF: u1, // bit offset: 6 desc: Transmission complete clear flag - reserved2: u1 = 0, - LBDCF: u1, // bit offset: 8 desc: LIN break detection clear flag - CTSCF: u1, // bit offset: 9 desc: CTS clear flag + /// Parity error clear flag + PECF: u1 = 0, + /// Framing error clear flag + FECF: u1 = 0, + /// Noise detected clear flag + NCF: u1 = 0, + /// Overrun error clear flag + ORECF: u1 = 0, + /// Idle line detected clear flag + IDLECF: u1 = 0, + reserved1: u1 = 0, + /// Transmission complete clear flag + TCCF: u1 = 0, + reserved2: u1 = 0, + /// LIN break detection clear flag + LBDCF: u1 = 0, + /// CTS clear flag + CTSCF: u1 = 0, reserved3: u1 = 0, - RTOCF: u1, // bit offset: 11 desc: Receiver timeout clear flag - EOBCF: u1, // bit offset: 12 desc: End of timeout clear flag + /// Receiver timeout clear flag + RTOCF: u1 = 0, + /// End of timeout clear flag + EOBCF: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - CMCF: u1, // bit offset: 17 desc: Character match clear flag + /// Character match clear flag + CMCF: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, - WUCF: u1, // bit offset: 20 desc: Wakeup from Stop mode clear flag + /// Wakeup from Stop mode clear flag + WUCF: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, @@ -7701,9 +10898,11 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 Receive data register + + /// Receive data register pub const RDR = mmio(Address + 0x00000024, 32, packed struct { - RDR: u9, // bit offset: 0 desc: Receive data value + /// Receive data value + RDR: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -7728,9 +10927,11 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 Transmit data register + + /// Transmit data register pub const TDR = mmio(Address + 0x00000028, 32, packed struct { - TDR: u9, // bit offset: 0 desc: Transmit data value + /// Transmit data value + TDR: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -7756,84 +10957,147 @@ pub const USART2 = extern struct { padding1: u1 = 0, }); }; + +/// Universal synchronous asynchronous receiver transmitter pub const USART3 = extern struct { pub const Address: u32 = 0x40004800; - // byte offset: 0 Control register 1 + + /// Control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - UE: u1, // bit offset: 0 desc: USART enable - UESM: u1, // bit offset: 1 desc: USART enable in Stop mode - RE: u1, // bit offset: 2 desc: Receiver enable - TE: u1, // bit offset: 3 desc: Transmitter enable - IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable - RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable - TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable - TXEIE: u1, // bit offset: 7 desc: interrupt enable - PEIE: u1, // bit offset: 8 desc: PE interrupt enable - PS: u1, // bit offset: 9 desc: Parity selection - PCE: u1, // bit offset: 10 desc: Parity control enable - WAKE: u1, // bit offset: 11 desc: Receiver wakeup method - M: u1, // bit offset: 12 desc: Word length - MME: u1, // bit offset: 13 desc: Mute mode enable - CMIE: u1, // bit offset: 14 desc: Character match interrupt enable - OVER8: u1, // bit offset: 15 desc: Oversampling mode - DEDT: u5, // bit offset: 16 desc: Driver Enable deassertion time - DEAT: u5, // bit offset: 21 desc: Driver Enable assertion time - RTOIE: u1, // bit offset: 26 desc: Receiver timeout interrupt enable - EOBIE: u1, // bit offset: 27 desc: End of Block interrupt enable - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Control register 2 + /// USART enable + UE: u1 = 0, + /// USART enable in Stop mode + UESM: u1 = 0, + /// Receiver enable + RE: u1 = 0, + /// Transmitter enable + TE: u1 = 0, + /// IDLE interrupt enable + IDLEIE: u1 = 0, + /// RXNE interrupt enable + RXNEIE: u1 = 0, + /// Transmission complete interrupt enable + TCIE: u1 = 0, + /// interrupt enable + TXEIE: u1 = 0, + /// PE interrupt enable + PEIE: u1 = 0, + /// Parity selection + PS: u1 = 0, + /// Parity control enable + PCE: u1 = 0, + /// Receiver wakeup method + WAKE: u1 = 0, + /// Word length + M: u1 = 0, + /// Mute mode enable + MME: u1 = 0, + /// Character match interrupt enable + CMIE: u1 = 0, + /// Oversampling mode + OVER8: u1 = 0, + /// Driver Enable deassertion time + DEDT: u5 = 0, + /// Driver Enable assertion time + DEAT: u5 = 0, + /// Receiver timeout interrupt enable + RTOIE: u1 = 0, + /// End of Block interrupt enable + EOBIE: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADDM7: u1, // bit offset: 4 desc: 7-bit Address Detection/4-bit Address Detection - LBDL: u1, // bit offset: 5 desc: LIN break detection length - LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable + /// 7-bit Address Detection/4-bit Address Detection + ADDM7: u1 = 0, + /// LIN break detection length + LBDL: u1 = 0, + /// LIN break detection interrupt enable + LBDIE: u1 = 0, reserved5: u1 = 0, - LBCL: u1, // bit offset: 8 desc: Last bit clock pulse - CPHA: u1, // bit offset: 9 desc: Clock phase - CPOL: u1, // bit offset: 10 desc: Clock polarity - CLKEN: u1, // bit offset: 11 desc: Clock enable - STOP: u2, // bit offset: 12 desc: STOP bits - LINEN: u1, // bit offset: 14 desc: LIN mode enable - SWAP: u1, // bit offset: 15 desc: Swap TX/RX pins - RXINV: u1, // bit offset: 16 desc: RX pin active level inversion - TXINV: u1, // bit offset: 17 desc: TX pin active level inversion - DATAINV: u1, // bit offset: 18 desc: Binary data inversion - MSBFIRST: u1, // bit offset: 19 desc: Most significant bit first - ABREN: u1, // bit offset: 20 desc: Auto baud rate enable - ABRMOD: u2, // bit offset: 21 desc: Auto baud rate mode - RTOEN: u1, // bit offset: 23 desc: Receiver timeout enable - ADD0: u4, // bit offset: 24 desc: Address of the USART node - ADD4: u4, // bit offset: 28 desc: Address of the USART node - }); - // byte offset: 8 Control register 3 + /// Last bit clock pulse + LBCL: u1 = 0, + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Clock enable + CLKEN: u1 = 0, + /// STOP bits + STOP: u2 = 0, + /// LIN mode enable + LINEN: u1 = 0, + /// Swap TX/RX pins + SWAP: u1 = 0, + /// RX pin active level inversion + RXINV: u1 = 0, + /// TX pin active level inversion + TXINV: u1 = 0, + /// Binary data inversion + DATAINV: u1 = 0, + /// Most significant bit first + MSBFIRST: u1 = 0, + /// Auto baud rate enable + ABREN: u1 = 0, + /// Auto baud rate mode + ABRMOD: u2 = 0, + /// Receiver timeout enable + RTOEN: u1 = 0, + /// Address of the USART node + ADD0: u4 = 0, + /// Address of the USART node + ADD4: u4 = 0, + }); + + /// Control register 3 pub const CR3 = mmio(Address + 0x00000008, 32, packed struct { - EIE: u1, // bit offset: 0 desc: Error interrupt enable - IREN: u1, // bit offset: 1 desc: IrDA mode enable - IRLP: u1, // bit offset: 2 desc: IrDA low-power - HDSEL: u1, // bit offset: 3 desc: Half-duplex selection - NACK: u1, // bit offset: 4 desc: Smartcard NACK enable - SCEN: u1, // bit offset: 5 desc: Smartcard mode enable - DMAR: u1, // bit offset: 6 desc: DMA enable receiver - DMAT: u1, // bit offset: 7 desc: DMA enable transmitter - RTSE: u1, // bit offset: 8 desc: RTS enable - CTSE: u1, // bit offset: 9 desc: CTS enable - CTSIE: u1, // bit offset: 10 desc: CTS interrupt enable - ONEBIT: u1, // bit offset: 11 desc: One sample bit method enable - OVRDIS: u1, // bit offset: 12 desc: Overrun Disable - DDRE: u1, // bit offset: 13 desc: DMA Disable on Reception Error - DEM: u1, // bit offset: 14 desc: Driver enable mode - DEP: u1, // bit offset: 15 desc: Driver enable polarity selection - reserved1: u1 = 0, - SCARCNT: u3, // bit offset: 17 desc: Smartcard auto-retry count - WUS: u2, // bit offset: 20 desc: Wakeup from Stop mode interrupt flag selection - WUFIE: u1, // bit offset: 22 desc: Wakeup from Stop mode interrupt enable + /// Error interrupt enable + EIE: u1 = 0, + /// IrDA mode enable + IREN: u1 = 0, + /// IrDA low-power + IRLP: u1 = 0, + /// Half-duplex selection + HDSEL: u1 = 0, + /// Smartcard NACK enable + NACK: u1 = 0, + /// Smartcard mode enable + SCEN: u1 = 0, + /// DMA enable receiver + DMAR: u1 = 0, + /// DMA enable transmitter + DMAT: u1 = 0, + /// RTS enable + RTSE: u1 = 0, + /// CTS enable + CTSE: u1 = 0, + /// CTS interrupt enable + CTSIE: u1 = 0, + /// One sample bit method enable + ONEBIT: u1 = 0, + /// Overrun Disable + OVRDIS: u1 = 0, + /// DMA Disable on Reception Error + DDRE: u1 = 0, + /// Driver enable mode + DEM: u1 = 0, + /// Driver enable polarity selection + DEP: u1 = 0, + reserved1: u1 = 0, + /// Smartcard auto-retry count + SCARCNT: u3 = 0, + /// Wakeup from Stop mode interrupt flag selection + WUS: u2 = 0, + /// Wakeup from Stop mode interrupt enable + WUFIE: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -7844,10 +11108,13 @@ pub const USART3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Baud rate register + + /// Baud rate register pub const BRR = mmio(Address + 0x0000000c, 32, packed struct { - DIV_Fraction: u4, // bit offset: 0 desc: fraction of USARTDIV - DIV_Mantissa: u12, // bit offset: 4 desc: mantissa of USARTDIV + /// fraction of USARTDIV + DIV_Fraction: u4 = 0, + /// mantissa of USARTDIV + DIV_Mantissa: u12 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7865,10 +11132,13 @@ pub const USART3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Guard time and prescaler register + + /// Guard time and prescaler register pub const GTPR = mmio(Address + 0x00000010, 32, packed struct { - PSC: u8, // bit offset: 0 desc: Prescaler value - GT: u8, // bit offset: 8 desc: Guard time value + /// Prescaler value + PSC: u8 = 0, + /// Guard time value + GT: u8 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7886,18 +11156,27 @@ pub const USART3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Receiver timeout register + + /// Receiver timeout register pub const RTOR = mmio(Address + 0x00000014, 32, packed struct { - RTO: u24, // bit offset: 0 desc: Receiver timeout value - BLEN: u8, // bit offset: 24 desc: Block Length + /// Receiver timeout value + RTO: u24 = 0, + /// Block Length + BLEN: u8 = 0, }); - // byte offset: 24 Request register + + /// Request register pub const RQR = mmio(Address + 0x00000018, 32, packed struct { - ABRRQ: u1, // bit offset: 0 desc: Auto baud rate request - SBKRQ: u1, // bit offset: 1 desc: Send break request - MMRQ: u1, // bit offset: 2 desc: Mute mode request - RXFRQ: u1, // bit offset: 3 desc: Receive data flush request - TXFRQ: u1, // bit offset: 4 desc: Transmit data flush request + /// Auto baud rate request + ABRRQ: u1 = 0, + /// Send break request + SBKRQ: u1 = 0, + /// Mute mode request + MMRQ: u1 = 0, + /// Receive data flush request + RXFRQ: u1 = 0, + /// Transmit data flush request + TXFRQ: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -7926,31 +11205,54 @@ pub const USART3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 Interrupt & status register + + /// Interrupt & status register pub const ISR = mmio(Address + 0x0000001c, 32, packed struct { - PE: u1, // bit offset: 0 desc: Parity error - FE: u1, // bit offset: 1 desc: Framing error - NF: u1, // bit offset: 2 desc: Noise detected flag - ORE: u1, // bit offset: 3 desc: Overrun error - IDLE: u1, // bit offset: 4 desc: Idle line detected - RXNE: u1, // bit offset: 5 desc: Read data register not empty - TC: u1, // bit offset: 6 desc: Transmission complete - TXE: u1, // bit offset: 7 desc: Transmit data register empty - LBDF: u1, // bit offset: 8 desc: LIN break detection flag - CTSIF: u1, // bit offset: 9 desc: CTS interrupt flag - CTS: u1, // bit offset: 10 desc: CTS flag - RTOF: u1, // bit offset: 11 desc: Receiver timeout - EOBF: u1, // bit offset: 12 desc: End of block flag - reserved1: u1 = 0, - ABRE: u1, // bit offset: 14 desc: Auto baud rate error - ABRF: u1, // bit offset: 15 desc: Auto baud rate flag - BUSY: u1, // bit offset: 16 desc: Busy flag - CMF: u1, // bit offset: 17 desc: character match flag - SBKF: u1, // bit offset: 18 desc: Send break flag - RWU: u1, // bit offset: 19 desc: Receiver wakeup from Mute mode - WUF: u1, // bit offset: 20 desc: Wakeup from Stop mode flag - TEACK: u1, // bit offset: 21 desc: Transmit enable acknowledge flag - REACK: u1, // bit offset: 22 desc: Receive enable acknowledge flag + /// Parity error + PE: u1 = 0, + /// Framing error + FE: u1 = 0, + /// Noise detected flag + NF: u1 = 0, + /// Overrun error + ORE: u1 = 0, + /// Idle line detected + IDLE: u1 = 0, + /// Read data register not empty + RXNE: u1 = 0, + /// Transmission complete + TC: u1 = 0, + /// Transmit data register empty + TXE: u1 = 0, + /// LIN break detection flag + LBDF: u1 = 0, + /// CTS interrupt flag + CTSIF: u1 = 0, + /// CTS flag + CTS: u1 = 0, + /// Receiver timeout + RTOF: u1 = 0, + /// End of block flag + EOBF: u1 = 0, + reserved1: u1 = 0, + /// Auto baud rate error + ABRE: u1 = 0, + /// Auto baud rate flag + ABRF: u1 = 0, + /// Busy flag + BUSY: u1 = 0, + /// character match flag + CMF: u1 = 0, + /// Send break flag + SBKF: u1 = 0, + /// Receiver wakeup from Mute mode + RWU: u1 = 0, + /// Wakeup from Stop mode flag + WUF: u1 = 0, + /// Transmit enable acknowledge flag + TEACK: u1 = 0, + /// Receive enable acknowledge flag + REACK: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -7961,29 +11263,42 @@ pub const USART3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 Interrupt flag clear register + + /// Interrupt flag clear register pub const ICR = mmio(Address + 0x00000020, 32, packed struct { - PECF: u1, // bit offset: 0 desc: Parity error clear flag - FECF: u1, // bit offset: 1 desc: Framing error clear flag - NCF: u1, // bit offset: 2 desc: Noise detected clear flag - ORECF: u1, // bit offset: 3 desc: Overrun error clear flag - IDLECF: u1, // bit offset: 4 desc: Idle line detected clear flag - reserved1: u1 = 0, - TCCF: u1, // bit offset: 6 desc: Transmission complete clear flag - reserved2: u1 = 0, - LBDCF: u1, // bit offset: 8 desc: LIN break detection clear flag - CTSCF: u1, // bit offset: 9 desc: CTS clear flag + /// Parity error clear flag + PECF: u1 = 0, + /// Framing error clear flag + FECF: u1 = 0, + /// Noise detected clear flag + NCF: u1 = 0, + /// Overrun error clear flag + ORECF: u1 = 0, + /// Idle line detected clear flag + IDLECF: u1 = 0, + reserved1: u1 = 0, + /// Transmission complete clear flag + TCCF: u1 = 0, + reserved2: u1 = 0, + /// LIN break detection clear flag + LBDCF: u1 = 0, + /// CTS clear flag + CTSCF: u1 = 0, reserved3: u1 = 0, - RTOCF: u1, // bit offset: 11 desc: Receiver timeout clear flag - EOBCF: u1, // bit offset: 12 desc: End of timeout clear flag + /// Receiver timeout clear flag + RTOCF: u1 = 0, + /// End of timeout clear flag + EOBCF: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - CMCF: u1, // bit offset: 17 desc: Character match clear flag + /// Character match clear flag + CMCF: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, - WUCF: u1, // bit offset: 20 desc: Wakeup from Stop mode clear flag + /// Wakeup from Stop mode clear flag + WUCF: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, @@ -7996,9 +11311,11 @@ pub const USART3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 Receive data register + + /// Receive data register pub const RDR = mmio(Address + 0x00000024, 32, packed struct { - RDR: u9, // bit offset: 0 desc: Receive data value + /// Receive data value + RDR: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -8023,9 +11340,11 @@ pub const USART3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 Transmit data register + + /// Transmit data register pub const TDR = mmio(Address + 0x00000028, 32, packed struct { - TDR: u9, // bit offset: 0 desc: Transmit data value + /// Transmit data value + TDR: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -8051,84 +11370,147 @@ pub const USART3 = extern struct { padding1: u1 = 0, }); }; + +/// Universal synchronous asynchronous receiver transmitter pub const UART4 = extern struct { pub const Address: u32 = 0x40004c00; - // byte offset: 0 Control register 1 + + /// Control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - UE: u1, // bit offset: 0 desc: USART enable - UESM: u1, // bit offset: 1 desc: USART enable in Stop mode - RE: u1, // bit offset: 2 desc: Receiver enable - TE: u1, // bit offset: 3 desc: Transmitter enable - IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable - RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable - TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable - TXEIE: u1, // bit offset: 7 desc: interrupt enable - PEIE: u1, // bit offset: 8 desc: PE interrupt enable - PS: u1, // bit offset: 9 desc: Parity selection - PCE: u1, // bit offset: 10 desc: Parity control enable - WAKE: u1, // bit offset: 11 desc: Receiver wakeup method - M: u1, // bit offset: 12 desc: Word length - MME: u1, // bit offset: 13 desc: Mute mode enable - CMIE: u1, // bit offset: 14 desc: Character match interrupt enable - OVER8: u1, // bit offset: 15 desc: Oversampling mode - DEDT: u5, // bit offset: 16 desc: Driver Enable deassertion time - DEAT: u5, // bit offset: 21 desc: Driver Enable assertion time - RTOIE: u1, // bit offset: 26 desc: Receiver timeout interrupt enable - EOBIE: u1, // bit offset: 27 desc: End of Block interrupt enable - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Control register 2 + /// USART enable + UE: u1 = 0, + /// USART enable in Stop mode + UESM: u1 = 0, + /// Receiver enable + RE: u1 = 0, + /// Transmitter enable + TE: u1 = 0, + /// IDLE interrupt enable + IDLEIE: u1 = 0, + /// RXNE interrupt enable + RXNEIE: u1 = 0, + /// Transmission complete interrupt enable + TCIE: u1 = 0, + /// interrupt enable + TXEIE: u1 = 0, + /// PE interrupt enable + PEIE: u1 = 0, + /// Parity selection + PS: u1 = 0, + /// Parity control enable + PCE: u1 = 0, + /// Receiver wakeup method + WAKE: u1 = 0, + /// Word length + M: u1 = 0, + /// Mute mode enable + MME: u1 = 0, + /// Character match interrupt enable + CMIE: u1 = 0, + /// Oversampling mode + OVER8: u1 = 0, + /// Driver Enable deassertion time + DEDT: u5 = 0, + /// Driver Enable assertion time + DEAT: u5 = 0, + /// Receiver timeout interrupt enable + RTOIE: u1 = 0, + /// End of Block interrupt enable + EOBIE: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADDM7: u1, // bit offset: 4 desc: 7-bit Address Detection/4-bit Address Detection - LBDL: u1, // bit offset: 5 desc: LIN break detection length - LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable + /// 7-bit Address Detection/4-bit Address Detection + ADDM7: u1 = 0, + /// LIN break detection length + LBDL: u1 = 0, + /// LIN break detection interrupt enable + LBDIE: u1 = 0, reserved5: u1 = 0, - LBCL: u1, // bit offset: 8 desc: Last bit clock pulse - CPHA: u1, // bit offset: 9 desc: Clock phase - CPOL: u1, // bit offset: 10 desc: Clock polarity - CLKEN: u1, // bit offset: 11 desc: Clock enable - STOP: u2, // bit offset: 12 desc: STOP bits - LINEN: u1, // bit offset: 14 desc: LIN mode enable - SWAP: u1, // bit offset: 15 desc: Swap TX/RX pins - RXINV: u1, // bit offset: 16 desc: RX pin active level inversion - TXINV: u1, // bit offset: 17 desc: TX pin active level inversion - DATAINV: u1, // bit offset: 18 desc: Binary data inversion - MSBFIRST: u1, // bit offset: 19 desc: Most significant bit first - ABREN: u1, // bit offset: 20 desc: Auto baud rate enable - ABRMOD: u2, // bit offset: 21 desc: Auto baud rate mode - RTOEN: u1, // bit offset: 23 desc: Receiver timeout enable - ADD0: u4, // bit offset: 24 desc: Address of the USART node - ADD4: u4, // bit offset: 28 desc: Address of the USART node - }); - // byte offset: 8 Control register 3 + /// Last bit clock pulse + LBCL: u1 = 0, + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Clock enable + CLKEN: u1 = 0, + /// STOP bits + STOP: u2 = 0, + /// LIN mode enable + LINEN: u1 = 0, + /// Swap TX/RX pins + SWAP: u1 = 0, + /// RX pin active level inversion + RXINV: u1 = 0, + /// TX pin active level inversion + TXINV: u1 = 0, + /// Binary data inversion + DATAINV: u1 = 0, + /// Most significant bit first + MSBFIRST: u1 = 0, + /// Auto baud rate enable + ABREN: u1 = 0, + /// Auto baud rate mode + ABRMOD: u2 = 0, + /// Receiver timeout enable + RTOEN: u1 = 0, + /// Address of the USART node + ADD0: u4 = 0, + /// Address of the USART node + ADD4: u4 = 0, + }); + + /// Control register 3 pub const CR3 = mmio(Address + 0x00000008, 32, packed struct { - EIE: u1, // bit offset: 0 desc: Error interrupt enable - IREN: u1, // bit offset: 1 desc: IrDA mode enable - IRLP: u1, // bit offset: 2 desc: IrDA low-power - HDSEL: u1, // bit offset: 3 desc: Half-duplex selection - NACK: u1, // bit offset: 4 desc: Smartcard NACK enable - SCEN: u1, // bit offset: 5 desc: Smartcard mode enable - DMAR: u1, // bit offset: 6 desc: DMA enable receiver - DMAT: u1, // bit offset: 7 desc: DMA enable transmitter - RTSE: u1, // bit offset: 8 desc: RTS enable - CTSE: u1, // bit offset: 9 desc: CTS enable - CTSIE: u1, // bit offset: 10 desc: CTS interrupt enable - ONEBIT: u1, // bit offset: 11 desc: One sample bit method enable - OVRDIS: u1, // bit offset: 12 desc: Overrun Disable - DDRE: u1, // bit offset: 13 desc: DMA Disable on Reception Error - DEM: u1, // bit offset: 14 desc: Driver enable mode - DEP: u1, // bit offset: 15 desc: Driver enable polarity selection - reserved1: u1 = 0, - SCARCNT: u3, // bit offset: 17 desc: Smartcard auto-retry count - WUS: u2, // bit offset: 20 desc: Wakeup from Stop mode interrupt flag selection - WUFIE: u1, // bit offset: 22 desc: Wakeup from Stop mode interrupt enable + /// Error interrupt enable + EIE: u1 = 0, + /// IrDA mode enable + IREN: u1 = 0, + /// IrDA low-power + IRLP: u1 = 0, + /// Half-duplex selection + HDSEL: u1 = 0, + /// Smartcard NACK enable + NACK: u1 = 0, + /// Smartcard mode enable + SCEN: u1 = 0, + /// DMA enable receiver + DMAR: u1 = 0, + /// DMA enable transmitter + DMAT: u1 = 0, + /// RTS enable + RTSE: u1 = 0, + /// CTS enable + CTSE: u1 = 0, + /// CTS interrupt enable + CTSIE: u1 = 0, + /// One sample bit method enable + ONEBIT: u1 = 0, + /// Overrun Disable + OVRDIS: u1 = 0, + /// DMA Disable on Reception Error + DDRE: u1 = 0, + /// Driver enable mode + DEM: u1 = 0, + /// Driver enable polarity selection + DEP: u1 = 0, + reserved1: u1 = 0, + /// Smartcard auto-retry count + SCARCNT: u3 = 0, + /// Wakeup from Stop mode interrupt flag selection + WUS: u2 = 0, + /// Wakeup from Stop mode interrupt enable + WUFIE: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -8139,10 +11521,13 @@ pub const UART4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Baud rate register + + /// Baud rate register pub const BRR = mmio(Address + 0x0000000c, 32, packed struct { - DIV_Fraction: u4, // bit offset: 0 desc: fraction of USARTDIV - DIV_Mantissa: u12, // bit offset: 4 desc: mantissa of USARTDIV + /// fraction of USARTDIV + DIV_Fraction: u4 = 0, + /// mantissa of USARTDIV + DIV_Mantissa: u12 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8160,10 +11545,13 @@ pub const UART4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Guard time and prescaler register + + /// Guard time and prescaler register pub const GTPR = mmio(Address + 0x00000010, 32, packed struct { - PSC: u8, // bit offset: 0 desc: Prescaler value - GT: u8, // bit offset: 8 desc: Guard time value + /// Prescaler value + PSC: u8 = 0, + /// Guard time value + GT: u8 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8181,18 +11569,27 @@ pub const UART4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Receiver timeout register + + /// Receiver timeout register pub const RTOR = mmio(Address + 0x00000014, 32, packed struct { - RTO: u24, // bit offset: 0 desc: Receiver timeout value - BLEN: u8, // bit offset: 24 desc: Block Length + /// Receiver timeout value + RTO: u24 = 0, + /// Block Length + BLEN: u8 = 0, }); - // byte offset: 24 Request register + + /// Request register pub const RQR = mmio(Address + 0x00000018, 32, packed struct { - ABRRQ: u1, // bit offset: 0 desc: Auto baud rate request - SBKRQ: u1, // bit offset: 1 desc: Send break request - MMRQ: u1, // bit offset: 2 desc: Mute mode request - RXFRQ: u1, // bit offset: 3 desc: Receive data flush request - TXFRQ: u1, // bit offset: 4 desc: Transmit data flush request + /// Auto baud rate request + ABRRQ: u1 = 0, + /// Send break request + SBKRQ: u1 = 0, + /// Mute mode request + MMRQ: u1 = 0, + /// Receive data flush request + RXFRQ: u1 = 0, + /// Transmit data flush request + TXFRQ: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -8221,31 +11618,54 @@ pub const UART4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 Interrupt & status register + + /// Interrupt & status register pub const ISR = mmio(Address + 0x0000001c, 32, packed struct { - PE: u1, // bit offset: 0 desc: Parity error - FE: u1, // bit offset: 1 desc: Framing error - NF: u1, // bit offset: 2 desc: Noise detected flag - ORE: u1, // bit offset: 3 desc: Overrun error - IDLE: u1, // bit offset: 4 desc: Idle line detected - RXNE: u1, // bit offset: 5 desc: Read data register not empty - TC: u1, // bit offset: 6 desc: Transmission complete - TXE: u1, // bit offset: 7 desc: Transmit data register empty - LBDF: u1, // bit offset: 8 desc: LIN break detection flag - CTSIF: u1, // bit offset: 9 desc: CTS interrupt flag - CTS: u1, // bit offset: 10 desc: CTS flag - RTOF: u1, // bit offset: 11 desc: Receiver timeout - EOBF: u1, // bit offset: 12 desc: End of block flag - reserved1: u1 = 0, - ABRE: u1, // bit offset: 14 desc: Auto baud rate error - ABRF: u1, // bit offset: 15 desc: Auto baud rate flag - BUSY: u1, // bit offset: 16 desc: Busy flag - CMF: u1, // bit offset: 17 desc: character match flag - SBKF: u1, // bit offset: 18 desc: Send break flag - RWU: u1, // bit offset: 19 desc: Receiver wakeup from Mute mode - WUF: u1, // bit offset: 20 desc: Wakeup from Stop mode flag - TEACK: u1, // bit offset: 21 desc: Transmit enable acknowledge flag - REACK: u1, // bit offset: 22 desc: Receive enable acknowledge flag + /// Parity error + PE: u1 = 0, + /// Framing error + FE: u1 = 0, + /// Noise detected flag + NF: u1 = 0, + /// Overrun error + ORE: u1 = 0, + /// Idle line detected + IDLE: u1 = 0, + /// Read data register not empty + RXNE: u1 = 0, + /// Transmission complete + TC: u1 = 0, + /// Transmit data register empty + TXE: u1 = 0, + /// LIN break detection flag + LBDF: u1 = 0, + /// CTS interrupt flag + CTSIF: u1 = 0, + /// CTS flag + CTS: u1 = 0, + /// Receiver timeout + RTOF: u1 = 0, + /// End of block flag + EOBF: u1 = 0, + reserved1: u1 = 0, + /// Auto baud rate error + ABRE: u1 = 0, + /// Auto baud rate flag + ABRF: u1 = 0, + /// Busy flag + BUSY: u1 = 0, + /// character match flag + CMF: u1 = 0, + /// Send break flag + SBKF: u1 = 0, + /// Receiver wakeup from Mute mode + RWU: u1 = 0, + /// Wakeup from Stop mode flag + WUF: u1 = 0, + /// Transmit enable acknowledge flag + TEACK: u1 = 0, + /// Receive enable acknowledge flag + REACK: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -8256,29 +11676,42 @@ pub const UART4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 Interrupt flag clear register + + /// Interrupt flag clear register pub const ICR = mmio(Address + 0x00000020, 32, packed struct { - PECF: u1, // bit offset: 0 desc: Parity error clear flag - FECF: u1, // bit offset: 1 desc: Framing error clear flag - NCF: u1, // bit offset: 2 desc: Noise detected clear flag - ORECF: u1, // bit offset: 3 desc: Overrun error clear flag - IDLECF: u1, // bit offset: 4 desc: Idle line detected clear flag - reserved1: u1 = 0, - TCCF: u1, // bit offset: 6 desc: Transmission complete clear flag - reserved2: u1 = 0, - LBDCF: u1, // bit offset: 8 desc: LIN break detection clear flag - CTSCF: u1, // bit offset: 9 desc: CTS clear flag + /// Parity error clear flag + PECF: u1 = 0, + /// Framing error clear flag + FECF: u1 = 0, + /// Noise detected clear flag + NCF: u1 = 0, + /// Overrun error clear flag + ORECF: u1 = 0, + /// Idle line detected clear flag + IDLECF: u1 = 0, + reserved1: u1 = 0, + /// Transmission complete clear flag + TCCF: u1 = 0, + reserved2: u1 = 0, + /// LIN break detection clear flag + LBDCF: u1 = 0, + /// CTS clear flag + CTSCF: u1 = 0, reserved3: u1 = 0, - RTOCF: u1, // bit offset: 11 desc: Receiver timeout clear flag - EOBCF: u1, // bit offset: 12 desc: End of timeout clear flag + /// Receiver timeout clear flag + RTOCF: u1 = 0, + /// End of timeout clear flag + EOBCF: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - CMCF: u1, // bit offset: 17 desc: Character match clear flag + /// Character match clear flag + CMCF: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, - WUCF: u1, // bit offset: 20 desc: Wakeup from Stop mode clear flag + /// Wakeup from Stop mode clear flag + WUCF: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, @@ -8291,9 +11724,11 @@ pub const UART4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 Receive data register + + /// Receive data register pub const RDR = mmio(Address + 0x00000024, 32, packed struct { - RDR: u9, // bit offset: 0 desc: Receive data value + /// Receive data value + RDR: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -8318,9 +11753,11 @@ pub const UART4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 Transmit data register + + /// Transmit data register pub const TDR = mmio(Address + 0x00000028, 32, packed struct { - TDR: u9, // bit offset: 0 desc: Transmit data value + /// Transmit data value + TDR: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -8346,84 +11783,147 @@ pub const UART4 = extern struct { padding1: u1 = 0, }); }; + +/// Universal synchronous asynchronous receiver transmitter pub const UART5 = extern struct { pub const Address: u32 = 0x40005000; - // byte offset: 0 Control register 1 + + /// Control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - UE: u1, // bit offset: 0 desc: USART enable - UESM: u1, // bit offset: 1 desc: USART enable in Stop mode - RE: u1, // bit offset: 2 desc: Receiver enable - TE: u1, // bit offset: 3 desc: Transmitter enable - IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable - RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable - TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable - TXEIE: u1, // bit offset: 7 desc: interrupt enable - PEIE: u1, // bit offset: 8 desc: PE interrupt enable - PS: u1, // bit offset: 9 desc: Parity selection - PCE: u1, // bit offset: 10 desc: Parity control enable - WAKE: u1, // bit offset: 11 desc: Receiver wakeup method - M: u1, // bit offset: 12 desc: Word length - MME: u1, // bit offset: 13 desc: Mute mode enable - CMIE: u1, // bit offset: 14 desc: Character match interrupt enable - OVER8: u1, // bit offset: 15 desc: Oversampling mode - DEDT: u5, // bit offset: 16 desc: Driver Enable deassertion time - DEAT: u5, // bit offset: 21 desc: Driver Enable assertion time - RTOIE: u1, // bit offset: 26 desc: Receiver timeout interrupt enable - EOBIE: u1, // bit offset: 27 desc: End of Block interrupt enable - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Control register 2 + /// USART enable + UE: u1 = 0, + /// USART enable in Stop mode + UESM: u1 = 0, + /// Receiver enable + RE: u1 = 0, + /// Transmitter enable + TE: u1 = 0, + /// IDLE interrupt enable + IDLEIE: u1 = 0, + /// RXNE interrupt enable + RXNEIE: u1 = 0, + /// Transmission complete interrupt enable + TCIE: u1 = 0, + /// interrupt enable + TXEIE: u1 = 0, + /// PE interrupt enable + PEIE: u1 = 0, + /// Parity selection + PS: u1 = 0, + /// Parity control enable + PCE: u1 = 0, + /// Receiver wakeup method + WAKE: u1 = 0, + /// Word length + M: u1 = 0, + /// Mute mode enable + MME: u1 = 0, + /// Character match interrupt enable + CMIE: u1 = 0, + /// Oversampling mode + OVER8: u1 = 0, + /// Driver Enable deassertion time + DEDT: u5 = 0, + /// Driver Enable assertion time + DEAT: u5 = 0, + /// Receiver timeout interrupt enable + RTOIE: u1 = 0, + /// End of Block interrupt enable + EOBIE: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADDM7: u1, // bit offset: 4 desc: 7-bit Address Detection/4-bit Address Detection - LBDL: u1, // bit offset: 5 desc: LIN break detection length - LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable + /// 7-bit Address Detection/4-bit Address Detection + ADDM7: u1 = 0, + /// LIN break detection length + LBDL: u1 = 0, + /// LIN break detection interrupt enable + LBDIE: u1 = 0, reserved5: u1 = 0, - LBCL: u1, // bit offset: 8 desc: Last bit clock pulse - CPHA: u1, // bit offset: 9 desc: Clock phase - CPOL: u1, // bit offset: 10 desc: Clock polarity - CLKEN: u1, // bit offset: 11 desc: Clock enable - STOP: u2, // bit offset: 12 desc: STOP bits - LINEN: u1, // bit offset: 14 desc: LIN mode enable - SWAP: u1, // bit offset: 15 desc: Swap TX/RX pins - RXINV: u1, // bit offset: 16 desc: RX pin active level inversion - TXINV: u1, // bit offset: 17 desc: TX pin active level inversion - DATAINV: u1, // bit offset: 18 desc: Binary data inversion - MSBFIRST: u1, // bit offset: 19 desc: Most significant bit first - ABREN: u1, // bit offset: 20 desc: Auto baud rate enable - ABRMOD: u2, // bit offset: 21 desc: Auto baud rate mode - RTOEN: u1, // bit offset: 23 desc: Receiver timeout enable - ADD0: u4, // bit offset: 24 desc: Address of the USART node - ADD4: u4, // bit offset: 28 desc: Address of the USART node - }); - // byte offset: 8 Control register 3 + /// Last bit clock pulse + LBCL: u1 = 0, + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Clock enable + CLKEN: u1 = 0, + /// STOP bits + STOP: u2 = 0, + /// LIN mode enable + LINEN: u1 = 0, + /// Swap TX/RX pins + SWAP: u1 = 0, + /// RX pin active level inversion + RXINV: u1 = 0, + /// TX pin active level inversion + TXINV: u1 = 0, + /// Binary data inversion + DATAINV: u1 = 0, + /// Most significant bit first + MSBFIRST: u1 = 0, + /// Auto baud rate enable + ABREN: u1 = 0, + /// Auto baud rate mode + ABRMOD: u2 = 0, + /// Receiver timeout enable + RTOEN: u1 = 0, + /// Address of the USART node + ADD0: u4 = 0, + /// Address of the USART node + ADD4: u4 = 0, + }); + + /// Control register 3 pub const CR3 = mmio(Address + 0x00000008, 32, packed struct { - EIE: u1, // bit offset: 0 desc: Error interrupt enable - IREN: u1, // bit offset: 1 desc: IrDA mode enable - IRLP: u1, // bit offset: 2 desc: IrDA low-power - HDSEL: u1, // bit offset: 3 desc: Half-duplex selection - NACK: u1, // bit offset: 4 desc: Smartcard NACK enable - SCEN: u1, // bit offset: 5 desc: Smartcard mode enable - DMAR: u1, // bit offset: 6 desc: DMA enable receiver - DMAT: u1, // bit offset: 7 desc: DMA enable transmitter - RTSE: u1, // bit offset: 8 desc: RTS enable - CTSE: u1, // bit offset: 9 desc: CTS enable - CTSIE: u1, // bit offset: 10 desc: CTS interrupt enable - ONEBIT: u1, // bit offset: 11 desc: One sample bit method enable - OVRDIS: u1, // bit offset: 12 desc: Overrun Disable - DDRE: u1, // bit offset: 13 desc: DMA Disable on Reception Error - DEM: u1, // bit offset: 14 desc: Driver enable mode - DEP: u1, // bit offset: 15 desc: Driver enable polarity selection - reserved1: u1 = 0, - SCARCNT: u3, // bit offset: 17 desc: Smartcard auto-retry count - WUS: u2, // bit offset: 20 desc: Wakeup from Stop mode interrupt flag selection - WUFIE: u1, // bit offset: 22 desc: Wakeup from Stop mode interrupt enable + /// Error interrupt enable + EIE: u1 = 0, + /// IrDA mode enable + IREN: u1 = 0, + /// IrDA low-power + IRLP: u1 = 0, + /// Half-duplex selection + HDSEL: u1 = 0, + /// Smartcard NACK enable + NACK: u1 = 0, + /// Smartcard mode enable + SCEN: u1 = 0, + /// DMA enable receiver + DMAR: u1 = 0, + /// DMA enable transmitter + DMAT: u1 = 0, + /// RTS enable + RTSE: u1 = 0, + /// CTS enable + CTSE: u1 = 0, + /// CTS interrupt enable + CTSIE: u1 = 0, + /// One sample bit method enable + ONEBIT: u1 = 0, + /// Overrun Disable + OVRDIS: u1 = 0, + /// DMA Disable on Reception Error + DDRE: u1 = 0, + /// Driver enable mode + DEM: u1 = 0, + /// Driver enable polarity selection + DEP: u1 = 0, + reserved1: u1 = 0, + /// Smartcard auto-retry count + SCARCNT: u3 = 0, + /// Wakeup from Stop mode interrupt flag selection + WUS: u2 = 0, + /// Wakeup from Stop mode interrupt enable + WUFIE: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -8434,10 +11934,13 @@ pub const UART5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Baud rate register + + /// Baud rate register pub const BRR = mmio(Address + 0x0000000c, 32, packed struct { - DIV_Fraction: u4, // bit offset: 0 desc: fraction of USARTDIV - DIV_Mantissa: u12, // bit offset: 4 desc: mantissa of USARTDIV + /// fraction of USARTDIV + DIV_Fraction: u4 = 0, + /// mantissa of USARTDIV + DIV_Mantissa: u12 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8455,10 +11958,13 @@ pub const UART5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Guard time and prescaler register + + /// Guard time and prescaler register pub const GTPR = mmio(Address + 0x00000010, 32, packed struct { - PSC: u8, // bit offset: 0 desc: Prescaler value - GT: u8, // bit offset: 8 desc: Guard time value + /// Prescaler value + PSC: u8 = 0, + /// Guard time value + GT: u8 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8476,18 +11982,27 @@ pub const UART5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Receiver timeout register + + /// Receiver timeout register pub const RTOR = mmio(Address + 0x00000014, 32, packed struct { - RTO: u24, // bit offset: 0 desc: Receiver timeout value - BLEN: u8, // bit offset: 24 desc: Block Length + /// Receiver timeout value + RTO: u24 = 0, + /// Block Length + BLEN: u8 = 0, }); - // byte offset: 24 Request register + + /// Request register pub const RQR = mmio(Address + 0x00000018, 32, packed struct { - ABRRQ: u1, // bit offset: 0 desc: Auto baud rate request - SBKRQ: u1, // bit offset: 1 desc: Send break request - MMRQ: u1, // bit offset: 2 desc: Mute mode request - RXFRQ: u1, // bit offset: 3 desc: Receive data flush request - TXFRQ: u1, // bit offset: 4 desc: Transmit data flush request + /// Auto baud rate request + ABRRQ: u1 = 0, + /// Send break request + SBKRQ: u1 = 0, + /// Mute mode request + MMRQ: u1 = 0, + /// Receive data flush request + RXFRQ: u1 = 0, + /// Transmit data flush request + TXFRQ: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -8516,31 +12031,54 @@ pub const UART5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 Interrupt & status register + + /// Interrupt & status register pub const ISR = mmio(Address + 0x0000001c, 32, packed struct { - PE: u1, // bit offset: 0 desc: Parity error - FE: u1, // bit offset: 1 desc: Framing error - NF: u1, // bit offset: 2 desc: Noise detected flag - ORE: u1, // bit offset: 3 desc: Overrun error - IDLE: u1, // bit offset: 4 desc: Idle line detected - RXNE: u1, // bit offset: 5 desc: Read data register not empty - TC: u1, // bit offset: 6 desc: Transmission complete - TXE: u1, // bit offset: 7 desc: Transmit data register empty - LBDF: u1, // bit offset: 8 desc: LIN break detection flag - CTSIF: u1, // bit offset: 9 desc: CTS interrupt flag - CTS: u1, // bit offset: 10 desc: CTS flag - RTOF: u1, // bit offset: 11 desc: Receiver timeout - EOBF: u1, // bit offset: 12 desc: End of block flag - reserved1: u1 = 0, - ABRE: u1, // bit offset: 14 desc: Auto baud rate error - ABRF: u1, // bit offset: 15 desc: Auto baud rate flag - BUSY: u1, // bit offset: 16 desc: Busy flag - CMF: u1, // bit offset: 17 desc: character match flag - SBKF: u1, // bit offset: 18 desc: Send break flag - RWU: u1, // bit offset: 19 desc: Receiver wakeup from Mute mode - WUF: u1, // bit offset: 20 desc: Wakeup from Stop mode flag - TEACK: u1, // bit offset: 21 desc: Transmit enable acknowledge flag - REACK: u1, // bit offset: 22 desc: Receive enable acknowledge flag + /// Parity error + PE: u1 = 0, + /// Framing error + FE: u1 = 0, + /// Noise detected flag + NF: u1 = 0, + /// Overrun error + ORE: u1 = 0, + /// Idle line detected + IDLE: u1 = 0, + /// Read data register not empty + RXNE: u1 = 0, + /// Transmission complete + TC: u1 = 0, + /// Transmit data register empty + TXE: u1 = 0, + /// LIN break detection flag + LBDF: u1 = 0, + /// CTS interrupt flag + CTSIF: u1 = 0, + /// CTS flag + CTS: u1 = 0, + /// Receiver timeout + RTOF: u1 = 0, + /// End of block flag + EOBF: u1 = 0, + reserved1: u1 = 0, + /// Auto baud rate error + ABRE: u1 = 0, + /// Auto baud rate flag + ABRF: u1 = 0, + /// Busy flag + BUSY: u1 = 0, + /// character match flag + CMF: u1 = 0, + /// Send break flag + SBKF: u1 = 0, + /// Receiver wakeup from Mute mode + RWU: u1 = 0, + /// Wakeup from Stop mode flag + WUF: u1 = 0, + /// Transmit enable acknowledge flag + TEACK: u1 = 0, + /// Receive enable acknowledge flag + REACK: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -8551,29 +12089,42 @@ pub const UART5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 Interrupt flag clear register + + /// Interrupt flag clear register pub const ICR = mmio(Address + 0x00000020, 32, packed struct { - PECF: u1, // bit offset: 0 desc: Parity error clear flag - FECF: u1, // bit offset: 1 desc: Framing error clear flag - NCF: u1, // bit offset: 2 desc: Noise detected clear flag - ORECF: u1, // bit offset: 3 desc: Overrun error clear flag - IDLECF: u1, // bit offset: 4 desc: Idle line detected clear flag - reserved1: u1 = 0, - TCCF: u1, // bit offset: 6 desc: Transmission complete clear flag - reserved2: u1 = 0, - LBDCF: u1, // bit offset: 8 desc: LIN break detection clear flag - CTSCF: u1, // bit offset: 9 desc: CTS clear flag + /// Parity error clear flag + PECF: u1 = 0, + /// Framing error clear flag + FECF: u1 = 0, + /// Noise detected clear flag + NCF: u1 = 0, + /// Overrun error clear flag + ORECF: u1 = 0, + /// Idle line detected clear flag + IDLECF: u1 = 0, + reserved1: u1 = 0, + /// Transmission complete clear flag + TCCF: u1 = 0, + reserved2: u1 = 0, + /// LIN break detection clear flag + LBDCF: u1 = 0, + /// CTS clear flag + CTSCF: u1 = 0, reserved3: u1 = 0, - RTOCF: u1, // bit offset: 11 desc: Receiver timeout clear flag - EOBCF: u1, // bit offset: 12 desc: End of timeout clear flag + /// Receiver timeout clear flag + RTOCF: u1 = 0, + /// End of timeout clear flag + EOBCF: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - CMCF: u1, // bit offset: 17 desc: Character match clear flag + /// Character match clear flag + CMCF: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, - WUCF: u1, // bit offset: 20 desc: Wakeup from Stop mode clear flag + /// Wakeup from Stop mode clear flag + WUCF: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, @@ -8586,9 +12137,11 @@ pub const UART5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 Receive data register + + /// Receive data register pub const RDR = mmio(Address + 0x00000024, 32, packed struct { - RDR: u9, // bit offset: 0 desc: Receive data value + /// Receive data value + RDR: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -8613,9 +12166,11 @@ pub const UART5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 Transmit data register + + /// Transmit data register pub const TDR = mmio(Address + 0x00000028, 32, packed struct { - TDR: u9, // bit offset: 0 desc: Transmit data value + /// Transmit data value + TDR: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -8641,24 +12196,41 @@ pub const UART5 = extern struct { padding1: u1 = 0, }); }; + +/// Serial peripheral interface/Inter-IC sound pub const SPI1 = extern struct { pub const Address: u32 = 0x40013000; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CPHA: u1, // bit offset: 0 desc: Clock phase - CPOL: u1, // bit offset: 1 desc: Clock polarity - MSTR: u1, // bit offset: 2 desc: Master selection - BR: u3, // bit offset: 3 desc: Baud rate control - SPE: u1, // bit offset: 6 desc: SPI enable - LSBFIRST: u1, // bit offset: 7 desc: Frame format - SSI: u1, // bit offset: 8 desc: Internal slave select - SSM: u1, // bit offset: 9 desc: Software slave management - RXONLY: u1, // bit offset: 10 desc: Receive only - CRCL: u1, // bit offset: 11 desc: CRC length - CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next - CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable - BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode - BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Master selection + MSTR: u1 = 0, + /// Baud rate control + BR: u3 = 0, + /// SPI enable + SPE: u1 = 0, + /// Frame format + LSBFIRST: u1 = 0, + /// Internal slave select + SSI: u1 = 0, + /// Software slave management + SSM: u1 = 0, + /// Receive only + RXONLY: u1 = 0, + /// CRC length + CRCL: u1 = 0, + /// CRC transfer next + CRCNEXT: u1 = 0, + /// Hardware CRC calculation enable + CRCEN: u1 = 0, + /// Output enable in bidirectional mode + BIDIOE: u1 = 0, + /// Bidirectional data mode enable + BIDIMODE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8676,20 +12248,33 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable - TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable - SSOE: u1, // bit offset: 2 desc: SS output enable - NSSP: u1, // bit offset: 3 desc: NSS pulse management - FRF: u1, // bit offset: 4 desc: Frame format - ERRIE: u1, // bit offset: 5 desc: Error interrupt enable - RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable - TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable - DS: u4, // bit offset: 8 desc: Data size - FRXTH: u1, // bit offset: 12 desc: FIFO reception threshold - LDMA_RX: u1, // bit offset: 13 desc: Last DMA transfer for reception - LDMA_TX: u1, // bit offset: 14 desc: Last DMA transfer for transmission + /// Rx buffer DMA enable + RXDMAEN: u1 = 0, + /// Tx buffer DMA enable + TXDMAEN: u1 = 0, + /// SS output enable + SSOE: u1 = 0, + /// NSS pulse management + NSSP: u1 = 0, + /// Frame format + FRF: u1 = 0, + /// Error interrupt enable + ERRIE: u1 = 0, + /// RX buffer not empty interrupt enable + RXNEIE: u1 = 0, + /// Tx buffer empty interrupt enable + TXEIE: u1 = 0, + /// Data size + DS: u4 = 0, + /// FIFO reception threshold + FRXTH: u1 = 0, + /// Last DMA transfer for reception + LDMA_RX: u1 = 0, + /// Last DMA transfer for transmission + LDMA_TX: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -8708,19 +12293,31 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 status register + + /// status register pub const SR = mmio(Address + 0x00000008, 32, packed struct { - RXNE: u1, // bit offset: 0 desc: Receive buffer not empty - TXE: u1, // bit offset: 1 desc: Transmit buffer empty - CHSIDE: u1, // bit offset: 2 desc: Channel side - UDR: u1, // bit offset: 3 desc: Underrun flag - CRCERR: u1, // bit offset: 4 desc: CRC error flag - MODF: u1, // bit offset: 5 desc: Mode fault - OVR: u1, // bit offset: 6 desc: Overrun flag - BSY: u1, // bit offset: 7 desc: Busy flag - TIFRFE: u1, // bit offset: 8 desc: TI frame format error - FRLVL: u2, // bit offset: 9 desc: FIFO reception level - FTLVL: u2, // bit offset: 11 desc: FIFO transmission level + /// Receive buffer not empty + RXNE: u1 = 0, + /// Transmit buffer empty + TXE: u1 = 0, + /// Channel side + CHSIDE: u1 = 0, + /// Underrun flag + UDR: u1 = 0, + /// CRC error flag + CRCERR: u1 = 0, + /// Mode fault + MODF: u1 = 0, + /// Overrun flag + OVR: u1 = 0, + /// Busy flag + BSY: u1 = 0, + /// TI frame format error + TIFRFE: u1 = 0, + /// FIFO reception level + FRLVL: u2 = 0, + /// FIFO transmission level + FTLVL: u2 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -8741,9 +12338,11 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 data register + + /// data register pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - DR: u16, // bit offset: 0 desc: Data register + /// Data register + DR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8761,9 +12360,11 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 CRC polynomial register + + /// CRC polynomial register pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + /// CRC polynomial register + CRCPOLY: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8781,9 +12382,11 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 RX CRC register + + /// RX CRC register pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - RxCRC: u16, // bit offset: 0 desc: Rx CRC register + /// Rx CRC register + RxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8801,9 +12404,11 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 TX CRC register + + /// TX CRC register pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - TxCRC: u16, // bit offset: 0 desc: Tx CRC register + /// Tx CRC register + TxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8821,17 +12426,26 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 I2S configuration register + + /// I2S configuration register pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) - DATLEN: u2, // bit offset: 1 desc: Data length to be transferred - CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity - I2SSTD: u2, // bit offset: 4 desc: I2S standard selection - reserved1: u1 = 0, - PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization - I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode - I2SE: u1, // bit offset: 10 desc: I2S Enable - I2SMOD: u1, // bit offset: 11 desc: I2S mode selection + /// Channel length (number of bits per audio channel) + CHLEN: u1 = 0, + /// Data length to be transferred + DATLEN: u2 = 0, + /// Steady state clock polarity + CKPOL: u1 = 0, + /// I2S standard selection + I2SSTD: u2 = 0, + reserved1: u1 = 0, + /// PCM frame synchronization + PCMSYNC: u1 = 0, + /// I2S configuration mode + I2SCFG: u2 = 0, + /// I2S Enable + I2SE: u1 = 0, + /// I2S mode selection + I2SMOD: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -8853,11 +12467,15 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 I2S prescaler register + + /// I2S prescaler register pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler - ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler - MCKOE: u1, // bit offset: 9 desc: Master clock output enable + /// I2S Linear prescaler + I2SDIV: u8 = 0, + /// Odd factor for the prescaler + ODD: u1 = 0, + /// Master clock output enable + MCKOE: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -8882,24 +12500,41 @@ pub const SPI1 = extern struct { padding1: u1 = 0, }); }; + +/// Serial peripheral interface/Inter-IC sound pub const SPI2 = extern struct { pub const Address: u32 = 0x40003800; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CPHA: u1, // bit offset: 0 desc: Clock phase - CPOL: u1, // bit offset: 1 desc: Clock polarity - MSTR: u1, // bit offset: 2 desc: Master selection - BR: u3, // bit offset: 3 desc: Baud rate control - SPE: u1, // bit offset: 6 desc: SPI enable - LSBFIRST: u1, // bit offset: 7 desc: Frame format - SSI: u1, // bit offset: 8 desc: Internal slave select - SSM: u1, // bit offset: 9 desc: Software slave management - RXONLY: u1, // bit offset: 10 desc: Receive only - CRCL: u1, // bit offset: 11 desc: CRC length - CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next - CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable - BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode - BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Master selection + MSTR: u1 = 0, + /// Baud rate control + BR: u3 = 0, + /// SPI enable + SPE: u1 = 0, + /// Frame format + LSBFIRST: u1 = 0, + /// Internal slave select + SSI: u1 = 0, + /// Software slave management + SSM: u1 = 0, + /// Receive only + RXONLY: u1 = 0, + /// CRC length + CRCL: u1 = 0, + /// CRC transfer next + CRCNEXT: u1 = 0, + /// Hardware CRC calculation enable + CRCEN: u1 = 0, + /// Output enable in bidirectional mode + BIDIOE: u1 = 0, + /// Bidirectional data mode enable + BIDIMODE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8917,20 +12552,33 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable - TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable - SSOE: u1, // bit offset: 2 desc: SS output enable - NSSP: u1, // bit offset: 3 desc: NSS pulse management - FRF: u1, // bit offset: 4 desc: Frame format - ERRIE: u1, // bit offset: 5 desc: Error interrupt enable - RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable - TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable - DS: u4, // bit offset: 8 desc: Data size - FRXTH: u1, // bit offset: 12 desc: FIFO reception threshold - LDMA_RX: u1, // bit offset: 13 desc: Last DMA transfer for reception - LDMA_TX: u1, // bit offset: 14 desc: Last DMA transfer for transmission + /// Rx buffer DMA enable + RXDMAEN: u1 = 0, + /// Tx buffer DMA enable + TXDMAEN: u1 = 0, + /// SS output enable + SSOE: u1 = 0, + /// NSS pulse management + NSSP: u1 = 0, + /// Frame format + FRF: u1 = 0, + /// Error interrupt enable + ERRIE: u1 = 0, + /// RX buffer not empty interrupt enable + RXNEIE: u1 = 0, + /// Tx buffer empty interrupt enable + TXEIE: u1 = 0, + /// Data size + DS: u4 = 0, + /// FIFO reception threshold + FRXTH: u1 = 0, + /// Last DMA transfer for reception + LDMA_RX: u1 = 0, + /// Last DMA transfer for transmission + LDMA_TX: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -8949,19 +12597,31 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 status register + + /// status register pub const SR = mmio(Address + 0x00000008, 32, packed struct { - RXNE: u1, // bit offset: 0 desc: Receive buffer not empty - TXE: u1, // bit offset: 1 desc: Transmit buffer empty - CHSIDE: u1, // bit offset: 2 desc: Channel side - UDR: u1, // bit offset: 3 desc: Underrun flag - CRCERR: u1, // bit offset: 4 desc: CRC error flag - MODF: u1, // bit offset: 5 desc: Mode fault - OVR: u1, // bit offset: 6 desc: Overrun flag - BSY: u1, // bit offset: 7 desc: Busy flag - TIFRFE: u1, // bit offset: 8 desc: TI frame format error - FRLVL: u2, // bit offset: 9 desc: FIFO reception level - FTLVL: u2, // bit offset: 11 desc: FIFO transmission level + /// Receive buffer not empty + RXNE: u1 = 0, + /// Transmit buffer empty + TXE: u1 = 0, + /// Channel side + CHSIDE: u1 = 0, + /// Underrun flag + UDR: u1 = 0, + /// CRC error flag + CRCERR: u1 = 0, + /// Mode fault + MODF: u1 = 0, + /// Overrun flag + OVR: u1 = 0, + /// Busy flag + BSY: u1 = 0, + /// TI frame format error + TIFRFE: u1 = 0, + /// FIFO reception level + FRLVL: u2 = 0, + /// FIFO transmission level + FTLVL: u2 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -8982,9 +12642,11 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 data register + + /// data register pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - DR: u16, // bit offset: 0 desc: Data register + /// Data register + DR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9002,9 +12664,11 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 CRC polynomial register + + /// CRC polynomial register pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + /// CRC polynomial register + CRCPOLY: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9022,9 +12686,11 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 RX CRC register + + /// RX CRC register pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - RxCRC: u16, // bit offset: 0 desc: Rx CRC register + /// Rx CRC register + RxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9042,9 +12708,11 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 TX CRC register + + /// TX CRC register pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - TxCRC: u16, // bit offset: 0 desc: Tx CRC register + /// Tx CRC register + TxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9062,17 +12730,26 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 I2S configuration register + + /// I2S configuration register pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) - DATLEN: u2, // bit offset: 1 desc: Data length to be transferred - CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity - I2SSTD: u2, // bit offset: 4 desc: I2S standard selection - reserved1: u1 = 0, - PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization - I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode - I2SE: u1, // bit offset: 10 desc: I2S Enable - I2SMOD: u1, // bit offset: 11 desc: I2S mode selection + /// Channel length (number of bits per audio channel) + CHLEN: u1 = 0, + /// Data length to be transferred + DATLEN: u2 = 0, + /// Steady state clock polarity + CKPOL: u1 = 0, + /// I2S standard selection + I2SSTD: u2 = 0, + reserved1: u1 = 0, + /// PCM frame synchronization + PCMSYNC: u1 = 0, + /// I2S configuration mode + I2SCFG: u2 = 0, + /// I2S Enable + I2SE: u1 = 0, + /// I2S mode selection + I2SMOD: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -9094,11 +12771,15 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 I2S prescaler register + + /// I2S prescaler register pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler - ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler - MCKOE: u1, // bit offset: 9 desc: Master clock output enable + /// I2S Linear prescaler + I2SDIV: u8 = 0, + /// Odd factor for the prescaler + ODD: u1 = 0, + /// Master clock output enable + MCKOE: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -9123,24 +12804,41 @@ pub const SPI2 = extern struct { padding1: u1 = 0, }); }; + +/// Serial peripheral interface/Inter-IC sound pub const SPI3 = extern struct { pub const Address: u32 = 0x40003c00; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CPHA: u1, // bit offset: 0 desc: Clock phase - CPOL: u1, // bit offset: 1 desc: Clock polarity - MSTR: u1, // bit offset: 2 desc: Master selection - BR: u3, // bit offset: 3 desc: Baud rate control - SPE: u1, // bit offset: 6 desc: SPI enable - LSBFIRST: u1, // bit offset: 7 desc: Frame format - SSI: u1, // bit offset: 8 desc: Internal slave select - SSM: u1, // bit offset: 9 desc: Software slave management - RXONLY: u1, // bit offset: 10 desc: Receive only - CRCL: u1, // bit offset: 11 desc: CRC length - CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next - CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable - BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode - BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Master selection + MSTR: u1 = 0, + /// Baud rate control + BR: u3 = 0, + /// SPI enable + SPE: u1 = 0, + /// Frame format + LSBFIRST: u1 = 0, + /// Internal slave select + SSI: u1 = 0, + /// Software slave management + SSM: u1 = 0, + /// Receive only + RXONLY: u1 = 0, + /// CRC length + CRCL: u1 = 0, + /// CRC transfer next + CRCNEXT: u1 = 0, + /// Hardware CRC calculation enable + CRCEN: u1 = 0, + /// Output enable in bidirectional mode + BIDIOE: u1 = 0, + /// Bidirectional data mode enable + BIDIMODE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9158,20 +12856,33 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable - TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable - SSOE: u1, // bit offset: 2 desc: SS output enable - NSSP: u1, // bit offset: 3 desc: NSS pulse management - FRF: u1, // bit offset: 4 desc: Frame format - ERRIE: u1, // bit offset: 5 desc: Error interrupt enable - RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable - TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable - DS: u4, // bit offset: 8 desc: Data size - FRXTH: u1, // bit offset: 12 desc: FIFO reception threshold - LDMA_RX: u1, // bit offset: 13 desc: Last DMA transfer for reception - LDMA_TX: u1, // bit offset: 14 desc: Last DMA transfer for transmission + /// Rx buffer DMA enable + RXDMAEN: u1 = 0, + /// Tx buffer DMA enable + TXDMAEN: u1 = 0, + /// SS output enable + SSOE: u1 = 0, + /// NSS pulse management + NSSP: u1 = 0, + /// Frame format + FRF: u1 = 0, + /// Error interrupt enable + ERRIE: u1 = 0, + /// RX buffer not empty interrupt enable + RXNEIE: u1 = 0, + /// Tx buffer empty interrupt enable + TXEIE: u1 = 0, + /// Data size + DS: u4 = 0, + /// FIFO reception threshold + FRXTH: u1 = 0, + /// Last DMA transfer for reception + LDMA_RX: u1 = 0, + /// Last DMA transfer for transmission + LDMA_TX: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -9190,19 +12901,31 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 status register + + /// status register pub const SR = mmio(Address + 0x00000008, 32, packed struct { - RXNE: u1, // bit offset: 0 desc: Receive buffer not empty - TXE: u1, // bit offset: 1 desc: Transmit buffer empty - CHSIDE: u1, // bit offset: 2 desc: Channel side - UDR: u1, // bit offset: 3 desc: Underrun flag - CRCERR: u1, // bit offset: 4 desc: CRC error flag - MODF: u1, // bit offset: 5 desc: Mode fault - OVR: u1, // bit offset: 6 desc: Overrun flag - BSY: u1, // bit offset: 7 desc: Busy flag - TIFRFE: u1, // bit offset: 8 desc: TI frame format error - FRLVL: u2, // bit offset: 9 desc: FIFO reception level - FTLVL: u2, // bit offset: 11 desc: FIFO transmission level + /// Receive buffer not empty + RXNE: u1 = 0, + /// Transmit buffer empty + TXE: u1 = 0, + /// Channel side + CHSIDE: u1 = 0, + /// Underrun flag + UDR: u1 = 0, + /// CRC error flag + CRCERR: u1 = 0, + /// Mode fault + MODF: u1 = 0, + /// Overrun flag + OVR: u1 = 0, + /// Busy flag + BSY: u1 = 0, + /// TI frame format error + TIFRFE: u1 = 0, + /// FIFO reception level + FRLVL: u2 = 0, + /// FIFO transmission level + FTLVL: u2 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -9223,9 +12946,11 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 data register + + /// data register pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - DR: u16, // bit offset: 0 desc: Data register + /// Data register + DR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9243,9 +12968,11 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 CRC polynomial register + + /// CRC polynomial register pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + /// CRC polynomial register + CRCPOLY: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9263,9 +12990,11 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 RX CRC register + + /// RX CRC register pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - RxCRC: u16, // bit offset: 0 desc: Rx CRC register + /// Rx CRC register + RxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9283,9 +13012,11 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 TX CRC register + + /// TX CRC register pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - TxCRC: u16, // bit offset: 0 desc: Tx CRC register + /// Tx CRC register + TxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9303,17 +13034,26 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 I2S configuration register + + /// I2S configuration register pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) - DATLEN: u2, // bit offset: 1 desc: Data length to be transferred - CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity - I2SSTD: u2, // bit offset: 4 desc: I2S standard selection - reserved1: u1 = 0, - PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization - I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode - I2SE: u1, // bit offset: 10 desc: I2S Enable - I2SMOD: u1, // bit offset: 11 desc: I2S mode selection + /// Channel length (number of bits per audio channel) + CHLEN: u1 = 0, + /// Data length to be transferred + DATLEN: u2 = 0, + /// Steady state clock polarity + CKPOL: u1 = 0, + /// I2S standard selection + I2SSTD: u2 = 0, + reserved1: u1 = 0, + /// PCM frame synchronization + PCMSYNC: u1 = 0, + /// I2S configuration mode + I2SCFG: u2 = 0, + /// I2S Enable + I2SE: u1 = 0, + /// I2S mode selection + I2SMOD: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -9335,11 +13075,15 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 I2S prescaler register + + /// I2S prescaler register pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler - ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler - MCKOE: u1, // bit offset: 9 desc: Master clock output enable + /// I2S Linear prescaler + I2SDIV: u8 = 0, + /// Odd factor for the prescaler + ODD: u1 = 0, + /// Master clock output enable + MCKOE: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -9364,24 +13108,41 @@ pub const SPI3 = extern struct { padding1: u1 = 0, }); }; + +/// Serial peripheral interface/Inter-IC sound pub const I2S2ext = extern struct { pub const Address: u32 = 0x40003400; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CPHA: u1, // bit offset: 0 desc: Clock phase - CPOL: u1, // bit offset: 1 desc: Clock polarity - MSTR: u1, // bit offset: 2 desc: Master selection - BR: u3, // bit offset: 3 desc: Baud rate control - SPE: u1, // bit offset: 6 desc: SPI enable - LSBFIRST: u1, // bit offset: 7 desc: Frame format - SSI: u1, // bit offset: 8 desc: Internal slave select - SSM: u1, // bit offset: 9 desc: Software slave management - RXONLY: u1, // bit offset: 10 desc: Receive only - CRCL: u1, // bit offset: 11 desc: CRC length - CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next - CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable - BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode - BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Master selection + MSTR: u1 = 0, + /// Baud rate control + BR: u3 = 0, + /// SPI enable + SPE: u1 = 0, + /// Frame format + LSBFIRST: u1 = 0, + /// Internal slave select + SSI: u1 = 0, + /// Software slave management + SSM: u1 = 0, + /// Receive only + RXONLY: u1 = 0, + /// CRC length + CRCL: u1 = 0, + /// CRC transfer next + CRCNEXT: u1 = 0, + /// Hardware CRC calculation enable + CRCEN: u1 = 0, + /// Output enable in bidirectional mode + BIDIOE: u1 = 0, + /// Bidirectional data mode enable + BIDIMODE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9399,20 +13160,33 @@ pub const I2S2ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable - TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable - SSOE: u1, // bit offset: 2 desc: SS output enable - NSSP: u1, // bit offset: 3 desc: NSS pulse management - FRF: u1, // bit offset: 4 desc: Frame format - ERRIE: u1, // bit offset: 5 desc: Error interrupt enable - RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable - TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable - DS: u4, // bit offset: 8 desc: Data size - FRXTH: u1, // bit offset: 12 desc: FIFO reception threshold - LDMA_RX: u1, // bit offset: 13 desc: Last DMA transfer for reception - LDMA_TX: u1, // bit offset: 14 desc: Last DMA transfer for transmission + /// Rx buffer DMA enable + RXDMAEN: u1 = 0, + /// Tx buffer DMA enable + TXDMAEN: u1 = 0, + /// SS output enable + SSOE: u1 = 0, + /// NSS pulse management + NSSP: u1 = 0, + /// Frame format + FRF: u1 = 0, + /// Error interrupt enable + ERRIE: u1 = 0, + /// RX buffer not empty interrupt enable + RXNEIE: u1 = 0, + /// Tx buffer empty interrupt enable + TXEIE: u1 = 0, + /// Data size + DS: u4 = 0, + /// FIFO reception threshold + FRXTH: u1 = 0, + /// Last DMA transfer for reception + LDMA_RX: u1 = 0, + /// Last DMA transfer for transmission + LDMA_TX: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -9431,19 +13205,31 @@ pub const I2S2ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 status register + + /// status register pub const SR = mmio(Address + 0x00000008, 32, packed struct { - RXNE: u1, // bit offset: 0 desc: Receive buffer not empty - TXE: u1, // bit offset: 1 desc: Transmit buffer empty - CHSIDE: u1, // bit offset: 2 desc: Channel side - UDR: u1, // bit offset: 3 desc: Underrun flag - CRCERR: u1, // bit offset: 4 desc: CRC error flag - MODF: u1, // bit offset: 5 desc: Mode fault - OVR: u1, // bit offset: 6 desc: Overrun flag - BSY: u1, // bit offset: 7 desc: Busy flag - TIFRFE: u1, // bit offset: 8 desc: TI frame format error - FRLVL: u2, // bit offset: 9 desc: FIFO reception level - FTLVL: u2, // bit offset: 11 desc: FIFO transmission level + /// Receive buffer not empty + RXNE: u1 = 0, + /// Transmit buffer empty + TXE: u1 = 0, + /// Channel side + CHSIDE: u1 = 0, + /// Underrun flag + UDR: u1 = 0, + /// CRC error flag + CRCERR: u1 = 0, + /// Mode fault + MODF: u1 = 0, + /// Overrun flag + OVR: u1 = 0, + /// Busy flag + BSY: u1 = 0, + /// TI frame format error + TIFRFE: u1 = 0, + /// FIFO reception level + FRLVL: u2 = 0, + /// FIFO transmission level + FTLVL: u2 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -9464,9 +13250,11 @@ pub const I2S2ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 data register + + /// data register pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - DR: u16, // bit offset: 0 desc: Data register + /// Data register + DR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9484,9 +13272,11 @@ pub const I2S2ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 CRC polynomial register + + /// CRC polynomial register pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + /// CRC polynomial register + CRCPOLY: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9504,9 +13294,11 @@ pub const I2S2ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 RX CRC register + + /// RX CRC register pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - RxCRC: u16, // bit offset: 0 desc: Rx CRC register + /// Rx CRC register + RxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9524,9 +13316,11 @@ pub const I2S2ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 TX CRC register + + /// TX CRC register pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - TxCRC: u16, // bit offset: 0 desc: Tx CRC register + /// Tx CRC register + TxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9544,17 +13338,26 @@ pub const I2S2ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 I2S configuration register + + /// I2S configuration register pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) - DATLEN: u2, // bit offset: 1 desc: Data length to be transferred - CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity - I2SSTD: u2, // bit offset: 4 desc: I2S standard selection - reserved1: u1 = 0, - PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization - I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode - I2SE: u1, // bit offset: 10 desc: I2S Enable - I2SMOD: u1, // bit offset: 11 desc: I2S mode selection + /// Channel length (number of bits per audio channel) + CHLEN: u1 = 0, + /// Data length to be transferred + DATLEN: u2 = 0, + /// Steady state clock polarity + CKPOL: u1 = 0, + /// I2S standard selection + I2SSTD: u2 = 0, + reserved1: u1 = 0, + /// PCM frame synchronization + PCMSYNC: u1 = 0, + /// I2S configuration mode + I2SCFG: u2 = 0, + /// I2S Enable + I2SE: u1 = 0, + /// I2S mode selection + I2SMOD: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -9576,11 +13379,15 @@ pub const I2S2ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 I2S prescaler register + + /// I2S prescaler register pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler - ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler - MCKOE: u1, // bit offset: 9 desc: Master clock output enable + /// I2S Linear prescaler + I2SDIV: u8 = 0, + /// Odd factor for the prescaler + ODD: u1 = 0, + /// Master clock output enable + MCKOE: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -9605,24 +13412,41 @@ pub const I2S2ext = extern struct { padding1: u1 = 0, }); }; + +/// Serial peripheral interface/Inter-IC sound pub const I2S3ext = extern struct { pub const Address: u32 = 0x40004000; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CPHA: u1, // bit offset: 0 desc: Clock phase - CPOL: u1, // bit offset: 1 desc: Clock polarity - MSTR: u1, // bit offset: 2 desc: Master selection - BR: u3, // bit offset: 3 desc: Baud rate control - SPE: u1, // bit offset: 6 desc: SPI enable - LSBFIRST: u1, // bit offset: 7 desc: Frame format - SSI: u1, // bit offset: 8 desc: Internal slave select - SSM: u1, // bit offset: 9 desc: Software slave management - RXONLY: u1, // bit offset: 10 desc: Receive only - CRCL: u1, // bit offset: 11 desc: CRC length - CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next - CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable - BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode - BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Master selection + MSTR: u1 = 0, + /// Baud rate control + BR: u3 = 0, + /// SPI enable + SPE: u1 = 0, + /// Frame format + LSBFIRST: u1 = 0, + /// Internal slave select + SSI: u1 = 0, + /// Software slave management + SSM: u1 = 0, + /// Receive only + RXONLY: u1 = 0, + /// CRC length + CRCL: u1 = 0, + /// CRC transfer next + CRCNEXT: u1 = 0, + /// Hardware CRC calculation enable + CRCEN: u1 = 0, + /// Output enable in bidirectional mode + BIDIOE: u1 = 0, + /// Bidirectional data mode enable + BIDIMODE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9640,20 +13464,33 @@ pub const I2S3ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable - TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable - SSOE: u1, // bit offset: 2 desc: SS output enable - NSSP: u1, // bit offset: 3 desc: NSS pulse management - FRF: u1, // bit offset: 4 desc: Frame format - ERRIE: u1, // bit offset: 5 desc: Error interrupt enable - RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable - TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable - DS: u4, // bit offset: 8 desc: Data size - FRXTH: u1, // bit offset: 12 desc: FIFO reception threshold - LDMA_RX: u1, // bit offset: 13 desc: Last DMA transfer for reception - LDMA_TX: u1, // bit offset: 14 desc: Last DMA transfer for transmission + /// Rx buffer DMA enable + RXDMAEN: u1 = 0, + /// Tx buffer DMA enable + TXDMAEN: u1 = 0, + /// SS output enable + SSOE: u1 = 0, + /// NSS pulse management + NSSP: u1 = 0, + /// Frame format + FRF: u1 = 0, + /// Error interrupt enable + ERRIE: u1 = 0, + /// RX buffer not empty interrupt enable + RXNEIE: u1 = 0, + /// Tx buffer empty interrupt enable + TXEIE: u1 = 0, + /// Data size + DS: u4 = 0, + /// FIFO reception threshold + FRXTH: u1 = 0, + /// Last DMA transfer for reception + LDMA_RX: u1 = 0, + /// Last DMA transfer for transmission + LDMA_TX: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -9672,19 +13509,31 @@ pub const I2S3ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 status register + + /// status register pub const SR = mmio(Address + 0x00000008, 32, packed struct { - RXNE: u1, // bit offset: 0 desc: Receive buffer not empty - TXE: u1, // bit offset: 1 desc: Transmit buffer empty - CHSIDE: u1, // bit offset: 2 desc: Channel side - UDR: u1, // bit offset: 3 desc: Underrun flag - CRCERR: u1, // bit offset: 4 desc: CRC error flag - MODF: u1, // bit offset: 5 desc: Mode fault - OVR: u1, // bit offset: 6 desc: Overrun flag - BSY: u1, // bit offset: 7 desc: Busy flag - TIFRFE: u1, // bit offset: 8 desc: TI frame format error - FRLVL: u2, // bit offset: 9 desc: FIFO reception level - FTLVL: u2, // bit offset: 11 desc: FIFO transmission level + /// Receive buffer not empty + RXNE: u1 = 0, + /// Transmit buffer empty + TXE: u1 = 0, + /// Channel side + CHSIDE: u1 = 0, + /// Underrun flag + UDR: u1 = 0, + /// CRC error flag + CRCERR: u1 = 0, + /// Mode fault + MODF: u1 = 0, + /// Overrun flag + OVR: u1 = 0, + /// Busy flag + BSY: u1 = 0, + /// TI frame format error + TIFRFE: u1 = 0, + /// FIFO reception level + FRLVL: u2 = 0, + /// FIFO transmission level + FTLVL: u2 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -9705,9 +13554,11 @@ pub const I2S3ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 data register + + /// data register pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - DR: u16, // bit offset: 0 desc: Data register + /// Data register + DR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9725,9 +13576,11 @@ pub const I2S3ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 CRC polynomial register + + /// CRC polynomial register pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + /// CRC polynomial register + CRCPOLY: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9745,9 +13598,11 @@ pub const I2S3ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 RX CRC register + + /// RX CRC register pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - RxCRC: u16, // bit offset: 0 desc: Rx CRC register + /// Rx CRC register + RxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9765,9 +13620,11 @@ pub const I2S3ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 TX CRC register + + /// TX CRC register pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - TxCRC: u16, // bit offset: 0 desc: Tx CRC register + /// Tx CRC register + TxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9785,17 +13642,26 @@ pub const I2S3ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 I2S configuration register + + /// I2S configuration register pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) - DATLEN: u2, // bit offset: 1 desc: Data length to be transferred - CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity - I2SSTD: u2, // bit offset: 4 desc: I2S standard selection - reserved1: u1 = 0, - PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization - I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode - I2SE: u1, // bit offset: 10 desc: I2S Enable - I2SMOD: u1, // bit offset: 11 desc: I2S mode selection + /// Channel length (number of bits per audio channel) + CHLEN: u1 = 0, + /// Data length to be transferred + DATLEN: u2 = 0, + /// Steady state clock polarity + CKPOL: u1 = 0, + /// I2S standard selection + I2SSTD: u2 = 0, + reserved1: u1 = 0, + /// PCM frame synchronization + PCMSYNC: u1 = 0, + /// I2S configuration mode + I2SCFG: u2 = 0, + /// I2S Enable + I2SE: u1 = 0, + /// I2S mode selection + I2SMOD: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -9817,11 +13683,15 @@ pub const I2S3ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 I2S prescaler register + + /// I2S prescaler register pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler - ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler - MCKOE: u1, // bit offset: 9 desc: Master clock output enable + /// I2S Linear prescaler + I2SDIV: u8 = 0, + /// Odd factor for the prescaler + ODD: u1 = 0, + /// Master clock output enable + MCKOE: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -9846,24 +13716,41 @@ pub const I2S3ext = extern struct { padding1: u1 = 0, }); }; + +/// Serial peripheral interface/Inter-IC sound pub const SPI4 = extern struct { pub const Address: u32 = 0x40013c00; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CPHA: u1, // bit offset: 0 desc: Clock phase - CPOL: u1, // bit offset: 1 desc: Clock polarity - MSTR: u1, // bit offset: 2 desc: Master selection - BR: u3, // bit offset: 3 desc: Baud rate control - SPE: u1, // bit offset: 6 desc: SPI enable - LSBFIRST: u1, // bit offset: 7 desc: Frame format - SSI: u1, // bit offset: 8 desc: Internal slave select - SSM: u1, // bit offset: 9 desc: Software slave management - RXONLY: u1, // bit offset: 10 desc: Receive only - CRCL: u1, // bit offset: 11 desc: CRC length - CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next - CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable - BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode - BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Master selection + MSTR: u1 = 0, + /// Baud rate control + BR: u3 = 0, + /// SPI enable + SPE: u1 = 0, + /// Frame format + LSBFIRST: u1 = 0, + /// Internal slave select + SSI: u1 = 0, + /// Software slave management + SSM: u1 = 0, + /// Receive only + RXONLY: u1 = 0, + /// CRC length + CRCL: u1 = 0, + /// CRC transfer next + CRCNEXT: u1 = 0, + /// Hardware CRC calculation enable + CRCEN: u1 = 0, + /// Output enable in bidirectional mode + BIDIOE: u1 = 0, + /// Bidirectional data mode enable + BIDIMODE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9881,20 +13768,33 @@ pub const SPI4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable - TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable - SSOE: u1, // bit offset: 2 desc: SS output enable - NSSP: u1, // bit offset: 3 desc: NSS pulse management - FRF: u1, // bit offset: 4 desc: Frame format - ERRIE: u1, // bit offset: 5 desc: Error interrupt enable - RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable - TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable - DS: u4, // bit offset: 8 desc: Data size - FRXTH: u1, // bit offset: 12 desc: FIFO reception threshold - LDMA_RX: u1, // bit offset: 13 desc: Last DMA transfer for reception - LDMA_TX: u1, // bit offset: 14 desc: Last DMA transfer for transmission + /// Rx buffer DMA enable + RXDMAEN: u1 = 0, + /// Tx buffer DMA enable + TXDMAEN: u1 = 0, + /// SS output enable + SSOE: u1 = 0, + /// NSS pulse management + NSSP: u1 = 0, + /// Frame format + FRF: u1 = 0, + /// Error interrupt enable + ERRIE: u1 = 0, + /// RX buffer not empty interrupt enable + RXNEIE: u1 = 0, + /// Tx buffer empty interrupt enable + TXEIE: u1 = 0, + /// Data size + DS: u4 = 0, + /// FIFO reception threshold + FRXTH: u1 = 0, + /// Last DMA transfer for reception + LDMA_RX: u1 = 0, + /// Last DMA transfer for transmission + LDMA_TX: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -9913,19 +13813,31 @@ pub const SPI4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 status register + + /// status register pub const SR = mmio(Address + 0x00000008, 32, packed struct { - RXNE: u1, // bit offset: 0 desc: Receive buffer not empty - TXE: u1, // bit offset: 1 desc: Transmit buffer empty - CHSIDE: u1, // bit offset: 2 desc: Channel side - UDR: u1, // bit offset: 3 desc: Underrun flag - CRCERR: u1, // bit offset: 4 desc: CRC error flag - MODF: u1, // bit offset: 5 desc: Mode fault - OVR: u1, // bit offset: 6 desc: Overrun flag - BSY: u1, // bit offset: 7 desc: Busy flag - TIFRFE: u1, // bit offset: 8 desc: TI frame format error - FRLVL: u2, // bit offset: 9 desc: FIFO reception level - FTLVL: u2, // bit offset: 11 desc: FIFO transmission level + /// Receive buffer not empty + RXNE: u1 = 0, + /// Transmit buffer empty + TXE: u1 = 0, + /// Channel side + CHSIDE: u1 = 0, + /// Underrun flag + UDR: u1 = 0, + /// CRC error flag + CRCERR: u1 = 0, + /// Mode fault + MODF: u1 = 0, + /// Overrun flag + OVR: u1 = 0, + /// Busy flag + BSY: u1 = 0, + /// TI frame format error + TIFRFE: u1 = 0, + /// FIFO reception level + FRLVL: u2 = 0, + /// FIFO transmission level + FTLVL: u2 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -9946,9 +13858,11 @@ pub const SPI4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 data register + + /// data register pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - DR: u16, // bit offset: 0 desc: Data register + /// Data register + DR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9966,9 +13880,11 @@ pub const SPI4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 CRC polynomial register + + /// CRC polynomial register pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + /// CRC polynomial register + CRCPOLY: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9986,9 +13902,11 @@ pub const SPI4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 RX CRC register + + /// RX CRC register pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - RxCRC: u16, // bit offset: 0 desc: Rx CRC register + /// Rx CRC register + RxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10006,9 +13924,11 @@ pub const SPI4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 TX CRC register + + /// TX CRC register pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - TxCRC: u16, // bit offset: 0 desc: Tx CRC register + /// Tx CRC register + TxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10026,17 +13946,26 @@ pub const SPI4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 I2S configuration register + + /// I2S configuration register pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) - DATLEN: u2, // bit offset: 1 desc: Data length to be transferred - CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity - I2SSTD: u2, // bit offset: 4 desc: I2S standard selection - reserved1: u1 = 0, - PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization - I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode - I2SE: u1, // bit offset: 10 desc: I2S Enable - I2SMOD: u1, // bit offset: 11 desc: I2S mode selection + /// Channel length (number of bits per audio channel) + CHLEN: u1 = 0, + /// Data length to be transferred + DATLEN: u2 = 0, + /// Steady state clock polarity + CKPOL: u1 = 0, + /// I2S standard selection + I2SSTD: u2 = 0, + reserved1: u1 = 0, + /// PCM frame synchronization + PCMSYNC: u1 = 0, + /// I2S configuration mode + I2SCFG: u2 = 0, + /// I2S Enable + I2SE: u1 = 0, + /// I2S mode selection + I2SMOD: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -10058,11 +13987,15 @@ pub const SPI4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 I2S prescaler register + + /// I2S prescaler register pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler - ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler - MCKOE: u1, // bit offset: 9 desc: Master clock output enable + /// I2S Linear prescaler + I2SDIV: u8 = 0, + /// Odd factor for the prescaler + ODD: u1 = 0, + /// Master clock output enable + MCKOE: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -10087,224 +14020,405 @@ pub const SPI4 = extern struct { padding1: u1 = 0, }); }; + +/// External interrupt/event controller pub const EXTI = extern struct { pub const Address: u32 = 0x40010400; - // byte offset: 0 Interrupt mask register + + /// Interrupt mask register pub const IMR1 = mmio(Address + 0x00000000, 32, packed struct { - MR0: u1, // bit offset: 0 desc: Interrupt Mask on line 0 - MR1: u1, // bit offset: 1 desc: Interrupt Mask on line 1 - MR2: u1, // bit offset: 2 desc: Interrupt Mask on line 2 - MR3: u1, // bit offset: 3 desc: Interrupt Mask on line 3 - MR4: u1, // bit offset: 4 desc: Interrupt Mask on line 4 - MR5: u1, // bit offset: 5 desc: Interrupt Mask on line 5 - MR6: u1, // bit offset: 6 desc: Interrupt Mask on line 6 - MR7: u1, // bit offset: 7 desc: Interrupt Mask on line 7 - MR8: u1, // bit offset: 8 desc: Interrupt Mask on line 8 - MR9: u1, // bit offset: 9 desc: Interrupt Mask on line 9 - MR10: u1, // bit offset: 10 desc: Interrupt Mask on line 10 - MR11: u1, // bit offset: 11 desc: Interrupt Mask on line 11 - MR12: u1, // bit offset: 12 desc: Interrupt Mask on line 12 - MR13: u1, // bit offset: 13 desc: Interrupt Mask on line 13 - MR14: u1, // bit offset: 14 desc: Interrupt Mask on line 14 - MR15: u1, // bit offset: 15 desc: Interrupt Mask on line 15 - MR16: u1, // bit offset: 16 desc: Interrupt Mask on line 16 - MR17: u1, // bit offset: 17 desc: Interrupt Mask on line 17 - MR18: u1, // bit offset: 18 desc: Interrupt Mask on line 18 - MR19: u1, // bit offset: 19 desc: Interrupt Mask on line 19 - MR20: u1, // bit offset: 20 desc: Interrupt Mask on line 20 - MR21: u1, // bit offset: 21 desc: Interrupt Mask on line 21 - MR22: u1, // bit offset: 22 desc: Interrupt Mask on line 22 - MR23: u1, // bit offset: 23 desc: Interrupt Mask on line 23 - MR24: u1, // bit offset: 24 desc: Interrupt Mask on line 24 - MR25: u1, // bit offset: 25 desc: Interrupt Mask on line 25 - MR26: u1, // bit offset: 26 desc: Interrupt Mask on line 26 - MR27: u1, // bit offset: 27 desc: Interrupt Mask on line 27 - MR28: u1, // bit offset: 28 desc: Interrupt Mask on line 28 - MR29: u1, // bit offset: 29 desc: Interrupt Mask on line 29 - MR30: u1, // bit offset: 30 desc: Interrupt Mask on line 30 - MR31: u1, // bit offset: 31 desc: Interrupt Mask on line 31 - }); - // byte offset: 4 Event mask register + /// Interrupt Mask on line 0 + MR0: u1 = 0, + /// Interrupt Mask on line 1 + MR1: u1 = 0, + /// Interrupt Mask on line 2 + MR2: u1 = 0, + /// Interrupt Mask on line 3 + MR3: u1 = 0, + /// Interrupt Mask on line 4 + MR4: u1 = 0, + /// Interrupt Mask on line 5 + MR5: u1 = 0, + /// Interrupt Mask on line 6 + MR6: u1 = 0, + /// Interrupt Mask on line 7 + MR7: u1 = 0, + /// Interrupt Mask on line 8 + MR8: u1 = 0, + /// Interrupt Mask on line 9 + MR9: u1 = 0, + /// Interrupt Mask on line 10 + MR10: u1 = 0, + /// Interrupt Mask on line 11 + MR11: u1 = 0, + /// Interrupt Mask on line 12 + MR12: u1 = 0, + /// Interrupt Mask on line 13 + MR13: u1 = 0, + /// Interrupt Mask on line 14 + MR14: u1 = 0, + /// Interrupt Mask on line 15 + MR15: u1 = 0, + /// Interrupt Mask on line 16 + MR16: u1 = 0, + /// Interrupt Mask on line 17 + MR17: u1 = 0, + /// Interrupt Mask on line 18 + MR18: u1 = 0, + /// Interrupt Mask on line 19 + MR19: u1 = 0, + /// Interrupt Mask on line 20 + MR20: u1 = 0, + /// Interrupt Mask on line 21 + MR21: u1 = 0, + /// Interrupt Mask on line 22 + MR22: u1 = 0, + /// Interrupt Mask on line 23 + MR23: u1 = 0, + /// Interrupt Mask on line 24 + MR24: u1 = 0, + /// Interrupt Mask on line 25 + MR25: u1 = 0, + /// Interrupt Mask on line 26 + MR26: u1 = 0, + /// Interrupt Mask on line 27 + MR27: u1 = 0, + /// Interrupt Mask on line 28 + MR28: u1 = 0, + /// Interrupt Mask on line 29 + MR29: u1 = 0, + /// Interrupt Mask on line 30 + MR30: u1 = 0, + /// Interrupt Mask on line 31 + MR31: u1 = 0, + }); + + /// Event mask register pub const EMR1 = mmio(Address + 0x00000004, 32, packed struct { - MR0: u1, // bit offset: 0 desc: Event Mask on line 0 - MR1: u1, // bit offset: 1 desc: Event Mask on line 1 - MR2: u1, // bit offset: 2 desc: Event Mask on line 2 - MR3: u1, // bit offset: 3 desc: Event Mask on line 3 - MR4: u1, // bit offset: 4 desc: Event Mask on line 4 - MR5: u1, // bit offset: 5 desc: Event Mask on line 5 - MR6: u1, // bit offset: 6 desc: Event Mask on line 6 - MR7: u1, // bit offset: 7 desc: Event Mask on line 7 - MR8: u1, // bit offset: 8 desc: Event Mask on line 8 - MR9: u1, // bit offset: 9 desc: Event Mask on line 9 - MR10: u1, // bit offset: 10 desc: Event Mask on line 10 - MR11: u1, // bit offset: 11 desc: Event Mask on line 11 - MR12: u1, // bit offset: 12 desc: Event Mask on line 12 - MR13: u1, // bit offset: 13 desc: Event Mask on line 13 - MR14: u1, // bit offset: 14 desc: Event Mask on line 14 - MR15: u1, // bit offset: 15 desc: Event Mask on line 15 - MR16: u1, // bit offset: 16 desc: Event Mask on line 16 - MR17: u1, // bit offset: 17 desc: Event Mask on line 17 - MR18: u1, // bit offset: 18 desc: Event Mask on line 18 - MR19: u1, // bit offset: 19 desc: Event Mask on line 19 - MR20: u1, // bit offset: 20 desc: Event Mask on line 20 - MR21: u1, // bit offset: 21 desc: Event Mask on line 21 - MR22: u1, // bit offset: 22 desc: Event Mask on line 22 - MR23: u1, // bit offset: 23 desc: Event Mask on line 23 - MR24: u1, // bit offset: 24 desc: Event Mask on line 24 - MR25: u1, // bit offset: 25 desc: Event Mask on line 25 - MR26: u1, // bit offset: 26 desc: Event Mask on line 26 - MR27: u1, // bit offset: 27 desc: Event Mask on line 27 - MR28: u1, // bit offset: 28 desc: Event Mask on line 28 - MR29: u1, // bit offset: 29 desc: Event Mask on line 29 - MR30: u1, // bit offset: 30 desc: Event Mask on line 30 - MR31: u1, // bit offset: 31 desc: Event Mask on line 31 - }); - // byte offset: 8 Rising Trigger selection register + /// Event Mask on line 0 + MR0: u1 = 0, + /// Event Mask on line 1 + MR1: u1 = 0, + /// Event Mask on line 2 + MR2: u1 = 0, + /// Event Mask on line 3 + MR3: u1 = 0, + /// Event Mask on line 4 + MR4: u1 = 0, + /// Event Mask on line 5 + MR5: u1 = 0, + /// Event Mask on line 6 + MR6: u1 = 0, + /// Event Mask on line 7 + MR7: u1 = 0, + /// Event Mask on line 8 + MR8: u1 = 0, + /// Event Mask on line 9 + MR9: u1 = 0, + /// Event Mask on line 10 + MR10: u1 = 0, + /// Event Mask on line 11 + MR11: u1 = 0, + /// Event Mask on line 12 + MR12: u1 = 0, + /// Event Mask on line 13 + MR13: u1 = 0, + /// Event Mask on line 14 + MR14: u1 = 0, + /// Event Mask on line 15 + MR15: u1 = 0, + /// Event Mask on line 16 + MR16: u1 = 0, + /// Event Mask on line 17 + MR17: u1 = 0, + /// Event Mask on line 18 + MR18: u1 = 0, + /// Event Mask on line 19 + MR19: u1 = 0, + /// Event Mask on line 20 + MR20: u1 = 0, + /// Event Mask on line 21 + MR21: u1 = 0, + /// Event Mask on line 22 + MR22: u1 = 0, + /// Event Mask on line 23 + MR23: u1 = 0, + /// Event Mask on line 24 + MR24: u1 = 0, + /// Event Mask on line 25 + MR25: u1 = 0, + /// Event Mask on line 26 + MR26: u1 = 0, + /// Event Mask on line 27 + MR27: u1 = 0, + /// Event Mask on line 28 + MR28: u1 = 0, + /// Event Mask on line 29 + MR29: u1 = 0, + /// Event Mask on line 30 + MR30: u1 = 0, + /// Event Mask on line 31 + MR31: u1 = 0, + }); + + /// Rising Trigger selection register pub const RTSR1 = mmio(Address + 0x00000008, 32, packed struct { - TR0: u1, // bit offset: 0 desc: Rising trigger event configuration of line 0 - TR1: u1, // bit offset: 1 desc: Rising trigger event configuration of line 1 - TR2: u1, // bit offset: 2 desc: Rising trigger event configuration of line 2 - TR3: u1, // bit offset: 3 desc: Rising trigger event configuration of line 3 - TR4: u1, // bit offset: 4 desc: Rising trigger event configuration of line 4 - TR5: u1, // bit offset: 5 desc: Rising trigger event configuration of line 5 - TR6: u1, // bit offset: 6 desc: Rising trigger event configuration of line 6 - TR7: u1, // bit offset: 7 desc: Rising trigger event configuration of line 7 - TR8: u1, // bit offset: 8 desc: Rising trigger event configuration of line 8 - TR9: u1, // bit offset: 9 desc: Rising trigger event configuration of line 9 - TR10: u1, // bit offset: 10 desc: Rising trigger event configuration of line 10 - TR11: u1, // bit offset: 11 desc: Rising trigger event configuration of line 11 - TR12: u1, // bit offset: 12 desc: Rising trigger event configuration of line 12 - TR13: u1, // bit offset: 13 desc: Rising trigger event configuration of line 13 - TR14: u1, // bit offset: 14 desc: Rising trigger event configuration of line 14 - TR15: u1, // bit offset: 15 desc: Rising trigger event configuration of line 15 - TR16: u1, // bit offset: 16 desc: Rising trigger event configuration of line 16 - TR17: u1, // bit offset: 17 desc: Rising trigger event configuration of line 17 - TR18: u1, // bit offset: 18 desc: Rising trigger event configuration of line 18 - TR19: u1, // bit offset: 19 desc: Rising trigger event configuration of line 19 - TR20: u1, // bit offset: 20 desc: Rising trigger event configuration of line 20 - TR21: u1, // bit offset: 21 desc: Rising trigger event configuration of line 21 - TR22: u1, // bit offset: 22 desc: Rising trigger event configuration of line 22 + /// Rising trigger event configuration of line 0 + TR0: u1 = 0, + /// Rising trigger event configuration of line 1 + TR1: u1 = 0, + /// Rising trigger event configuration of line 2 + TR2: u1 = 0, + /// Rising trigger event configuration of line 3 + TR3: u1 = 0, + /// Rising trigger event configuration of line 4 + TR4: u1 = 0, + /// Rising trigger event configuration of line 5 + TR5: u1 = 0, + /// Rising trigger event configuration of line 6 + TR6: u1 = 0, + /// Rising trigger event configuration of line 7 + TR7: u1 = 0, + /// Rising trigger event configuration of line 8 + TR8: u1 = 0, + /// Rising trigger event configuration of line 9 + TR9: u1 = 0, + /// Rising trigger event configuration of line 10 + TR10: u1 = 0, + /// Rising trigger event configuration of line 11 + TR11: u1 = 0, + /// Rising trigger event configuration of line 12 + TR12: u1 = 0, + /// Rising trigger event configuration of line 13 + TR13: u1 = 0, + /// Rising trigger event configuration of line 14 + TR14: u1 = 0, + /// Rising trigger event configuration of line 15 + TR15: u1 = 0, + /// Rising trigger event configuration of line 16 + TR16: u1 = 0, + /// Rising trigger event configuration of line 17 + TR17: u1 = 0, + /// Rising trigger event configuration of line 18 + TR18: u1 = 0, + /// Rising trigger event configuration of line 19 + TR19: u1 = 0, + /// Rising trigger event configuration of line 20 + TR20: u1 = 0, + /// Rising trigger event configuration of line 21 + TR21: u1 = 0, + /// Rising trigger event configuration of line 22 + TR22: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TR29: u1, // bit offset: 29 desc: Rising trigger event configuration of line 29 - TR30: u1, // bit offset: 30 desc: Rising trigger event configuration of line 30 - TR31: u1, // bit offset: 31 desc: Rising trigger event configuration of line 31 + /// Rising trigger event configuration of line 29 + TR29: u1 = 0, + /// Rising trigger event configuration of line 30 + TR30: u1 = 0, + /// Rising trigger event configuration of line 31 + TR31: u1 = 0, }); - // byte offset: 12 Falling Trigger selection register + + /// Falling Trigger selection register pub const FTSR1 = mmio(Address + 0x0000000c, 32, packed struct { - TR0: u1, // bit offset: 0 desc: Falling trigger event configuration of line 0 - TR1: u1, // bit offset: 1 desc: Falling trigger event configuration of line 1 - TR2: u1, // bit offset: 2 desc: Falling trigger event configuration of line 2 - TR3: u1, // bit offset: 3 desc: Falling trigger event configuration of line 3 - TR4: u1, // bit offset: 4 desc: Falling trigger event configuration of line 4 - TR5: u1, // bit offset: 5 desc: Falling trigger event configuration of line 5 - TR6: u1, // bit offset: 6 desc: Falling trigger event configuration of line 6 - TR7: u1, // bit offset: 7 desc: Falling trigger event configuration of line 7 - TR8: u1, // bit offset: 8 desc: Falling trigger event configuration of line 8 - TR9: u1, // bit offset: 9 desc: Falling trigger event configuration of line 9 - TR10: u1, // bit offset: 10 desc: Falling trigger event configuration of line 10 - TR11: u1, // bit offset: 11 desc: Falling trigger event configuration of line 11 - TR12: u1, // bit offset: 12 desc: Falling trigger event configuration of line 12 - TR13: u1, // bit offset: 13 desc: Falling trigger event configuration of line 13 - TR14: u1, // bit offset: 14 desc: Falling trigger event configuration of line 14 - TR15: u1, // bit offset: 15 desc: Falling trigger event configuration of line 15 - TR16: u1, // bit offset: 16 desc: Falling trigger event configuration of line 16 - TR17: u1, // bit offset: 17 desc: Falling trigger event configuration of line 17 - TR18: u1, // bit offset: 18 desc: Falling trigger event configuration of line 18 - TR19: u1, // bit offset: 19 desc: Falling trigger event configuration of line 19 - TR20: u1, // bit offset: 20 desc: Falling trigger event configuration of line 20 - TR21: u1, // bit offset: 21 desc: Falling trigger event configuration of line 21 - TR22: u1, // bit offset: 22 desc: Falling trigger event configuration of line 22 + /// Falling trigger event configuration of line 0 + TR0: u1 = 0, + /// Falling trigger event configuration of line 1 + TR1: u1 = 0, + /// Falling trigger event configuration of line 2 + TR2: u1 = 0, + /// Falling trigger event configuration of line 3 + TR3: u1 = 0, + /// Falling trigger event configuration of line 4 + TR4: u1 = 0, + /// Falling trigger event configuration of line 5 + TR5: u1 = 0, + /// Falling trigger event configuration of line 6 + TR6: u1 = 0, + /// Falling trigger event configuration of line 7 + TR7: u1 = 0, + /// Falling trigger event configuration of line 8 + TR8: u1 = 0, + /// Falling trigger event configuration of line 9 + TR9: u1 = 0, + /// Falling trigger event configuration of line 10 + TR10: u1 = 0, + /// Falling trigger event configuration of line 11 + TR11: u1 = 0, + /// Falling trigger event configuration of line 12 + TR12: u1 = 0, + /// Falling trigger event configuration of line 13 + TR13: u1 = 0, + /// Falling trigger event configuration of line 14 + TR14: u1 = 0, + /// Falling trigger event configuration of line 15 + TR15: u1 = 0, + /// Falling trigger event configuration of line 16 + TR16: u1 = 0, + /// Falling trigger event configuration of line 17 + TR17: u1 = 0, + /// Falling trigger event configuration of line 18 + TR18: u1 = 0, + /// Falling trigger event configuration of line 19 + TR19: u1 = 0, + /// Falling trigger event configuration of line 20 + TR20: u1 = 0, + /// Falling trigger event configuration of line 21 + TR21: u1 = 0, + /// Falling trigger event configuration of line 22 + TR22: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TR29: u1, // bit offset: 29 desc: Falling trigger event configuration of line 29 - TR30: u1, // bit offset: 30 desc: Falling trigger event configuration of line 30. - TR31: u1, // bit offset: 31 desc: Falling trigger event configuration of line 31 + /// Falling trigger event configuration of line 29 + TR29: u1 = 0, + /// Falling trigger event configuration of line 30. + TR30: u1 = 0, + /// Falling trigger event configuration of line 31 + TR31: u1 = 0, }); - // byte offset: 16 Software interrupt event register + + /// Software interrupt event register pub const SWIER1 = mmio(Address + 0x00000010, 32, packed struct { - SWIER0: u1, // bit offset: 0 desc: Software Interrupt on line 0 - SWIER1: u1, // bit offset: 1 desc: Software Interrupt on line 1 - SWIER2: u1, // bit offset: 2 desc: Software Interrupt on line 2 - SWIER3: u1, // bit offset: 3 desc: Software Interrupt on line 3 - SWIER4: u1, // bit offset: 4 desc: Software Interrupt on line 4 - SWIER5: u1, // bit offset: 5 desc: Software Interrupt on line 5 - SWIER6: u1, // bit offset: 6 desc: Software Interrupt on line 6 - SWIER7: u1, // bit offset: 7 desc: Software Interrupt on line 7 - SWIER8: u1, // bit offset: 8 desc: Software Interrupt on line 8 - SWIER9: u1, // bit offset: 9 desc: Software Interrupt on line 9 - SWIER10: u1, // bit offset: 10 desc: Software Interrupt on line 10 - SWIER11: u1, // bit offset: 11 desc: Software Interrupt on line 11 - SWIER12: u1, // bit offset: 12 desc: Software Interrupt on line 12 - SWIER13: u1, // bit offset: 13 desc: Software Interrupt on line 13 - SWIER14: u1, // bit offset: 14 desc: Software Interrupt on line 14 - SWIER15: u1, // bit offset: 15 desc: Software Interrupt on line 15 - SWIER16: u1, // bit offset: 16 desc: Software Interrupt on line 16 - SWIER17: u1, // bit offset: 17 desc: Software Interrupt on line 17 - SWIER18: u1, // bit offset: 18 desc: Software Interrupt on line 18 - SWIER19: u1, // bit offset: 19 desc: Software Interrupt on line 19 - SWIER20: u1, // bit offset: 20 desc: Software Interrupt on line 20 - SWIER21: u1, // bit offset: 21 desc: Software Interrupt on line 21 - SWIER22: u1, // bit offset: 22 desc: Software Interrupt on line 22 + /// Software Interrupt on line 0 + SWIER0: u1 = 0, + /// Software Interrupt on line 1 + SWIER1: u1 = 0, + /// Software Interrupt on line 2 + SWIER2: u1 = 0, + /// Software Interrupt on line 3 + SWIER3: u1 = 0, + /// Software Interrupt on line 4 + SWIER4: u1 = 0, + /// Software Interrupt on line 5 + SWIER5: u1 = 0, + /// Software Interrupt on line 6 + SWIER6: u1 = 0, + /// Software Interrupt on line 7 + SWIER7: u1 = 0, + /// Software Interrupt on line 8 + SWIER8: u1 = 0, + /// Software Interrupt on line 9 + SWIER9: u1 = 0, + /// Software Interrupt on line 10 + SWIER10: u1 = 0, + /// Software Interrupt on line 11 + SWIER11: u1 = 0, + /// Software Interrupt on line 12 + SWIER12: u1 = 0, + /// Software Interrupt on line 13 + SWIER13: u1 = 0, + /// Software Interrupt on line 14 + SWIER14: u1 = 0, + /// Software Interrupt on line 15 + SWIER15: u1 = 0, + /// Software Interrupt on line 16 + SWIER16: u1 = 0, + /// Software Interrupt on line 17 + SWIER17: u1 = 0, + /// Software Interrupt on line 18 + SWIER18: u1 = 0, + /// Software Interrupt on line 19 + SWIER19: u1 = 0, + /// Software Interrupt on line 20 + SWIER20: u1 = 0, + /// Software Interrupt on line 21 + SWIER21: u1 = 0, + /// Software Interrupt on line 22 + SWIER22: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - SWIER29: u1, // bit offset: 29 desc: Software Interrupt on line 29 - SWIER30: u1, // bit offset: 30 desc: Software Interrupt on line 309 - SWIER31: u1, // bit offset: 31 desc: Software Interrupt on line 319 + /// Software Interrupt on line 29 + SWIER29: u1 = 0, + /// Software Interrupt on line 309 + SWIER30: u1 = 0, + /// Software Interrupt on line 319 + SWIER31: u1 = 0, }); - // byte offset: 20 Pending register + + /// Pending register pub const PR1 = mmio(Address + 0x00000014, 32, packed struct { - PR0: u1, // bit offset: 0 desc: Pending bit 0 - PR1: u1, // bit offset: 1 desc: Pending bit 1 - PR2: u1, // bit offset: 2 desc: Pending bit 2 - PR3: u1, // bit offset: 3 desc: Pending bit 3 - PR4: u1, // bit offset: 4 desc: Pending bit 4 - PR5: u1, // bit offset: 5 desc: Pending bit 5 - PR6: u1, // bit offset: 6 desc: Pending bit 6 - PR7: u1, // bit offset: 7 desc: Pending bit 7 - PR8: u1, // bit offset: 8 desc: Pending bit 8 - PR9: u1, // bit offset: 9 desc: Pending bit 9 - PR10: u1, // bit offset: 10 desc: Pending bit 10 - PR11: u1, // bit offset: 11 desc: Pending bit 11 - PR12: u1, // bit offset: 12 desc: Pending bit 12 - PR13: u1, // bit offset: 13 desc: Pending bit 13 - PR14: u1, // bit offset: 14 desc: Pending bit 14 - PR15: u1, // bit offset: 15 desc: Pending bit 15 - PR16: u1, // bit offset: 16 desc: Pending bit 16 - PR17: u1, // bit offset: 17 desc: Pending bit 17 - PR18: u1, // bit offset: 18 desc: Pending bit 18 - PR19: u1, // bit offset: 19 desc: Pending bit 19 - PR20: u1, // bit offset: 20 desc: Pending bit 20 - PR21: u1, // bit offset: 21 desc: Pending bit 21 - PR22: u1, // bit offset: 22 desc: Pending bit 22 + /// Pending bit 0 + PR0: u1 = 0, + /// Pending bit 1 + PR1: u1 = 0, + /// Pending bit 2 + PR2: u1 = 0, + /// Pending bit 3 + PR3: u1 = 0, + /// Pending bit 4 + PR4: u1 = 0, + /// Pending bit 5 + PR5: u1 = 0, + /// Pending bit 6 + PR6: u1 = 0, + /// Pending bit 7 + PR7: u1 = 0, + /// Pending bit 8 + PR8: u1 = 0, + /// Pending bit 9 + PR9: u1 = 0, + /// Pending bit 10 + PR10: u1 = 0, + /// Pending bit 11 + PR11: u1 = 0, + /// Pending bit 12 + PR12: u1 = 0, + /// Pending bit 13 + PR13: u1 = 0, + /// Pending bit 14 + PR14: u1 = 0, + /// Pending bit 15 + PR15: u1 = 0, + /// Pending bit 16 + PR16: u1 = 0, + /// Pending bit 17 + PR17: u1 = 0, + /// Pending bit 18 + PR18: u1 = 0, + /// Pending bit 19 + PR19: u1 = 0, + /// Pending bit 20 + PR20: u1 = 0, + /// Pending bit 21 + PR21: u1 = 0, + /// Pending bit 22 + PR22: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - PR29: u1, // bit offset: 29 desc: Pending bit 29 - PR30: u1, // bit offset: 30 desc: Pending bit 30 - PR31: u1, // bit offset: 31 desc: Pending bit 31 + /// Pending bit 29 + PR29: u1 = 0, + /// Pending bit 30 + PR30: u1 = 0, + /// Pending bit 31 + PR31: u1 = 0, }); - // byte offset: 24 Interrupt mask register + + /// Interrupt mask register pub const IMR2 = mmio(Address + 0x00000018, 32, packed struct { - MR32: u1, // bit offset: 0 desc: Interrupt Mask on external/internal line 32 - MR33: u1, // bit offset: 1 desc: Interrupt Mask on external/internal line 33 - MR34: u1, // bit offset: 2 desc: Interrupt Mask on external/internal line 34 - MR35: u1, // bit offset: 3 desc: Interrupt Mask on external/internal line 35 + /// Interrupt Mask on external/internal line 32 + MR32: u1 = 0, + /// Interrupt Mask on external/internal line 33 + MR33: u1 = 0, + /// Interrupt Mask on external/internal line 34 + MR34: u1 = 0, + /// Interrupt Mask on external/internal line 35 + MR35: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -10334,12 +14448,17 @@ pub const EXTI = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 Event mask register + + /// Event mask register pub const EMR2 = mmio(Address + 0x0000001c, 32, packed struct { - MR32: u1, // bit offset: 0 desc: Event mask on external/internal line 32 - MR33: u1, // bit offset: 1 desc: Event mask on external/internal line 33 - MR34: u1, // bit offset: 2 desc: Event mask on external/internal line 34 - MR35: u1, // bit offset: 3 desc: Event mask on external/internal line 35 + /// Event mask on external/internal line 32 + MR32: u1 = 0, + /// Event mask on external/internal line 33 + MR33: u1 = 0, + /// Event mask on external/internal line 34 + MR34: u1 = 0, + /// Event mask on external/internal line 35 + MR35: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -10369,10 +14488,13 @@ pub const EXTI = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 Rising Trigger selection register + + /// Rising Trigger selection register pub const RTSR2 = mmio(Address + 0x00000020, 32, packed struct { - TR32: u1, // bit offset: 0 desc: Rising trigger event configuration bit of line 32 - TR33: u1, // bit offset: 1 desc: Rising trigger event configuration bit of line 33 + /// Rising trigger event configuration bit of line 32 + TR32: u1 = 0, + /// Rising trigger event configuration bit of line 33 + TR33: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -10404,10 +14526,13 @@ pub const EXTI = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 Falling Trigger selection register + + /// Falling Trigger selection register pub const FTSR2 = mmio(Address + 0x00000024, 32, packed struct { - TR32: u1, // bit offset: 0 desc: Falling trigger event configuration bit of line 32 - TR33: u1, // bit offset: 1 desc: Falling trigger event configuration bit of line 33 + /// Falling trigger event configuration bit of line 32 + TR32: u1 = 0, + /// Falling trigger event configuration bit of line 33 + TR33: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -10439,10 +14564,13 @@ pub const EXTI = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 Software interrupt event register + + /// Software interrupt event register pub const SWIER2 = mmio(Address + 0x00000028, 32, packed struct { - SWIER32: u1, // bit offset: 0 desc: Software interrupt on line 32 - SWIER33: u1, // bit offset: 1 desc: Software interrupt on line 33 + /// Software interrupt on line 32 + SWIER32: u1 = 0, + /// Software interrupt on line 33 + SWIER33: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -10474,10 +14602,13 @@ pub const EXTI = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 Pending register + + /// Pending register pub const PR2 = mmio(Address + 0x0000002c, 32, packed struct { - PR32: u1, // bit offset: 0 desc: Pending bit on line 32 - PR33: u1, // bit offset: 1 desc: Pending bit on line 33 + /// Pending bit on line 32 + PR32: u1 = 0, + /// Pending bit on line 33 + PR33: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -10510,17 +14641,27 @@ pub const EXTI = extern struct { padding1: u1 = 0, }); }; + +/// Power control pub const PWR = extern struct { pub const Address: u32 = 0x40007000; - // byte offset: 0 power control register + + /// power control register pub const CR = mmio(Address + 0x00000000, 32, packed struct { - LPDS: u1, // bit offset: 0 desc: Low-power deep sleep - PDDS: u1, // bit offset: 1 desc: Power down deepsleep - CWUF: u1, // bit offset: 2 desc: Clear wakeup flag - CSBF: u1, // bit offset: 3 desc: Clear standby flag - PVDE: u1, // bit offset: 4 desc: Power voltage detector enable - PLS: u3, // bit offset: 5 desc: PVD level selection - DBP: u1, // bit offset: 8 desc: Disable backup domain write protection + /// Low-power deep sleep + LPDS: u1 = 0, + /// Power down deepsleep + PDDS: u1 = 0, + /// Clear wakeup flag + CWUF: u1 = 0, + /// Clear standby flag + CSBF: u1 = 0, + /// Power voltage detector enable + PVDE: u1 = 0, + /// PVD level selection + PLS: u3 = 0, + /// Disable backup domain write protection + DBP: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -10545,18 +14686,24 @@ pub const PWR = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 power control/status register + + /// power control/status register pub const CSR = mmio(Address + 0x00000004, 32, packed struct { - WUF: u1, // bit offset: 0 desc: Wakeup flag - SBF: u1, // bit offset: 1 desc: Standby flag - PVDO: u1, // bit offset: 2 desc: PVD output + /// Wakeup flag + WUF: u1 = 0, + /// Standby flag + SBF: u1 = 0, + /// PVD output + PVDO: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - EWUP1: u1, // bit offset: 8 desc: Enable WKUP1 pin - EWUP2: u1, // bit offset: 9 desc: Enable WKUP2 pin + /// Enable WKUP1 pin + EWUP1: u1 = 0, + /// Enable WKUP2 pin + EWUP2: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -10581,18 +14728,13 @@ pub const PWR = extern struct { padding1: u1 = 0, }); }; + +/// Controller area network pub const CAN = extern struct { pub const Address: u32 = 0x40006400; - // byte offset: 0 master control register + + /// master control register pub const MCR = mmio(Address + 0x00000000, 32, packed struct { - INRQ: u1, // bit offset: 0 desc: INRQ - SLEEP: u1, // bit offset: 1 desc: SLEEP - TXFP: u1, // bit offset: 2 desc: TXFP - RFLM: u1, // bit offset: 3 desc: RFLM - NART: u1, // bit offset: 4 desc: NART - AWUM: u1, // bit offset: 5 desc: AWUM - ABOM: u1, // bit offset: 6 desc: ABOM - TTCM: u1, // bit offset: 7 desc: TTCM reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -10600,8 +14742,6 @@ pub const CAN = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - RESET: u1, // bit offset: 15 desc: RESET - DBF: u1, // bit offset: 16 desc: DBF padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -10618,20 +14758,12 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 master status register + + /// master status register pub const MSR = mmio(Address + 0x00000004, 32, packed struct { - INAK: u1, // bit offset: 0 desc: INAK - SLAK: u1, // bit offset: 1 desc: SLAK - ERRI: u1, // bit offset: 2 desc: ERRI - WKUI: u1, // bit offset: 3 desc: WKUI - SLAKI: u1, // bit offset: 4 desc: SLAKI reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TXM: u1, // bit offset: 8 desc: TXM - RXM: u1, // bit offset: 9 desc: RXM - SAMP: u1, // bit offset: 10 desc: SAMP - RX: u1, // bit offset: 11 desc: RX padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -10653,47 +14785,35 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 transmit status register + + /// transmit status register pub const TSR = mmio(Address + 0x00000008, 32, packed struct { - RQCP0: u1, // bit offset: 0 desc: RQCP0 - TXOK0: u1, // bit offset: 1 desc: TXOK0 - ALST0: u1, // bit offset: 2 desc: ALST0 - TERR0: u1, // bit offset: 3 desc: TERR0 reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ABRQ0: u1, // bit offset: 7 desc: ABRQ0 - RQCP1: u1, // bit offset: 8 desc: RQCP1 - TXOK1: u1, // bit offset: 9 desc: TXOK1 - ALST1: u1, // bit offset: 10 desc: ALST1 - TERR1: u1, // bit offset: 11 desc: TERR1 reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - ABRQ1: u1, // bit offset: 15 desc: ABRQ1 - RQCP2: u1, // bit offset: 16 desc: RQCP2 - TXOK2: u1, // bit offset: 17 desc: TXOK2 - ALST2: u1, // bit offset: 18 desc: ALST2 - TERR2: u1, // bit offset: 19 desc: TERR2 reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, - ABRQ2: u1, // bit offset: 23 desc: ABRQ2 - CODE: u2, // bit offset: 24 desc: CODE - TME0: u1, // bit offset: 26 desc: Lowest priority flag for mailbox 0 - TME1: u1, // bit offset: 27 desc: Lowest priority flag for mailbox 1 - TME2: u1, // bit offset: 28 desc: Lowest priority flag for mailbox 2 - LOW0: u1, // bit offset: 29 desc: Lowest priority flag for mailbox 0 - LOW1: u1, // bit offset: 30 desc: Lowest priority flag for mailbox 1 - LOW2: u1, // bit offset: 31 desc: Lowest priority flag for mailbox 2 - }); - // byte offset: 12 receive FIFO 0 register + /// Lowest priority flag for mailbox 0 + TME0: u1 = 0, + /// Lowest priority flag for mailbox 1 + TME1: u1 = 0, + /// Lowest priority flag for mailbox 2 + TME2: u1 = 0, + /// Lowest priority flag for mailbox 0 + LOW0: u1 = 0, + /// Lowest priority flag for mailbox 1 + LOW1: u1 = 0, + /// Lowest priority flag for mailbox 2 + LOW2: u1 = 0, + }); + + /// receive FIFO 0 register pub const RF0R = mmio(Address + 0x0000000c, 32, packed struct { - FMP0: u2, // bit offset: 0 desc: FMP0 reserved1: u1 = 0, - FULL0: u1, // bit offset: 3 desc: FULL0 - FOVR0: u1, // bit offset: 4 desc: FOVR0 - RFOM0: u1, // bit offset: 5 desc: RFOM0 padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -10721,13 +14841,10 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 receive FIFO 1 register + + /// receive FIFO 1 register pub const RF1R = mmio(Address + 0x00000010, 32, packed struct { - FMP1: u2, // bit offset: 0 desc: FMP1 reserved1: u1 = 0, - FULL1: u1, // bit offset: 3 desc: FULL1 - FOVR1: u1, // bit offset: 4 desc: FOVR1 - RFOM1: u1, // bit offset: 5 desc: RFOM1 padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -10755,26 +14872,13 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 interrupt enable register + + /// interrupt enable register pub const IER = mmio(Address + 0x00000014, 32, packed struct { - TMEIE: u1, // bit offset: 0 desc: TMEIE - FMPIE0: u1, // bit offset: 1 desc: FMPIE0 - FFIE0: u1, // bit offset: 2 desc: FFIE0 - FOVIE0: u1, // bit offset: 3 desc: FOVIE0 - FMPIE1: u1, // bit offset: 4 desc: FMPIE1 - FFIE1: u1, // bit offset: 5 desc: FFIE1 - FOVIE1: u1, // bit offset: 6 desc: FOVIE1 - reserved1: u1 = 0, - EWGIE: u1, // bit offset: 8 desc: EWGIE - EPVIE: u1, // bit offset: 9 desc: EPVIE - BOFIE: u1, // bit offset: 10 desc: BOFIE - LECIE: u1, // bit offset: 11 desc: LECIE + reserved1: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - ERRIE: u1, // bit offset: 15 desc: ERRIE - WKUIE: u1, // bit offset: 16 desc: WKUIE - SLKIE: u1, // bit offset: 17 desc: SLKIE padding14: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, @@ -10790,13 +14894,10 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 error status register + + /// error status register pub const ESR = mmio(Address + 0x00000018, 32, packed struct { - EWGF: u1, // bit offset: 0 desc: EWGF - EPVF: u1, // bit offset: 1 desc: EPVF - BOFF: u1, // bit offset: 2 desc: BOFF reserved1: u1 = 0, - LEC: u3, // bit offset: 4 desc: LEC reserved10: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, @@ -10806,45 +14907,32 @@ pub const CAN = extern struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - TEC: u8, // bit offset: 16 desc: TEC - REC: u8, // bit offset: 24 desc: REC }); - // byte offset: 28 bit timing register + + /// bit timing register pub const BTR = mmio(Address + 0x0000001c, 32, packed struct { - BRP: u10, // bit offset: 0 desc: BRP reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TS1: u4, // bit offset: 16 desc: TS1 - TS2: u3, // bit offset: 20 desc: TS2 reserved7: u1 = 0, - SJW: u2, // bit offset: 24 desc: SJW reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, - LBKM: u1, // bit offset: 30 desc: LBKM - SILM: u1, // bit offset: 31 desc: SILM - }); - // byte offset: 384 TX mailbox identifier register - pub const TI0R = mmio(Address + 0x00000180, 32, packed struct { - TXRQ: u1, // bit offset: 0 desc: TXRQ - RTR: u1, // bit offset: 1 desc: RTR - IDE: u1, // bit offset: 2 desc: IDE - EXID: u18, // bit offset: 3 desc: EXID - STID: u11, // bit offset: 21 desc: STID - }); - // byte offset: 388 mailbox data length control and time stamp register + }); + + /// TX mailbox identifier register + pub const TI0R = mmio(Address + 0x00000180, 32, packed struct {}); + + /// mailbox data length control and time stamp register pub const TDT0R = mmio(Address + 0x00000184, 32, packed struct { - DLC: u4, // bit offset: 0 desc: DLC reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TGT: u1, // bit offset: 8 desc: TGT reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -10852,38 +14940,23 @@ pub const CAN = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - TIME: u16, // bit offset: 16 desc: TIME - }); - // byte offset: 392 mailbox data low register - pub const TDL0R = mmio(Address + 0x00000188, 32, packed struct { - DATA0: u8, // bit offset: 0 desc: DATA0 - DATA1: u8, // bit offset: 8 desc: DATA1 - DATA2: u8, // bit offset: 16 desc: DATA2 - DATA3: u8, // bit offset: 24 desc: DATA3 - }); - // byte offset: 396 mailbox data high register - pub const TDH0R = mmio(Address + 0x0000018c, 32, packed struct { - DATA4: u8, // bit offset: 0 desc: DATA4 - DATA5: u8, // bit offset: 8 desc: DATA5 - DATA6: u8, // bit offset: 16 desc: DATA6 - DATA7: u8, // bit offset: 24 desc: DATA7 - }); - // byte offset: 400 TX mailbox identifier register - pub const TI1R = mmio(Address + 0x00000190, 32, packed struct { - TXRQ: u1, // bit offset: 0 desc: TXRQ - RTR: u1, // bit offset: 1 desc: RTR - IDE: u1, // bit offset: 2 desc: IDE - EXID: u18, // bit offset: 3 desc: EXID - STID: u11, // bit offset: 21 desc: STID - }); - // byte offset: 404 mailbox data length control and time stamp register + }); + + /// mailbox data low register + pub const TDL0R = mmio(Address + 0x00000188, 32, packed struct {}); + + /// mailbox data high register + pub const TDH0R = mmio(Address + 0x0000018c, 32, packed struct {}); + + /// TX mailbox identifier register + pub const TI1R = mmio(Address + 0x00000190, 32, packed struct {}); + + /// mailbox data length control and time stamp register pub const TDT1R = mmio(Address + 0x00000194, 32, packed struct { - DLC: u4, // bit offset: 0 desc: DLC reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TGT: u1, // bit offset: 8 desc: TGT reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -10891,38 +14964,23 @@ pub const CAN = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - TIME: u16, // bit offset: 16 desc: TIME - }); - // byte offset: 408 mailbox data low register - pub const TDL1R = mmio(Address + 0x00000198, 32, packed struct { - DATA0: u8, // bit offset: 0 desc: DATA0 - DATA1: u8, // bit offset: 8 desc: DATA1 - DATA2: u8, // bit offset: 16 desc: DATA2 - DATA3: u8, // bit offset: 24 desc: DATA3 - }); - // byte offset: 412 mailbox data high register - pub const TDH1R = mmio(Address + 0x0000019c, 32, packed struct { - DATA4: u8, // bit offset: 0 desc: DATA4 - DATA5: u8, // bit offset: 8 desc: DATA5 - DATA6: u8, // bit offset: 16 desc: DATA6 - DATA7: u8, // bit offset: 24 desc: DATA7 - }); - // byte offset: 416 TX mailbox identifier register - pub const TI2R = mmio(Address + 0x000001a0, 32, packed struct { - TXRQ: u1, // bit offset: 0 desc: TXRQ - RTR: u1, // bit offset: 1 desc: RTR - IDE: u1, // bit offset: 2 desc: IDE - EXID: u18, // bit offset: 3 desc: EXID - STID: u11, // bit offset: 21 desc: STID - }); - // byte offset: 420 mailbox data length control and time stamp register + }); + + /// mailbox data low register + pub const TDL1R = mmio(Address + 0x00000198, 32, packed struct {}); + + /// mailbox data high register + pub const TDH1R = mmio(Address + 0x0000019c, 32, packed struct {}); + + /// TX mailbox identifier register + pub const TI2R = mmio(Address + 0x000001a0, 32, packed struct {}); + + /// mailbox data length control and time stamp register pub const TDT2R = mmio(Address + 0x000001a4, 32, packed struct { - DLC: u4, // bit offset: 0 desc: DLC reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TGT: u1, // bit offset: 8 desc: TGT reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -10930,89 +14988,56 @@ pub const CAN = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - TIME: u16, // bit offset: 16 desc: TIME - }); - // byte offset: 424 mailbox data low register - pub const TDL2R = mmio(Address + 0x000001a8, 32, packed struct { - DATA0: u8, // bit offset: 0 desc: DATA0 - DATA1: u8, // bit offset: 8 desc: DATA1 - DATA2: u8, // bit offset: 16 desc: DATA2 - DATA3: u8, // bit offset: 24 desc: DATA3 - }); - // byte offset: 428 mailbox data high register - pub const TDH2R = mmio(Address + 0x000001ac, 32, packed struct { - DATA4: u8, // bit offset: 0 desc: DATA4 - DATA5: u8, // bit offset: 8 desc: DATA5 - DATA6: u8, // bit offset: 16 desc: DATA6 - DATA7: u8, // bit offset: 24 desc: DATA7 - }); - // byte offset: 432 receive FIFO mailbox identifier register + }); + + /// mailbox data low register + pub const TDL2R = mmio(Address + 0x000001a8, 32, packed struct {}); + + /// mailbox data high register + pub const TDH2R = mmio(Address + 0x000001ac, 32, packed struct {}); + + /// receive FIFO mailbox identifier register pub const RI0R = mmio(Address + 0x000001b0, 32, packed struct { reserved1: u1 = 0, - RTR: u1, // bit offset: 1 desc: RTR - IDE: u1, // bit offset: 2 desc: IDE - EXID: u18, // bit offset: 3 desc: EXID - STID: u11, // bit offset: 21 desc: STID }); - // byte offset: 436 receive FIFO mailbox data length control and time stamp register + + /// receive FIFO mailbox data length control and time stamp register pub const RDT0R = mmio(Address + 0x000001b4, 32, packed struct { - DLC: u4, // bit offset: 0 desc: DLC reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - FMI: u8, // bit offset: 8 desc: FMI - TIME: u16, // bit offset: 16 desc: TIME - }); - // byte offset: 440 receive FIFO mailbox data low register - pub const RDL0R = mmio(Address + 0x000001b8, 32, packed struct { - DATA0: u8, // bit offset: 0 desc: DATA0 - DATA1: u8, // bit offset: 8 desc: DATA1 - DATA2: u8, // bit offset: 16 desc: DATA2 - DATA3: u8, // bit offset: 24 desc: DATA3 }); - // byte offset: 444 receive FIFO mailbox data high register - pub const RDH0R = mmio(Address + 0x000001bc, 32, packed struct { - DATA4: u8, // bit offset: 0 desc: DATA4 - DATA5: u8, // bit offset: 8 desc: DATA5 - DATA6: u8, // bit offset: 16 desc: DATA6 - DATA7: u8, // bit offset: 24 desc: DATA7 - }); - // byte offset: 448 receive FIFO mailbox identifier register + + /// receive FIFO mailbox data low register + pub const RDL0R = mmio(Address + 0x000001b8, 32, packed struct {}); + + /// receive FIFO mailbox data high register + pub const RDH0R = mmio(Address + 0x000001bc, 32, packed struct {}); + + /// receive FIFO mailbox identifier register pub const RI1R = mmio(Address + 0x000001c0, 32, packed struct { reserved1: u1 = 0, - RTR: u1, // bit offset: 1 desc: RTR - IDE: u1, // bit offset: 2 desc: IDE - EXID: u18, // bit offset: 3 desc: EXID - STID: u11, // bit offset: 21 desc: STID }); - // byte offset: 452 receive FIFO mailbox data length control and time stamp register + + /// receive FIFO mailbox data length control and time stamp register pub const RDT1R = mmio(Address + 0x000001c4, 32, packed struct { - DLC: u4, // bit offset: 0 desc: DLC reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - FMI: u8, // bit offset: 8 desc: FMI - TIME: u16, // bit offset: 16 desc: TIME - }); - // byte offset: 456 receive FIFO mailbox data low register - pub const RDL1R = mmio(Address + 0x000001c8, 32, packed struct { - DATA0: u8, // bit offset: 0 desc: DATA0 - DATA1: u8, // bit offset: 8 desc: DATA1 - DATA2: u8, // bit offset: 16 desc: DATA2 - DATA3: u8, // bit offset: 24 desc: DATA3 }); - // byte offset: 460 receive FIFO mailbox data high register - pub const RDH1R = mmio(Address + 0x000001cc, 32, packed struct { - DATA4: u8, // bit offset: 0 desc: DATA4 - DATA5: u8, // bit offset: 8 desc: DATA5 - DATA6: u8, // bit offset: 16 desc: DATA6 - DATA7: u8, // bit offset: 24 desc: DATA7 - }); - // byte offset: 512 filter master register + + /// receive FIFO mailbox data low register + pub const RDL1R = mmio(Address + 0x000001c8, 32, packed struct {}); + + /// receive FIFO mailbox data high register + pub const RDH1R = mmio(Address + 0x000001cc, 32, packed struct {}); + + /// filter master register pub const FMR = mmio(Address + 0x00000200, 32, packed struct { - FINIT: u1, // bit offset: 0 desc: Filter init mode + /// Filter init mode + FINIT: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -11020,7 +15045,8 @@ pub const CAN = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CAN2SB: u6, // bit offset: 8 desc: CAN2 start bank + /// CAN2 start bank + CAN2SB: u6 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -11040,2121 +15066,4098 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 516 filter mode register + + /// filter mode register pub const FM1R = mmio(Address + 0x00000204, 32, packed struct { - FBM0: u1, // bit offset: 0 desc: Filter mode - FBM1: u1, // bit offset: 1 desc: Filter mode - FBM2: u1, // bit offset: 2 desc: Filter mode - FBM3: u1, // bit offset: 3 desc: Filter mode - FBM4: u1, // bit offset: 4 desc: Filter mode - FBM5: u1, // bit offset: 5 desc: Filter mode - FBM6: u1, // bit offset: 6 desc: Filter mode - FBM7: u1, // bit offset: 7 desc: Filter mode - FBM8: u1, // bit offset: 8 desc: Filter mode - FBM9: u1, // bit offset: 9 desc: Filter mode - FBM10: u1, // bit offset: 10 desc: Filter mode - FBM11: u1, // bit offset: 11 desc: Filter mode - FBM12: u1, // bit offset: 12 desc: Filter mode - FBM13: u1, // bit offset: 13 desc: Filter mode - FBM14: u1, // bit offset: 14 desc: Filter mode - FBM15: u1, // bit offset: 15 desc: Filter mode - FBM16: u1, // bit offset: 16 desc: Filter mode - FBM17: u1, // bit offset: 17 desc: Filter mode - FBM18: u1, // bit offset: 18 desc: Filter mode - FBM19: u1, // bit offset: 19 desc: Filter mode - FBM20: u1, // bit offset: 20 desc: Filter mode - FBM21: u1, // bit offset: 21 desc: Filter mode - FBM22: u1, // bit offset: 22 desc: Filter mode - FBM23: u1, // bit offset: 23 desc: Filter mode - FBM24: u1, // bit offset: 24 desc: Filter mode - FBM25: u1, // bit offset: 25 desc: Filter mode - FBM26: u1, // bit offset: 26 desc: Filter mode - FBM27: u1, // bit offset: 27 desc: Filter mode - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 524 filter scale register + /// Filter mode + FBM0: u1 = 0, + /// Filter mode + FBM1: u1 = 0, + /// Filter mode + FBM2: u1 = 0, + /// Filter mode + FBM3: u1 = 0, + /// Filter mode + FBM4: u1 = 0, + /// Filter mode + FBM5: u1 = 0, + /// Filter mode + FBM6: u1 = 0, + /// Filter mode + FBM7: u1 = 0, + /// Filter mode + FBM8: u1 = 0, + /// Filter mode + FBM9: u1 = 0, + /// Filter mode + FBM10: u1 = 0, + /// Filter mode + FBM11: u1 = 0, + /// Filter mode + FBM12: u1 = 0, + /// Filter mode + FBM13: u1 = 0, + /// Filter mode + FBM14: u1 = 0, + /// Filter mode + FBM15: u1 = 0, + /// Filter mode + FBM16: u1 = 0, + /// Filter mode + FBM17: u1 = 0, + /// Filter mode + FBM18: u1 = 0, + /// Filter mode + FBM19: u1 = 0, + /// Filter mode + FBM20: u1 = 0, + /// Filter mode + FBM21: u1 = 0, + /// Filter mode + FBM22: u1 = 0, + /// Filter mode + FBM23: u1 = 0, + /// Filter mode + FBM24: u1 = 0, + /// Filter mode + FBM25: u1 = 0, + /// Filter mode + FBM26: u1 = 0, + /// Filter mode + FBM27: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// filter scale register pub const FS1R = mmio(Address + 0x0000020c, 32, packed struct { - FSC0: u1, // bit offset: 0 desc: Filter scale configuration - FSC1: u1, // bit offset: 1 desc: Filter scale configuration - FSC2: u1, // bit offset: 2 desc: Filter scale configuration - FSC3: u1, // bit offset: 3 desc: Filter scale configuration - FSC4: u1, // bit offset: 4 desc: Filter scale configuration - FSC5: u1, // bit offset: 5 desc: Filter scale configuration - FSC6: u1, // bit offset: 6 desc: Filter scale configuration - FSC7: u1, // bit offset: 7 desc: Filter scale configuration - FSC8: u1, // bit offset: 8 desc: Filter scale configuration - FSC9: u1, // bit offset: 9 desc: Filter scale configuration - FSC10: u1, // bit offset: 10 desc: Filter scale configuration - FSC11: u1, // bit offset: 11 desc: Filter scale configuration - FSC12: u1, // bit offset: 12 desc: Filter scale configuration - FSC13: u1, // bit offset: 13 desc: Filter scale configuration - FSC14: u1, // bit offset: 14 desc: Filter scale configuration - FSC15: u1, // bit offset: 15 desc: Filter scale configuration - FSC16: u1, // bit offset: 16 desc: Filter scale configuration - FSC17: u1, // bit offset: 17 desc: Filter scale configuration - FSC18: u1, // bit offset: 18 desc: Filter scale configuration - FSC19: u1, // bit offset: 19 desc: Filter scale configuration - FSC20: u1, // bit offset: 20 desc: Filter scale configuration - FSC21: u1, // bit offset: 21 desc: Filter scale configuration - FSC22: u1, // bit offset: 22 desc: Filter scale configuration - FSC23: u1, // bit offset: 23 desc: Filter scale configuration - FSC24: u1, // bit offset: 24 desc: Filter scale configuration - FSC25: u1, // bit offset: 25 desc: Filter scale configuration - FSC26: u1, // bit offset: 26 desc: Filter scale configuration - FSC27: u1, // bit offset: 27 desc: Filter scale configuration - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 532 filter FIFO assignment register + /// Filter scale configuration + FSC0: u1 = 0, + /// Filter scale configuration + FSC1: u1 = 0, + /// Filter scale configuration + FSC2: u1 = 0, + /// Filter scale configuration + FSC3: u1 = 0, + /// Filter scale configuration + FSC4: u1 = 0, + /// Filter scale configuration + FSC5: u1 = 0, + /// Filter scale configuration + FSC6: u1 = 0, + /// Filter scale configuration + FSC7: u1 = 0, + /// Filter scale configuration + FSC8: u1 = 0, + /// Filter scale configuration + FSC9: u1 = 0, + /// Filter scale configuration + FSC10: u1 = 0, + /// Filter scale configuration + FSC11: u1 = 0, + /// Filter scale configuration + FSC12: u1 = 0, + /// Filter scale configuration + FSC13: u1 = 0, + /// Filter scale configuration + FSC14: u1 = 0, + /// Filter scale configuration + FSC15: u1 = 0, + /// Filter scale configuration + FSC16: u1 = 0, + /// Filter scale configuration + FSC17: u1 = 0, + /// Filter scale configuration + FSC18: u1 = 0, + /// Filter scale configuration + FSC19: u1 = 0, + /// Filter scale configuration + FSC20: u1 = 0, + /// Filter scale configuration + FSC21: u1 = 0, + /// Filter scale configuration + FSC22: u1 = 0, + /// Filter scale configuration + FSC23: u1 = 0, + /// Filter scale configuration + FSC24: u1 = 0, + /// Filter scale configuration + FSC25: u1 = 0, + /// Filter scale configuration + FSC26: u1 = 0, + /// Filter scale configuration + FSC27: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// filter FIFO assignment register pub const FFA1R = mmio(Address + 0x00000214, 32, packed struct { - FFA0: u1, // bit offset: 0 desc: Filter FIFO assignment for filter 0 - FFA1: u1, // bit offset: 1 desc: Filter FIFO assignment for filter 1 - FFA2: u1, // bit offset: 2 desc: Filter FIFO assignment for filter 2 - FFA3: u1, // bit offset: 3 desc: Filter FIFO assignment for filter 3 - FFA4: u1, // bit offset: 4 desc: Filter FIFO assignment for filter 4 - FFA5: u1, // bit offset: 5 desc: Filter FIFO assignment for filter 5 - FFA6: u1, // bit offset: 6 desc: Filter FIFO assignment for filter 6 - FFA7: u1, // bit offset: 7 desc: Filter FIFO assignment for filter 7 - FFA8: u1, // bit offset: 8 desc: Filter FIFO assignment for filter 8 - FFA9: u1, // bit offset: 9 desc: Filter FIFO assignment for filter 9 - FFA10: u1, // bit offset: 10 desc: Filter FIFO assignment for filter 10 - FFA11: u1, // bit offset: 11 desc: Filter FIFO assignment for filter 11 - FFA12: u1, // bit offset: 12 desc: Filter FIFO assignment for filter 12 - FFA13: u1, // bit offset: 13 desc: Filter FIFO assignment for filter 13 - FFA14: u1, // bit offset: 14 desc: Filter FIFO assignment for filter 14 - FFA15: u1, // bit offset: 15 desc: Filter FIFO assignment for filter 15 - FFA16: u1, // bit offset: 16 desc: Filter FIFO assignment for filter 16 - FFA17: u1, // bit offset: 17 desc: Filter FIFO assignment for filter 17 - FFA18: u1, // bit offset: 18 desc: Filter FIFO assignment for filter 18 - FFA19: u1, // bit offset: 19 desc: Filter FIFO assignment for filter 19 - FFA20: u1, // bit offset: 20 desc: Filter FIFO assignment for filter 20 - FFA21: u1, // bit offset: 21 desc: Filter FIFO assignment for filter 21 - FFA22: u1, // bit offset: 22 desc: Filter FIFO assignment for filter 22 - FFA23: u1, // bit offset: 23 desc: Filter FIFO assignment for filter 23 - FFA24: u1, // bit offset: 24 desc: Filter FIFO assignment for filter 24 - FFA25: u1, // bit offset: 25 desc: Filter FIFO assignment for filter 25 - FFA26: u1, // bit offset: 26 desc: Filter FIFO assignment for filter 26 - FFA27: u1, // bit offset: 27 desc: Filter FIFO assignment for filter 27 - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 540 CAN filter activation register + /// Filter FIFO assignment for filter 0 + FFA0: u1 = 0, + /// Filter FIFO assignment for filter 1 + FFA1: u1 = 0, + /// Filter FIFO assignment for filter 2 + FFA2: u1 = 0, + /// Filter FIFO assignment for filter 3 + FFA3: u1 = 0, + /// Filter FIFO assignment for filter 4 + FFA4: u1 = 0, + /// Filter FIFO assignment for filter 5 + FFA5: u1 = 0, + /// Filter FIFO assignment for filter 6 + FFA6: u1 = 0, + /// Filter FIFO assignment for filter 7 + FFA7: u1 = 0, + /// Filter FIFO assignment for filter 8 + FFA8: u1 = 0, + /// Filter FIFO assignment for filter 9 + FFA9: u1 = 0, + /// Filter FIFO assignment for filter 10 + FFA10: u1 = 0, + /// Filter FIFO assignment for filter 11 + FFA11: u1 = 0, + /// Filter FIFO assignment for filter 12 + FFA12: u1 = 0, + /// Filter FIFO assignment for filter 13 + FFA13: u1 = 0, + /// Filter FIFO assignment for filter 14 + FFA14: u1 = 0, + /// Filter FIFO assignment for filter 15 + FFA15: u1 = 0, + /// Filter FIFO assignment for filter 16 + FFA16: u1 = 0, + /// Filter FIFO assignment for filter 17 + FFA17: u1 = 0, + /// Filter FIFO assignment for filter 18 + FFA18: u1 = 0, + /// Filter FIFO assignment for filter 19 + FFA19: u1 = 0, + /// Filter FIFO assignment for filter 20 + FFA20: u1 = 0, + /// Filter FIFO assignment for filter 21 + FFA21: u1 = 0, + /// Filter FIFO assignment for filter 22 + FFA22: u1 = 0, + /// Filter FIFO assignment for filter 23 + FFA23: u1 = 0, + /// Filter FIFO assignment for filter 24 + FFA24: u1 = 0, + /// Filter FIFO assignment for filter 25 + FFA25: u1 = 0, + /// Filter FIFO assignment for filter 26 + FFA26: u1 = 0, + /// Filter FIFO assignment for filter 27 + FFA27: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// CAN filter activation register pub const FA1R = mmio(Address + 0x0000021c, 32, packed struct { - FACT0: u1, // bit offset: 0 desc: Filter active - FACT1: u1, // bit offset: 1 desc: Filter active - FACT2: u1, // bit offset: 2 desc: Filter active - FACT3: u1, // bit offset: 3 desc: Filter active - FACT4: u1, // bit offset: 4 desc: Filter active - FACT5: u1, // bit offset: 5 desc: Filter active - FACT6: u1, // bit offset: 6 desc: Filter active - FACT7: u1, // bit offset: 7 desc: Filter active - FACT8: u1, // bit offset: 8 desc: Filter active - FACT9: u1, // bit offset: 9 desc: Filter active - FACT10: u1, // bit offset: 10 desc: Filter active - FACT11: u1, // bit offset: 11 desc: Filter active - FACT12: u1, // bit offset: 12 desc: Filter active - FACT13: u1, // bit offset: 13 desc: Filter active - FACT14: u1, // bit offset: 14 desc: Filter active - FACT15: u1, // bit offset: 15 desc: Filter active - FACT16: u1, // bit offset: 16 desc: Filter active - FACT17: u1, // bit offset: 17 desc: Filter active - FACT18: u1, // bit offset: 18 desc: Filter active - FACT19: u1, // bit offset: 19 desc: Filter active - FACT20: u1, // bit offset: 20 desc: Filter active - FACT21: u1, // bit offset: 21 desc: Filter active - FACT22: u1, // bit offset: 22 desc: Filter active - FACT23: u1, // bit offset: 23 desc: Filter active - FACT24: u1, // bit offset: 24 desc: Filter active - FACT25: u1, // bit offset: 25 desc: Filter active - FACT26: u1, // bit offset: 26 desc: Filter active - FACT27: u1, // bit offset: 27 desc: Filter active - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 576 Filter bank 0 register 1 + /// Filter active + FACT0: u1 = 0, + /// Filter active + FACT1: u1 = 0, + /// Filter active + FACT2: u1 = 0, + /// Filter active + FACT3: u1 = 0, + /// Filter active + FACT4: u1 = 0, + /// Filter active + FACT5: u1 = 0, + /// Filter active + FACT6: u1 = 0, + /// Filter active + FACT7: u1 = 0, + /// Filter active + FACT8: u1 = 0, + /// Filter active + FACT9: u1 = 0, + /// Filter active + FACT10: u1 = 0, + /// Filter active + FACT11: u1 = 0, + /// Filter active + FACT12: u1 = 0, + /// Filter active + FACT13: u1 = 0, + /// Filter active + FACT14: u1 = 0, + /// Filter active + FACT15: u1 = 0, + /// Filter active + FACT16: u1 = 0, + /// Filter active + FACT17: u1 = 0, + /// Filter active + FACT18: u1 = 0, + /// Filter active + FACT19: u1 = 0, + /// Filter active + FACT20: u1 = 0, + /// Filter active + FACT21: u1 = 0, + /// Filter active + FACT22: u1 = 0, + /// Filter active + FACT23: u1 = 0, + /// Filter active + FACT24: u1 = 0, + /// Filter active + FACT25: u1 = 0, + /// Filter active + FACT26: u1 = 0, + /// Filter active + FACT27: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Filter bank 0 register 1 pub const F0R1 = mmio(Address + 0x00000240, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 580 Filter bank 0 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 0 register 2 pub const F0R2 = mmio(Address + 0x00000244, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 584 Filter bank 1 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 1 register 1 pub const F1R1 = mmio(Address + 0x00000248, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 588 Filter bank 1 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 1 register 2 pub const F1R2 = mmio(Address + 0x0000024c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 592 Filter bank 2 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 2 register 1 pub const F2R1 = mmio(Address + 0x00000250, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 596 Filter bank 2 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 2 register 2 pub const F2R2 = mmio(Address + 0x00000254, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 600 Filter bank 3 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 3 register 1 pub const F3R1 = mmio(Address + 0x00000258, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 604 Filter bank 3 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 3 register 2 pub const F3R2 = mmio(Address + 0x0000025c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 608 Filter bank 4 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 4 register 1 pub const F4R1 = mmio(Address + 0x00000260, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 612 Filter bank 4 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 4 register 2 pub const F4R2 = mmio(Address + 0x00000264, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 616 Filter bank 5 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 5 register 1 pub const F5R1 = mmio(Address + 0x00000268, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 620 Filter bank 5 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 5 register 2 pub const F5R2 = mmio(Address + 0x0000026c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 624 Filter bank 6 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 6 register 1 pub const F6R1 = mmio(Address + 0x00000270, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 628 Filter bank 6 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 6 register 2 pub const F6R2 = mmio(Address + 0x00000274, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 632 Filter bank 7 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 7 register 1 pub const F7R1 = mmio(Address + 0x00000278, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 636 Filter bank 7 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 7 register 2 pub const F7R2 = mmio(Address + 0x0000027c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 640 Filter bank 8 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 8 register 1 pub const F8R1 = mmio(Address + 0x00000280, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 644 Filter bank 8 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 8 register 2 pub const F8R2 = mmio(Address + 0x00000284, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 648 Filter bank 9 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 9 register 1 pub const F9R1 = mmio(Address + 0x00000288, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 652 Filter bank 9 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 9 register 2 pub const F9R2 = mmio(Address + 0x0000028c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 656 Filter bank 10 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 10 register 1 pub const F10R1 = mmio(Address + 0x00000290, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 660 Filter bank 10 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 10 register 2 pub const F10R2 = mmio(Address + 0x00000294, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 664 Filter bank 11 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 11 register 1 pub const F11R1 = mmio(Address + 0x00000298, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 668 Filter bank 11 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 11 register 2 pub const F11R2 = mmio(Address + 0x0000029c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 672 Filter bank 4 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 4 register 1 pub const F12R1 = mmio(Address + 0x000002a0, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 676 Filter bank 12 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 12 register 2 pub const F12R2 = mmio(Address + 0x000002a4, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 680 Filter bank 13 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 13 register 1 pub const F13R1 = mmio(Address + 0x000002a8, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 684 Filter bank 13 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 13 register 2 pub const F13R2 = mmio(Address + 0x000002ac, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 688 Filter bank 14 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 14 register 1 pub const F14R1 = mmio(Address + 0x000002b0, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 692 Filter bank 14 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 14 register 2 pub const F14R2 = mmio(Address + 0x000002b4, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 696 Filter bank 15 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 15 register 1 pub const F15R1 = mmio(Address + 0x000002b8, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 700 Filter bank 15 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 15 register 2 pub const F15R2 = mmio(Address + 0x000002bc, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 704 Filter bank 16 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 16 register 1 pub const F16R1 = mmio(Address + 0x000002c0, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 708 Filter bank 16 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 16 register 2 pub const F16R2 = mmio(Address + 0x000002c4, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 712 Filter bank 17 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 17 register 1 pub const F17R1 = mmio(Address + 0x000002c8, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 716 Filter bank 17 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 17 register 2 pub const F17R2 = mmio(Address + 0x000002cc, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 720 Filter bank 18 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 18 register 1 pub const F18R1 = mmio(Address + 0x000002d0, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 724 Filter bank 18 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 18 register 2 pub const F18R2 = mmio(Address + 0x000002d4, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 728 Filter bank 19 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 19 register 1 pub const F19R1 = mmio(Address + 0x000002d8, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 732 Filter bank 19 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 19 register 2 pub const F19R2 = mmio(Address + 0x000002dc, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 736 Filter bank 20 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 20 register 1 pub const F20R1 = mmio(Address + 0x000002e0, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 740 Filter bank 20 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 20 register 2 pub const F20R2 = mmio(Address + 0x000002e4, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 744 Filter bank 21 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 21 register 1 pub const F21R1 = mmio(Address + 0x000002e8, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 748 Filter bank 21 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 21 register 2 pub const F21R2 = mmio(Address + 0x000002ec, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 752 Filter bank 22 register 1 - pub const F22R1 = mmio(Address + 0x000002f0, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 756 Filter bank 22 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 22 register 1 + pub const F22R1 = mmio(Address + 0x000002f0, 32, packed struct { + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 22 register 2 pub const F22R2 = mmio(Address + 0x000002f4, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 760 Filter bank 23 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 23 register 1 pub const F23R1 = mmio(Address + 0x000002f8, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 764 Filter bank 23 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 23 register 2 pub const F23R2 = mmio(Address + 0x000002fc, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 768 Filter bank 24 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 24 register 1 pub const F24R1 = mmio(Address + 0x00000300, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 772 Filter bank 24 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 24 register 2 pub const F24R2 = mmio(Address + 0x00000304, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 776 Filter bank 25 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 25 register 1 pub const F25R1 = mmio(Address + 0x00000308, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 780 Filter bank 25 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 25 register 2 pub const F25R2 = mmio(Address + 0x0000030c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 784 Filter bank 26 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 26 register 1 pub const F26R1 = mmio(Address + 0x00000310, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 788 Filter bank 26 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 26 register 2 pub const F26R2 = mmio(Address + 0x00000314, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 792 Filter bank 27 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 27 register 1 pub const F27R1 = mmio(Address + 0x00000318, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 796 Filter bank 27 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 27 register 2 pub const F27R2 = mmio(Address + 0x0000031c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, }); }; + +/// Universal serial bus full-speed device interface pub const USB_FS = extern struct { pub const Address: u32 = 0x40005c00; - // byte offset: 0 endpoint 0 register + + /// endpoint 0 register pub const USB_EP0R = mmio(Address + 0x00000000, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13172,18 +19175,29 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 endpoint 1 register + + /// endpoint 1 register pub const USB_EP1R = mmio(Address + 0x00000004, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13201,18 +19215,29 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 endpoint 2 register + + /// endpoint 2 register pub const USB_EP2R = mmio(Address + 0x00000008, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13230,18 +19255,29 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 endpoint 3 register + + /// endpoint 3 register pub const USB_EP3R = mmio(Address + 0x0000000c, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13259,18 +19295,29 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 endpoint 4 register + + /// endpoint 4 register pub const USB_EP4R = mmio(Address + 0x00000010, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13288,18 +19335,29 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 endpoint 5 register + + /// endpoint 5 register pub const USB_EP5R = mmio(Address + 0x00000014, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13317,18 +19375,29 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 endpoint 6 register + + /// endpoint 6 register pub const USB_EP6R = mmio(Address + 0x00000018, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13346,18 +19415,29 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 endpoint 7 register + + /// endpoint 7 register pub const USB_EP7R = mmio(Address + 0x0000001c, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13375,24 +19455,38 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 control register + + /// control register pub const USB_CNTR = mmio(Address + 0x00000040, 32, packed struct { - FRES: u1, // bit offset: 0 desc: Force USB Reset - PDWN: u1, // bit offset: 1 desc: Power down - LPMODE: u1, // bit offset: 2 desc: Low-power mode - FSUSP: u1, // bit offset: 3 desc: Force suspend - RESUME: u1, // bit offset: 4 desc: Resume request + /// Force USB Reset + FRES: u1 = 0, + /// Power down + PDWN: u1 = 0, + /// Low-power mode + LPMODE: u1 = 0, + /// Force suspend + FSUSP: u1 = 0, + /// Resume request + RESUME: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ESOFM: u1, // bit offset: 8 desc: Expected start of frame interrupt mask - SOFM: u1, // bit offset: 9 desc: Start of frame interrupt mask - RESETM: u1, // bit offset: 10 desc: USB reset interrupt mask - SUSPM: u1, // bit offset: 11 desc: Suspend mode interrupt mask - WKUPM: u1, // bit offset: 12 desc: Wakeup interrupt mask - ERRM: u1, // bit offset: 13 desc: Error interrupt mask - PMAOVRM: u1, // bit offset: 14 desc: Packet memory area over / underrun interrupt mask - CTRM: u1, // bit offset: 15 desc: Correct transfer interrupt mask + /// Expected start of frame interrupt mask + ESOFM: u1 = 0, + /// Start of frame interrupt mask + SOFM: u1 = 0, + /// USB reset interrupt mask + RESETM: u1 = 0, + /// Suspend mode interrupt mask + SUSPM: u1 = 0, + /// Wakeup interrupt mask + WKUPM: u1 = 0, + /// Error interrupt mask + ERRM: u1 = 0, + /// Packet memory area over / underrun interrupt mask + PMAOVRM: u1 = 0, + /// Correct transfer interrupt mask + CTRM: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13410,21 +19504,32 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 interrupt status register + + /// interrupt status register pub const ISTR = mmio(Address + 0x00000044, 32, packed struct { - EP_ID: u4, // bit offset: 0 desc: Endpoint Identifier - DIR: u1, // bit offset: 4 desc: Direction of transaction + /// Endpoint Identifier + EP_ID: u4 = 0, + /// Direction of transaction + DIR: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ESOF: u1, // bit offset: 8 desc: Expected start frame - SOF: u1, // bit offset: 9 desc: start of frame - RESET: u1, // bit offset: 10 desc: reset request - SUSP: u1, // bit offset: 11 desc: Suspend mode request - WKUP: u1, // bit offset: 12 desc: Wakeup - ERR: u1, // bit offset: 13 desc: Error - PMAOVR: u1, // bit offset: 14 desc: Packet memory area over / underrun - CTR: u1, // bit offset: 15 desc: Correct transfer + /// Expected start frame + ESOF: u1 = 0, + /// start of frame + SOF: u1 = 0, + /// reset request + RESET: u1 = 0, + /// Suspend mode request + SUSP: u1 = 0, + /// Wakeup + WKUP: u1 = 0, + /// Error + ERR: u1 = 0, + /// Packet memory area over / underrun + PMAOVR: u1 = 0, + /// Correct transfer + CTR: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13442,13 +19547,19 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 frame number register + + /// frame number register pub const FNR = mmio(Address + 0x00000048, 32, packed struct { - FN: u11, // bit offset: 0 desc: Frame number - LSOF: u2, // bit offset: 11 desc: Lost SOF - LCK: u1, // bit offset: 13 desc: Locked - RXDM: u1, // bit offset: 14 desc: Receive data - line status - RXDP: u1, // bit offset: 15 desc: Receive data + line status + /// Frame number + FN: u11 = 0, + /// Lost SOF + LSOF: u2 = 0, + /// Locked + LCK: u1 = 0, + /// Receive data - line status + RXDM: u1 = 0, + /// Receive data + line status + RXDP: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13466,16 +19577,25 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 device address + + /// device address pub const DADDR = mmio(Address + 0x0000004c, 32, packed struct { - ADD: u1, // bit offset: 0 desc: Device address - ADD1: u1, // bit offset: 1 desc: Device address - ADD2: u1, // bit offset: 2 desc: Device address - ADD3: u1, // bit offset: 3 desc: Device address - ADD4: u1, // bit offset: 4 desc: Device address - ADD5: u1, // bit offset: 5 desc: Device address - ADD6: u1, // bit offset: 6 desc: Device address - EF: u1, // bit offset: 7 desc: Enable function + /// Device address + ADD: u1 = 0, + /// Device address + ADD1: u1 = 0, + /// Device address + ADD2: u1 = 0, + /// Device address + ADD3: u1 = 0, + /// Device address + ADD4: u1 = 0, + /// Device address + ADD5: u1 = 0, + /// Device address + ADD6: u1 = 0, + /// Enable function + EF: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -13501,12 +19621,14 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 80 Buffer table address + + /// Buffer table address pub const BTABLE = mmio(Address + 0x00000050, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - BTABLE: u13, // bit offset: 3 desc: Buffer table + /// Buffer table + BTABLE: u13 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13525,31 +19647,55 @@ pub const USB_FS = extern struct { padding1: u1 = 0, }); }; + +/// Inter-integrated circuit pub const I2C1 = extern struct { pub const Address: u32 = 0x40005400; - // byte offset: 0 Control register 1 + + /// Control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - PE: u1, // bit offset: 0 desc: Peripheral enable - TXIE: u1, // bit offset: 1 desc: TX Interrupt enable - RXIE: u1, // bit offset: 2 desc: RX Interrupt enable - ADDRIE: u1, // bit offset: 3 desc: Address match interrupt enable (slave only) - NACKIE: u1, // bit offset: 4 desc: Not acknowledge received interrupt enable - STOPIE: u1, // bit offset: 5 desc: STOP detection Interrupt enable - TCIE: u1, // bit offset: 6 desc: Transfer Complete interrupt enable - ERRIE: u1, // bit offset: 7 desc: Error interrupts enable - DNF: u4, // bit offset: 8 desc: Digital noise filter - ANFOFF: u1, // bit offset: 12 desc: Analog noise filter OFF - SWRST: u1, // bit offset: 13 desc: Software reset - TXDMAEN: u1, // bit offset: 14 desc: DMA transmission requests enable - RXDMAEN: u1, // bit offset: 15 desc: DMA reception requests enable - SBC: u1, // bit offset: 16 desc: Slave byte control - NOSTRETCH: u1, // bit offset: 17 desc: Clock stretching disable - WUPEN: u1, // bit offset: 18 desc: Wakeup from STOP enable - GCEN: u1, // bit offset: 19 desc: General call enable - SMBHEN: u1, // bit offset: 20 desc: SMBus Host address enable - SMBDEN: u1, // bit offset: 21 desc: SMBus Device Default address enable - ALERTEN: u1, // bit offset: 22 desc: SMBUS alert enable - PECEN: u1, // bit offset: 23 desc: PEC enable + /// Peripheral enable + PE: u1 = 0, + /// TX Interrupt enable + TXIE: u1 = 0, + /// RX Interrupt enable + RXIE: u1 = 0, + /// Address match interrupt enable (slave only) + ADDRIE: u1 = 0, + /// Not acknowledge received interrupt enable + NACKIE: u1 = 0, + /// STOP detection Interrupt enable + STOPIE: u1 = 0, + /// Transfer Complete interrupt enable + TCIE: u1 = 0, + /// Error interrupts enable + ERRIE: u1 = 0, + /// Digital noise filter + DNF: u4 = 0, + /// Analog noise filter OFF + ANFOFF: u1 = 0, + /// Software reset + SWRST: u1 = 0, + /// DMA transmission requests enable + TXDMAEN: u1 = 0, + /// DMA reception requests enable + RXDMAEN: u1 = 0, + /// Slave byte control + SBC: u1 = 0, + /// Clock stretching disable + NOSTRETCH: u1 = 0, + /// Wakeup from STOP enable + WUPEN: u1 = 0, + /// General call enable + GCEN: u1 = 0, + /// SMBus Host address enable + SMBHEN: u1 = 0, + /// SMBus Device Default address enable + SMBDEN: u1 = 0, + /// SMBUS alert enable + ALERTEN: u1 = 0, + /// PEC enable + PECEN: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -13559,38 +19705,58 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Control register 2 + + /// Control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - SADD0: u1, // bit offset: 0 desc: Slave address bit 0 (master mode) - SADD1: u7, // bit offset: 1 desc: Slave address bit 7:1 (master mode) - SADD8: u2, // bit offset: 8 desc: Slave address bit 9:8 (master mode) - RD_WRN: u1, // bit offset: 10 desc: Transfer direction (master mode) - ADD10: u1, // bit offset: 11 desc: 10-bit addressing mode (master mode) - HEAD10R: u1, // bit offset: 12 desc: 10-bit address header only read direction (master receiver mode) - START: u1, // bit offset: 13 desc: Start generation - STOP: u1, // bit offset: 14 desc: Stop generation (master mode) - NACK: u1, // bit offset: 15 desc: NACK generation (slave mode) - NBYTES: u8, // bit offset: 16 desc: Number of bytes - RELOAD: u1, // bit offset: 24 desc: NBYTES reload mode - AUTOEND: u1, // bit offset: 25 desc: Automatic end mode (master mode) - PECBYTE: u1, // bit offset: 26 desc: Packet error checking byte + /// Slave address bit 0 (master mode) + SADD0: u1 = 0, + /// Slave address bit 7:1 (master mode) + SADD1: u7 = 0, + /// Slave address bit 9:8 (master mode) + SADD8: u2 = 0, + /// Transfer direction (master mode) + RD_WRN: u1 = 0, + /// 10-bit addressing mode (master mode) + ADD10: u1 = 0, + /// 10-bit address header only read direction (master receiver mode) + HEAD10R: u1 = 0, + /// Start generation + START: u1 = 0, + /// Stop generation (master mode) + STOP: u1 = 0, + /// NACK generation (slave mode) + NACK: u1 = 0, + /// Number of bytes + NBYTES: u8 = 0, + /// NBYTES reload mode + RELOAD: u1 = 0, + /// Automatic end mode (master mode) + AUTOEND: u1 = 0, + /// Packet error checking byte + PECBYTE: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Own address register 1 + + /// Own address register 1 pub const OAR1 = mmio(Address + 0x00000008, 32, packed struct { - OA1_0: u1, // bit offset: 0 desc: Interface address - OA1_1: u7, // bit offset: 1 desc: Interface address - OA1_8: u2, // bit offset: 8 desc: Interface address - OA1MODE: u1, // bit offset: 10 desc: Own Address 1 10-bit mode + /// Interface address + OA1_0: u1 = 0, + /// Interface address + OA1_1: u7 = 0, + /// Interface address + OA1_8: u2 = 0, + /// Own Address 1 10-bit mode + OA1MODE: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OA1EN: u1, // bit offset: 15 desc: Own Address 1 enable + /// Own Address 1 enable + OA1EN: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13608,16 +19774,20 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Own address register 2 + + /// Own address register 2 pub const OAR2 = mmio(Address + 0x0000000c, 32, packed struct { reserved1: u1 = 0, - OA2: u7, // bit offset: 1 desc: Interface address - OA2MSK: u3, // bit offset: 8 desc: Own Address 2 masks + /// Interface address + OA2: u7 = 0, + /// Own Address 2 masks + OA2MSK: u3 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - OA2EN: u1, // bit offset: 15 desc: Own Address 2 enable + /// Own Address 2 enable + OA2EN: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13635,51 +19805,81 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Timing register + + /// Timing register pub const TIMINGR = mmio(Address + 0x00000010, 32, packed struct { - SCLL: u8, // bit offset: 0 desc: SCL low period (master mode) - SCLH: u8, // bit offset: 8 desc: SCL high period (master mode) - SDADEL: u4, // bit offset: 16 desc: Data hold time - SCLDEL: u4, // bit offset: 20 desc: Data setup time + /// SCL low period (master mode) + SCLL: u8 = 0, + /// SCL high period (master mode) + SCLH: u8 = 0, + /// Data hold time + SDADEL: u4 = 0, + /// Data setup time + SCLDEL: u4 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - PRESC: u4, // bit offset: 28 desc: Timing prescaler + /// Timing prescaler + PRESC: u4 = 0, }); - // byte offset: 20 Status register 1 + + /// Status register 1 pub const TIMEOUTR = mmio(Address + 0x00000014, 32, packed struct { - TIMEOUTA: u12, // bit offset: 0 desc: Bus timeout A - TIDLE: u1, // bit offset: 12 desc: Idle clock timeout detection + /// Bus timeout A + TIMEOUTA: u12 = 0, + /// Idle clock timeout detection + TIDLE: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TIMOUTEN: u1, // bit offset: 15 desc: Clock timeout enable - TIMEOUTB: u12, // bit offset: 16 desc: Bus timeout B + /// Clock timeout enable + TIMOUTEN: u1 = 0, + /// Bus timeout B + TIMEOUTB: u12 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - TEXTEN: u1, // bit offset: 31 desc: Extended clock timeout enable + /// Extended clock timeout enable + TEXTEN: u1 = 0, }); - // byte offset: 24 Interrupt and Status register + + /// Interrupt and Status register pub const ISR = mmio(Address + 0x00000018, 32, packed struct { - TXE: u1, // bit offset: 0 desc: Transmit data register empty (transmitters) - TXIS: u1, // bit offset: 1 desc: Transmit interrupt status (transmitters) - RXNE: u1, // bit offset: 2 desc: Receive data register not empty (receivers) - ADDR: u1, // bit offset: 3 desc: Address matched (slave mode) - NACKF: u1, // bit offset: 4 desc: Not acknowledge received flag - STOPF: u1, // bit offset: 5 desc: Stop detection flag - TC: u1, // bit offset: 6 desc: Transfer Complete (master mode) - TCR: u1, // bit offset: 7 desc: Transfer Complete Reload - BERR: u1, // bit offset: 8 desc: Bus error - ARLO: u1, // bit offset: 9 desc: Arbitration lost - OVR: u1, // bit offset: 10 desc: Overrun/Underrun (slave mode) - PECERR: u1, // bit offset: 11 desc: PEC Error in reception - TIMEOUT: u1, // bit offset: 12 desc: Timeout or t_low detection flag - ALERT: u1, // bit offset: 13 desc: SMBus alert - reserved1: u1 = 0, - BUSY: u1, // bit offset: 15 desc: Bus busy - DIR: u1, // bit offset: 16 desc: Transfer direction (Slave mode) - ADDCODE: u7, // bit offset: 17 desc: Address match code (Slave mode) + /// Transmit data register empty (transmitters) + TXE: u1 = 0, + /// Transmit interrupt status (transmitters) + TXIS: u1 = 0, + /// Receive data register not empty (receivers) + RXNE: u1 = 0, + /// Address matched (slave mode) + ADDR: u1 = 0, + /// Not acknowledge received flag + NACKF: u1 = 0, + /// Stop detection flag + STOPF: u1 = 0, + /// Transfer Complete (master mode) + TC: u1 = 0, + /// Transfer Complete Reload + TCR: u1 = 0, + /// Bus error + BERR: u1 = 0, + /// Arbitration lost + ARLO: u1 = 0, + /// Overrun/Underrun (slave mode) + OVR: u1 = 0, + /// PEC Error in reception + PECERR: u1 = 0, + /// Timeout or t_low detection flag + TIMEOUT: u1 = 0, + /// SMBus alert + ALERT: u1 = 0, + reserved1: u1 = 0, + /// Bus busy + BUSY: u1 = 0, + /// Transfer direction (Slave mode) + DIR: u1 = 0, + /// Address match code (Slave mode) + ADDCODE: u7 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -13689,22 +19889,32 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 Interrupt clear register + + /// Interrupt clear register pub const ICR = mmio(Address + 0x0000001c, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADDRCF: u1, // bit offset: 3 desc: Address Matched flag clear - NACKCF: u1, // bit offset: 4 desc: Not Acknowledge flag clear - STOPCF: u1, // bit offset: 5 desc: Stop detection flag clear + /// Address Matched flag clear + ADDRCF: u1 = 0, + /// Not Acknowledge flag clear + NACKCF: u1 = 0, + /// Stop detection flag clear + STOPCF: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - BERRCF: u1, // bit offset: 8 desc: Bus error flag clear - ARLOCF: u1, // bit offset: 9 desc: Arbitration lost flag clear - OVRCF: u1, // bit offset: 10 desc: Overrun/Underrun flag clear - PECCF: u1, // bit offset: 11 desc: PEC Error flag clear - TIMOUTCF: u1, // bit offset: 12 desc: Timeout detection flag clear - ALERTCF: u1, // bit offset: 13 desc: Alert flag clear + /// Bus error flag clear + BERRCF: u1 = 0, + /// Arbitration lost flag clear + ARLOCF: u1 = 0, + /// Overrun/Underrun flag clear + OVRCF: u1 = 0, + /// PEC Error flag clear + PECCF: u1 = 0, + /// Timeout detection flag clear + TIMOUTCF: u1 = 0, + /// Alert flag clear + ALERTCF: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -13724,9 +19934,11 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 PEC register + + /// PEC register pub const PECR = mmio(Address + 0x00000020, 32, packed struct { - PEC: u8, // bit offset: 0 desc: Packet error checking register + /// Packet error checking register + PEC: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -13752,9 +19964,11 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 Receive data register + + /// Receive data register pub const RXDR = mmio(Address + 0x00000024, 32, packed struct { - RXDATA: u8, // bit offset: 0 desc: 8-bit receive data + /// 8-bit receive data + RXDATA: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -13780,9 +19994,11 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 Transmit data register + + /// Transmit data register pub const TXDR = mmio(Address + 0x00000028, 32, packed struct { - TXDATA: u8, // bit offset: 0 desc: 8-bit transmit data + /// 8-bit transmit data + TXDATA: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -13809,31 +20025,55 @@ pub const I2C1 = extern struct { padding1: u1 = 0, }); }; + +/// Inter-integrated circuit pub const I2C2 = extern struct { pub const Address: u32 = 0x40005800; - // byte offset: 0 Control register 1 + + /// Control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - PE: u1, // bit offset: 0 desc: Peripheral enable - TXIE: u1, // bit offset: 1 desc: TX Interrupt enable - RXIE: u1, // bit offset: 2 desc: RX Interrupt enable - ADDRIE: u1, // bit offset: 3 desc: Address match interrupt enable (slave only) - NACKIE: u1, // bit offset: 4 desc: Not acknowledge received interrupt enable - STOPIE: u1, // bit offset: 5 desc: STOP detection Interrupt enable - TCIE: u1, // bit offset: 6 desc: Transfer Complete interrupt enable - ERRIE: u1, // bit offset: 7 desc: Error interrupts enable - DNF: u4, // bit offset: 8 desc: Digital noise filter - ANFOFF: u1, // bit offset: 12 desc: Analog noise filter OFF - SWRST: u1, // bit offset: 13 desc: Software reset - TXDMAEN: u1, // bit offset: 14 desc: DMA transmission requests enable - RXDMAEN: u1, // bit offset: 15 desc: DMA reception requests enable - SBC: u1, // bit offset: 16 desc: Slave byte control - NOSTRETCH: u1, // bit offset: 17 desc: Clock stretching disable - WUPEN: u1, // bit offset: 18 desc: Wakeup from STOP enable - GCEN: u1, // bit offset: 19 desc: General call enable - SMBHEN: u1, // bit offset: 20 desc: SMBus Host address enable - SMBDEN: u1, // bit offset: 21 desc: SMBus Device Default address enable - ALERTEN: u1, // bit offset: 22 desc: SMBUS alert enable - PECEN: u1, // bit offset: 23 desc: PEC enable + /// Peripheral enable + PE: u1 = 0, + /// TX Interrupt enable + TXIE: u1 = 0, + /// RX Interrupt enable + RXIE: u1 = 0, + /// Address match interrupt enable (slave only) + ADDRIE: u1 = 0, + /// Not acknowledge received interrupt enable + NACKIE: u1 = 0, + /// STOP detection Interrupt enable + STOPIE: u1 = 0, + /// Transfer Complete interrupt enable + TCIE: u1 = 0, + /// Error interrupts enable + ERRIE: u1 = 0, + /// Digital noise filter + DNF: u4 = 0, + /// Analog noise filter OFF + ANFOFF: u1 = 0, + /// Software reset + SWRST: u1 = 0, + /// DMA transmission requests enable + TXDMAEN: u1 = 0, + /// DMA reception requests enable + RXDMAEN: u1 = 0, + /// Slave byte control + SBC: u1 = 0, + /// Clock stretching disable + NOSTRETCH: u1 = 0, + /// Wakeup from STOP enable + WUPEN: u1 = 0, + /// General call enable + GCEN: u1 = 0, + /// SMBus Host address enable + SMBHEN: u1 = 0, + /// SMBus Device Default address enable + SMBDEN: u1 = 0, + /// SMBUS alert enable + ALERTEN: u1 = 0, + /// PEC enable + PECEN: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -13843,38 +20083,58 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Control register 2 + + /// Control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - SADD0: u1, // bit offset: 0 desc: Slave address bit 0 (master mode) - SADD1: u7, // bit offset: 1 desc: Slave address bit 7:1 (master mode) - SADD8: u2, // bit offset: 8 desc: Slave address bit 9:8 (master mode) - RD_WRN: u1, // bit offset: 10 desc: Transfer direction (master mode) - ADD10: u1, // bit offset: 11 desc: 10-bit addressing mode (master mode) - HEAD10R: u1, // bit offset: 12 desc: 10-bit address header only read direction (master receiver mode) - START: u1, // bit offset: 13 desc: Start generation - STOP: u1, // bit offset: 14 desc: Stop generation (master mode) - NACK: u1, // bit offset: 15 desc: NACK generation (slave mode) - NBYTES: u8, // bit offset: 16 desc: Number of bytes - RELOAD: u1, // bit offset: 24 desc: NBYTES reload mode - AUTOEND: u1, // bit offset: 25 desc: Automatic end mode (master mode) - PECBYTE: u1, // bit offset: 26 desc: Packet error checking byte + /// Slave address bit 0 (master mode) + SADD0: u1 = 0, + /// Slave address bit 7:1 (master mode) + SADD1: u7 = 0, + /// Slave address bit 9:8 (master mode) + SADD8: u2 = 0, + /// Transfer direction (master mode) + RD_WRN: u1 = 0, + /// 10-bit addressing mode (master mode) + ADD10: u1 = 0, + /// 10-bit address header only read direction (master receiver mode) + HEAD10R: u1 = 0, + /// Start generation + START: u1 = 0, + /// Stop generation (master mode) + STOP: u1 = 0, + /// NACK generation (slave mode) + NACK: u1 = 0, + /// Number of bytes + NBYTES: u8 = 0, + /// NBYTES reload mode + RELOAD: u1 = 0, + /// Automatic end mode (master mode) + AUTOEND: u1 = 0, + /// Packet error checking byte + PECBYTE: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Own address register 1 + + /// Own address register 1 pub const OAR1 = mmio(Address + 0x00000008, 32, packed struct { - OA1_0: u1, // bit offset: 0 desc: Interface address - OA1_1: u7, // bit offset: 1 desc: Interface address - OA1_8: u2, // bit offset: 8 desc: Interface address - OA1MODE: u1, // bit offset: 10 desc: Own Address 1 10-bit mode + /// Interface address + OA1_0: u1 = 0, + /// Interface address + OA1_1: u7 = 0, + /// Interface address + OA1_8: u2 = 0, + /// Own Address 1 10-bit mode + OA1MODE: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OA1EN: u1, // bit offset: 15 desc: Own Address 1 enable + /// Own Address 1 enable + OA1EN: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13892,16 +20152,20 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Own address register 2 + + /// Own address register 2 pub const OAR2 = mmio(Address + 0x0000000c, 32, packed struct { reserved1: u1 = 0, - OA2: u7, // bit offset: 1 desc: Interface address - OA2MSK: u3, // bit offset: 8 desc: Own Address 2 masks + /// Interface address + OA2: u7 = 0, + /// Own Address 2 masks + OA2MSK: u3 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - OA2EN: u1, // bit offset: 15 desc: Own Address 2 enable + /// Own Address 2 enable + OA2EN: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13919,51 +20183,81 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Timing register + + /// Timing register pub const TIMINGR = mmio(Address + 0x00000010, 32, packed struct { - SCLL: u8, // bit offset: 0 desc: SCL low period (master mode) - SCLH: u8, // bit offset: 8 desc: SCL high period (master mode) - SDADEL: u4, // bit offset: 16 desc: Data hold time - SCLDEL: u4, // bit offset: 20 desc: Data setup time + /// SCL low period (master mode) + SCLL: u8 = 0, + /// SCL high period (master mode) + SCLH: u8 = 0, + /// Data hold time + SDADEL: u4 = 0, + /// Data setup time + SCLDEL: u4 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - PRESC: u4, // bit offset: 28 desc: Timing prescaler + /// Timing prescaler + PRESC: u4 = 0, }); - // byte offset: 20 Status register 1 + + /// Status register 1 pub const TIMEOUTR = mmio(Address + 0x00000014, 32, packed struct { - TIMEOUTA: u12, // bit offset: 0 desc: Bus timeout A - TIDLE: u1, // bit offset: 12 desc: Idle clock timeout detection + /// Bus timeout A + TIMEOUTA: u12 = 0, + /// Idle clock timeout detection + TIDLE: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TIMOUTEN: u1, // bit offset: 15 desc: Clock timeout enable - TIMEOUTB: u12, // bit offset: 16 desc: Bus timeout B + /// Clock timeout enable + TIMOUTEN: u1 = 0, + /// Bus timeout B + TIMEOUTB: u12 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - TEXTEN: u1, // bit offset: 31 desc: Extended clock timeout enable + /// Extended clock timeout enable + TEXTEN: u1 = 0, }); - // byte offset: 24 Interrupt and Status register + + /// Interrupt and Status register pub const ISR = mmio(Address + 0x00000018, 32, packed struct { - TXE: u1, // bit offset: 0 desc: Transmit data register empty (transmitters) - TXIS: u1, // bit offset: 1 desc: Transmit interrupt status (transmitters) - RXNE: u1, // bit offset: 2 desc: Receive data register not empty (receivers) - ADDR: u1, // bit offset: 3 desc: Address matched (slave mode) - NACKF: u1, // bit offset: 4 desc: Not acknowledge received flag - STOPF: u1, // bit offset: 5 desc: Stop detection flag - TC: u1, // bit offset: 6 desc: Transfer Complete (master mode) - TCR: u1, // bit offset: 7 desc: Transfer Complete Reload - BERR: u1, // bit offset: 8 desc: Bus error - ARLO: u1, // bit offset: 9 desc: Arbitration lost - OVR: u1, // bit offset: 10 desc: Overrun/Underrun (slave mode) - PECERR: u1, // bit offset: 11 desc: PEC Error in reception - TIMEOUT: u1, // bit offset: 12 desc: Timeout or t_low detection flag - ALERT: u1, // bit offset: 13 desc: SMBus alert - reserved1: u1 = 0, - BUSY: u1, // bit offset: 15 desc: Bus busy - DIR: u1, // bit offset: 16 desc: Transfer direction (Slave mode) - ADDCODE: u7, // bit offset: 17 desc: Address match code (Slave mode) + /// Transmit data register empty (transmitters) + TXE: u1 = 0, + /// Transmit interrupt status (transmitters) + TXIS: u1 = 0, + /// Receive data register not empty (receivers) + RXNE: u1 = 0, + /// Address matched (slave mode) + ADDR: u1 = 0, + /// Not acknowledge received flag + NACKF: u1 = 0, + /// Stop detection flag + STOPF: u1 = 0, + /// Transfer Complete (master mode) + TC: u1 = 0, + /// Transfer Complete Reload + TCR: u1 = 0, + /// Bus error + BERR: u1 = 0, + /// Arbitration lost + ARLO: u1 = 0, + /// Overrun/Underrun (slave mode) + OVR: u1 = 0, + /// PEC Error in reception + PECERR: u1 = 0, + /// Timeout or t_low detection flag + TIMEOUT: u1 = 0, + /// SMBus alert + ALERT: u1 = 0, + reserved1: u1 = 0, + /// Bus busy + BUSY: u1 = 0, + /// Transfer direction (Slave mode) + DIR: u1 = 0, + /// Address match code (Slave mode) + ADDCODE: u7 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -13973,22 +20267,32 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 Interrupt clear register + + /// Interrupt clear register pub const ICR = mmio(Address + 0x0000001c, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADDRCF: u1, // bit offset: 3 desc: Address Matched flag clear - NACKCF: u1, // bit offset: 4 desc: Not Acknowledge flag clear - STOPCF: u1, // bit offset: 5 desc: Stop detection flag clear + /// Address Matched flag clear + ADDRCF: u1 = 0, + /// Not Acknowledge flag clear + NACKCF: u1 = 0, + /// Stop detection flag clear + STOPCF: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - BERRCF: u1, // bit offset: 8 desc: Bus error flag clear - ARLOCF: u1, // bit offset: 9 desc: Arbitration lost flag clear - OVRCF: u1, // bit offset: 10 desc: Overrun/Underrun flag clear - PECCF: u1, // bit offset: 11 desc: PEC Error flag clear - TIMOUTCF: u1, // bit offset: 12 desc: Timeout detection flag clear - ALERTCF: u1, // bit offset: 13 desc: Alert flag clear + /// Bus error flag clear + BERRCF: u1 = 0, + /// Arbitration lost flag clear + ARLOCF: u1 = 0, + /// Overrun/Underrun flag clear + OVRCF: u1 = 0, + /// PEC Error flag clear + PECCF: u1 = 0, + /// Timeout detection flag clear + TIMOUTCF: u1 = 0, + /// Alert flag clear + ALERTCF: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -14008,9 +20312,11 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 PEC register + + /// PEC register pub const PECR = mmio(Address + 0x00000020, 32, packed struct { - PEC: u8, // bit offset: 0 desc: Packet error checking register + /// Packet error checking register + PEC: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -14036,9 +20342,11 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 Receive data register + + /// Receive data register pub const RXDR = mmio(Address + 0x00000024, 32, packed struct { - RXDATA: u8, // bit offset: 0 desc: 8-bit receive data + /// 8-bit receive data + RXDATA: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -14064,9 +20372,11 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 Transmit data register + + /// Transmit data register pub const TXDR = mmio(Address + 0x00000028, 32, packed struct { - TXDATA: u8, // bit offset: 0 desc: 8-bit transmit data + /// 8-bit transmit data + TXDATA: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -14093,31 +20403,55 @@ pub const I2C2 = extern struct { padding1: u1 = 0, }); }; + +/// Inter-integrated circuit pub const I2C3 = extern struct { pub const Address: u32 = 0x40007800; - // byte offset: 0 Control register 1 + + /// Control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - PE: u1, // bit offset: 0 desc: Peripheral enable - TXIE: u1, // bit offset: 1 desc: TX Interrupt enable - RXIE: u1, // bit offset: 2 desc: RX Interrupt enable - ADDRIE: u1, // bit offset: 3 desc: Address match interrupt enable (slave only) - NACKIE: u1, // bit offset: 4 desc: Not acknowledge received interrupt enable - STOPIE: u1, // bit offset: 5 desc: STOP detection Interrupt enable - TCIE: u1, // bit offset: 6 desc: Transfer Complete interrupt enable - ERRIE: u1, // bit offset: 7 desc: Error interrupts enable - DNF: u4, // bit offset: 8 desc: Digital noise filter - ANFOFF: u1, // bit offset: 12 desc: Analog noise filter OFF - SWRST: u1, // bit offset: 13 desc: Software reset - TXDMAEN: u1, // bit offset: 14 desc: DMA transmission requests enable - RXDMAEN: u1, // bit offset: 15 desc: DMA reception requests enable - SBC: u1, // bit offset: 16 desc: Slave byte control - NOSTRETCH: u1, // bit offset: 17 desc: Clock stretching disable - WUPEN: u1, // bit offset: 18 desc: Wakeup from STOP enable - GCEN: u1, // bit offset: 19 desc: General call enable - SMBHEN: u1, // bit offset: 20 desc: SMBus Host address enable - SMBDEN: u1, // bit offset: 21 desc: SMBus Device Default address enable - ALERTEN: u1, // bit offset: 22 desc: SMBUS alert enable - PECEN: u1, // bit offset: 23 desc: PEC enable + /// Peripheral enable + PE: u1 = 0, + /// TX Interrupt enable + TXIE: u1 = 0, + /// RX Interrupt enable + RXIE: u1 = 0, + /// Address match interrupt enable (slave only) + ADDRIE: u1 = 0, + /// Not acknowledge received interrupt enable + NACKIE: u1 = 0, + /// STOP detection Interrupt enable + STOPIE: u1 = 0, + /// Transfer Complete interrupt enable + TCIE: u1 = 0, + /// Error interrupts enable + ERRIE: u1 = 0, + /// Digital noise filter + DNF: u4 = 0, + /// Analog noise filter OFF + ANFOFF: u1 = 0, + /// Software reset + SWRST: u1 = 0, + /// DMA transmission requests enable + TXDMAEN: u1 = 0, + /// DMA reception requests enable + RXDMAEN: u1 = 0, + /// Slave byte control + SBC: u1 = 0, + /// Clock stretching disable + NOSTRETCH: u1 = 0, + /// Wakeup from STOP enable + WUPEN: u1 = 0, + /// General call enable + GCEN: u1 = 0, + /// SMBus Host address enable + SMBHEN: u1 = 0, + /// SMBus Device Default address enable + SMBDEN: u1 = 0, + /// SMBUS alert enable + ALERTEN: u1 = 0, + /// PEC enable + PECEN: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -14127,38 +20461,58 @@ pub const I2C3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Control register 2 + + /// Control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - SADD0: u1, // bit offset: 0 desc: Slave address bit 0 (master mode) - SADD1: u7, // bit offset: 1 desc: Slave address bit 7:1 (master mode) - SADD8: u2, // bit offset: 8 desc: Slave address bit 9:8 (master mode) - RD_WRN: u1, // bit offset: 10 desc: Transfer direction (master mode) - ADD10: u1, // bit offset: 11 desc: 10-bit addressing mode (master mode) - HEAD10R: u1, // bit offset: 12 desc: 10-bit address header only read direction (master receiver mode) - START: u1, // bit offset: 13 desc: Start generation - STOP: u1, // bit offset: 14 desc: Stop generation (master mode) - NACK: u1, // bit offset: 15 desc: NACK generation (slave mode) - NBYTES: u8, // bit offset: 16 desc: Number of bytes - RELOAD: u1, // bit offset: 24 desc: NBYTES reload mode - AUTOEND: u1, // bit offset: 25 desc: Automatic end mode (master mode) - PECBYTE: u1, // bit offset: 26 desc: Packet error checking byte + /// Slave address bit 0 (master mode) + SADD0: u1 = 0, + /// Slave address bit 7:1 (master mode) + SADD1: u7 = 0, + /// Slave address bit 9:8 (master mode) + SADD8: u2 = 0, + /// Transfer direction (master mode) + RD_WRN: u1 = 0, + /// 10-bit addressing mode (master mode) + ADD10: u1 = 0, + /// 10-bit address header only read direction (master receiver mode) + HEAD10R: u1 = 0, + /// Start generation + START: u1 = 0, + /// Stop generation (master mode) + STOP: u1 = 0, + /// NACK generation (slave mode) + NACK: u1 = 0, + /// Number of bytes + NBYTES: u8 = 0, + /// NBYTES reload mode + RELOAD: u1 = 0, + /// Automatic end mode (master mode) + AUTOEND: u1 = 0, + /// Packet error checking byte + PECBYTE: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Own address register 1 + + /// Own address register 1 pub const OAR1 = mmio(Address + 0x00000008, 32, packed struct { - OA1_0: u1, // bit offset: 0 desc: Interface address - OA1_1: u7, // bit offset: 1 desc: Interface address - OA1_8: u2, // bit offset: 8 desc: Interface address - OA1MODE: u1, // bit offset: 10 desc: Own Address 1 10-bit mode + /// Interface address + OA1_0: u1 = 0, + /// Interface address + OA1_1: u7 = 0, + /// Interface address + OA1_8: u2 = 0, + /// Own Address 1 10-bit mode + OA1MODE: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OA1EN: u1, // bit offset: 15 desc: Own Address 1 enable + /// Own Address 1 enable + OA1EN: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14176,16 +20530,20 @@ pub const I2C3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Own address register 2 + + /// Own address register 2 pub const OAR2 = mmio(Address + 0x0000000c, 32, packed struct { reserved1: u1 = 0, - OA2: u7, // bit offset: 1 desc: Interface address - OA2MSK: u3, // bit offset: 8 desc: Own Address 2 masks + /// Interface address + OA2: u7 = 0, + /// Own Address 2 masks + OA2MSK: u3 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - OA2EN: u1, // bit offset: 15 desc: Own Address 2 enable + /// Own Address 2 enable + OA2EN: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14203,51 +20561,81 @@ pub const I2C3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Timing register + + /// Timing register pub const TIMINGR = mmio(Address + 0x00000010, 32, packed struct { - SCLL: u8, // bit offset: 0 desc: SCL low period (master mode) - SCLH: u8, // bit offset: 8 desc: SCL high period (master mode) - SDADEL: u4, // bit offset: 16 desc: Data hold time - SCLDEL: u4, // bit offset: 20 desc: Data setup time + /// SCL low period (master mode) + SCLL: u8 = 0, + /// SCL high period (master mode) + SCLH: u8 = 0, + /// Data hold time + SDADEL: u4 = 0, + /// Data setup time + SCLDEL: u4 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - PRESC: u4, // bit offset: 28 desc: Timing prescaler + /// Timing prescaler + PRESC: u4 = 0, }); - // byte offset: 20 Status register 1 + + /// Status register 1 pub const TIMEOUTR = mmio(Address + 0x00000014, 32, packed struct { - TIMEOUTA: u12, // bit offset: 0 desc: Bus timeout A - TIDLE: u1, // bit offset: 12 desc: Idle clock timeout detection + /// Bus timeout A + TIMEOUTA: u12 = 0, + /// Idle clock timeout detection + TIDLE: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TIMOUTEN: u1, // bit offset: 15 desc: Clock timeout enable - TIMEOUTB: u12, // bit offset: 16 desc: Bus timeout B + /// Clock timeout enable + TIMOUTEN: u1 = 0, + /// Bus timeout B + TIMEOUTB: u12 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - TEXTEN: u1, // bit offset: 31 desc: Extended clock timeout enable + /// Extended clock timeout enable + TEXTEN: u1 = 0, }); - // byte offset: 24 Interrupt and Status register + + /// Interrupt and Status register pub const ISR = mmio(Address + 0x00000018, 32, packed struct { - TXE: u1, // bit offset: 0 desc: Transmit data register empty (transmitters) - TXIS: u1, // bit offset: 1 desc: Transmit interrupt status (transmitters) - RXNE: u1, // bit offset: 2 desc: Receive data register not empty (receivers) - ADDR: u1, // bit offset: 3 desc: Address matched (slave mode) - NACKF: u1, // bit offset: 4 desc: Not acknowledge received flag - STOPF: u1, // bit offset: 5 desc: Stop detection flag - TC: u1, // bit offset: 6 desc: Transfer Complete (master mode) - TCR: u1, // bit offset: 7 desc: Transfer Complete Reload - BERR: u1, // bit offset: 8 desc: Bus error - ARLO: u1, // bit offset: 9 desc: Arbitration lost - OVR: u1, // bit offset: 10 desc: Overrun/Underrun (slave mode) - PECERR: u1, // bit offset: 11 desc: PEC Error in reception - TIMEOUT: u1, // bit offset: 12 desc: Timeout or t_low detection flag - ALERT: u1, // bit offset: 13 desc: SMBus alert - reserved1: u1 = 0, - BUSY: u1, // bit offset: 15 desc: Bus busy - DIR: u1, // bit offset: 16 desc: Transfer direction (Slave mode) - ADDCODE: u7, // bit offset: 17 desc: Address match code (Slave mode) + /// Transmit data register empty (transmitters) + TXE: u1 = 0, + /// Transmit interrupt status (transmitters) + TXIS: u1 = 0, + /// Receive data register not empty (receivers) + RXNE: u1 = 0, + /// Address matched (slave mode) + ADDR: u1 = 0, + /// Not acknowledge received flag + NACKF: u1 = 0, + /// Stop detection flag + STOPF: u1 = 0, + /// Transfer Complete (master mode) + TC: u1 = 0, + /// Transfer Complete Reload + TCR: u1 = 0, + /// Bus error + BERR: u1 = 0, + /// Arbitration lost + ARLO: u1 = 0, + /// Overrun/Underrun (slave mode) + OVR: u1 = 0, + /// PEC Error in reception + PECERR: u1 = 0, + /// Timeout or t_low detection flag + TIMEOUT: u1 = 0, + /// SMBus alert + ALERT: u1 = 0, + reserved1: u1 = 0, + /// Bus busy + BUSY: u1 = 0, + /// Transfer direction (Slave mode) + DIR: u1 = 0, + /// Address match code (Slave mode) + ADDCODE: u7 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -14257,22 +20645,32 @@ pub const I2C3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 Interrupt clear register + + /// Interrupt clear register pub const ICR = mmio(Address + 0x0000001c, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADDRCF: u1, // bit offset: 3 desc: Address Matched flag clear - NACKCF: u1, // bit offset: 4 desc: Not Acknowledge flag clear - STOPCF: u1, // bit offset: 5 desc: Stop detection flag clear + /// Address Matched flag clear + ADDRCF: u1 = 0, + /// Not Acknowledge flag clear + NACKCF: u1 = 0, + /// Stop detection flag clear + STOPCF: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - BERRCF: u1, // bit offset: 8 desc: Bus error flag clear - ARLOCF: u1, // bit offset: 9 desc: Arbitration lost flag clear - OVRCF: u1, // bit offset: 10 desc: Overrun/Underrun flag clear - PECCF: u1, // bit offset: 11 desc: PEC Error flag clear - TIMOUTCF: u1, // bit offset: 12 desc: Timeout detection flag clear - ALERTCF: u1, // bit offset: 13 desc: Alert flag clear + /// Bus error flag clear + BERRCF: u1 = 0, + /// Arbitration lost flag clear + ARLOCF: u1 = 0, + /// Overrun/Underrun flag clear + OVRCF: u1 = 0, + /// PEC Error flag clear + PECCF: u1 = 0, + /// Timeout detection flag clear + TIMOUTCF: u1 = 0, + /// Alert flag clear + ALERTCF: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -14292,9 +20690,11 @@ pub const I2C3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 PEC register + + /// PEC register pub const PECR = mmio(Address + 0x00000020, 32, packed struct { - PEC: u8, // bit offset: 0 desc: Packet error checking register + /// Packet error checking register + PEC: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -14320,9 +20720,11 @@ pub const I2C3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 Receive data register + + /// Receive data register pub const RXDR = mmio(Address + 0x00000024, 32, packed struct { - RXDATA: u8, // bit offset: 0 desc: 8-bit receive data + /// 8-bit receive data + RXDATA: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -14348,9 +20750,11 @@ pub const I2C3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 Transmit data register + + /// Transmit data register pub const TXDR = mmio(Address + 0x00000028, 32, packed struct { - TXDATA: u8, // bit offset: 0 desc: 8-bit transmit data + /// 8-bit transmit data + TXDATA: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -14377,11 +20781,15 @@ pub const I2C3 = extern struct { padding1: u1 = 0, }); }; + +/// Independent watchdog pub const IWDG = extern struct { pub const Address: u32 = 0x40003000; - // byte offset: 0 Key register + + /// Key register pub const KR = mmio(Address + 0x00000000, 32, packed struct { - KEY: u16, // bit offset: 0 desc: Key value + /// Key value + KEY: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14399,9 +20807,11 @@ pub const IWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Prescaler register + + /// Prescaler register pub const PR = mmio(Address + 0x00000004, 32, packed struct { - PR: u3, // bit offset: 0 desc: Prescaler divider + /// Prescaler divider + PR: u3 = 0, padding29: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, @@ -14432,9 +20842,11 @@ pub const IWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Reload register + + /// Reload register pub const RLR = mmio(Address + 0x00000008, 32, packed struct { - RL: u12, // bit offset: 0 desc: Watchdog counter reload value + /// Watchdog counter reload value + RL: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -14456,11 +20868,15 @@ pub const IWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Status register + + /// Status register pub const SR = mmio(Address + 0x0000000c, 32, packed struct { - PVU: u1, // bit offset: 0 desc: Watchdog prescaler value update - RVU: u1, // bit offset: 1 desc: Watchdog counter reload value update - WVU: u1, // bit offset: 2 desc: Watchdog counter window value update + /// Watchdog prescaler value update + PVU: u1 = 0, + /// Watchdog counter reload value update + RVU: u1 = 0, + /// Watchdog counter window value update + WVU: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, @@ -14491,9 +20907,11 @@ pub const IWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Window register + + /// Window register pub const WINR = mmio(Address + 0x00000010, 32, packed struct { - WIN: u12, // bit offset: 0 desc: Watchdog counter window value + /// Watchdog counter window value + WIN: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -14516,12 +20934,17 @@ pub const IWDG = extern struct { padding1: u1 = 0, }); }; + +/// Window watchdog pub const WWDG = extern struct { pub const Address: u32 = 0x40002c00; - // byte offset: 0 Control register + + /// Control register pub const CR = mmio(Address + 0x00000000, 32, packed struct { - T: u7, // bit offset: 0 desc: 7-bit counter - WDGA: u1, // bit offset: 7 desc: Activation bit + /// 7-bit counter + T: u7 = 0, + /// Activation bit + WDGA: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -14547,11 +20970,15 @@ pub const WWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Configuration register + + /// Configuration register pub const CFR = mmio(Address + 0x00000004, 32, packed struct { - W: u7, // bit offset: 0 desc: 7-bit window value - WDGTB: u2, // bit offset: 7 desc: Timer base - EWI: u1, // bit offset: 9 desc: Early wakeup interrupt + /// 7-bit window value + W: u7 = 0, + /// Timer base + WDGTB: u2 = 0, + /// Early wakeup interrupt + EWI: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -14575,9 +21002,11 @@ pub const WWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Status register + + /// Status register pub const SR = mmio(Address + 0x00000008, 32, packed struct { - EWIF: u1, // bit offset: 0 desc: Early wakeup interrupt flag + /// Early wakeup interrupt flag + EWIF: u1 = 0, padding31: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, @@ -14611,19 +21040,29 @@ pub const WWDG = extern struct { padding1: u1 = 0, }); }; + +/// Real-time clock pub const RTC = extern struct { pub const Address: u32 = 0x40002800; - // byte offset: 0 time register + + /// time register pub const TR = mmio(Address + 0x00000000, 32, packed struct { - SU: u4, // bit offset: 0 desc: Second units in BCD format - ST: u3, // bit offset: 4 desc: Second tens in BCD format + /// Second units in BCD format + SU: u4 = 0, + /// Second tens in BCD format + ST: u3 = 0, reserved1: u1 = 0, - MNU: u4, // bit offset: 8 desc: Minute units in BCD format - MNT: u3, // bit offset: 12 desc: Minute tens in BCD format + /// Minute units in BCD format + MNU: u4 = 0, + /// Minute tens in BCD format + MNT: u3 = 0, reserved2: u1 = 0, - HU: u4, // bit offset: 16 desc: Hour units in BCD format - HT: u2, // bit offset: 20 desc: Hour tens in BCD format - PM: u1, // bit offset: 22 desc: AM/PM notation + /// Hour units in BCD format + HU: u4 = 0, + /// Hour tens in BCD format + HT: u2 = 0, + /// AM/PM notation + PM: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -14634,17 +21073,25 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 date register + + /// date register pub const DR = mmio(Address + 0x00000004, 32, packed struct { - DU: u4, // bit offset: 0 desc: Date units in BCD format - DT: u2, // bit offset: 4 desc: Date tens in BCD format + /// Date units in BCD format + DU: u4 = 0, + /// Date tens in BCD format + DT: u2 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MU: u4, // bit offset: 8 desc: Month units in BCD format - MT: u1, // bit offset: 12 desc: Month tens in BCD format - WDU: u3, // bit offset: 13 desc: Week day units - YU: u4, // bit offset: 16 desc: Year units in BCD format - YT: u4, // bit offset: 20 desc: Year tens in BCD format + /// Month units in BCD format + MU: u4 = 0, + /// Month tens in BCD format + MT: u1 = 0, + /// Week day units + WDU: u3 = 0, + /// Year units in BCD format + YU: u4 = 0, + /// Year tens in BCD format + YT: u4 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -14654,29 +21101,50 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 control register + + /// control register pub const CR = mmio(Address + 0x00000008, 32, packed struct { - WCKSEL: u3, // bit offset: 0 desc: Wakeup clock selection - TSEDGE: u1, // bit offset: 3 desc: Time-stamp event active edge - REFCKON: u1, // bit offset: 4 desc: Reference clock detection enable (50 or 60 Hz) - BYPSHAD: u1, // bit offset: 5 desc: Bypass the shadow registers - FMT: u1, // bit offset: 6 desc: Hour format - reserved1: u1 = 0, - ALRAE: u1, // bit offset: 8 desc: Alarm A enable - ALRBE: u1, // bit offset: 9 desc: Alarm B enable - WUTE: u1, // bit offset: 10 desc: Wakeup timer enable - TSE: u1, // bit offset: 11 desc: Time stamp enable - ALRAIE: u1, // bit offset: 12 desc: Alarm A interrupt enable - ALRBIE: u1, // bit offset: 13 desc: Alarm B interrupt enable - WUTIE: u1, // bit offset: 14 desc: Wakeup timer interrupt enable - TSIE: u1, // bit offset: 15 desc: Time-stamp interrupt enable - ADD1H: u1, // bit offset: 16 desc: Add 1 hour (summer time change) - SUB1H: u1, // bit offset: 17 desc: Subtract 1 hour (winter time change) - BKP: u1, // bit offset: 18 desc: Backup - COSEL: u1, // bit offset: 19 desc: Calibration output selection - POL: u1, // bit offset: 20 desc: Output polarity - OSEL: u2, // bit offset: 21 desc: Output selection - COE: u1, // bit offset: 23 desc: Calibration output enable + /// Wakeup clock selection + WCKSEL: u3 = 0, + /// Time-stamp event active edge + TSEDGE: u1 = 0, + /// Reference clock detection enable (50 or 60 Hz) + REFCKON: u1 = 0, + /// Bypass the shadow registers + BYPSHAD: u1 = 0, + /// Hour format + FMT: u1 = 0, + reserved1: u1 = 0, + /// Alarm A enable + ALRAE: u1 = 0, + /// Alarm B enable + ALRBE: u1 = 0, + /// Wakeup timer enable + WUTE: u1 = 0, + /// Time stamp enable + TSE: u1 = 0, + /// Alarm A interrupt enable + ALRAIE: u1 = 0, + /// Alarm B interrupt enable + ALRBIE: u1 = 0, + /// Wakeup timer interrupt enable + WUTIE: u1 = 0, + /// Time-stamp interrupt enable + TSIE: u1 = 0, + /// Add 1 hour (summer time change) + ADD1H: u1 = 0, + /// Subtract 1 hour (winter time change) + SUB1H: u1 = 0, + /// Backup + BKP: u1 = 0, + /// Calibration output selection + COSEL: u1 = 0, + /// Output polarity + POL: u1 = 0, + /// Output selection + OSEL: u2 = 0, + /// Calibration output enable + COE: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -14686,25 +21154,43 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 initialization and status register + + /// initialization and status register pub const ISR = mmio(Address + 0x0000000c, 32, packed struct { - ALRAWF: u1, // bit offset: 0 desc: Alarm A write flag - ALRBWF: u1, // bit offset: 1 desc: Alarm B write flag - WUTWF: u1, // bit offset: 2 desc: Wakeup timer write flag - SHPF: u1, // bit offset: 3 desc: Shift operation pending - INITS: u1, // bit offset: 4 desc: Initialization status flag - RSF: u1, // bit offset: 5 desc: Registers synchronization flag - INITF: u1, // bit offset: 6 desc: Initialization flag - INIT: u1, // bit offset: 7 desc: Initialization mode - ALRAF: u1, // bit offset: 8 desc: Alarm A flag - ALRBF: u1, // bit offset: 9 desc: Alarm B flag - WUTF: u1, // bit offset: 10 desc: Wakeup timer flag - TSF: u1, // bit offset: 11 desc: Time-stamp flag - TSOVF: u1, // bit offset: 12 desc: Time-stamp overflow flag - TAMP1F: u1, // bit offset: 13 desc: Tamper detection flag - TAMP2F: u1, // bit offset: 14 desc: RTC_TAMP2 detection flag - TAMP3F: u1, // bit offset: 15 desc: RTC_TAMP3 detection flag - RECALPF: u1, // bit offset: 16 desc: Recalibration pending Flag + /// Alarm A write flag + ALRAWF: u1 = 0, + /// Alarm B write flag + ALRBWF: u1 = 0, + /// Wakeup timer write flag + WUTWF: u1 = 0, + /// Shift operation pending + SHPF: u1 = 0, + /// Initialization status flag + INITS: u1 = 0, + /// Registers synchronization flag + RSF: u1 = 0, + /// Initialization flag + INITF: u1 = 0, + /// Initialization mode + INIT: u1 = 0, + /// Alarm A flag + ALRAF: u1 = 0, + /// Alarm B flag + ALRBF: u1 = 0, + /// Wakeup timer flag + WUTF: u1 = 0, + /// Time-stamp flag + TSF: u1 = 0, + /// Time-stamp overflow flag + TSOVF: u1 = 0, + /// Tamper detection flag + TAMP1F: u1 = 0, + /// RTC_TAMP2 detection flag + TAMP2F: u1 = 0, + /// RTC_TAMP3 detection flag + TAMP3F: u1 = 0, + /// Recalibration pending Flag + RECALPF: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -14721,11 +21207,14 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 prescaler register + + /// prescaler register pub const PRER = mmio(Address + 0x00000010, 32, packed struct { - PREDIV_S: u15, // bit offset: 0 desc: Synchronous prescaler factor + /// Synchronous prescaler factor + PREDIV_S: u15 = 0, reserved1: u1 = 0, - PREDIV_A: u7, // bit offset: 16 desc: Asynchronous prescaler factor + /// Asynchronous prescaler factor + PREDIV_A: u7 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -14736,9 +21225,11 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 wakeup timer register + + /// wakeup timer register pub const WUTR = mmio(Address + 0x00000014, 32, packed struct { - WUT: u16, // bit offset: 0 desc: Wakeup auto-reload value bits + /// Wakeup auto-reload value bits + WUT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14756,43 +21247,75 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 alarm A register + + /// alarm A register pub const ALRMAR = mmio(Address + 0x0000001c, 32, packed struct { - SU: u4, // bit offset: 0 desc: Second units in BCD format - ST: u3, // bit offset: 4 desc: Second tens in BCD format - MSK1: u1, // bit offset: 7 desc: Alarm A seconds mask - MNU: u4, // bit offset: 8 desc: Minute units in BCD format - MNT: u3, // bit offset: 12 desc: Minute tens in BCD format - MSK2: u1, // bit offset: 15 desc: Alarm A minutes mask - HU: u4, // bit offset: 16 desc: Hour units in BCD format - HT: u2, // bit offset: 20 desc: Hour tens in BCD format - PM: u1, // bit offset: 22 desc: AM/PM notation - MSK3: u1, // bit offset: 23 desc: Alarm A hours mask - DU: u4, // bit offset: 24 desc: Date units or day in BCD format - DT: u2, // bit offset: 28 desc: Date tens in BCD format - WDSEL: u1, // bit offset: 30 desc: Week day selection - MSK4: u1, // bit offset: 31 desc: Alarm A date mask - }); - // byte offset: 32 alarm B register + /// Second units in BCD format + SU: u4 = 0, + /// Second tens in BCD format + ST: u3 = 0, + /// Alarm A seconds mask + MSK1: u1 = 0, + /// Minute units in BCD format + MNU: u4 = 0, + /// Minute tens in BCD format + MNT: u3 = 0, + /// Alarm A minutes mask + MSK2: u1 = 0, + /// Hour units in BCD format + HU: u4 = 0, + /// Hour tens in BCD format + HT: u2 = 0, + /// AM/PM notation + PM: u1 = 0, + /// Alarm A hours mask + MSK3: u1 = 0, + /// Date units or day in BCD format + DU: u4 = 0, + /// Date tens in BCD format + DT: u2 = 0, + /// Week day selection + WDSEL: u1 = 0, + /// Alarm A date mask + MSK4: u1 = 0, + }); + + /// alarm B register pub const ALRMBR = mmio(Address + 0x00000020, 32, packed struct { - SU: u4, // bit offset: 0 desc: Second units in BCD format - ST: u3, // bit offset: 4 desc: Second tens in BCD format - MSK1: u1, // bit offset: 7 desc: Alarm B seconds mask - MNU: u4, // bit offset: 8 desc: Minute units in BCD format - MNT: u3, // bit offset: 12 desc: Minute tens in BCD format - MSK2: u1, // bit offset: 15 desc: Alarm B minutes mask - HU: u4, // bit offset: 16 desc: Hour units in BCD format - HT: u2, // bit offset: 20 desc: Hour tens in BCD format - PM: u1, // bit offset: 22 desc: AM/PM notation - MSK3: u1, // bit offset: 23 desc: Alarm B hours mask - DU: u4, // bit offset: 24 desc: Date units or day in BCD format - DT: u2, // bit offset: 28 desc: Date tens in BCD format - WDSEL: u1, // bit offset: 30 desc: Week day selection - MSK4: u1, // bit offset: 31 desc: Alarm B date mask - }); - // byte offset: 36 write protection register + /// Second units in BCD format + SU: u4 = 0, + /// Second tens in BCD format + ST: u3 = 0, + /// Alarm B seconds mask + MSK1: u1 = 0, + /// Minute units in BCD format + MNU: u4 = 0, + /// Minute tens in BCD format + MNT: u3 = 0, + /// Alarm B minutes mask + MSK2: u1 = 0, + /// Hour units in BCD format + HU: u4 = 0, + /// Hour tens in BCD format + HT: u2 = 0, + /// AM/PM notation + PM: u1 = 0, + /// Alarm B hours mask + MSK3: u1 = 0, + /// Date units or day in BCD format + DU: u4 = 0, + /// Date tens in BCD format + DT: u2 = 0, + /// Week day selection + WDSEL: u1 = 0, + /// Alarm B date mask + MSK4: u1 = 0, + }); + + /// write protection register pub const WPR = mmio(Address + 0x00000024, 32, packed struct { - KEY: u8, // bit offset: 0 desc: Write protection key + /// Write protection key + KEY: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -14818,9 +21341,11 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 sub second register + + /// sub second register pub const SSR = mmio(Address + 0x00000028, 32, packed struct { - SS: u16, // bit offset: 0 desc: Sub second value + /// Sub second value + SS: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14838,9 +21363,11 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 shift control register + + /// shift control register pub const SHIFTR = mmio(Address + 0x0000002c, 32, packed struct { - SUBFS: u15, // bit offset: 0 desc: Subtract a fraction of a second + /// Subtract a fraction of a second + SUBFS: u15 = 0, reserved16: u1 = 0, reserved15: u1 = 0, reserved14: u1 = 0, @@ -14857,19 +21384,28 @@ pub const RTC = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADD1S: u1, // bit offset: 31 desc: Add one second + /// Add one second + ADD1S: u1 = 0, }); - // byte offset: 48 time stamp time register + + /// time stamp time register pub const TSTR = mmio(Address + 0x00000030, 32, packed struct { - SU: u4, // bit offset: 0 desc: Second units in BCD format - ST: u3, // bit offset: 4 desc: Second tens in BCD format + /// Second units in BCD format + SU: u4 = 0, + /// Second tens in BCD format + ST: u3 = 0, reserved1: u1 = 0, - MNU: u4, // bit offset: 8 desc: Minute units in BCD format - MNT: u3, // bit offset: 12 desc: Minute tens in BCD format + /// Minute units in BCD format + MNU: u4 = 0, + /// Minute tens in BCD format + MNT: u3 = 0, reserved2: u1 = 0, - HU: u4, // bit offset: 16 desc: Hour units in BCD format - HT: u2, // bit offset: 20 desc: Hour tens in BCD format - PM: u1, // bit offset: 22 desc: AM/PM notation + /// Hour units in BCD format + HU: u4 = 0, + /// Hour tens in BCD format + HT: u2 = 0, + /// AM/PM notation + PM: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -14880,15 +21416,21 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 time stamp date register + + /// time stamp date register pub const TSDR = mmio(Address + 0x00000034, 32, packed struct { - DU: u4, // bit offset: 0 desc: Date units in BCD format - DT: u2, // bit offset: 4 desc: Date tens in BCD format + /// Date units in BCD format + DU: u4 = 0, + /// Date tens in BCD format + DT: u2 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MU: u4, // bit offset: 8 desc: Month units in BCD format - MT: u1, // bit offset: 12 desc: Month tens in BCD format - WDU: u3, // bit offset: 13 desc: Week day units + /// Month units in BCD format + MU: u4 = 0, + /// Month tens in BCD format + MT: u1 = 0, + /// Week day units + WDU: u3 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14906,9 +21448,11 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 timestamp sub second register + + /// timestamp sub second register pub const TSSSR = mmio(Address + 0x00000038, 32, packed struct { - SS: u16, // bit offset: 0 desc: Sub second value + /// Sub second value + SS: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14926,16 +21470,21 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 calibration register + + /// calibration register pub const CALR = mmio(Address + 0x0000003c, 32, packed struct { - CALM: u9, // bit offset: 0 desc: Calibration minus + /// Calibration minus + CALM: u9 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CALW16: u1, // bit offset: 13 desc: Use a 16-second calibration cycle period - CALW8: u1, // bit offset: 14 desc: Use an 8-second calibration cycle period - CALP: u1, // bit offset: 15 desc: Increase frequency of RTC by 488.5 ppm + /// Use a 16-second calibration cycle period + CALW16: u1 = 0, + /// Use an 8-second calibration cycle period + CALW8: u1 = 0, + /// Increase frequency of RTC by 488.5 ppm + CALP: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14953,28 +21502,47 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 tamper and alternate function configuration register + + /// tamper and alternate function configuration register pub const TAFCR = mmio(Address + 0x00000040, 32, packed struct { - TAMP1E: u1, // bit offset: 0 desc: Tamper 1 detection enable - TAMP1TRG: u1, // bit offset: 1 desc: Active level for tamper 1 - TAMPIE: u1, // bit offset: 2 desc: Tamper interrupt enable - TAMP2E: u1, // bit offset: 3 desc: Tamper 2 detection enable - TAMP2TRG: u1, // bit offset: 4 desc: Active level for tamper 2 - TAMP3E: u1, // bit offset: 5 desc: Tamper 3 detection enable - TAMP3TRG: u1, // bit offset: 6 desc: Active level for tamper 3 - TAMPTS: u1, // bit offset: 7 desc: Activate timestamp on tamper detection event - TAMPFREQ: u3, // bit offset: 8 desc: Tamper sampling frequency - TAMPFLT: u2, // bit offset: 11 desc: Tamper filter count - TAMPPRCH: u2, // bit offset: 13 desc: Tamper precharge duration - TAMPPUDIS: u1, // bit offset: 15 desc: TAMPER pull-up disable + /// Tamper 1 detection enable + TAMP1E: u1 = 0, + /// Active level for tamper 1 + TAMP1TRG: u1 = 0, + /// Tamper interrupt enable + TAMPIE: u1 = 0, + /// Tamper 2 detection enable + TAMP2E: u1 = 0, + /// Active level for tamper 2 + TAMP2TRG: u1 = 0, + /// Tamper 3 detection enable + TAMP3E: u1 = 0, + /// Active level for tamper 3 + TAMP3TRG: u1 = 0, + /// Activate timestamp on tamper detection event + TAMPTS: u1 = 0, + /// Tamper sampling frequency + TAMPFREQ: u3 = 0, + /// Tamper filter count + TAMPFLT: u2 = 0, + /// Tamper precharge duration + TAMPPRCH: u2 = 0, + /// TAMPER pull-up disable + TAMPPUDIS: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - PC13VALUE: u1, // bit offset: 18 desc: PC13 value - PC13MODE: u1, // bit offset: 19 desc: PC13 mode - PC14VALUE: u1, // bit offset: 20 desc: PC14 value - PC14MODE: u1, // bit offset: 21 desc: PC 14 mode - PC15VALUE: u1, // bit offset: 22 desc: PC15 value - PC15MODE: u1, // bit offset: 23 desc: PC15 mode + /// PC13 value + PC13VALUE: u1 = 0, + /// PC13 mode + PC13MODE: u1 = 0, + /// PC14 value + PC14VALUE: u1 = 0, + /// PC 14 mode + PC14MODE: u1 = 0, + /// PC15 value + PC15VALUE: u1 = 0, + /// PC15 mode + PC15MODE: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -14984,9 +21552,11 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 alarm A sub second register + + /// alarm A sub second register pub const ALRMASSR = mmio(Address + 0x00000044, 32, packed struct { - SS: u15, // bit offset: 0 desc: Sub seconds value + /// Sub seconds value + SS: u15 = 0, reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, @@ -14996,15 +21566,18 @@ pub const RTC = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MASKSS: u4, // bit offset: 24 desc: Mask the most-significant bits starting at this bit + /// Mask the most-significant bits starting at this bit + MASKSS: u4 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 alarm B sub second register + + /// alarm B sub second register pub const ALRMBSSR = mmio(Address + 0x00000048, 32, packed struct { - SS: u15, // bit offset: 0 desc: Sub seconds value + /// Sub seconds value + SS: u15 = 0, reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, @@ -15014,157 +21587,135 @@ pub const RTC = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MASKSS: u4, // bit offset: 24 desc: Mask the most-significant bits starting at this bit + /// Mask the most-significant bits starting at this bit + MASKSS: u4 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 80 backup register - pub const BKP0R = mmio(Address + 0x00000050, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 84 backup register - pub const BKP1R = mmio(Address + 0x00000054, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 88 backup register - pub const BKP2R = mmio(Address + 0x00000058, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 92 backup register - pub const BKP3R = mmio(Address + 0x0000005c, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 96 backup register - pub const BKP4R = mmio(Address + 0x00000060, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 100 backup register - pub const BKP5R = mmio(Address + 0x00000064, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 104 backup register - pub const BKP6R = mmio(Address + 0x00000068, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 108 backup register - pub const BKP7R = mmio(Address + 0x0000006c, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 112 backup register - pub const BKP8R = mmio(Address + 0x00000070, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 116 backup register - pub const BKP9R = mmio(Address + 0x00000074, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 120 backup register - pub const BKP10R = mmio(Address + 0x00000078, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 124 backup register - pub const BKP11R = mmio(Address + 0x0000007c, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 128 backup register - pub const BKP12R = mmio(Address + 0x00000080, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 132 backup register - pub const BKP13R = mmio(Address + 0x00000084, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 136 backup register - pub const BKP14R = mmio(Address + 0x00000088, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 140 backup register - pub const BKP15R = mmio(Address + 0x0000008c, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 144 backup register - pub const BKP16R = mmio(Address + 0x00000090, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 148 backup register - pub const BKP17R = mmio(Address + 0x00000094, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 152 backup register - pub const BKP18R = mmio(Address + 0x00000098, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 156 backup register - pub const BKP19R = mmio(Address + 0x0000009c, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 160 backup register - pub const BKP20R = mmio(Address + 0x000000a0, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 164 backup register - pub const BKP21R = mmio(Address + 0x000000a4, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 168 backup register - pub const BKP22R = mmio(Address + 0x000000a8, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 172 backup register - pub const BKP23R = mmio(Address + 0x000000ac, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 176 backup register - pub const BKP24R = mmio(Address + 0x000000b0, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 180 backup register - pub const BKP25R = mmio(Address + 0x000000b4, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 184 backup register - pub const BKP26R = mmio(Address + 0x000000b8, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 188 backup register - pub const BKP27R = mmio(Address + 0x000000bc, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 192 backup register - pub const BKP28R = mmio(Address + 0x000000c0, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 196 backup register - pub const BKP29R = mmio(Address + 0x000000c4, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 200 backup register - pub const BKP30R = mmio(Address + 0x000000c8, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 204 backup register - pub const BKP31R = mmio(Address + 0x000000cc, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); + + /// backup register + pub const BKP0R = mmio(Address + 0x00000050, 32, packed struct {}); + + /// backup register + pub const BKP1R = mmio(Address + 0x00000054, 32, packed struct {}); + + /// backup register + pub const BKP2R = mmio(Address + 0x00000058, 32, packed struct {}); + + /// backup register + pub const BKP3R = mmio(Address + 0x0000005c, 32, packed struct {}); + + /// backup register + pub const BKP4R = mmio(Address + 0x00000060, 32, packed struct {}); + + /// backup register + pub const BKP5R = mmio(Address + 0x00000064, 32, packed struct {}); + + /// backup register + pub const BKP6R = mmio(Address + 0x00000068, 32, packed struct {}); + + /// backup register + pub const BKP7R = mmio(Address + 0x0000006c, 32, packed struct {}); + + /// backup register + pub const BKP8R = mmio(Address + 0x00000070, 32, packed struct {}); + + /// backup register + pub const BKP9R = mmio(Address + 0x00000074, 32, packed struct {}); + + /// backup register + pub const BKP10R = mmio(Address + 0x00000078, 32, packed struct {}); + + /// backup register + pub const BKP11R = mmio(Address + 0x0000007c, 32, packed struct {}); + + /// backup register + pub const BKP12R = mmio(Address + 0x00000080, 32, packed struct {}); + + /// backup register + pub const BKP13R = mmio(Address + 0x00000084, 32, packed struct {}); + + /// backup register + pub const BKP14R = mmio(Address + 0x00000088, 32, packed struct {}); + + /// backup register + pub const BKP15R = mmio(Address + 0x0000008c, 32, packed struct {}); + + /// backup register + pub const BKP16R = mmio(Address + 0x00000090, 32, packed struct {}); + + /// backup register + pub const BKP17R = mmio(Address + 0x00000094, 32, packed struct {}); + + /// backup register + pub const BKP18R = mmio(Address + 0x00000098, 32, packed struct {}); + + /// backup register + pub const BKP19R = mmio(Address + 0x0000009c, 32, packed struct {}); + + /// backup register + pub const BKP20R = mmio(Address + 0x000000a0, 32, packed struct {}); + + /// backup register + pub const BKP21R = mmio(Address + 0x000000a4, 32, packed struct {}); + + /// backup register + pub const BKP22R = mmio(Address + 0x000000a8, 32, packed struct {}); + + /// backup register + pub const BKP23R = mmio(Address + 0x000000ac, 32, packed struct {}); + + /// backup register + pub const BKP24R = mmio(Address + 0x000000b0, 32, packed struct {}); + + /// backup register + pub const BKP25R = mmio(Address + 0x000000b4, 32, packed struct {}); + + /// backup register + pub const BKP26R = mmio(Address + 0x000000b8, 32, packed struct {}); + + /// backup register + pub const BKP27R = mmio(Address + 0x000000bc, 32, packed struct {}); + + /// backup register + pub const BKP28R = mmio(Address + 0x000000c0, 32, packed struct {}); + + /// backup register + pub const BKP29R = mmio(Address + 0x000000c4, 32, packed struct {}); + + /// backup register + pub const BKP30R = mmio(Address + 0x000000c8, 32, packed struct {}); + + /// backup register + pub const BKP31R = mmio(Address + 0x000000cc, 32, packed struct {}); }; + +/// Basic timers pub const TIM6 = extern struct { pub const Address: u32 = 0x40001000; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + /// Auto-reload preload enable + ARPE: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + /// UIF status bit remapping + UIFREMAP: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -15186,13 +21737,15 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MMS: u3, // bit offset: 4 desc: Master mode selection + /// Master mode selection + MMS: u3 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -15219,9 +21772,11 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable + /// Update interrupt enable + UIE: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -15229,7 +21784,8 @@ pub const TIM6 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UDE: u1, // bit offset: 8 desc: Update DMA request enable + /// Update DMA request enable + UDE: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -15254,9 +21810,11 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag + /// Update interrupt flag + UIF: u1 = 0, padding31: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, @@ -15289,9 +21847,11 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation + /// Update generation + UG: u1 = 0, padding31: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, @@ -15324,9 +21884,11 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: Low counter value + /// Low counter value + CNT: u16 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, @@ -15342,11 +21904,14 @@ pub const TIM6 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UIFCPY: u1, // bit offset: 31 desc: UIF Copy + /// UIF Copy + UIFCPY: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -15364,9 +21929,11 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Low Auto-reload value + /// Low Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -15385,22 +21952,31 @@ pub const TIM6 = extern struct { padding1: u1 = 0, }); }; + +/// Basic timers pub const TIM7 = extern struct { pub const Address: u32 = 0x40001400; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + /// Auto-reload preload enable + ARPE: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + /// UIF status bit remapping + UIFREMAP: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -15422,13 +21998,15 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MMS: u3, // bit offset: 4 desc: Master mode selection + /// Master mode selection + MMS: u3 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -15455,9 +22033,11 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable + /// Update interrupt enable + UIE: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -15465,7 +22045,8 @@ pub const TIM7 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UDE: u1, // bit offset: 8 desc: Update DMA request enable + /// Update DMA request enable + UDE: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -15490,9 +22071,11 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag + /// Update interrupt flag + UIF: u1 = 0, padding31: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, @@ -15525,9 +22108,11 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation + /// Update generation + UG: u1 = 0, padding31: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, @@ -15560,9 +22145,11 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: Low counter value + /// Low counter value + CNT: u16 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, @@ -15578,11 +22165,14 @@ pub const TIM7 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UIFCPY: u1, // bit offset: 31 desc: UIF Copy + /// UIF Copy + UIFCPY: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -15600,9 +22190,11 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Low Auto-reload value + /// Low Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -15621,35 +22213,57 @@ pub const TIM7 = extern struct { padding1: u1 = 0, }); }; + +/// Digital-to-analog converter pub const DAC = extern struct { pub const Address: u32 = 0x40007400; - // byte offset: 0 control register + + /// control register pub const CR = mmio(Address + 0x00000000, 32, packed struct { - EN1: u1, // bit offset: 0 desc: DAC channel1 enable - BOFF1: u1, // bit offset: 1 desc: DAC channel1 output buffer disable - TEN1: u1, // bit offset: 2 desc: DAC channel1 trigger enable - TSEL1: u3, // bit offset: 3 desc: DAC channel1 trigger selection - WAVE1: u2, // bit offset: 6 desc: DAC channel1 noise/triangle wave generation enable - MAMP1: u4, // bit offset: 8 desc: DAC channel1 mask/amplitude selector - DMAEN1: u1, // bit offset: 12 desc: DAC channel1 DMA enable - DMAUDRIE1: u1, // bit offset: 13 desc: DAC channel1 DMA Underrun Interrupt enable - reserved2: u1 = 0, - reserved1: u1 = 0, - EN2: u1, // bit offset: 16 desc: DAC channel2 enable - BOFF2: u1, // bit offset: 17 desc: DAC channel2 output buffer disable - TEN2: u1, // bit offset: 18 desc: DAC channel2 trigger enable - TSEL2: u3, // bit offset: 19 desc: DAC channel2 trigger selection - WAVE2: u2, // bit offset: 22 desc: DAC channel2 noise/triangle wave generation enable - MAMP2: u4, // bit offset: 24 desc: DAC channel2 mask/amplitude selector - DMAEN2: u1, // bit offset: 28 desc: DAC channel2 DMA enable - DMAUDRIE2: u1, // bit offset: 29 desc: DAC channel2 DMA underrun interrupt enable + /// DAC channel1 enable + EN1: u1 = 0, + /// DAC channel1 output buffer disable + BOFF1: u1 = 0, + /// DAC channel1 trigger enable + TEN1: u1 = 0, + /// DAC channel1 trigger selection + TSEL1: u3 = 0, + /// DAC channel1 noise/triangle wave generation enable + WAVE1: u2 = 0, + /// DAC channel1 mask/amplitude selector + MAMP1: u4 = 0, + /// DAC channel1 DMA enable + DMAEN1: u1 = 0, + /// DAC channel1 DMA Underrun Interrupt enable + DMAUDRIE1: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// DAC channel2 enable + EN2: u1 = 0, + /// DAC channel2 output buffer disable + BOFF2: u1 = 0, + /// DAC channel2 trigger enable + TEN2: u1 = 0, + /// DAC channel2 trigger selection + TSEL2: u3 = 0, + /// DAC channel2 noise/triangle wave generation enable + WAVE2: u2 = 0, + /// DAC channel2 mask/amplitude selector + MAMP2: u4 = 0, + /// DAC channel2 DMA enable + DMAEN2: u1 = 0, + /// DAC channel2 DMA underrun interrupt enable + DMAUDRIE2: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 software trigger register + + /// software trigger register pub const SWTRIGR = mmio(Address + 0x00000004, 32, packed struct { - SWTRIG1: u1, // bit offset: 0 desc: DAC channel1 software trigger - SWTRIG2: u1, // bit offset: 1 desc: DAC channel2 software trigger + /// DAC channel1 software trigger + SWTRIG1: u1 = 0, + /// DAC channel2 software trigger + SWTRIG2: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -15681,9 +22295,11 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 channel1 12-bit right-aligned data holding register + + /// channel1 12-bit right-aligned data holding register pub const DHR12R1 = mmio(Address + 0x00000008, 32, packed struct { - DACC1DHR: u12, // bit offset: 0 desc: DAC channel1 12-bit right-aligned data + /// DAC channel1 12-bit right-aligned data + DACC1DHR: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -15705,13 +22321,15 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 channel1 12-bit left aligned data holding register + + /// channel1 12-bit left aligned data holding register pub const DHR12L1 = mmio(Address + 0x0000000c, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DACC1DHR: u12, // bit offset: 4 desc: DAC channel1 12-bit left-aligned data + /// DAC channel1 12-bit left-aligned data + DACC1DHR: u12 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -15729,9 +22347,11 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 channel1 8-bit right aligned data holding register + + /// channel1 8-bit right aligned data holding register pub const DHR8R1 = mmio(Address + 0x00000010, 32, packed struct { - DACC1DHR: u8, // bit offset: 0 desc: DAC channel1 8-bit right-aligned data + /// DAC channel1 8-bit right-aligned data + DACC1DHR: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -15757,9 +22377,11 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 channel2 12-bit right aligned data holding register + + /// channel2 12-bit right aligned data holding register pub const DHR12R2 = mmio(Address + 0x00000014, 32, packed struct { - DACC2DHR: u12, // bit offset: 0 desc: DAC channel2 12-bit right-aligned data + /// DAC channel2 12-bit right-aligned data + DACC2DHR: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -15781,13 +22403,15 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 channel2 12-bit left aligned data holding register + + /// channel2 12-bit left aligned data holding register pub const DHR12L2 = mmio(Address + 0x00000018, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DACC2DHR: u12, // bit offset: 4 desc: DAC channel2 12-bit left-aligned data + /// DAC channel2 12-bit left-aligned data + DACC2DHR: u12 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -15805,9 +22429,11 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 channel2 8-bit right-aligned data holding register + + /// channel2 8-bit right-aligned data holding register pub const DHR8R2 = mmio(Address + 0x0000001c, 32, packed struct { - DACC2DHR: u8, // bit offset: 0 desc: DAC channel2 8-bit right-aligned data + /// DAC channel2 8-bit right-aligned data + DACC2DHR: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -15833,36 +22459,45 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 Dual DAC 12-bit right-aligned data holding register + + /// Dual DAC 12-bit right-aligned data holding register pub const DHR12RD = mmio(Address + 0x00000020, 32, packed struct { - DACC1DHR: u12, // bit offset: 0 desc: DAC channel1 12-bit right-aligned data + /// DAC channel1 12-bit right-aligned data + DACC1DHR: u12 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DACC2DHR: u12, // bit offset: 16 desc: DAC channel2 12-bit right-aligned data + /// DAC channel2 12-bit right-aligned data + DACC2DHR: u12 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 DUAL DAC 12-bit left aligned data holding register + + /// DUAL DAC 12-bit left aligned data holding register pub const DHR12LD = mmio(Address + 0x00000024, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DACC1DHR: u12, // bit offset: 4 desc: DAC channel1 12-bit left-aligned data + /// DAC channel1 12-bit left-aligned data + DACC1DHR: u12 = 0, reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - DACC2DHR: u12, // bit offset: 20 desc: DAC channel2 12-bit left-aligned data + /// DAC channel2 12-bit left-aligned data + DACC2DHR: u12 = 0, }); - // byte offset: 40 DUAL DAC 8-bit right aligned data holding register + + /// DUAL DAC 8-bit right aligned data holding register pub const DHR8RD = mmio(Address + 0x00000028, 32, packed struct { - DACC1DHR: u8, // bit offset: 0 desc: DAC channel1 8-bit right-aligned data - DACC2DHR: u8, // bit offset: 8 desc: DAC channel2 8-bit right-aligned data + /// DAC channel1 8-bit right-aligned data + DACC1DHR: u8 = 0, + /// DAC channel2 8-bit right-aligned data + DACC2DHR: u8 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -15880,9 +22515,11 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 channel1 data output register + + /// channel1 data output register pub const DOR1 = mmio(Address + 0x0000002c, 32, packed struct { - DACC1DOR: u12, // bit offset: 0 desc: DAC channel1 data output + /// DAC channel1 data output + DACC1DOR: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -15904,9 +22541,11 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 channel2 data output register + + /// channel2 data output register pub const DOR2 = mmio(Address + 0x00000030, 32, packed struct { - DACC2DOR: u12, // bit offset: 0 desc: DAC channel2 data output + /// DAC channel2 data output + DACC2DOR: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -15928,7 +22567,8 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 status register + + /// status register pub const SR = mmio(Address + 0x00000034, 32, packed struct { reserved13: u1 = 0, reserved12: u1 = 0, @@ -15943,7 +22583,8 @@ pub const DAC = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DMAUDR1: u1, // bit offset: 13 desc: DAC channel1 DMA underrun flag + /// DAC channel1 DMA underrun flag + DMAUDR1: u1 = 0, reserved28: u1 = 0, reserved27: u1 = 0, reserved26: u1 = 0, @@ -15959,31 +22600,43 @@ pub const DAC = extern struct { reserved16: u1 = 0, reserved15: u1 = 0, reserved14: u1 = 0, - DMAUDR2: u1, // bit offset: 29 desc: DAC channel2 DMA underrun flag + /// DAC channel2 DMA underrun flag + DMAUDR2: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); }; + +/// Debug support pub const DBGMCU = extern struct { pub const Address: u32 = 0xe0042000; - // byte offset: 0 MCU Device ID Code Register + + /// MCU Device ID Code Register pub const IDCODE = mmio(Address + 0x00000000, 32, packed struct { - DEV_ID: u12, // bit offset: 0 desc: Device Identifier + /// Device Identifier + DEV_ID: u12 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - REV_ID: u16, // bit offset: 16 desc: Revision Identifier + /// Revision Identifier + REV_ID: u16 = 0, }); - // byte offset: 4 Debug MCU Configuration Register + + /// Debug MCU Configuration Register pub const CR = mmio(Address + 0x00000004, 32, packed struct { - DBG_SLEEP: u1, // bit offset: 0 desc: Debug Sleep mode - DBG_STOP: u1, // bit offset: 1 desc: Debug Stop Mode - DBG_STANDBY: u1, // bit offset: 2 desc: Debug Standby Mode - reserved2: u1 = 0, - reserved1: u1 = 0, - TRACE_IOEN: u1, // bit offset: 5 desc: Trace pin assignment control - TRACE_MODE: u2, // bit offset: 6 desc: Trace pin assignment control + /// Debug Sleep mode + DBG_SLEEP: u1 = 0, + /// Debug Stop Mode + DBG_STOP: u1 = 0, + /// Debug Standby Mode + DBG_STANDBY: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Trace pin assignment control + TRACE_IOEN: u1 = 0, + /// Trace pin assignment control + TRACE_MODE: u2 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -16009,21 +22662,35 @@ pub const DBGMCU = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 APB Low Freeze Register + + /// APB Low Freeze Register pub const APB1FZ = mmio(Address + 0x00000008, 32, packed struct { - DBG_TIM2_STOP: u1, // bit offset: 0 desc: Debug Timer 2 stopped when Core is halted - DBG_TIM3_STOP: u1, // bit offset: 1 desc: Debug Timer 3 stopped when Core is halted - DBG_TIM4_STOP: u1, // bit offset: 2 desc: Debug Timer 4 stopped when Core is halted - DBG_TIM5_STOP: u1, // bit offset: 3 desc: Debug Timer 5 stopped when Core is halted - DBG_TIM6_STOP: u1, // bit offset: 4 desc: Debug Timer 6 stopped when Core is halted - DBG_TIM7_STOP: u1, // bit offset: 5 desc: Debug Timer 7 stopped when Core is halted - DBG_TIM12_STOP: u1, // bit offset: 6 desc: Debug Timer 12 stopped when Core is halted - DBG_TIM13_STOP: u1, // bit offset: 7 desc: Debug Timer 13 stopped when Core is halted - DBG_TIMER14_STOP: u1, // bit offset: 8 desc: Debug Timer 14 stopped when Core is halted - DBG_TIM18_STOP: u1, // bit offset: 9 desc: Debug Timer 18 stopped when Core is halted - DBG_RTC_STOP: u1, // bit offset: 10 desc: Debug RTC stopped when Core is halted - DBG_WWDG_STOP: u1, // bit offset: 11 desc: Debug Window Wachdog stopped when Core is halted - DBG_IWDG_STOP: u1, // bit offset: 12 desc: Debug Independent Wachdog stopped when Core is halted + /// Debug Timer 2 stopped when Core is halted + DBG_TIM2_STOP: u1 = 0, + /// Debug Timer 3 stopped when Core is halted + DBG_TIM3_STOP: u1 = 0, + /// Debug Timer 4 stopped when Core is halted + DBG_TIM4_STOP: u1 = 0, + /// Debug Timer 5 stopped when Core is halted + DBG_TIM5_STOP: u1 = 0, + /// Debug Timer 6 stopped when Core is halted + DBG_TIM6_STOP: u1 = 0, + /// Debug Timer 7 stopped when Core is halted + DBG_TIM7_STOP: u1 = 0, + /// Debug Timer 12 stopped when Core is halted + DBG_TIM12_STOP: u1 = 0, + /// Debug Timer 13 stopped when Core is halted + DBG_TIM13_STOP: u1 = 0, + /// Debug Timer 14 stopped when Core is halted + DBG_TIMER14_STOP: u1 = 0, + /// Debug Timer 18 stopped when Core is halted + DBG_TIM18_STOP: u1 = 0, + /// Debug RTC stopped when Core is halted + DBG_RTC_STOP: u1 = 0, + /// Debug Window Wachdog stopped when Core is halted + DBG_WWDG_STOP: u1 = 0, + /// Debug Independent Wachdog stopped when Core is halted + DBG_IWDG_STOP: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -16032,11 +22699,14 @@ pub const DBGMCU = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - I2C1_SMBUS_TIMEOUT: u1, // bit offset: 21 desc: SMBUS timeout mode stopped when Core is halted - I2C2_SMBUS_TIMEOUT: u1, // bit offset: 22 desc: SMBUS timeout mode stopped when Core is halted + /// SMBUS timeout mode stopped when Core is halted + I2C1_SMBUS_TIMEOUT: u1 = 0, + /// SMBUS timeout mode stopped when Core is halted + I2C2_SMBUS_TIMEOUT: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, - DBG_CAN_STOP: u1, // bit offset: 25 desc: Debug CAN stopped when core is halted + /// Debug CAN stopped when core is halted + DBG_CAN_STOP: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, @@ -16044,14 +22714,19 @@ pub const DBGMCU = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 APB High Freeze Register + + /// APB High Freeze Register pub const APB2FZ = mmio(Address + 0x0000000c, 32, packed struct { reserved2: u1 = 0, reserved1: u1 = 0, - DBG_TIM15_STOP: u1, // bit offset: 2 desc: Debug Timer 15 stopped when Core is halted - DBG_TIM16_STOP: u1, // bit offset: 3 desc: Debug Timer 16 stopped when Core is halted - DBG_TIM17_STO: u1, // bit offset: 4 desc: Debug Timer 17 stopped when Core is halted - DBG_TIM19_STOP: u1, // bit offset: 5 desc: Debug Timer 19 stopped when Core is halted + /// Debug Timer 15 stopped when Core is halted + DBG_TIM15_STOP: u1 = 0, + /// Debug Timer 16 stopped when Core is halted + DBG_TIM16_STOP: u1 = 0, + /// Debug Timer 17 stopped when Core is halted + DBG_TIM17_STO: u1 = 0, + /// Debug Timer 19 stopped when Core is halted + DBG_TIM19_STOP: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -16080,20 +22755,32 @@ pub const DBGMCU = extern struct { padding1: u1 = 0, }); }; + +/// Advanced timer pub const TIM1 = extern struct { pub const Address: u32 = 0x40012c00; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode - DIR: u1, // bit offset: 4 desc: Direction - CMS: u2, // bit offset: 5 desc: Center-aligned mode selection - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division - reserved1: u1 = 0, - UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, + /// Direction + DIR: u1 = 0, + /// Center-aligned mode selection + CMS: u2 = 0, + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, + reserved1: u1 = 0, + /// UIF status bit remapping + UIFREMAP: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -16115,27 +22802,43 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - CCPC: u1, // bit offset: 0 desc: Capture/compare preloaded control - reserved1: u1 = 0, - CCUS: u1, // bit offset: 2 desc: Capture/compare control update selection - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection - MMS: u3, // bit offset: 4 desc: Master mode selection - TI1S: u1, // bit offset: 7 desc: TI1 selection - OIS1: u1, // bit offset: 8 desc: Output Idle state 1 - OIS1N: u1, // bit offset: 9 desc: Output Idle state 1 - OIS2: u1, // bit offset: 10 desc: Output Idle state 2 - OIS2N: u1, // bit offset: 11 desc: Output Idle state 2 - OIS3: u1, // bit offset: 12 desc: Output Idle state 3 - OIS3N: u1, // bit offset: 13 desc: Output Idle state 3 - OIS4: u1, // bit offset: 14 desc: Output Idle state 4 - reserved2: u1 = 0, - OIS5: u1, // bit offset: 16 desc: Output Idle state 5 + /// Capture/compare preloaded control + CCPC: u1 = 0, + reserved1: u1 = 0, + /// Capture/compare control update selection + CCUS: u1 = 0, + /// Capture/compare DMA selection + CCDS: u1 = 0, + /// Master mode selection + MMS: u3 = 0, + /// TI1 selection + TI1S: u1 = 0, + /// Output Idle state 1 + OIS1: u1 = 0, + /// Output Idle state 1 + OIS1N: u1 = 0, + /// Output Idle state 2 + OIS2: u1 = 0, + /// Output Idle state 2 + OIS2N: u1 = 0, + /// Output Idle state 3 + OIS3: u1 = 0, + /// Output Idle state 3 + OIS3N: u1 = 0, + /// Output Idle state 4 + OIS4: u1 = 0, + reserved2: u1 = 0, + /// Output Idle state 5 + OIS5: u1 = 0, reserved3: u1 = 0, - OIS6: u1, // bit offset: 18 desc: Output Idle state 6 + /// Output Idle state 6 + OIS6: u1 = 0, reserved4: u1 = 0, - MMS2: u4, // bit offset: 20 desc: Master mode selection 2 + /// Master mode selection 2 + MMS2: u4 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -16145,17 +22848,27 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection - OCCS: u1, // bit offset: 3 desc: OCREF clear selection - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode - ETF: u4, // bit offset: 8 desc: External trigger filter - ETPS: u2, // bit offset: 12 desc: External trigger prescaler - ECE: u1, // bit offset: 14 desc: External clock enable - ETP: u1, // bit offset: 15 desc: External trigger polarity - SMS3: u1, // bit offset: 16 desc: Slave mode selection bit 3 + /// Slave mode selection + SMS: u3 = 0, + /// OCREF clear selection + OCCS: u1 = 0, + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, + /// External trigger filter + ETF: u4 = 0, + /// External trigger prescaler + ETPS: u2 = 0, + /// External clock enable + ECE: u1 = 0, + /// External trigger polarity + ETP: u1 = 0, + /// Slave mode selection bit 3 + SMS3: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -16172,23 +22885,39 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable - CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable - CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable - COMIE: u1, // bit offset: 5 desc: COM interrupt enable - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable - BIE: u1, // bit offset: 7 desc: Break interrupt enable - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable - CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable - CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable - CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable - COMDE: u1, // bit offset: 13 desc: COM DMA request enable - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, + /// Capture/Compare 3 interrupt enable + CC3IE: u1 = 0, + /// Capture/Compare 4 interrupt enable + CC4IE: u1 = 0, + /// COM interrupt enable + COMIE: u1 = 0, + /// Trigger interrupt enable + TIE: u1 = 0, + /// Break interrupt enable + BIE: u1 = 0, + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, + /// Capture/Compare 2 DMA request enable + CC2DE: u1 = 0, + /// Capture/Compare 3 DMA request enable + CC3DE: u1 = 0, + /// Capture/Compare 4 DMA request enable + CC4DE: u1 = 0, + /// COM DMA request enable + COMDE: u1 = 0, + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -16207,26 +22936,42 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag - CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag - CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag - COMIF: u1, // bit offset: 5 desc: COM interrupt flag - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag - BIF: u1, // bit offset: 7 desc: Break interrupt flag - B2IF: u1, // bit offset: 8 desc: Break 2 interrupt flag - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag - CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag - CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, + /// Capture/Compare 3 interrupt flag + CC3IF: u1 = 0, + /// Capture/Compare 4 interrupt flag + CC4IF: u1 = 0, + /// COM interrupt flag + COMIF: u1 = 0, + /// Trigger interrupt flag + TIF: u1 = 0, + /// Break interrupt flag + BIF: u1 = 0, + /// Break 2 interrupt flag + B2IF: u1 = 0, + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, + /// Capture/Compare 3 overcapture flag + CC3OF: u1 = 0, + /// Capture/Compare 4 overcapture flag + CC4OF: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - C5IF: u1, // bit offset: 16 desc: Capture/Compare 5 interrupt flag - C6IF: u1, // bit offset: 17 desc: Capture/Compare 6 interrupt flag + /// Capture/Compare 5 interrupt flag + C5IF: u1 = 0, + /// Capture/Compare 6 interrupt flag + C6IF: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, @@ -16242,17 +22987,27 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation - CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation - CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation - COMG: u1, // bit offset: 5 desc: Capture/Compare control update generation - TG: u1, // bit offset: 6 desc: Trigger generation - BG: u1, // bit offset: 7 desc: Break generation - B2G: u1, // bit offset: 8 desc: Break 2 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, + /// Capture/compare 3 generation + CC3G: u1 = 0, + /// Capture/compare 4 generation + CC4G: u1 = 0, + /// Capture/Compare control update generation + COMG: u1 = 0, + /// Trigger generation + TG: u1 = 0, + /// Break generation + BG: u1 = 0, + /// Break 2 generation + B2G: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -16277,19 +23032,31 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode - OC1CE: u1, // bit offset: 7 desc: Output Compare 1 clear enable - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output Compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output Compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output Compare 2 mode - OC2CE: u1, // bit offset: 15 desc: Output Compare 2 clear enable - OC1M_3: u1, // bit offset: 16 desc: Output Compare 1 mode bit 3 + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output Compare 1 fast enable + OC1FE: u1 = 0, + /// Output Compare 1 preload enable + OC1PE: u1 = 0, + /// Output Compare 1 mode + OC1M: u3 = 0, + /// Output Compare 1 clear enable + OC1CE: u1 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output Compare 2 fast enable + OC2FE: u1 = 0, + /// Output Compare 2 preload enable + OC2PE: u1 = 0, + /// Output Compare 2 mode + OC2M: u3 = 0, + /// Output Compare 2 clear enable + OC2CE: u1 = 0, + /// Output Compare 1 mode bit 3 + OC1M_3: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -16297,7 +23064,8 @@ pub const TIM1 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC2M_3: u1, // bit offset: 24 desc: Output Compare 2 mode bit 3 + /// Output Compare 2 mode bit 3 + OC2M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -16306,14 +23074,21 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PCS: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - IC2PCS: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PCS: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PCS: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16331,19 +23106,31 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable - OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable - OC3M: u3, // bit offset: 4 desc: Output compare 3 mode - OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable - OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable - OC4M: u3, // bit offset: 12 desc: Output compare 4 mode - OC4CE: u1, // bit offset: 15 desc: Output compare 4 clear enable - OC3M_3: u1, // bit offset: 16 desc: Output Compare 3 mode bit 3 + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Output compare 3 fast enable + OC3FE: u1 = 0, + /// Output compare 3 preload enable + OC3PE: u1 = 0, + /// Output compare 3 mode + OC3M: u3 = 0, + /// Output compare 3 clear enable + OC3CE: u1 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Output compare 4 fast enable + OC4FE: u1 = 0, + /// Output compare 4 preload enable + OC4PE: u1 = 0, + /// Output compare 4 mode + OC4M: u3 = 0, + /// Output compare 4 clear enable + OC4CE: u1 = 0, + /// Output Compare 3 mode bit 3 + OC3M_3: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -16351,7 +23138,8 @@ pub const TIM1 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC4M_3: u1, // bit offset: 24 desc: Output Compare 4 mode bit 3 + /// Output Compare 4 mode bit 3 + OC4M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -16360,14 +23148,21 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (input mode) + + /// capture/compare mode register 2 (input mode) pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/compare 3 selection - IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler - IC3F: u4, // bit offset: 4 desc: Input capture 3 filter - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler - IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + /// Capture/compare 3 selection + CC3S: u2 = 0, + /// Input capture 3 prescaler + IC3PSC: u2 = 0, + /// Input capture 3 filter + IC3F: u4 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Input capture 4 prescaler + IC4PSC: u2 = 0, + /// Input capture 4 filter + IC4F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16385,30 +23180,50 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity - CC1NE: u1, // bit offset: 2 desc: Capture/Compare 1 complementary output enable - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity - CC2NE: u1, // bit offset: 6 desc: Capture/Compare 2 complementary output enable - CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity - CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable - CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity - CC3NE: u1, // bit offset: 10 desc: Capture/Compare 3 complementary output enable - CC3NP: u1, // bit offset: 11 desc: Capture/Compare 3 output Polarity - CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable - CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity - reserved1: u1 = 0, - CC4NP: u1, // bit offset: 15 desc: Capture/Compare 4 output Polarity - CC5E: u1, // bit offset: 16 desc: Capture/Compare 5 output enable - CC5P: u1, // bit offset: 17 desc: Capture/Compare 5 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, + /// Capture/Compare 1 complementary output enable + CC1NE: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, + /// Capture/Compare 2 complementary output enable + CC2NE: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2NP: u1 = 0, + /// Capture/Compare 3 output enable + CC3E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3P: u1 = 0, + /// Capture/Compare 3 complementary output enable + CC3NE: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3NP: u1 = 0, + /// Capture/Compare 4 output enable + CC4E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC4P: u1 = 0, + reserved1: u1 = 0, + /// Capture/Compare 4 output Polarity + CC4NP: u1 = 0, + /// Capture/Compare 5 output enable + CC5E: u1 = 0, + /// Capture/Compare 5 output Polarity + CC5P: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CC6E: u1, // bit offset: 20 desc: Capture/Compare 6 output enable - CC6P: u1, // bit offset: 21 desc: Capture/Compare 6 output Polarity + /// Capture/Compare 6 output enable + CC6E: u1 = 0, + /// Capture/Compare 6 output Polarity + CC6P: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, @@ -16420,9 +23235,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, @@ -16438,11 +23255,14 @@ pub const TIM1 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UIFCPY: u1, // bit offset: 31 desc: UIF copy + /// UIF copy + UIFCPY: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16460,9 +23280,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16480,9 +23302,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 repetition counter register + + /// repetition counter register pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - REP: u16, // bit offset: 0 desc: Repetition counter value + /// Repetition counter value + REP: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16500,9 +23324,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16520,9 +23346,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + /// Capture/Compare 2 value + CCR2: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16540,9 +23368,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 capture/compare register 3 + + /// capture/compare register 3 pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - CCR3: u16, // bit offset: 0 desc: Capture/Compare 3 value + /// Capture/Compare 3 value + CCR3: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16560,9 +23390,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 capture/compare register 4 + + /// capture/compare register 4 pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - CCR4: u16, // bit offset: 0 desc: Capture/Compare 3 value + /// Capture/Compare 3 value + CCR4: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16580,20 +23412,33 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 break and dead-time register + + /// break and dead-time register pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - DTG: u8, // bit offset: 0 desc: Dead-time generator setup - LOCK: u2, // bit offset: 8 desc: Lock configuration - OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode - OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode - BKE: u1, // bit offset: 12 desc: Break enable - BKP: u1, // bit offset: 13 desc: Break polarity - AOE: u1, // bit offset: 14 desc: Automatic output enable - MOE: u1, // bit offset: 15 desc: Main output enable - BKF: u4, // bit offset: 16 desc: Break filter - BK2F: u4, // bit offset: 20 desc: Break 2 filter - BK2E: u1, // bit offset: 24 desc: Break 2 enable - BK2P: u1, // bit offset: 25 desc: Break 2 polarity + /// Dead-time generator setup + DTG: u8 = 0, + /// Lock configuration + LOCK: u2 = 0, + /// Off-state selection for Idle mode + OSSI: u1 = 0, + /// Off-state selection for Run mode + OSSR: u1 = 0, + /// Break enable + BKE: u1 = 0, + /// Break polarity + BKP: u1 = 0, + /// Automatic output enable + AOE: u1 = 0, + /// Main output enable + MOE: u1 = 0, + /// Break filter + BKF: u4 = 0, + /// Break 2 filter + BK2F: u4 = 0, + /// Break 2 enable + BK2E: u1 = 0, + /// Break 2 polarity + BK2P: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, @@ -16601,13 +23446,16 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -16628,9 +23476,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16648,21 +23498,31 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 84 capture/compare mode register 3 (output mode) + + /// capture/compare mode register 3 (output mode) pub const CCMR3_Output = mmio(Address + 0x00000054, 32, packed struct { reserved2: u1 = 0, reserved1: u1 = 0, - OC5FE: u1, // bit offset: 2 desc: Output compare 5 fast enable - OC5PE: u1, // bit offset: 3 desc: Output compare 5 preload enable - OC5M: u3, // bit offset: 4 desc: Output compare 5 mode - OC5CE: u1, // bit offset: 7 desc: Output compare 5 clear enable + /// Output compare 5 fast enable + OC5FE: u1 = 0, + /// Output compare 5 preload enable + OC5PE: u1 = 0, + /// Output compare 5 mode + OC5M: u3 = 0, + /// Output compare 5 clear enable + OC5CE: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - OC6FE: u1, // bit offset: 10 desc: Output compare 6 fast enable - OC6PE: u1, // bit offset: 11 desc: Output compare 6 preload enable - OC6M: u3, // bit offset: 12 desc: Output compare 6 mode - OC6CE: u1, // bit offset: 15 desc: Output compare 6 clear enable - OC5M_3: u1, // bit offset: 16 desc: Outout Compare 5 mode bit 3 + /// Output compare 6 fast enable + OC6FE: u1 = 0, + /// Output compare 6 preload enable + OC6PE: u1 = 0, + /// Output compare 6 mode + OC6M: u3 = 0, + /// Output compare 6 clear enable + OC6CE: u1 = 0, + /// Outout Compare 5 mode bit 3 + OC5M_3: u1 = 0, reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -16670,7 +23530,8 @@ pub const TIM1 = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - OC6M_3: u1, // bit offset: 24 desc: Outout Compare 6 mode bit 3 + /// Outout Compare 6 mode bit 3 + OC6M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -16679,9 +23540,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 88 capture/compare register 5 + + /// capture/compare register 5 pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - CCR5: u16, // bit offset: 0 desc: Capture/Compare 5 value + /// Capture/Compare 5 value + CCR5: u16 = 0, reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, @@ -16695,13 +23558,18 @@ pub const TIM1 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - GC5C1: u1, // bit offset: 29 desc: Group Channel 5 and Channel 1 - GC5C2: u1, // bit offset: 30 desc: Group Channel 5 and Channel 2 - GC5C3: u1, // bit offset: 31 desc: Group Channel 5 and Channel 3 + /// Group Channel 5 and Channel 1 + GC5C1: u1 = 0, + /// Group Channel 5 and Channel 2 + GC5C2: u1 = 0, + /// Group Channel 5 and Channel 3 + GC5C3: u1 = 0, }); - // byte offset: 92 capture/compare register 6 + + /// capture/compare register 6 pub const CCR6 = mmio(Address + 0x0000005c, 32, packed struct { - CCR6: u16, // bit offset: 0 desc: Capture/Compare 6 value + /// Capture/Compare 6 value + CCR6: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16719,10 +23587,13 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 96 option registers + + /// option registers pub const OR = mmio(Address + 0x00000060, 32, packed struct { - TIM1_ETR_ADC1_RMP: u2, // bit offset: 0 desc: TIM1_ETR_ADC1 remapping capability - TIM1_ETR_ADC4_RMP: u2, // bit offset: 2 desc: TIM1_ETR_ADC4 remapping capability + /// TIM1_ETR_ADC1 remapping capability + TIM1_ETR_ADC1_RMP: u2 = 0, + /// TIM1_ETR_ADC4 remapping capability + TIM1_ETR_ADC4_RMP: u2 = 0, padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -16753,20 +23624,32 @@ pub const TIM1 = extern struct { padding1: u1 = 0, }); }; + +/// Advanced timer pub const TIM20 = extern struct { pub const Address: u32 = 0x40015000; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode - DIR: u1, // bit offset: 4 desc: Direction - CMS: u2, // bit offset: 5 desc: Center-aligned mode selection - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division - reserved1: u1 = 0, - UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, + /// Direction + DIR: u1 = 0, + /// Center-aligned mode selection + CMS: u2 = 0, + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, + reserved1: u1 = 0, + /// UIF status bit remapping + UIFREMAP: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -16788,27 +23671,43 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - CCPC: u1, // bit offset: 0 desc: Capture/compare preloaded control - reserved1: u1 = 0, - CCUS: u1, // bit offset: 2 desc: Capture/compare control update selection - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection - MMS: u3, // bit offset: 4 desc: Master mode selection - TI1S: u1, // bit offset: 7 desc: TI1 selection - OIS1: u1, // bit offset: 8 desc: Output Idle state 1 - OIS1N: u1, // bit offset: 9 desc: Output Idle state 1 - OIS2: u1, // bit offset: 10 desc: Output Idle state 2 - OIS2N: u1, // bit offset: 11 desc: Output Idle state 2 - OIS3: u1, // bit offset: 12 desc: Output Idle state 3 - OIS3N: u1, // bit offset: 13 desc: Output Idle state 3 - OIS4: u1, // bit offset: 14 desc: Output Idle state 4 - reserved2: u1 = 0, - OIS5: u1, // bit offset: 16 desc: Output Idle state 5 + /// Capture/compare preloaded control + CCPC: u1 = 0, + reserved1: u1 = 0, + /// Capture/compare control update selection + CCUS: u1 = 0, + /// Capture/compare DMA selection + CCDS: u1 = 0, + /// Master mode selection + MMS: u3 = 0, + /// TI1 selection + TI1S: u1 = 0, + /// Output Idle state 1 + OIS1: u1 = 0, + /// Output Idle state 1 + OIS1N: u1 = 0, + /// Output Idle state 2 + OIS2: u1 = 0, + /// Output Idle state 2 + OIS2N: u1 = 0, + /// Output Idle state 3 + OIS3: u1 = 0, + /// Output Idle state 3 + OIS3N: u1 = 0, + /// Output Idle state 4 + OIS4: u1 = 0, + reserved2: u1 = 0, + /// Output Idle state 5 + OIS5: u1 = 0, reserved3: u1 = 0, - OIS6: u1, // bit offset: 18 desc: Output Idle state 6 + /// Output Idle state 6 + OIS6: u1 = 0, reserved4: u1 = 0, - MMS2: u4, // bit offset: 20 desc: Master mode selection 2 + /// Master mode selection 2 + MMS2: u4 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -16818,17 +23717,27 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection - OCCS: u1, // bit offset: 3 desc: OCREF clear selection - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode - ETF: u4, // bit offset: 8 desc: External trigger filter - ETPS: u2, // bit offset: 12 desc: External trigger prescaler - ECE: u1, // bit offset: 14 desc: External clock enable - ETP: u1, // bit offset: 15 desc: External trigger polarity - SMS3: u1, // bit offset: 16 desc: Slave mode selection bit 3 + /// Slave mode selection + SMS: u3 = 0, + /// OCREF clear selection + OCCS: u1 = 0, + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, + /// External trigger filter + ETF: u4 = 0, + /// External trigger prescaler + ETPS: u2 = 0, + /// External clock enable + ECE: u1 = 0, + /// External trigger polarity + ETP: u1 = 0, + /// Slave mode selection bit 3 + SMS3: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -16845,23 +23754,39 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable - CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable - CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable - COMIE: u1, // bit offset: 5 desc: COM interrupt enable - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable - BIE: u1, // bit offset: 7 desc: Break interrupt enable - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable - CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable - CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable - CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable - COMDE: u1, // bit offset: 13 desc: COM DMA request enable - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, + /// Capture/Compare 3 interrupt enable + CC3IE: u1 = 0, + /// Capture/Compare 4 interrupt enable + CC4IE: u1 = 0, + /// COM interrupt enable + COMIE: u1 = 0, + /// Trigger interrupt enable + TIE: u1 = 0, + /// Break interrupt enable + BIE: u1 = 0, + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, + /// Capture/Compare 2 DMA request enable + CC2DE: u1 = 0, + /// Capture/Compare 3 DMA request enable + CC3DE: u1 = 0, + /// Capture/Compare 4 DMA request enable + CC4DE: u1 = 0, + /// COM DMA request enable + COMDE: u1 = 0, + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -16880,26 +23805,42 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag - CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag - CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag - COMIF: u1, // bit offset: 5 desc: COM interrupt flag - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag - BIF: u1, // bit offset: 7 desc: Break interrupt flag - B2IF: u1, // bit offset: 8 desc: Break 2 interrupt flag - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag - CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag - CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, + /// Capture/Compare 3 interrupt flag + CC3IF: u1 = 0, + /// Capture/Compare 4 interrupt flag + CC4IF: u1 = 0, + /// COM interrupt flag + COMIF: u1 = 0, + /// Trigger interrupt flag + TIF: u1 = 0, + /// Break interrupt flag + BIF: u1 = 0, + /// Break 2 interrupt flag + B2IF: u1 = 0, + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, + /// Capture/Compare 3 overcapture flag + CC3OF: u1 = 0, + /// Capture/Compare 4 overcapture flag + CC4OF: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - C5IF: u1, // bit offset: 16 desc: Capture/Compare 5 interrupt flag - C6IF: u1, // bit offset: 17 desc: Capture/Compare 6 interrupt flag + /// Capture/Compare 5 interrupt flag + C5IF: u1 = 0, + /// Capture/Compare 6 interrupt flag + C6IF: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, @@ -16915,17 +23856,27 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation - CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation - CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation - COMG: u1, // bit offset: 5 desc: Capture/Compare control update generation - TG: u1, // bit offset: 6 desc: Trigger generation - BG: u1, // bit offset: 7 desc: Break generation - B2G: u1, // bit offset: 8 desc: Break 2 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, + /// Capture/compare 3 generation + CC3G: u1 = 0, + /// Capture/compare 4 generation + CC4G: u1 = 0, + /// Capture/Compare control update generation + COMG: u1 = 0, + /// Trigger generation + TG: u1 = 0, + /// Break generation + BG: u1 = 0, + /// Break 2 generation + B2G: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -16950,19 +23901,31 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode - OC1CE: u1, // bit offset: 7 desc: Output Compare 1 clear enable - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output Compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output Compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output Compare 2 mode - OC2CE: u1, // bit offset: 15 desc: Output Compare 2 clear enable - OC1M_3: u1, // bit offset: 16 desc: Output Compare 1 mode bit 3 + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output Compare 1 fast enable + OC1FE: u1 = 0, + /// Output Compare 1 preload enable + OC1PE: u1 = 0, + /// Output Compare 1 mode + OC1M: u3 = 0, + /// Output Compare 1 clear enable + OC1CE: u1 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output Compare 2 fast enable + OC2FE: u1 = 0, + /// Output Compare 2 preload enable + OC2PE: u1 = 0, + /// Output Compare 2 mode + OC2M: u3 = 0, + /// Output Compare 2 clear enable + OC2CE: u1 = 0, + /// Output Compare 1 mode bit 3 + OC1M_3: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -16970,7 +23933,8 @@ pub const TIM20 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC2M_3: u1, // bit offset: 24 desc: Output Compare 2 mode bit 3 + /// Output Compare 2 mode bit 3 + OC2M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -16979,14 +23943,21 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PCS: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - IC2PCS: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PCS: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PCS: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17004,19 +23975,31 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable - OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable - OC3M: u3, // bit offset: 4 desc: Output compare 3 mode - OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable - OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable - OC4M: u3, // bit offset: 12 desc: Output compare 4 mode - OC4CE: u1, // bit offset: 15 desc: Output compare 4 clear enable - OC3M_3: u1, // bit offset: 16 desc: Output Compare 3 mode bit 3 + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Output compare 3 fast enable + OC3FE: u1 = 0, + /// Output compare 3 preload enable + OC3PE: u1 = 0, + /// Output compare 3 mode + OC3M: u3 = 0, + /// Output compare 3 clear enable + OC3CE: u1 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Output compare 4 fast enable + OC4FE: u1 = 0, + /// Output compare 4 preload enable + OC4PE: u1 = 0, + /// Output compare 4 mode + OC4M: u3 = 0, + /// Output compare 4 clear enable + OC4CE: u1 = 0, + /// Output Compare 3 mode bit 3 + OC3M_3: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -17024,7 +24007,8 @@ pub const TIM20 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC4M_3: u1, // bit offset: 24 desc: Output Compare 4 mode bit 3 + /// Output Compare 4 mode bit 3 + OC4M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -17033,14 +24017,21 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (input mode) + + /// capture/compare mode register 2 (input mode) pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/compare 3 selection - IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler - IC3F: u4, // bit offset: 4 desc: Input capture 3 filter - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler - IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + /// Capture/compare 3 selection + CC3S: u2 = 0, + /// Input capture 3 prescaler + IC3PSC: u2 = 0, + /// Input capture 3 filter + IC3F: u4 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Input capture 4 prescaler + IC4PSC: u2 = 0, + /// Input capture 4 filter + IC4F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17058,30 +24049,50 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity - CC1NE: u1, // bit offset: 2 desc: Capture/Compare 1 complementary output enable - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity - CC2NE: u1, // bit offset: 6 desc: Capture/Compare 2 complementary output enable - CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity - CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable - CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity - CC3NE: u1, // bit offset: 10 desc: Capture/Compare 3 complementary output enable - CC3NP: u1, // bit offset: 11 desc: Capture/Compare 3 output Polarity - CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable - CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity - reserved1: u1 = 0, - CC4NP: u1, // bit offset: 15 desc: Capture/Compare 4 output Polarity - CC5E: u1, // bit offset: 16 desc: Capture/Compare 5 output enable - CC5P: u1, // bit offset: 17 desc: Capture/Compare 5 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, + /// Capture/Compare 1 complementary output enable + CC1NE: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, + /// Capture/Compare 2 complementary output enable + CC2NE: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2NP: u1 = 0, + /// Capture/Compare 3 output enable + CC3E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3P: u1 = 0, + /// Capture/Compare 3 complementary output enable + CC3NE: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3NP: u1 = 0, + /// Capture/Compare 4 output enable + CC4E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC4P: u1 = 0, + reserved1: u1 = 0, + /// Capture/Compare 4 output Polarity + CC4NP: u1 = 0, + /// Capture/Compare 5 output enable + CC5E: u1 = 0, + /// Capture/Compare 5 output Polarity + CC5P: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CC6E: u1, // bit offset: 20 desc: Capture/Compare 6 output enable - CC6P: u1, // bit offset: 21 desc: Capture/Compare 6 output Polarity + /// Capture/Compare 6 output enable + CC6E: u1 = 0, + /// Capture/Compare 6 output Polarity + CC6P: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, @@ -17093,9 +24104,11 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, @@ -17111,11 +24124,14 @@ pub const TIM20 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UIFCPY: u1, // bit offset: 31 desc: UIF copy + /// UIF copy + UIFCPY: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17133,9 +24149,11 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17153,9 +24171,11 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 repetition counter register + + /// repetition counter register pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - REP: u16, // bit offset: 0 desc: Repetition counter value + /// Repetition counter value + REP: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17173,9 +24193,11 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17193,9 +24215,11 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + /// Capture/Compare 2 value + CCR2: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17213,9 +24237,11 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 capture/compare register 3 + + /// capture/compare register 3 pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - CCR3: u16, // bit offset: 0 desc: Capture/Compare 3 value + /// Capture/Compare 3 value + CCR3: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17233,9 +24259,11 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 capture/compare register 4 + + /// capture/compare register 4 pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - CCR4: u16, // bit offset: 0 desc: Capture/Compare 3 value + /// Capture/Compare 3 value + CCR4: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17253,20 +24281,33 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 break and dead-time register + + /// break and dead-time register pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - DTG: u8, // bit offset: 0 desc: Dead-time generator setup - LOCK: u2, // bit offset: 8 desc: Lock configuration - OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode - OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode - BKE: u1, // bit offset: 12 desc: Break enable - BKP: u1, // bit offset: 13 desc: Break polarity - AOE: u1, // bit offset: 14 desc: Automatic output enable - MOE: u1, // bit offset: 15 desc: Main output enable - BKF: u4, // bit offset: 16 desc: Break filter - BK2F: u4, // bit offset: 20 desc: Break 2 filter - BK2E: u1, // bit offset: 24 desc: Break 2 enable - BK2P: u1, // bit offset: 25 desc: Break 2 polarity + /// Dead-time generator setup + DTG: u8 = 0, + /// Lock configuration + LOCK: u2 = 0, + /// Off-state selection for Idle mode + OSSI: u1 = 0, + /// Off-state selection for Run mode + OSSR: u1 = 0, + /// Break enable + BKE: u1 = 0, + /// Break polarity + BKP: u1 = 0, + /// Automatic output enable + AOE: u1 = 0, + /// Main output enable + MOE: u1 = 0, + /// Break filter + BKF: u4 = 0, + /// Break 2 filter + BK2F: u4 = 0, + /// Break 2 enable + BK2E: u1 = 0, + /// Break 2 polarity + BK2P: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, @@ -17274,13 +24315,16 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -17301,9 +24345,11 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17321,21 +24367,31 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 84 capture/compare mode register 3 (output mode) + + /// capture/compare mode register 3 (output mode) pub const CCMR3_Output = mmio(Address + 0x00000054, 32, packed struct { reserved2: u1 = 0, reserved1: u1 = 0, - OC5FE: u1, // bit offset: 2 desc: Output compare 5 fast enable - OC5PE: u1, // bit offset: 3 desc: Output compare 5 preload enable - OC5M: u3, // bit offset: 4 desc: Output compare 5 mode - OC5CE: u1, // bit offset: 7 desc: Output compare 5 clear enable + /// Output compare 5 fast enable + OC5FE: u1 = 0, + /// Output compare 5 preload enable + OC5PE: u1 = 0, + /// Output compare 5 mode + OC5M: u3 = 0, + /// Output compare 5 clear enable + OC5CE: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - OC6FE: u1, // bit offset: 10 desc: Output compare 6 fast enable - OC6PE: u1, // bit offset: 11 desc: Output compare 6 preload enable - OC6M: u3, // bit offset: 12 desc: Output compare 6 mode - OC6CE: u1, // bit offset: 15 desc: Output compare 6 clear enable - OC5M_3: u1, // bit offset: 16 desc: Outout Compare 5 mode bit 3 + /// Output compare 6 fast enable + OC6FE: u1 = 0, + /// Output compare 6 preload enable + OC6PE: u1 = 0, + /// Output compare 6 mode + OC6M: u3 = 0, + /// Output compare 6 clear enable + OC6CE: u1 = 0, + /// Outout Compare 5 mode bit 3 + OC5M_3: u1 = 0, reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -17343,7 +24399,8 @@ pub const TIM20 = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - OC6M_3: u1, // bit offset: 24 desc: Outout Compare 6 mode bit 3 + /// Outout Compare 6 mode bit 3 + OC6M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -17352,9 +24409,11 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 88 capture/compare register 5 + + /// capture/compare register 5 pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - CCR5: u16, // bit offset: 0 desc: Capture/Compare 5 value + /// Capture/Compare 5 value + CCR5: u16 = 0, reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, @@ -17368,13 +24427,18 @@ pub const TIM20 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - GC5C1: u1, // bit offset: 29 desc: Group Channel 5 and Channel 1 - GC5C2: u1, // bit offset: 30 desc: Group Channel 5 and Channel 2 - GC5C3: u1, // bit offset: 31 desc: Group Channel 5 and Channel 3 + /// Group Channel 5 and Channel 1 + GC5C1: u1 = 0, + /// Group Channel 5 and Channel 2 + GC5C2: u1 = 0, + /// Group Channel 5 and Channel 3 + GC5C3: u1 = 0, }); - // byte offset: 92 capture/compare register 6 + + /// capture/compare register 6 pub const CCR6 = mmio(Address + 0x0000005c, 32, packed struct { - CCR6: u16, // bit offset: 0 desc: Capture/Compare 6 value + /// Capture/Compare 6 value + CCR6: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17392,10 +24456,13 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 96 option registers + + /// option registers pub const OR = mmio(Address + 0x00000060, 32, packed struct { - TIM1_ETR_ADC1_RMP: u2, // bit offset: 0 desc: TIM1_ETR_ADC1 remapping capability - TIM1_ETR_ADC4_RMP: u2, // bit offset: 2 desc: TIM1_ETR_ADC4 remapping capability + /// TIM1_ETR_ADC1 remapping capability + TIM1_ETR_ADC1_RMP: u2 = 0, + /// TIM1_ETR_ADC4 remapping capability + TIM1_ETR_ADC4_RMP: u2 = 0, padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -17426,20 +24493,32 @@ pub const TIM20 = extern struct { padding1: u1 = 0, }); }; + +/// Advanced-timers pub const TIM8 = extern struct { pub const Address: u32 = 0x40013400; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode - DIR: u1, // bit offset: 4 desc: Direction - CMS: u2, // bit offset: 5 desc: Center-aligned mode selection - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division - reserved1: u1 = 0, - UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, + /// Direction + DIR: u1 = 0, + /// Center-aligned mode selection + CMS: u2 = 0, + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, + reserved1: u1 = 0, + /// UIF status bit remapping + UIFREMAP: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -17461,27 +24540,43 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - CCPC: u1, // bit offset: 0 desc: Capture/compare preloaded control - reserved1: u1 = 0, - CCUS: u1, // bit offset: 2 desc: Capture/compare control update selection - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection - MMS: u3, // bit offset: 4 desc: Master mode selection - TI1S: u1, // bit offset: 7 desc: TI1 selection - OIS1: u1, // bit offset: 8 desc: Output Idle state 1 - OIS1N: u1, // bit offset: 9 desc: Output Idle state 1 - OIS2: u1, // bit offset: 10 desc: Output Idle state 2 - OIS2N: u1, // bit offset: 11 desc: Output Idle state 2 - OIS3: u1, // bit offset: 12 desc: Output Idle state 3 - OIS3N: u1, // bit offset: 13 desc: Output Idle state 3 - OIS4: u1, // bit offset: 14 desc: Output Idle state 4 - reserved2: u1 = 0, - OIS5: u1, // bit offset: 16 desc: Output Idle state 5 + /// Capture/compare preloaded control + CCPC: u1 = 0, + reserved1: u1 = 0, + /// Capture/compare control update selection + CCUS: u1 = 0, + /// Capture/compare DMA selection + CCDS: u1 = 0, + /// Master mode selection + MMS: u3 = 0, + /// TI1 selection + TI1S: u1 = 0, + /// Output Idle state 1 + OIS1: u1 = 0, + /// Output Idle state 1 + OIS1N: u1 = 0, + /// Output Idle state 2 + OIS2: u1 = 0, + /// Output Idle state 2 + OIS2N: u1 = 0, + /// Output Idle state 3 + OIS3: u1 = 0, + /// Output Idle state 3 + OIS3N: u1 = 0, + /// Output Idle state 4 + OIS4: u1 = 0, + reserved2: u1 = 0, + /// Output Idle state 5 + OIS5: u1 = 0, reserved3: u1 = 0, - OIS6: u1, // bit offset: 18 desc: Output Idle state 6 + /// Output Idle state 6 + OIS6: u1 = 0, reserved4: u1 = 0, - MMS2: u4, // bit offset: 20 desc: Master mode selection 2 + /// Master mode selection 2 + MMS2: u4 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -17491,17 +24586,27 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection - OCCS: u1, // bit offset: 3 desc: OCREF clear selection - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode - ETF: u4, // bit offset: 8 desc: External trigger filter - ETPS: u2, // bit offset: 12 desc: External trigger prescaler - ECE: u1, // bit offset: 14 desc: External clock enable - ETP: u1, // bit offset: 15 desc: External trigger polarity - SMS3: u1, // bit offset: 16 desc: Slave mode selection bit 3 + /// Slave mode selection + SMS: u3 = 0, + /// OCREF clear selection + OCCS: u1 = 0, + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, + /// External trigger filter + ETF: u4 = 0, + /// External trigger prescaler + ETPS: u2 = 0, + /// External clock enable + ECE: u1 = 0, + /// External trigger polarity + ETP: u1 = 0, + /// Slave mode selection bit 3 + SMS3: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -17518,23 +24623,39 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable - CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable - CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable - COMIE: u1, // bit offset: 5 desc: COM interrupt enable - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable - BIE: u1, // bit offset: 7 desc: Break interrupt enable - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable - CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable - CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable - CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable - COMDE: u1, // bit offset: 13 desc: COM DMA request enable - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, + /// Capture/Compare 3 interrupt enable + CC3IE: u1 = 0, + /// Capture/Compare 4 interrupt enable + CC4IE: u1 = 0, + /// COM interrupt enable + COMIE: u1 = 0, + /// Trigger interrupt enable + TIE: u1 = 0, + /// Break interrupt enable + BIE: u1 = 0, + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, + /// Capture/Compare 2 DMA request enable + CC2DE: u1 = 0, + /// Capture/Compare 3 DMA request enable + CC3DE: u1 = 0, + /// Capture/Compare 4 DMA request enable + CC4DE: u1 = 0, + /// COM DMA request enable + COMDE: u1 = 0, + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -17553,26 +24674,42 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag - CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag - CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag - COMIF: u1, // bit offset: 5 desc: COM interrupt flag - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag - BIF: u1, // bit offset: 7 desc: Break interrupt flag - B2IF: u1, // bit offset: 8 desc: Break 2 interrupt flag - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag - CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag - CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, + /// Capture/Compare 3 interrupt flag + CC3IF: u1 = 0, + /// Capture/Compare 4 interrupt flag + CC4IF: u1 = 0, + /// COM interrupt flag + COMIF: u1 = 0, + /// Trigger interrupt flag + TIF: u1 = 0, + /// Break interrupt flag + BIF: u1 = 0, + /// Break 2 interrupt flag + B2IF: u1 = 0, + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, + /// Capture/Compare 3 overcapture flag + CC3OF: u1 = 0, + /// Capture/Compare 4 overcapture flag + CC4OF: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - C5IF: u1, // bit offset: 16 desc: Capture/Compare 5 interrupt flag - C6IF: u1, // bit offset: 17 desc: Capture/Compare 6 interrupt flag + /// Capture/Compare 5 interrupt flag + C5IF: u1 = 0, + /// Capture/Compare 6 interrupt flag + C6IF: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, @@ -17588,17 +24725,27 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation - CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation - CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation - COMG: u1, // bit offset: 5 desc: Capture/Compare control update generation - TG: u1, // bit offset: 6 desc: Trigger generation - BG: u1, // bit offset: 7 desc: Break generation - B2G: u1, // bit offset: 8 desc: Break 2 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, + /// Capture/compare 3 generation + CC3G: u1 = 0, + /// Capture/compare 4 generation + CC4G: u1 = 0, + /// Capture/Compare control update generation + COMG: u1 = 0, + /// Trigger generation + TG: u1 = 0, + /// Break generation + BG: u1 = 0, + /// Break 2 generation + B2G: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -17623,19 +24770,31 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode - OC1CE: u1, // bit offset: 7 desc: Output Compare 1 clear enable - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output Compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output Compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output Compare 2 mode - OC2CE: u1, // bit offset: 15 desc: Output Compare 2 clear enable - OC1M_3: u1, // bit offset: 16 desc: Output Compare 1 mode bit 3 + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output Compare 1 fast enable + OC1FE: u1 = 0, + /// Output Compare 1 preload enable + OC1PE: u1 = 0, + /// Output Compare 1 mode + OC1M: u3 = 0, + /// Output Compare 1 clear enable + OC1CE: u1 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output Compare 2 fast enable + OC2FE: u1 = 0, + /// Output Compare 2 preload enable + OC2PE: u1 = 0, + /// Output Compare 2 mode + OC2M: u3 = 0, + /// Output Compare 2 clear enable + OC2CE: u1 = 0, + /// Output Compare 1 mode bit 3 + OC1M_3: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -17643,7 +24802,8 @@ pub const TIM8 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC2M_3: u1, // bit offset: 24 desc: Output Compare 2 mode bit 3 + /// Output Compare 2 mode bit 3 + OC2M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -17652,14 +24812,21 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PCS: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - IC2PCS: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PCS: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PCS: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17677,19 +24844,31 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable - OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable - OC3M: u3, // bit offset: 4 desc: Output compare 3 mode - OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable - OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable - OC4M: u3, // bit offset: 12 desc: Output compare 4 mode - OC4CE: u1, // bit offset: 15 desc: Output compare 4 clear enable - OC3M_3: u1, // bit offset: 16 desc: Output Compare 3 mode bit 3 + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Output compare 3 fast enable + OC3FE: u1 = 0, + /// Output compare 3 preload enable + OC3PE: u1 = 0, + /// Output compare 3 mode + OC3M: u3 = 0, + /// Output compare 3 clear enable + OC3CE: u1 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Output compare 4 fast enable + OC4FE: u1 = 0, + /// Output compare 4 preload enable + OC4PE: u1 = 0, + /// Output compare 4 mode + OC4M: u3 = 0, + /// Output compare 4 clear enable + OC4CE: u1 = 0, + /// Output Compare 3 mode bit 3 + OC3M_3: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -17697,7 +24876,8 @@ pub const TIM8 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC4M_3: u1, // bit offset: 24 desc: Output Compare 4 mode bit 3 + /// Output Compare 4 mode bit 3 + OC4M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -17706,14 +24886,21 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (input mode) + + /// capture/compare mode register 2 (input mode) pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/compare 3 selection - IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler - IC3F: u4, // bit offset: 4 desc: Input capture 3 filter - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler - IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + /// Capture/compare 3 selection + CC3S: u2 = 0, + /// Input capture 3 prescaler + IC3PSC: u2 = 0, + /// Input capture 3 filter + IC3F: u4 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Input capture 4 prescaler + IC4PSC: u2 = 0, + /// Input capture 4 filter + IC4F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17731,30 +24918,50 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity - CC1NE: u1, // bit offset: 2 desc: Capture/Compare 1 complementary output enable - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity - CC2NE: u1, // bit offset: 6 desc: Capture/Compare 2 complementary output enable - CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity - CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable - CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity - CC3NE: u1, // bit offset: 10 desc: Capture/Compare 3 complementary output enable - CC3NP: u1, // bit offset: 11 desc: Capture/Compare 3 output Polarity - CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable - CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity - reserved1: u1 = 0, - CC4NP: u1, // bit offset: 15 desc: Capture/Compare 4 output Polarity - CC5E: u1, // bit offset: 16 desc: Capture/Compare 5 output enable - CC5P: u1, // bit offset: 17 desc: Capture/Compare 5 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, + /// Capture/Compare 1 complementary output enable + CC1NE: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, + /// Capture/Compare 2 complementary output enable + CC2NE: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2NP: u1 = 0, + /// Capture/Compare 3 output enable + CC3E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3P: u1 = 0, + /// Capture/Compare 3 complementary output enable + CC3NE: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3NP: u1 = 0, + /// Capture/Compare 4 output enable + CC4E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC4P: u1 = 0, + reserved1: u1 = 0, + /// Capture/Compare 4 output Polarity + CC4NP: u1 = 0, + /// Capture/Compare 5 output enable + CC5E: u1 = 0, + /// Capture/Compare 5 output Polarity + CC5P: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CC6E: u1, // bit offset: 20 desc: Capture/Compare 6 output enable - CC6P: u1, // bit offset: 21 desc: Capture/Compare 6 output Polarity + /// Capture/Compare 6 output enable + CC6E: u1 = 0, + /// Capture/Compare 6 output Polarity + CC6P: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, @@ -17766,9 +24973,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, @@ -17784,11 +24993,14 @@ pub const TIM8 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UIFCPY: u1, // bit offset: 31 desc: UIF copy + /// UIF copy + UIFCPY: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17806,9 +25018,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17826,9 +25040,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 repetition counter register + + /// repetition counter register pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - REP: u16, // bit offset: 0 desc: Repetition counter value + /// Repetition counter value + REP: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17846,9 +25062,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17866,9 +25084,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + /// Capture/Compare 2 value + CCR2: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17886,9 +25106,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 capture/compare register 3 + + /// capture/compare register 3 pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - CCR3: u16, // bit offset: 0 desc: Capture/Compare 3 value + /// Capture/Compare 3 value + CCR3: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17906,9 +25128,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 capture/compare register 4 + + /// capture/compare register 4 pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - CCR4: u16, // bit offset: 0 desc: Capture/Compare 3 value + /// Capture/Compare 3 value + CCR4: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17926,20 +25150,33 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 break and dead-time register + + /// break and dead-time register pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - DTG: u8, // bit offset: 0 desc: Dead-time generator setup - LOCK: u2, // bit offset: 8 desc: Lock configuration - OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode - OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode - BKE: u1, // bit offset: 12 desc: Break enable - BKP: u1, // bit offset: 13 desc: Break polarity - AOE: u1, // bit offset: 14 desc: Automatic output enable - MOE: u1, // bit offset: 15 desc: Main output enable - BKF: u4, // bit offset: 16 desc: Break filter - BK2F: u4, // bit offset: 20 desc: Break 2 filter - BK2E: u1, // bit offset: 24 desc: Break 2 enable - BK2P: u1, // bit offset: 25 desc: Break 2 polarity + /// Dead-time generator setup + DTG: u8 = 0, + /// Lock configuration + LOCK: u2 = 0, + /// Off-state selection for Idle mode + OSSI: u1 = 0, + /// Off-state selection for Run mode + OSSR: u1 = 0, + /// Break enable + BKE: u1 = 0, + /// Break polarity + BKP: u1 = 0, + /// Automatic output enable + AOE: u1 = 0, + /// Main output enable + MOE: u1 = 0, + /// Break filter + BKF: u4 = 0, + /// Break 2 filter + BK2F: u4 = 0, + /// Break 2 enable + BK2E: u1 = 0, + /// Break 2 polarity + BK2P: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, @@ -17947,13 +25184,16 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -17974,9 +25214,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17994,21 +25236,31 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 84 capture/compare mode register 3 (output mode) + + /// capture/compare mode register 3 (output mode) pub const CCMR3_Output = mmio(Address + 0x00000054, 32, packed struct { reserved2: u1 = 0, reserved1: u1 = 0, - OC5FE: u1, // bit offset: 2 desc: Output compare 5 fast enable - OC5PE: u1, // bit offset: 3 desc: Output compare 5 preload enable - OC5M: u3, // bit offset: 4 desc: Output compare 5 mode - OC5CE: u1, // bit offset: 7 desc: Output compare 5 clear enable + /// Output compare 5 fast enable + OC5FE: u1 = 0, + /// Output compare 5 preload enable + OC5PE: u1 = 0, + /// Output compare 5 mode + OC5M: u3 = 0, + /// Output compare 5 clear enable + OC5CE: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - OC6FE: u1, // bit offset: 10 desc: Output compare 6 fast enable - OC6PE: u1, // bit offset: 11 desc: Output compare 6 preload enable - OC6M: u3, // bit offset: 12 desc: Output compare 6 mode - OC6CE: u1, // bit offset: 15 desc: Output compare 6 clear enable - OC5M_3: u1, // bit offset: 16 desc: Outout Compare 5 mode bit 3 + /// Output compare 6 fast enable + OC6FE: u1 = 0, + /// Output compare 6 preload enable + OC6PE: u1 = 0, + /// Output compare 6 mode + OC6M: u3 = 0, + /// Output compare 6 clear enable + OC6CE: u1 = 0, + /// Outout Compare 5 mode bit 3 + OC5M_3: u1 = 0, reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -18016,7 +25268,8 @@ pub const TIM8 = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - OC6M_3: u1, // bit offset: 24 desc: Outout Compare 6 mode bit 3 + /// Outout Compare 6 mode bit 3 + OC6M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -18025,9 +25278,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 88 capture/compare register 5 + + /// capture/compare register 5 pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - CCR5: u16, // bit offset: 0 desc: Capture/Compare 5 value + /// Capture/Compare 5 value + CCR5: u16 = 0, reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, @@ -18041,13 +25296,18 @@ pub const TIM8 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - GC5C1: u1, // bit offset: 29 desc: Group Channel 5 and Channel 1 - GC5C2: u1, // bit offset: 30 desc: Group Channel 5 and Channel 2 - GC5C3: u1, // bit offset: 31 desc: Group Channel 5 and Channel 3 + /// Group Channel 5 and Channel 1 + GC5C1: u1 = 0, + /// Group Channel 5 and Channel 2 + GC5C2: u1 = 0, + /// Group Channel 5 and Channel 3 + GC5C3: u1 = 0, }); - // byte offset: 92 capture/compare register 6 + + /// capture/compare register 6 pub const CCR6 = mmio(Address + 0x0000005c, 32, packed struct { - CCR6: u16, // bit offset: 0 desc: Capture/Compare 6 value + /// Capture/Compare 6 value + CCR6: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -18065,10 +25325,13 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 96 option registers + + /// option registers pub const OR = mmio(Address + 0x00000060, 32, packed struct { - TIM8_ETR_ADC2_RMP: u2, // bit offset: 0 desc: TIM8_ETR_ADC2 remapping capability - TIM8_ETR_ADC3_RMP: u2, // bit offset: 2 desc: TIM8_ETR_ADC3 remapping capability + /// TIM8_ETR_ADC2 remapping capability + TIM8_ETR_ADC2_RMP: u2 = 0, + /// TIM8_ETR_ADC3 remapping capability + TIM8_ETR_ADC3_RMP: u2 = 0, padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -18099,21 +25362,13 @@ pub const TIM8 = extern struct { padding1: u1 = 0, }); }; + +/// Analog-to-Digital Converter pub const ADC1 = extern struct { pub const Address: u32 = 0x50000000; - // byte offset: 0 interrupt and status register + + /// interrupt and status register pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - ADRDY: u1, // bit offset: 0 desc: ADRDY - EOSMP: u1, // bit offset: 1 desc: EOSMP - EOC: u1, // bit offset: 2 desc: EOC - EOS: u1, // bit offset: 3 desc: EOS - OVR: u1, // bit offset: 4 desc: OVR - JEOC: u1, // bit offset: 5 desc: JEOC - JEOS: u1, // bit offset: 6 desc: JEOS - AWD1: u1, // bit offset: 7 desc: AWD1 - AWD2: u1, // bit offset: 8 desc: AWD2 - AWD3: u1, // bit offset: 9 desc: AWD3 - JQOVF: u1, // bit offset: 10 desc: JQOVF padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -18136,19 +25391,9 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 interrupt enable register + + /// interrupt enable register pub const IER = mmio(Address + 0x00000004, 32, packed struct { - ADRDYIE: u1, // bit offset: 0 desc: ADRDYIE - EOSMPIE: u1, // bit offset: 1 desc: EOSMPIE - EOCIE: u1, // bit offset: 2 desc: EOCIE - EOSIE: u1, // bit offset: 3 desc: EOSIE - OVRIE: u1, // bit offset: 4 desc: OVRIE - JEOCIE: u1, // bit offset: 5 desc: JEOCIE - JEOSIE: u1, // bit offset: 6 desc: JEOSIE - AWD1IE: u1, // bit offset: 7 desc: AWD1IE - AWD2IE: u1, // bit offset: 8 desc: AWD2IE - AWD3IE: u1, // bit offset: 9 desc: AWD3IE - JQOVFIE: u1, // bit offset: 10 desc: JQOVFIE padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -18171,14 +25416,9 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 control register + + /// control register pub const CR = mmio(Address + 0x00000008, 32, packed struct { - ADEN: u1, // bit offset: 0 desc: ADEN - ADDIS: u1, // bit offset: 1 desc: ADDIS - ADSTART: u1, // bit offset: 2 desc: ADSTART - JADSTART: u1, // bit offset: 3 desc: JADSTART - ADSTP: u1, // bit offset: 4 desc: ADSTP - JADSTP: u1, // bit offset: 5 desc: JADSTP reserved22: u1 = 0, reserved21: u1 = 0, reserved20: u1 = 0, @@ -18201,85 +25441,46 @@ pub const ADC1 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADVREGEN: u1, // bit offset: 28 desc: ADVREGEN - DEEPPWD: u1, // bit offset: 29 desc: DEEPPWD - ADCALDIF: u1, // bit offset: 30 desc: ADCALDIF - ADCAL: u1, // bit offset: 31 desc: ADCAL }); - // byte offset: 12 configuration register + + /// configuration register pub const CFGR = mmio(Address + 0x0000000c, 32, packed struct { - DMAEN: u1, // bit offset: 0 desc: DMAEN - DMACFG: u1, // bit offset: 1 desc: DMACFG - reserved1: u1 = 0, - RES: u2, // bit offset: 3 desc: RES - ALIGN: u1, // bit offset: 5 desc: ALIGN - EXTSEL: u4, // bit offset: 6 desc: EXTSEL - EXTEN: u2, // bit offset: 10 desc: EXTEN - OVRMOD: u1, // bit offset: 12 desc: OVRMOD - CONT: u1, // bit offset: 13 desc: CONT - AUTDLY: u1, // bit offset: 14 desc: AUTDLY - AUTOFF: u1, // bit offset: 15 desc: AUTOFF - DISCEN: u1, // bit offset: 16 desc: DISCEN - DISCNUM: u3, // bit offset: 17 desc: DISCNUM - JDISCEN: u1, // bit offset: 20 desc: JDISCEN - JQM: u1, // bit offset: 21 desc: JQM - AWD1SGL: u1, // bit offset: 22 desc: AWD1SGL - AWD1EN: u1, // bit offset: 23 desc: AWD1EN - JAWD1EN: u1, // bit offset: 24 desc: JAWD1EN - JAUTO: u1, // bit offset: 25 desc: JAUTO - AWDCH1CH: u5, // bit offset: 26 desc: AWDCH1CH - padding1: u1 = 0, - }); - // byte offset: 20 sample time register 1 + reserved1: u1 = 0, + padding1: u1 = 0, + }); + + /// sample time register 1 pub const SMPR1 = mmio(Address + 0x00000014, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - SMP1: u3, // bit offset: 3 desc: SMP1 - SMP2: u3, // bit offset: 6 desc: SMP2 - SMP3: u3, // bit offset: 9 desc: SMP3 - SMP4: u3, // bit offset: 12 desc: SMP4 - SMP5: u3, // bit offset: 15 desc: SMP5 - SMP6: u3, // bit offset: 18 desc: SMP6 - SMP7: u3, // bit offset: 21 desc: SMP7 - SMP8: u3, // bit offset: 24 desc: SMP8 - SMP9: u3, // bit offset: 27 desc: SMP9 padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 sample time register 2 + + /// sample time register 2 pub const SMPR2 = mmio(Address + 0x00000018, 32, packed struct { - SMP10: u3, // bit offset: 0 desc: SMP10 - SMP11: u3, // bit offset: 3 desc: SMP11 - SMP12: u3, // bit offset: 6 desc: SMP12 - SMP13: u3, // bit offset: 9 desc: SMP13 - SMP14: u3, // bit offset: 12 desc: SMP14 - SMP15: u3, // bit offset: 15 desc: SMP15 - SMP16: u3, // bit offset: 18 desc: SMP16 - SMP17: u3, // bit offset: 21 desc: SMP17 - SMP18: u3, // bit offset: 24 desc: SMP18 padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 watchdog threshold register 1 + + /// watchdog threshold register 1 pub const TR1 = mmio(Address + 0x00000020, 32, packed struct { - LT1: u12, // bit offset: 0 desc: LT1 reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - HT1: u12, // bit offset: 16 desc: HT1 padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 watchdog threshold register + + /// watchdog threshold register pub const TR2 = mmio(Address + 0x00000024, 32, packed struct { - LT2: u8, // bit offset: 0 desc: LT2 reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -18288,7 +25489,6 @@ pub const ADC1 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - HT2: u8, // bit offset: 16 desc: HT2 padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -18298,9 +25498,9 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 watchdog threshold register 3 + + /// watchdog threshold register 3 pub const TR3 = mmio(Address + 0x00000028, 32, packed struct { - LT3: u8, // bit offset: 0 desc: LT3 reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -18309,7 +25509,6 @@ pub const ADC1 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - HT3: u8, // bit offset: 16 desc: HT3 padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -18319,57 +25518,44 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 regular sequence register 1 + + /// regular sequence register 1 pub const SQR1 = mmio(Address + 0x00000030, 32, packed struct { - L3: u4, // bit offset: 0 desc: L3 reserved2: u1 = 0, reserved1: u1 = 0, - SQ1: u5, // bit offset: 6 desc: SQ1 reserved3: u1 = 0, - SQ2: u5, // bit offset: 12 desc: SQ2 reserved4: u1 = 0, - SQ3: u5, // bit offset: 18 desc: SQ3 reserved5: u1 = 0, - SQ4: u5, // bit offset: 24 desc: SQ4 padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 regular sequence register 2 + + /// regular sequence register 2 pub const SQR2 = mmio(Address + 0x00000034, 32, packed struct { - SQ5: u5, // bit offset: 0 desc: SQ5 reserved1: u1 = 0, - SQ6: u5, // bit offset: 6 desc: SQ6 reserved2: u1 = 0, - SQ7: u5, // bit offset: 12 desc: SQ7 reserved3: u1 = 0, - SQ8: u5, // bit offset: 18 desc: SQ8 reserved4: u1 = 0, - SQ9: u5, // bit offset: 24 desc: SQ9 padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 regular sequence register 3 + + /// regular sequence register 3 pub const SQR3 = mmio(Address + 0x00000038, 32, packed struct { - SQ10: u5, // bit offset: 0 desc: SQ10 reserved1: u1 = 0, - SQ11: u5, // bit offset: 6 desc: SQ11 reserved2: u1 = 0, - SQ12: u5, // bit offset: 12 desc: SQ12 reserved3: u1 = 0, - SQ13: u5, // bit offset: 18 desc: SQ13 reserved4: u1 = 0, - SQ14: u5, // bit offset: 24 desc: SQ14 padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 regular sequence register 4 + + /// regular sequence register 4 pub const SQR4 = mmio(Address + 0x0000003c, 32, packed struct { - SQ15: u5, // bit offset: 0 desc: SQ15 reserved1: u1 = 0, - SQ16: u5, // bit offset: 6 desc: SQ16 padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -18392,9 +25578,9 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 regular Data Register + + /// regular Data Register pub const DR = mmio(Address + 0x00000040, 32, packed struct { - regularDATA: u16, // bit offset: 0 desc: regularDATA padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -18412,23 +25598,17 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 injected sequence register + + /// injected sequence register pub const JSQR = mmio(Address + 0x0000004c, 32, packed struct { - JL: u2, // bit offset: 0 desc: JL - JEXTSEL: u4, // bit offset: 2 desc: JEXTSEL - JEXTEN: u2, // bit offset: 6 desc: JEXTEN - JSQ1: u5, // bit offset: 8 desc: JSQ1 reserved1: u1 = 0, - JSQ2: u5, // bit offset: 14 desc: JSQ2 reserved2: u1 = 0, - JSQ3: u5, // bit offset: 20 desc: JSQ3 reserved3: u1 = 0, - JSQ4: u5, // bit offset: 26 desc: JSQ4 padding1: u1 = 0, }); - // byte offset: 96 offset register 1 + + /// offset register 1 pub const OFR1 = mmio(Address + 0x00000060, 32, packed struct { - OFFSET1: u12, // bit offset: 0 desc: OFFSET1 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -18443,12 +25623,10 @@ pub const ADC1 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET1_CH: u5, // bit offset: 26 desc: OFFSET1_CH - OFFSET1_EN: u1, // bit offset: 31 desc: OFFSET1_EN }); - // byte offset: 100 offset register 2 + + /// offset register 2 pub const OFR2 = mmio(Address + 0x00000064, 32, packed struct { - OFFSET2: u12, // bit offset: 0 desc: OFFSET2 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -18463,12 +25641,10 @@ pub const ADC1 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET2_CH: u5, // bit offset: 26 desc: OFFSET2_CH - OFFSET2_EN: u1, // bit offset: 31 desc: OFFSET2_EN }); - // byte offset: 104 offset register 3 + + /// offset register 3 pub const OFR3 = mmio(Address + 0x00000068, 32, packed struct { - OFFSET3: u12, // bit offset: 0 desc: OFFSET3 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -18483,12 +25659,10 @@ pub const ADC1 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET3_CH: u5, // bit offset: 26 desc: OFFSET3_CH - OFFSET3_EN: u1, // bit offset: 31 desc: OFFSET3_EN }); - // byte offset: 108 offset register 4 + + /// offset register 4 pub const OFR4 = mmio(Address + 0x0000006c, 32, packed struct { - OFFSET4: u12, // bit offset: 0 desc: OFFSET4 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -18503,12 +25677,10 @@ pub const ADC1 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET4_CH: u5, // bit offset: 26 desc: OFFSET4_CH - OFFSET4_EN: u1, // bit offset: 31 desc: OFFSET4_EN }); - // byte offset: 128 injected data register 1 + + /// injected data register 1 pub const JDR1 = mmio(Address + 0x00000080, 32, packed struct { - JDATA1: u16, // bit offset: 0 desc: JDATA1 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -18526,9 +25698,9 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 132 injected data register 2 + + /// injected data register 2 pub const JDR2 = mmio(Address + 0x00000084, 32, packed struct { - JDATA2: u16, // bit offset: 0 desc: JDATA2 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -18546,9 +25718,9 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 136 injected data register 3 + + /// injected data register 3 pub const JDR3 = mmio(Address + 0x00000088, 32, packed struct { - JDATA3: u16, // bit offset: 0 desc: JDATA3 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -18566,9 +25738,9 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 140 injected data register 4 + + /// injected data register 4 pub const JDR4 = mmio(Address + 0x0000008c, 32, packed struct { - JDATA4: u16, // bit offset: 0 desc: JDATA4 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -18586,10 +25758,10 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 160 Analog Watchdog 2 Configuration Register + + /// Analog Watchdog 2 Configuration Register pub const AWD2CR = mmio(Address + 0x000000a0, 32, packed struct { reserved1: u1 = 0, - AWD2CH: u18, // bit offset: 1 desc: AWD2CH padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -18604,10 +25776,10 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 164 Analog Watchdog 3 Configuration Register + + /// Analog Watchdog 3 Configuration Register pub const AWD3CR = mmio(Address + 0x000000a4, 32, packed struct { reserved1: u1 = 0, - AWD3CH: u18, // bit offset: 1 desc: AWD3CH padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -18622,11 +25794,14 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 176 Differential Mode Selection Register 2 + + /// Differential Mode Selection Register 2 pub const DIFSEL = mmio(Address + 0x000000b0, 32, packed struct { reserved1: u1 = 0, - DIFSEL_1_15: u15, // bit offset: 1 desc: Differential mode for channels 15 to 1 - DIFSEL_16_18: u3, // bit offset: 16 desc: Differential mode for channels 18 to 16 + /// Differential mode for channels 15 to 1 + DIFSEL_1_15: u15 = 0, + /// Differential mode for channels 18 to 16 + DIFSEL_16_18: u3 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -18641,9 +25816,9 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 180 Calibration Factors + + /// Calibration Factors pub const CALFACT = mmio(Address + 0x000000b4, 32, packed struct { - CALFACT_S: u7, // bit offset: 0 desc: CALFACT_S reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, @@ -18653,7 +25828,6 @@ pub const ADC1 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CALFACT_D: u7, // bit offset: 16 desc: CALFACT_D padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -18665,21 +25839,13 @@ pub const ADC1 = extern struct { padding1: u1 = 0, }); }; + +/// Analog-to-Digital Converter pub const ADC2 = extern struct { pub const Address: u32 = 0x50000100; - // byte offset: 0 interrupt and status register + + /// interrupt and status register pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - ADRDY: u1, // bit offset: 0 desc: ADRDY - EOSMP: u1, // bit offset: 1 desc: EOSMP - EOC: u1, // bit offset: 2 desc: EOC - EOS: u1, // bit offset: 3 desc: EOS - OVR: u1, // bit offset: 4 desc: OVR - JEOC: u1, // bit offset: 5 desc: JEOC - JEOS: u1, // bit offset: 6 desc: JEOS - AWD1: u1, // bit offset: 7 desc: AWD1 - AWD2: u1, // bit offset: 8 desc: AWD2 - AWD3: u1, // bit offset: 9 desc: AWD3 - JQOVF: u1, // bit offset: 10 desc: JQOVF padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -18702,19 +25868,9 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 interrupt enable register + + /// interrupt enable register pub const IER = mmio(Address + 0x00000004, 32, packed struct { - ADRDYIE: u1, // bit offset: 0 desc: ADRDYIE - EOSMPIE: u1, // bit offset: 1 desc: EOSMPIE - EOCIE: u1, // bit offset: 2 desc: EOCIE - EOSIE: u1, // bit offset: 3 desc: EOSIE - OVRIE: u1, // bit offset: 4 desc: OVRIE - JEOCIE: u1, // bit offset: 5 desc: JEOCIE - JEOSIE: u1, // bit offset: 6 desc: JEOSIE - AWD1IE: u1, // bit offset: 7 desc: AWD1IE - AWD2IE: u1, // bit offset: 8 desc: AWD2IE - AWD3IE: u1, // bit offset: 9 desc: AWD3IE - JQOVFIE: u1, // bit offset: 10 desc: JQOVFIE padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -18737,14 +25893,9 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 control register + + /// control register pub const CR = mmio(Address + 0x00000008, 32, packed struct { - ADEN: u1, // bit offset: 0 desc: ADEN - ADDIS: u1, // bit offset: 1 desc: ADDIS - ADSTART: u1, // bit offset: 2 desc: ADSTART - JADSTART: u1, // bit offset: 3 desc: JADSTART - ADSTP: u1, // bit offset: 4 desc: ADSTP - JADSTP: u1, // bit offset: 5 desc: JADSTP reserved22: u1 = 0, reserved21: u1 = 0, reserved20: u1 = 0, @@ -18767,85 +25918,46 @@ pub const ADC2 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADVREGEN: u1, // bit offset: 28 desc: ADVREGEN - DEEPPWD: u1, // bit offset: 29 desc: DEEPPWD - ADCALDIF: u1, // bit offset: 30 desc: ADCALDIF - ADCAL: u1, // bit offset: 31 desc: ADCAL }); - // byte offset: 12 configuration register + + /// configuration register pub const CFGR = mmio(Address + 0x0000000c, 32, packed struct { - DMAEN: u1, // bit offset: 0 desc: DMAEN - DMACFG: u1, // bit offset: 1 desc: DMACFG - reserved1: u1 = 0, - RES: u2, // bit offset: 3 desc: RES - ALIGN: u1, // bit offset: 5 desc: ALIGN - EXTSEL: u4, // bit offset: 6 desc: EXTSEL - EXTEN: u2, // bit offset: 10 desc: EXTEN - OVRMOD: u1, // bit offset: 12 desc: OVRMOD - CONT: u1, // bit offset: 13 desc: CONT - AUTDLY: u1, // bit offset: 14 desc: AUTDLY - AUTOFF: u1, // bit offset: 15 desc: AUTOFF - DISCEN: u1, // bit offset: 16 desc: DISCEN - DISCNUM: u3, // bit offset: 17 desc: DISCNUM - JDISCEN: u1, // bit offset: 20 desc: JDISCEN - JQM: u1, // bit offset: 21 desc: JQM - AWD1SGL: u1, // bit offset: 22 desc: AWD1SGL - AWD1EN: u1, // bit offset: 23 desc: AWD1EN - JAWD1EN: u1, // bit offset: 24 desc: JAWD1EN - JAUTO: u1, // bit offset: 25 desc: JAUTO - AWDCH1CH: u5, // bit offset: 26 desc: AWDCH1CH - padding1: u1 = 0, - }); - // byte offset: 20 sample time register 1 + reserved1: u1 = 0, + padding1: u1 = 0, + }); + + /// sample time register 1 pub const SMPR1 = mmio(Address + 0x00000014, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - SMP1: u3, // bit offset: 3 desc: SMP1 - SMP2: u3, // bit offset: 6 desc: SMP2 - SMP3: u3, // bit offset: 9 desc: SMP3 - SMP4: u3, // bit offset: 12 desc: SMP4 - SMP5: u3, // bit offset: 15 desc: SMP5 - SMP6: u3, // bit offset: 18 desc: SMP6 - SMP7: u3, // bit offset: 21 desc: SMP7 - SMP8: u3, // bit offset: 24 desc: SMP8 - SMP9: u3, // bit offset: 27 desc: SMP9 padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 sample time register 2 + + /// sample time register 2 pub const SMPR2 = mmio(Address + 0x00000018, 32, packed struct { - SMP10: u3, // bit offset: 0 desc: SMP10 - SMP11: u3, // bit offset: 3 desc: SMP11 - SMP12: u3, // bit offset: 6 desc: SMP12 - SMP13: u3, // bit offset: 9 desc: SMP13 - SMP14: u3, // bit offset: 12 desc: SMP14 - SMP15: u3, // bit offset: 15 desc: SMP15 - SMP16: u3, // bit offset: 18 desc: SMP16 - SMP17: u3, // bit offset: 21 desc: SMP17 - SMP18: u3, // bit offset: 24 desc: SMP18 padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 watchdog threshold register 1 + + /// watchdog threshold register 1 pub const TR1 = mmio(Address + 0x00000020, 32, packed struct { - LT1: u12, // bit offset: 0 desc: LT1 reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - HT1: u12, // bit offset: 16 desc: HT1 padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 watchdog threshold register + + /// watchdog threshold register pub const TR2 = mmio(Address + 0x00000024, 32, packed struct { - LT2: u8, // bit offset: 0 desc: LT2 reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -18854,7 +25966,6 @@ pub const ADC2 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - HT2: u8, // bit offset: 16 desc: HT2 padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -18864,9 +25975,9 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 watchdog threshold register 3 + + /// watchdog threshold register 3 pub const TR3 = mmio(Address + 0x00000028, 32, packed struct { - LT3: u8, // bit offset: 0 desc: LT3 reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -18875,7 +25986,6 @@ pub const ADC2 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - HT3: u8, // bit offset: 16 desc: HT3 padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -18885,57 +25995,44 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 regular sequence register 1 + + /// regular sequence register 1 pub const SQR1 = mmio(Address + 0x00000030, 32, packed struct { - L3: u4, // bit offset: 0 desc: L3 reserved2: u1 = 0, reserved1: u1 = 0, - SQ1: u5, // bit offset: 6 desc: SQ1 reserved3: u1 = 0, - SQ2: u5, // bit offset: 12 desc: SQ2 reserved4: u1 = 0, - SQ3: u5, // bit offset: 18 desc: SQ3 reserved5: u1 = 0, - SQ4: u5, // bit offset: 24 desc: SQ4 padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 regular sequence register 2 + + /// regular sequence register 2 pub const SQR2 = mmio(Address + 0x00000034, 32, packed struct { - SQ5: u5, // bit offset: 0 desc: SQ5 reserved1: u1 = 0, - SQ6: u5, // bit offset: 6 desc: SQ6 reserved2: u1 = 0, - SQ7: u5, // bit offset: 12 desc: SQ7 reserved3: u1 = 0, - SQ8: u5, // bit offset: 18 desc: SQ8 reserved4: u1 = 0, - SQ9: u5, // bit offset: 24 desc: SQ9 padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 regular sequence register 3 + + /// regular sequence register 3 pub const SQR3 = mmio(Address + 0x00000038, 32, packed struct { - SQ10: u5, // bit offset: 0 desc: SQ10 reserved1: u1 = 0, - SQ11: u5, // bit offset: 6 desc: SQ11 reserved2: u1 = 0, - SQ12: u5, // bit offset: 12 desc: SQ12 reserved3: u1 = 0, - SQ13: u5, // bit offset: 18 desc: SQ13 reserved4: u1 = 0, - SQ14: u5, // bit offset: 24 desc: SQ14 padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 regular sequence register 4 + + /// regular sequence register 4 pub const SQR4 = mmio(Address + 0x0000003c, 32, packed struct { - SQ15: u5, // bit offset: 0 desc: SQ15 reserved1: u1 = 0, - SQ16: u5, // bit offset: 6 desc: SQ16 padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -18958,9 +26055,9 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 regular Data Register + + /// regular Data Register pub const DR = mmio(Address + 0x00000040, 32, packed struct { - regularDATA: u16, // bit offset: 0 desc: regularDATA padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -18978,23 +26075,17 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 injected sequence register + + /// injected sequence register pub const JSQR = mmio(Address + 0x0000004c, 32, packed struct { - JL: u2, // bit offset: 0 desc: JL - JEXTSEL: u4, // bit offset: 2 desc: JEXTSEL - JEXTEN: u2, // bit offset: 6 desc: JEXTEN - JSQ1: u5, // bit offset: 8 desc: JSQ1 reserved1: u1 = 0, - JSQ2: u5, // bit offset: 14 desc: JSQ2 reserved2: u1 = 0, - JSQ3: u5, // bit offset: 20 desc: JSQ3 reserved3: u1 = 0, - JSQ4: u5, // bit offset: 26 desc: JSQ4 padding1: u1 = 0, }); - // byte offset: 96 offset register 1 + + /// offset register 1 pub const OFR1 = mmio(Address + 0x00000060, 32, packed struct { - OFFSET1: u12, // bit offset: 0 desc: OFFSET1 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -19009,12 +26100,10 @@ pub const ADC2 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET1_CH: u5, // bit offset: 26 desc: OFFSET1_CH - OFFSET1_EN: u1, // bit offset: 31 desc: OFFSET1_EN }); - // byte offset: 100 offset register 2 + + /// offset register 2 pub const OFR2 = mmio(Address + 0x00000064, 32, packed struct { - OFFSET2: u12, // bit offset: 0 desc: OFFSET2 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -19029,12 +26118,10 @@ pub const ADC2 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET2_CH: u5, // bit offset: 26 desc: OFFSET2_CH - OFFSET2_EN: u1, // bit offset: 31 desc: OFFSET2_EN }); - // byte offset: 104 offset register 3 + + /// offset register 3 pub const OFR3 = mmio(Address + 0x00000068, 32, packed struct { - OFFSET3: u12, // bit offset: 0 desc: OFFSET3 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -19049,12 +26136,10 @@ pub const ADC2 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET3_CH: u5, // bit offset: 26 desc: OFFSET3_CH - OFFSET3_EN: u1, // bit offset: 31 desc: OFFSET3_EN }); - // byte offset: 108 offset register 4 + + /// offset register 4 pub const OFR4 = mmio(Address + 0x0000006c, 32, packed struct { - OFFSET4: u12, // bit offset: 0 desc: OFFSET4 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -19069,12 +26154,10 @@ pub const ADC2 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET4_CH: u5, // bit offset: 26 desc: OFFSET4_CH - OFFSET4_EN: u1, // bit offset: 31 desc: OFFSET4_EN }); - // byte offset: 128 injected data register 1 + + /// injected data register 1 pub const JDR1 = mmio(Address + 0x00000080, 32, packed struct { - JDATA1: u16, // bit offset: 0 desc: JDATA1 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -19092,9 +26175,9 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 132 injected data register 2 + + /// injected data register 2 pub const JDR2 = mmio(Address + 0x00000084, 32, packed struct { - JDATA2: u16, // bit offset: 0 desc: JDATA2 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -19112,9 +26195,9 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 136 injected data register 3 + + /// injected data register 3 pub const JDR3 = mmio(Address + 0x00000088, 32, packed struct { - JDATA3: u16, // bit offset: 0 desc: JDATA3 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -19132,9 +26215,9 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 140 injected data register 4 + + /// injected data register 4 pub const JDR4 = mmio(Address + 0x0000008c, 32, packed struct { - JDATA4: u16, // bit offset: 0 desc: JDATA4 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -19152,10 +26235,10 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 160 Analog Watchdog 2 Configuration Register + + /// Analog Watchdog 2 Configuration Register pub const AWD2CR = mmio(Address + 0x000000a0, 32, packed struct { reserved1: u1 = 0, - AWD2CH: u18, // bit offset: 1 desc: AWD2CH padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -19170,10 +26253,10 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 164 Analog Watchdog 3 Configuration Register + + /// Analog Watchdog 3 Configuration Register pub const AWD3CR = mmio(Address + 0x000000a4, 32, packed struct { reserved1: u1 = 0, - AWD3CH: u18, // bit offset: 1 desc: AWD3CH padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -19188,11 +26271,14 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 176 Differential Mode Selection Register 2 + + /// Differential Mode Selection Register 2 pub const DIFSEL = mmio(Address + 0x000000b0, 32, packed struct { reserved1: u1 = 0, - DIFSEL_1_15: u15, // bit offset: 1 desc: Differential mode for channels 15 to 1 - DIFSEL_16_18: u3, // bit offset: 16 desc: Differential mode for channels 18 to 16 + /// Differential mode for channels 15 to 1 + DIFSEL_1_15: u15 = 0, + /// Differential mode for channels 18 to 16 + DIFSEL_16_18: u3 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -19207,9 +26293,9 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 180 Calibration Factors + + /// Calibration Factors pub const CALFACT = mmio(Address + 0x000000b4, 32, packed struct { - CALFACT_S: u7, // bit offset: 0 desc: CALFACT_S reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, @@ -19219,7 +26305,6 @@ pub const ADC2 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CALFACT_D: u7, // bit offset: 16 desc: CALFACT_D padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -19231,21 +26316,13 @@ pub const ADC2 = extern struct { padding1: u1 = 0, }); }; + +/// Analog-to-Digital Converter pub const ADC3 = extern struct { pub const Address: u32 = 0x50000400; - // byte offset: 0 interrupt and status register + + /// interrupt and status register pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - ADRDY: u1, // bit offset: 0 desc: ADRDY - EOSMP: u1, // bit offset: 1 desc: EOSMP - EOC: u1, // bit offset: 2 desc: EOC - EOS: u1, // bit offset: 3 desc: EOS - OVR: u1, // bit offset: 4 desc: OVR - JEOC: u1, // bit offset: 5 desc: JEOC - JEOS: u1, // bit offset: 6 desc: JEOS - AWD1: u1, // bit offset: 7 desc: AWD1 - AWD2: u1, // bit offset: 8 desc: AWD2 - AWD3: u1, // bit offset: 9 desc: AWD3 - JQOVF: u1, // bit offset: 10 desc: JQOVF padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -19268,19 +26345,9 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 interrupt enable register + + /// interrupt enable register pub const IER = mmio(Address + 0x00000004, 32, packed struct { - ADRDYIE: u1, // bit offset: 0 desc: ADRDYIE - EOSMPIE: u1, // bit offset: 1 desc: EOSMPIE - EOCIE: u1, // bit offset: 2 desc: EOCIE - EOSIE: u1, // bit offset: 3 desc: EOSIE - OVRIE: u1, // bit offset: 4 desc: OVRIE - JEOCIE: u1, // bit offset: 5 desc: JEOCIE - JEOSIE: u1, // bit offset: 6 desc: JEOSIE - AWD1IE: u1, // bit offset: 7 desc: AWD1IE - AWD2IE: u1, // bit offset: 8 desc: AWD2IE - AWD3IE: u1, // bit offset: 9 desc: AWD3IE - JQOVFIE: u1, // bit offset: 10 desc: JQOVFIE padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -19303,14 +26370,9 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 control register + + /// control register pub const CR = mmio(Address + 0x00000008, 32, packed struct { - ADEN: u1, // bit offset: 0 desc: ADEN - ADDIS: u1, // bit offset: 1 desc: ADDIS - ADSTART: u1, // bit offset: 2 desc: ADSTART - JADSTART: u1, // bit offset: 3 desc: JADSTART - ADSTP: u1, // bit offset: 4 desc: ADSTP - JADSTP: u1, // bit offset: 5 desc: JADSTP reserved22: u1 = 0, reserved21: u1 = 0, reserved20: u1 = 0, @@ -19333,85 +26395,46 @@ pub const ADC3 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADVREGEN: u1, // bit offset: 28 desc: ADVREGEN - DEEPPWD: u1, // bit offset: 29 desc: DEEPPWD - ADCALDIF: u1, // bit offset: 30 desc: ADCALDIF - ADCAL: u1, // bit offset: 31 desc: ADCAL }); - // byte offset: 12 configuration register + + /// configuration register pub const CFGR = mmio(Address + 0x0000000c, 32, packed struct { - DMAEN: u1, // bit offset: 0 desc: DMAEN - DMACFG: u1, // bit offset: 1 desc: DMACFG - reserved1: u1 = 0, - RES: u2, // bit offset: 3 desc: RES - ALIGN: u1, // bit offset: 5 desc: ALIGN - EXTSEL: u4, // bit offset: 6 desc: EXTSEL - EXTEN: u2, // bit offset: 10 desc: EXTEN - OVRMOD: u1, // bit offset: 12 desc: OVRMOD - CONT: u1, // bit offset: 13 desc: CONT - AUTDLY: u1, // bit offset: 14 desc: AUTDLY - AUTOFF: u1, // bit offset: 15 desc: AUTOFF - DISCEN: u1, // bit offset: 16 desc: DISCEN - DISCNUM: u3, // bit offset: 17 desc: DISCNUM - JDISCEN: u1, // bit offset: 20 desc: JDISCEN - JQM: u1, // bit offset: 21 desc: JQM - AWD1SGL: u1, // bit offset: 22 desc: AWD1SGL - AWD1EN: u1, // bit offset: 23 desc: AWD1EN - JAWD1EN: u1, // bit offset: 24 desc: JAWD1EN - JAUTO: u1, // bit offset: 25 desc: JAUTO - AWDCH1CH: u5, // bit offset: 26 desc: AWDCH1CH - padding1: u1 = 0, - }); - // byte offset: 20 sample time register 1 + reserved1: u1 = 0, + padding1: u1 = 0, + }); + + /// sample time register 1 pub const SMPR1 = mmio(Address + 0x00000014, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - SMP1: u3, // bit offset: 3 desc: SMP1 - SMP2: u3, // bit offset: 6 desc: SMP2 - SMP3: u3, // bit offset: 9 desc: SMP3 - SMP4: u3, // bit offset: 12 desc: SMP4 - SMP5: u3, // bit offset: 15 desc: SMP5 - SMP6: u3, // bit offset: 18 desc: SMP6 - SMP7: u3, // bit offset: 21 desc: SMP7 - SMP8: u3, // bit offset: 24 desc: SMP8 - SMP9: u3, // bit offset: 27 desc: SMP9 padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 sample time register 2 + + /// sample time register 2 pub const SMPR2 = mmio(Address + 0x00000018, 32, packed struct { - SMP10: u3, // bit offset: 0 desc: SMP10 - SMP11: u3, // bit offset: 3 desc: SMP11 - SMP12: u3, // bit offset: 6 desc: SMP12 - SMP13: u3, // bit offset: 9 desc: SMP13 - SMP14: u3, // bit offset: 12 desc: SMP14 - SMP15: u3, // bit offset: 15 desc: SMP15 - SMP16: u3, // bit offset: 18 desc: SMP16 - SMP17: u3, // bit offset: 21 desc: SMP17 - SMP18: u3, // bit offset: 24 desc: SMP18 padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 watchdog threshold register 1 + + /// watchdog threshold register 1 pub const TR1 = mmio(Address + 0x00000020, 32, packed struct { - LT1: u12, // bit offset: 0 desc: LT1 reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - HT1: u12, // bit offset: 16 desc: HT1 padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 watchdog threshold register + + /// watchdog threshold register pub const TR2 = mmio(Address + 0x00000024, 32, packed struct { - LT2: u8, // bit offset: 0 desc: LT2 reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -19420,7 +26443,6 @@ pub const ADC3 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - HT2: u8, // bit offset: 16 desc: HT2 padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -19430,9 +26452,9 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 watchdog threshold register 3 + + /// watchdog threshold register 3 pub const TR3 = mmio(Address + 0x00000028, 32, packed struct { - LT3: u8, // bit offset: 0 desc: LT3 reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -19441,7 +26463,6 @@ pub const ADC3 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - HT3: u8, // bit offset: 16 desc: HT3 padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -19451,57 +26472,44 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 regular sequence register 1 + + /// regular sequence register 1 pub const SQR1 = mmio(Address + 0x00000030, 32, packed struct { - L3: u4, // bit offset: 0 desc: L3 reserved2: u1 = 0, reserved1: u1 = 0, - SQ1: u5, // bit offset: 6 desc: SQ1 reserved3: u1 = 0, - SQ2: u5, // bit offset: 12 desc: SQ2 reserved4: u1 = 0, - SQ3: u5, // bit offset: 18 desc: SQ3 reserved5: u1 = 0, - SQ4: u5, // bit offset: 24 desc: SQ4 padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 regular sequence register 2 + + /// regular sequence register 2 pub const SQR2 = mmio(Address + 0x00000034, 32, packed struct { - SQ5: u5, // bit offset: 0 desc: SQ5 reserved1: u1 = 0, - SQ6: u5, // bit offset: 6 desc: SQ6 reserved2: u1 = 0, - SQ7: u5, // bit offset: 12 desc: SQ7 reserved3: u1 = 0, - SQ8: u5, // bit offset: 18 desc: SQ8 reserved4: u1 = 0, - SQ9: u5, // bit offset: 24 desc: SQ9 padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 regular sequence register 3 + + /// regular sequence register 3 pub const SQR3 = mmio(Address + 0x00000038, 32, packed struct { - SQ10: u5, // bit offset: 0 desc: SQ10 reserved1: u1 = 0, - SQ11: u5, // bit offset: 6 desc: SQ11 reserved2: u1 = 0, - SQ12: u5, // bit offset: 12 desc: SQ12 reserved3: u1 = 0, - SQ13: u5, // bit offset: 18 desc: SQ13 reserved4: u1 = 0, - SQ14: u5, // bit offset: 24 desc: SQ14 padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 regular sequence register 4 + + /// regular sequence register 4 pub const SQR4 = mmio(Address + 0x0000003c, 32, packed struct { - SQ15: u5, // bit offset: 0 desc: SQ15 reserved1: u1 = 0, - SQ16: u5, // bit offset: 6 desc: SQ16 padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -19524,9 +26532,9 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 regular Data Register + + /// regular Data Register pub const DR = mmio(Address + 0x00000040, 32, packed struct { - regularDATA: u16, // bit offset: 0 desc: regularDATA padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -19544,23 +26552,17 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 injected sequence register + + /// injected sequence register pub const JSQR = mmio(Address + 0x0000004c, 32, packed struct { - JL: u2, // bit offset: 0 desc: JL - JEXTSEL: u4, // bit offset: 2 desc: JEXTSEL - JEXTEN: u2, // bit offset: 6 desc: JEXTEN - JSQ1: u5, // bit offset: 8 desc: JSQ1 reserved1: u1 = 0, - JSQ2: u5, // bit offset: 14 desc: JSQ2 reserved2: u1 = 0, - JSQ3: u5, // bit offset: 20 desc: JSQ3 reserved3: u1 = 0, - JSQ4: u5, // bit offset: 26 desc: JSQ4 padding1: u1 = 0, }); - // byte offset: 96 offset register 1 + + /// offset register 1 pub const OFR1 = mmio(Address + 0x00000060, 32, packed struct { - OFFSET1: u12, // bit offset: 0 desc: OFFSET1 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -19575,12 +26577,10 @@ pub const ADC3 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET1_CH: u5, // bit offset: 26 desc: OFFSET1_CH - OFFSET1_EN: u1, // bit offset: 31 desc: OFFSET1_EN }); - // byte offset: 100 offset register 2 + + /// offset register 2 pub const OFR2 = mmio(Address + 0x00000064, 32, packed struct { - OFFSET2: u12, // bit offset: 0 desc: OFFSET2 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -19595,12 +26595,10 @@ pub const ADC3 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET2_CH: u5, // bit offset: 26 desc: OFFSET2_CH - OFFSET2_EN: u1, // bit offset: 31 desc: OFFSET2_EN }); - // byte offset: 104 offset register 3 + + /// offset register 3 pub const OFR3 = mmio(Address + 0x00000068, 32, packed struct { - OFFSET3: u12, // bit offset: 0 desc: OFFSET3 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -19615,12 +26613,10 @@ pub const ADC3 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET3_CH: u5, // bit offset: 26 desc: OFFSET3_CH - OFFSET3_EN: u1, // bit offset: 31 desc: OFFSET3_EN }); - // byte offset: 108 offset register 4 + + /// offset register 4 pub const OFR4 = mmio(Address + 0x0000006c, 32, packed struct { - OFFSET4: u12, // bit offset: 0 desc: OFFSET4 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -19635,12 +26631,10 @@ pub const ADC3 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET4_CH: u5, // bit offset: 26 desc: OFFSET4_CH - OFFSET4_EN: u1, // bit offset: 31 desc: OFFSET4_EN }); - // byte offset: 128 injected data register 1 + + /// injected data register 1 pub const JDR1 = mmio(Address + 0x00000080, 32, packed struct { - JDATA1: u16, // bit offset: 0 desc: JDATA1 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -19658,9 +26652,9 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 132 injected data register 2 + + /// injected data register 2 pub const JDR2 = mmio(Address + 0x00000084, 32, packed struct { - JDATA2: u16, // bit offset: 0 desc: JDATA2 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -19678,9 +26672,9 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 136 injected data register 3 + + /// injected data register 3 pub const JDR3 = mmio(Address + 0x00000088, 32, packed struct { - JDATA3: u16, // bit offset: 0 desc: JDATA3 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -19698,9 +26692,9 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 140 injected data register 4 + + /// injected data register 4 pub const JDR4 = mmio(Address + 0x0000008c, 32, packed struct { - JDATA4: u16, // bit offset: 0 desc: JDATA4 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -19718,10 +26712,10 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 160 Analog Watchdog 2 Configuration Register + + /// Analog Watchdog 2 Configuration Register pub const AWD2CR = mmio(Address + 0x000000a0, 32, packed struct { reserved1: u1 = 0, - AWD2CH: u18, // bit offset: 1 desc: AWD2CH padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -19736,10 +26730,10 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 164 Analog Watchdog 3 Configuration Register + + /// Analog Watchdog 3 Configuration Register pub const AWD3CR = mmio(Address + 0x000000a4, 32, packed struct { reserved1: u1 = 0, - AWD3CH: u18, // bit offset: 1 desc: AWD3CH padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -19754,11 +26748,14 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 176 Differential Mode Selection Register 2 + + /// Differential Mode Selection Register 2 pub const DIFSEL = mmio(Address + 0x000000b0, 32, packed struct { reserved1: u1 = 0, - DIFSEL_1_15: u15, // bit offset: 1 desc: Differential mode for channels 15 to 1 - DIFSEL_16_18: u3, // bit offset: 16 desc: Differential mode for channels 18 to 16 + /// Differential mode for channels 15 to 1 + DIFSEL_1_15: u15 = 0, + /// Differential mode for channels 18 to 16 + DIFSEL_16_18: u3 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -19773,9 +26770,9 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 180 Calibration Factors + + /// Calibration Factors pub const CALFACT = mmio(Address + 0x000000b4, 32, packed struct { - CALFACT_S: u7, // bit offset: 0 desc: CALFACT_S reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, @@ -19785,7 +26782,6 @@ pub const ADC3 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CALFACT_D: u7, // bit offset: 16 desc: CALFACT_D padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -19797,21 +26793,13 @@ pub const ADC3 = extern struct { padding1: u1 = 0, }); }; + +/// Analog-to-Digital Converter pub const ADC4 = extern struct { pub const Address: u32 = 0x50000500; - // byte offset: 0 interrupt and status register + + /// interrupt and status register pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - ADRDY: u1, // bit offset: 0 desc: ADRDY - EOSMP: u1, // bit offset: 1 desc: EOSMP - EOC: u1, // bit offset: 2 desc: EOC - EOS: u1, // bit offset: 3 desc: EOS - OVR: u1, // bit offset: 4 desc: OVR - JEOC: u1, // bit offset: 5 desc: JEOC - JEOS: u1, // bit offset: 6 desc: JEOS - AWD1: u1, // bit offset: 7 desc: AWD1 - AWD2: u1, // bit offset: 8 desc: AWD2 - AWD3: u1, // bit offset: 9 desc: AWD3 - JQOVF: u1, // bit offset: 10 desc: JQOVF padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -19834,19 +26822,9 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 interrupt enable register + + /// interrupt enable register pub const IER = mmio(Address + 0x00000004, 32, packed struct { - ADRDYIE: u1, // bit offset: 0 desc: ADRDYIE - EOSMPIE: u1, // bit offset: 1 desc: EOSMPIE - EOCIE: u1, // bit offset: 2 desc: EOCIE - EOSIE: u1, // bit offset: 3 desc: EOSIE - OVRIE: u1, // bit offset: 4 desc: OVRIE - JEOCIE: u1, // bit offset: 5 desc: JEOCIE - JEOSIE: u1, // bit offset: 6 desc: JEOSIE - AWD1IE: u1, // bit offset: 7 desc: AWD1IE - AWD2IE: u1, // bit offset: 8 desc: AWD2IE - AWD3IE: u1, // bit offset: 9 desc: AWD3IE - JQOVFIE: u1, // bit offset: 10 desc: JQOVFIE padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -19869,14 +26847,9 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 control register + + /// control register pub const CR = mmio(Address + 0x00000008, 32, packed struct { - ADEN: u1, // bit offset: 0 desc: ADEN - ADDIS: u1, // bit offset: 1 desc: ADDIS - ADSTART: u1, // bit offset: 2 desc: ADSTART - JADSTART: u1, // bit offset: 3 desc: JADSTART - ADSTP: u1, // bit offset: 4 desc: ADSTP - JADSTP: u1, // bit offset: 5 desc: JADSTP reserved22: u1 = 0, reserved21: u1 = 0, reserved20: u1 = 0, @@ -19899,85 +26872,46 @@ pub const ADC4 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADVREGEN: u1, // bit offset: 28 desc: ADVREGEN - DEEPPWD: u1, // bit offset: 29 desc: DEEPPWD - ADCALDIF: u1, // bit offset: 30 desc: ADCALDIF - ADCAL: u1, // bit offset: 31 desc: ADCAL }); - // byte offset: 12 configuration register + + /// configuration register pub const CFGR = mmio(Address + 0x0000000c, 32, packed struct { - DMAEN: u1, // bit offset: 0 desc: DMAEN - DMACFG: u1, // bit offset: 1 desc: DMACFG - reserved1: u1 = 0, - RES: u2, // bit offset: 3 desc: RES - ALIGN: u1, // bit offset: 5 desc: ALIGN - EXTSEL: u4, // bit offset: 6 desc: EXTSEL - EXTEN: u2, // bit offset: 10 desc: EXTEN - OVRMOD: u1, // bit offset: 12 desc: OVRMOD - CONT: u1, // bit offset: 13 desc: CONT - AUTDLY: u1, // bit offset: 14 desc: AUTDLY - AUTOFF: u1, // bit offset: 15 desc: AUTOFF - DISCEN: u1, // bit offset: 16 desc: DISCEN - DISCNUM: u3, // bit offset: 17 desc: DISCNUM - JDISCEN: u1, // bit offset: 20 desc: JDISCEN - JQM: u1, // bit offset: 21 desc: JQM - AWD1SGL: u1, // bit offset: 22 desc: AWD1SGL - AWD1EN: u1, // bit offset: 23 desc: AWD1EN - JAWD1EN: u1, // bit offset: 24 desc: JAWD1EN - JAUTO: u1, // bit offset: 25 desc: JAUTO - AWDCH1CH: u5, // bit offset: 26 desc: AWDCH1CH - padding1: u1 = 0, - }); - // byte offset: 20 sample time register 1 + reserved1: u1 = 0, + padding1: u1 = 0, + }); + + /// sample time register 1 pub const SMPR1 = mmio(Address + 0x00000014, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - SMP1: u3, // bit offset: 3 desc: SMP1 - SMP2: u3, // bit offset: 6 desc: SMP2 - SMP3: u3, // bit offset: 9 desc: SMP3 - SMP4: u3, // bit offset: 12 desc: SMP4 - SMP5: u3, // bit offset: 15 desc: SMP5 - SMP6: u3, // bit offset: 18 desc: SMP6 - SMP7: u3, // bit offset: 21 desc: SMP7 - SMP8: u3, // bit offset: 24 desc: SMP8 - SMP9: u3, // bit offset: 27 desc: SMP9 padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 sample time register 2 + + /// sample time register 2 pub const SMPR2 = mmio(Address + 0x00000018, 32, packed struct { - SMP10: u3, // bit offset: 0 desc: SMP10 - SMP11: u3, // bit offset: 3 desc: SMP11 - SMP12: u3, // bit offset: 6 desc: SMP12 - SMP13: u3, // bit offset: 9 desc: SMP13 - SMP14: u3, // bit offset: 12 desc: SMP14 - SMP15: u3, // bit offset: 15 desc: SMP15 - SMP16: u3, // bit offset: 18 desc: SMP16 - SMP17: u3, // bit offset: 21 desc: SMP17 - SMP18: u3, // bit offset: 24 desc: SMP18 padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 watchdog threshold register 1 + + /// watchdog threshold register 1 pub const TR1 = mmio(Address + 0x00000020, 32, packed struct { - LT1: u12, // bit offset: 0 desc: LT1 reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - HT1: u12, // bit offset: 16 desc: HT1 padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 watchdog threshold register + + /// watchdog threshold register pub const TR2 = mmio(Address + 0x00000024, 32, packed struct { - LT2: u8, // bit offset: 0 desc: LT2 reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -19986,7 +26920,6 @@ pub const ADC4 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - HT2: u8, // bit offset: 16 desc: HT2 padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -19996,9 +26929,9 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 watchdog threshold register 3 + + /// watchdog threshold register 3 pub const TR3 = mmio(Address + 0x00000028, 32, packed struct { - LT3: u8, // bit offset: 0 desc: LT3 reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -20007,7 +26940,6 @@ pub const ADC4 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - HT3: u8, // bit offset: 16 desc: HT3 padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -20017,57 +26949,44 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 regular sequence register 1 + + /// regular sequence register 1 pub const SQR1 = mmio(Address + 0x00000030, 32, packed struct { - L3: u4, // bit offset: 0 desc: L3 reserved2: u1 = 0, reserved1: u1 = 0, - SQ1: u5, // bit offset: 6 desc: SQ1 reserved3: u1 = 0, - SQ2: u5, // bit offset: 12 desc: SQ2 reserved4: u1 = 0, - SQ3: u5, // bit offset: 18 desc: SQ3 reserved5: u1 = 0, - SQ4: u5, // bit offset: 24 desc: SQ4 padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 regular sequence register 2 + + /// regular sequence register 2 pub const SQR2 = mmio(Address + 0x00000034, 32, packed struct { - SQ5: u5, // bit offset: 0 desc: SQ5 reserved1: u1 = 0, - SQ6: u5, // bit offset: 6 desc: SQ6 reserved2: u1 = 0, - SQ7: u5, // bit offset: 12 desc: SQ7 reserved3: u1 = 0, - SQ8: u5, // bit offset: 18 desc: SQ8 reserved4: u1 = 0, - SQ9: u5, // bit offset: 24 desc: SQ9 padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 regular sequence register 3 + + /// regular sequence register 3 pub const SQR3 = mmio(Address + 0x00000038, 32, packed struct { - SQ10: u5, // bit offset: 0 desc: SQ10 reserved1: u1 = 0, - SQ11: u5, // bit offset: 6 desc: SQ11 reserved2: u1 = 0, - SQ12: u5, // bit offset: 12 desc: SQ12 reserved3: u1 = 0, - SQ13: u5, // bit offset: 18 desc: SQ13 reserved4: u1 = 0, - SQ14: u5, // bit offset: 24 desc: SQ14 padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 regular sequence register 4 + + /// regular sequence register 4 pub const SQR4 = mmio(Address + 0x0000003c, 32, packed struct { - SQ15: u5, // bit offset: 0 desc: SQ15 reserved1: u1 = 0, - SQ16: u5, // bit offset: 6 desc: SQ16 padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -20090,9 +27009,9 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 regular Data Register + + /// regular Data Register pub const DR = mmio(Address + 0x00000040, 32, packed struct { - regularDATA: u16, // bit offset: 0 desc: regularDATA padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -20110,23 +27029,17 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 injected sequence register + + /// injected sequence register pub const JSQR = mmio(Address + 0x0000004c, 32, packed struct { - JL: u2, // bit offset: 0 desc: JL - JEXTSEL: u4, // bit offset: 2 desc: JEXTSEL - JEXTEN: u2, // bit offset: 6 desc: JEXTEN - JSQ1: u5, // bit offset: 8 desc: JSQ1 reserved1: u1 = 0, - JSQ2: u5, // bit offset: 14 desc: JSQ2 reserved2: u1 = 0, - JSQ3: u5, // bit offset: 20 desc: JSQ3 reserved3: u1 = 0, - JSQ4: u5, // bit offset: 26 desc: JSQ4 padding1: u1 = 0, }); - // byte offset: 96 offset register 1 + + /// offset register 1 pub const OFR1 = mmio(Address + 0x00000060, 32, packed struct { - OFFSET1: u12, // bit offset: 0 desc: OFFSET1 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -20141,12 +27054,10 @@ pub const ADC4 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET1_CH: u5, // bit offset: 26 desc: OFFSET1_CH - OFFSET1_EN: u1, // bit offset: 31 desc: OFFSET1_EN }); - // byte offset: 100 offset register 2 + + /// offset register 2 pub const OFR2 = mmio(Address + 0x00000064, 32, packed struct { - OFFSET2: u12, // bit offset: 0 desc: OFFSET2 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -20161,12 +27072,10 @@ pub const ADC4 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET2_CH: u5, // bit offset: 26 desc: OFFSET2_CH - OFFSET2_EN: u1, // bit offset: 31 desc: OFFSET2_EN }); - // byte offset: 104 offset register 3 + + /// offset register 3 pub const OFR3 = mmio(Address + 0x00000068, 32, packed struct { - OFFSET3: u12, // bit offset: 0 desc: OFFSET3 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -20181,12 +27090,10 @@ pub const ADC4 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET3_CH: u5, // bit offset: 26 desc: OFFSET3_CH - OFFSET3_EN: u1, // bit offset: 31 desc: OFFSET3_EN }); - // byte offset: 108 offset register 4 + + /// offset register 4 pub const OFR4 = mmio(Address + 0x0000006c, 32, packed struct { - OFFSET4: u12, // bit offset: 0 desc: OFFSET4 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -20201,12 +27108,10 @@ pub const ADC4 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET4_CH: u5, // bit offset: 26 desc: OFFSET4_CH - OFFSET4_EN: u1, // bit offset: 31 desc: OFFSET4_EN }); - // byte offset: 128 injected data register 1 + + /// injected data register 1 pub const JDR1 = mmio(Address + 0x00000080, 32, packed struct { - JDATA1: u16, // bit offset: 0 desc: JDATA1 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -20224,9 +27129,9 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 132 injected data register 2 + + /// injected data register 2 pub const JDR2 = mmio(Address + 0x00000084, 32, packed struct { - JDATA2: u16, // bit offset: 0 desc: JDATA2 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -20244,9 +27149,9 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 136 injected data register 3 + + /// injected data register 3 pub const JDR3 = mmio(Address + 0x00000088, 32, packed struct { - JDATA3: u16, // bit offset: 0 desc: JDATA3 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -20264,9 +27169,9 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 140 injected data register 4 + + /// injected data register 4 pub const JDR4 = mmio(Address + 0x0000008c, 32, packed struct { - JDATA4: u16, // bit offset: 0 desc: JDATA4 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -20284,10 +27189,10 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 160 Analog Watchdog 2 Configuration Register + + /// Analog Watchdog 2 Configuration Register pub const AWD2CR = mmio(Address + 0x000000a0, 32, packed struct { reserved1: u1 = 0, - AWD2CH: u18, // bit offset: 1 desc: AWD2CH padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -20302,10 +27207,10 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 164 Analog Watchdog 3 Configuration Register + + /// Analog Watchdog 3 Configuration Register pub const AWD3CR = mmio(Address + 0x000000a4, 32, packed struct { reserved1: u1 = 0, - AWD3CH: u18, // bit offset: 1 desc: AWD3CH padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -20320,11 +27225,14 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 176 Differential Mode Selection Register 2 + + /// Differential Mode Selection Register 2 pub const DIFSEL = mmio(Address + 0x000000b0, 32, packed struct { reserved1: u1 = 0, - DIFSEL_1_15: u15, // bit offset: 1 desc: Differential mode for channels 15 to 1 - DIFSEL_16_18: u3, // bit offset: 16 desc: Differential mode for channels 18 to 16 + /// Differential mode for channels 15 to 1 + DIFSEL_1_15: u15 = 0, + /// Differential mode for channels 18 to 16 + DIFSEL_16_18: u3 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -20339,9 +27247,9 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 180 Calibration Factors + + /// Calibration Factors pub const CALFACT = mmio(Address + 0x000000b4, 32, packed struct { - CALFACT_S: u7, // bit offset: 0 desc: CALFACT_S reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, @@ -20351,7 +27259,6 @@ pub const ADC4 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CALFACT_D: u7, // bit offset: 16 desc: CALFACT_D padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -20363,61 +27270,69 @@ pub const ADC4 = extern struct { padding1: u1 = 0, }); }; + +/// Analog-to-Digital Converter pub const ADC1_2 = extern struct { pub const Address: u32 = 0x50000300; - // byte offset: 0 ADC Common status register + + /// ADC Common status register pub const CSR = mmio(Address + 0x00000000, 32, packed struct { - ADDRDY_MST: u1, // bit offset: 0 desc: ADDRDY_MST - EOSMP_MST: u1, // bit offset: 1 desc: EOSMP_MST - EOC_MST: u1, // bit offset: 2 desc: EOC_MST - EOS_MST: u1, // bit offset: 3 desc: EOS_MST - OVR_MST: u1, // bit offset: 4 desc: OVR_MST - JEOC_MST: u1, // bit offset: 5 desc: JEOC_MST - JEOS_MST: u1, // bit offset: 6 desc: JEOS_MST - AWD1_MST: u1, // bit offset: 7 desc: AWD1_MST - AWD2_MST: u1, // bit offset: 8 desc: AWD2_MST - AWD3_MST: u1, // bit offset: 9 desc: AWD3_MST - JQOVF_MST: u1, // bit offset: 10 desc: JQOVF_MST reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADRDY_SLV: u1, // bit offset: 16 desc: ADRDY_SLV - EOSMP_SLV: u1, // bit offset: 17 desc: EOSMP_SLV - EOC_SLV: u1, // bit offset: 18 desc: End of regular conversion of the slave ADC - EOS_SLV: u1, // bit offset: 19 desc: End of regular sequence flag of the slave ADC - OVR_SLV: u1, // bit offset: 20 desc: Overrun flag of the slave ADC - JEOC_SLV: u1, // bit offset: 21 desc: End of injected conversion flag of the slave ADC - JEOS_SLV: u1, // bit offset: 22 desc: End of injected sequence flag of the slave ADC - AWD1_SLV: u1, // bit offset: 23 desc: Analog watchdog 1 flag of the slave ADC - AWD2_SLV: u1, // bit offset: 24 desc: Analog watchdog 2 flag of the slave ADC - AWD3_SLV: u1, // bit offset: 25 desc: Analog watchdog 3 flag of the slave ADC - JQOVF_SLV: u1, // bit offset: 26 desc: Injected Context Queue Overflow flag of the slave ADC + /// End of regular conversion of the slave ADC + EOC_SLV: u1 = 0, + /// End of regular sequence flag of the slave ADC + EOS_SLV: u1 = 0, + /// Overrun flag of the slave ADC + OVR_SLV: u1 = 0, + /// End of injected conversion flag of the slave ADC + JEOC_SLV: u1 = 0, + /// End of injected sequence flag of the slave ADC + JEOS_SLV: u1 = 0, + /// Analog watchdog 1 flag of the slave ADC + AWD1_SLV: u1 = 0, + /// Analog watchdog 2 flag of the slave ADC + AWD2_SLV: u1 = 0, + /// Analog watchdog 3 flag of the slave ADC + AWD3_SLV: u1 = 0, + /// Injected Context Queue Overflow flag of the slave ADC + JQOVF_SLV: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 ADC common control register + + /// ADC common control register pub const CCR = mmio(Address + 0x00000008, 32, packed struct { - MULT: u5, // bit offset: 0 desc: Multi ADC mode selection + /// Multi ADC mode selection + MULT: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DELAY: u4, // bit offset: 8 desc: Delay between 2 sampling phases + /// Delay between 2 sampling phases + DELAY: u4 = 0, reserved4: u1 = 0, - DMACFG: u1, // bit offset: 13 desc: DMA configuration (for multi-ADC mode) - MDMA: u2, // bit offset: 14 desc: Direct memory access mode for multi ADC mode - CKMODE: u2, // bit offset: 16 desc: ADC clock mode + /// DMA configuration (for multi-ADC mode) + DMACFG: u1 = 0, + /// Direct memory access mode for multi ADC mode + MDMA: u2 = 0, + /// ADC clock mode + CKMODE: u2 = 0, reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - VREFEN: u1, // bit offset: 22 desc: VREFINT enable - TSEN: u1, // bit offset: 23 desc: Temperature sensor enable - VBATEN: u1, // bit offset: 24 desc: VBAT enable + /// VREFINT enable + VREFEN: u1 = 0, + /// Temperature sensor enable + TSEN: u1 = 0, + /// VBAT enable + VBATEN: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -20426,67 +27341,78 @@ pub const ADC1_2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 ADC common regular data register for dual and triple modes + + /// ADC common regular data register for dual and triple modes pub const CDR = mmio(Address + 0x0000000c, 32, packed struct { - RDATA_MST: u16, // bit offset: 0 desc: Regular data of the master ADC - RDATA_SLV: u16, // bit offset: 16 desc: Regular data of the slave ADC + /// Regular data of the master ADC + RDATA_MST: u16 = 0, + /// Regular data of the slave ADC + RDATA_SLV: u16 = 0, }); }; + +/// Analog-to-Digital Converter pub const ADC3_4 = extern struct { pub const Address: u32 = 0x50000700; - // byte offset: 0 ADC Common status register + + /// ADC Common status register pub const CSR = mmio(Address + 0x00000000, 32, packed struct { - ADDRDY_MST: u1, // bit offset: 0 desc: ADDRDY_MST - EOSMP_MST: u1, // bit offset: 1 desc: EOSMP_MST - EOC_MST: u1, // bit offset: 2 desc: EOC_MST - EOS_MST: u1, // bit offset: 3 desc: EOS_MST - OVR_MST: u1, // bit offset: 4 desc: OVR_MST - JEOC_MST: u1, // bit offset: 5 desc: JEOC_MST - JEOS_MST: u1, // bit offset: 6 desc: JEOS_MST - AWD1_MST: u1, // bit offset: 7 desc: AWD1_MST - AWD2_MST: u1, // bit offset: 8 desc: AWD2_MST - AWD3_MST: u1, // bit offset: 9 desc: AWD3_MST - JQOVF_MST: u1, // bit offset: 10 desc: JQOVF_MST reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADRDY_SLV: u1, // bit offset: 16 desc: ADRDY_SLV - EOSMP_SLV: u1, // bit offset: 17 desc: EOSMP_SLV - EOC_SLV: u1, // bit offset: 18 desc: End of regular conversion of the slave ADC - EOS_SLV: u1, // bit offset: 19 desc: End of regular sequence flag of the slave ADC - OVR_SLV: u1, // bit offset: 20 desc: Overrun flag of the slave ADC - JEOC_SLV: u1, // bit offset: 21 desc: End of injected conversion flag of the slave ADC - JEOS_SLV: u1, // bit offset: 22 desc: End of injected sequence flag of the slave ADC - AWD1_SLV: u1, // bit offset: 23 desc: Analog watchdog 1 flag of the slave ADC - AWD2_SLV: u1, // bit offset: 24 desc: Analog watchdog 2 flag of the slave ADC - AWD3_SLV: u1, // bit offset: 25 desc: Analog watchdog 3 flag of the slave ADC - JQOVF_SLV: u1, // bit offset: 26 desc: Injected Context Queue Overflow flag of the slave ADC + /// End of regular conversion of the slave ADC + EOC_SLV: u1 = 0, + /// End of regular sequence flag of the slave ADC + EOS_SLV: u1 = 0, + /// Overrun flag of the slave ADC + OVR_SLV: u1 = 0, + /// End of injected conversion flag of the slave ADC + JEOC_SLV: u1 = 0, + /// End of injected sequence flag of the slave ADC + JEOS_SLV: u1 = 0, + /// Analog watchdog 1 flag of the slave ADC + AWD1_SLV: u1 = 0, + /// Analog watchdog 2 flag of the slave ADC + AWD2_SLV: u1 = 0, + /// Analog watchdog 3 flag of the slave ADC + AWD3_SLV: u1 = 0, + /// Injected Context Queue Overflow flag of the slave ADC + JQOVF_SLV: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 ADC common control register + + /// ADC common control register pub const CCR = mmio(Address + 0x00000008, 32, packed struct { - MULT: u5, // bit offset: 0 desc: Multi ADC mode selection + /// Multi ADC mode selection + MULT: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DELAY: u4, // bit offset: 8 desc: Delay between 2 sampling phases + /// Delay between 2 sampling phases + DELAY: u4 = 0, reserved4: u1 = 0, - DMACFG: u1, // bit offset: 13 desc: DMA configuration (for multi-ADC mode) - MDMA: u2, // bit offset: 14 desc: Direct memory access mode for multi ADC mode - CKMODE: u2, // bit offset: 16 desc: ADC clock mode + /// DMA configuration (for multi-ADC mode) + DMACFG: u1 = 0, + /// Direct memory access mode for multi ADC mode + MDMA: u2 = 0, + /// ADC clock mode + CKMODE: u2 = 0, reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - VREFEN: u1, // bit offset: 22 desc: VREFINT enable - TSEN: u1, // bit offset: 23 desc: Temperature sensor enable - VBATEN: u1, // bit offset: 24 desc: VBAT enable + /// VREFINT enable + VREFEN: u1 = 0, + /// Temperature sensor enable + TSEN: u1 = 0, + /// VBAT enable + VBATEN: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -20495,52 +27421,84 @@ pub const ADC3_4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 ADC common regular data register for dual and triple modes + + /// ADC common regular data register for dual and triple modes pub const CDR = mmio(Address + 0x0000000c, 32, packed struct { - RDATA_MST: u16, // bit offset: 0 desc: Regular data of the master ADC - RDATA_SLV: u16, // bit offset: 16 desc: Regular data of the slave ADC + /// Regular data of the master ADC + RDATA_MST: u16 = 0, + /// Regular data of the slave ADC + RDATA_SLV: u16 = 0, }); }; + +/// System configuration controller _Comparator and Operational amplifier pub const SYSCFG_COMP_OPAMP = extern struct { pub const Address: u32 = 0x40010000; - // byte offset: 0 configuration register 1 + + /// configuration register 1 pub const SYSCFG_CFGR1 = mmio(Address + 0x00000000, 32, packed struct { - MEM_MODE: u2, // bit offset: 0 desc: Memory mapping selection bits + /// Memory mapping selection bits + MEM_MODE: u2 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - USB_IT_RMP: u1, // bit offset: 5 desc: USB interrupt remap - TIM1_ITR_RMP: u1, // bit offset: 6 desc: Timer 1 ITR3 selection - DAC_TRIG_RMP: u1, // bit offset: 7 desc: DAC trigger remap (when TSEL = 001) - ADC24_DMA_RMP: u1, // bit offset: 8 desc: ADC24 DMA remapping bit + /// USB interrupt remap + USB_IT_RMP: u1 = 0, + /// Timer 1 ITR3 selection + TIM1_ITR_RMP: u1 = 0, + /// DAC trigger remap (when TSEL = 001) + DAC_TRIG_RMP: u1 = 0, + /// ADC24 DMA remapping bit + ADC24_DMA_RMP: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - TIM16_DMA_RMP: u1, // bit offset: 11 desc: TIM16 DMA request remapping bit - TIM17_DMA_RMP: u1, // bit offset: 12 desc: TIM17 DMA request remapping bit - TIM6_DAC1_DMA_RMP: u1, // bit offset: 13 desc: TIM6 and DAC1 DMA request remapping bit - TIM7_DAC2_DMA_RMP: u1, // bit offset: 14 desc: TIM7 and DAC2 DMA request remapping bit + /// TIM16 DMA request remapping bit + TIM16_DMA_RMP: u1 = 0, + /// TIM17 DMA request remapping bit + TIM17_DMA_RMP: u1 = 0, + /// TIM6 and DAC1 DMA request remapping bit + TIM6_DAC1_DMA_RMP: u1 = 0, + /// TIM7 and DAC2 DMA request remapping bit + TIM7_DAC2_DMA_RMP: u1 = 0, reserved6: u1 = 0, - I2C_PB6_FM: u1, // bit offset: 16 desc: Fast Mode Plus (FM+) driving capability activation bits. - I2C_PB7_FM: u1, // bit offset: 17 desc: Fast Mode Plus (FM+) driving capability activation bits. - I2C_PB8_FM: u1, // bit offset: 18 desc: Fast Mode Plus (FM+) driving capability activation bits. - I2C_PB9_FM: u1, // bit offset: 19 desc: Fast Mode Plus (FM+) driving capability activation bits. - I2C1_FM: u1, // bit offset: 20 desc: I2C1 Fast Mode Plus - I2C2_FM: u1, // bit offset: 21 desc: I2C2 Fast Mode Plus - ENCODER_MODE: u2, // bit offset: 22 desc: Encoder mode + /// Fast Mode Plus (FM+) driving capability activation bits. + I2C_PB6_FM: u1 = 0, + /// Fast Mode Plus (FM+) driving capability activation bits. + I2C_PB7_FM: u1 = 0, + /// Fast Mode Plus (FM+) driving capability activation bits. + I2C_PB8_FM: u1 = 0, + /// Fast Mode Plus (FM+) driving capability activation bits. + I2C_PB9_FM: u1 = 0, + /// I2C1 Fast Mode Plus + I2C1_FM: u1 = 0, + /// I2C2 Fast Mode Plus + I2C2_FM: u1 = 0, + /// Encoder mode + ENCODER_MODE: u2 = 0, reserved8: u1 = 0, reserved7: u1 = 0, - FPU_IT: u6, // bit offset: 26 desc: Interrupt enable bits from FPU + /// Interrupt enable bits from FPU + FPU_IT: u6 = 0, }); - // byte offset: 4 CCM SRAM protection register + + /// CCM SRAM protection register pub const SYSCFG_RCR = mmio(Address + 0x00000004, 32, packed struct { - PAGE0_WP: u1, // bit offset: 0 desc: CCM SRAM page write protection bit - PAGE1_WP: u1, // bit offset: 1 desc: CCM SRAM page write protection bit - PAGE2_WP: u1, // bit offset: 2 desc: CCM SRAM page write protection bit - PAGE3_WP: u1, // bit offset: 3 desc: CCM SRAM page write protection bit - PAGE4_WP: u1, // bit offset: 4 desc: CCM SRAM page write protection bit - PAGE5_WP: u1, // bit offset: 5 desc: CCM SRAM page write protection bit - PAGE6_WP: u1, // bit offset: 6 desc: CCM SRAM page write protection bit - PAGE7_WP: u1, // bit offset: 7 desc: CCM SRAM page write protection bit + /// CCM SRAM page write protection bit + PAGE0_WP: u1 = 0, + /// CCM SRAM page write protection bit + PAGE1_WP: u1 = 0, + /// CCM SRAM page write protection bit + PAGE2_WP: u1 = 0, + /// CCM SRAM page write protection bit + PAGE3_WP: u1 = 0, + /// CCM SRAM page write protection bit + PAGE4_WP: u1 = 0, + /// CCM SRAM page write protection bit + PAGE5_WP: u1 = 0, + /// CCM SRAM page write protection bit + PAGE6_WP: u1 = 0, + /// CCM SRAM page write protection bit + PAGE7_WP: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -20566,12 +27524,17 @@ pub const SYSCFG_COMP_OPAMP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 external interrupt configuration register 1 + + /// external interrupt configuration register 1 pub const SYSCFG_EXTICR1 = mmio(Address + 0x00000008, 32, packed struct { - EXTI0: u4, // bit offset: 0 desc: EXTI 0 configuration bits - EXTI1: u4, // bit offset: 4 desc: EXTI 1 configuration bits - EXTI2: u4, // bit offset: 8 desc: EXTI 2 configuration bits - EXTI3: u4, // bit offset: 12 desc: EXTI 3 configuration bits + /// EXTI 0 configuration bits + EXTI0: u4 = 0, + /// EXTI 1 configuration bits + EXTI1: u4 = 0, + /// EXTI 2 configuration bits + EXTI2: u4 = 0, + /// EXTI 3 configuration bits + EXTI3: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -20589,12 +27552,17 @@ pub const SYSCFG_COMP_OPAMP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 external interrupt configuration register 2 + + /// external interrupt configuration register 2 pub const SYSCFG_EXTICR2 = mmio(Address + 0x0000000c, 32, packed struct { - EXTI4: u4, // bit offset: 0 desc: EXTI 4 configuration bits - EXTI5: u4, // bit offset: 4 desc: EXTI 5 configuration bits - EXTI6: u4, // bit offset: 8 desc: EXTI 6 configuration bits - EXTI7: u4, // bit offset: 12 desc: EXTI 7 configuration bits + /// EXTI 4 configuration bits + EXTI4: u4 = 0, + /// EXTI 5 configuration bits + EXTI5: u4 = 0, + /// EXTI 6 configuration bits + EXTI6: u4 = 0, + /// EXTI 7 configuration bits + EXTI7: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -20612,12 +27580,17 @@ pub const SYSCFG_COMP_OPAMP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 external interrupt configuration register 3 + + /// external interrupt configuration register 3 pub const SYSCFG_EXTICR3 = mmio(Address + 0x00000010, 32, packed struct { - EXTI8: u4, // bit offset: 0 desc: EXTI 8 configuration bits - EXTI9: u4, // bit offset: 4 desc: EXTI 9 configuration bits - EXTI10: u4, // bit offset: 8 desc: EXTI 10 configuration bits - EXTI11: u4, // bit offset: 12 desc: EXTI 11 configuration bits + /// EXTI 8 configuration bits + EXTI8: u4 = 0, + /// EXTI 9 configuration bits + EXTI9: u4 = 0, + /// EXTI 10 configuration bits + EXTI10: u4 = 0, + /// EXTI 11 configuration bits + EXTI11: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -20635,12 +27608,17 @@ pub const SYSCFG_COMP_OPAMP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 external interrupt configuration register 4 + + /// external interrupt configuration register 4 pub const SYSCFG_EXTICR4 = mmio(Address + 0x00000014, 32, packed struct { - EXTI12: u4, // bit offset: 0 desc: EXTI 12 configuration bits - EXTI13: u4, // bit offset: 4 desc: EXTI 13 configuration bits - EXTI14: u4, // bit offset: 8 desc: EXTI 14 configuration bits - EXTI15: u4, // bit offset: 12 desc: EXTI 15 configuration bits + /// EXTI 12 configuration bits + EXTI12: u4 = 0, + /// EXTI 13 configuration bits + EXTI13: u4 = 0, + /// EXTI 14 configuration bits + EXTI14: u4 = 0, + /// EXTI 15 configuration bits + EXTI15: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -20658,17 +27636,23 @@ pub const SYSCFG_COMP_OPAMP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 configuration register 2 + + /// configuration register 2 pub const SYSCFG_CFGR2 = mmio(Address + 0x00000018, 32, packed struct { - LOCUP_LOCK: u1, // bit offset: 0 desc: Cortex-M0 LOCKUP bit enable bit - SRAM_PARITY_LOCK: u1, // bit offset: 1 desc: SRAM parity lock bit - PVD_LOCK: u1, // bit offset: 2 desc: PVD lock enable bit - reserved1: u1 = 0, - BYP_ADD_PAR: u1, // bit offset: 4 desc: Bypass address bit 29 in parity calculation + /// Cortex-M0 LOCKUP bit enable bit + LOCUP_LOCK: u1 = 0, + /// SRAM parity lock bit + SRAM_PARITY_LOCK: u1 = 0, + /// PVD lock enable bit + PVD_LOCK: u1 = 0, + reserved1: u1 = 0, + /// Bypass address bit 29 in parity calculation + BYP_ADD_PAR: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - SRAM_PEF: u1, // bit offset: 8 desc: SRAM parity flag + /// SRAM parity flag + SRAM_PEF: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -20693,20 +27677,27 @@ pub const SYSCFG_COMP_OPAMP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 control and status register + + /// control and status register pub const COMP1_CSR = mmio(Address + 0x0000001c, 32, packed struct { - COMP1EN: u1, // bit offset: 0 desc: Comparator 1 enable - COMP1_INP_DAC: u1, // bit offset: 1 desc: COMP1_INP_DAC - COMP1MODE: u2, // bit offset: 2 desc: Comparator 1 mode - COMP1INSEL: u3, // bit offset: 4 desc: Comparator 1 inverting input selection + /// Comparator 1 enable + COMP1EN: u1 = 0, + /// Comparator 1 mode + COMP1MODE: u2 = 0, + /// Comparator 1 inverting input selection + COMP1INSEL: u3 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - COMP1_OUT_SEL: u4, // bit offset: 10 desc: Comparator 1 output selection + /// Comparator 1 output selection + COMP1_OUT_SEL: u4 = 0, reserved4: u1 = 0, - COMP1POL: u1, // bit offset: 15 desc: Comparator 1 output polarity - COMP1HYST: u2, // bit offset: 16 desc: Comparator 1 hysteresis - COMP1_BLANKING: u3, // bit offset: 18 desc: Comparator 1 blanking source + /// Comparator 1 output polarity + COMP1POL: u1 = 0, + /// Comparator 1 hysteresis + COMP1HYST: u2 = 0, + /// Comparator 1 blanking source + COMP1_BLANKING: u3 = 0, reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, @@ -20716,23 +27707,35 @@ pub const SYSCFG_COMP_OPAMP = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - COMP1OUT: u1, // bit offset: 30 desc: Comparator 1 output - COMP1LOCK: u1, // bit offset: 31 desc: Comparator 1 lock + /// Comparator 1 output + COMP1OUT: u1 = 0, + /// Comparator 1 lock + COMP1LOCK: u1 = 0, }); - // byte offset: 32 control and status register + + /// control and status register pub const COMP2_CSR = mmio(Address + 0x00000020, 32, packed struct { - COMP2EN: u1, // bit offset: 0 desc: Comparator 2 enable - reserved1: u1 = 0, - COMP2MODE: u2, // bit offset: 2 desc: Comparator 2 mode - COMP2INSEL: u3, // bit offset: 4 desc: Comparator 2 inverting input selection - COMP2INPSEL: u1, // bit offset: 7 desc: Comparator 2 non inverted input selection - reserved2: u1 = 0, - COMP2INMSEL: u1, // bit offset: 9 desc: Comparator 1inverting input selection - COMP2_OUT_SEL: u4, // bit offset: 10 desc: Comparator 2 output selection + /// Comparator 2 enable + COMP2EN: u1 = 0, + reserved1: u1 = 0, + /// Comparator 2 mode + COMP2MODE: u2 = 0, + /// Comparator 2 inverting input selection + COMP2INSEL: u3 = 0, + /// Comparator 2 non inverted input selection + COMP2INPSEL: u1 = 0, + reserved2: u1 = 0, + /// Comparator 1inverting input selection + COMP2INMSEL: u1 = 0, + /// Comparator 2 output selection + COMP2_OUT_SEL: u4 = 0, reserved3: u1 = 0, - COMP2POL: u1, // bit offset: 15 desc: Comparator 2 output polarity - COMP2HYST: u2, // bit offset: 16 desc: Comparator 2 hysteresis - COMP2_BLANKING: u3, // bit offset: 18 desc: Comparator 2 blanking source + /// Comparator 2 output polarity + COMP2POL: u1 = 0, + /// Comparator 2 hysteresis + COMP2HYST: u2 = 0, + /// Comparator 2 blanking source + COMP2_BLANKING: u3 = 0, reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, @@ -20743,22 +27746,32 @@ pub const SYSCFG_COMP_OPAMP = extern struct { reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - COMP2LOCK: u1, // bit offset: 31 desc: Comparator 2 lock + /// Comparator 2 lock + COMP2LOCK: u1 = 0, }); - // byte offset: 36 control and status register + + /// control and status register pub const COMP3_CSR = mmio(Address + 0x00000024, 32, packed struct { - COMP3EN: u1, // bit offset: 0 desc: Comparator 3 enable - reserved1: u1 = 0, - COMP3MODE: u2, // bit offset: 2 desc: Comparator 3 mode - COMP3INSEL: u3, // bit offset: 4 desc: Comparator 3 inverting input selection - COMP3INPSEL: u1, // bit offset: 7 desc: Comparator 3 non inverted input selection + /// Comparator 3 enable + COMP3EN: u1 = 0, + reserved1: u1 = 0, + /// Comparator 3 mode + COMP3MODE: u2 = 0, + /// Comparator 3 inverting input selection + COMP3INSEL: u3 = 0, + /// Comparator 3 non inverted input selection + COMP3INPSEL: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - COMP3_OUT_SEL: u4, // bit offset: 10 desc: Comparator 3 output selection + /// Comparator 3 output selection + COMP3_OUT_SEL: u4 = 0, reserved4: u1 = 0, - COMP3POL: u1, // bit offset: 15 desc: Comparator 3 output polarity - COMP3HYST: u2, // bit offset: 16 desc: Comparator 3 hysteresis - COMP3_BLANKING: u3, // bit offset: 18 desc: Comparator 3 blanking source + /// Comparator 3 output polarity + COMP3POL: u1 = 0, + /// Comparator 3 hysteresis + COMP3HYST: u2 = 0, + /// Comparator 3 blanking source + COMP3_BLANKING: u3 = 0, reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, @@ -20768,23 +27781,35 @@ pub const SYSCFG_COMP_OPAMP = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - COMP3OUT: u1, // bit offset: 30 desc: Comparator 3 output - COMP3LOCK: u1, // bit offset: 31 desc: Comparator 3 lock + /// Comparator 3 output + COMP3OUT: u1 = 0, + /// Comparator 3 lock + COMP3LOCK: u1 = 0, }); - // byte offset: 40 control and status register + + /// control and status register pub const COMP4_CSR = mmio(Address + 0x00000028, 32, packed struct { - COMP4EN: u1, // bit offset: 0 desc: Comparator 4 enable - reserved1: u1 = 0, - COMP4MODE: u2, // bit offset: 2 desc: Comparator 4 mode - COMP4INSEL: u3, // bit offset: 4 desc: Comparator 4 inverting input selection - COMP4INPSEL: u1, // bit offset: 7 desc: Comparator 4 non inverted input selection - reserved2: u1 = 0, - COM4WINMODE: u1, // bit offset: 9 desc: Comparator 4 window mode - COMP4_OUT_SEL: u4, // bit offset: 10 desc: Comparator 4 output selection + /// Comparator 4 enable + COMP4EN: u1 = 0, + reserved1: u1 = 0, + /// Comparator 4 mode + COMP4MODE: u2 = 0, + /// Comparator 4 inverting input selection + COMP4INSEL: u3 = 0, + /// Comparator 4 non inverted input selection + COMP4INPSEL: u1 = 0, + reserved2: u1 = 0, + /// Comparator 4 window mode + COM4WINMODE: u1 = 0, + /// Comparator 4 output selection + COMP4_OUT_SEL: u4 = 0, reserved3: u1 = 0, - COMP4POL: u1, // bit offset: 15 desc: Comparator 4 output polarity - COMP4HYST: u2, // bit offset: 16 desc: Comparator 4 hysteresis - COMP4_BLANKING: u3, // bit offset: 18 desc: Comparator 4 blanking source + /// Comparator 4 output polarity + COMP4POL: u1 = 0, + /// Comparator 4 hysteresis + COMP4HYST: u2 = 0, + /// Comparator 4 blanking source + COMP4_BLANKING: u3 = 0, reserved12: u1 = 0, reserved11: u1 = 0, reserved10: u1 = 0, @@ -20794,23 +27819,34 @@ pub const SYSCFG_COMP_OPAMP = extern struct { reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - COMP4OUT: u1, // bit offset: 30 desc: Comparator 4 output - COMP4LOCK: u1, // bit offset: 31 desc: Comparator 4 lock + /// Comparator 4 output + COMP4OUT: u1 = 0, + /// Comparator 4 lock + COMP4LOCK: u1 = 0, }); - // byte offset: 44 control and status register + + /// control and status register pub const COMP5_CSR = mmio(Address + 0x0000002c, 32, packed struct { - COMP5EN: u1, // bit offset: 0 desc: Comparator 5 enable - reserved1: u1 = 0, - COMP5MODE: u2, // bit offset: 2 desc: Comparator 5 mode - COMP5INSEL: u3, // bit offset: 4 desc: Comparator 5 inverting input selection - COMP5INPSEL: u1, // bit offset: 7 desc: Comparator 5 non inverted input selection + /// Comparator 5 enable + COMP5EN: u1 = 0, + reserved1: u1 = 0, + /// Comparator 5 mode + COMP5MODE: u2 = 0, + /// Comparator 5 inverting input selection + COMP5INSEL: u3 = 0, + /// Comparator 5 non inverted input selection + COMP5INPSEL: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - COMP5_OUT_SEL: u4, // bit offset: 10 desc: Comparator 5 output selection + /// Comparator 5 output selection + COMP5_OUT_SEL: u4 = 0, reserved4: u1 = 0, - COMP5POL: u1, // bit offset: 15 desc: Comparator 5 output polarity - COMP5HYST: u2, // bit offset: 16 desc: Comparator 5 hysteresis - COMP5_BLANKING: u3, // bit offset: 18 desc: Comparator 5 blanking source + /// Comparator 5 output polarity + COMP5POL: u1 = 0, + /// Comparator 5 hysteresis + COMP5HYST: u2 = 0, + /// Comparator 5 blanking source + COMP5_BLANKING: u3 = 0, reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, @@ -20820,23 +27856,35 @@ pub const SYSCFG_COMP_OPAMP = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - COMP5OUT: u1, // bit offset: 30 desc: Comparator51 output - COMP5LOCK: u1, // bit offset: 31 desc: Comparator 5 lock + /// Comparator51 output + COMP5OUT: u1 = 0, + /// Comparator 5 lock + COMP5LOCK: u1 = 0, }); - // byte offset: 48 control and status register + + /// control and status register pub const COMP6_CSR = mmio(Address + 0x00000030, 32, packed struct { - COMP6EN: u1, // bit offset: 0 desc: Comparator 6 enable - reserved1: u1 = 0, - COMP6MODE: u2, // bit offset: 2 desc: Comparator 6 mode - COMP6INSEL: u3, // bit offset: 4 desc: Comparator 6 inverting input selection - COMP6INPSEL: u1, // bit offset: 7 desc: Comparator 6 non inverted input selection - reserved2: u1 = 0, - COM6WINMODE: u1, // bit offset: 9 desc: Comparator 6 window mode - COMP6_OUT_SEL: u4, // bit offset: 10 desc: Comparator 6 output selection + /// Comparator 6 enable + COMP6EN: u1 = 0, + reserved1: u1 = 0, + /// Comparator 6 mode + COMP6MODE: u2 = 0, + /// Comparator 6 inverting input selection + COMP6INSEL: u3 = 0, + /// Comparator 6 non inverted input selection + COMP6INPSEL: u1 = 0, + reserved2: u1 = 0, + /// Comparator 6 window mode + COM6WINMODE: u1 = 0, + /// Comparator 6 output selection + COMP6_OUT_SEL: u4 = 0, reserved3: u1 = 0, - COMP6POL: u1, // bit offset: 15 desc: Comparator 6 output polarity - COMP6HYST: u2, // bit offset: 16 desc: Comparator 6 hysteresis - COMP6_BLANKING: u3, // bit offset: 18 desc: Comparator 6 blanking source + /// Comparator 6 output polarity + COMP6POL: u1 = 0, + /// Comparator 6 hysteresis + COMP6HYST: u2 = 0, + /// Comparator 6 blanking source + COMP6_BLANKING: u3 = 0, reserved12: u1 = 0, reserved11: u1 = 0, reserved10: u1 = 0, @@ -20846,23 +27894,34 @@ pub const SYSCFG_COMP_OPAMP = extern struct { reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - COMP6OUT: u1, // bit offset: 30 desc: Comparator 6 output - COMP6LOCK: u1, // bit offset: 31 desc: Comparator 6 lock + /// Comparator 6 output + COMP6OUT: u1 = 0, + /// Comparator 6 lock + COMP6LOCK: u1 = 0, }); - // byte offset: 52 control and status register + + /// control and status register pub const COMP7_CSR = mmio(Address + 0x00000034, 32, packed struct { - COMP7EN: u1, // bit offset: 0 desc: Comparator 7 enable - reserved1: u1 = 0, - COMP7MODE: u2, // bit offset: 2 desc: Comparator 7 mode - COMP7INSEL: u3, // bit offset: 4 desc: Comparator 7 inverting input selection - COMP7INPSEL: u1, // bit offset: 7 desc: Comparator 7 non inverted input selection + /// Comparator 7 enable + COMP7EN: u1 = 0, + reserved1: u1 = 0, + /// Comparator 7 mode + COMP7MODE: u2 = 0, + /// Comparator 7 inverting input selection + COMP7INSEL: u3 = 0, + /// Comparator 7 non inverted input selection + COMP7INPSEL: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - COMP7_OUT_SEL: u4, // bit offset: 10 desc: Comparator 7 output selection + /// Comparator 7 output selection + COMP7_OUT_SEL: u4 = 0, reserved4: u1 = 0, - COMP7POL: u1, // bit offset: 15 desc: Comparator 7 output polarity - COMP7HYST: u2, // bit offset: 16 desc: Comparator 7 hysteresis - COMP7_BLANKING: u3, // bit offset: 18 desc: Comparator 7 blanking source + /// Comparator 7 output polarity + COMP7POL: u1 = 0, + /// Comparator 7 hysteresis + COMP7HYST: u2 = 0, + /// Comparator 7 blanking source + COMP7_BLANKING: u3 = 0, reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, @@ -20872,113 +27931,156 @@ pub const SYSCFG_COMP_OPAMP = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - COMP7OUT: u1, // bit offset: 30 desc: Comparator 7 output - COMP7LOCK: u1, // bit offset: 31 desc: Comparator 7 lock + /// Comparator 7 output + COMP7OUT: u1 = 0, + /// Comparator 7 lock + COMP7LOCK: u1 = 0, }); - // byte offset: 56 control register + + /// control register pub const OPAMP1_CSR = mmio(Address + 0x00000038, 32, packed struct { - OPAMP1_EN: u1, // bit offset: 0 desc: OPAMP1 enable - FORCE_VP: u1, // bit offset: 1 desc: FORCE_VP - VP_SEL: u2, // bit offset: 2 desc: OPAMP1 Non inverting input selection - reserved1: u1 = 0, - VM_SEL: u2, // bit offset: 5 desc: OPAMP1 inverting input selection - TCM_EN: u1, // bit offset: 7 desc: Timer controlled Mux mode enable - VMS_SEL: u1, // bit offset: 8 desc: OPAMP1 inverting input secondary selection - VPS_SEL: u2, // bit offset: 9 desc: OPAMP1 Non inverting input secondary selection - CALON: u1, // bit offset: 11 desc: Calibration mode enable - CALSEL: u2, // bit offset: 12 desc: Calibration selection - PGA_GAIN: u4, // bit offset: 14 desc: Gain in PGA mode - USER_TRIM: u1, // bit offset: 18 desc: User trimming enable - TRIMOFFSETP: u5, // bit offset: 19 desc: Offset trimming value (PMOS) - TRIMOFFSETN: u5, // bit offset: 24 desc: Offset trimming value (NMOS) - TSTREF: u1, // bit offset: 29 desc: TSTREF - OUTCAL: u1, // bit offset: 30 desc: OPAMP 1 ouput status flag - LOCK: u1, // bit offset: 31 desc: OPAMP 1 lock - }); - // byte offset: 60 control register + /// OPAMP1 enable + OPAMP1_EN: u1 = 0, + /// OPAMP1 Non inverting input selection + VP_SEL: u2 = 0, + reserved1: u1 = 0, + /// OPAMP1 inverting input selection + VM_SEL: u2 = 0, + /// Timer controlled Mux mode enable + TCM_EN: u1 = 0, + /// OPAMP1 inverting input secondary selection + VMS_SEL: u1 = 0, + /// OPAMP1 Non inverting input secondary selection + VPS_SEL: u2 = 0, + /// Calibration mode enable + CALON: u1 = 0, + /// Calibration selection + CALSEL: u2 = 0, + /// Gain in PGA mode + PGA_GAIN: u4 = 0, + /// User trimming enable + USER_TRIM: u1 = 0, + /// Offset trimming value (PMOS) + TRIMOFFSETP: u5 = 0, + /// Offset trimming value (NMOS) + TRIMOFFSETN: u5 = 0, + /// OPAMP 1 ouput status flag + OUTCAL: u1 = 0, + /// OPAMP 1 lock + LOCK: u1 = 0, + }); + + /// control register pub const OPAMP2_CSR = mmio(Address + 0x0000003c, 32, packed struct { - OPAMP2EN: u1, // bit offset: 0 desc: OPAMP2 enable - FORCE_VP: u1, // bit offset: 1 desc: FORCE_VP - VP_SEL: u2, // bit offset: 2 desc: OPAMP2 Non inverting input selection - reserved1: u1 = 0, - VM_SEL: u2, // bit offset: 5 desc: OPAMP2 inverting input selection - TCM_EN: u1, // bit offset: 7 desc: Timer controlled Mux mode enable - VMS_SEL: u1, // bit offset: 8 desc: OPAMP2 inverting input secondary selection - VPS_SEL: u2, // bit offset: 9 desc: OPAMP2 Non inverting input secondary selection - CALON: u1, // bit offset: 11 desc: Calibration mode enable - CAL_SEL: u2, // bit offset: 12 desc: Calibration selection - PGA_GAIN: u4, // bit offset: 14 desc: Gain in PGA mode - USER_TRIM: u1, // bit offset: 18 desc: User trimming enable - TRIMOFFSETP: u5, // bit offset: 19 desc: Offset trimming value (PMOS) - TRIMOFFSETN: u5, // bit offset: 24 desc: Offset trimming value (NMOS) - TSTREF: u1, // bit offset: 29 desc: TSTREF - OUTCAL: u1, // bit offset: 30 desc: OPAMP 2 ouput status flag - LOCK: u1, // bit offset: 31 desc: OPAMP 2 lock - }); - // byte offset: 64 control register + /// OPAMP2 enable + OPAMP2EN: u1 = 0, + /// OPAMP2 Non inverting input selection + VP_SEL: u2 = 0, + reserved1: u1 = 0, + /// OPAMP2 inverting input selection + VM_SEL: u2 = 0, + /// Timer controlled Mux mode enable + TCM_EN: u1 = 0, + /// OPAMP2 inverting input secondary selection + VMS_SEL: u1 = 0, + /// OPAMP2 Non inverting input secondary selection + VPS_SEL: u2 = 0, + /// Calibration mode enable + CALON: u1 = 0, + /// Calibration selection + CAL_SEL: u2 = 0, + /// Gain in PGA mode + PGA_GAIN: u4 = 0, + /// User trimming enable + USER_TRIM: u1 = 0, + /// Offset trimming value (PMOS) + TRIMOFFSETP: u5 = 0, + /// Offset trimming value (NMOS) + TRIMOFFSETN: u5 = 0, + /// OPAMP 2 ouput status flag + OUTCAL: u1 = 0, + /// OPAMP 2 lock + LOCK: u1 = 0, + }); + + /// control register pub const OPAMP3_CSR = mmio(Address + 0x00000040, 32, packed struct { - OPAMP3EN: u1, // bit offset: 0 desc: OPAMP3 enable - FORCE_VP: u1, // bit offset: 1 desc: FORCE_VP - VP_SEL: u2, // bit offset: 2 desc: OPAMP3 Non inverting input selection - reserved1: u1 = 0, - VM_SEL: u2, // bit offset: 5 desc: OPAMP3 inverting input selection - TCM_EN: u1, // bit offset: 7 desc: Timer controlled Mux mode enable - VMS_SEL: u1, // bit offset: 8 desc: OPAMP3 inverting input secondary selection - VPS_SEL: u2, // bit offset: 9 desc: OPAMP3 Non inverting input secondary selection - CALON: u1, // bit offset: 11 desc: Calibration mode enable - CALSEL: u2, // bit offset: 12 desc: Calibration selection - PGA_GAIN: u4, // bit offset: 14 desc: Gain in PGA mode - USER_TRIM: u1, // bit offset: 18 desc: User trimming enable - TRIMOFFSETP: u5, // bit offset: 19 desc: Offset trimming value (PMOS) - TRIMOFFSETN: u5, // bit offset: 24 desc: Offset trimming value (NMOS) - TSTREF: u1, // bit offset: 29 desc: TSTREF - OUTCAL: u1, // bit offset: 30 desc: OPAMP 3 ouput status flag - LOCK: u1, // bit offset: 31 desc: OPAMP 3 lock - }); - // byte offset: 68 control register + /// OPAMP3 enable + OPAMP3EN: u1 = 0, + /// OPAMP3 Non inverting input selection + VP_SEL: u2 = 0, + reserved1: u1 = 0, + /// OPAMP3 inverting input selection + VM_SEL: u2 = 0, + /// Timer controlled Mux mode enable + TCM_EN: u1 = 0, + /// OPAMP3 inverting input secondary selection + VMS_SEL: u1 = 0, + /// OPAMP3 Non inverting input secondary selection + VPS_SEL: u2 = 0, + /// Calibration mode enable + CALON: u1 = 0, + /// Calibration selection + CALSEL: u2 = 0, + /// Gain in PGA mode + PGA_GAIN: u4 = 0, + /// User trimming enable + USER_TRIM: u1 = 0, + /// Offset trimming value (PMOS) + TRIMOFFSETP: u5 = 0, + /// Offset trimming value (NMOS) + TRIMOFFSETN: u5 = 0, + /// OPAMP 3 ouput status flag + OUTCAL: u1 = 0, + /// OPAMP 3 lock + LOCK: u1 = 0, + }); + + /// control register pub const OPAMP4_CSR = mmio(Address + 0x00000044, 32, packed struct { - OPAMP4EN: u1, // bit offset: 0 desc: OPAMP4 enable - FORCE_VP: u1, // bit offset: 1 desc: FORCE_VP - VP_SEL: u2, // bit offset: 2 desc: OPAMP4 Non inverting input selection - reserved1: u1 = 0, - VM_SEL: u2, // bit offset: 5 desc: OPAMP4 inverting input selection - TCM_EN: u1, // bit offset: 7 desc: Timer controlled Mux mode enable - VMS_SEL: u1, // bit offset: 8 desc: OPAMP4 inverting input secondary selection - VPS_SEL: u2, // bit offset: 9 desc: OPAMP4 Non inverting input secondary selection - CALON: u1, // bit offset: 11 desc: Calibration mode enable - CALSEL: u2, // bit offset: 12 desc: Calibration selection - PGA_GAIN: u4, // bit offset: 14 desc: Gain in PGA mode - USER_TRIM: u1, // bit offset: 18 desc: User trimming enable - TRIMOFFSETP: u5, // bit offset: 19 desc: Offset trimming value (PMOS) - TRIMOFFSETN: u5, // bit offset: 24 desc: Offset trimming value (NMOS) - TSTREF: u1, // bit offset: 29 desc: TSTREF - OUTCAL: u1, // bit offset: 30 desc: OPAMP 4 ouput status flag - LOCK: u1, // bit offset: 31 desc: OPAMP 4 lock + /// OPAMP4 enable + OPAMP4EN: u1 = 0, + /// OPAMP4 Non inverting input selection + VP_SEL: u2 = 0, + reserved1: u1 = 0, + /// OPAMP4 inverting input selection + VM_SEL: u2 = 0, + /// Timer controlled Mux mode enable + TCM_EN: u1 = 0, + /// OPAMP4 inverting input secondary selection + VMS_SEL: u1 = 0, + /// OPAMP4 Non inverting input secondary selection + VPS_SEL: u2 = 0, + /// Calibration mode enable + CALON: u1 = 0, + /// Calibration selection + CALSEL: u2 = 0, + /// Gain in PGA mode + PGA_GAIN: u4 = 0, + /// User trimming enable + USER_TRIM: u1 = 0, + /// Offset trimming value (PMOS) + TRIMOFFSETP: u5 = 0, + /// Offset trimming value (NMOS) + TRIMOFFSETN: u5 = 0, + /// OPAMP 4 ouput status flag + OUTCAL: u1 = 0, + /// OPAMP 4 lock + LOCK: u1 = 0, }); }; + +/// Flexible memory controller pub const FMC = extern struct { pub const Address: u32 = 0xa0000400; - // byte offset: 0 SRAM/NOR-Flash chip-select control register 1 + + /// SRAM/NOR-Flash chip-select control register 1 pub const BCR1 = mmio(Address + 0x00000000, 32, packed struct { - MBKEN: u1, // bit offset: 0 desc: MBKEN - MUXEN: u1, // bit offset: 1 desc: MUXEN - MTYP: u2, // bit offset: 2 desc: MTYP - MWID: u2, // bit offset: 4 desc: MWID - FACCEN: u1, // bit offset: 6 desc: FACCEN - reserved1: u1 = 0, - BURSTEN: u1, // bit offset: 8 desc: BURSTEN - WAITPOL: u1, // bit offset: 9 desc: WAITPOL - reserved2: u1 = 0, - WAITCFG: u1, // bit offset: 11 desc: WAITCFG - WREN: u1, // bit offset: 12 desc: WREN - WAITEN: u1, // bit offset: 13 desc: WAITEN - EXTMOD: u1, // bit offset: 14 desc: EXTMOD - ASYNCWAIT: u1, // bit offset: 15 desc: ASYNCWAIT + reserved1: u1 = 0, + reserved2: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - CBURSTRW: u1, // bit offset: 19 desc: CBURSTRW - CCLKEN: u1, // bit offset: 20 desc: CCLKEN padding11: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, @@ -20991,38 +28093,19 @@ pub const FMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 SRAM/NOR-Flash chip-select timing register 1 + + /// SRAM/NOR-Flash chip-select timing register 1 pub const BTR1 = mmio(Address + 0x00000004, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST - BUSTURN: u4, // bit offset: 16 desc: BUSTURN - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 SRAM/NOR-Flash chip-select control register 2 + + /// SRAM/NOR-Flash chip-select control register 2 pub const BCR2 = mmio(Address + 0x00000008, 32, packed struct { - MBKEN: u1, // bit offset: 0 desc: MBKEN - MUXEN: u1, // bit offset: 1 desc: MUXEN - MTYP: u2, // bit offset: 2 desc: MTYP - MWID: u2, // bit offset: 4 desc: MWID - FACCEN: u1, // bit offset: 6 desc: FACCEN - reserved1: u1 = 0, - BURSTEN: u1, // bit offset: 8 desc: BURSTEN - WAITPOL: u1, // bit offset: 9 desc: WAITPOL - WRAPMOD: u1, // bit offset: 10 desc: WRAPMOD - WAITCFG: u1, // bit offset: 11 desc: WAITCFG - WREN: u1, // bit offset: 12 desc: WREN - WAITEN: u1, // bit offset: 13 desc: WAITEN - EXTMOD: u1, // bit offset: 14 desc: EXTMOD - ASYNCWAIT: u1, // bit offset: 15 desc: ASYNCWAIT + reserved1: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CBURSTRW: u1, // bit offset: 19 desc: CBURSTRW padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -21036,38 +28119,19 @@ pub const FMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 SRAM/NOR-Flash chip-select timing register 2 + + /// SRAM/NOR-Flash chip-select timing register 2 pub const BTR2 = mmio(Address + 0x0000000c, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST - BUSTURN: u4, // bit offset: 16 desc: BUSTURN - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 SRAM/NOR-Flash chip-select control register 3 + + /// SRAM/NOR-Flash chip-select control register 3 pub const BCR3 = mmio(Address + 0x00000010, 32, packed struct { - MBKEN: u1, // bit offset: 0 desc: MBKEN - MUXEN: u1, // bit offset: 1 desc: MUXEN - MTYP: u2, // bit offset: 2 desc: MTYP - MWID: u2, // bit offset: 4 desc: MWID - FACCEN: u1, // bit offset: 6 desc: FACCEN - reserved1: u1 = 0, - BURSTEN: u1, // bit offset: 8 desc: BURSTEN - WAITPOL: u1, // bit offset: 9 desc: WAITPOL - WRAPMOD: u1, // bit offset: 10 desc: WRAPMOD - WAITCFG: u1, // bit offset: 11 desc: WAITCFG - WREN: u1, // bit offset: 12 desc: WREN - WAITEN: u1, // bit offset: 13 desc: WAITEN - EXTMOD: u1, // bit offset: 14 desc: EXTMOD - ASYNCWAIT: u1, // bit offset: 15 desc: ASYNCWAIT + reserved1: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CBURSTRW: u1, // bit offset: 19 desc: CBURSTRW padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -21081,38 +28145,19 @@ pub const FMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 SRAM/NOR-Flash chip-select timing register 3 + + /// SRAM/NOR-Flash chip-select timing register 3 pub const BTR3 = mmio(Address + 0x00000014, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST - BUSTURN: u4, // bit offset: 16 desc: BUSTURN - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 SRAM/NOR-Flash chip-select control register 4 + + /// SRAM/NOR-Flash chip-select control register 4 pub const BCR4 = mmio(Address + 0x00000018, 32, packed struct { - MBKEN: u1, // bit offset: 0 desc: MBKEN - MUXEN: u1, // bit offset: 1 desc: MUXEN - MTYP: u2, // bit offset: 2 desc: MTYP - MWID: u2, // bit offset: 4 desc: MWID - FACCEN: u1, // bit offset: 6 desc: FACCEN - reserved1: u1 = 0, - BURSTEN: u1, // bit offset: 8 desc: BURSTEN - WAITPOL: u1, // bit offset: 9 desc: WAITPOL - WRAPMOD: u1, // bit offset: 10 desc: WRAPMOD - WAITCFG: u1, // bit offset: 11 desc: WAITCFG - WREN: u1, // bit offset: 12 desc: WREN - WAITEN: u1, // bit offset: 13 desc: WAITEN - EXTMOD: u1, // bit offset: 14 desc: EXTMOD - ASYNCWAIT: u1, // bit offset: 15 desc: ASYNCWAIT + reserved1: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CBURSTRW: u1, // bit offset: 19 desc: CBURSTRW padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -21126,31 +28171,18 @@ pub const FMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 SRAM/NOR-Flash chip-select timing register 4 + + /// SRAM/NOR-Flash chip-select timing register 4 pub const BTR4 = mmio(Address + 0x0000001c, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST - BUSTURN: u4, // bit offset: 16 desc: BUSTURN - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 96 PC Card/NAND Flash control register 2 + + /// PC Card/NAND Flash control register 2 pub const PCR2 = mmio(Address + 0x00000060, 32, packed struct { reserved1: u1 = 0, - PWAITEN: u1, // bit offset: 1 desc: PWAITEN - PBKEN: u1, // bit offset: 2 desc: PBKEN - PTYP: u1, // bit offset: 3 desc: PTYP - PWID: u2, // bit offset: 4 desc: PWID - ECCEN: u1, // bit offset: 6 desc: ECCEN reserved3: u1 = 0, reserved2: u1 = 0, - TCLR: u4, // bit offset: 9 desc: TCLR - TAR: u4, // bit offset: 13 desc: TAR - ECCPS: u3, // bit offset: 17 desc: ECCPS padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -21164,15 +28196,9 @@ pub const FMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 100 FIFO status and interrupt register 2 + + /// FIFO status and interrupt register 2 pub const SR2 = mmio(Address + 0x00000064, 32, packed struct { - IRS: u1, // bit offset: 0 desc: IRS - ILS: u1, // bit offset: 1 desc: ILS - IFS: u1, // bit offset: 2 desc: IFS - IREN: u1, // bit offset: 3 desc: IREN - ILEN: u1, // bit offset: 4 desc: ILEN - IFEN: u1, // bit offset: 5 desc: IFEN - FEMPT: u1, // bit offset: 6 desc: FEMPT padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -21199,37 +28225,21 @@ pub const FMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 104 Common memory space timing register 2 - pub const PMEM2 = mmio(Address + 0x00000068, 32, packed struct { - MEMSETx: u8, // bit offset: 0 desc: MEMSETx - MEMWAITx: u8, // bit offset: 8 desc: MEMWAITx - MEMHOLDx: u8, // bit offset: 16 desc: MEMHOLDx - MEMHIZx: u8, // bit offset: 24 desc: MEMHIZx - }); - // byte offset: 108 Attribute memory space timing register 2 - pub const PATT2 = mmio(Address + 0x0000006c, 32, packed struct { - ATTSETx: u8, // bit offset: 0 desc: ATTSETx - ATTWAITx: u8, // bit offset: 8 desc: ATTWAITx - ATTHOLDx: u8, // bit offset: 16 desc: ATTHOLDx - ATTHIZx: u8, // bit offset: 24 desc: ATTHIZx - }); - // byte offset: 116 ECC result register 2 - pub const ECCR2 = mmio(Address + 0x00000074, 32, packed struct { - ECCx: u32, // bit offset: 0 desc: ECCx - }); - // byte offset: 128 PC Card/NAND Flash control register 3 + + /// Common memory space timing register 2 + pub const PMEM2 = mmio(Address + 0x00000068, 32, packed struct {}); + + /// Attribute memory space timing register 2 + pub const PATT2 = mmio(Address + 0x0000006c, 32, packed struct {}); + + /// ECC result register 2 + pub const ECCR2 = mmio(Address + 0x00000074, 32, packed struct {}); + + /// PC Card/NAND Flash control register 3 pub const PCR3 = mmio(Address + 0x00000080, 32, packed struct { reserved1: u1 = 0, - PWAITEN: u1, // bit offset: 1 desc: PWAITEN - PBKEN: u1, // bit offset: 2 desc: PBKEN - PTYP: u1, // bit offset: 3 desc: PTYP - PWID: u2, // bit offset: 4 desc: PWID - ECCEN: u1, // bit offset: 6 desc: ECCEN reserved3: u1 = 0, reserved2: u1 = 0, - TCLR: u4, // bit offset: 9 desc: TCLR - TAR: u4, // bit offset: 13 desc: TAR - ECCPS: u3, // bit offset: 17 desc: ECCPS padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -21243,15 +28253,9 @@ pub const FMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 132 FIFO status and interrupt register 3 + + /// FIFO status and interrupt register 3 pub const SR3 = mmio(Address + 0x00000084, 32, packed struct { - IRS: u1, // bit offset: 0 desc: IRS - ILS: u1, // bit offset: 1 desc: ILS - IFS: u1, // bit offset: 2 desc: IFS - IREN: u1, // bit offset: 3 desc: IREN - ILEN: u1, // bit offset: 4 desc: ILEN - IFEN: u1, // bit offset: 5 desc: IFEN - FEMPT: u1, // bit offset: 6 desc: FEMPT padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -21278,37 +28282,21 @@ pub const FMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 136 Common memory space timing register 3 - pub const PMEM3 = mmio(Address + 0x00000088, 32, packed struct { - MEMSETx: u8, // bit offset: 0 desc: MEMSETx - MEMWAITx: u8, // bit offset: 8 desc: MEMWAITx - MEMHOLDx: u8, // bit offset: 16 desc: MEMHOLDx - MEMHIZx: u8, // bit offset: 24 desc: MEMHIZx - }); - // byte offset: 140 Attribute memory space timing register 3 - pub const PATT3 = mmio(Address + 0x0000008c, 32, packed struct { - ATTSETx: u8, // bit offset: 0 desc: ATTSETx - ATTWAITx: u8, // bit offset: 8 desc: ATTWAITx - ATTHOLDx: u8, // bit offset: 16 desc: ATTHOLDx - ATTHIZx: u8, // bit offset: 24 desc: ATTHIZx - }); - // byte offset: 148 ECC result register 3 - pub const ECCR3 = mmio(Address + 0x00000094, 32, packed struct { - ECCx: u32, // bit offset: 0 desc: ECCx - }); - // byte offset: 160 PC Card/NAND Flash control register 4 + + /// Common memory space timing register 3 + pub const PMEM3 = mmio(Address + 0x00000088, 32, packed struct {}); + + /// Attribute memory space timing register 3 + pub const PATT3 = mmio(Address + 0x0000008c, 32, packed struct {}); + + /// ECC result register 3 + pub const ECCR3 = mmio(Address + 0x00000094, 32, packed struct {}); + + /// PC Card/NAND Flash control register 4 pub const PCR4 = mmio(Address + 0x000000a0, 32, packed struct { reserved1: u1 = 0, - PWAITEN: u1, // bit offset: 1 desc: PWAITEN - PBKEN: u1, // bit offset: 2 desc: PBKEN - PTYP: u1, // bit offset: 3 desc: PTYP - PWID: u2, // bit offset: 4 desc: PWID - ECCEN: u1, // bit offset: 6 desc: ECCEN reserved3: u1 = 0, reserved2: u1 = 0, - TCLR: u4, // bit offset: 9 desc: TCLR - TAR: u4, // bit offset: 13 desc: TAR - ECCPS: u3, // bit offset: 17 desc: ECCPS padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -21322,15 +28310,9 @@ pub const FMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 164 FIFO status and interrupt register 4 + + /// FIFO status and interrupt register 4 pub const SR4 = mmio(Address + 0x000000a4, 32, packed struct { - IRS: u1, // bit offset: 0 desc: IRS - ILS: u1, // bit offset: 1 desc: ILS - IFS: u1, // bit offset: 2 desc: IFS - IREN: u1, // bit offset: 3 desc: IREN - ILEN: u1, // bit offset: 4 desc: ILEN - IFEN: u1, // bit offset: 5 desc: IFEN - FEMPT: u1, // bit offset: 6 desc: FEMPT padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -21357,299 +28339,170 @@ pub const FMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 168 Common memory space timing register 4 - pub const PMEM4 = mmio(Address + 0x000000a8, 32, packed struct { - MEMSETx: u8, // bit offset: 0 desc: MEMSETx - MEMWAITx: u8, // bit offset: 8 desc: MEMWAITx - MEMHOLDx: u8, // bit offset: 16 desc: MEMHOLDx - MEMHIZx: u8, // bit offset: 24 desc: MEMHIZx - }); - // byte offset: 172 Attribute memory space timing register 4 - pub const PATT4 = mmio(Address + 0x000000ac, 32, packed struct { - ATTSETx: u8, // bit offset: 0 desc: ATTSETx - ATTWAITx: u8, // bit offset: 8 desc: ATTWAITx - ATTHOLDx: u8, // bit offset: 16 desc: ATTHOLDx - ATTHIZx: u8, // bit offset: 24 desc: ATTHIZx - }); - // byte offset: 176 I/O space timing register 4 - pub const PIO4 = mmio(Address + 0x000000b0, 32, packed struct { - IOSETx: u8, // bit offset: 0 desc: IOSETx - IOWAITx: u8, // bit offset: 8 desc: IOWAITx - IOHOLDx: u8, // bit offset: 16 desc: IOHOLDx - IOHIZx: u8, // bit offset: 24 desc: IOHIZx - }); - // byte offset: 260 SRAM/NOR-Flash write timing registers 1 + + /// Common memory space timing register 4 + pub const PMEM4 = mmio(Address + 0x000000a8, 32, packed struct {}); + + /// Attribute memory space timing register 4 + pub const PATT4 = mmio(Address + 0x000000ac, 32, packed struct {}); + + /// I/O space timing register 4 + pub const PIO4 = mmio(Address + 0x000000b0, 32, packed struct {}); + + /// SRAM/NOR-Flash write timing registers 1 pub const BWTR1 = mmio(Address + 0x00000104, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST - BUSTURN: u4, // bit offset: 16 desc: Bus turnaround phase duration - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD + /// Bus turnaround phase duration + BUSTURN: u4 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 268 SRAM/NOR-Flash write timing registers 2 + + /// SRAM/NOR-Flash write timing registers 2 pub const BWTR2 = mmio(Address + 0x0000010c, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST - BUSTURN: u4, // bit offset: 16 desc: Bus turnaround phase duration - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD + /// Bus turnaround phase duration + BUSTURN: u4 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 276 SRAM/NOR-Flash write timing registers 3 + + /// SRAM/NOR-Flash write timing registers 3 pub const BWTR3 = mmio(Address + 0x00000114, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST - BUSTURN: u4, // bit offset: 16 desc: Bus turnaround phase duration - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD + /// Bus turnaround phase duration + BUSTURN: u4 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 284 SRAM/NOR-Flash write timing registers 4 + + /// SRAM/NOR-Flash write timing registers 4 pub const BWTR4 = mmio(Address + 0x0000011c, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST - BUSTURN: u4, // bit offset: 16 desc: Bus turnaround phase duration - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD + /// Bus turnaround phase duration + BUSTURN: u4 = 0, padding2: u1 = 0, padding1: u1 = 0, }); }; + +/// Nested Vectored Interrupt Controller pub const NVIC = extern struct { pub const Address: u32 = 0xe000e100; - // byte offset: 0 Interrupt Set-Enable Register - pub const ISER0 = mmio(Address + 0x00000000, 32, packed struct { - SETENA: u32, // bit offset: 0 desc: SETENA - }); - // byte offset: 4 Interrupt Set-Enable Register - pub const ISER1 = mmio(Address + 0x00000004, 32, packed struct { - SETENA: u32, // bit offset: 0 desc: SETENA - }); - // byte offset: 8 Interrupt Set-Enable Register - pub const ISER2 = mmio(Address + 0x00000008, 32, packed struct { - SETENA: u32, // bit offset: 0 desc: SETENA - }); - // byte offset: 128 Interrupt Clear-Enable Register - pub const ICER0 = mmio(Address + 0x00000080, 32, packed struct { - CLRENA: u32, // bit offset: 0 desc: CLRENA - }); - // byte offset: 132 Interrupt Clear-Enable Register - pub const ICER1 = mmio(Address + 0x00000084, 32, packed struct { - CLRENA: u32, // bit offset: 0 desc: CLRENA - }); - // byte offset: 136 Interrupt Clear-Enable Register - pub const ICER2 = mmio(Address + 0x00000088, 32, packed struct { - CLRENA: u32, // bit offset: 0 desc: CLRENA - }); - // byte offset: 256 Interrupt Set-Pending Register - pub const ISPR0 = mmio(Address + 0x00000100, 32, packed struct { - SETPEND: u32, // bit offset: 0 desc: SETPEND - }); - // byte offset: 260 Interrupt Set-Pending Register - pub const ISPR1 = mmio(Address + 0x00000104, 32, packed struct { - SETPEND: u32, // bit offset: 0 desc: SETPEND - }); - // byte offset: 264 Interrupt Set-Pending Register - pub const ISPR2 = mmio(Address + 0x00000108, 32, packed struct { - SETPEND: u32, // bit offset: 0 desc: SETPEND - }); - // byte offset: 384 Interrupt Clear-Pending Register - pub const ICPR0 = mmio(Address + 0x00000180, 32, packed struct { - CLRPEND: u32, // bit offset: 0 desc: CLRPEND - }); - // byte offset: 388 Interrupt Clear-Pending Register - pub const ICPR1 = mmio(Address + 0x00000184, 32, packed struct { - CLRPEND: u32, // bit offset: 0 desc: CLRPEND - }); - // byte offset: 392 Interrupt Clear-Pending Register - pub const ICPR2 = mmio(Address + 0x00000188, 32, packed struct { - CLRPEND: u32, // bit offset: 0 desc: CLRPEND - }); - // byte offset: 512 Interrupt Active Bit Register - pub const IABR0 = mmio(Address + 0x00000200, 32, packed struct { - ACTIVE: u32, // bit offset: 0 desc: ACTIVE - }); - // byte offset: 516 Interrupt Active Bit Register - pub const IABR1 = mmio(Address + 0x00000204, 32, packed struct { - ACTIVE: u32, // bit offset: 0 desc: ACTIVE - }); - // byte offset: 520 Interrupt Active Bit Register - pub const IABR2 = mmio(Address + 0x00000208, 32, packed struct { - ACTIVE: u32, // bit offset: 0 desc: ACTIVE - }); - // byte offset: 768 Interrupt Priority Register - pub const IPR0 = mmio(Address + 0x00000300, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 772 Interrupt Priority Register - pub const IPR1 = mmio(Address + 0x00000304, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 776 Interrupt Priority Register - pub const IPR2 = mmio(Address + 0x00000308, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 780 Interrupt Priority Register - pub const IPR3 = mmio(Address + 0x0000030c, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 784 Interrupt Priority Register - pub const IPR4 = mmio(Address + 0x00000310, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 788 Interrupt Priority Register - pub const IPR5 = mmio(Address + 0x00000314, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 792 Interrupt Priority Register - pub const IPR6 = mmio(Address + 0x00000318, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 796 Interrupt Priority Register - pub const IPR7 = mmio(Address + 0x0000031c, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 800 Interrupt Priority Register - pub const IPR8 = mmio(Address + 0x00000320, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 804 Interrupt Priority Register - pub const IPR9 = mmio(Address + 0x00000324, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 808 Interrupt Priority Register - pub const IPR10 = mmio(Address + 0x00000328, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 812 Interrupt Priority Register - pub const IPR11 = mmio(Address + 0x0000032c, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 816 Interrupt Priority Register - pub const IPR12 = mmio(Address + 0x00000330, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 820 Interrupt Priority Register - pub const IPR13 = mmio(Address + 0x00000334, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 824 Interrupt Priority Register - pub const IPR14 = mmio(Address + 0x00000338, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 828 Interrupt Priority Register - pub const IPR15 = mmio(Address + 0x0000033c, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 832 Interrupt Priority Register - pub const IPR16 = mmio(Address + 0x00000340, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 836 Interrupt Priority Register - pub const IPR17 = mmio(Address + 0x00000344, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 840 Interrupt Priority Register - pub const IPR18 = mmio(Address + 0x00000348, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 844 Interrupt Priority Register - pub const IPR19 = mmio(Address + 0x0000034c, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 848 Interrupt Priority Register - pub const IPR20 = mmio(Address + 0x00000350, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); + + /// Interrupt Set-Enable Register + pub const ISER0 = mmio(Address + 0x00000000, 32, packed struct {}); + + /// Interrupt Set-Enable Register + pub const ISER1 = mmio(Address + 0x00000004, 32, packed struct {}); + + /// Interrupt Set-Enable Register + pub const ISER2 = mmio(Address + 0x00000008, 32, packed struct {}); + + /// Interrupt Clear-Enable Register + pub const ICER0 = mmio(Address + 0x00000080, 32, packed struct {}); + + /// Interrupt Clear-Enable Register + pub const ICER1 = mmio(Address + 0x00000084, 32, packed struct {}); + + /// Interrupt Clear-Enable Register + pub const ICER2 = mmio(Address + 0x00000088, 32, packed struct {}); + + /// Interrupt Set-Pending Register + pub const ISPR0 = mmio(Address + 0x00000100, 32, packed struct {}); + + /// Interrupt Set-Pending Register + pub const ISPR1 = mmio(Address + 0x00000104, 32, packed struct {}); + + /// Interrupt Set-Pending Register + pub const ISPR2 = mmio(Address + 0x00000108, 32, packed struct {}); + + /// Interrupt Clear-Pending Register + pub const ICPR0 = mmio(Address + 0x00000180, 32, packed struct {}); + + /// Interrupt Clear-Pending Register + pub const ICPR1 = mmio(Address + 0x00000184, 32, packed struct {}); + + /// Interrupt Clear-Pending Register + pub const ICPR2 = mmio(Address + 0x00000188, 32, packed struct {}); + + /// Interrupt Active Bit Register + pub const IABR0 = mmio(Address + 0x00000200, 32, packed struct {}); + + /// Interrupt Active Bit Register + pub const IABR1 = mmio(Address + 0x00000204, 32, packed struct {}); + + /// Interrupt Active Bit Register + pub const IABR2 = mmio(Address + 0x00000208, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR0 = mmio(Address + 0x00000300, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR1 = mmio(Address + 0x00000304, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR2 = mmio(Address + 0x00000308, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR3 = mmio(Address + 0x0000030c, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR4 = mmio(Address + 0x00000310, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR5 = mmio(Address + 0x00000314, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR6 = mmio(Address + 0x00000318, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR7 = mmio(Address + 0x0000031c, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR8 = mmio(Address + 0x00000320, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR9 = mmio(Address + 0x00000324, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR10 = mmio(Address + 0x00000328, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR11 = mmio(Address + 0x0000032c, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR12 = mmio(Address + 0x00000330, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR13 = mmio(Address + 0x00000334, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR14 = mmio(Address + 0x00000338, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR15 = mmio(Address + 0x0000033c, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR16 = mmio(Address + 0x00000340, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR17 = mmio(Address + 0x00000344, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR18 = mmio(Address + 0x00000348, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR19 = mmio(Address + 0x0000034c, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR20 = mmio(Address + 0x00000350, 32, packed struct {}); }; + +/// Floting point unit pub const FPU = extern struct { pub const Address: u32 = 0xe000ef34; - // byte offset: 0 Floating-point context control register + + /// Floating-point context control register pub const FPCCR = mmio(Address + 0x00000000, 32, packed struct { - LSPACT: u1, // bit offset: 0 desc: LSPACT - USER: u1, // bit offset: 1 desc: USER reserved1: u1 = 0, - THREAD: u1, // bit offset: 3 desc: THREAD - HFRDY: u1, // bit offset: 4 desc: HFRDY - MMRDY: u1, // bit offset: 5 desc: MMRDY - BFRDY: u1, // bit offset: 6 desc: BFRDY reserved2: u1 = 0, - MONRDY: u1, // bit offset: 8 desc: MONRDY reserved23: u1 = 0, reserved22: u1 = 0, reserved21: u1 = 0, @@ -21671,26 +28524,33 @@ pub const FPU = extern struct { reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - LSPEN: u1, // bit offset: 30 desc: LSPEN - ASPEN: u1, // bit offset: 31 desc: ASPEN }); - // byte offset: 4 Floating-point context address register + + /// Floating-point context address register pub const FPCAR = mmio(Address + 0x00000004, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADDRESS: u29, // bit offset: 3 desc: Location of unpopulated floating-point + /// Location of unpopulated floating-point + ADDRESS: u29 = 0, }); - // byte offset: 8 Floating-point status control register + + /// Floating-point status control register pub const FPSCR = mmio(Address + 0x00000008, 32, packed struct { - IOC: u1, // bit offset: 0 desc: Invalid operation cumulative exception bit - DZC: u1, // bit offset: 1 desc: Division by zero cumulative exception bit. - OFC: u1, // bit offset: 2 desc: Overflow cumulative exception bit - UFC: u1, // bit offset: 3 desc: Underflow cumulative exception bit - IXC: u1, // bit offset: 4 desc: Inexact cumulative exception bit - reserved2: u1 = 0, - reserved1: u1 = 0, - IDC: u1, // bit offset: 7 desc: Input denormal cumulative exception bit. + /// Invalid operation cumulative exception bit + IOC: u1 = 0, + /// Division by zero cumulative exception bit. + DZC: u1 = 0, + /// Overflow cumulative exception bit + OFC: u1 = 0, + /// Underflow cumulative exception bit + UFC: u1 = 0, + /// Inexact cumulative exception bit + IXC: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Input denormal cumulative exception bit. + IDC: u1 = 0, reserved16: u1 = 0, reserved15: u1 = 0, reserved14: u1 = 0, @@ -21705,22 +28565,34 @@ pub const FPU = extern struct { reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - RMode: u2, // bit offset: 22 desc: Rounding Mode control field - FZ: u1, // bit offset: 24 desc: Flush-to-zero mode control bit: - DN: u1, // bit offset: 25 desc: Default NaN mode control bit - AHP: u1, // bit offset: 26 desc: Alternative half-precision control bit + /// Rounding Mode control field + RMode: u2 = 0, + /// Flush-to-zero mode control bit: + FZ: u1 = 0, + /// Default NaN mode control bit + DN: u1 = 0, + /// Alternative half-precision control bit + AHP: u1 = 0, reserved17: u1 = 0, - V: u1, // bit offset: 28 desc: Overflow condition code flag - C: u1, // bit offset: 29 desc: Carry condition code flag - Z: u1, // bit offset: 30 desc: Zero condition code flag - N: u1, // bit offset: 31 desc: Negative condition code flag + /// Overflow condition code flag + V: u1 = 0, + /// Carry condition code flag + C: u1 = 0, + /// Zero condition code flag + Z: u1 = 0, + /// Negative condition code flag + N: u1 = 0, }); }; + +/// Memory protection unit pub const MPU = extern struct { pub const Address: u32 = 0xe000ed90; - // byte offset: 0 MPU type register + + /// MPU type register pub const MPU_TYPER = mmio(Address + 0x00000000, 32, packed struct { - SEPARATE: u1, // bit offset: 0 desc: Separate flag + /// Separate flag + SEPARATE: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -21728,8 +28600,10 @@ pub const MPU = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DREGION: u8, // bit offset: 8 desc: Number of MPU data regions - IREGION: u8, // bit offset: 16 desc: Number of MPU instruction regions + /// Number of MPU data regions + DREGION: u8 = 0, + /// Number of MPU instruction regions + IREGION: u8 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -21739,11 +28613,15 @@ pub const MPU = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 MPU control register + + /// MPU control register pub const MPU_CTRL = mmio(Address + 0x00000004, 32, packed struct { - ENABLE: u1, // bit offset: 0 desc: Enables the MPU - HFNMIENA: u1, // bit offset: 1 desc: Enables the operation of MPU during hard fault - PRIVDEFENA: u1, // bit offset: 2 desc: Enable priviliged software access to default memory map + /// Enables the MPU + ENABLE: u1 = 0, + /// Enables the operation of MPU during hard fault + HFNMIENA: u1 = 0, + /// Enable priviliged software access to default memory map + PRIVDEFENA: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, @@ -21774,9 +28652,11 @@ pub const MPU = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 MPU region number register + + /// MPU region number register pub const MPU_RNR = mmio(Address + 0x00000008, 32, packed struct { - REGION: u8, // bit offset: 0 desc: MPU region + /// MPU region + REGION: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -21802,40 +28682,60 @@ pub const MPU = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 MPU region base address register + + /// MPU region base address register pub const MPU_RBAR = mmio(Address + 0x0000000c, 32, packed struct { - REGION: u4, // bit offset: 0 desc: MPU region field - VALID: u1, // bit offset: 4 desc: MPU region number valid - ADDR: u27, // bit offset: 5 desc: Region base address field + /// MPU region field + REGION: u4 = 0, + /// MPU region number valid + VALID: u1 = 0, + /// Region base address field + ADDR: u27 = 0, }); - // byte offset: 16 MPU region attribute and size register + + /// MPU region attribute and size register pub const MPU_RASR = mmio(Address + 0x00000010, 32, packed struct { - ENABLE: u1, // bit offset: 0 desc: Region enable bit. - SIZE: u5, // bit offset: 1 desc: Size of the MPU protection region - reserved2: u1 = 0, - reserved1: u1 = 0, - SRD: u8, // bit offset: 8 desc: Subregion disable bits - B: u1, // bit offset: 16 desc: memory attribute - C: u1, // bit offset: 17 desc: memory attribute - S: u1, // bit offset: 18 desc: Shareable memory attribute - TEX: u3, // bit offset: 19 desc: memory attribute + /// Region enable bit. + ENABLE: u1 = 0, + /// Size of the MPU protection region + SIZE: u5 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Subregion disable bits + SRD: u8 = 0, + /// memory attribute + B: u1 = 0, + /// memory attribute + C: u1 = 0, + /// Shareable memory attribute + S: u1 = 0, + /// memory attribute + TEX: u3 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - AP: u3, // bit offset: 24 desc: Access permission + /// Access permission + AP: u3 = 0, reserved5: u1 = 0, - XN: u1, // bit offset: 28 desc: Instruction access disable bit + /// Instruction access disable bit + XN: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); }; + +/// SysTick timer pub const STK = extern struct { pub const Address: u32 = 0xe000e010; - // byte offset: 0 SysTick control and status register + + /// SysTick control and status register pub const CTRL = mmio(Address + 0x00000000, 32, packed struct { - ENABLE: u1, // bit offset: 0 desc: Counter enable - TICKINT: u1, // bit offset: 1 desc: SysTick exception request enable - CLKSOURCE: u1, // bit offset: 2 desc: Clock source selection + /// Counter enable + ENABLE: u1 = 0, + /// SysTick exception request enable + TICKINT: u1 = 0, + /// Clock source selection + CLKSOURCE: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, @@ -21849,7 +28749,6 @@ pub const STK = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - COUNTFLAG: u1, // bit offset: 16 desc: COUNTFLAG padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -21866,9 +28765,11 @@ pub const STK = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 SysTick reload value register + + /// SysTick reload value register pub const LOAD = mmio(Address + 0x00000004, 32, packed struct { - RELOAD: u24, // bit offset: 0 desc: RELOAD value + /// RELOAD value + RELOAD: u24 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -21878,9 +28779,11 @@ pub const STK = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 SysTick current value register + + /// SysTick current value register pub const VAL = mmio(Address + 0x00000008, 32, packed struct { - CURRENT: u24, // bit offset: 0 desc: Current counter value + /// Current counter value + CURRENT: u24 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -21890,51 +28793,74 @@ pub const STK = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 SysTick calibration value register + + /// SysTick calibration value register pub const CALIB = mmio(Address + 0x0000000c, 32, packed struct { - TENMS: u24, // bit offset: 0 desc: Calibration value + /// Calibration value + TENMS: u24 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - SKEW: u1, // bit offset: 30 desc: SKEW flag: Indicates whether the TENMS value is exact - NOREF: u1, // bit offset: 31 desc: NOREF flag. Reads as zero + /// SKEW flag: Indicates whether the TENMS value is exact + SKEW: u1 = 0, + /// NOREF flag. Reads as zero + NOREF: u1 = 0, }); }; + +/// System control block pub const SCB = extern struct { pub const Address: u32 = 0xe000ed00; - // byte offset: 0 CPUID base register + + /// CPUID base register pub const CPUID = mmio(Address + 0x00000000, 32, packed struct { - Revision: u4, // bit offset: 0 desc: Revision number - PartNo: u12, // bit offset: 4 desc: Part number of the processor - Constant: u4, // bit offset: 16 desc: Reads as 0xF - Variant: u4, // bit offset: 20 desc: Variant number - Implementer: u8, // bit offset: 24 desc: Implementer code + /// Revision number + Revision: u4 = 0, + /// Part number of the processor + PartNo: u12 = 0, + /// Reads as 0xF + Constant: u4 = 0, + /// Variant number + Variant: u4 = 0, + /// Implementer code + Implementer: u8 = 0, }); - // byte offset: 4 Interrupt control and state register + + /// Interrupt control and state register pub const ICSR = mmio(Address + 0x00000004, 32, packed struct { - VECTACTIVE: u9, // bit offset: 0 desc: Active vector + /// Active vector + VECTACTIVE: u9 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - RETTOBASE: u1, // bit offset: 11 desc: Return to base level - VECTPENDING: u7, // bit offset: 12 desc: Pending vector + /// Return to base level + RETTOBASE: u1 = 0, + /// Pending vector + VECTPENDING: u7 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - ISRPENDING: u1, // bit offset: 22 desc: Interrupt pending flag + /// Interrupt pending flag + ISRPENDING: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, - PENDSTCLR: u1, // bit offset: 25 desc: SysTick exception clear-pending bit - PENDSTSET: u1, // bit offset: 26 desc: SysTick exception set-pending bit - PENDSVCLR: u1, // bit offset: 27 desc: PendSV clear-pending bit - PENDSVSET: u1, // bit offset: 28 desc: PendSV set-pending bit + /// SysTick exception clear-pending bit + PENDSTCLR: u1 = 0, + /// SysTick exception set-pending bit + PENDSTSET: u1 = 0, + /// PendSV clear-pending bit + PENDSVCLR: u1 = 0, + /// PendSV set-pending bit + PENDSVSET: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, - NMIPENDSET: u1, // bit offset: 31 desc: NMI set-pending bit. + /// NMI set-pending bit. + NMIPENDSET: u1 = 0, }); - // byte offset: 8 Vector table offset register + + /// Vector table offset register pub const VTOR = mmio(Address + 0x00000008, 32, packed struct { reserved9: u1 = 0, reserved8: u1 = 0, @@ -21945,35 +28871,33 @@ pub const SCB = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TBLOFF: u21, // bit offset: 9 desc: Vector table base offset field + /// Vector table base offset field + TBLOFF: u21 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Application interrupt and reset control register + + /// Application interrupt and reset control register pub const AIRCR = mmio(Address + 0x0000000c, 32, packed struct { - VECTRESET: u1, // bit offset: 0 desc: VECTRESET - VECTCLRACTIVE: u1, // bit offset: 1 desc: VECTCLRACTIVE - SYSRESETREQ: u1, // bit offset: 2 desc: SYSRESETREQ reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - PRIGROUP: u3, // bit offset: 8 desc: PRIGROUP reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, - ENDIANESS: u1, // bit offset: 15 desc: ENDIANESS - VECTKEYSTAT: u16, // bit offset: 16 desc: Register key + /// Register key + VECTKEYSTAT: u16 = 0, }); - // byte offset: 16 System control register + + /// System control register pub const SCR = mmio(Address + 0x00000010, 32, packed struct { reserved1: u1 = 0, - SLEEPONEXIT: u1, // bit offset: 1 desc: SLEEPONEXIT - SLEEPDEEP: u1, // bit offset: 2 desc: SLEEPDEEP reserved2: u1 = 0, - SEVEONPEND: u1, // bit offset: 4 desc: Send Event on Pending bit + /// Send Event on Pending bit + SEVEONPEND: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -22002,18 +28926,17 @@ pub const SCB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Configuration and control register + + /// Configuration and control register pub const CCR = mmio(Address + 0x00000014, 32, packed struct { - NONBASETHRDENA: u1, // bit offset: 0 desc: Configures how the processor enters Thread mode - USERSETMPEND: u1, // bit offset: 1 desc: USERSETMPEND + /// Configures how the processor enters Thread mode + NONBASETHRDENA: u1 = 0, reserved1: u1 = 0, - UNALIGN__TRP: u1, // bit offset: 3 desc: UNALIGN_ TRP - DIV_0_TRP: u1, // bit offset: 4 desc: DIV_0_TRP + /// UNALIGN_ TRP + UNALIGN__TRP: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - BFHFNMIGN: u1, // bit offset: 8 desc: BFHFNMIGN - STKALIGN: u1, // bit offset: 9 desc: STKALIGN padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -22037,11 +28960,15 @@ pub const SCB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 System handler priority registers + + /// System handler priority registers pub const SHPR1 = mmio(Address + 0x00000018, 32, packed struct { - PRI_4: u8, // bit offset: 0 desc: Priority of system handler 4 - PRI_5: u8, // bit offset: 8 desc: Priority of system handler 5 - PRI_6: u8, // bit offset: 16 desc: Priority of system handler 6 + /// Priority of system handler 4 + PRI_4: u8 = 0, + /// Priority of system handler 5 + PRI_5: u8 = 0, + /// Priority of system handler 6 + PRI_6: u8 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -22051,7 +28978,8 @@ pub const SCB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 System handler priority registers + + /// System handler priority registers pub const SHPR2 = mmio(Address + 0x0000001c, 32, packed struct { reserved24: u1 = 0, reserved23: u1 = 0, @@ -22077,9 +29005,11 @@ pub const SCB = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - PRI_11: u8, // bit offset: 24 desc: Priority of system handler 11 + /// Priority of system handler 11 + PRI_11: u8 = 0, }); - // byte offset: 32 System handler priority registers + + /// System handler priority registers pub const SHPR3 = mmio(Address + 0x00000020, 32, packed struct { reserved16: u1 = 0, reserved15: u1 = 0, @@ -22097,30 +29027,47 @@ pub const SCB = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - PRI_14: u8, // bit offset: 16 desc: Priority of system handler 14 - PRI_15: u8, // bit offset: 24 desc: Priority of system handler 15 + /// Priority of system handler 14 + PRI_14: u8 = 0, + /// Priority of system handler 15 + PRI_15: u8 = 0, }); - // byte offset: 36 System handler control and state register + + /// System handler control and state register pub const SHCRS = mmio(Address + 0x00000024, 32, packed struct { - MEMFAULTACT: u1, // bit offset: 0 desc: Memory management fault exception active bit - BUSFAULTACT: u1, // bit offset: 1 desc: Bus fault exception active bit + /// Memory management fault exception active bit + MEMFAULTACT: u1 = 0, + /// Bus fault exception active bit + BUSFAULTACT: u1 = 0, reserved1: u1 = 0, - USGFAULTACT: u1, // bit offset: 3 desc: Usage fault exception active bit + /// Usage fault exception active bit + USGFAULTACT: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - SVCALLACT: u1, // bit offset: 7 desc: SVC call active bit - MONITORACT: u1, // bit offset: 8 desc: Debug monitor active bit + /// SVC call active bit + SVCALLACT: u1 = 0, + /// Debug monitor active bit + MONITORACT: u1 = 0, reserved5: u1 = 0, - PENDSVACT: u1, // bit offset: 10 desc: PendSV exception active bit - SYSTICKACT: u1, // bit offset: 11 desc: SysTick exception active bit - USGFAULTPENDED: u1, // bit offset: 12 desc: Usage fault exception pending bit - MEMFAULTPENDED: u1, // bit offset: 13 desc: Memory management fault exception pending bit - BUSFAULTPENDED: u1, // bit offset: 14 desc: Bus fault exception pending bit - SVCALLPENDED: u1, // bit offset: 15 desc: SVC call pending bit - MEMFAULTENA: u1, // bit offset: 16 desc: Memory management fault enable bit - BUSFAULTENA: u1, // bit offset: 17 desc: Bus fault enable bit - USGFAULTENA: u1, // bit offset: 18 desc: Usage fault enable bit + /// PendSV exception active bit + PENDSVACT: u1 = 0, + /// SysTick exception active bit + SYSTICKACT: u1 = 0, + /// Usage fault exception pending bit + USGFAULTPENDED: u1 = 0, + /// Memory management fault exception pending bit + MEMFAULTPENDED: u1 = 0, + /// Bus fault exception pending bit + BUSFAULTPENDED: u1 = 0, + /// SVC call pending bit + SVCALLPENDED: u1 = 0, + /// Memory management fault enable bit + MEMFAULTENA: u1 = 0, + /// Bus fault enable bit + BUSFAULTENA: u1 = 0, + /// Usage fault enable bit + USGFAULTENA: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -22135,34 +29082,51 @@ pub const SCB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 Configurable fault status register + + /// Configurable fault status register pub const CFSR_UFSR_BFSR_MMFSR = mmio(Address + 0x00000028, 32, packed struct { reserved1: u1 = 0, - IACCVIOL: u1, // bit offset: 1 desc: Instruction access violation flag + /// Instruction access violation flag + IACCVIOL: u1 = 0, reserved2: u1 = 0, - MUNSTKERR: u1, // bit offset: 3 desc: Memory manager fault on unstacking for a return from exception - MSTKERR: u1, // bit offset: 4 desc: Memory manager fault on stacking for exception entry. - MLSPERR: u1, // bit offset: 5 desc: MLSPERR + /// Memory manager fault on unstacking for a return from exception + MUNSTKERR: u1 = 0, + /// Memory manager fault on stacking for exception entry. + MSTKERR: u1 = 0, reserved3: u1 = 0, - MMARVALID: u1, // bit offset: 7 desc: Memory Management Fault Address Register (MMAR) valid flag - IBUSERR: u1, // bit offset: 8 desc: Instruction bus error - PRECISERR: u1, // bit offset: 9 desc: Precise data bus error - IMPRECISERR: u1, // bit offset: 10 desc: Imprecise data bus error - UNSTKERR: u1, // bit offset: 11 desc: Bus fault on unstacking for a return from exception - STKERR: u1, // bit offset: 12 desc: Bus fault on stacking for exception entry - LSPERR: u1, // bit offset: 13 desc: Bus fault on floating-point lazy state preservation + /// Memory Management Fault Address Register (MMAR) valid flag + MMARVALID: u1 = 0, + /// Instruction bus error + IBUSERR: u1 = 0, + /// Precise data bus error + PRECISERR: u1 = 0, + /// Imprecise data bus error + IMPRECISERR: u1 = 0, + /// Bus fault on unstacking for a return from exception + UNSTKERR: u1 = 0, + /// Bus fault on stacking for exception entry + STKERR: u1 = 0, + /// Bus fault on floating-point lazy state preservation + LSPERR: u1 = 0, reserved4: u1 = 0, - BFARVALID: u1, // bit offset: 15 desc: Bus Fault Address Register (BFAR) valid flag - UNDEFINSTR: u1, // bit offset: 16 desc: Undefined instruction usage fault - INVSTATE: u1, // bit offset: 17 desc: Invalid state usage fault - INVPC: u1, // bit offset: 18 desc: Invalid PC load usage fault - NOCP: u1, // bit offset: 19 desc: No coprocessor usage fault. + /// Bus Fault Address Register (BFAR) valid flag + BFARVALID: u1 = 0, + /// Undefined instruction usage fault + UNDEFINSTR: u1 = 0, + /// Invalid state usage fault + INVSTATE: u1 = 0, + /// Invalid PC load usage fault + INVPC: u1 = 0, + /// No coprocessor usage fault. + NOCP: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - UNALIGNED: u1, // bit offset: 24 desc: Unaligned access usage fault - DIVBYZERO: u1, // bit offset: 25 desc: Divide by zero usage fault + /// Unaligned access usage fault + UNALIGNED: u1 = 0, + /// Divide by zero usage fault + DIVBYZERO: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, @@ -22170,10 +29134,12 @@ pub const SCB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 Hard fault status register + + /// Hard fault status register pub const HFSR = mmio(Address + 0x0000002c, 32, packed struct { reserved1: u1 = 0, - VECTTBL: u1, // bit offset: 1 desc: Vector table hard fault + /// Vector table hard fault + VECTTBL: u1 = 0, reserved29: u1 = 0, reserved28: u1 = 0, reserved27: u1 = 0, @@ -22202,27 +29168,33 @@ pub const SCB = extern struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - FORCED: u1, // bit offset: 30 desc: Forced hard fault - DEBUG_VT: u1, // bit offset: 31 desc: Reserved for Debug use - }); - // byte offset: 52 Memory management fault address register - pub const MMFAR = mmio(Address + 0x00000034, 32, packed struct { - MMFAR: u32, // bit offset: 0 desc: Memory management fault address + /// Forced hard fault + FORCED: u1 = 0, + /// Reserved for Debug use + DEBUG_VT: u1 = 0, }); - // byte offset: 56 Bus fault address register - pub const BFAR = mmio(Address + 0x00000038, 32, packed struct { - BFAR: u32, // bit offset: 0 desc: Bus fault address - }); - // byte offset: 60 Auxiliary fault status register + + /// Memory management fault address register + pub const MMFAR = @intToPtr(*volatile u32, Address + 0x00000034); + + /// Bus fault address register + pub const BFAR = @intToPtr(*volatile u32, Address + 0x00000038); + + /// Auxiliary fault status register pub const AFSR = mmio(Address + 0x0000003c, 32, packed struct { - IMPDEF: u32, // bit offset: 0 desc: Implementation defined + /// Implementation defined + IMPDEF: u32 = 0, }); }; + +/// Nested vectored interrupt controller pub const NVIC_STIR = extern struct { pub const Address: u32 = 0xe000ef00; - // byte offset: 0 Software trigger interrupt register + + /// Software trigger interrupt register pub const STIR = mmio(Address + 0x00000000, 32, packed struct { - INTID: u9, // bit offset: 0 desc: Software generated interrupt ID + /// Software generated interrupt ID + INTID: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -22248,9 +29220,12 @@ pub const NVIC_STIR = extern struct { padding1: u1 = 0, }); }; + +/// Floating point unit CPACR pub const FPU_CPACR = extern struct { pub const Address: u32 = 0xe000ed88; - // byte offset: 0 Coprocessor access control register + + /// Coprocessor access control register pub const CPACR = mmio(Address + 0x00000000, 32, packed struct { reserved20: u1 = 0, reserved19: u1 = 0, @@ -22272,7 +29247,6 @@ pub const FPU_CPACR = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CP: u4, // bit offset: 20 desc: CP padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -22283,20 +29257,18 @@ pub const FPU_CPACR = extern struct { padding1: u1 = 0, }); }; + +/// System control block ACTLR pub const SCB_ACTRL = extern struct { pub const Address: u32 = 0xe000e008; - // byte offset: 0 Auxiliary control register + + /// Auxiliary control register pub const ACTRL = mmio(Address + 0x00000000, 32, packed struct { - DISMCYCINT: u1, // bit offset: 0 desc: DISMCYCINT - DISDEFWBUF: u1, // bit offset: 1 desc: DISDEFWBUF - DISFOLD: u1, // bit offset: 2 desc: DISFOLD reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DISFPCA: u1, // bit offset: 8 desc: DISFPCA - DISOOFP: u1, // bit offset: 9 desc: DISOOFP padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -22361,194 +29333,134 @@ pub const VectorTable = extern struct { /// Window Watchdog interrupt WWDG: InterruptVector = makeUnhandledHandler("WWDG"), - /// PVD through EXTI line detection interrupt PVD: InterruptVector = makeUnhandledHandler("PVD"), - /// Tamper and TimeStamp interrupts TAMP_STAMP: InterruptVector = makeUnhandledHandler("TAMP_STAMP"), - /// RTC Wakeup interrupt through the EXTI line RTC_WKUP: InterruptVector = makeUnhandledHandler("RTC_WKUP"), - /// Flash global interrupt FLASH: InterruptVector = makeUnhandledHandler("FLASH"), - /// RCC global interrupt RCC: InterruptVector = makeUnhandledHandler("RCC"), - /// EXTI Line0 interrupt EXTI0: InterruptVector = makeUnhandledHandler("EXTI0"), - /// EXTI Line3 interrupt EXTI1: InterruptVector = makeUnhandledHandler("EXTI1"), - /// EXTI Line2 and Touch sensing interrupts EXTI2_TSC: InterruptVector = makeUnhandledHandler("EXTI2_TSC"), - /// EXTI Line3 interrupt EXTI3: InterruptVector = makeUnhandledHandler("EXTI3"), - /// EXTI Line4 interrupt EXTI4: InterruptVector = makeUnhandledHandler("EXTI4"), - /// DMA1 channel 1 interrupt DMA1_CH1: InterruptVector = makeUnhandledHandler("DMA1_CH1"), - /// DMA1 channel 2 interrupt DMA1_CH2: InterruptVector = makeUnhandledHandler("DMA1_CH2"), - /// DMA1 channel 3 interrupt DMA1_CH3: InterruptVector = makeUnhandledHandler("DMA1_CH3"), - /// DMA1 channel 4 interrupt DMA1_CH4: InterruptVector = makeUnhandledHandler("DMA1_CH4"), - /// DMA1 channel 5 interrupt DMA1_CH5: InterruptVector = makeUnhandledHandler("DMA1_CH5"), - /// DMA1 channel 6 interrupt DMA1_CH6: InterruptVector = makeUnhandledHandler("DMA1_CH6"), - /// DMA1 channel 7interrupt DMA1_CH7: InterruptVector = makeUnhandledHandler("DMA1_CH7"), - /// ADC1 and ADC2 global interrupt ADC1_2: InterruptVector = makeUnhandledHandler("ADC1_2"), - /// USB High Priority/CAN_TX interrupts USB_HP_CAN_TX: InterruptVector = makeUnhandledHandler("USB_HP_CAN_TX"), - /// USB Low Priority/CAN_RX0 interrupts USB_LP_CAN_RX0: InterruptVector = makeUnhandledHandler("USB_LP_CAN_RX0"), - /// CAN_RX1 interrupt CAN_RX1: InterruptVector = makeUnhandledHandler("CAN_RX1"), - /// CAN_SCE interrupt CAN_SCE: InterruptVector = makeUnhandledHandler("CAN_SCE"), - /// EXTI Line5 to Line9 interrupts EXTI9_5: InterruptVector = makeUnhandledHandler("EXTI9_5"), - /// TIM1 Break/TIM15 global interruts TIM1_BRK_TIM15: InterruptVector = makeUnhandledHandler("TIM1_BRK_TIM15"), - /// TIM1 Update/TIM16 global interrupts TIM1_UP_TIM16: InterruptVector = makeUnhandledHandler("TIM1_UP_TIM16"), - /// TIM1 trigger and commutation/TIM17 interrupts TIM1_TRG_COM_TIM17: InterruptVector = makeUnhandledHandler("TIM1_TRG_COM_TIM17"), - /// TIM1 capture compare interrupt TIM1_CC: InterruptVector = makeUnhandledHandler("TIM1_CC"), - /// TIM2 global interrupt TIM2: InterruptVector = makeUnhandledHandler("TIM2"), - /// TIM3 global interrupt TIM3: InterruptVector = makeUnhandledHandler("TIM3"), - /// TIM4 global interrupt TIM4: InterruptVector = makeUnhandledHandler("TIM4"), - /// I2C1 event interrupt and EXTI Line23 interrupt I2C1_EV_EXTI23: InterruptVector = makeUnhandledHandler("I2C1_EV_EXTI23"), - /// I2C1 error interrupt I2C1_ER: InterruptVector = makeUnhandledHandler("I2C1_ER"), - /// I2C2 event interrupt & EXTI Line24 interrupt I2C2_EV_EXTI24: InterruptVector = makeUnhandledHandler("I2C2_EV_EXTI24"), - /// I2C2 error interrupt I2C2_ER: InterruptVector = makeUnhandledHandler("I2C2_ER"), - /// SPI1 global interrupt SPI1: InterruptVector = makeUnhandledHandler("SPI1"), - /// SPI2 global interrupt SPI2: InterruptVector = makeUnhandledHandler("SPI2"), - /// USART1 global interrupt and EXTI Line 25 interrupt USART1_EXTI25: InterruptVector = makeUnhandledHandler("USART1_EXTI25"), - /// USART2 global interrupt and EXTI Line 26 interrupt USART2_EXTI26: InterruptVector = makeUnhandledHandler("USART2_EXTI26"), - /// USART3 global interrupt and EXTI Line 28 interrupt USART3_EXTI28: InterruptVector = makeUnhandledHandler("USART3_EXTI28"), - /// EXTI Line15 to Line10 interrupts EXTI15_10: InterruptVector = makeUnhandledHandler("EXTI15_10"), - /// RTC alarm interrupt RTCAlarm: InterruptVector = makeUnhandledHandler("RTCAlarm"), - /// USB wakeup from Suspend USB_WKUP: InterruptVector = makeUnhandledHandler("USB_WKUP"), - /// TIM8 break interrupt TIM8_BRK: InterruptVector = makeUnhandledHandler("TIM8_BRK"), - /// TIM8 update interrupt TIM8_UP: InterruptVector = makeUnhandledHandler("TIM8_UP"), - /// TIM8 Trigger and commutation interrupts TIM8_TRG_COM: InterruptVector = makeUnhandledHandler("TIM8_TRG_COM"), - /// TIM8 capture compare interrupt TIM8_CC: InterruptVector = makeUnhandledHandler("TIM8_CC"), - /// ADC3 global interrupt ADC3: InterruptVector = makeUnhandledHandler("ADC3"), - /// FSMC global interrupt FMC: InterruptVector = makeUnhandledHandler("FMC"), reserved2: u32 = 0, reserved3: u32 = 0, - /// SPI3 global interrupt SPI3: InterruptVector = makeUnhandledHandler("SPI3"), - /// UART4 global and EXTI Line 34 interrupts UART4_EXTI34: InterruptVector = makeUnhandledHandler("UART4_EXTI34"), - /// UART5 global and EXTI Line 35 interrupts UART5_EXTI35: InterruptVector = makeUnhandledHandler("UART5_EXTI35"), - /// TIM6 global and DAC12 underrun interrupts TIM6_DACUNDER: InterruptVector = makeUnhandledHandler("TIM6_DACUNDER"), - /// TIM7 global interrupt TIM7: InterruptVector = makeUnhandledHandler("TIM7"), - /// DMA2 channel1 global interrupt DMA2_CH1: InterruptVector = makeUnhandledHandler("DMA2_CH1"), - /// DMA2 channel2 global interrupt DMA2_CH2: InterruptVector = makeUnhandledHandler("DMA2_CH2"), - /// DMA2 channel3 global interrupt DMA2_CH3: InterruptVector = makeUnhandledHandler("DMA2_CH3"), - /// DMA2 channel4 global interrupt DMA2_CH4: InterruptVector = makeUnhandledHandler("DMA2_CH4"), - /// DMA2 channel5 global interrupt DMA2_CH5: InterruptVector = makeUnhandledHandler("DMA2_CH5"), - /// ADC4 global interrupt ADC4: InterruptVector = makeUnhandledHandler("ADC4"), reserved4: u32 = 0, reserved5: u32 = 0, - - /// COMP1 & COMP2 & COMP3 interrupts combined with EXTI Lines 21, 22 and 29 interrupts + /// COMP1 & COMP2 & COMP3 interrupts combined with EXTI Lines 21, 22 and 29 + /// interrupts COMP123: InterruptVector = makeUnhandledHandler("COMP123"), - - /// COMP4 & COMP5 & COMP6 interrupts combined with EXTI Lines 30, 31 and 32 interrupts + /// COMP4 & COMP5 & COMP6 interrupts combined with EXTI Lines 30, 31 and 32 + /// interrupts COMP456: InterruptVector = makeUnhandledHandler("COMP456"), - /// COMP7 interrupt combined with EXTI Line 33 interrupt COMP7: InterruptVector = makeUnhandledHandler("COMP7"), reserved6: u32 = 0, @@ -22556,39 +29468,28 @@ pub const VectorTable = extern struct { reserved8: u32 = 0, reserved9: u32 = 0, reserved10: u32 = 0, - /// I2C3 Event interrupt I2C3_EV: InterruptVector = makeUnhandledHandler("I2C3_EV"), - /// I2C3 Error interrupt I2C3_ER: InterruptVector = makeUnhandledHandler("I2C3_ER"), - /// USB High priority interrupt USB_HP: InterruptVector = makeUnhandledHandler("USB_HP"), - /// USB Low priority interrupt USB_LP: InterruptVector = makeUnhandledHandler("USB_LP"), - /// USB wakeup from Suspend and EXTI Line 18 USB_WKUP_EXTI: InterruptVector = makeUnhandledHandler("USB_WKUP_EXTI"), - /// TIM20 Break interrupt TIM20_BRK: InterruptVector = makeUnhandledHandler("TIM20_BRK"), - /// TIM20 Upgrade interrupt TIM20_UP: InterruptVector = makeUnhandledHandler("TIM20_UP"), - /// TIM20 Trigger and Commutation interrupt TIM20_TRG_COM: InterruptVector = makeUnhandledHandler("TIM20_TRG_COM"), - /// TIM20 Capture Compare interrupt TIM20_CC: InterruptVector = makeUnhandledHandler("TIM20_CC"), - /// Floating point unit interrupt; Floating point interrupt FPU: InterruptVector = makeUnhandledHandler("FPU"), reserved11: u32 = 0, reserved12: u32 = 0, - /// SPI4 Global interrupt SPI4: InterruptVector = makeUnhandledHandler("SPI4"), }; @@ -22643,4 +29544,3 @@ export const vectors: VectorTable linksection("microzig_flash_start") = blk: { } break :blk temp; }; - diff --git a/src/tools/svd2zig.py b/src/tools/svd2zig.py index e7cf163..b13f673 100755 --- a/src/tools/svd2zig.py +++ b/src/tools/svd2zig.py @@ -2,8 +2,10 @@ import sys import subprocess import re +import textwrap from cmsis_svd.parser import SVDParser +import cmsis_svd.model as model def cleanup_description(description): @@ -12,12 +14,19 @@ def cleanup_description(description): return ' '.join(description.replace('\n', ' ').split()) +def comment_description(description): + if description is None: + return None + + description = ' '.join(description.replace('\n', ' ').split()) + return textwrap.fill(description, width=80, initial_indent='/// ', subsequent_indent='/// ') + -# register names in some SVDs are using foo[n] for registers names -# and also for some reaons there are string formatters like %s in the reigster names -NAME_REGEX = re.compile(r"\[([^\]]+)]") -def cleanup_name(name): - return NAME_REGEX.sub(r"_\1", name).replace("%", "_") +def escape_field(field): + if not field[0].isdigit() and re.match(r'^[A-Za-z0-9_]+$', field): + return field + else: + return f"@\"{field}\"" class MMIOFileGenerator: @@ -32,89 +41,217 @@ class MMIOFileGenerator: def generate_enumerated_field(self, field): ''' returns something like: - name: enum(u){ // bit offset: 0 desc: foo description + name: enum(u){ // foo description name = value, // desc: ... name = value, // desc: _, // non-exhustive }, ''' - field.description = cleanup_description(field.description) - self.write_line(f"{field.name}:enum(u{field.bit_width}){{// bit offset: {field.bit_offset} desc: {field.description}") - - total_fields_with_values = 0 - for e in field.enumerated_values: - e.description = cleanup_description(e.description) - if e.value is None or e.name == "RESERVED": - # reserved fields doesn't have a value so we have to comment them out - self.write_line(f"// @\"{e.name}\", // desc: {e.description}") - else: - total_fields_with_values = total_fields_with_values + 1 - self.write_line(f"@\"{e.name}\" = {e.value}, // desc: {e.description}") - - # if the fields doesn't use all possible values make the enum non-exhaustive - if total_fields_with_values < 2**field.bit_width: - self.write_line("_, // non-exhaustive") - - self.write_line("},") + description = comment_description(field.description) + self.write_line(description) + self.write_line(f"{field.name}: u{field.bit_width} = 0,") + + # TODO: turn enums back on later + #self.write_line(f"{field.name}:enum(u{field.bit_width}){{") + + #total_fields_with_values = 0 + #for e in field.enumerated_values: + # e.description = cleanup_description(e.description) + # if e.value is None or e.name == "RESERVED": + # # reserved fields doesn't have a value so we have to comment them out + # escaped_field_name = escape_field(e.name) + # self.write_line(f"// {escaped_field_name}, // {e.description}") + # else: + # total_fields_with_values = total_fields_with_values + 1 + # escaped_field_name = escape_field(e.name) + # if e.name != e.description: + # self.write_line(f"/// {e.description}") + # self.write_line(f"{escaped_field_name} = {e.value},") + + ## if the fields doesn't use all possible values make the enum non-exhaustive + #if total_fields_with_values < 2**field.bit_width: + # self.write_line("_, // non-exhaustive") + + #self.write_line("},") return field.bit_offset + field.bit_width def generate_register_field(self, field): ''' returns something like: - name: u, // bit offset: 0 desc: foo description + name: u, // foo description ''' - field.description = cleanup_description(field.description) - self.write_line(f"{field.name}:u{field.bit_width},// bit offset: {field.bit_offset} desc: {field.description}") + description = comment_description(field.description) + if field.name != field.description: + self.write_line(description) + self.write_line(f"{field.name}:u{field.bit_width} = 0,") + return field.bit_offset + field.bit_width - def generate_register_declaration(self, register): - ''' + def generate_fields(self, fields, size): + last_offset = 0 + reserved_index = 0 + for field in sorted(fields, key=lambda f: f.bit_offset): + # workaround for NXP SVD which has overleaping reserved fields + if field.name == "RESERVED": + self.write_line(f"// RESERVED: u{field.bit_width}, // {field.description}") + continue + + if last_offset != field.bit_offset: + reserved_size = field.bit_offset - last_offset + self.generate_padding(reserved_size, "reserved", reserved_index) + reserved_index += reserved_size + + if field.is_enumerated_type: + last_offset = self.generate_enumerated_field(field) + else: + last_offset = self.generate_register_field(field) + + if size is not None and size != last_offset: + self.generate_padding(size - last_offset, "padding", 0) - ''' - register.description = cleanup_description(register.description) - self.write_line(f"// byte offset: {register.address_offset} {register.description}") - register.name = cleanup_name(register.name) + def generate_register_declaration_manual(self, name, description, address_offset, fields, size): + num_fields = len(fields) + description = comment_description(description) + self.write_line("") + self.write_line(description) + if num_fields == 0 or (num_fields == 1 and fields[0].bit_width == 32 and name == fields[0].name): + # TODO: hardcoded 32 bit here + self.write_line(f"pub const {name} = @intToPtr(*volatile u{size}, Address + 0x{address_offset:08x});") + else: + self.write_line(f"pub const {name} = mmio(Address + 0x{address_offset:08x}, {size}, packed struct{{") + self.generate_fields(fields, size) + self.write_line("});") + + def generate_register_declaration(self, register): size = register.size if size == None: size = 32 # hack for now... - self.write_line(f" pub const {register.name} = mmio(Address + 0x{register.address_offset:08x}, {size}, packed struct{{") - last_offset = 0 - reserved_index = 0 - for field in sorted(register.fields, key=lambda f: f.bit_offset): - # workaround for NXP SVD which has overleaping reserved fields - if field.name == "RESERVED": - self.write_line(f"// RESERVED: u{field.bit_width}, // bit offset: {field.bit_offset} desc: {field.description}") - continue - - if last_offset != field.bit_offset: - reserved_size = field.bit_offset - last_offset - self.generate_padding(reserved_size, "reserved", reserved_index) - reserved_index = reserved_index + reserved_size - - if field.is_enumerated_type: - last_offset = self.generate_enumerated_field(field) - else: - last_offset = self.generate_register_field(field) + num_fields = len(register.fields) + description = comment_description(register.description) - if size is not None: - if len(register.fields) == 0: - self.write_line(f"raw: u{size}, // placeholder field") - else: - self.generate_padding(size - last_offset, "padding", 0) + self.write_line("") + self.write_line(description) + if num_fields == 0 or (num_fields == 1 and register.fields[0].bit_width == 32 and register.name == register.fields[0].name): + # TODO: hardcoded 32 bit here + self.write_line(f"pub const {register.name} = @intToPtr(*volatile u{size}, Address + 0x{register.address_offset:08x});") + else: + self.write_line(f"pub const {register.name} = mmio(Address + 0x{register.address_offset:08x}, {size}, packed struct{{") + self.generate_fields(register.fields, size) + self.write_line("});") + + def generate_register_cluster(self, cluster): + if cluster.derived_from is not None: + raise Exception("TODO: derived_from") - self.write_line("});") + self.write_line("") + self.write_line(f"pub const {cluster.name} = struct {{") + for register in cluster._register: + if isinstance(register, model.SVDRegisterArray): + self.generate_register_array(register) + elif isinstance(register, model.SVDRegister): + self.generate_register_declaration(register) + + + self.write_line("};") + + def generate_register_cluster_array(self, cluster): + max_fields = int(cluster.dim_increment / 4) + if len(cluster._register) > max_fields: + raise Exception("not enough room for fields") + + name = cluster.name.replace("[%s]", "") + self.write_line(f"pub const {name} = @intToPtr(*volatile [{cluster.dim}]packed struct {{") + for register in cluster._register: + + size = register.size + if size == None: + size = 32 # hack for now... + last_offset = 0 + reserved_index = 0 + + if size != 32: + raise Exception("TODO: handle registers that are not 32-bit") + + description = comment_description(register.description) - def generate_peripherial_declaration(self, peripherial): - # TODO: write peripherial description - self.write_line(f"pub const {peripherial.name} = extern struct {{") - self.write_line(f"pub const Address: u32 = 0x{peripherial.base_address:08x};") + self.write_line("") + self.write_line(description) + if len(register.fields) == 0 or (len(register.fields) == 1 and register.fields[0].bit_width == size and register.name == register.fields[0].name): + self.write_line(f"{register.name}: u{size},") + else: + self.write_line(register.name + f": MMIO({size}, packed struct {{") + self.generate_fields(register.fields, size) + self.write_line("}),") + + + for i in range(0, max_fields - len(cluster._register)): + self.write_line(f" padding{i}: u32,") + + # TODO: this would be cleaner, but we'll probably run into packed struct bugs + #num_bits = size * (max_fields - len(cluster._register)) + #self.write_line(f"_: u{num_bits},") + + self.write_line(f" }}, Address + 0x{cluster.address_offset:08x});") + + + # TODO: calculate size in here, fine since everything we're working with rn is 32 bit + def generate_register_array(self, register_array): + description = comment_description(register_array.description) + + if register_array.dim_indices.start != 0 or ("%s" in register_array.name and not "[%s]" in register_array.name): + for i in register_array.dim_indices: + fmt = register_array.name.replace("%s", "{}") + name = fmt.format(i) + self.generate_register_declaration_manual(name, + register_array.description, + register_array.address_offset + (i * register_array.dim_increment), + register_array._fields, + 32) + return + + if register_array.dim_increment != 4: + raise Exception("TODO register " + register_array.name + " dim_increment != 4" + ", it is " + str(register_array.dim_increment)) + + name = register_array.name.replace("%s", "").replace("[]", "") + self.write_line(description) + num_fields = len(register_array._fields) + + # TODO: hardcoded 32 bit here + if num_fields == 0 or (num_fields == 1 and register_array._fields[0].bit_width == 32 and name == register_array._fields[0].name): + + # TODO: hardcoded 32 bit here + self.write_line(f"pub const {name} = @intToPtr(*volatile [{register_array.dim}]u32, Address + 0x{register_array.address_offset:08x});") + else: + self.write_line(f"pub const {name} = @intToPtr(*volatile [{register_array.dim}]MMIO(32, packed struct {{") + self.generate_fields(register_array._fields, 32) + + self.write_line(f"}}), Address + 0x{register_array.address_offset:08x});") + + def generate_peripheral_declaration(self, peripheral): + description = comment_description(peripheral.description) + self.write_line("") + self.write_line(description) + self.write_line(f"pub const {peripheral.name} = extern struct {{") + self.write_line(f"pub const Address: u32 = 0x{peripheral.base_address:08x};") - for register in sorted(peripherial.registers, key=lambda f: f.address_offset): + for register in sorted(peripheral._lookup_possibly_derived_attribute('registers'), key=lambda f: f.address_offset): self.generate_register_declaration(register) + for register_array in sorted(peripheral._lookup_possibly_derived_attribute('register_arrays'), key=lambda f: f.address_offset): + self.generate_register_array(register_array) + + for cluster in sorted(peripheral._lookup_possibly_derived_attribute('clusters'), key=lambda f: f.address_offset): + if isinstance(cluster, model.SVDRegisterCluster): + self.generate_register_cluster(cluster) + elif isinstance(cluster, model.SVDRegisterClusterArray): + #self.generate_register_cluster_array(cluster) + pass + else: + raise Exception("unhandled cluster type") + self.write_line("};") # TODO: descriptions on system interrupts/exceptions, turn on system interrupts/exceptions @@ -172,7 +309,8 @@ pub const VectorTable = extern struct { reserved_count += 1 if interrupt.description is not None: - self.write_line(f"\n /// {interrupt.description}") + description = comment_description(interrupt.description) + self.write_line(description) self.write_line(f" {interrupt.name}: InterruptVector = makeUnhandledHandler(\"{interrupt.name}\"),") expected_next_value += 1 self.write_line("};") @@ -235,11 +373,14 @@ export const vectors: VectorTable linksection(\"microzig_flash_start\") = blk: { self.write_line("// generated using svd2zig.py\n// DO NOT EDIT") self.write_line(f"// based on {device.name} version {device.version}") - self.write_line("const mmio = @import(\"microzig-mmio\").mmio;") + + self.write_line("const microzig_mmio = @import(\"microzig-mmio\");") + self.write_line("const mmio = microzig_mmio.mmio;") + self.write_line("const MMIO = microzig_mmio.MMIO;") self.write_line(f"const Name = \"{device.name}\";") interrupts = {} for peripheral in device.peripherals: - self.generate_peripherial_declaration(peripheral) + self.generate_peripheral_declaration(peripheral) if peripheral.interrupts != None: for interrupt in peripheral.interrupts: if interrupt.value in interrupts and interrupts[interrupt.value].description != interrupt.description: @@ -262,16 +403,8 @@ def main(): parser = SVDParser.for_packaged_svd(sys.argv[1], sys.argv[2] + '.svd') device = parser.get_device() - zig_fmt = subprocess.Popen(('zig', 'fmt', '--stdin'), stdin=subprocess.PIPE, - stdout=subprocess.PIPE, encoding='utf8') - - generator = MMIOFileGenerator(zig_fmt.stdin) + generator = MMIOFileGenerator(sys.stdout) generator.generate_file(device) - zig_fmt.stdin.flush() - zig_fmt.stdin.close() - print(zig_fmt.stdout.read()) - - if __name__ == "__main__": main()