From 873e5995b65c0515b5db3f088f92d2cfd60e6b53 Mon Sep 17 00:00:00 2001 From: Riccardo Binetti Date: Fri, 1 Apr 2022 02:45:50 +0200 Subject: [PATCH] Add initial support for the stm32f429idiscovery eval board (#38) * Add stm32f429 registers Generated using regz with: ./regz STM32F429.svd > registers.zig Using this SVD: https://github.com/posborne/cmsis-svd/blob/871761af63200f5edad553b03fe0482113ac6a60/data/STMicro/STM32F429.svd * Add initial support for the stm32f429idiscovery eval board Blinky example working on the board --- build.zig | 1 + src/modules/boards.zig | 6 + .../stm32f429idiscovery.zig | 15 + src/modules/chips.zig | 12 + src/modules/chips/stm32f429/registers.zig | 53887 ++++++++++++++++ src/modules/chips/stm32f429/stm32f429.zig | 78 + tests/blinky.zig | 1 + 7 files changed, 54000 insertions(+) create mode 100644 src/modules/boards/stm32f429idiscovery/stm32f429idiscovery.zig create mode 100644 src/modules/chips/stm32f429/registers.zig create mode 100644 src/modules/chips/stm32f429/stm32f429.zig diff --git a/build.zig b/build.zig index bb60c58..c63cb0f 100644 --- a/build.zig +++ b/build.zig @@ -23,6 +23,7 @@ pub fn build(b: *std.build.Builder) !void { //BuildConfig{ .name = "chips.stm32f103x8", .backing = Backing{ .chip = chips.stm32f103x8 } }, BuildConfig{ .name = "boards.stm32f3discovery", .backing = Backing{ .board = boards.stm32f3discovery }, .supports_uart_test = false }, BuildConfig{ .name = "boards.stm32f4discovery", .backing = Backing{ .board = boards.stm32f4discovery }, .supports_uart_test = false }, + BuildConfig{ .name = "boards.stm32f429idiscovery", .backing = Backing{ .board = boards.stm32f429idiscovery }, .supports_uart_test = false }, }; const Test = struct { name: []const u8, source: []const u8, uses_uart: bool = false, on_avr: bool = true }; diff --git a/src/modules/boards.zig b/src/modules/boards.zig index 954cd4b..6793a7b 100644 --- a/src/modules/boards.zig +++ b/src/modules/boards.zig @@ -31,3 +31,9 @@ pub const stm32f4discovery = Board{ .path = root_path ++ "boards/stm32f4discovery/stm32f4discovery.zig", .chip = chips.stm32f407vg, }; + +pub const stm32f429idiscovery = Board{ + .name = "STM32F429IDISCOVERY", + .path = root_path ++ "boards/stm32f429idiscovery/stm32f429idiscovery.zig", + .chip = chips.stm32f429zit6u, +}; diff --git a/src/modules/boards/stm32f429idiscovery/stm32f429idiscovery.zig b/src/modules/boards/stm32f429idiscovery/stm32f429idiscovery.zig new file mode 100644 index 0000000..35418d6 --- /dev/null +++ b/src/modules/boards/stm32f429idiscovery/stm32f429idiscovery.zig @@ -0,0 +1,15 @@ +pub const chip = @import("chip"); +pub const micro = @import("microzig"); + +pub const cpu_frequency = 16_000_000; + +pub const pin_map = .{ + // LEDs, connected to GPIOG bits 13, 14 + // green + .@"LD3" = "PG13", + // red + .@"LD4" = "PG14", + + // User button + .@"B1" = "PA0", +}; diff --git a/src/modules/chips.zig b/src/modules/chips.zig index 52504d5..5a2d5a0 100644 --- a/src/modules/chips.zig +++ b/src/modules/chips.zig @@ -62,6 +62,18 @@ pub const stm32f407vg = Chip{ }, }; +pub const stm32f429zit6u = Chip{ + .name = "STM32F429ZIT6U", + .path = root_path ++ "chips/stm32f429/stm32f429.zig", + .cpu = cpus.cortex_m4, + .memory_regions = &.{ + MemoryRegion{ .offset = 0x08000000, .length = 2048 * 1024, .kind = .flash }, + MemoryRegion{ .offset = 0x20000000, .length = 192 * 1024, .kind = .ram }, + // CCM RAM + MemoryRegion{ .offset = 0x10000000, .length = 64 * 1024, .kind = .ram }, + }, +}; + pub const nrf52832 = Chip{ .name = "nRF52832", .path = root_path ++ "chips/nrf52/nrf52.zig", diff --git a/src/modules/chips/stm32f429/registers.zig b/src/modules/chips/stm32f429/registers.zig new file mode 100644 index 0000000..7bd4b62 --- /dev/null +++ b/src/modules/chips/stm32f429/registers.zig @@ -0,0 +1,53887 @@ +// this file was generated by regz: https://github.com/ZigEmbeddedGroup/regz +// commit: 6376709051af4d8920d5c8bb48945ca688af32ae +// +// device: STM32F429 +// cpu: CM4 + +pub const VectorTable = extern struct { + initial_stack_pointer: u32, + Reset: InterruptVector = unhandled, + NMI: InterruptVector = unhandled, + HardFault: InterruptVector = unhandled, + MemManage: InterruptVector = unhandled, + BusFault: InterruptVector = unhandled, + UsageFault: InterruptVector = unhandled, + reserved0: [4]u32 = undefined, + SVCall: InterruptVector = unhandled, + reserved1: [2]u32 = undefined, + PendSV: InterruptVector = unhandled, + SysTick: InterruptVector = unhandled, + /// Window Watchdog interrupt + WWDG: InterruptVector = unhandled, + /// PVD through EXTI line detection + /// interrupt + PVD: InterruptVector = unhandled, + /// Tamper and TimeStamp interrupts through the + /// EXTI line + TAMP_STAMP: InterruptVector = unhandled, + /// RTC Wakeup interrupt through the EXTI + /// line + RTC_WKUP: InterruptVector = unhandled, + /// Flash global interrupt + FLASH: InterruptVector = unhandled, + /// RCC global interrupt + RCC: InterruptVector = unhandled, + /// EXTI Line0 interrupt + EXTI0: InterruptVector = unhandled, + /// EXTI Line1 interrupt + EXTI1: InterruptVector = unhandled, + /// EXTI Line2 interrupt + EXTI2: InterruptVector = unhandled, + /// EXTI Line3 interrupt + EXTI3: InterruptVector = unhandled, + /// EXTI Line4 interrupt + EXTI4: InterruptVector = unhandled, + /// DMA1 Stream0 global interrupt + DMA1_Stream0: InterruptVector = unhandled, + /// DMA1 Stream1 global interrupt + DMA1_Stream1: InterruptVector = unhandled, + /// DMA1 Stream2 global interrupt + DMA1_Stream2: InterruptVector = unhandled, + /// DMA1 Stream3 global interrupt + DMA1_Stream3: InterruptVector = unhandled, + /// DMA1 Stream4 global interrupt + DMA1_Stream4: InterruptVector = unhandled, + /// DMA1 Stream5 global interrupt + DMA1_Stream5: InterruptVector = unhandled, + /// DMA1 Stream6 global interrupt + DMA1_Stream6: InterruptVector = unhandled, + /// ADC2 global interrupts + ADC: InterruptVector = unhandled, + /// CAN1 TX interrupts + CAN1_TX: InterruptVector = unhandled, + /// CAN1 RX0 interrupts + CAN1_RX0: InterruptVector = unhandled, + /// CAN1 RX1 interrupts + CAN1_RX1: InterruptVector = unhandled, + /// CAN1 SCE interrupt + CAN1_SCE: InterruptVector = unhandled, + /// EXTI Line[9:5] interrupts + EXTI9_5: InterruptVector = unhandled, + /// TIM1 Break interrupt and TIM9 global + /// interrupt + TIM1_BRK_TIM9: InterruptVector = unhandled, + /// TIM1 Update interrupt and TIM10 global + /// interrupt + TIM1_UP_TIM10: InterruptVector = unhandled, + /// TIM1 Trigger and Commutation interrupts and + /// TIM11 global interrupt + TIM1_TRG_COM_TIM11: InterruptVector = unhandled, + /// TIM1 Capture Compare interrupt + TIM1_CC: InterruptVector = unhandled, + /// TIM2 global interrupt + TIM2: InterruptVector = unhandled, + /// TIM3 global interrupt + TIM3: InterruptVector = unhandled, + /// TIM4 global interrupt + TIM4: InterruptVector = unhandled, + /// I2C1 event interrupt + I2C1_EV: InterruptVector = unhandled, + /// I2C1 error interrupt + I2C1_ER: InterruptVector = unhandled, + /// I2C2 event interrupt + I2C2_EV: InterruptVector = unhandled, + /// I2C2 error interrupt + I2C2_ER: InterruptVector = unhandled, + /// SPI1 global interrupt + SPI1: InterruptVector = unhandled, + /// SPI2 global interrupt + SPI2: InterruptVector = unhandled, + /// USART1 global interrupt + USART1: InterruptVector = unhandled, + /// USART2 global interrupt + USART2: InterruptVector = unhandled, + /// USART3 global interrupt + USART3: InterruptVector = unhandled, + /// EXTI Line[15:10] interrupts + EXTI15_10: InterruptVector = unhandled, + /// RTC Alarms (A and B) through EXTI line + /// interrupt + RTC_Alarm: InterruptVector = unhandled, + /// USB On-The-Go FS Wakeup through EXTI line + /// interrupt + OTG_FS_WKUP: InterruptVector = unhandled, + /// TIM8 Break interrupt and TIM12 global + /// interrupt + TIM8_BRK_TIM12: InterruptVector = unhandled, + /// TIM8 Update interrupt and TIM13 global + /// interrupt + TIM8_UP_TIM13: InterruptVector = unhandled, + /// TIM8 Trigger and Commutation interrupts and + /// TIM14 global interrupt + TIM8_TRG_COM_TIM14: InterruptVector = unhandled, + /// TIM8 Capture Compare interrupt + TIM8_CC: InterruptVector = unhandled, + /// DMA1 Stream7 global interrupt + DMA1_Stream7: InterruptVector = unhandled, + /// FMC global interrupt + FMC: InterruptVector = unhandled, + /// SDIO global interrupt + SDIO: InterruptVector = unhandled, + /// TIM5 global interrupt + TIM5: InterruptVector = unhandled, + /// SPI3 global interrupt + SPI3: InterruptVector = unhandled, + /// UART4 global interrupt + UART4: InterruptVector = unhandled, + /// UART5 global interrupt + UART5: InterruptVector = unhandled, + /// TIM6 global interrupt, DAC1 and DAC2 underrun + /// error interrupt + TIM6_DAC: InterruptVector = unhandled, + /// TIM7 global interrupt + TIM7: InterruptVector = unhandled, + /// DMA2 Stream0 global interrupt + DMA2_Stream0: InterruptVector = unhandled, + /// DMA2 Stream1 global interrupt + DMA2_Stream1: InterruptVector = unhandled, + /// DMA2 Stream2 global interrupt + DMA2_Stream2: InterruptVector = unhandled, + /// DMA2 Stream3 global interrupt + DMA2_Stream3: InterruptVector = unhandled, + /// DMA2 Stream4 global interrupt + DMA2_Stream4: InterruptVector = unhandled, + /// Ethernet global interrupt + ETH: InterruptVector = unhandled, + /// Ethernet Wakeup through EXTI line + /// interrupt + ETH_WKUP: InterruptVector = unhandled, + /// CAN2 TX interrupts + CAN2_TX: InterruptVector = unhandled, + /// CAN2 RX0 interrupts + CAN2_RX0: InterruptVector = unhandled, + /// CAN2 RX1 interrupts + CAN2_RX1: InterruptVector = unhandled, + /// CAN2 SCE interrupt + CAN2_SCE: InterruptVector = unhandled, + /// USB On The Go FS global + /// interrupt + OTG_FS: InterruptVector = unhandled, + /// DMA2 Stream5 global interrupt + DMA2_Stream5: InterruptVector = unhandled, + /// DMA2 Stream6 global interrupt + DMA2_Stream6: InterruptVector = unhandled, + /// DMA2 Stream7 global interrupt + DMA2_Stream7: InterruptVector = unhandled, + /// USART6 global interrupt + USART6: InterruptVector = unhandled, + /// I2C3 event interrupt + I2C3_EV: InterruptVector = unhandled, + /// I2C3 error interrupt + I2C3_ER: InterruptVector = unhandled, + /// USB On The Go HS End Point 1 Out global + /// interrupt + OTG_HS_EP1_OUT: InterruptVector = unhandled, + /// USB On The Go HS End Point 1 In global + /// interrupt + OTG_HS_EP1_IN: InterruptVector = unhandled, + /// USB On The Go HS Wakeup through EXTI + /// interrupt + OTG_HS_WKUP: InterruptVector = unhandled, + /// USB On The Go HS global + /// interrupt + OTG_HS: InterruptVector = unhandled, + /// DCMI global interrupt + DCMI: InterruptVector = unhandled, + /// CRYP crypto global interrupt + CRYP: InterruptVector = unhandled, + /// Hash and Rng global interrupt + HASH_RNG: InterruptVector = unhandled, + /// FPU interrupt + FPU: InterruptVector = unhandled, + /// UART 7 global interrupt + UART7: InterruptVector = unhandled, + /// UART 8 global interrupt + UART8: InterruptVector = unhandled, + /// SPI 4 global interrupt + SPI4: InterruptVector = unhandled, + /// SPI 5 global interrupt + SPI5: InterruptVector = unhandled, + /// SPI 6 global interrupt + SPI6: InterruptVector = unhandled, + /// SAI1 global interrupt + SAI1: InterruptVector = unhandled, + /// LTDC global interrupt + LCD_TFT: InterruptVector = unhandled, + /// LTDC global error interrupt + LCD_TFT_1: InterruptVector = unhandled, + /// DMA2D global interrupt + DMA2D: InterruptVector = unhandled, +}; + +pub const registers = struct { + + /// Random number generator + pub const RNG = struct { + pub const base_address = 0x50060800; + + /// address: 0x50060800 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + /// Random number generator + /// enable + RNGEN: u1, + /// Interrupt enable + IE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x0); + + /// address: 0x50060804 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Data ready + DRDY: u1, + /// Clock error current status + CECS: u1, + /// Seed error current status + SECS: u1, + reserved0: u1, + reserved1: u1, + /// Clock error interrupt + /// status + CEIS: u1, + /// Seed error interrupt + /// status + SEIS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x50060808 + /// data register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { + /// Random data + RNDATA: u32, + }), base_address + 0x8); + }; + + /// Hash processor + pub const HASH = struct { + pub const base_address = 0x50060400; + + /// address: 0x50060400 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + /// Initialize message digest + /// calculation + INIT: u1, + /// DMA enable + DMAE: u1, + /// Data type selection + DATATYPE: u2, + /// Mode selection + MODE: u1, + /// Algorithm selection + ALGO0: u1, + /// Number of words already + /// pushed + NBW: u4, + /// DIN not empty + DINNE: u1, + /// Multiple DMA Transfers + MDMAT: u1, + reserved2: u1, + reserved3: u1, + /// Long key selection + LKEY: u1, + reserved4: u1, + /// ALGO + ALGO1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x0); + + /// address: 0x50060404 + /// data input register + pub const DIN = @intToPtr(*volatile Mmio(32, packed struct { + /// Data input + DATAIN: u32, + }), base_address + 0x4); + + /// address: 0x50060408 + /// start register + pub const STR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of valid bits in the last word of + /// the message + NBLW: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Digest calculation + DCAL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x5006040c + /// digest registers + pub const HR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// H0 + H0: u32, + }), base_address + 0xc); + + /// address: 0x50060410 + /// digest registers + pub const HR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// H1 + H1: u32, + }), base_address + 0x10); + + /// address: 0x50060414 + /// digest registers + pub const HR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// H2 + H2: u32, + }), base_address + 0x14); + + /// address: 0x50060418 + /// digest registers + pub const HR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// H3 + H3: u32, + }), base_address + 0x18); + + /// address: 0x5006041c + /// digest registers + pub const HR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// H4 + H4: u32, + }), base_address + 0x1c); + + /// address: 0x50060420 + /// interrupt enable register + pub const IMR = @intToPtr(*volatile Mmio(32, packed struct { + /// Data input interrupt + /// enable + DINIE: u1, + /// Digest calculation completion interrupt + /// enable + DCIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x20); + + /// address: 0x50060424 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Data input interrupt + /// status + DINIS: u1, + /// Digest calculation completion interrupt + /// status + DCIS: u1, + /// DMA Status + DMAS: u1, + /// Busy bit + BUSY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x24); + + /// address: 0x500604f8 + /// context swap registers + pub const CSR0 = @intToPtr(*volatile u32, base_address + 0xf8); + + /// address: 0x500604fc + /// context swap registers + pub const CSR1 = @intToPtr(*volatile u32, base_address + 0xfc); + + /// address: 0x50060500 + /// context swap registers + pub const CSR2 = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x50060504 + /// context swap registers + pub const CSR3 = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x50060508 + /// context swap registers + pub const CSR4 = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x5006050c + /// context swap registers + pub const CSR5 = @intToPtr(*volatile u32, base_address + 0x10c); + + /// address: 0x50060510 + /// context swap registers + pub const CSR6 = @intToPtr(*volatile u32, base_address + 0x110); + + /// address: 0x50060514 + /// context swap registers + pub const CSR7 = @intToPtr(*volatile u32, base_address + 0x114); + + /// address: 0x50060518 + /// context swap registers + pub const CSR8 = @intToPtr(*volatile u32, base_address + 0x118); + + /// address: 0x5006051c + /// context swap registers + pub const CSR9 = @intToPtr(*volatile u32, base_address + 0x11c); + + /// address: 0x50060520 + /// context swap registers + pub const CSR10 = @intToPtr(*volatile u32, base_address + 0x120); + + /// address: 0x50060524 + /// context swap registers + pub const CSR11 = @intToPtr(*volatile u32, base_address + 0x124); + + /// address: 0x50060528 + /// context swap registers + pub const CSR12 = @intToPtr(*volatile u32, base_address + 0x128); + + /// address: 0x5006052c + /// context swap registers + pub const CSR13 = @intToPtr(*volatile u32, base_address + 0x12c); + + /// address: 0x50060530 + /// context swap registers + pub const CSR14 = @intToPtr(*volatile u32, base_address + 0x130); + + /// address: 0x50060534 + /// context swap registers + pub const CSR15 = @intToPtr(*volatile u32, base_address + 0x134); + + /// address: 0x50060538 + /// context swap registers + pub const CSR16 = @intToPtr(*volatile u32, base_address + 0x138); + + /// address: 0x5006053c + /// context swap registers + pub const CSR17 = @intToPtr(*volatile u32, base_address + 0x13c); + + /// address: 0x50060540 + /// context swap registers + pub const CSR18 = @intToPtr(*volatile u32, base_address + 0x140); + + /// address: 0x50060544 + /// context swap registers + pub const CSR19 = @intToPtr(*volatile u32, base_address + 0x144); + + /// address: 0x50060548 + /// context swap registers + pub const CSR20 = @intToPtr(*volatile u32, base_address + 0x148); + + /// address: 0x5006054c + /// context swap registers + pub const CSR21 = @intToPtr(*volatile u32, base_address + 0x14c); + + /// address: 0x50060550 + /// context swap registers + pub const CSR22 = @intToPtr(*volatile u32, base_address + 0x150); + + /// address: 0x50060554 + /// context swap registers + pub const CSR23 = @intToPtr(*volatile u32, base_address + 0x154); + + /// address: 0x50060558 + /// context swap registers + pub const CSR24 = @intToPtr(*volatile u32, base_address + 0x158); + + /// address: 0x5006055c + /// context swap registers + pub const CSR25 = @intToPtr(*volatile u32, base_address + 0x15c); + + /// address: 0x50060560 + /// context swap registers + pub const CSR26 = @intToPtr(*volatile u32, base_address + 0x160); + + /// address: 0x50060564 + /// context swap registers + pub const CSR27 = @intToPtr(*volatile u32, base_address + 0x164); + + /// address: 0x50060568 + /// context swap registers + pub const CSR28 = @intToPtr(*volatile u32, base_address + 0x168); + + /// address: 0x5006056c + /// context swap registers + pub const CSR29 = @intToPtr(*volatile u32, base_address + 0x16c); + + /// address: 0x50060570 + /// context swap registers + pub const CSR30 = @intToPtr(*volatile u32, base_address + 0x170); + + /// address: 0x50060574 + /// context swap registers + pub const CSR31 = @intToPtr(*volatile u32, base_address + 0x174); + + /// address: 0x50060578 + /// context swap registers + pub const CSR32 = @intToPtr(*volatile u32, base_address + 0x178); + + /// address: 0x5006057c + /// context swap registers + pub const CSR33 = @intToPtr(*volatile u32, base_address + 0x17c); + + /// address: 0x50060580 + /// context swap registers + pub const CSR34 = @intToPtr(*volatile u32, base_address + 0x180); + + /// address: 0x50060584 + /// context swap registers + pub const CSR35 = @intToPtr(*volatile u32, base_address + 0x184); + + /// address: 0x50060588 + /// context swap registers + pub const CSR36 = @intToPtr(*volatile u32, base_address + 0x188); + + /// address: 0x5006058c + /// context swap registers + pub const CSR37 = @intToPtr(*volatile u32, base_address + 0x18c); + + /// address: 0x50060590 + /// context swap registers + pub const CSR38 = @intToPtr(*volatile u32, base_address + 0x190); + + /// address: 0x50060594 + /// context swap registers + pub const CSR39 = @intToPtr(*volatile u32, base_address + 0x194); + + /// address: 0x50060598 + /// context swap registers + pub const CSR40 = @intToPtr(*volatile u32, base_address + 0x198); + + /// address: 0x5006059c + /// context swap registers + pub const CSR41 = @intToPtr(*volatile u32, base_address + 0x19c); + + /// address: 0x500605a0 + /// context swap registers + pub const CSR42 = @intToPtr(*volatile u32, base_address + 0x1a0); + + /// address: 0x500605a4 + /// context swap registers + pub const CSR43 = @intToPtr(*volatile u32, base_address + 0x1a4); + + /// address: 0x500605a8 + /// context swap registers + pub const CSR44 = @intToPtr(*volatile u32, base_address + 0x1a8); + + /// address: 0x500605ac + /// context swap registers + pub const CSR45 = @intToPtr(*volatile u32, base_address + 0x1ac); + + /// address: 0x500605b0 + /// context swap registers + pub const CSR46 = @intToPtr(*volatile u32, base_address + 0x1b0); + + /// address: 0x500605b4 + /// context swap registers + pub const CSR47 = @intToPtr(*volatile u32, base_address + 0x1b4); + + /// address: 0x500605b8 + /// context swap registers + pub const CSR48 = @intToPtr(*volatile u32, base_address + 0x1b8); + + /// address: 0x500605bc + /// context swap registers + pub const CSR49 = @intToPtr(*volatile u32, base_address + 0x1bc); + + /// address: 0x500605c0 + /// context swap registers + pub const CSR50 = @intToPtr(*volatile u32, base_address + 0x1c0); + + /// address: 0x500605c4 + /// context swap registers + pub const CSR51 = @intToPtr(*volatile u32, base_address + 0x1c4); + + /// address: 0x500605c8 + /// context swap registers + pub const CSR52 = @intToPtr(*volatile u32, base_address + 0x1c8); + + /// address: 0x500605cc + /// context swap registers + pub const CSR53 = @intToPtr(*volatile u32, base_address + 0x1cc); + + /// address: 0x50060710 + /// HASH digest register + pub const HASH_HR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// H0 + H0: u32, + }), base_address + 0x310); + + /// address: 0x50060714 + /// read-only + pub const HASH_HR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// H1 + H1: u32, + }), base_address + 0x314); + + /// address: 0x50060718 + /// read-only + pub const HASH_HR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// H2 + H2: u32, + }), base_address + 0x318); + + /// address: 0x5006071c + /// read-only + pub const HASH_HR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// H3 + H3: u32, + }), base_address + 0x31c); + + /// address: 0x50060720 + /// read-only + pub const HASH_HR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// H4 + H4: u32, + }), base_address + 0x320); + + /// address: 0x50060724 + /// read-only + pub const HASH_HR5 = @intToPtr(*volatile Mmio(32, packed struct { + /// H5 + H5: u32, + }), base_address + 0x324); + + /// address: 0x50060728 + /// read-only + pub const HASH_HR6 = @intToPtr(*volatile Mmio(32, packed struct { + /// H6 + H6: u32, + }), base_address + 0x328); + + /// address: 0x5006072c + /// read-only + pub const HASH_HR7 = @intToPtr(*volatile Mmio(32, packed struct { + /// H7 + H7: u32, + }), base_address + 0x32c); + }; + + /// Cryptographic processor + pub const CRYP = struct { + pub const base_address = 0x50060000; + + /// address: 0x50060000 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + /// Algorithm direction + ALGODIR: u1, + /// Algorithm mode + ALGOMODE0: u3, + /// Data type selection + DATATYPE: u2, + /// Key size selection (AES mode + /// only) + KEYSIZE: u2, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// FIFO flush + FFLUSH: u1, + /// Cryptographic processor + /// enable + CRYPEN: u1, + /// GCM_CCMPH + GCM_CCMPH: u2, + reserved6: u1, + /// ALGOMODE + ALGOMODE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x0); + + /// address: 0x50060004 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Input FIFO empty + IFEM: u1, + /// Input FIFO not full + IFNF: u1, + /// Output FIFO not empty + OFNE: u1, + /// Output FIFO full + OFFU: u1, + /// Busy bit + BUSY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x4); + + /// address: 0x50060008 + /// data input register + pub const DIN = @intToPtr(*volatile Mmio(32, packed struct { + /// Data input + DATAIN: u32, + }), base_address + 0x8); + + /// address: 0x5006000c + /// data output register + pub const DOUT = @intToPtr(*volatile Mmio(32, packed struct { + /// Data output + DATAOUT: u32, + }), base_address + 0xc); + + /// address: 0x50060010 + /// DMA control register + pub const DMACR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA input enable + DIEN: u1, + /// DMA output enable + DOEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x10); + + /// address: 0x50060014 + /// interrupt mask set/clear + /// register + pub const IMSCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Input FIFO service interrupt + /// mask + INIM: u1, + /// Output FIFO service interrupt + /// mask + OUTIM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x14); + + /// address: 0x50060018 + /// raw interrupt status register + pub const RISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Input FIFO service raw interrupt + /// status + INRIS: u1, + /// Output FIFO service raw interrupt + /// status + OUTRIS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x18); + + /// address: 0x5006001c + /// masked interrupt status + /// register + pub const MISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Input FIFO service masked interrupt + /// status + INMIS: u1, + /// Output FIFO service masked interrupt + /// status + OUTMIS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x1c); + + /// address: 0x50060020 + /// key registers + pub const K0LR = @intToPtr(*volatile Mmio(32, packed struct { + /// b224 + b224: u1, + /// b225 + b225: u1, + /// b226 + b226: u1, + /// b227 + b227: u1, + /// b228 + b228: u1, + /// b229 + b229: u1, + /// b230 + b230: u1, + /// b231 + b231: u1, + /// b232 + b232: u1, + /// b233 + b233: u1, + /// b234 + b234: u1, + /// b235 + b235: u1, + /// b236 + b236: u1, + /// b237 + b237: u1, + /// b238 + b238: u1, + /// b239 + b239: u1, + /// b240 + b240: u1, + /// b241 + b241: u1, + /// b242 + b242: u1, + /// b243 + b243: u1, + /// b244 + b244: u1, + /// b245 + b245: u1, + /// b246 + b246: u1, + /// b247 + b247: u1, + /// b248 + b248: u1, + /// b249 + b249: u1, + /// b250 + b250: u1, + /// b251 + b251: u1, + /// b252 + b252: u1, + /// b253 + b253: u1, + /// b254 + b254: u1, + /// b255 + b255: u1, + }), base_address + 0x20); + + /// address: 0x50060024 + /// key registers + pub const K0RR = @intToPtr(*volatile Mmio(32, packed struct { + /// b192 + b192: u1, + /// b193 + b193: u1, + /// b194 + b194: u1, + /// b195 + b195: u1, + /// b196 + b196: u1, + /// b197 + b197: u1, + /// b198 + b198: u1, + /// b199 + b199: u1, + /// b200 + b200: u1, + /// b201 + b201: u1, + /// b202 + b202: u1, + /// b203 + b203: u1, + /// b204 + b204: u1, + /// b205 + b205: u1, + /// b206 + b206: u1, + /// b207 + b207: u1, + /// b208 + b208: u1, + /// b209 + b209: u1, + /// b210 + b210: u1, + /// b211 + b211: u1, + /// b212 + b212: u1, + /// b213 + b213: u1, + /// b214 + b214: u1, + /// b215 + b215: u1, + /// b216 + b216: u1, + /// b217 + b217: u1, + /// b218 + b218: u1, + /// b219 + b219: u1, + /// b220 + b220: u1, + /// b221 + b221: u1, + /// b222 + b222: u1, + /// b223 + b223: u1, + }), base_address + 0x24); + + /// address: 0x50060028 + /// key registers + pub const K1LR = @intToPtr(*volatile Mmio(32, packed struct { + /// b160 + b160: u1, + /// b161 + b161: u1, + /// b162 + b162: u1, + /// b163 + b163: u1, + /// b164 + b164: u1, + /// b165 + b165: u1, + /// b166 + b166: u1, + /// b167 + b167: u1, + /// b168 + b168: u1, + /// b169 + b169: u1, + /// b170 + b170: u1, + /// b171 + b171: u1, + /// b172 + b172: u1, + /// b173 + b173: u1, + /// b174 + b174: u1, + /// b175 + b175: u1, + /// b176 + b176: u1, + /// b177 + b177: u1, + /// b178 + b178: u1, + /// b179 + b179: u1, + /// b180 + b180: u1, + /// b181 + b181: u1, + /// b182 + b182: u1, + /// b183 + b183: u1, + /// b184 + b184: u1, + /// b185 + b185: u1, + /// b186 + b186: u1, + /// b187 + b187: u1, + /// b188 + b188: u1, + /// b189 + b189: u1, + /// b190 + b190: u1, + /// b191 + b191: u1, + }), base_address + 0x28); + + /// address: 0x5006002c + /// key registers + pub const K1RR = @intToPtr(*volatile Mmio(32, packed struct { + /// b128 + b128: u1, + /// b129 + b129: u1, + /// b130 + b130: u1, + /// b131 + b131: u1, + /// b132 + b132: u1, + /// b133 + b133: u1, + /// b134 + b134: u1, + /// b135 + b135: u1, + /// b136 + b136: u1, + /// b137 + b137: u1, + /// b138 + b138: u1, + /// b139 + b139: u1, + /// b140 + b140: u1, + /// b141 + b141: u1, + /// b142 + b142: u1, + /// b143 + b143: u1, + /// b144 + b144: u1, + /// b145 + b145: u1, + /// b146 + b146: u1, + /// b147 + b147: u1, + /// b148 + b148: u1, + /// b149 + b149: u1, + /// b150 + b150: u1, + /// b151 + b151: u1, + /// b152 + b152: u1, + /// b153 + b153: u1, + /// b154 + b154: u1, + /// b155 + b155: u1, + /// b156 + b156: u1, + /// b157 + b157: u1, + /// b158 + b158: u1, + /// b159 + b159: u1, + }), base_address + 0x2c); + + /// address: 0x50060030 + /// key registers + pub const K2LR = @intToPtr(*volatile Mmio(32, packed struct { + /// b96 + b96: u1, + /// b97 + b97: u1, + /// b98 + b98: u1, + /// b99 + b99: u1, + /// b100 + b100: u1, + /// b101 + b101: u1, + /// b102 + b102: u1, + /// b103 + b103: u1, + /// b104 + b104: u1, + /// b105 + b105: u1, + /// b106 + b106: u1, + /// b107 + b107: u1, + /// b108 + b108: u1, + /// b109 + b109: u1, + /// b110 + b110: u1, + /// b111 + b111: u1, + /// b112 + b112: u1, + /// b113 + b113: u1, + /// b114 + b114: u1, + /// b115 + b115: u1, + /// b116 + b116: u1, + /// b117 + b117: u1, + /// b118 + b118: u1, + /// b119 + b119: u1, + /// b120 + b120: u1, + /// b121 + b121: u1, + /// b122 + b122: u1, + /// b123 + b123: u1, + /// b124 + b124: u1, + /// b125 + b125: u1, + /// b126 + b126: u1, + /// b127 + b127: u1, + }), base_address + 0x30); + + /// address: 0x50060034 + /// key registers + pub const K2RR = @intToPtr(*volatile Mmio(32, packed struct { + /// b64 + b64: u1, + /// b65 + b65: u1, + /// b66 + b66: u1, + /// b67 + b67: u1, + /// b68 + b68: u1, + /// b69 + b69: u1, + /// b70 + b70: u1, + /// b71 + b71: u1, + /// b72 + b72: u1, + /// b73 + b73: u1, + /// b74 + b74: u1, + /// b75 + b75: u1, + /// b76 + b76: u1, + /// b77 + b77: u1, + /// b78 + b78: u1, + /// b79 + b79: u1, + /// b80 + b80: u1, + /// b81 + b81: u1, + /// b82 + b82: u1, + /// b83 + b83: u1, + /// b84 + b84: u1, + /// b85 + b85: u1, + /// b86 + b86: u1, + /// b87 + b87: u1, + /// b88 + b88: u1, + /// b89 + b89: u1, + /// b90 + b90: u1, + /// b91 + b91: u1, + /// b92 + b92: u1, + /// b93 + b93: u1, + /// b94 + b94: u1, + /// b95 + b95: u1, + }), base_address + 0x34); + + /// address: 0x50060038 + /// key registers + pub const K3LR = @intToPtr(*volatile Mmio(32, packed struct { + /// b32 + b32: u1, + /// b33 + b33: u1, + /// b34 + b34: u1, + /// b35 + b35: u1, + /// b36 + b36: u1, + /// b37 + b37: u1, + /// b38 + b38: u1, + /// b39 + b39: u1, + /// b40 + b40: u1, + /// b41 + b41: u1, + /// b42 + b42: u1, + /// b43 + b43: u1, + /// b44 + b44: u1, + /// b45 + b45: u1, + /// b46 + b46: u1, + /// b47 + b47: u1, + /// b48 + b48: u1, + /// b49 + b49: u1, + /// b50 + b50: u1, + /// b51 + b51: u1, + /// b52 + b52: u1, + /// b53 + b53: u1, + /// b54 + b54: u1, + /// b55 + b55: u1, + /// b56 + b56: u1, + /// b57 + b57: u1, + /// b58 + b58: u1, + /// b59 + b59: u1, + /// b60 + b60: u1, + /// b61 + b61: u1, + /// b62 + b62: u1, + /// b63 + b63: u1, + }), base_address + 0x38); + + /// address: 0x5006003c + /// key registers + pub const K3RR = @intToPtr(*volatile Mmio(32, packed struct { + /// b0 + b0: u1, + /// b1 + b1: u1, + /// b2 + b2: u1, + /// b3 + b3: u1, + /// b4 + b4: u1, + /// b5 + b5: u1, + /// b6 + b6: u1, + /// b7 + b7: u1, + /// b8 + b8: u1, + /// b9 + b9: u1, + /// b10 + b10: u1, + /// b11 + b11: u1, + /// b12 + b12: u1, + /// b13 + b13: u1, + /// b14 + b14: u1, + /// b15 + b15: u1, + /// b16 + b16: u1, + /// b17 + b17: u1, + /// b18 + b18: u1, + /// b19 + b19: u1, + /// b20 + b20: u1, + /// b21 + b21: u1, + /// b22 + b22: u1, + /// b23 + b23: u1, + /// b24 + b24: u1, + /// b25 + b25: u1, + /// b26 + b26: u1, + /// b27 + b27: u1, + /// b28 + b28: u1, + /// b29 + b29: u1, + /// b30 + b30: u1, + /// b31 + b31: u1, + }), base_address + 0x3c); + + /// address: 0x50060040 + /// initialization vector + /// registers + pub const IV0LR = @intToPtr(*volatile Mmio(32, packed struct { + /// IV31 + IV31: u1, + /// IV30 + IV30: u1, + /// IV29 + IV29: u1, + /// IV28 + IV28: u1, + /// IV27 + IV27: u1, + /// IV26 + IV26: u1, + /// IV25 + IV25: u1, + /// IV24 + IV24: u1, + /// IV23 + IV23: u1, + /// IV22 + IV22: u1, + /// IV21 + IV21: u1, + /// IV20 + IV20: u1, + /// IV19 + IV19: u1, + /// IV18 + IV18: u1, + /// IV17 + IV17: u1, + /// IV16 + IV16: u1, + /// IV15 + IV15: u1, + /// IV14 + IV14: u1, + /// IV13 + IV13: u1, + /// IV12 + IV12: u1, + /// IV11 + IV11: u1, + /// IV10 + IV10: u1, + /// IV9 + IV9: u1, + /// IV8 + IV8: u1, + /// IV7 + IV7: u1, + /// IV6 + IV6: u1, + /// IV5 + IV5: u1, + /// IV4 + IV4: u1, + /// IV3 + IV3: u1, + /// IV2 + IV2: u1, + /// IV1 + IV1: u1, + /// IV0 + IV0: u1, + }), base_address + 0x40); + + /// address: 0x50060044 + /// initialization vector + /// registers + pub const IV0RR = @intToPtr(*volatile Mmio(32, packed struct { + /// IV63 + IV63: u1, + /// IV62 + IV62: u1, + /// IV61 + IV61: u1, + /// IV60 + IV60: u1, + /// IV59 + IV59: u1, + /// IV58 + IV58: u1, + /// IV57 + IV57: u1, + /// IV56 + IV56: u1, + /// IV55 + IV55: u1, + /// IV54 + IV54: u1, + /// IV53 + IV53: u1, + /// IV52 + IV52: u1, + /// IV51 + IV51: u1, + /// IV50 + IV50: u1, + /// IV49 + IV49: u1, + /// IV48 + IV48: u1, + /// IV47 + IV47: u1, + /// IV46 + IV46: u1, + /// IV45 + IV45: u1, + /// IV44 + IV44: u1, + /// IV43 + IV43: u1, + /// IV42 + IV42: u1, + /// IV41 + IV41: u1, + /// IV40 + IV40: u1, + /// IV39 + IV39: u1, + /// IV38 + IV38: u1, + /// IV37 + IV37: u1, + /// IV36 + IV36: u1, + /// IV35 + IV35: u1, + /// IV34 + IV34: u1, + /// IV33 + IV33: u1, + /// IV32 + IV32: u1, + }), base_address + 0x44); + + /// address: 0x50060048 + /// initialization vector + /// registers + pub const IV1LR = @intToPtr(*volatile Mmio(32, packed struct { + /// IV95 + IV95: u1, + /// IV94 + IV94: u1, + /// IV93 + IV93: u1, + /// IV92 + IV92: u1, + /// IV91 + IV91: u1, + /// IV90 + IV90: u1, + /// IV89 + IV89: u1, + /// IV88 + IV88: u1, + /// IV87 + IV87: u1, + /// IV86 + IV86: u1, + /// IV85 + IV85: u1, + /// IV84 + IV84: u1, + /// IV83 + IV83: u1, + /// IV82 + IV82: u1, + /// IV81 + IV81: u1, + /// IV80 + IV80: u1, + /// IV79 + IV79: u1, + /// IV78 + IV78: u1, + /// IV77 + IV77: u1, + /// IV76 + IV76: u1, + /// IV75 + IV75: u1, + /// IV74 + IV74: u1, + /// IV73 + IV73: u1, + /// IV72 + IV72: u1, + /// IV71 + IV71: u1, + /// IV70 + IV70: u1, + /// IV69 + IV69: u1, + /// IV68 + IV68: u1, + /// IV67 + IV67: u1, + /// IV66 + IV66: u1, + /// IV65 + IV65: u1, + /// IV64 + IV64: u1, + }), base_address + 0x48); + + /// address: 0x5006004c + /// initialization vector + /// registers + pub const IV1RR = @intToPtr(*volatile Mmio(32, packed struct { + /// IV127 + IV127: u1, + /// IV126 + IV126: u1, + /// IV125 + IV125: u1, + /// IV124 + IV124: u1, + /// IV123 + IV123: u1, + /// IV122 + IV122: u1, + /// IV121 + IV121: u1, + /// IV120 + IV120: u1, + /// IV119 + IV119: u1, + /// IV118 + IV118: u1, + /// IV117 + IV117: u1, + /// IV116 + IV116: u1, + /// IV115 + IV115: u1, + /// IV114 + IV114: u1, + /// IV113 + IV113: u1, + /// IV112 + IV112: u1, + /// IV111 + IV111: u1, + /// IV110 + IV110: u1, + /// IV109 + IV109: u1, + /// IV108 + IV108: u1, + /// IV107 + IV107: u1, + /// IV106 + IV106: u1, + /// IV105 + IV105: u1, + /// IV104 + IV104: u1, + /// IV103 + IV103: u1, + /// IV102 + IV102: u1, + /// IV101 + IV101: u1, + /// IV100 + IV100: u1, + /// IV99 + IV99: u1, + /// IV98 + IV98: u1, + /// IV97 + IV97: u1, + /// IV96 + IV96: u1, + }), base_address + 0x4c); + + /// address: 0x50060050 + /// context swap register + pub const CSGCMCCM0R = @intToPtr(*volatile u32, base_address + 0x50); + + /// address: 0x50060054 + /// context swap register + pub const CSGCMCCM1R = @intToPtr(*volatile u32, base_address + 0x54); + + /// address: 0x50060058 + /// context swap register + pub const CSGCMCCM2R = @intToPtr(*volatile u32, base_address + 0x58); + + /// address: 0x5006005c + /// context swap register + pub const CSGCMCCM3R = @intToPtr(*volatile u32, base_address + 0x5c); + + /// address: 0x50060060 + /// context swap register + pub const CSGCMCCM4R = @intToPtr(*volatile u32, base_address + 0x60); + + /// address: 0x50060064 + /// context swap register + pub const CSGCMCCM5R = @intToPtr(*volatile u32, base_address + 0x64); + + /// address: 0x50060068 + /// context swap register + pub const CSGCMCCM6R = @intToPtr(*volatile u32, base_address + 0x68); + + /// address: 0x5006006c + /// context swap register + pub const CSGCMCCM7R = @intToPtr(*volatile u32, base_address + 0x6c); + + /// address: 0x50060070 + /// context swap register + pub const CSGCM0R = @intToPtr(*volatile u32, base_address + 0x70); + + /// address: 0x50060074 + /// context swap register + pub const CSGCM1R = @intToPtr(*volatile u32, base_address + 0x74); + + /// address: 0x50060078 + /// context swap register + pub const CSGCM2R = @intToPtr(*volatile u32, base_address + 0x78); + + /// address: 0x5006007c + /// context swap register + pub const CSGCM3R = @intToPtr(*volatile u32, base_address + 0x7c); + + /// address: 0x50060080 + /// context swap register + pub const CSGCM4R = @intToPtr(*volatile u32, base_address + 0x80); + + /// address: 0x50060084 + /// context swap register + pub const CSGCM5R = @intToPtr(*volatile u32, base_address + 0x84); + + /// address: 0x50060088 + /// context swap register + pub const CSGCM6R = @intToPtr(*volatile u32, base_address + 0x88); + + /// address: 0x5006008c + /// context swap register + pub const CSGCM7R = @intToPtr(*volatile u32, base_address + 0x8c); + }; + + /// Digital camera interface + pub const DCMI = struct { + pub const base_address = 0x50050000; + + /// address: 0x50050000 + /// control register 1 + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture enable + CAPTURE: u1, + /// Capture mode + CM: u1, + /// Crop feature + CROP: u1, + /// JPEG format + JPEG: u1, + /// Embedded synchronization + /// select + ESS: u1, + /// Pixel clock polarity + PCKPOL: u1, + /// Horizontal synchronization + /// polarity + HSPOL: u1, + /// Vertical synchronization + /// polarity + VSPOL: u1, + /// Frame capture rate control + FCRC: u2, + /// Extended data mode + EDM: u2, + reserved0: u1, + reserved1: u1, + /// DCMI enable + ENABLE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x0); + + /// address: 0x50050004 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// HSYNC + HSYNC: u1, + /// VSYNC + VSYNC: u1, + /// FIFO not empty + FNE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x4); + + /// address: 0x50050008 + /// raw interrupt status register + pub const RIS = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture complete raw interrupt + /// status + FRAME_RIS: u1, + /// Overrun raw interrupt + /// status + OVR_RIS: u1, + /// Synchronization error raw interrupt + /// status + ERR_RIS: u1, + /// VSYNC raw interrupt status + VSYNC_RIS: u1, + /// Line raw interrupt status + LINE_RIS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x8); + + /// address: 0x5005000c + /// interrupt enable register + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture complete interrupt + /// enable + FRAME_IE: u1, + /// Overrun interrupt enable + OVR_IE: u1, + /// Synchronization error interrupt + /// enable + ERR_IE: u1, + /// VSYNC interrupt enable + VSYNC_IE: u1, + /// Line interrupt enable + LINE_IE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0xc); + + /// address: 0x50050010 + /// masked interrupt status + /// register + pub const MIS = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture complete masked interrupt + /// status + FRAME_MIS: u1, + /// Overrun masked interrupt + /// status + OVR_MIS: u1, + /// Synchronization error masked interrupt + /// status + ERR_MIS: u1, + /// VSYNC masked interrupt + /// status + VSYNC_MIS: u1, + /// Line masked interrupt + /// status + LINE_MIS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x10); + + /// address: 0x50050014 + /// interrupt clear register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture complete interrupt status + /// clear + FRAME_ISC: u1, + /// Overrun interrupt status + /// clear + OVR_ISC: u1, + /// Synchronization error interrupt status + /// clear + ERR_ISC: u1, + /// Vertical synch interrupt status + /// clear + VSYNC_ISC: u1, + /// line interrupt status + /// clear + LINE_ISC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x14); + + /// address: 0x50050018 + /// embedded synchronization code + /// register + pub const ESCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame start delimiter code + FSC: u8, + /// Line start delimiter code + LSC: u8, + /// Line end delimiter code + LEC: u8, + /// Frame end delimiter code + FEC: u8, + }), base_address + 0x18); + + /// address: 0x5005001c + /// embedded synchronization unmask + /// register + pub const ESUR = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame start delimiter + /// unmask + FSU: u8, + /// Line start delimiter + /// unmask + LSU: u8, + /// Line end delimiter unmask + LEU: u8, + /// Frame end delimiter unmask + FEU: u8, + }), base_address + 0x1c); + + /// address: 0x50050020 + /// crop window start + pub const CWSTRT = @intToPtr(*volatile Mmio(32, packed struct { + /// Horizontal offset count + HOFFCNT: u14, + reserved0: u1, + reserved1: u1, + /// Vertical start line count + VST: u13, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x20); + + /// address: 0x50050024 + /// crop window size + pub const CWSIZE = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture count + CAPCNT: u14, + reserved0: u1, + reserved1: u1, + /// Vertical line count + VLINE: u14, + padding0: u1, + padding1: u1, + }), base_address + 0x24); + + /// address: 0x50050028 + /// data register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { + /// Data byte 0 + Byte0: u8, + /// Data byte 1 + Byte1: u8, + /// Data byte 2 + Byte2: u8, + /// Data byte 3 + Byte3: u8, + }), base_address + 0x28); + }; + + /// Flexible memory controller + pub const FMC = struct { + pub const base_address = 0xa0000000; + + /// address: 0xa0000000 + /// SRAM/NOR-Flash chip-select control register + /// 1 + pub const BCR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved0: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + reserved1: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// CBURSTRW + CBURSTRW: u1, + /// CCLKEN + CCLKEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x0); + + /// address: 0xa0000004 + /// SRAM/NOR-Flash chip-select timing register + /// 1 + pub const BTR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x4); + + /// address: 0xa0000008 + /// SRAM/NOR-Flash chip-select control register + /// 2 + pub const BCR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved0: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CBURSTRW + CBURSTRW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x8); + + /// address: 0xa000000c + /// SRAM/NOR-Flash chip-select timing register + /// 2 + pub const BTR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0xc); + + /// address: 0xa0000010 + /// SRAM/NOR-Flash chip-select control register + /// 3 + pub const BCR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved0: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CBURSTRW + CBURSTRW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x10); + + /// address: 0xa0000014 + /// SRAM/NOR-Flash chip-select timing register + /// 3 + pub const BTR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x14); + + /// address: 0xa0000018 + /// SRAM/NOR-Flash chip-select control register + /// 4 + pub const BCR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved0: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CBURSTRW + CBURSTRW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x18); + + /// address: 0xa000001c + /// SRAM/NOR-Flash chip-select timing register + /// 4 + pub const BTR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x1c); + + /// address: 0xa0000060 + /// PC Card/NAND Flash control register + /// 2 + pub const PCR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved1: u1, + reserved2: u1, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x60); + + /// address: 0xa0000064 + /// FIFO status and interrupt register + /// 2 + pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x64); + + /// address: 0xa0000068 + /// Common memory space timing register + /// 2 + pub const PMEM2 = @intToPtr(*volatile Mmio(32, packed struct { + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), base_address + 0x68); + + /// address: 0xa000006c + /// Attribute memory space timing register + /// 2 + pub const PATT2 = @intToPtr(*volatile Mmio(32, packed struct { + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), base_address + 0x6c); + + /// address: 0xa0000074 + /// ECC result register 2 + pub const ECCR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// ECCx + ECCx: u32, + }), base_address + 0x74); + + /// address: 0xa0000080 + /// PC Card/NAND Flash control register + /// 3 + pub const PCR3 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved1: u1, + reserved2: u1, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x80); + + /// address: 0xa0000084 + /// FIFO status and interrupt register + /// 3 + pub const SR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x84); + + /// address: 0xa0000088 + /// Common memory space timing register + /// 3 + pub const PMEM3 = @intToPtr(*volatile Mmio(32, packed struct { + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), base_address + 0x88); + + /// address: 0xa000008c + /// Attribute memory space timing register + /// 3 + pub const PATT3 = @intToPtr(*volatile Mmio(32, packed struct { + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), base_address + 0x8c); + + /// address: 0xa0000094 + /// ECC result register 3 + pub const ECCR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// ECCx + ECCx: u32, + }), base_address + 0x94); + + /// address: 0xa00000a0 + /// PC Card/NAND Flash control register + /// 4 + pub const PCR4 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved1: u1, + reserved2: u1, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0xa0); + + /// address: 0xa00000a4 + /// FIFO status and interrupt register + /// 4 + pub const SR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0xa4); + + /// address: 0xa00000a8 + /// Common memory space timing register + /// 4 + pub const PMEM4 = @intToPtr(*volatile Mmio(32, packed struct { + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), base_address + 0xa8); + + /// address: 0xa00000ac + /// Attribute memory space timing register + /// 4 + pub const PATT4 = @intToPtr(*volatile Mmio(32, packed struct { + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), base_address + 0xac); + + /// address: 0xa00000b0 + /// I/O space timing register 4 + pub const PIO4 = @intToPtr(*volatile Mmio(32, packed struct { + /// IOSETx + IOSETx: u8, + /// IOWAITx + IOWAITx: u8, + /// IOHOLDx + IOHOLDx: u8, + /// IOHIZx + IOHIZx: u8, + }), base_address + 0xb0); + + /// address: 0xa0000104 + /// SRAM/NOR-Flash write timing registers + /// 1 + pub const BWTR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x104); + + /// address: 0xa000010c + /// SRAM/NOR-Flash write timing registers + /// 2 + pub const BWTR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x10c); + + /// address: 0xa0000104 + /// SRAM/NOR-Flash write timing registers + /// 3 + pub const BWTR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x104); + + /// address: 0xa000010c + /// SRAM/NOR-Flash write timing registers + /// 4 + pub const BWTR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x10c); + + /// address: 0xa0000140 + /// SDRAM Control Register 1 + pub const SDCR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of column address + /// bits + NC: u2, + /// Number of row address bits + NR: u2, + /// Memory data bus width + MWID: u2, + /// Number of internal banks + NB: u1, + /// CAS latency + CAS: u2, + /// Write protection + WP: u1, + /// SDRAM clock configuration + SDCLK: u2, + /// Burst read + RBURST: u1, + /// Read pipe + RPIPE: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x140); + + /// address: 0xa0000144 + /// SDRAM Control Register 2 + pub const SDCR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of column address + /// bits + NC: u2, + /// Number of row address bits + NR: u2, + /// Memory data bus width + MWID: u2, + /// Number of internal banks + NB: u1, + /// CAS latency + CAS: u2, + /// Write protection + WP: u1, + /// SDRAM clock configuration + SDCLK: u2, + /// Burst read + RBURST: u1, + /// Read pipe + RPIPE: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x144); + + /// address: 0xa0000148 + /// SDRAM Timing register 1 + pub const SDTR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Load Mode Register to + /// Active + TMRD: u4, + /// Exit self-refresh delay + TXSR: u4, + /// Self refresh time + TRAS: u4, + /// Row cycle delay + TRC: u4, + /// Recovery delay + TWR: u4, + /// Row precharge delay + TRP: u4, + /// Row to column delay + TRCD: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x148); + + /// address: 0xa000014c + /// SDRAM Timing register 2 + pub const SDTR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Load Mode Register to + /// Active + TMRD: u4, + /// Exit self-refresh delay + TXSR: u4, + /// Self refresh time + TRAS: u4, + /// Row cycle delay + TRC: u4, + /// Recovery delay + TWR: u4, + /// Row precharge delay + TRP: u4, + /// Row to column delay + TRCD: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x14c); + + /// address: 0xa0000150 + /// SDRAM Command Mode register + pub const SDCMR = @intToPtr(*volatile Mmio(32, packed struct { + /// Command mode + MODE: u3, + /// Command target bank 2 + CTB2: u1, + /// Command target bank 1 + CTB1: u1, + /// Number of Auto-refresh + NRFS: u4, + /// Mode Register definition + MRD: u13, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x150); + + /// address: 0xa0000154 + /// SDRAM Refresh Timer register + pub const SDRTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clear Refresh error flag + CRE: u1, + /// Refresh Timer Count + COUNT: u13, + /// RES Interrupt Enable + REIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x154); + + /// address: 0xa0000158 + /// SDRAM Status register + pub const SDSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Refresh error flag + RE: u1, + /// Status Mode for Bank 1 + MODES1: u2, + /// Status Mode for Bank 2 + MODES2: u2, + /// Busy status + BUSY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x158); + }; + + /// Debug support + pub const DBG = struct { + pub const base_address = 0xe0042000; + + /// address: 0xe0042000 + /// IDCODE + pub const DBGMCU_IDCODE = @intToPtr(*volatile Mmio(32, packed struct { + /// DEV_ID + DEV_ID: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// REV_ID + REV_ID: u16, + }), base_address + 0x0); + + /// address: 0xe0042004 + /// Control Register + pub const DBGMCU_CR = @intToPtr(*volatile Mmio(32, packed struct { + /// DBG_SLEEP + DBG_SLEEP: u1, + /// DBG_STOP + DBG_STOP: u1, + /// DBG_STANDBY + DBG_STANDBY: u1, + reserved0: u1, + reserved1: u1, + /// TRACE_IOEN + TRACE_IOEN: u1, + /// TRACE_MODE + TRACE_MODE: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0xe0042008 + /// Debug MCU APB1 Freeze registe + pub const DBGMCU_APB1_FZ = @intToPtr(*volatile Mmio(32, packed struct { + /// DBG_TIM2_STOP + DBG_TIM2_STOP: u1, + /// DBG_TIM3 _STOP + DBG_TIM3_STOP: u1, + /// DBG_TIM4_STOP + DBG_TIM4_STOP: u1, + /// DBG_TIM5_STOP + DBG_TIM5_STOP: u1, + /// DBG_TIM6_STOP + DBG_TIM6_STOP: u1, + /// DBG_TIM7_STOP + DBG_TIM7_STOP: u1, + /// DBG_TIM12_STOP + DBG_TIM12_STOP: u1, + /// DBG_TIM13_STOP + DBG_TIM13_STOP: u1, + /// DBG_TIM14_STOP + DBG_TIM14_STOP: u1, + reserved0: u1, + reserved1: u1, + /// DBG_WWDG_STOP + DBG_WWDG_STOP: u1, + /// DBG_IWDEG_STOP + DBG_IWDEG_STOP: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// DBG_J2C1_SMBUS_TIMEOUT + DBG_J2C1_SMBUS_TIMEOUT: u1, + /// DBG_J2C2_SMBUS_TIMEOUT + DBG_J2C2_SMBUS_TIMEOUT: u1, + /// DBG_J2C3SMBUS_TIMEOUT + DBG_J2C3SMBUS_TIMEOUT: u1, + reserved10: u1, + /// DBG_CAN1_STOP + DBG_CAN1_STOP: u1, + /// DBG_CAN2_STOP + DBG_CAN2_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x8); + + /// address: 0xe004200c + /// Debug MCU APB2 Freeze registe + pub const DBGMCU_APB2_FZ = @intToPtr(*volatile Mmio(32, packed struct { + /// TIM1 counter stopped when core is + /// halted + DBG_TIM1_STOP: u1, + /// TIM8 counter stopped when core is + /// halted + DBG_TIM8_STOP: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// TIM9 counter stopped when core is + /// halted + DBG_TIM9_STOP: u1, + /// TIM10 counter stopped when core is + /// halted + DBG_TIM10_STOP: u1, + /// TIM11 counter stopped when core is + /// halted + DBG_TIM11_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xc); + }; + + /// DMA controller + pub const DMA2 = struct { + pub const base_address = 0x40026400; + + /// address: 0x40026400 + /// low interrupt status register + pub const LISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream x FIFO error interrupt flag + /// (x=3..0) + FEIF0: u1, + reserved0: u1, + /// Stream x direct mode error interrupt + /// flag (x=3..0) + DMEIF0: u1, + /// Stream x transfer error interrupt flag + /// (x=3..0) + TEIF0: u1, + /// Stream x half transfer interrupt flag + /// (x=3..0) + HTIF0: u1, + /// Stream x transfer complete interrupt + /// flag (x = 3..0) + TCIF0: u1, + /// Stream x FIFO error interrupt flag + /// (x=3..0) + FEIF1: u1, + reserved1: u1, + /// Stream x direct mode error interrupt + /// flag (x=3..0) + DMEIF1: u1, + /// Stream x transfer error interrupt flag + /// (x=3..0) + TEIF1: u1, + /// Stream x half transfer interrupt flag + /// (x=3..0) + HTIF1: u1, + /// Stream x transfer complete interrupt + /// flag (x = 3..0) + TCIF1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Stream x FIFO error interrupt flag + /// (x=3..0) + FEIF2: u1, + reserved6: u1, + /// Stream x direct mode error interrupt + /// flag (x=3..0) + DMEIF2: u1, + /// Stream x transfer error interrupt flag + /// (x=3..0) + TEIF2: u1, + /// Stream x half transfer interrupt flag + /// (x=3..0) + HTIF2: u1, + /// Stream x transfer complete interrupt + /// flag (x = 3..0) + TCIF2: u1, + /// Stream x FIFO error interrupt flag + /// (x=3..0) + FEIF3: u1, + reserved7: u1, + /// Stream x direct mode error interrupt + /// flag (x=3..0) + DMEIF3: u1, + /// Stream x transfer error interrupt flag + /// (x=3..0) + TEIF3: u1, + /// Stream x half transfer interrupt flag + /// (x=3..0) + HTIF3: u1, + /// Stream x transfer complete interrupt + /// flag (x = 3..0) + TCIF3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x40026404 + /// high interrupt status register + pub const HISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream x FIFO error interrupt flag + /// (x=7..4) + FEIF4: u1, + reserved0: u1, + /// Stream x direct mode error interrupt + /// flag (x=7..4) + DMEIF4: u1, + /// Stream x transfer error interrupt flag + /// (x=7..4) + TEIF4: u1, + /// Stream x half transfer interrupt flag + /// (x=7..4) + HTIF4: u1, + /// Stream x transfer complete interrupt + /// flag (x=7..4) + TCIF4: u1, + /// Stream x FIFO error interrupt flag + /// (x=7..4) + FEIF5: u1, + reserved1: u1, + /// Stream x direct mode error interrupt + /// flag (x=7..4) + DMEIF5: u1, + /// Stream x transfer error interrupt flag + /// (x=7..4) + TEIF5: u1, + /// Stream x half transfer interrupt flag + /// (x=7..4) + HTIF5: u1, + /// Stream x transfer complete interrupt + /// flag (x=7..4) + TCIF5: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Stream x FIFO error interrupt flag + /// (x=7..4) + FEIF6: u1, + reserved6: u1, + /// Stream x direct mode error interrupt + /// flag (x=7..4) + DMEIF6: u1, + /// Stream x transfer error interrupt flag + /// (x=7..4) + TEIF6: u1, + /// Stream x half transfer interrupt flag + /// (x=7..4) + HTIF6: u1, + /// Stream x transfer complete interrupt + /// flag (x=7..4) + TCIF6: u1, + /// Stream x FIFO error interrupt flag + /// (x=7..4) + FEIF7: u1, + reserved7: u1, + /// Stream x direct mode error interrupt + /// flag (x=7..4) + DMEIF7: u1, + /// Stream x transfer error interrupt flag + /// (x=7..4) + TEIF7: u1, + /// Stream x half transfer interrupt flag + /// (x=7..4) + HTIF7: u1, + /// Stream x transfer complete interrupt + /// flag (x=7..4) + TCIF7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x4); + + /// address: 0x40026408 + /// low interrupt flag clear + /// register + pub const LIFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream x clear FIFO error interrupt flag + /// (x = 3..0) + CFEIF0: u1, + reserved0: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 3..0) + CDMEIF0: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 3..0) + CTEIF0: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 3..0) + CHTIF0: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 3..0) + CTCIF0: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 3..0) + CFEIF1: u1, + reserved1: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 3..0) + CDMEIF1: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 3..0) + CTEIF1: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 3..0) + CHTIF1: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 3..0) + CTCIF1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 3..0) + CFEIF2: u1, + reserved6: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 3..0) + CDMEIF2: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 3..0) + CTEIF2: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 3..0) + CHTIF2: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 3..0) + CTCIF2: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 3..0) + CFEIF3: u1, + reserved7: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 3..0) + CDMEIF3: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 3..0) + CTEIF3: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 3..0) + CHTIF3: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 3..0) + CTCIF3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x8); + + /// address: 0x4002640c + /// high interrupt flag clear + /// register + pub const HIFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream x clear FIFO error interrupt flag + /// (x = 7..4) + CFEIF4: u1, + reserved0: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 7..4) + CDMEIF4: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 7..4) + CTEIF4: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 7..4) + CHTIF4: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 7..4) + CTCIF4: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 7..4) + CFEIF5: u1, + reserved1: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 7..4) + CDMEIF5: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 7..4) + CTEIF5: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 7..4) + CHTIF5: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 7..4) + CTCIF5: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 7..4) + CFEIF6: u1, + reserved6: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 7..4) + CDMEIF6: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 7..4) + CTEIF6: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 7..4) + CHTIF6: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 7..4) + CTCIF6: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 7..4) + CFEIF7: u1, + reserved7: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 7..4) + CDMEIF7: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 7..4) + CTEIF7: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 7..4) + CHTIF7: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 7..4) + CTCIF7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xc); + + /// address: 0x40026410 + /// stream x configuration + /// register + pub const S0CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + reserved0: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x10); + + /// address: 0x40026414 + /// stream x number of data + /// register + pub const S0NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40026418 + /// stream x peripheral address + /// register + pub const S0PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x18); + + /// address: 0x4002641c + /// stream x memory 0 address + /// register + pub const S0M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x1c); + + /// address: 0x40026420 + /// stream x memory 1 address + /// register + pub const S0M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x20); + + /// address: 0x40026424 + /// stream x FIFO control register + pub const S0FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x24); + + /// address: 0x40026428 + /// stream x configuration + /// register + pub const S1CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x28); + + /// address: 0x4002642c + /// stream x number of data + /// register + pub const S1NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x2c); + + /// address: 0x40026430 + /// stream x peripheral address + /// register + pub const S1PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x30); + + /// address: 0x40026434 + /// stream x memory 0 address + /// register + pub const S1M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x34); + + /// address: 0x40026438 + /// stream x memory 1 address + /// register + pub const S1M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x38); + + /// address: 0x4002643c + /// stream x FIFO control register + pub const S1FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x3c); + + /// address: 0x40026440 + /// stream x configuration + /// register + pub const S2CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x40); + + /// address: 0x40026444 + /// stream x number of data + /// register + pub const S2NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + + /// address: 0x40026448 + /// stream x peripheral address + /// register + pub const S2PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x48); + + /// address: 0x4002644c + /// stream x memory 0 address + /// register + pub const S2M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x4c); + + /// address: 0x40026450 + /// stream x memory 1 address + /// register + pub const S2M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x50); + + /// address: 0x40026454 + /// stream x FIFO control register + pub const S2FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x54); + + /// address: 0x40026458 + /// stream x configuration + /// register + pub const S3CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x58); + + /// address: 0x4002645c + /// stream x number of data + /// register + pub const S3NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x5c); + + /// address: 0x40026460 + /// stream x peripheral address + /// register + pub const S3PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x60); + + /// address: 0x40026464 + /// stream x memory 0 address + /// register + pub const S3M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x64); + + /// address: 0x40026468 + /// stream x memory 1 address + /// register + pub const S3M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x68); + + /// address: 0x4002646c + /// stream x FIFO control register + pub const S3FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x6c); + + /// address: 0x40026470 + /// stream x configuration + /// register + pub const S4CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x70); + + /// address: 0x40026474 + /// stream x number of data + /// register + pub const S4NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x74); + + /// address: 0x40026478 + /// stream x peripheral address + /// register + pub const S4PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x78); + + /// address: 0x4002647c + /// stream x memory 0 address + /// register + pub const S4M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x7c); + + /// address: 0x40026480 + /// stream x memory 1 address + /// register + pub const S4M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x80); + + /// address: 0x40026484 + /// stream x FIFO control register + pub const S4FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x84); + + /// address: 0x40026488 + /// stream x configuration + /// register + pub const S5CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x88); + + /// address: 0x4002648c + /// stream x number of data + /// register + pub const S5NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8c); + + /// address: 0x40026490 + /// stream x peripheral address + /// register + pub const S5PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x90); + + /// address: 0x40026494 + /// stream x memory 0 address + /// register + pub const S5M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x94); + + /// address: 0x40026498 + /// stream x memory 1 address + /// register + pub const S5M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x98); + + /// address: 0x4002649c + /// stream x FIFO control register + pub const S5FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x9c); + + /// address: 0x400264a0 + /// stream x configuration + /// register + pub const S6CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xa0); + + /// address: 0x400264a4 + /// stream x number of data + /// register + pub const S6NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xa4); + + /// address: 0x400264a8 + /// stream x peripheral address + /// register + pub const S6PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0xa8); + + /// address: 0x400264ac + /// stream x memory 0 address + /// register + pub const S6M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0xac); + + /// address: 0x400264b0 + /// stream x memory 1 address + /// register + pub const S6M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0xb0); + + /// address: 0x400264b4 + /// stream x FIFO control register + pub const S6FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xb4); + + /// address: 0x400264b8 + /// stream x configuration + /// register + pub const S7CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xb8); + + /// address: 0x400264bc + /// stream x number of data + /// register + pub const S7NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xbc); + + /// address: 0x400264c0 + /// stream x peripheral address + /// register + pub const S7PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0xc0); + + /// address: 0x400264c4 + /// stream x memory 0 address + /// register + pub const S7M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0xc4); + + /// address: 0x400264c8 + /// stream x memory 1 address + /// register + pub const S7M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0xc8); + + /// address: 0x400264cc + /// stream x FIFO control register + pub const S7FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xcc); + }; + pub const DMA1 = struct { + pub const base_address = 0x40026000; + + /// address: 0x40026000 + /// low interrupt status register + pub const LISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream x FIFO error interrupt flag + /// (x=3..0) + FEIF0: u1, + reserved0: u1, + /// Stream x direct mode error interrupt + /// flag (x=3..0) + DMEIF0: u1, + /// Stream x transfer error interrupt flag + /// (x=3..0) + TEIF0: u1, + /// Stream x half transfer interrupt flag + /// (x=3..0) + HTIF0: u1, + /// Stream x transfer complete interrupt + /// flag (x = 3..0) + TCIF0: u1, + /// Stream x FIFO error interrupt flag + /// (x=3..0) + FEIF1: u1, + reserved1: u1, + /// Stream x direct mode error interrupt + /// flag (x=3..0) + DMEIF1: u1, + /// Stream x transfer error interrupt flag + /// (x=3..0) + TEIF1: u1, + /// Stream x half transfer interrupt flag + /// (x=3..0) + HTIF1: u1, + /// Stream x transfer complete interrupt + /// flag (x = 3..0) + TCIF1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Stream x FIFO error interrupt flag + /// (x=3..0) + FEIF2: u1, + reserved6: u1, + /// Stream x direct mode error interrupt + /// flag (x=3..0) + DMEIF2: u1, + /// Stream x transfer error interrupt flag + /// (x=3..0) + TEIF2: u1, + /// Stream x half transfer interrupt flag + /// (x=3..0) + HTIF2: u1, + /// Stream x transfer complete interrupt + /// flag (x = 3..0) + TCIF2: u1, + /// Stream x FIFO error interrupt flag + /// (x=3..0) + FEIF3: u1, + reserved7: u1, + /// Stream x direct mode error interrupt + /// flag (x=3..0) + DMEIF3: u1, + /// Stream x transfer error interrupt flag + /// (x=3..0) + TEIF3: u1, + /// Stream x half transfer interrupt flag + /// (x=3..0) + HTIF3: u1, + /// Stream x transfer complete interrupt + /// flag (x = 3..0) + TCIF3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x40026004 + /// high interrupt status register + pub const HISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream x FIFO error interrupt flag + /// (x=7..4) + FEIF4: u1, + reserved0: u1, + /// Stream x direct mode error interrupt + /// flag (x=7..4) + DMEIF4: u1, + /// Stream x transfer error interrupt flag + /// (x=7..4) + TEIF4: u1, + /// Stream x half transfer interrupt flag + /// (x=7..4) + HTIF4: u1, + /// Stream x transfer complete interrupt + /// flag (x=7..4) + TCIF4: u1, + /// Stream x FIFO error interrupt flag + /// (x=7..4) + FEIF5: u1, + reserved1: u1, + /// Stream x direct mode error interrupt + /// flag (x=7..4) + DMEIF5: u1, + /// Stream x transfer error interrupt flag + /// (x=7..4) + TEIF5: u1, + /// Stream x half transfer interrupt flag + /// (x=7..4) + HTIF5: u1, + /// Stream x transfer complete interrupt + /// flag (x=7..4) + TCIF5: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Stream x FIFO error interrupt flag + /// (x=7..4) + FEIF6: u1, + reserved6: u1, + /// Stream x direct mode error interrupt + /// flag (x=7..4) + DMEIF6: u1, + /// Stream x transfer error interrupt flag + /// (x=7..4) + TEIF6: u1, + /// Stream x half transfer interrupt flag + /// (x=7..4) + HTIF6: u1, + /// Stream x transfer complete interrupt + /// flag (x=7..4) + TCIF6: u1, + /// Stream x FIFO error interrupt flag + /// (x=7..4) + FEIF7: u1, + reserved7: u1, + /// Stream x direct mode error interrupt + /// flag (x=7..4) + DMEIF7: u1, + /// Stream x transfer error interrupt flag + /// (x=7..4) + TEIF7: u1, + /// Stream x half transfer interrupt flag + /// (x=7..4) + HTIF7: u1, + /// Stream x transfer complete interrupt + /// flag (x=7..4) + TCIF7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x4); + + /// address: 0x40026008 + /// low interrupt flag clear + /// register + pub const LIFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream x clear FIFO error interrupt flag + /// (x = 3..0) + CFEIF0: u1, + reserved0: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 3..0) + CDMEIF0: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 3..0) + CTEIF0: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 3..0) + CHTIF0: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 3..0) + CTCIF0: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 3..0) + CFEIF1: u1, + reserved1: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 3..0) + CDMEIF1: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 3..0) + CTEIF1: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 3..0) + CHTIF1: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 3..0) + CTCIF1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 3..0) + CFEIF2: u1, + reserved6: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 3..0) + CDMEIF2: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 3..0) + CTEIF2: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 3..0) + CHTIF2: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 3..0) + CTCIF2: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 3..0) + CFEIF3: u1, + reserved7: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 3..0) + CDMEIF3: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 3..0) + CTEIF3: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 3..0) + CHTIF3: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 3..0) + CTCIF3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x8); + + /// address: 0x4002600c + /// high interrupt flag clear + /// register + pub const HIFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream x clear FIFO error interrupt flag + /// (x = 7..4) + CFEIF4: u1, + reserved0: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 7..4) + CDMEIF4: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 7..4) + CTEIF4: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 7..4) + CHTIF4: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 7..4) + CTCIF4: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 7..4) + CFEIF5: u1, + reserved1: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 7..4) + CDMEIF5: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 7..4) + CTEIF5: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 7..4) + CHTIF5: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 7..4) + CTCIF5: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 7..4) + CFEIF6: u1, + reserved6: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 7..4) + CDMEIF6: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 7..4) + CTEIF6: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 7..4) + CHTIF6: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 7..4) + CTCIF6: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 7..4) + CFEIF7: u1, + reserved7: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 7..4) + CDMEIF7: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 7..4) + CTEIF7: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 7..4) + CHTIF7: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 7..4) + CTCIF7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xc); + + /// address: 0x40026010 + /// stream x configuration + /// register + pub const S0CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + reserved0: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x10); + + /// address: 0x40026014 + /// stream x number of data + /// register + pub const S0NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40026018 + /// stream x peripheral address + /// register + pub const S0PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x18); + + /// address: 0x4002601c + /// stream x memory 0 address + /// register + pub const S0M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x1c); + + /// address: 0x40026020 + /// stream x memory 1 address + /// register + pub const S0M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x20); + + /// address: 0x40026024 + /// stream x FIFO control register + pub const S0FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x24); + + /// address: 0x40026028 + /// stream x configuration + /// register + pub const S1CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x28); + + /// address: 0x4002602c + /// stream x number of data + /// register + pub const S1NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x2c); + + /// address: 0x40026030 + /// stream x peripheral address + /// register + pub const S1PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x30); + + /// address: 0x40026034 + /// stream x memory 0 address + /// register + pub const S1M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x34); + + /// address: 0x40026038 + /// stream x memory 1 address + /// register + pub const S1M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x38); + + /// address: 0x4002603c + /// stream x FIFO control register + pub const S1FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x3c); + + /// address: 0x40026040 + /// stream x configuration + /// register + pub const S2CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x40); + + /// address: 0x40026044 + /// stream x number of data + /// register + pub const S2NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + + /// address: 0x40026048 + /// stream x peripheral address + /// register + pub const S2PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x48); + + /// address: 0x4002604c + /// stream x memory 0 address + /// register + pub const S2M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x4c); + + /// address: 0x40026050 + /// stream x memory 1 address + /// register + pub const S2M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x50); + + /// address: 0x40026054 + /// stream x FIFO control register + pub const S2FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x54); + + /// address: 0x40026058 + /// stream x configuration + /// register + pub const S3CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x58); + + /// address: 0x4002605c + /// stream x number of data + /// register + pub const S3NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x5c); + + /// address: 0x40026060 + /// stream x peripheral address + /// register + pub const S3PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x60); + + /// address: 0x40026064 + /// stream x memory 0 address + /// register + pub const S3M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x64); + + /// address: 0x40026068 + /// stream x memory 1 address + /// register + pub const S3M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x68); + + /// address: 0x4002606c + /// stream x FIFO control register + pub const S3FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x6c); + + /// address: 0x40026070 + /// stream x configuration + /// register + pub const S4CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x70); + + /// address: 0x40026074 + /// stream x number of data + /// register + pub const S4NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x74); + + /// address: 0x40026078 + /// stream x peripheral address + /// register + pub const S4PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x78); + + /// address: 0x4002607c + /// stream x memory 0 address + /// register + pub const S4M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x7c); + + /// address: 0x40026080 + /// stream x memory 1 address + /// register + pub const S4M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x80); + + /// address: 0x40026084 + /// stream x FIFO control register + pub const S4FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x84); + + /// address: 0x40026088 + /// stream x configuration + /// register + pub const S5CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x88); + + /// address: 0x4002608c + /// stream x number of data + /// register + pub const S5NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8c); + + /// address: 0x40026090 + /// stream x peripheral address + /// register + pub const S5PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x90); + + /// address: 0x40026094 + /// stream x memory 0 address + /// register + pub const S5M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x94); + + /// address: 0x40026098 + /// stream x memory 1 address + /// register + pub const S5M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x98); + + /// address: 0x4002609c + /// stream x FIFO control register + pub const S5FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x9c); + + /// address: 0x400260a0 + /// stream x configuration + /// register + pub const S6CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xa0); + + /// address: 0x400260a4 + /// stream x number of data + /// register + pub const S6NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xa4); + + /// address: 0x400260a8 + /// stream x peripheral address + /// register + pub const S6PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0xa8); + + /// address: 0x400260ac + /// stream x memory 0 address + /// register + pub const S6M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0xac); + + /// address: 0x400260b0 + /// stream x memory 1 address + /// register + pub const S6M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0xb0); + + /// address: 0x400260b4 + /// stream x FIFO control register + pub const S6FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xb4); + + /// address: 0x400260b8 + /// stream x configuration + /// register + pub const S7CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xb8); + + /// address: 0x400260bc + /// stream x number of data + /// register + pub const S7NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xbc); + + /// address: 0x400260c0 + /// stream x peripheral address + /// register + pub const S7PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0xc0); + + /// address: 0x400260c4 + /// stream x memory 0 address + /// register + pub const S7M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0xc4); + + /// address: 0x400260c8 + /// stream x memory 1 address + /// register + pub const S7M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0xc8); + + /// address: 0x400260cc + /// stream x FIFO control register + pub const S7FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xcc); + }; + + /// Reset and clock control + pub const RCC = struct { + pub const base_address = 0x40023800; + + /// address: 0x40023800 + /// clock control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Internal high-speed clock + /// enable + HSION: u1, + /// Internal high-speed clock ready + /// flag + HSIRDY: u1, + reserved0: u1, + /// Internal high-speed clock + /// trimming + HSITRIM: u5, + /// Internal high-speed clock + /// calibration + HSICAL: u8, + /// HSE clock enable + HSEON: u1, + /// HSE clock ready flag + HSERDY: u1, + /// HSE clock bypass + HSEBYP: u1, + /// Clock security system + /// enable + CSSON: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Main PLL (PLL) enable + PLLON: u1, + /// Main PLL (PLL) clock ready + /// flag + PLLRDY: u1, + /// PLLI2S enable + PLLI2SON: u1, + /// PLLI2S clock ready flag + PLLI2SRDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x40023804 + /// PLL configuration register + pub const PLLCFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Division factor for the main PLL (PLL) + /// and audio PLL (PLLI2S) input clock + PLLM0: u1, + /// Division factor for the main PLL (PLL) + /// and audio PLL (PLLI2S) input clock + PLLM1: u1, + /// Division factor for the main PLL (PLL) + /// and audio PLL (PLLI2S) input clock + PLLM2: u1, + /// Division factor for the main PLL (PLL) + /// and audio PLL (PLLI2S) input clock + PLLM3: u1, + /// Division factor for the main PLL (PLL) + /// and audio PLL (PLLI2S) input clock + PLLM4: u1, + /// Division factor for the main PLL (PLL) + /// and audio PLL (PLLI2S) input clock + PLLM5: u1, + /// Main PLL (PLL) multiplication factor for + /// VCO + PLLN0: u1, + /// Main PLL (PLL) multiplication factor for + /// VCO + PLLN1: u1, + /// Main PLL (PLL) multiplication factor for + /// VCO + PLLN2: u1, + /// Main PLL (PLL) multiplication factor for + /// VCO + PLLN3: u1, + /// Main PLL (PLL) multiplication factor for + /// VCO + PLLN4: u1, + /// Main PLL (PLL) multiplication factor for + /// VCO + PLLN5: u1, + /// Main PLL (PLL) multiplication factor for + /// VCO + PLLN6: u1, + /// Main PLL (PLL) multiplication factor for + /// VCO + PLLN7: u1, + /// Main PLL (PLL) multiplication factor for + /// VCO + PLLN8: u1, + reserved0: u1, + /// Main PLL (PLL) division factor for main + /// system clock + PLLP0: u1, + /// Main PLL (PLL) division factor for main + /// system clock + PLLP1: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Main PLL(PLL) and audio PLL (PLLI2S) + /// entry clock source + PLLSRC: u1, + reserved5: u1, + /// Main PLL (PLL) division factor for USB + /// OTG FS, SDIO and random number generator + /// clocks + PLLQ0: u1, + /// Main PLL (PLL) division factor for USB + /// OTG FS, SDIO and random number generator + /// clocks + PLLQ1: u1, + /// Main PLL (PLL) division factor for USB + /// OTG FS, SDIO and random number generator + /// clocks + PLLQ2: u1, + /// Main PLL (PLL) division factor for USB + /// OTG FS, SDIO and random number generator + /// clocks + PLLQ3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x4); + + /// address: 0x40023808 + /// clock configuration register + pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// System clock switch + SW0: u1, + /// System clock switch + SW1: u1, + /// System clock switch status + SWS0: u1, + /// System clock switch status + SWS1: u1, + /// AHB prescaler + HPRE: u4, + reserved0: u1, + reserved1: u1, + /// APB Low speed prescaler + /// (APB1) + PPRE1: u3, + /// APB high-speed prescaler + /// (APB2) + PPRE2: u3, + /// HSE division factor for RTC + /// clock + RTCPRE: u5, + /// Microcontroller clock output + /// 1 + MCO1: u2, + /// I2S clock selection + I2SSRC: u1, + /// MCO1 prescaler + MCO1PRE: u3, + /// MCO2 prescaler + MCO2PRE: u3, + /// Microcontroller clock output + /// 2 + MCO2: u2, + }), base_address + 0x8); + + /// address: 0x4002380c + /// clock interrupt register + pub const CIR = @intToPtr(*volatile Mmio(32, packed struct { + /// LSI ready interrupt flag + LSIRDYF: u1, + /// LSE ready interrupt flag + LSERDYF: u1, + /// HSI ready interrupt flag + HSIRDYF: u1, + /// HSE ready interrupt flag + HSERDYF: u1, + /// Main PLL (PLL) ready interrupt + /// flag + PLLRDYF: u1, + /// PLLI2S ready interrupt + /// flag + PLLI2SRDYF: u1, + reserved0: u1, + /// Clock security system interrupt + /// flag + CSSF: u1, + /// LSI ready interrupt enable + LSIRDYIE: u1, + /// LSE ready interrupt enable + LSERDYIE: u1, + /// HSI ready interrupt enable + HSIRDYIE: u1, + /// HSE ready interrupt enable + HSERDYIE: u1, + /// Main PLL (PLL) ready interrupt + /// enable + PLLRDYIE: u1, + /// PLLI2S ready interrupt + /// enable + PLLI2SRDYIE: u1, + reserved1: u1, + reserved2: u1, + /// LSI ready interrupt clear + LSIRDYC: u1, + /// LSE ready interrupt clear + LSERDYC: u1, + /// HSI ready interrupt clear + HSIRDYC: u1, + /// HSE ready interrupt clear + HSERDYC: u1, + /// Main PLL(PLL) ready interrupt + /// clear + PLLRDYC: u1, + /// PLLI2S ready interrupt + /// clear + PLLI2SRDYC: u1, + reserved3: u1, + /// Clock security system interrupt + /// clear + CSSC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0xc); + + /// address: 0x40023810 + /// AHB1 peripheral reset register + pub const AHB1RSTR = @intToPtr(*volatile Mmio(32, packed struct { + /// IO port A reset + GPIOARST: u1, + /// IO port B reset + GPIOBRST: u1, + /// IO port C reset + GPIOCRST: u1, + /// IO port D reset + GPIODRST: u1, + /// IO port E reset + GPIOERST: u1, + /// IO port F reset + GPIOFRST: u1, + /// IO port G reset + GPIOGRST: u1, + /// IO port H reset + GPIOHRST: u1, + /// IO port I reset + GPIOIRST: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// CRC reset + CRCRST: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// DMA2 reset + DMA1RST: u1, + /// DMA2 reset + DMA2RST: u1, + reserved11: u1, + reserved12: u1, + /// Ethernet MAC reset + ETHMACRST: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// USB OTG HS module reset + OTGHSRST: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x10); + + /// address: 0x40023814 + /// AHB2 peripheral reset register + pub const AHB2RSTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Camera interface reset + DCMIRST: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Cryptographic module reset + CRYPRST: u1, + /// Hash module reset + HSAHRST: u1, + /// Random number generator module + /// reset + RNGRST: u1, + /// USB OTG FS module reset + OTGFSRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x14); + + /// address: 0x40023818 + /// AHB3 peripheral reset register + pub const AHB3RSTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Flexible memory controller module + /// reset + FMCRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x18); + + /// address: 0x40023820 + /// APB1 peripheral reset register + pub const APB1RSTR = @intToPtr(*volatile Mmio(32, packed struct { + /// TIM2 reset + TIM2RST: u1, + /// TIM3 reset + TIM3RST: u1, + /// TIM4 reset + TIM4RST: u1, + /// TIM5 reset + TIM5RST: u1, + /// TIM6 reset + TIM6RST: u1, + /// TIM7 reset + TIM7RST: u1, + /// TIM12 reset + TIM12RST: u1, + /// TIM13 reset + TIM13RST: u1, + /// TIM14 reset + TIM14RST: u1, + reserved0: u1, + reserved1: u1, + /// Window watchdog reset + WWDGRST: u1, + reserved2: u1, + reserved3: u1, + /// SPI 2 reset + SPI2RST: u1, + /// SPI 3 reset + SPI3RST: u1, + reserved4: u1, + /// USART 2 reset + UART2RST: u1, + /// USART 3 reset + UART3RST: u1, + /// USART 4 reset + UART4RST: u1, + /// USART 5 reset + UART5RST: u1, + /// I2C 1 reset + I2C1RST: u1, + /// I2C 2 reset + I2C2RST: u1, + /// I2C3 reset + I2C3RST: u1, + reserved5: u1, + /// CAN1 reset + CAN1RST: u1, + /// CAN2 reset + CAN2RST: u1, + reserved6: u1, + /// Power interface reset + PWRRST: u1, + /// DAC reset + DACRST: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x20); + + /// address: 0x40023824 + /// APB2 peripheral reset register + pub const APB2RSTR = @intToPtr(*volatile Mmio(32, packed struct { + /// TIM1 reset + TIM1RST: u1, + /// TIM8 reset + TIM8RST: u1, + reserved0: u1, + reserved1: u1, + /// USART1 reset + USART1RST: u1, + /// USART6 reset + USART6RST: u1, + reserved2: u1, + reserved3: u1, + /// ADC interface reset (common to all + /// ADCs) + ADCRST: u1, + reserved4: u1, + reserved5: u1, + /// SDIO reset + SDIORST: u1, + /// SPI 1 reset + SPI1RST: u1, + reserved6: u1, + /// System configuration controller + /// reset + SYSCFGRST: u1, + reserved7: u1, + /// TIM9 reset + TIM9RST: u1, + /// TIM10 reset + TIM10RST: u1, + /// TIM11 reset + TIM11RST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x24); + + /// address: 0x40023830 + /// AHB1 peripheral clock register + pub const AHB1ENR = @intToPtr(*volatile Mmio(32, packed struct { + /// IO port A clock enable + GPIOAEN: u1, + /// IO port B clock enable + GPIOBEN: u1, + /// IO port C clock enable + GPIOCEN: u1, + /// IO port D clock enable + GPIODEN: u1, + /// IO port E clock enable + GPIOEEN: u1, + /// IO port F clock enable + GPIOFEN: u1, + /// IO port G clock enable + GPIOGEN: u1, + /// IO port H clock enable + GPIOHEN: u1, + /// IO port I clock enable + GPIOIEN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// CRC clock enable + CRCEN: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Backup SRAM interface clock + /// enable + BKPSRAMEN: u1, + reserved8: u1, + /// CCM data RAM clock enable + CCMDATARAMEN: u1, + /// DMA1 clock enable + DMA1EN: u1, + /// DMA2 clock enable + DMA2EN: u1, + reserved9: u1, + reserved10: u1, + /// Ethernet MAC clock enable + ETHMACEN: u1, + /// Ethernet Transmission clock + /// enable + ETHMACTXEN: u1, + /// Ethernet Reception clock + /// enable + ETHMACRXEN: u1, + /// Ethernet PTP clock enable + ETHMACPTPEN: u1, + /// USB OTG HS clock enable + OTGHSEN: u1, + /// USB OTG HSULPI clock + /// enable + OTGHSULPIEN: u1, + padding0: u1, + }), base_address + 0x30); + + /// address: 0x40023834 + /// AHB2 peripheral clock enable + /// register + pub const AHB2ENR = @intToPtr(*volatile Mmio(32, packed struct { + /// Camera interface enable + DCMIEN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Cryptographic modules clock + /// enable + CRYPEN: u1, + /// Hash modules clock enable + HASHEN: u1, + /// Random number generator clock + /// enable + RNGEN: u1, + /// USB OTG FS clock enable + OTGFSEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x34); + + /// address: 0x40023838 + /// AHB3 peripheral clock enable + /// register + pub const AHB3ENR = @intToPtr(*volatile Mmio(32, packed struct { + /// Flexible memory controller module clock + /// enable + FMCEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x38); + + /// address: 0x40023840 + /// APB1 peripheral clock enable + /// register + pub const APB1ENR = @intToPtr(*volatile Mmio(32, packed struct { + /// TIM2 clock enable + TIM2EN: u1, + /// TIM3 clock enable + TIM3EN: u1, + /// TIM4 clock enable + TIM4EN: u1, + /// TIM5 clock enable + TIM5EN: u1, + /// TIM6 clock enable + TIM6EN: u1, + /// TIM7 clock enable + TIM7EN: u1, + /// TIM12 clock enable + TIM12EN: u1, + /// TIM13 clock enable + TIM13EN: u1, + /// TIM14 clock enable + TIM14EN: u1, + reserved0: u1, + reserved1: u1, + /// Window watchdog clock + /// enable + WWDGEN: u1, + reserved2: u1, + reserved3: u1, + /// SPI2 clock enable + SPI2EN: u1, + /// SPI3 clock enable + SPI3EN: u1, + reserved4: u1, + /// USART 2 clock enable + USART2EN: u1, + /// USART3 clock enable + USART3EN: u1, + /// UART4 clock enable + UART4EN: u1, + /// UART5 clock enable + UART5EN: u1, + /// I2C1 clock enable + I2C1EN: u1, + /// I2C2 clock enable + I2C2EN: u1, + /// I2C3 clock enable + I2C3EN: u1, + reserved5: u1, + /// CAN 1 clock enable + CAN1EN: u1, + /// CAN 2 clock enable + CAN2EN: u1, + reserved6: u1, + /// Power interface clock + /// enable + PWREN: u1, + /// DAC interface clock enable + DACEN: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x40); + + /// address: 0x40023844 + /// APB2 peripheral clock enable + /// register + pub const APB2ENR = @intToPtr(*volatile Mmio(32, packed struct { + /// TIM1 clock enable + TIM1EN: u1, + /// TIM8 clock enable + TIM8EN: u1, + reserved0: u1, + reserved1: u1, + /// USART1 clock enable + USART1EN: u1, + /// USART6 clock enable + USART6EN: u1, + reserved2: u1, + reserved3: u1, + /// ADC1 clock enable + ADC1EN: u1, + /// ADC2 clock enable + ADC2EN: u1, + /// ADC3 clock enable + ADC3EN: u1, + /// SDIO clock enable + SDIOEN: u1, + /// SPI1 clock enable + SPI1EN: u1, + reserved4: u1, + /// System configuration controller clock + /// enable + SYSCFGEN: u1, + reserved5: u1, + /// TIM9 clock enable + TIM9EN: u1, + /// TIM10 clock enable + TIM10EN: u1, + /// TIM11 clock enable + TIM11EN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x44); + + /// address: 0x40023850 + /// AHB1 peripheral clock enable in low power + /// mode register + pub const AHB1LPENR = @intToPtr(*volatile Mmio(32, packed struct { + /// IO port A clock enable during sleep + /// mode + GPIOALPEN: u1, + /// IO port B clock enable during Sleep + /// mode + GPIOBLPEN: u1, + /// IO port C clock enable during Sleep + /// mode + GPIOCLPEN: u1, + /// IO port D clock enable during Sleep + /// mode + GPIODLPEN: u1, + /// IO port E clock enable during Sleep + /// mode + GPIOELPEN: u1, + /// IO port F clock enable during Sleep + /// mode + GPIOFLPEN: u1, + /// IO port G clock enable during Sleep + /// mode + GPIOGLPEN: u1, + /// IO port H clock enable during Sleep + /// mode + GPIOHLPEN: u1, + /// IO port I clock enable during Sleep + /// mode + GPIOILPEN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// CRC clock enable during Sleep + /// mode + CRCLPEN: u1, + reserved3: u1, + reserved4: u1, + /// Flash interface clock enable during + /// Sleep mode + FLITFLPEN: u1, + /// SRAM 1interface clock enable during + /// Sleep mode + SRAM1LPEN: u1, + /// SRAM 2 interface clock enable during + /// Sleep mode + SRAM2LPEN: u1, + /// Backup SRAM interface clock enable + /// during Sleep mode + BKPSRAMLPEN: u1, + reserved5: u1, + reserved6: u1, + /// DMA1 clock enable during Sleep + /// mode + DMA1LPEN: u1, + /// DMA2 clock enable during Sleep + /// mode + DMA2LPEN: u1, + reserved7: u1, + reserved8: u1, + /// Ethernet MAC clock enable during Sleep + /// mode + ETHMACLPEN: u1, + /// Ethernet transmission clock enable + /// during Sleep mode + ETHMACTXLPEN: u1, + /// Ethernet reception clock enable during + /// Sleep mode + ETHMACRXLPEN: u1, + /// Ethernet PTP clock enable during Sleep + /// mode + ETHMACPTPLPEN: u1, + /// USB OTG HS clock enable during Sleep + /// mode + OTGHSLPEN: u1, + /// USB OTG HS ULPI clock enable during + /// Sleep mode + OTGHSULPILPEN: u1, + padding0: u1, + }), base_address + 0x50); + + /// address: 0x40023854 + /// AHB2 peripheral clock enable in low power + /// mode register + pub const AHB2LPENR = @intToPtr(*volatile Mmio(32, packed struct { + /// Camera interface enable during Sleep + /// mode + DCMILPEN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Cryptography modules clock enable during + /// Sleep mode + CRYPLPEN: u1, + /// Hash modules clock enable during Sleep + /// mode + HASHLPEN: u1, + /// Random number generator clock enable + /// during Sleep mode + RNGLPEN: u1, + /// USB OTG FS clock enable during Sleep + /// mode + OTGFSLPEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x54); + + /// address: 0x40023858 + /// AHB3 peripheral clock enable in low power + /// mode register + pub const AHB3LPENR = @intToPtr(*volatile Mmio(32, packed struct { + /// Flexible memory controller module clock + /// enable during Sleep mode + FMCLPEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x58); + + /// address: 0x40023860 + /// APB1 peripheral clock enable in low power + /// mode register + pub const APB1LPENR = @intToPtr(*volatile Mmio(32, packed struct { + /// TIM2 clock enable during Sleep + /// mode + TIM2LPEN: u1, + /// TIM3 clock enable during Sleep + /// mode + TIM3LPEN: u1, + /// TIM4 clock enable during Sleep + /// mode + TIM4LPEN: u1, + /// TIM5 clock enable during Sleep + /// mode + TIM5LPEN: u1, + /// TIM6 clock enable during Sleep + /// mode + TIM6LPEN: u1, + /// TIM7 clock enable during Sleep + /// mode + TIM7LPEN: u1, + /// TIM12 clock enable during Sleep + /// mode + TIM12LPEN: u1, + /// TIM13 clock enable during Sleep + /// mode + TIM13LPEN: u1, + /// TIM14 clock enable during Sleep + /// mode + TIM14LPEN: u1, + reserved0: u1, + reserved1: u1, + /// Window watchdog clock enable during + /// Sleep mode + WWDGLPEN: u1, + reserved2: u1, + reserved3: u1, + /// SPI2 clock enable during Sleep + /// mode + SPI2LPEN: u1, + /// SPI3 clock enable during Sleep + /// mode + SPI3LPEN: u1, + reserved4: u1, + /// USART2 clock enable during Sleep + /// mode + USART2LPEN: u1, + /// USART3 clock enable during Sleep + /// mode + USART3LPEN: u1, + /// UART4 clock enable during Sleep + /// mode + UART4LPEN: u1, + /// UART5 clock enable during Sleep + /// mode + UART5LPEN: u1, + /// I2C1 clock enable during Sleep + /// mode + I2C1LPEN: u1, + /// I2C2 clock enable during Sleep + /// mode + I2C2LPEN: u1, + /// I2C3 clock enable during Sleep + /// mode + I2C3LPEN: u1, + reserved5: u1, + /// CAN 1 clock enable during Sleep + /// mode + CAN1LPEN: u1, + /// CAN 2 clock enable during Sleep + /// mode + CAN2LPEN: u1, + reserved6: u1, + /// Power interface clock enable during + /// Sleep mode + PWRLPEN: u1, + /// DAC interface clock enable during Sleep + /// mode + DACLPEN: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x60); + + /// address: 0x40023864 + /// APB2 peripheral clock enabled in low power + /// mode register + pub const APB2LPENR = @intToPtr(*volatile Mmio(32, packed struct { + /// TIM1 clock enable during Sleep + /// mode + TIM1LPEN: u1, + /// TIM8 clock enable during Sleep + /// mode + TIM8LPEN: u1, + reserved0: u1, + reserved1: u1, + /// USART1 clock enable during Sleep + /// mode + USART1LPEN: u1, + /// USART6 clock enable during Sleep + /// mode + USART6LPEN: u1, + reserved2: u1, + reserved3: u1, + /// ADC1 clock enable during Sleep + /// mode + ADC1LPEN: u1, + /// ADC2 clock enable during Sleep + /// mode + ADC2LPEN: u1, + /// ADC 3 clock enable during Sleep + /// mode + ADC3LPEN: u1, + /// SDIO clock enable during Sleep + /// mode + SDIOLPEN: u1, + /// SPI 1 clock enable during Sleep + /// mode + SPI1LPEN: u1, + reserved4: u1, + /// System configuration controller clock + /// enable during Sleep mode + SYSCFGLPEN: u1, + reserved5: u1, + /// TIM9 clock enable during sleep + /// mode + TIM9LPEN: u1, + /// TIM10 clock enable during Sleep + /// mode + TIM10LPEN: u1, + /// TIM11 clock enable during Sleep + /// mode + TIM11LPEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x64); + + /// address: 0x40023870 + /// Backup domain control register + pub const BDCR = @intToPtr(*volatile Mmio(32, packed struct { + /// External low-speed oscillator + /// enable + LSEON: u1, + /// External low-speed oscillator + /// ready + LSERDY: u1, + /// External low-speed oscillator + /// bypass + LSEBYP: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// RTC clock source selection + RTCSEL0: u1, + /// RTC clock source selection + RTCSEL1: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software + /// reset + BDRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x70); + + /// address: 0x40023874 + /// clock control & status + /// register + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Internal low-speed oscillator + /// enable + LSION: u1, + /// Internal low-speed oscillator + /// ready + LSIRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// Remove reset flag + RMVF: u1, + /// BOR reset flag + BORRSTF: u1, + /// PIN reset flag + PADRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent watchdog reset + /// flag + WDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, + }), base_address + 0x74); + + /// address: 0x40023880 + /// spread spectrum clock generation + /// register + pub const SSCGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Modulation period + MODPER: u13, + /// Incrementation step + INCSTEP: u15, + reserved0: u1, + reserved1: u1, + /// Spread Select + SPREADSEL: u1, + /// Spread spectrum modulation + /// enable + SSCGEN: u1, + }), base_address + 0x80); + + /// address: 0x40023884 + /// PLLI2S configuration register + pub const PLLI2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// PLLI2S multiplication factor for + /// VCO + PLLI2SN: u9, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// PLLI2S division factor for SAI1 + /// clock + PLLI2SQ: u4, + /// PLLI2S division factor for I2S + /// clocks + PLLI2SR: u3, + padding0: u1, + }), base_address + 0x84); + + /// address: 0x4002388c + /// RCC Dedicated Clock Configuration + /// Register + pub const DCKCFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// PLLI2S division factor for SAI1 + /// clock + PLLI2SDIVQ: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// PLLSAI division factor for SAI1 + /// clock + PLLSAIDIVQ: u5, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// division factor for + /// LCD_CLK + PLLSAIDIVR: u2, + reserved6: u1, + reserved7: u1, + /// SAI1-A clock source + /// selection + SAI1ASRC: u2, + /// SAI1-B clock source + /// selection + SAI1BSRC: u2, + /// Timers clocks prescalers + /// selection + TIMPRE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x8c); + + /// address: 0x40023888 + /// RCC PLL configuration register + pub const PLLSAICFGR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// PLLSAI division factor for + /// VCO + PLLSAIN: u9, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// PLLSAI division factor for SAI1 + /// clock + PLLSAIQ: u4, + /// PLLSAI division factor for LCD + /// clock + PLLSAIR: u3, + padding0: u1, + }), base_address + 0x88); + }; + + /// General-purpose I/Os + pub const GPIOK = struct { + pub const base_address = 0x40022800; + + /// address: 0x40022800 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40022804 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40022808 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4002280c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40022810 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40022814 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40022818 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4002281c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40022820 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40022824 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + pub const GPIOJ = struct { + pub const base_address = 0x40022400; + + /// address: 0x40022400 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40022404 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40022408 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4002240c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40022410 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40022414 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40022418 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4002241c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40022420 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40022424 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + pub const GPIOI = struct { + pub const base_address = 0x40022000; + + /// address: 0x40022000 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40022004 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40022008 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4002200c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40022010 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40022014 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40022018 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4002201c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40022020 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40022024 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + pub const GPIOH = struct { + pub const base_address = 0x40021c00; + + /// address: 0x40021c00 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40021c04 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40021c08 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x40021c0c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40021c10 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40021c14 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40021c18 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x40021c1c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40021c20 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40021c24 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + pub const GPIOG = struct { + pub const base_address = 0x40021800; + + /// address: 0x40021800 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40021804 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40021808 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4002180c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40021810 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40021814 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40021818 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4002181c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40021820 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40021824 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + pub const GPIOF = struct { + pub const base_address = 0x40021400; + + /// address: 0x40021400 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40021404 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40021408 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4002140c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40021410 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40021414 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40021418 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4002141c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40021420 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40021424 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + pub const GPIOE = struct { + pub const base_address = 0x40021000; + + /// address: 0x40021000 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40021004 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40021008 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4002100c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40021010 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40021014 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40021018 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4002101c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40021020 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40021024 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + pub const GPIOD = struct { + pub const base_address = 0x40020c00; + + /// address: 0x40020c00 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40020c04 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40020c08 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x40020c0c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40020c10 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40020c14 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40020c18 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x40020c1c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40020c20 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40020c24 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + pub const GPIOC = struct { + pub const base_address = 0x40020800; + + /// address: 0x40020800 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40020804 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40020808 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4002080c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40020810 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40020814 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40020818 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4002081c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40020820 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40020824 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + + /// General-purpose I/Os + pub const GPIOB = struct { + pub const base_address = 0x40020400; + + /// address: 0x40020400 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40020404 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40020408 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4002040c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40020410 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40020414 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40020418 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4002041c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40020420 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40020424 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + + /// General-purpose I/Os + pub const GPIOA = struct { + pub const base_address = 0x40020000; + + /// address: 0x40020000 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40020004 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40020008 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4002000c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40020010 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40020014 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40020018 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4002001c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40020020 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40020024 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + + /// System configuration controller + pub const SYSCFG = struct { + pub const base_address = 0x40013800; + + /// address: 0x40013800 + /// memory remap register + pub const MEMRM = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory mapping selection + MEM_MODE: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Flash bank mode selection + FB_MODE: u1, + reserved5: u1, + /// FMC memory mapping swap + SWP_FMC: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x0); + + /// address: 0x40013804 + /// peripheral mode configuration + /// register + pub const PMC = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// ADC1DC2 + ADC1DC2: u1, + /// ADC2DC2 + ADC2DC2: u1, + /// ADC3DC2 + ADC3DC2: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + /// Ethernet PHY interface + /// selection + MII_RMII_SEL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40013808 + /// external interrupt configuration register + /// 1 + pub const EXTICR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// EXTI x configuration (x = 0 to + /// 3) + EXTI0: u4, + /// EXTI x configuration (x = 0 to + /// 3) + EXTI1: u4, + /// EXTI x configuration (x = 0 to + /// 3) + EXTI2: u4, + /// EXTI x configuration (x = 0 to + /// 3) + EXTI3: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001380c + /// external interrupt configuration register + /// 2 + pub const EXTICR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// EXTI x configuration (x = 4 to + /// 7) + EXTI4: u4, + /// EXTI x configuration (x = 4 to + /// 7) + EXTI5: u4, + /// EXTI x configuration (x = 4 to + /// 7) + EXTI6: u4, + /// EXTI x configuration (x = 4 to + /// 7) + EXTI7: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40013810 + /// external interrupt configuration register + /// 3 + pub const EXTICR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// EXTI x configuration (x = 8 to + /// 11) + EXTI8: u4, + /// EXTI x configuration (x = 8 to + /// 11) + EXTI9: u4, + /// EXTI10 + EXTI10: u4, + /// EXTI x configuration (x = 8 to + /// 11) + EXTI11: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40013814 + /// external interrupt configuration register + /// 4 + pub const EXTICR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// EXTI x configuration (x = 12 to + /// 15) + EXTI12: u4, + /// EXTI x configuration (x = 12 to + /// 15) + EXTI13: u4, + /// EXTI x configuration (x = 12 to + /// 15) + EXTI14: u4, + /// EXTI x configuration (x = 12 to + /// 15) + EXTI15: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40013820 + /// Compensation cell control + /// register + pub const CMPCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Compensation cell + /// power-down + CMP_PD: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// READY + READY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x20); + }; + + /// Serial peripheral interface + pub const SPI1 = struct { + pub const base_address = 0x40013000; + + /// address: 0x40013000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40013004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40013008 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x4001300c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40013010 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40013014 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40013018 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4001301c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40013020 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const SPI2 = struct { + pub const base_address = 0x40003800; + + /// address: 0x40003800 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40003804 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40003808 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x4000380c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40003810 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40003814 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40003818 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000381c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40003820 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const SPI3 = struct { + pub const base_address = 0x40003c00; + + /// address: 0x40003c00 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40003c04 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40003c08 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x40003c0c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40003c10 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40003c14 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40003c18 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40003c1c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40003c20 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const I2S2ext = struct { + pub const base_address = 0x40003400; + + /// address: 0x40003400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40003404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40003408 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x4000340c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40003410 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40003414 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40003418 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000341c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40003420 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const I2S3ext = struct { + pub const base_address = 0x40004000; + + /// address: 0x40004000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40004004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40004008 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x4000400c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40004010 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40004014 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40004018 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000401c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40004020 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const SPI4 = struct { + pub const base_address = 0x40013400; + + /// address: 0x40013400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40013404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40013408 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x4001340c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40013410 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40013414 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40013418 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4001341c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40013420 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const SPI5 = struct { + pub const base_address = 0x40015000; + + /// address: 0x40015000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40015004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40015008 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x4001500c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40015010 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40015014 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40015018 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4001501c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40015020 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const SPI6 = struct { + pub const base_address = 0x40015400; + + /// address: 0x40015400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40015404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40015408 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x4001540c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40015410 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40015414 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40015418 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4001541c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40015420 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + + /// Secure digital input/output + /// interface + pub const SDIO = struct { + pub const base_address = 0x40012c00; + + /// address: 0x40012c00 + /// power control register + pub const POWER = @intToPtr(*volatile Mmio(32, packed struct { + /// PWRCTRL + PWRCTRL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x0); + + /// address: 0x40012c04 + /// SDI clock control register + pub const CLKCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock divide factor + CLKDIV: u8, + /// Clock enable bit + CLKEN: u1, + /// Power saving configuration + /// bit + PWRSAV: u1, + /// Clock divider bypass enable + /// bit + BYPASS: u1, + /// Wide bus mode enable bit + WIDBUS: u2, + /// SDIO_CK dephasing selection + /// bit + NEGEDGE: u1, + /// HW Flow Control enable + HWFC_EN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + + /// address: 0x40012c08 + /// argument register + pub const ARG = @intToPtr(*volatile Mmio(32, packed struct { + /// Command argument + CMDARG: u32, + }), base_address + 0x8); + + /// address: 0x40012c0c + /// command register + pub const CMD = @intToPtr(*volatile Mmio(32, packed struct { + /// Command index + CMDINDEX: u6, + /// Wait for response bits + WAITRESP: u2, + /// CPSM waits for interrupt + /// request + WAITINT: u1, + /// CPSM Waits for ends of data transfer + /// (CmdPend internal signal). + WAITPEND: u1, + /// Command path state machine (CPSM) Enable + /// bit + CPSMEN: u1, + /// SD I/O suspend command + SDIOSuspend: u1, + /// Enable CMD completion + ENCMDcompl: u1, + /// not Interrupt Enable + nIEN: u1, + /// CE-ATA command + CE_ATACMD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40012c10 + /// command response register + pub const RESPCMD = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x10); + + /// address: 0x40012c14 + /// response 1..4 register + pub const RESP1 = @intToPtr(*volatile Mmio(32, packed struct { + /// see Table 132. + CARDSTATUS1: u32, + }), base_address + 0x14); + + /// address: 0x40012c18 + /// response 1..4 register + pub const RESP2 = @intToPtr(*volatile Mmio(32, packed struct { + /// see Table 132. + CARDSTATUS2: u32, + }), base_address + 0x18); + + /// address: 0x40012c1c + /// response 1..4 register + pub const RESP3 = @intToPtr(*volatile Mmio(32, packed struct { + /// see Table 132. + CARDSTATUS3: u32, + }), base_address + 0x1c); + + /// address: 0x40012c20 + /// response 1..4 register + pub const RESP4 = @intToPtr(*volatile Mmio(32, packed struct { + /// see Table 132. + CARDSTATUS4: u32, + }), base_address + 0x20); + + /// address: 0x40012c24 + /// data timer register + pub const DTIMER = @intToPtr(*volatile Mmio(32, packed struct { + /// Data timeout period + DATATIME: u32, + }), base_address + 0x24); + + /// address: 0x40012c28 + /// data length register + pub const DLEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Data length value + DATALENGTH: u25, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x28); + + /// address: 0x40012c2c + /// data control register + pub const DCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// DTEN + DTEN: u1, + /// Data transfer direction + /// selection + DTDIR: u1, + /// Data transfer mode selection 1: Stream + /// or SDIO multibyte data transfer. + DTMODE: u1, + /// DMA enable bit + DMAEN: u1, + /// Data block size + DBLOCKSIZE: u4, + /// Read wait start + RWSTART: u1, + /// Read wait stop + RWSTOP: u1, + /// Read wait mode + RWMOD: u1, + /// SD I/O enable functions + SDIOEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x2c); + + /// address: 0x40012c30 + /// data counter register + pub const DCOUNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Data count value + DATACOUNT: u25, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x30); + + /// address: 0x40012c34 + /// status register + pub const STA = @intToPtr(*volatile Mmio(32, packed struct { + /// Command response received (CRC check + /// failed) + CCRCFAIL: u1, + /// Data block sent/received (CRC check + /// failed) + DCRCFAIL: u1, + /// Command response timeout + CTIMEOUT: u1, + /// Data timeout + DTIMEOUT: u1, + /// Transmit FIFO underrun + /// error + TXUNDERR: u1, + /// Received FIFO overrun + /// error + RXOVERR: u1, + /// Command response received (CRC check + /// passed) + CMDREND: u1, + /// Command sent (no response + /// required) + CMDSENT: u1, + /// Data end (data counter, SDIDCOUNT, is + /// zero) + DATAEND: u1, + /// Start bit not detected on all data + /// signals in wide bus mode + STBITERR: u1, + /// Data block sent/received (CRC check + /// passed) + DBCKEND: u1, + /// Command transfer in + /// progress + CMDACT: u1, + /// Data transmit in progress + TXACT: u1, + /// Data receive in progress + RXACT: u1, + /// Transmit FIFO half empty: at least 8 + /// words can be written into the FIFO + TXFIFOHE: u1, + /// Receive FIFO half full: there are at + /// least 8 words in the FIFO + RXFIFOHF: u1, + /// Transmit FIFO full + TXFIFOF: u1, + /// Receive FIFO full + RXFIFOF: u1, + /// Transmit FIFO empty + TXFIFOE: u1, + /// Receive FIFO empty + RXFIFOE: u1, + /// Data available in transmit + /// FIFO + TXDAVL: u1, + /// Data available in receive + /// FIFO + RXDAVL: u1, + /// SDIO interrupt received + SDIOIT: u1, + /// CE-ATA command completion signal + /// received for CMD61 + CEATAEND: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x40012c38 + /// interrupt clear register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { + /// CCRCFAIL flag clear bit + CCRCFAILC: u1, + /// DCRCFAIL flag clear bit + DCRCFAILC: u1, + /// CTIMEOUT flag clear bit + CTIMEOUTC: u1, + /// DTIMEOUT flag clear bit + DTIMEOUTC: u1, + /// TXUNDERR flag clear bit + TXUNDERRC: u1, + /// RXOVERR flag clear bit + RXOVERRC: u1, + /// CMDREND flag clear bit + CMDRENDC: u1, + /// CMDSENT flag clear bit + CMDSENTC: u1, + /// DATAEND flag clear bit + DATAENDC: u1, + /// STBITERR flag clear bit + STBITERRC: u1, + /// DBCKEND flag clear bit + DBCKENDC: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// SDIOIT flag clear bit + SDIOITC: u1, + /// CEATAEND flag clear bit + CEATAENDC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x38); + + /// address: 0x40012c3c + /// mask register + pub const MASK = @intToPtr(*volatile Mmio(32, packed struct { + /// Command CRC fail interrupt + /// enable + CCRCFAILIE: u1, + /// Data CRC fail interrupt + /// enable + DCRCFAILIE: u1, + /// Command timeout interrupt + /// enable + CTIMEOUTIE: u1, + /// Data timeout interrupt + /// enable + DTIMEOUTIE: u1, + /// Tx FIFO underrun error interrupt + /// enable + TXUNDERRIE: u1, + /// Rx FIFO overrun error interrupt + /// enable + RXOVERRIE: u1, + /// Command response received interrupt + /// enable + CMDRENDIE: u1, + /// Command sent interrupt + /// enable + CMDSENTIE: u1, + /// Data end interrupt enable + DATAENDIE: u1, + /// Start bit error interrupt + /// enable + STBITERRIE: u1, + /// Data block end interrupt + /// enable + DBCKENDIE: u1, + /// Command acting interrupt + /// enable + CMDACTIE: u1, + /// Data transmit acting interrupt + /// enable + TXACTIE: u1, + /// Data receive acting interrupt + /// enable + RXACTIE: u1, + /// Tx FIFO half empty interrupt + /// enable + TXFIFOHEIE: u1, + /// Rx FIFO half full interrupt + /// enable + RXFIFOHFIE: u1, + /// Tx FIFO full interrupt + /// enable + TXFIFOFIE: u1, + /// Rx FIFO full interrupt + /// enable + RXFIFOFIE: u1, + /// Tx FIFO empty interrupt + /// enable + TXFIFOEIE: u1, + /// Rx FIFO empty interrupt + /// enable + RXFIFOEIE: u1, + /// Data available in Tx FIFO interrupt + /// enable + TXDAVLIE: u1, + /// Data available in Rx FIFO interrupt + /// enable + RXDAVLIE: u1, + /// SDIO mode interrupt received interrupt + /// enable + SDIOITIE: u1, + /// CE-ATA command completion signal + /// received interrupt enable + CEATAENDIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x3c); + + /// address: 0x40012c48 + /// FIFO counter register + pub const FIFOCNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Remaining number of words to be written + /// to or read from the FIFO. + FIFOCOUNT: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x48); + + /// address: 0x40012c80 + /// data FIFO register + pub const FIFO = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive and transmit FIFO + /// data + FIFOData: u32, + }), base_address + 0x80); + }; + + /// Analog-to-digital converter + pub const ADC1 = struct { + pub const base_address = 0x40012000; + + /// address: 0x40012000 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog flag + AWD: u1, + /// Regular channel end of + /// conversion + EOC: u1, + /// Injected channel end of + /// conversion + JEOC: u1, + /// Injected channel start + /// flag + JSTRT: u1, + /// Regular channel start flag + STRT: u1, + /// Overrun + OVR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x0); + + /// address: 0x40012004 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog channel select + /// bits + AWDCH: u5, + /// Interrupt enable for EOC + EOCIE: u1, + /// Analog watchdog interrupt + /// enable + AWDIE: u1, + /// Interrupt enable for injected + /// channels + JEOCIE: u1, + /// Scan mode + SCAN: u1, + /// Enable the watchdog on a single channel + /// in scan mode + AWDSGL: u1, + /// Automatic injected group + /// conversion + JAUTO: u1, + /// Discontinuous mode on regular + /// channels + DISCEN: u1, + /// Discontinuous mode on injected + /// channels + JDISCEN: u1, + /// Discontinuous mode channel + /// count + DISCNUM: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Analog watchdog enable on injected + /// channels + JAWDEN: u1, + /// Analog watchdog enable on regular + /// channels + AWDEN: u1, + /// Resolution + RES: u2, + /// Overrun interrupt enable + OVRIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x4); + + /// address: 0x40012008 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// A/D Converter ON / OFF + ADON: u1, + /// Continuous conversion + CONT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Direct memory access mode (for single + /// ADC mode) + DMA: u1, + /// DMA disable selection (for single ADC + /// mode) + DDS: u1, + /// End of conversion + /// selection + EOCS: u1, + /// Data alignment + ALIGN: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// External event select for injected + /// group + JEXTSEL: u4, + /// External trigger enable for injected + /// channels + JEXTEN: u2, + /// Start conversion of injected + /// channels + JSWSTART: u1, + reserved10: u1, + /// External event select for regular + /// group + EXTSEL: u4, + /// External trigger enable for regular + /// channels + EXTEN: u2, + /// Start conversion of regular + /// channels + SWSTART: u1, + padding0: u1, + }), base_address + 0x8); + + /// address: 0x4001200c + /// sample time register 1 + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Sample time bits + SMPx_x: u32, + }), base_address + 0xc); + + /// address: 0x40012010 + /// sample time register 2 + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Sample time bits + SMPx_x: u32, + }), base_address + 0x10); + + /// address: 0x40012014 + /// injected channel data offset register + /// x + pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET1: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40012018 + /// injected channel data offset register + /// x + pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET2: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x18); + + /// address: 0x4001201c + /// injected channel data offset register + /// x + pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET3: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40012020 + /// injected channel data offset register + /// x + pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET4: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x20); + + /// address: 0x40012024 + /// watchdog higher threshold + /// register + pub const HTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog higher + /// threshold + HT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x24); + + /// address: 0x40012028 + /// watchdog lower threshold + /// register + pub const LTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog lower + /// threshold + LT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x28); + + /// address: 0x4001202c + /// regular sequence register 1 + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// 13th conversion in regular + /// sequence + SQ13: u5, + /// 14th conversion in regular + /// sequence + SQ14: u5, + /// 15th conversion in regular + /// sequence + SQ15: u5, + /// 16th conversion in regular + /// sequence + SQ16: u5, + /// Regular channel sequence + /// length + L: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x2c); + + /// address: 0x40012030 + /// regular sequence register 2 + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// 7th conversion in regular + /// sequence + SQ7: u5, + /// 8th conversion in regular + /// sequence + SQ8: u5, + /// 9th conversion in regular + /// sequence + SQ9: u5, + /// 10th conversion in regular + /// sequence + SQ10: u5, + /// 11th conversion in regular + /// sequence + SQ11: u5, + /// 12th conversion in regular + /// sequence + SQ12: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x30); + + /// address: 0x40012034 + /// regular sequence register 3 + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// 1st conversion in regular + /// sequence + SQ1: u5, + /// 2nd conversion in regular + /// sequence + SQ2: u5, + /// 3rd conversion in regular + /// sequence + SQ3: u5, + /// 4th conversion in regular + /// sequence + SQ4: u5, + /// 5th conversion in regular + /// sequence + SQ5: u5, + /// 6th conversion in regular + /// sequence + SQ6: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x34); + + /// address: 0x40012038 + /// injected sequence register + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct { + /// 1st conversion in injected + /// sequence + JSQ1: u5, + /// 2nd conversion in injected + /// sequence + JSQ2: u5, + /// 3rd conversion in injected + /// sequence + JSQ3: u5, + /// 4th conversion in injected + /// sequence + JSQ4: u5, + /// Injected sequence length + JL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x38); + + /// address: 0x4001203c + /// injected data register x + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x3c); + + /// address: 0x40012040 + /// injected data register x + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x40); + + /// address: 0x40012044 + /// injected data register x + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + + /// address: 0x40012048 + /// injected data register x + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x4001204c + /// regular data register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { + /// Regular data + DATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + pub const ADC2 = struct { + pub const base_address = 0x40012100; + + /// address: 0x40012100 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog flag + AWD: u1, + /// Regular channel end of + /// conversion + EOC: u1, + /// Injected channel end of + /// conversion + JEOC: u1, + /// Injected channel start + /// flag + JSTRT: u1, + /// Regular channel start flag + STRT: u1, + /// Overrun + OVR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x0); + + /// address: 0x40012104 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog channel select + /// bits + AWDCH: u5, + /// Interrupt enable for EOC + EOCIE: u1, + /// Analog watchdog interrupt + /// enable + AWDIE: u1, + /// Interrupt enable for injected + /// channels + JEOCIE: u1, + /// Scan mode + SCAN: u1, + /// Enable the watchdog on a single channel + /// in scan mode + AWDSGL: u1, + /// Automatic injected group + /// conversion + JAUTO: u1, + /// Discontinuous mode on regular + /// channels + DISCEN: u1, + /// Discontinuous mode on injected + /// channels + JDISCEN: u1, + /// Discontinuous mode channel + /// count + DISCNUM: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Analog watchdog enable on injected + /// channels + JAWDEN: u1, + /// Analog watchdog enable on regular + /// channels + AWDEN: u1, + /// Resolution + RES: u2, + /// Overrun interrupt enable + OVRIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x4); + + /// address: 0x40012108 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// A/D Converter ON / OFF + ADON: u1, + /// Continuous conversion + CONT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Direct memory access mode (for single + /// ADC mode) + DMA: u1, + /// DMA disable selection (for single ADC + /// mode) + DDS: u1, + /// End of conversion + /// selection + EOCS: u1, + /// Data alignment + ALIGN: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// External event select for injected + /// group + JEXTSEL: u4, + /// External trigger enable for injected + /// channels + JEXTEN: u2, + /// Start conversion of injected + /// channels + JSWSTART: u1, + reserved10: u1, + /// External event select for regular + /// group + EXTSEL: u4, + /// External trigger enable for regular + /// channels + EXTEN: u2, + /// Start conversion of regular + /// channels + SWSTART: u1, + padding0: u1, + }), base_address + 0x8); + + /// address: 0x4001210c + /// sample time register 1 + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Sample time bits + SMPx_x: u32, + }), base_address + 0xc); + + /// address: 0x40012110 + /// sample time register 2 + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Sample time bits + SMPx_x: u32, + }), base_address + 0x10); + + /// address: 0x40012114 + /// injected channel data offset register + /// x + pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET1: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40012118 + /// injected channel data offset register + /// x + pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET2: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x18); + + /// address: 0x4001211c + /// injected channel data offset register + /// x + pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET3: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40012120 + /// injected channel data offset register + /// x + pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET4: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x20); + + /// address: 0x40012124 + /// watchdog higher threshold + /// register + pub const HTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog higher + /// threshold + HT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x24); + + /// address: 0x40012128 + /// watchdog lower threshold + /// register + pub const LTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog lower + /// threshold + LT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x28); + + /// address: 0x4001212c + /// regular sequence register 1 + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// 13th conversion in regular + /// sequence + SQ13: u5, + /// 14th conversion in regular + /// sequence + SQ14: u5, + /// 15th conversion in regular + /// sequence + SQ15: u5, + /// 16th conversion in regular + /// sequence + SQ16: u5, + /// Regular channel sequence + /// length + L: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x2c); + + /// address: 0x40012130 + /// regular sequence register 2 + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// 7th conversion in regular + /// sequence + SQ7: u5, + /// 8th conversion in regular + /// sequence + SQ8: u5, + /// 9th conversion in regular + /// sequence + SQ9: u5, + /// 10th conversion in regular + /// sequence + SQ10: u5, + /// 11th conversion in regular + /// sequence + SQ11: u5, + /// 12th conversion in regular + /// sequence + SQ12: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x30); + + /// address: 0x40012134 + /// regular sequence register 3 + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// 1st conversion in regular + /// sequence + SQ1: u5, + /// 2nd conversion in regular + /// sequence + SQ2: u5, + /// 3rd conversion in regular + /// sequence + SQ3: u5, + /// 4th conversion in regular + /// sequence + SQ4: u5, + /// 5th conversion in regular + /// sequence + SQ5: u5, + /// 6th conversion in regular + /// sequence + SQ6: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x34); + + /// address: 0x40012138 + /// injected sequence register + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct { + /// 1st conversion in injected + /// sequence + JSQ1: u5, + /// 2nd conversion in injected + /// sequence + JSQ2: u5, + /// 3rd conversion in injected + /// sequence + JSQ3: u5, + /// 4th conversion in injected + /// sequence + JSQ4: u5, + /// Injected sequence length + JL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x38); + + /// address: 0x4001213c + /// injected data register x + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x3c); + + /// address: 0x40012140 + /// injected data register x + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x40); + + /// address: 0x40012144 + /// injected data register x + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + + /// address: 0x40012148 + /// injected data register x + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x4001214c + /// regular data register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { + /// Regular data + DATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + pub const ADC3 = struct { + pub const base_address = 0x40012200; + + /// address: 0x40012200 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog flag + AWD: u1, + /// Regular channel end of + /// conversion + EOC: u1, + /// Injected channel end of + /// conversion + JEOC: u1, + /// Injected channel start + /// flag + JSTRT: u1, + /// Regular channel start flag + STRT: u1, + /// Overrun + OVR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x0); + + /// address: 0x40012204 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog channel select + /// bits + AWDCH: u5, + /// Interrupt enable for EOC + EOCIE: u1, + /// Analog watchdog interrupt + /// enable + AWDIE: u1, + /// Interrupt enable for injected + /// channels + JEOCIE: u1, + /// Scan mode + SCAN: u1, + /// Enable the watchdog on a single channel + /// in scan mode + AWDSGL: u1, + /// Automatic injected group + /// conversion + JAUTO: u1, + /// Discontinuous mode on regular + /// channels + DISCEN: u1, + /// Discontinuous mode on injected + /// channels + JDISCEN: u1, + /// Discontinuous mode channel + /// count + DISCNUM: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Analog watchdog enable on injected + /// channels + JAWDEN: u1, + /// Analog watchdog enable on regular + /// channels + AWDEN: u1, + /// Resolution + RES: u2, + /// Overrun interrupt enable + OVRIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x4); + + /// address: 0x40012208 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// A/D Converter ON / OFF + ADON: u1, + /// Continuous conversion + CONT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Direct memory access mode (for single + /// ADC mode) + DMA: u1, + /// DMA disable selection (for single ADC + /// mode) + DDS: u1, + /// End of conversion + /// selection + EOCS: u1, + /// Data alignment + ALIGN: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// External event select for injected + /// group + JEXTSEL: u4, + /// External trigger enable for injected + /// channels + JEXTEN: u2, + /// Start conversion of injected + /// channels + JSWSTART: u1, + reserved10: u1, + /// External event select for regular + /// group + EXTSEL: u4, + /// External trigger enable for regular + /// channels + EXTEN: u2, + /// Start conversion of regular + /// channels + SWSTART: u1, + padding0: u1, + }), base_address + 0x8); + + /// address: 0x4001220c + /// sample time register 1 + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Sample time bits + SMPx_x: u32, + }), base_address + 0xc); + + /// address: 0x40012210 + /// sample time register 2 + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Sample time bits + SMPx_x: u32, + }), base_address + 0x10); + + /// address: 0x40012214 + /// injected channel data offset register + /// x + pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET1: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40012218 + /// injected channel data offset register + /// x + pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET2: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x18); + + /// address: 0x4001221c + /// injected channel data offset register + /// x + pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET3: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40012220 + /// injected channel data offset register + /// x + pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET4: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x20); + + /// address: 0x40012224 + /// watchdog higher threshold + /// register + pub const HTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog higher + /// threshold + HT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x24); + + /// address: 0x40012228 + /// watchdog lower threshold + /// register + pub const LTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog lower + /// threshold + LT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x28); + + /// address: 0x4001222c + /// regular sequence register 1 + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// 13th conversion in regular + /// sequence + SQ13: u5, + /// 14th conversion in regular + /// sequence + SQ14: u5, + /// 15th conversion in regular + /// sequence + SQ15: u5, + /// 16th conversion in regular + /// sequence + SQ16: u5, + /// Regular channel sequence + /// length + L: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x2c); + + /// address: 0x40012230 + /// regular sequence register 2 + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// 7th conversion in regular + /// sequence + SQ7: u5, + /// 8th conversion in regular + /// sequence + SQ8: u5, + /// 9th conversion in regular + /// sequence + SQ9: u5, + /// 10th conversion in regular + /// sequence + SQ10: u5, + /// 11th conversion in regular + /// sequence + SQ11: u5, + /// 12th conversion in regular + /// sequence + SQ12: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x30); + + /// address: 0x40012234 + /// regular sequence register 3 + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// 1st conversion in regular + /// sequence + SQ1: u5, + /// 2nd conversion in regular + /// sequence + SQ2: u5, + /// 3rd conversion in regular + /// sequence + SQ3: u5, + /// 4th conversion in regular + /// sequence + SQ4: u5, + /// 5th conversion in regular + /// sequence + SQ5: u5, + /// 6th conversion in regular + /// sequence + SQ6: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x34); + + /// address: 0x40012238 + /// injected sequence register + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct { + /// 1st conversion in injected + /// sequence + JSQ1: u5, + /// 2nd conversion in injected + /// sequence + JSQ2: u5, + /// 3rd conversion in injected + /// sequence + JSQ3: u5, + /// 4th conversion in injected + /// sequence + JSQ4: u5, + /// Injected sequence length + JL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x38); + + /// address: 0x4001223c + /// injected data register x + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x3c); + + /// address: 0x40012240 + /// injected data register x + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x40); + + /// address: 0x40012244 + /// injected data register x + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + + /// address: 0x40012248 + /// injected data register x + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x4001224c + /// regular data register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { + /// Regular data + DATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + + /// Universal synchronous asynchronous receiver + /// transmitter + pub const USART6 = struct { + pub const base_address = 0x40011400; + + /// address: 0x40011400 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS flag + CTS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40011404 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40011408 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001140c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + reserved0: u1, + /// Oversampling mode + OVER8: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40011410 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40011414 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40011418 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + }; + pub const USART1 = struct { + pub const base_address = 0x40011000; + + /// address: 0x40011000 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS flag + CTS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40011004 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40011008 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001100c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + reserved0: u1, + /// Oversampling mode + OVER8: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40011010 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40011014 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40011018 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + }; + pub const USART2 = struct { + pub const base_address = 0x40004400; + + /// address: 0x40004400 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS flag + CTS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40004404 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40004408 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000440c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + reserved0: u1, + /// Oversampling mode + OVER8: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40004410 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40004414 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40004418 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + }; + pub const USART3 = struct { + pub const base_address = 0x40004800; + + /// address: 0x40004800 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS flag + CTS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40004804 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40004808 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000480c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + reserved0: u1, + /// Oversampling mode + OVER8: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40004810 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40004814 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40004818 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + }; + pub const UART7 = struct { + pub const base_address = 0x40007800; + + /// address: 0x40007800 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS flag + CTS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40007804 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40007808 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000780c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + reserved0: u1, + /// Oversampling mode + OVER8: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40007810 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40007814 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40007818 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + }; + pub const UART8 = struct { + pub const base_address = 0x40007c00; + + /// address: 0x40007c00 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS flag + CTS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40007c04 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40007c08 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40007c0c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + reserved0: u1, + /// Oversampling mode + OVER8: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40007c10 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40007c14 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40007c18 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + }; + + /// Digital-to-analog converter + pub const DAC = struct { + pub const base_address = 0x40007400; + + /// address: 0x40007400 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel1 enable + EN1: u1, + /// DAC channel1 output buffer + /// disable + BOFF1: u1, + /// DAC channel1 trigger + /// enable + TEN1: u1, + /// DAC channel1 trigger + /// selection + TSEL1: u3, + /// DAC channel1 noise/triangle wave + /// generation enable + WAVE1: u2, + /// DAC channel1 mask/amplitude + /// selector + MAMP1: u4, + /// DAC channel1 DMA enable + DMAEN1: u1, + /// DAC channel1 DMA Underrun Interrupt + /// enable + DMAUDRIE1: u1, + reserved0: u1, + reserved1: u1, + /// DAC channel2 enable + EN2: u1, + /// DAC channel2 output buffer + /// disable + BOFF2: u1, + /// DAC channel2 trigger + /// enable + TEN2: u1, + /// DAC channel2 trigger + /// selection + TSEL2: u3, + /// DAC channel2 noise/triangle wave + /// generation enable + WAVE2: u2, + /// DAC channel2 mask/amplitude + /// selector + MAMP2: u4, + /// DAC channel2 DMA enable + DMAEN2: u1, + /// DAC channel2 DMA underrun interrupt + /// enable + DMAUDRIE2: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x0); + + /// address: 0x40007404 + /// software trigger register + pub const SWTRIGR = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel1 software + /// trigger + SWTRIG1: u1, + /// DAC channel2 software + /// trigger + SWTRIG2: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x4); + + /// address: 0x40007408 + /// channel1 12-bit right-aligned data holding + /// register + pub const DHR12R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel1 12-bit right-aligned + /// data + DACC1DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x8); + + /// address: 0x4000740c + /// channel1 12-bit left aligned data holding + /// register + pub const DHR12L1 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC channel1 12-bit left-aligned + /// data + DACC1DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40007410 + /// channel1 8-bit right aligned data holding + /// register + pub const DHR8R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel1 8-bit right-aligned + /// data + DACC1DHR: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x10); + + /// address: 0x40007414 + /// channel2 12-bit right aligned data holding + /// register + pub const DHR12R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel2 12-bit right-aligned + /// data + DACC2DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40007418 + /// channel2 12-bit left aligned data holding + /// register + pub const DHR12L2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC channel2 12-bit left-aligned + /// data + DACC2DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000741c + /// channel2 8-bit right-aligned data holding + /// register + pub const DHR8R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel2 8-bit right-aligned + /// data + DACC2DHR: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x1c); + + /// address: 0x40007420 + /// Dual DAC 12-bit right-aligned data holding + /// register + pub const DHR12RD = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel1 12-bit right-aligned + /// data + DACC1DHR: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC channel2 12-bit right-aligned + /// data + DACC2DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x20); + + /// address: 0x40007424 + /// DUAL DAC 12-bit left aligned data holding + /// register + pub const DHR12LD = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC channel1 12-bit left-aligned + /// data + DACC1DHR: u12, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// DAC channel2 12-bit left-aligned + /// data + DACC2DHR: u12, + }), base_address + 0x24); + + /// address: 0x40007428 + /// DUAL DAC 8-bit right aligned data holding + /// register + pub const DHR8RD = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel1 8-bit right-aligned + /// data + DACC1DHR: u8, + /// DAC channel2 8-bit right-aligned + /// data + DACC2DHR: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + + /// address: 0x4000742c + /// channel1 data output register + pub const DOR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel1 data output + DACC1DOR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x2c); + + /// address: 0x40007430 + /// channel2 data output register + pub const DOR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel2 data output + DACC2DOR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x30); + + /// address: 0x40007434 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// DAC channel1 DMA underrun + /// flag + DMAUDR1: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + reserved26: u1, + reserved27: u1, + /// DAC channel2 DMA underrun + /// flag + DMAUDR2: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x34); + }; + + /// Power control + pub const PWR = struct { + pub const base_address = 0x40007000; + + /// address: 0x40007000 + /// power control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Low-power deep sleep + LPDS: u1, + /// Power down deepsleep + PDDS: u1, + /// Clear wakeup flag + CWUF: u1, + /// Clear standby flag + CSBF: u1, + /// Power voltage detector + /// enable + PVDE: u1, + /// PVD level selection + PLS: u3, + /// Disable backup domain write + /// protection + DBP: u1, + /// Flash power down in Stop + /// mode + FPDS: u1, + /// Low-Power Regulator Low Voltage in + /// deepsleep + LPLVDS: u1, + /// Main regulator low voltage in deepsleep + /// mode + MRLVDS: u1, + reserved0: u1, + reserved1: u1, + /// Regulator voltage scaling output + /// selection + VOS: u2, + /// Over-drive enable + ODEN: u1, + /// Over-drive switching + /// enabled + ODSWEN: u1, + /// Under-drive enable in stop + /// mode + UDEN: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x0); + + /// address: 0x40007004 + /// power control/status register + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Wakeup flag + WUF: u1, + /// Standby flag + SBF: u1, + /// PVD output + PVDO: u1, + /// Backup regulator ready + BRR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Enable WKUP pin + EWUP: u1, + /// Backup regulator enable + BRE: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Regulator voltage scaling output + /// selection ready bit + VOSRDY: u1, + reserved8: u1, + /// Over-drive mode ready + ODRDY: u1, + /// Over-drive mode switching + /// ready + ODSWRDY: u1, + /// Under-drive ready flag + UDRDY: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x4); + }; + + /// Independent watchdog + pub const IWDG = struct { + pub const base_address = 0x40003000; + + /// address: 0x40003000 + /// Key register + pub const KR = @intToPtr(*volatile Mmio(32, packed struct { + /// Key value (write only, read + /// 0000h) + KEY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// Prescaler register + pub const PR = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x4); + + /// address: 0x40003008 + /// Reload register + pub const RLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Watchdog counter reload + /// value + RL: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x8); + + /// address: 0x4000300c + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Watchdog prescaler value + /// update + PVU: u1, + /// Watchdog counter reload value + /// update + RVU: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + }; + + /// Window watchdog + pub const WWDG = struct { + pub const base_address = 0x40002c00; + + /// address: 0x40002c00 + /// Control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// 7-bit counter (MSB to LSB) + T: u7, + /// Activation bit + WDGA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x0); + + /// address: 0x40002c04 + /// Configuration register + pub const CFR = @intToPtr(*volatile Mmio(32, packed struct { + /// 7-bit window value + W: u7, + /// Timer base + WDGTB0: u1, + /// Timer base + WDGTB1: u1, + /// Early wakeup interrupt + EWI: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x4); + + /// address: 0x40002c08 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Early wakeup interrupt + /// flag + EWIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x8); + }; + + /// Real-time clock + pub const RTC = struct { + pub const base_address = 0x40002800; + + /// address: 0x40002800 + /// time register + pub const TR = @intToPtr(*volatile Mmio(32, packed struct { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved0: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved1: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x0); + + /// address: 0x40002804 + /// date register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved0: u1, + reserved1: u1, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + /// Year units in BCD format + YU: u4, + /// Year tens in BCD format + YT: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40002808 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Wakeup clock selection + WCKSEL: u3, + /// Time-stamp event active + /// edge + TSEDGE: u1, + /// Reference clock detection enable (50 or + /// 60 Hz) + REFCKON: u1, + reserved0: u1, + /// Hour format + FMT: u1, + /// Coarse digital calibration + /// enable + DCE: u1, + /// Alarm A enable + ALRAE: u1, + /// Alarm B enable + ALRBE: u1, + /// Wakeup timer enable + WUTE: u1, + /// Time stamp enable + TSE: u1, + /// Alarm A interrupt enable + ALRAIE: u1, + /// Alarm B interrupt enable + ALRBIE: u1, + /// Wakeup timer interrupt + /// enable + WUTIE: u1, + /// Time-stamp interrupt + /// enable + TSIE: u1, + /// Add 1 hour (summer time + /// change) + ADD1H: u1, + /// Subtract 1 hour (winter time + /// change) + SUB1H: u1, + /// Backup + BKP: u1, + reserved1: u1, + /// Output polarity + POL: u1, + /// Output selection + OSEL: u2, + /// Calibration output enable + COE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x8); + + /// address: 0x4000280c + /// initialization and status + /// register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Alarm A write flag + ALRAWF: u1, + /// Alarm B write flag + ALRBWF: u1, + /// Wakeup timer write flag + WUTWF: u1, + /// Shift operation pending + SHPF: u1, + /// Initialization status flag + INITS: u1, + /// Registers synchronization + /// flag + RSF: u1, + /// Initialization flag + INITF: u1, + /// Initialization mode + INIT: u1, + /// Alarm A flag + ALRAF: u1, + /// Alarm B flag + ALRBF: u1, + /// Wakeup timer flag + WUTF: u1, + /// Time-stamp flag + TSF: u1, + /// Time-stamp overflow flag + TSOVF: u1, + /// Tamper detection flag + TAMP1F: u1, + /// TAMPER2 detection flag + TAMP2F: u1, + reserved0: u1, + /// Recalibration pending Flag + RECALPF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0xc); + + /// address: 0x40002810 + /// prescaler register + pub const PRER = @intToPtr(*volatile Mmio(32, packed struct { + /// Synchronous prescaler + /// factor + PREDIV_S: u15, + reserved0: u1, + /// Asynchronous prescaler + /// factor + PREDIV_A: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x10); + + /// address: 0x40002814 + /// wakeup timer register + pub const WUTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Wakeup auto-reload value + /// bits + WUT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40002818 + /// calibration register + pub const CALIBR = @intToPtr(*volatile Mmio(32, packed struct { + /// Digital calibration + DC: u5, + reserved0: u1, + reserved1: u1, + /// Digital calibration sign + DCS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + + /// address: 0x4000281c + /// alarm A register + pub const ALRMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + /// Alarm A seconds mask + MSK1: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + /// Alarm A minutes mask + MSK2: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + /// Alarm A hours mask + MSK3: u1, + /// Date units or day in BCD + /// format + DU: u4, + /// Date tens in BCD format + DT: u2, + /// Week day selection + WDSEL: u1, + /// Alarm A date mask + MSK4: u1, + }), base_address + 0x1c); + + /// address: 0x40002820 + /// alarm B register + pub const ALRMBR = @intToPtr(*volatile Mmio(32, packed struct { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + /// Alarm B seconds mask + MSK1: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + /// Alarm B minutes mask + MSK2: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + /// Alarm B hours mask + MSK3: u1, + /// Date units or day in BCD + /// format + DU: u4, + /// Date tens in BCD format + DT: u2, + /// Week day selection + WDSEL: u1, + /// Alarm B date mask + MSK4: u1, + }), base_address + 0x20); + + /// address: 0x40002824 + /// write protection register + pub const WPR = @intToPtr(*volatile Mmio(32, packed struct { + /// Write protection key + KEY: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x24); + + /// address: 0x40002828 + /// sub second register + pub const SSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Sub second value + SS: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + + /// address: 0x4000282c + /// shift control register + pub const SHIFTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Subtract a fraction of a + /// second + SUBFS: u15, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Add one second + ADD1S: u1, + }), base_address + 0x2c); + + /// address: 0x40002830 + /// time stamp time register + pub const TSTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tamper 1 detection enable + TAMP1E: u1, + /// Active level for tamper 1 + TAMP1TRG: u1, + /// Tamper interrupt enable + TAMPIE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// TAMPER1 mapping + TAMP1INSEL: u1, + /// TIMESTAMP mapping + TSINSEL: u1, + /// AFO_ALARM output type + ALARMOUTTYPE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x30); + + /// address: 0x40002834 + /// time stamp date register + pub const TSDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved0: u1, + reserved1: u1, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x34); + + /// address: 0x40002838 + /// timestamp sub second register + pub const TSSSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Sub second value + SS: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x38); + + /// address: 0x4000283c + /// calibration register + pub const CALR = @intToPtr(*volatile Mmio(32, packed struct { + /// Calibration minus + CALM: u9, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Use a 16-second calibration cycle + /// period + CALW16: u1, + /// Use an 8-second calibration cycle + /// period + CALW8: u1, + /// Increase frequency of RTC by 488.5 + /// ppm + CALP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x3c); + + /// address: 0x40002840 + /// tamper and alternate function configuration + /// register + pub const TAFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tamper 1 detection enable + TAMP1E: u1, + /// Active level for tamper 1 + TAMP1TRG: u1, + /// Tamper interrupt enable + TAMPIE: u1, + /// Tamper 2 detection enable + TAMP2E: u1, + /// Active level for tamper 2 + TAMP2TRG: u1, + reserved0: u1, + reserved1: u1, + /// Activate timestamp on tamper detection + /// event + TAMPTS: u1, + /// Tamper sampling frequency + TAMPFREQ: u3, + /// Tamper filter count + TAMPFLT: u2, + /// Tamper precharge duration + TAMPPRCH: u2, + /// TAMPER pull-up disable + TAMPPUDIS: u1, + /// TAMPER1 mapping + TAMP1INSEL: u1, + /// TIMESTAMP mapping + TSINSEL: u1, + /// AFO_ALARM output type + ALARMOUTTYPE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x40); + + /// address: 0x40002844 + /// alarm A sub second register + pub const ALRMASSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Sub seconds value + SS: u15, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Mask the most-significant bits starting + /// at this bit + MASKSS: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x44); + + /// address: 0x40002848 + /// alarm B sub second register + pub const ALRMBSSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Sub seconds value + SS: u15, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Mask the most-significant bits starting + /// at this bit + MASKSS: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x48); + + /// address: 0x40002850 + /// backup register + pub const BKP0R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x50); + + /// address: 0x40002854 + /// backup register + pub const BKP1R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x54); + + /// address: 0x40002858 + /// backup register + pub const BKP2R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x58); + + /// address: 0x4000285c + /// backup register + pub const BKP3R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x5c); + + /// address: 0x40002860 + /// backup register + pub const BKP4R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x60); + + /// address: 0x40002864 + /// backup register + pub const BKP5R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x64); + + /// address: 0x40002868 + /// backup register + pub const BKP6R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x68); + + /// address: 0x4000286c + /// backup register + pub const BKP7R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x6c); + + /// address: 0x40002870 + /// backup register + pub const BKP8R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x70); + + /// address: 0x40002874 + /// backup register + pub const BKP9R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x74); + + /// address: 0x40002878 + /// backup register + pub const BKP10R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x78); + + /// address: 0x4000287c + /// backup register + pub const BKP11R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x7c); + + /// address: 0x40002880 + /// backup register + pub const BKP12R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x80); + + /// address: 0x40002884 + /// backup register + pub const BKP13R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x84); + + /// address: 0x40002888 + /// backup register + pub const BKP14R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x88); + + /// address: 0x4000288c + /// backup register + pub const BKP15R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x8c); + + /// address: 0x40002890 + /// backup register + pub const BKP16R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x90); + + /// address: 0x40002894 + /// backup register + pub const BKP17R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x94); + + /// address: 0x40002898 + /// backup register + pub const BKP18R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x98); + + /// address: 0x4000289c + /// backup register + pub const BKP19R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x9c); + }; + + /// Universal synchronous asynchronous receiver + /// transmitter + pub const UART4 = struct { + pub const base_address = 0x40004c00; + + /// address: 0x40004c00 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x0); + + /// address: 0x40004c04 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40004c08 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40004c0c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + reserved0: u1, + /// Oversampling mode + OVER8: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40004c10 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40004c14 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + reserved0: u1, + reserved1: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + }; + pub const UART5 = struct { + pub const base_address = 0x40005000; + + /// address: 0x40005000 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x0); + + /// address: 0x40005004 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40005008 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000500c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + reserved0: u1, + /// Oversampling mode + OVER8: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40005010 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40005014 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + reserved0: u1, + reserved1: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + }; + + /// Common ADC registers + pub const C_ADC = struct { + pub const base_address = 0x40012300; + + /// address: 0x40012300 + /// ADC Common status register + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog flag of ADC + /// 1 + AWD1: u1, + /// End of conversion of ADC 1 + EOC1: u1, + /// Injected channel end of conversion of + /// ADC 1 + JEOC1: u1, + /// Injected channel Start flag of ADC + /// 1 + JSTRT1: u1, + /// Regular channel Start flag of ADC + /// 1 + STRT1: u1, + /// Overrun flag of ADC 1 + OVR1: u1, + reserved0: u1, + reserved1: u1, + /// Analog watchdog flag of ADC + /// 2 + AWD2: u1, + /// End of conversion of ADC 2 + EOC2: u1, + /// Injected channel end of conversion of + /// ADC 2 + JEOC2: u1, + /// Injected channel Start flag of ADC + /// 2 + JSTRT2: u1, + /// Regular channel Start flag of ADC + /// 2 + STRT2: u1, + /// Overrun flag of ADC 2 + OVR2: u1, + reserved2: u1, + reserved3: u1, + /// Analog watchdog flag of ADC + /// 3 + AWD3: u1, + /// End of conversion of ADC 3 + EOC3: u1, + /// Injected channel end of conversion of + /// ADC 3 + JEOC3: u1, + /// Injected channel Start flag of ADC + /// 3 + JSTRT3: u1, + /// Regular channel Start flag of ADC + /// 3 + STRT3: u1, + /// Overrun flag of ADC3 + OVR3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x0); + + /// address: 0x40012304 + /// ADC common control register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Multi ADC mode selection + MULT: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Delay between 2 sampling + /// phases + DELAY: u4, + reserved3: u1, + /// DMA disable selection for multi-ADC + /// mode + DDS: u1, + /// Direct memory access mode for multi ADC + /// mode + DMA: u2, + /// ADC prescaler + ADCPRE: u2, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// VBAT enable + VBATE: u1, + /// Temperature sensor and VREFINT + /// enable + TSVREFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40012308 + /// ADC common regular data register for dual + /// and triple modes + pub const CDR = @intToPtr(*volatile Mmio(32, packed struct { + /// 1st data item of a pair of regular + /// conversions + DATA1: u16, + /// 2nd data item of a pair of regular + /// conversions + DATA2: u16, + }), base_address + 0x8); + }; + + /// Advanced-timers + pub const TIM1 = struct { + pub const base_address = 0x40010000; + + /// address: 0x40010000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40010004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/compare preloaded + /// control + CCPC: u1, + reserved0: u1, + /// Capture/compare control update + /// selection + CCUS: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + /// Output Idle state 2 + OIS2: u1, + /// Output Idle state 2 + OIS2N: u1, + /// Output Idle state 3 + OIS3: u1, + /// Output Idle state 3 + OIS3N: u1, + /// Output Idle state 4 + OIS4: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + + /// address: 0x40010008 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001000c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40010010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + reserved0: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40010014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + /// Capture/Compare control update + /// generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x14); + + /// address: 0x40010018 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + /// Output Compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output Compare 2 fast + /// enable + OC2FE: u1, + /// Output Compare 2 preload + /// enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + /// Output Compare 2 clear + /// enable + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40010018 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4001001c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + OC4CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x4001001c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40010020 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output + /// enable + CC1NE: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + /// Capture/Compare 2 complementary output + /// enable + CC2NE: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + /// Capture/Compare 3 complementary output + /// enable + CC3NE: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x20); + + /// address: 0x40010024 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40010028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001002c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40010034 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40010038 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + + /// address: 0x4001003c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); + + /// address: 0x40010040 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); + + /// address: 0x40010048 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4001004c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + + /// address: 0x40010030 + /// repetition counter register + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Repetition counter value + REP: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x30); + + /// address: 0x40010044 + /// break and dead-time register + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle + /// mode + OSSI: u1, + /// Off-state selection for Run + /// mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + }; + pub const TIM8 = struct { + pub const base_address = 0x40010400; + + /// address: 0x40010400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40010404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/compare preloaded + /// control + CCPC: u1, + reserved0: u1, + /// Capture/compare control update + /// selection + CCUS: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + /// Output Idle state 2 + OIS2: u1, + /// Output Idle state 2 + OIS2N: u1, + /// Output Idle state 3 + OIS3: u1, + /// Output Idle state 3 + OIS3N: u1, + /// Output Idle state 4 + OIS4: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + + /// address: 0x40010408 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001040c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40010410 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + reserved0: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40010414 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + /// Capture/Compare control update + /// generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x14); + + /// address: 0x40010418 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + /// Output Compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output Compare 2 fast + /// enable + OC2FE: u1, + /// Output Compare 2 preload + /// enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + /// Output Compare 2 clear + /// enable + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40010418 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4001041c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + OC4CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x4001041c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40010420 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output + /// enable + CC1NE: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + /// Capture/Compare 2 complementary output + /// enable + CC2NE: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + /// Capture/Compare 3 complementary output + /// enable + CC3NE: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x20); + + /// address: 0x40010424 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40010428 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001042c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40010434 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40010438 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + + /// address: 0x4001043c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); + + /// address: 0x40010440 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); + + /// address: 0x40010448 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4001044c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + + /// address: 0x40010430 + /// repetition counter register + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Repetition counter value + REP: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x30); + + /// address: 0x40010444 + /// break and dead-time register + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle + /// mode + OSSI: u1, + /// Off-state selection for Run + /// mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + }; + + /// General purpose timers + pub const TIM2 = struct { + pub const base_address = 0x40000000; + + /// address: 0x40000000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40000004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40000008 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000000c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TIE: u1, + reserved1: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + reserved2: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40000010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TIF: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40000014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + reserved0: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40000018 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// CC1S + CC1S: u2, + /// OC1FE + OC1FE: u1, + /// OC1PE + OC1PE: u1, + /// OC1M + OC1M: u3, + /// OC1CE + OC1CE: u1, + /// CC2S + CC2S: u2, + /// OC2FE + OC2FE: u1, + /// OC2PE + OC2PE: u1, + /// OC2M + OC2M: u3, + /// OC2CE + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40000018 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000001c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// CC3S + CC3S: u2, + /// OC3FE + OC3FE: u1, + /// OC3PE + OC3PE: u1, + /// OC3M + OC3M: u3, + /// OC3CE + OC3CE: u1, + /// CC4S + CC4S: u2, + /// OC4FE + OC4FE: u1, + /// OC4PE + OC4PE: u1, + /// OC4M + OC4M: u3, + /// O24CE + O24CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x4000001c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000020 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + reserved2: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + reserved3: u1, + /// Capture/Compare 4 output + /// Polarity + CC4NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40000024 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Low counter value + CNT_L: u16, + /// High counter value + CNT_H: u16, + }), base_address + 0x24); + + /// address: 0x40000028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000002c + /// auto-reload register + pub const ARR = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Auto-reload value + ARR_L: u16, + /// High Auto-reload value + ARR_H: u16, + }), base_address + 0x2c); + + /// address: 0x40000034 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare 1 + /// value + CCR1_L: u16, + /// High Capture/Compare 1 + /// value + CCR1_H: u16, + }), base_address + 0x34); + + /// address: 0x40000038 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare 2 + /// value + CCR2_L: u16, + /// High Capture/Compare 2 + /// value + CCR2_H: u16, + }), base_address + 0x38); + + /// address: 0x4000003c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare value + CCR3_L: u16, + /// High Capture/Compare value + CCR3_H: u16, + }), base_address + 0x3c); + + /// address: 0x40000040 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare value + CCR4_L: u16, + /// High Capture/Compare value + CCR4_H: u16, + }), base_address + 0x40); + + /// address: 0x40000048 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4000004c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + + /// address: 0x40000050 + /// TIM5 option register + pub const OR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Timer Input 4 remap + ITR1_RMP: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x50); + }; + + /// General purpose timers + pub const TIM3 = struct { + pub const base_address = 0x40000400; + + /// address: 0x40000400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40000404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40000408 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000040c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TIE: u1, + reserved1: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + reserved2: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40000410 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TIF: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40000414 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + reserved0: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40000418 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// CC1S + CC1S: u2, + /// OC1FE + OC1FE: u1, + /// OC1PE + OC1PE: u1, + /// OC1M + OC1M: u3, + /// OC1CE + OC1CE: u1, + /// CC2S + CC2S: u2, + /// OC2FE + OC2FE: u1, + /// OC2PE + OC2PE: u1, + /// OC2M + OC2M: u3, + /// OC2CE + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40000418 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000041c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// CC3S + CC3S: u2, + /// OC3FE + OC3FE: u1, + /// OC3PE + OC3PE: u1, + /// OC3M + OC3M: u3, + /// OC3CE + OC3CE: u1, + /// CC4S + CC4S: u2, + /// OC4FE + OC4FE: u1, + /// OC4PE + OC4PE: u1, + /// OC4M + OC4M: u3, + /// O24CE + O24CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x4000041c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000420 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + reserved2: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + reserved3: u1, + /// Capture/Compare 4 output + /// Polarity + CC4NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40000424 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Low counter value + CNT_L: u16, + /// High counter value + CNT_H: u16, + }), base_address + 0x24); + + /// address: 0x40000428 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000042c + /// auto-reload register + pub const ARR = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Auto-reload value + ARR_L: u16, + /// High Auto-reload value + ARR_H: u16, + }), base_address + 0x2c); + + /// address: 0x40000434 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare 1 + /// value + CCR1_L: u16, + /// High Capture/Compare 1 + /// value + CCR1_H: u16, + }), base_address + 0x34); + + /// address: 0x40000438 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare 2 + /// value + CCR2_L: u16, + /// High Capture/Compare 2 + /// value + CCR2_H: u16, + }), base_address + 0x38); + + /// address: 0x4000043c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare value + CCR3_L: u16, + /// High Capture/Compare value + CCR3_H: u16, + }), base_address + 0x3c); + + /// address: 0x40000440 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare value + CCR4_L: u16, + /// High Capture/Compare value + CCR4_H: u16, + }), base_address + 0x40); + + /// address: 0x40000448 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4000044c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + pub const TIM4 = struct { + pub const base_address = 0x40000800; + + /// address: 0x40000800 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40000804 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40000808 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000080c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TIE: u1, + reserved1: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + reserved2: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40000810 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TIF: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40000814 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + reserved0: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40000818 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// CC1S + CC1S: u2, + /// OC1FE + OC1FE: u1, + /// OC1PE + OC1PE: u1, + /// OC1M + OC1M: u3, + /// OC1CE + OC1CE: u1, + /// CC2S + CC2S: u2, + /// OC2FE + OC2FE: u1, + /// OC2PE + OC2PE: u1, + /// OC2M + OC2M: u3, + /// OC2CE + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40000818 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000081c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// CC3S + CC3S: u2, + /// OC3FE + OC3FE: u1, + /// OC3PE + OC3PE: u1, + /// OC3M + OC3M: u3, + /// OC3CE + OC3CE: u1, + /// CC4S + CC4S: u2, + /// OC4FE + OC4FE: u1, + /// OC4PE + OC4PE: u1, + /// OC4M + OC4M: u3, + /// O24CE + O24CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x4000081c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000820 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + reserved2: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + reserved3: u1, + /// Capture/Compare 4 output + /// Polarity + CC4NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40000824 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Low counter value + CNT_L: u16, + /// High counter value + CNT_H: u16, + }), base_address + 0x24); + + /// address: 0x40000828 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000082c + /// auto-reload register + pub const ARR = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Auto-reload value + ARR_L: u16, + /// High Auto-reload value + ARR_H: u16, + }), base_address + 0x2c); + + /// address: 0x40000834 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare 1 + /// value + CCR1_L: u16, + /// High Capture/Compare 1 + /// value + CCR1_H: u16, + }), base_address + 0x34); + + /// address: 0x40000838 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare 2 + /// value + CCR2_L: u16, + /// High Capture/Compare 2 + /// value + CCR2_H: u16, + }), base_address + 0x38); + + /// address: 0x4000083c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare value + CCR3_L: u16, + /// High Capture/Compare value + CCR3_H: u16, + }), base_address + 0x3c); + + /// address: 0x40000840 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare value + CCR4_L: u16, + /// High Capture/Compare value + CCR4_H: u16, + }), base_address + 0x40); + + /// address: 0x40000848 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4000084c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + + /// General-purpose-timers + pub const TIM5 = struct { + pub const base_address = 0x40000c00; + + /// address: 0x40000c00 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40000c04 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40000c08 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40000c0c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TIE: u1, + reserved1: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + reserved2: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40000c10 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TIF: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40000c14 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + reserved0: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40000c18 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// CC1S + CC1S: u2, + /// OC1FE + OC1FE: u1, + /// OC1PE + OC1PE: u1, + /// OC1M + OC1M: u3, + /// OC1CE + OC1CE: u1, + /// CC2S + CC2S: u2, + /// OC2FE + OC2FE: u1, + /// OC2PE + OC2PE: u1, + /// OC2M + OC2M: u3, + /// OC2CE + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40000c18 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40000c1c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// CC3S + CC3S: u2, + /// OC3FE + OC3FE: u1, + /// OC3PE + OC3PE: u1, + /// OC3M + OC3M: u3, + /// OC3CE + OC3CE: u1, + /// CC4S + CC4S: u2, + /// OC4FE + OC4FE: u1, + /// OC4PE + OC4PE: u1, + /// OC4M + OC4M: u3, + /// O24CE + O24CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000c1c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000c20 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + reserved2: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + reserved3: u1, + /// Capture/Compare 4 output + /// Polarity + CC4NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40000c24 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Low counter value + CNT_L: u16, + /// High counter value + CNT_H: u16, + }), base_address + 0x24); + + /// address: 0x40000c28 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x40000c2c + /// auto-reload register + pub const ARR = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Auto-reload value + ARR_L: u16, + /// High Auto-reload value + ARR_H: u16, + }), base_address + 0x2c); + + /// address: 0x40000c34 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare 1 + /// value + CCR1_L: u16, + /// High Capture/Compare 1 + /// value + CCR1_H: u16, + }), base_address + 0x34); + + /// address: 0x40000c38 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare 2 + /// value + CCR2_L: u16, + /// High Capture/Compare 2 + /// value + CCR2_H: u16, + }), base_address + 0x38); + + /// address: 0x40000c3c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare value + CCR3_L: u16, + /// High Capture/Compare value + CCR3_H: u16, + }), base_address + 0x3c); + + /// address: 0x40000c40 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare value + CCR4_L: u16, + /// High Capture/Compare value + CCR4_H: u16, + }), base_address + 0x40); + + /// address: 0x40000c48 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x40000c4c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + + /// address: 0x40000c50 + /// TIM5 option register + pub const OR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Timer Input 4 remap + IT4_RMP: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x50); + }; + + /// General purpose timers + pub const TIM9 = struct { + pub const base_address = 0x40014000; + + /// address: 0x40014000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40014004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x40014008 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x8); + + /// address: 0x4001400c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger interrupt enable + TIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0xc); + + /// address: 0x40014010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger interrupt flag + TIF: u1, + reserved3: u1, + reserved4: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x10); + + /// address: 0x40014014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40014018 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + reserved0: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output Compare 2 fast + /// enable + OC2FE: u1, + /// Output Compare 2 preload + /// enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x18); + + /// address: 0x40014018 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u3, + reserved0: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x18); + + /// address: 0x40014020 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x20); + + /// address: 0x40014024 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40014028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001402c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40014034 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40014038 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + }; + pub const TIM12 = struct { + pub const base_address = 0x40001800; + + /// address: 0x40001800 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40001804 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x40001808 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x8); + + /// address: 0x4000180c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger interrupt enable + TIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0xc); + + /// address: 0x40001810 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger interrupt flag + TIF: u1, + reserved3: u1, + reserved4: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x10); + + /// address: 0x40001814 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40001818 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + reserved0: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output Compare 2 fast + /// enable + OC2FE: u1, + /// Output Compare 2 preload + /// enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x18); + + /// address: 0x40001818 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u3, + reserved0: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x18); + + /// address: 0x40001820 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x20); + + /// address: 0x40001824 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40001828 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000182c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40001834 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40001838 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + }; + + /// General-purpose-timers + pub const TIM10 = struct { + pub const base_address = 0x40014400; + + /// address: 0x40014400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x4001440c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + + /// address: 0x40014410 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x10); + + /// address: 0x40014414 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x14); + + /// address: 0x40014418 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x18); + + /// address: 0x40014418 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + + /// address: 0x40014420 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x20); + + /// address: 0x40014424 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40014428 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001442c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40014434 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + }; + pub const TIM13 = struct { + pub const base_address = 0x40001c00; + + /// address: 0x40001c00 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40001c0c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + + /// address: 0x40001c10 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x10); + + /// address: 0x40001c14 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x14); + + /// address: 0x40001c18 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x18); + + /// address: 0x40001c18 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + + /// address: 0x40001c20 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x20); + + /// address: 0x40001c24 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40001c28 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x40001c2c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40001c34 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + }; + pub const TIM14 = struct { + pub const base_address = 0x40002000; + + /// address: 0x40002000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x4000200c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + + /// address: 0x40002010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x10); + + /// address: 0x40002014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x14); + + /// address: 0x40002018 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x18); + + /// address: 0x40002018 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + + /// address: 0x40002020 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x20); + + /// address: 0x40002024 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40002028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000202c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40002034 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + }; + + /// General-purpose-timers + pub const TIM11 = struct { + pub const base_address = 0x40014800; + + /// address: 0x40014800 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x4001480c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + + /// address: 0x40014810 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x10); + + /// address: 0x40014814 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x14); + + /// address: 0x40014818 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x18); + + /// address: 0x40014818 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + + /// address: 0x40014820 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x20); + + /// address: 0x40014824 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40014828 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001482c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40014834 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40014850 + /// option register + pub const OR = @intToPtr(*volatile Mmio(32, packed struct { + /// Input 1 remapping + /// capability + RMP: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x50); + }; + + /// Basic timers + pub const TIM6 = struct { + pub const base_address = 0x40001000; + + /// address: 0x40001000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x0); + + /// address: 0x40001004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x4000100c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Update DMA request enable + UDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0xc); + + /// address: 0x40001010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x10); + + /// address: 0x40001014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x14); + + /// address: 0x40001024 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40001028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000102c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + }; + pub const TIM7 = struct { + pub const base_address = 0x40001400; + + /// address: 0x40001400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x0); + + /// address: 0x40001404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x4000140c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Update DMA request enable + UDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0xc); + + /// address: 0x40001410 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x10); + + /// address: 0x40001414 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x14); + + /// address: 0x40001424 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40001428 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000142c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + }; + + /// Ethernet: media access control + /// (MAC) + pub const Ethernet_MAC = struct { + pub const base_address = 0x40028000; + + /// address: 0x40028000 + /// Ethernet MAC configuration + /// register + pub const MACCR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + /// RE + RE: u1, + /// TE + TE: u1, + /// DC + DC: u1, + /// BL + BL: u2, + /// APCS + APCS: u1, + reserved2: u1, + /// RD + RD: u1, + /// IPCO + IPCO: u1, + /// DM + DM: u1, + /// LM + LM: u1, + /// ROD + ROD: u1, + /// FES + FES: u1, + reserved3: u1, + /// CSD + CSD: u1, + /// IFG + IFG: u3, + reserved4: u1, + reserved5: u1, + /// JD + JD: u1, + /// WD + WD: u1, + reserved6: u1, + /// CSTF + CSTF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x0); + + /// address: 0x40028004 + /// Ethernet MAC frame filter + /// register + pub const MACFFR = @intToPtr(*volatile Mmio(32, packed struct { + /// PM + PM: u1, + /// HU + HU: u1, + /// HM + HM: u1, + /// DAIF + DAIF: u1, + /// RAM + RAM: u1, + /// BFD + BFD: u1, + /// PCF + PCF: u1, + /// SAIF + SAIF: u1, + /// SAF + SAF: u1, + /// HPF + HPF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + /// RA + RA: u1, + }), base_address + 0x4); + + /// address: 0x40028008 + /// Ethernet MAC hash table high + /// register + pub const MACHTHR = @intToPtr(*volatile Mmio(32, packed struct { + /// HTH + HTH: u32, + }), base_address + 0x8); + + /// address: 0x4002800c + /// Ethernet MAC hash table low + /// register + pub const MACHTLR = @intToPtr(*volatile Mmio(32, packed struct { + /// HTL + HTL: u32, + }), base_address + 0xc); + + /// address: 0x40028010 + /// Ethernet MAC MII address + /// register + pub const MACMIIAR = @intToPtr(*volatile Mmio(32, packed struct { + /// MB + MB: u1, + /// MW + MW: u1, + /// CR + CR: u3, + reserved0: u1, + /// MR + MR: u5, + /// PA + PA: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40028014 + /// Ethernet MAC MII data register + pub const MACMIIDR = @intToPtr(*volatile Mmio(32, packed struct { + /// TD + TD: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40028018 + /// Ethernet MAC flow control + /// register + pub const MACFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FCB + FCB: u1, + /// TFCE + TFCE: u1, + /// RFCE + RFCE: u1, + /// UPFD + UPFD: u1, + /// PLT + PLT: u2, + reserved0: u1, + /// ZQPD + ZQPD: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// PT + PT: u16, + }), base_address + 0x18); + + /// address: 0x4002801c + /// Ethernet MAC VLAN tag register + pub const MACVLANTR = @intToPtr(*volatile Mmio(32, packed struct { + /// VLANTI + VLANTI: u16, + /// VLANTC + VLANTC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x4002802c + /// Ethernet MAC PMT control and status + /// register + pub const MACPMTCSR = @intToPtr(*volatile Mmio(32, packed struct { + /// PD + PD: u1, + /// MPE + MPE: u1, + /// WFE + WFE: u1, + reserved0: u1, + reserved1: u1, + /// MPR + MPR: u1, + /// WFR + WFR: u1, + reserved2: u1, + reserved3: u1, + /// GU + GU: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + /// WFFRPR + WFFRPR: u1, + }), base_address + 0x2c); + + /// address: 0x40028034 + /// Ethernet MAC debug register + pub const MACDBGR = @intToPtr(*volatile Mmio(32, packed struct { + /// CR + CR: u1, + /// CSR + CSR: u1, + /// ROR + ROR: u1, + /// MCF + MCF: u1, + /// MCP + MCP: u1, + /// MCFHP + MCFHP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x34); + + /// address: 0x40028038 + /// Ethernet MAC interrupt status + /// register + pub const MACSR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// PMTS + PMTS: u1, + /// MMCS + MMCS: u1, + /// MMCRS + MMCRS: u1, + /// MMCTS + MMCTS: u1, + reserved3: u1, + reserved4: u1, + /// TSTS + TSTS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x38); + + /// address: 0x4002803c + /// Ethernet MAC interrupt mask + /// register + pub const MACIMR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// PMTIM + PMTIM: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// TSTIM + TSTIM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x3c); + + /// address: 0x40028040 + /// Ethernet MAC address 0 high + /// register + pub const MACA0HR = @intToPtr(*volatile Mmio(32, packed struct { + /// MAC address0 high + MACA0H: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// Always 1 + MO: u1, + }), base_address + 0x40); + + /// address: 0x40028044 + /// Ethernet MAC address 0 low + /// register + pub const MACA0LR = @intToPtr(*volatile Mmio(32, packed struct { + /// 0 + MACA0L: u32, + }), base_address + 0x44); + + /// address: 0x40028048 + /// Ethernet MAC address 1 high + /// register + pub const MACA1HR = @intToPtr(*volatile Mmio(32, packed struct { + /// MACA1H + MACA1H: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// MBC + MBC: u6, + /// SA + SA: u1, + /// AE + AE: u1, + }), base_address + 0x48); + + /// address: 0x4002804c + /// Ethernet MAC address1 low + /// register + pub const MACA1LR = @intToPtr(*volatile u32, base_address + 0x4c); + + /// address: 0x40028050 + /// Ethernet MAC address 2 high + /// register + pub const MACA2HR = @intToPtr(*volatile Mmio(32, packed struct { + /// MAC2AH + MAC2AH: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// MBC + MBC: u6, + /// SA + SA: u1, + /// AE + AE: u1, + }), base_address + 0x50); + + /// address: 0x40028054 + /// Ethernet MAC address 2 low + /// register + pub const MACA2LR = @intToPtr(*volatile Mmio(32, packed struct { + /// MACA2L + MACA2L: u31, + padding0: u1, + }), base_address + 0x54); + + /// address: 0x40028058 + /// Ethernet MAC address 3 high + /// register + pub const MACA3HR = @intToPtr(*volatile Mmio(32, packed struct { + /// MACA3H + MACA3H: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// MBC + MBC: u6, + /// SA + SA: u1, + /// AE + AE: u1, + }), base_address + 0x58); + + /// address: 0x4002805c + /// Ethernet MAC address 3 low + /// register + pub const MACA3LR = @intToPtr(*volatile Mmio(32, packed struct { + /// MBCA3L + MBCA3L: u32, + }), base_address + 0x5c); + }; + + /// Ethernet: MAC management counters + pub const Ethernet_MMC = struct { + pub const base_address = 0x40028100; + + /// address: 0x40028100 + /// Ethernet MMC control register + pub const MMCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// CR + CR: u1, + /// CSR + CSR: u1, + /// ROR + ROR: u1, + /// MCF + MCF: u1, + /// MCP + MCP: u1, + /// MCFHP + MCFHP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x0); + + /// address: 0x40028104 + /// Ethernet MMC receive interrupt + /// register + pub const MMCRIR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// RFCES + RFCES: u1, + /// RFAES + RFAES: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// RGUFS + RGUFS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x4); + + /// address: 0x40028108 + /// Ethernet MMC transmit interrupt + /// register + pub const MMCTIR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// TGFSCS + TGFSCS: u1, + /// TGFMSCS + TGFMSCS: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + /// TGFS + TGFS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x8); + + /// address: 0x4002810c + /// Ethernet MMC receive interrupt mask + /// register + pub const MMCRIMR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// RFCEM + RFCEM: u1, + /// RFAEM + RFAEM: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// RGUFM + RGUFM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0xc); + + /// address: 0x40028110 + /// Ethernet MMC transmit interrupt mask + /// register + pub const MMCTIMR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// TGFSCM + TGFSCM: u1, + /// TGFMSCM + TGFMSCM: u1, + /// TGFM + TGFM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x10); + + /// address: 0x4002814c + /// Ethernet MMC transmitted good frames after a + /// single collision counter + pub const MMCTGFSCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// TGFSCC + TGFSCC: u32, + }), base_address + 0x4c); + + /// address: 0x40028150 + /// Ethernet MMC transmitted good frames after + /// more than a single collision + pub const MMCTGFMSCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// TGFMSCC + TGFMSCC: u32, + }), base_address + 0x50); + + /// address: 0x40028168 + /// Ethernet MMC transmitted good frames counter + /// register + pub const MMCTGFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// HTL + TGFC: u32, + }), base_address + 0x68); + + /// address: 0x40028194 + /// Ethernet MMC received frames with CRC error + /// counter register + pub const MMCRFCECR = @intToPtr(*volatile Mmio(32, packed struct { + /// RFCFC + RFCFC: u32, + }), base_address + 0x94); + + /// address: 0x40028198 + /// Ethernet MMC received frames with alignment + /// error counter register + pub const MMCRFAECR = @intToPtr(*volatile Mmio(32, packed struct { + /// RFAEC + RFAEC: u32, + }), base_address + 0x98); + + /// address: 0x400281c4 + /// MMC received good unicast frames counter + /// register + pub const MMCRGUFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// RGUFC + RGUFC: u32, + }), base_address + 0xc4); + }; + + /// Ethernet: Precision time protocol + pub const Ethernet_PTP = struct { + pub const base_address = 0x40028700; + + /// address: 0x40028700 + /// Ethernet PTP time stamp control + /// register + pub const PTPTSCR = @intToPtr(*volatile Mmio(32, packed struct { + /// TSE + TSE: u1, + /// TSFCU + TSFCU: u1, + /// TSSTI + TSSTI: u1, + /// TSSTU + TSSTU: u1, + /// TSITE + TSITE: u1, + /// TTSARU + TTSARU: u1, + reserved0: u1, + reserved1: u1, + /// TSSARFE + TSSARFE: u1, + /// TSSSR + TSSSR: u1, + /// TSPTPPSV2E + TSPTPPSV2E: u1, + /// TSSPTPOEFE + TSSPTPOEFE: u1, + /// TSSIPV6FE + TSSIPV6FE: u1, + /// TSSIPV4FE + TSSIPV4FE: u1, + /// TSSEME + TSSEME: u1, + /// TSSMRME + TSSMRME: u1, + /// TSCNT + TSCNT: u2, + /// TSPFFMAE + TSPFFMAE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x0); + + /// address: 0x40028704 + /// Ethernet PTP subsecond increment + /// register + pub const PTPSSIR = @intToPtr(*volatile Mmio(32, packed struct { + /// STSSI + STSSI: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40028708 + /// Ethernet PTP time stamp high + /// register + pub const PTPTSHR = @intToPtr(*volatile Mmio(32, packed struct { + /// STS + STS: u32, + }), base_address + 0x8); + + /// address: 0x4002870c + /// Ethernet PTP time stamp low + /// register + pub const PTPTSLR = @intToPtr(*volatile Mmio(32, packed struct { + /// STSS + STSS: u31, + /// STPNS + STPNS: u1, + }), base_address + 0xc); + + /// address: 0x40028710 + /// Ethernet PTP time stamp high update + /// register + pub const PTPTSHUR = @intToPtr(*volatile Mmio(32, packed struct { + /// TSUS + TSUS: u32, + }), base_address + 0x10); + + /// address: 0x40028714 + /// Ethernet PTP time stamp low update + /// register + pub const PTPTSLUR = @intToPtr(*volatile Mmio(32, packed struct { + /// TSUSS + TSUSS: u31, + /// TSUSS + TSUPNS: u1, + }), base_address + 0x14); + + /// address: 0x40028718 + /// Ethernet PTP time stamp addend + /// register + pub const PTPTSAR = @intToPtr(*volatile Mmio(32, packed struct { + /// TSA + TSA: u32, + }), base_address + 0x18); + + /// address: 0x4002871c + /// Ethernet PTP target time high + /// register + pub const PTPTTHR = @intToPtr(*volatile Mmio(32, packed struct { + /// 0 + TTSH: u32, + }), base_address + 0x1c); + + /// address: 0x40028720 + /// Ethernet PTP target time low + /// register + pub const PTPTTLR = @intToPtr(*volatile Mmio(32, packed struct { + /// TTSL + TTSL: u32, + }), base_address + 0x20); + + /// address: 0x40028728 + /// Ethernet PTP time stamp status + /// register + pub const PTPTSSR = @intToPtr(*volatile Mmio(32, packed struct { + /// TSSO + TSSO: u1, + /// TSTTR + TSTTR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x28); + + /// address: 0x4002872c + /// Ethernet PTP PPS control + /// register + pub const PTPPPSCR = @intToPtr(*volatile Mmio(32, packed struct { + /// TSSO + TSSO: u1, + /// TSTTR + TSTTR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x2c); + }; + + /// Ethernet: DMA controller operation + pub const Ethernet_DMA = struct { + pub const base_address = 0x40029000; + + /// address: 0x40029000 + /// Ethernet DMA bus mode register + pub const DMABMR = @intToPtr(*volatile Mmio(32, packed struct { + /// SR + SR: u1, + /// DA + DA: u1, + /// DSL + DSL: u5, + /// EDFE + EDFE: u1, + /// PBL + PBL: u6, + /// RTPR + RTPR: u2, + /// FB + FB: u1, + /// RDP + RDP: u6, + /// USP + USP: u1, + /// FPM + FPM: u1, + /// AAB + AAB: u1, + /// MB + MB: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x0); + + /// address: 0x40029004 + /// Ethernet DMA transmit poll demand + /// register + pub const DMATPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// TPD + TPD: u32, + }), base_address + 0x4); + + /// address: 0x40029008 + /// EHERNET DMA receive poll demand + /// register + pub const DMARPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// RPD + RPD: u32, + }), base_address + 0x8); + + /// address: 0x4002900c + /// Ethernet DMA receive descriptor list address + /// register + pub const DMARDLAR = @intToPtr(*volatile Mmio(32, packed struct { + /// SRL + SRL: u32, + }), base_address + 0xc); + + /// address: 0x40029010 + /// Ethernet DMA transmit descriptor list + /// address register + pub const DMATDLAR = @intToPtr(*volatile Mmio(32, packed struct { + /// STL + STL: u32, + }), base_address + 0x10); + + /// address: 0x40029014 + /// Ethernet DMA status register + pub const DMASR = @intToPtr(*volatile Mmio(32, packed struct { + /// TS + TS: u1, + /// TPSS + TPSS: u1, + /// TBUS + TBUS: u1, + /// TJTS + TJTS: u1, + /// ROS + ROS: u1, + /// TUS + TUS: u1, + /// RS + RS: u1, + /// RBUS + RBUS: u1, + /// RPSS + RPSS: u1, + /// PWTS + PWTS: u1, + /// ETS + ETS: u1, + reserved0: u1, + reserved1: u1, + /// FBES + FBES: u1, + /// ERS + ERS: u1, + /// AIS + AIS: u1, + /// NIS + NIS: u1, + /// RPS + RPS: u3, + /// TPS + TPS: u3, + /// EBS + EBS: u3, + reserved2: u1, + /// MMCS + MMCS: u1, + /// PMTS + PMTS: u1, + /// TSTS + TSTS: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x14); + + /// address: 0x40029018 + /// Ethernet DMA operation mode + /// register + pub const DMAOMR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// SR + SR: u1, + /// OSF + OSF: u1, + /// RTC + RTC: u2, + reserved1: u1, + /// FUGF + FUGF: u1, + /// FEF + FEF: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// ST + ST: u1, + /// TTC + TTC: u3, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// FTF + FTF: u1, + /// TSF + TSF: u1, + reserved10: u1, + reserved11: u1, + /// DFRF + DFRF: u1, + /// RSF + RSF: u1, + /// DTCEFD + DTCEFD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x18); + + /// address: 0x4002901c + /// Ethernet DMA interrupt enable + /// register + pub const DMAIER = @intToPtr(*volatile Mmio(32, packed struct { + /// TIE + TIE: u1, + /// TPSIE + TPSIE: u1, + /// TBUIE + TBUIE: u1, + /// TJTIE + TJTIE: u1, + /// ROIE + ROIE: u1, + /// TUIE + TUIE: u1, + /// RIE + RIE: u1, + /// RBUIE + RBUIE: u1, + /// RPSIE + RPSIE: u1, + /// RWTIE + RWTIE: u1, + /// ETIE + ETIE: u1, + reserved0: u1, + reserved1: u1, + /// FBEIE + FBEIE: u1, + /// ERIE + ERIE: u1, + /// AISE + AISE: u1, + /// NISE + NISE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40029020 + /// Ethernet DMA missed frame and buffer + /// overflow counter register + pub const DMAMFBOCR = @intToPtr(*volatile Mmio(32, packed struct { + /// MFC + MFC: u16, + /// OMFC + OMFC: u1, + /// MFA + MFA: u11, + /// OFOC + OFOC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x20); + + /// address: 0x40029024 + /// Ethernet DMA receive status watchdog timer + /// register + pub const DMARSWTR = @intToPtr(*volatile Mmio(32, packed struct { + /// RSWTC + RSWTC: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x24); + + /// address: 0x40029048 + /// Ethernet DMA current host transmit + /// descriptor register + pub const DMACHTDR = @intToPtr(*volatile Mmio(32, packed struct { + /// HTDAP + HTDAP: u32, + }), base_address + 0x48); + + /// address: 0x4002904c + /// Ethernet DMA current host receive descriptor + /// register + pub const DMACHRDR = @intToPtr(*volatile Mmio(32, packed struct { + /// HRDAP + HRDAP: u32, + }), base_address + 0x4c); + + /// address: 0x40029050 + /// Ethernet DMA current host transmit buffer + /// address register + pub const DMACHTBAR = @intToPtr(*volatile Mmio(32, packed struct { + /// HTBAP + HTBAP: u32, + }), base_address + 0x50); + + /// address: 0x40029054 + /// Ethernet DMA current host receive buffer + /// address register + pub const DMACHRBAR = @intToPtr(*volatile Mmio(32, packed struct { + /// HRBAP + HRBAP: u32, + }), base_address + 0x54); + }; + + /// Cryptographic processor + pub const CRC = struct { + pub const base_address = 0x40023000; + + /// address: 0x40023000 + /// Data register + pub const DR = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40023004 + /// Independent Data register + pub const IDR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); + + /// address: 0x40023008 + /// Control register + pub const CR = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x8); + }; + + /// USB on the go full speed + pub const OTG_FS_GLOBAL = struct { + pub const base_address = 0x50000000; + + /// address: 0x50000000 + /// OTG_FS control and status register + /// (OTG_FS_GOTGCTL) + pub const FS_GOTGCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Session request success + SRQSCS: u1, + /// Session request + SRQ: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Host negotiation success + HNGSCS: u1, + /// HNP request + HNPRQ: u1, + /// Host set HNP enable + HSHNPEN: u1, + /// Device HNP enabled + DHNPEN: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Connector ID status + CIDSTS: u1, + /// Long/short debounce time + DBCT: u1, + /// A-session valid + ASVLD: u1, + /// B-session valid + BSVLD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x0); + + /// address: 0x50000004 + /// OTG_FS interrupt register + /// (OTG_FS_GOTGINT) + pub const FS_GOTGINT = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + /// Session end detected + SEDET: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Session request success status + /// change + SRSSCHG: u1, + /// Host negotiation success status + /// change + HNSSCHG: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Host negotiation detected + HNGDET: u1, + /// A-device timeout change + ADTOCHG: u1, + /// Debounce done + DBCDNE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x4); + + /// address: 0x50000008 + /// OTG_FS AHB configuration register + /// (OTG_FS_GAHBCFG) + pub const FS_GAHBCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Global interrupt mask + GINT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// TxFIFO empty level + TXFELVL: u1, + /// Periodic TxFIFO empty + /// level + PTXFELVL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x5000000c + /// OTG_FS USB configuration register + /// (OTG_FS_GUSBCFG) + pub const FS_GUSBCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// FS timeout calibration + TOCAL: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Full Speed serial transceiver + /// select + PHYSEL: u1, + reserved3: u1, + /// SRP-capable + SRPCAP: u1, + /// HNP-capable + HNPCAP: u1, + /// USB turnaround time + TRDT: u4, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + /// Force host mode + FHMOD: u1, + /// Force device mode + FDMOD: u1, + /// Corrupt Tx packet + CTXPKT: u1, + }), base_address + 0xc); + + /// address: 0x50000010 + /// OTG_FS reset register + /// (OTG_FS_GRSTCTL) + pub const FS_GRSTCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Core soft reset + CSRST: u1, + /// HCLK soft reset + HSRST: u1, + /// Host frame counter reset + FCRST: u1, + reserved0: u1, + /// RxFIFO flush + RXFFLSH: u1, + /// TxFIFO flush + TXFFLSH: u1, + /// TxFIFO number + TXFNUM: u5, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + /// AHB master idle + AHBIDL: u1, + }), base_address + 0x10); + + /// address: 0x50000014 + /// OTG_FS core interrupt register + /// (OTG_FS_GINTSTS) + pub const FS_GINTSTS = @intToPtr(*volatile Mmio(32, packed struct { + /// Current mode of operation + CMOD: u1, + /// Mode mismatch interrupt + MMIS: u1, + /// OTG interrupt + OTGINT: u1, + /// Start of frame + SOF: u1, + /// RxFIFO non-empty + RXFLVL: u1, + /// Non-periodic TxFIFO empty + NPTXFE: u1, + /// Global IN non-periodic NAK + /// effective + GINAKEFF: u1, + /// Global OUT NAK effective + GOUTNAKEFF: u1, + reserved0: u1, + reserved1: u1, + /// Early suspend + ESUSP: u1, + /// USB suspend + USBSUSP: u1, + /// USB reset + USBRST: u1, + /// Enumeration done + ENUMDNE: u1, + /// Isochronous OUT packet dropped + /// interrupt + ISOODRP: u1, + /// End of periodic frame + /// interrupt + EOPF: u1, + reserved2: u1, + reserved3: u1, + /// IN endpoint interrupt + IEPINT: u1, + /// OUT endpoint interrupt + OEPINT: u1, + /// Incomplete isochronous IN + /// transfer + IISOIXFR: u1, + /// Incomplete periodic transfer(Host + /// mode)/Incomplete isochronous OUT transfer(Device + /// mode) + IPXFR_INCOMPISOOUT: u1, + reserved4: u1, + reserved5: u1, + /// Host port interrupt + HPRTINT: u1, + /// Host channels interrupt + HCINT: u1, + /// Periodic TxFIFO empty + PTXFE: u1, + reserved6: u1, + /// Connector ID status change + CIDSCHG: u1, + /// Disconnect detected + /// interrupt + DISCINT: u1, + /// Session request/new session detected + /// interrupt + SRQINT: u1, + /// Resume/remote wakeup detected + /// interrupt + WKUPINT: u1, + }), base_address + 0x14); + + /// address: 0x50000018 + /// OTG_FS interrupt mask register + /// (OTG_FS_GINTMSK) + pub const FS_GINTMSK = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Mode mismatch interrupt + /// mask + MMISM: u1, + /// OTG interrupt mask + OTGINT: u1, + /// Start of frame mask + SOFM: u1, + /// Receive FIFO non-empty + /// mask + RXFLVLM: u1, + /// Non-periodic TxFIFO empty + /// mask + NPTXFEM: u1, + /// Global non-periodic IN NAK effective + /// mask + GINAKEFFM: u1, + /// Global OUT NAK effective + /// mask + GONAKEFFM: u1, + reserved1: u1, + reserved2: u1, + /// Early suspend mask + ESUSPM: u1, + /// USB suspend mask + USBSUSPM: u1, + /// USB reset mask + USBRST: u1, + /// Enumeration done mask + ENUMDNEM: u1, + /// Isochronous OUT packet dropped interrupt + /// mask + ISOODRPM: u1, + /// End of periodic frame interrupt + /// mask + EOPFM: u1, + reserved3: u1, + /// Endpoint mismatch interrupt + /// mask + EPMISM: u1, + /// IN endpoints interrupt + /// mask + IEPINT: u1, + /// OUT endpoints interrupt + /// mask + OEPINT: u1, + /// Incomplete isochronous IN transfer + /// mask + IISOIXFRM: u1, + /// Incomplete periodic transfer mask(Host + /// mode)/Incomplete isochronous OUT transfer mask(Device + /// mode) + IPXFRM_IISOOXFRM: u1, + reserved4: u1, + reserved5: u1, + /// Host port interrupt mask + PRTIM: u1, + /// Host channels interrupt + /// mask + HCIM: u1, + /// Periodic TxFIFO empty mask + PTXFEM: u1, + reserved6: u1, + /// Connector ID status change + /// mask + CIDSCHGM: u1, + /// Disconnect detected interrupt + /// mask + DISCINT: u1, + /// Session request/new session detected + /// interrupt mask + SRQIM: u1, + /// Resume/remote wakeup detected interrupt + /// mask + WUIM: u1, + }), base_address + 0x18); + + /// address: 0x5000001c + /// OTG_FS Receive status debug read(Device + /// mode) + pub const FS_GRXSTSR_Device = @intToPtr(*volatile Mmio(32, packed struct { + /// Endpoint number + EPNUM: u4, + /// Byte count + BCNT: u11, + /// Data PID + DPID: u2, + /// Packet status + PKTSTS: u4, + /// Frame number + FRMNUM: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x1c); + + /// address: 0x5000001c + /// OTG_FS Receive status debug + /// read(Hostmode) + pub const FS_GRXSTSR_Host = @intToPtr(*volatile Mmio(32, packed struct { + /// Endpoint number + EPNUM: u4, + /// Byte count + BCNT: u11, + /// Data PID + DPID: u2, + /// Packet status + PKTSTS: u4, + /// Frame number + FRMNUM: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x1c); + + /// address: 0x50000024 + /// OTG_FS Receive FIFO size register + /// (OTG_FS_GRXFSIZ) + pub const FS_GRXFSIZ = @intToPtr(*volatile Mmio(32, packed struct { + /// RxFIFO depth + RXFD: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x24); + + /// address: 0x50000028 + /// OTG_FS non-periodic transmit FIFO size + /// register (Device mode) + pub const FS_GNPTXFSIZ_Device = @intToPtr(*volatile Mmio(32, packed struct { + /// Endpoint 0 transmit RAM start + /// address + TX0FSA: u16, + /// Endpoint 0 TxFIFO depth + TX0FD: u16, + }), base_address + 0x28); + + /// address: 0x50000028 + /// OTG_FS non-periodic transmit FIFO size + /// register (Host mode) + pub const FS_GNPTXFSIZ_Host = @intToPtr(*volatile Mmio(32, packed struct { + /// Non-periodic transmit RAM start + /// address + NPTXFSA: u16, + /// Non-periodic TxFIFO depth + NPTXFD: u16, + }), base_address + 0x28); + + /// address: 0x5000002c + /// OTG_FS non-periodic transmit FIFO/queue + /// status register (OTG_FS_GNPTXSTS) + pub const FS_GNPTXSTS = @intToPtr(*volatile Mmio(32, packed struct { + /// Non-periodic TxFIFO space + /// available + NPTXFSAV: u16, + /// Non-periodic transmit request queue + /// space available + NPTQXSAV: u8, + /// Top of the non-periodic transmit request + /// queue + NPTXQTOP: u7, + padding0: u1, + }), base_address + 0x2c); + + /// address: 0x50000038 + /// OTG_FS general core configuration register + /// (OTG_FS_GCCFG) + pub const FS_GCCFG = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Power down + PWRDWN: u1, + reserved16: u1, + /// Enable the VBUS sensing + /// device + VBUSASEN: u1, + /// Enable the VBUS sensing + /// device + VBUSBSEN: u1, + /// SOF output enable + SOFOUTEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x38); + + /// address: 0x5000003c + /// core ID register + pub const FS_CID = @intToPtr(*volatile Mmio(32, packed struct { + /// Product ID field + PRODUCT_ID: u32, + }), base_address + 0x3c); + + /// address: 0x50000100 + /// OTG_FS Host periodic transmit FIFO size + /// register (OTG_FS_HPTXFSIZ) + pub const FS_HPTXFSIZ = @intToPtr(*volatile Mmio(32, packed struct { + /// Host periodic TxFIFO start + /// address + PTXSA: u16, + /// Host periodic TxFIFO depth + PTXFSIZ: u16, + }), base_address + 0x100); + + /// address: 0x50000104 + /// OTG_FS device IN endpoint transmit FIFO size + /// register (OTG_FS_DIEPTXF2) + pub const FS_DIEPTXF1 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFO2 transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x104); + + /// address: 0x50000108 + /// OTG_FS device IN endpoint transmit FIFO size + /// register (OTG_FS_DIEPTXF3) + pub const FS_DIEPTXF2 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFO3 transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x108); + + /// address: 0x5000010c + /// OTG_FS device IN endpoint transmit FIFO size + /// register (OTG_FS_DIEPTXF4) + pub const FS_DIEPTXF3 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFO4 transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x10c); + }; + + /// USB on the go full speed + pub const OTG_FS_HOST = struct { + pub const base_address = 0x50000400; + + /// address: 0x50000400 + /// OTG_FS host configuration register + /// (OTG_FS_HCFG) + pub const FS_HCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// FS/LS PHY clock select + FSLSPCS: u2, + /// FS- and LS-only support + FSLSS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x0); + + /// address: 0x50000404 + /// OTG_FS Host frame interval + /// register + pub const HFIR = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame interval + FRIVL: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x50000408 + /// OTG_FS host frame number/frame time + /// remaining register (OTG_FS_HFNUM) + pub const FS_HFNUM = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame number + FRNUM: u16, + /// Frame time remaining + FTREM: u16, + }), base_address + 0x8); + + /// address: 0x50000410 + /// OTG_FS_Host periodic transmit FIFO/queue + /// status register (OTG_FS_HPTXSTS) + pub const FS_HPTXSTS = @intToPtr(*volatile Mmio(32, packed struct { + /// Periodic transmit data FIFO space + /// available + PTXFSAVL: u16, + /// Periodic transmit request queue space + /// available + PTXQSAV: u8, + /// Top of the periodic transmit request + /// queue + PTXQTOP: u8, + }), base_address + 0x10); + + /// address: 0x50000414 + /// OTG_FS Host all channels interrupt + /// register + pub const HAINT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x14); + + /// address: 0x50000418 + /// OTG_FS host all channels interrupt mask + /// register + pub const HAINTMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel interrupt mask + HAINTM: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x50000440 + /// OTG_FS host port control and status register + /// (OTG_FS_HPRT) + pub const FS_HPRT = @intToPtr(*volatile Mmio(32, packed struct { + /// Port connect status + PCSTS: u1, + /// Port connect detected + PCDET: u1, + /// Port enable + PENA: u1, + /// Port enable/disable change + PENCHNG: u1, + /// Port overcurrent active + POCA: u1, + /// Port overcurrent change + POCCHNG: u1, + /// Port resume + PRES: u1, + /// Port suspend + PSUSP: u1, + /// Port reset + PRST: u1, + reserved0: u1, + /// Port line status + PLSTS: u2, + /// Port power + PPWR: u1, + /// Port test control + PTCTL: u4, + /// Port speed + PSPD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x40); + + /// address: 0x50000500 + /// OTG_FS host channel-0 characteristics + /// register (OTG_FS_HCCHAR0) + pub const FS_HCCHAR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x100); + + /// address: 0x50000520 + /// OTG_FS host channel-1 characteristics + /// register (OTG_FS_HCCHAR1) + pub const FS_HCCHAR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x120); + + /// address: 0x50000540 + /// OTG_FS host channel-2 characteristics + /// register (OTG_FS_HCCHAR2) + pub const FS_HCCHAR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x140); + + /// address: 0x50000560 + /// OTG_FS host channel-3 characteristics + /// register (OTG_FS_HCCHAR3) + pub const FS_HCCHAR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x160); + + /// address: 0x50000580 + /// OTG_FS host channel-4 characteristics + /// register (OTG_FS_HCCHAR4) + pub const FS_HCCHAR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x180); + + /// address: 0x500005a0 + /// OTG_FS host channel-5 characteristics + /// register (OTG_FS_HCCHAR5) + pub const FS_HCCHAR5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x1a0); + + /// address: 0x500005c0 + /// OTG_FS host channel-6 characteristics + /// register (OTG_FS_HCCHAR6) + pub const FS_HCCHAR6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x1c0); + + /// address: 0x500005e0 + /// OTG_FS host channel-7 characteristics + /// register (OTG_FS_HCCHAR7) + pub const FS_HCCHAR7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x1e0); + + /// address: 0x50000508 + /// OTG_FS host channel-0 interrupt register + /// (OTG_FS_HCINT0) + pub const FS_HCINT0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x108); + + /// address: 0x50000528 + /// OTG_FS host channel-1 interrupt register + /// (OTG_FS_HCINT1) + pub const FS_HCINT1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x128); + + /// address: 0x50000548 + /// OTG_FS host channel-2 interrupt register + /// (OTG_FS_HCINT2) + pub const FS_HCINT2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x148); + + /// address: 0x50000568 + /// OTG_FS host channel-3 interrupt register + /// (OTG_FS_HCINT3) + pub const FS_HCINT3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x168); + + /// address: 0x50000588 + /// OTG_FS host channel-4 interrupt register + /// (OTG_FS_HCINT4) + pub const FS_HCINT4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x188); + + /// address: 0x500005a8 + /// OTG_FS host channel-5 interrupt register + /// (OTG_FS_HCINT5) + pub const FS_HCINT5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1a8); + + /// address: 0x500005c8 + /// OTG_FS host channel-6 interrupt register + /// (OTG_FS_HCINT6) + pub const FS_HCINT6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1c8); + + /// address: 0x500005e8 + /// OTG_FS host channel-7 interrupt register + /// (OTG_FS_HCINT7) + pub const FS_HCINT7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1e8); + + /// address: 0x5000050c + /// OTG_FS host channel-0 mask register + /// (OTG_FS_HCINTMSK0) + pub const FS_HCINTMSK0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved0: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x10c); + + /// address: 0x5000052c + /// OTG_FS host channel-1 mask register + /// (OTG_FS_HCINTMSK1) + pub const FS_HCINTMSK1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved0: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x12c); + + /// address: 0x5000054c + /// OTG_FS host channel-2 mask register + /// (OTG_FS_HCINTMSK2) + pub const FS_HCINTMSK2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved0: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x14c); + + /// address: 0x5000056c + /// OTG_FS host channel-3 mask register + /// (OTG_FS_HCINTMSK3) + pub const FS_HCINTMSK3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved0: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x16c); + + /// address: 0x5000058c + /// OTG_FS host channel-4 mask register + /// (OTG_FS_HCINTMSK4) + pub const FS_HCINTMSK4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved0: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x18c); + + /// address: 0x500005ac + /// OTG_FS host channel-5 mask register + /// (OTG_FS_HCINTMSK5) + pub const FS_HCINTMSK5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved0: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1ac); + + /// address: 0x500005cc + /// OTG_FS host channel-6 mask register + /// (OTG_FS_HCINTMSK6) + pub const FS_HCINTMSK6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved0: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1cc); + + /// address: 0x500005ec + /// OTG_FS host channel-7 mask register + /// (OTG_FS_HCINTMSK7) + pub const FS_HCINTMSK7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved0: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1ec); + + /// address: 0x50000510 + /// OTG_FS host channel-0 transfer size + /// register + pub const FS_HCTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x110); + + /// address: 0x50000530 + /// OTG_FS host channel-1 transfer size + /// register + pub const FS_HCTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x130); + + /// address: 0x50000550 + /// OTG_FS host channel-2 transfer size + /// register + pub const FS_HCTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x150); + + /// address: 0x50000570 + /// OTG_FS host channel-3 transfer size + /// register + pub const FS_HCTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x170); + + /// address: 0x50000590 + /// OTG_FS host channel-x transfer size + /// register + pub const FS_HCTSIZ4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x190); + + /// address: 0x500005b0 + /// OTG_FS host channel-5 transfer size + /// register + pub const FS_HCTSIZ5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x1b0); + + /// address: 0x500005d0 + /// OTG_FS host channel-6 transfer size + /// register + pub const FS_HCTSIZ6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x1d0); + + /// address: 0x500005f0 + /// OTG_FS host channel-7 transfer size + /// register + pub const FS_HCTSIZ7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x1f0); + }; + + /// USB on the go full speed + pub const OTG_FS_DEVICE = struct { + pub const base_address = 0x50000800; + + /// address: 0x50000800 + /// OTG_FS device configuration register + /// (OTG_FS_DCFG) + pub const FS_DCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Device speed + DSPD: u2, + /// Non-zero-length status OUT + /// handshake + NZLSOHSK: u1, + reserved0: u1, + /// Device address + DAD: u7, + /// Periodic frame interval + PFIVL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x0); + + /// address: 0x50000804 + /// OTG_FS device control register + /// (OTG_FS_DCTL) + pub const FS_DCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Remote wakeup signaling + RWUSIG: u1, + /// Soft disconnect + SDIS: u1, + /// Global IN NAK status + GINSTS: u1, + /// Global OUT NAK status + GONSTS: u1, + /// Test control + TCTL: u3, + /// Set global IN NAK + SGINAK: u1, + /// Clear global IN NAK + CGINAK: u1, + /// Set global OUT NAK + SGONAK: u1, + /// Clear global OUT NAK + CGONAK: u1, + /// Power-on programming done + POPRGDNE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x4); + + /// address: 0x50000808 + /// OTG_FS device status register + /// (OTG_FS_DSTS) + pub const FS_DSTS = @intToPtr(*volatile Mmio(32, packed struct { + /// Suspend status + SUSPSTS: u1, + /// Enumerated speed + ENUMSPD: u2, + /// Erratic error + EERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Frame number of the received + /// SOF + FNSOF: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x8); + + /// address: 0x50000810 + /// OTG_FS device IN endpoint common interrupt + /// mask register (OTG_FS_DIEPMSK) + pub const FS_DIEPMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed interrupt + /// mask + XFRCM: u1, + /// Endpoint disabled interrupt + /// mask + EPDM: u1, + reserved0: u1, + /// Timeout condition mask (Non-isochronous + /// endpoints) + TOM: u1, + /// IN token received when TxFIFO empty + /// mask + ITTXFEMSK: u1, + /// IN token received with EP mismatch + /// mask + INEPNMM: u1, + /// IN endpoint NAK effective + /// mask + INEPNEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x10); + + /// address: 0x50000814 + /// OTG_FS device OUT endpoint common interrupt + /// mask register (OTG_FS_DOEPMSK) + pub const FS_DOEPMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed interrupt + /// mask + XFRCM: u1, + /// Endpoint disabled interrupt + /// mask + EPDM: u1, + reserved0: u1, + /// SETUP phase done mask + STUPM: u1, + /// OUT token received when endpoint + /// disabled mask + OTEPDM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x14); + + /// address: 0x50000818 + /// OTG_FS device all endpoints interrupt + /// register (OTG_FS_DAINT) + pub const FS_DAINT = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint interrupt bits + IEPINT: u16, + /// OUT endpoint interrupt + /// bits + OEPINT: u16, + }), base_address + 0x18); + + /// address: 0x5000081c + /// OTG_FS all endpoints interrupt mask register + /// (OTG_FS_DAINTMSK) + pub const FS_DAINTMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// IN EP interrupt mask bits + IEPM: u16, + /// OUT endpoint interrupt + /// bits + OEPINT: u16, + }), base_address + 0x1c); + + /// address: 0x50000828 + /// OTG_FS device VBUS discharge time + /// register + pub const DVBUSDIS = @intToPtr(*volatile Mmio(32, packed struct { + /// Device VBUS discharge time + VBUSDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + + /// address: 0x5000082c + /// OTG_FS device VBUS pulsing time + /// register + pub const DVBUSPULSE = @intToPtr(*volatile Mmio(32, packed struct { + /// Device VBUS pulsing time + DVBUSP: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x2c); + + /// address: 0x50000834 + /// OTG_FS device IN endpoint FIFO empty + /// interrupt mask register + pub const DIEPEMPMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// IN EP Tx FIFO empty interrupt mask + /// bits + INEPTXFEM: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x34); + + /// address: 0x50000900 + /// OTG_FS device control IN endpoint 0 control + /// register (OTG_FS_DIEPCTL0) + pub const FS_DIEPCTL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// USB active endpoint + USBAEP: u1, + reserved13: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved14: u1, + /// STALL handshake + STALL: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + reserved15: u1, + reserved16: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x100); + + /// address: 0x50000920 + /// OTG device endpoint-1 control + /// register + pub const DIEPCTL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// MPSIZ + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + reserved4: u1, + /// Stall + Stall: u1, + /// TXFNUM + TXFNUM: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM/SD1PID + SODDFRM_SD1PID: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), base_address + 0x120); + + /// address: 0x50000940 + /// OTG device endpoint-2 control + /// register + pub const DIEPCTL2 = @intToPtr(*volatile Mmio(32, packed struct { + /// MPSIZ + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + reserved4: u1, + /// Stall + Stall: u1, + /// TXFNUM + TXFNUM: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), base_address + 0x140); + + /// address: 0x50000960 + /// OTG device endpoint-3 control + /// register + pub const DIEPCTL3 = @intToPtr(*volatile Mmio(32, packed struct { + /// MPSIZ + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + reserved4: u1, + /// Stall + Stall: u1, + /// TXFNUM + TXFNUM: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), base_address + 0x160); + + /// address: 0x50000b00 + /// device endpoint-0 control + /// register + pub const DOEPCTL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// MPSIZ + MPSIZ: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// USBAEP + USBAEP: u1, + reserved13: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + /// SNPM + SNPM: u1, + /// Stall + Stall: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + reserved18: u1, + reserved19: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), base_address + 0x300); + + /// address: 0x50000b20 + /// device endpoint-1 control + /// register + pub const DOEPCTL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// MPSIZ + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + /// SNPM + SNPM: u1, + /// Stall + Stall: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), base_address + 0x320); + + /// address: 0x50000b40 + /// device endpoint-2 control + /// register + pub const DOEPCTL2 = @intToPtr(*volatile Mmio(32, packed struct { + /// MPSIZ + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + /// SNPM + SNPM: u1, + /// Stall + Stall: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), base_address + 0x340); + + /// address: 0x50000b60 + /// device endpoint-3 control + /// register + pub const DOEPCTL3 = @intToPtr(*volatile Mmio(32, packed struct { + /// MPSIZ + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + /// SNPM + SNPM: u1, + /// Stall + Stall: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), base_address + 0x360); + + /// address: 0x50000908 + /// device endpoint-x interrupt + /// register + pub const DIEPINT0 = @intToPtr(*volatile Mmio(32, packed struct { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved0: u1, + /// TOC + TOC: u1, + /// ITTXFE + ITTXFE: u1, + reserved1: u1, + /// INEPNE + INEPNE: u1, + /// TXFE + TXFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x108); + + /// address: 0x50000928 + /// device endpoint-1 interrupt + /// register + pub const DIEPINT1 = @intToPtr(*volatile Mmio(32, packed struct { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved0: u1, + /// TOC + TOC: u1, + /// ITTXFE + ITTXFE: u1, + reserved1: u1, + /// INEPNE + INEPNE: u1, + /// TXFE + TXFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x128); + + /// address: 0x50000948 + /// device endpoint-2 interrupt + /// register + pub const DIEPINT2 = @intToPtr(*volatile Mmio(32, packed struct { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved0: u1, + /// TOC + TOC: u1, + /// ITTXFE + ITTXFE: u1, + reserved1: u1, + /// INEPNE + INEPNE: u1, + /// TXFE + TXFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x148); + + /// address: 0x50000968 + /// device endpoint-3 interrupt + /// register + pub const DIEPINT3 = @intToPtr(*volatile Mmio(32, packed struct { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved0: u1, + /// TOC + TOC: u1, + /// ITTXFE + ITTXFE: u1, + reserved1: u1, + /// INEPNE + INEPNE: u1, + /// TXFE + TXFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x168); + + /// address: 0x50000b08 + /// device endpoint-0 interrupt + /// register + pub const DOEPINT0 = @intToPtr(*volatile Mmio(32, packed struct { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved0: u1, + /// STUP + STUP: u1, + /// OTEPDIS + OTEPDIS: u1, + reserved1: u1, + /// B2BSTUP + B2BSTUP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x308); + + /// address: 0x50000b28 + /// device endpoint-1 interrupt + /// register + pub const DOEPINT1 = @intToPtr(*volatile Mmio(32, packed struct { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved0: u1, + /// STUP + STUP: u1, + /// OTEPDIS + OTEPDIS: u1, + reserved1: u1, + /// B2BSTUP + B2BSTUP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x328); + + /// address: 0x50000b48 + /// device endpoint-2 interrupt + /// register + pub const DOEPINT2 = @intToPtr(*volatile Mmio(32, packed struct { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved0: u1, + /// STUP + STUP: u1, + /// OTEPDIS + OTEPDIS: u1, + reserved1: u1, + /// B2BSTUP + B2BSTUP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x348); + + /// address: 0x50000b68 + /// device endpoint-3 interrupt + /// register + pub const DOEPINT3 = @intToPtr(*volatile Mmio(32, packed struct { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved0: u1, + /// STUP + STUP: u1, + /// OTEPDIS + OTEPDIS: u1, + reserved1: u1, + /// B2BSTUP + B2BSTUP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x368); + + /// address: 0x50000910 + /// device endpoint-0 transfer size + /// register + pub const DIEPTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u7, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Packet count + PKTCNT: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x110); + + /// address: 0x50000b10 + /// device OUT endpoint-0 transfer size + /// register + pub const DOEPTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u7, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Packet count + PKTCNT: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + /// SETUP packet count + STUPCNT: u2, + padding0: u1, + }), base_address + 0x310); + + /// address: 0x50000930 + /// device endpoint-1 transfer size + /// register + pub const DIEPTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding0: u1, + }), base_address + 0x130); + + /// address: 0x50000950 + /// device endpoint-2 transfer size + /// register + pub const DIEPTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding0: u1, + }), base_address + 0x150); + + /// address: 0x50000970 + /// device endpoint-3 transfer size + /// register + pub const DIEPTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding0: u1, + }), base_address + 0x170); + + /// address: 0x50000918 + /// OTG_FS device IN endpoint transmit FIFO + /// status register + pub const DTXFSTS0 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// available + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x118); + + /// address: 0x50000938 + /// OTG_FS device IN endpoint transmit FIFO + /// status register + pub const DTXFSTS1 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// available + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x138); + + /// address: 0x50000958 + /// OTG_FS device IN endpoint transmit FIFO + /// status register + pub const DTXFSTS2 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// available + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x158); + + /// address: 0x50000978 + /// OTG_FS device IN endpoint transmit FIFO + /// status register + pub const DTXFSTS3 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// available + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x178); + + /// address: 0x50000b30 + /// device OUT endpoint-1 transfer size + /// register + pub const DOEPTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet + /// count + RXDPID_STUPCNT: u2, + padding0: u1, + }), base_address + 0x330); + + /// address: 0x50000b50 + /// device OUT endpoint-2 transfer size + /// register + pub const DOEPTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet + /// count + RXDPID_STUPCNT: u2, + padding0: u1, + }), base_address + 0x350); + + /// address: 0x50000b70 + /// device OUT endpoint-3 transfer size + /// register + pub const DOEPTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet + /// count + RXDPID_STUPCNT: u2, + padding0: u1, + }), base_address + 0x370); + }; + + /// USB on the go full speed + pub const OTG_FS_PWRCLK = struct { + pub const base_address = 0x50000e00; + + /// address: 0x50000e00 + /// OTG_FS power and clock gating control + /// register (OTG_FS_PCGCCTL) + pub const FS_PCGCCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Stop PHY clock + STPPCLK: u1, + /// Gate HCLK + GATEHCLK: u1, + reserved0: u1, + reserved1: u1, + /// PHY Suspended + PHYSUSP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x0); + }; + + /// Controller area network + pub const CAN1 = struct { + pub const base_address = 0x40006400; + + /// address: 0x40006400 + /// master control register + pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { + /// INRQ + INRQ: u1, + /// SLEEP + SLEEP: u1, + /// TXFP + TXFP: u1, + /// RFLM + RFLM: u1, + /// NART + NART: u1, + /// AWUM + AWUM: u1, + /// ABOM + ABOM: u1, + /// TTCM + TTCM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// RESET + RESET: u1, + /// DBF + DBF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x0); + + /// address: 0x40006404 + /// master status register + pub const MSR = @intToPtr(*volatile Mmio(32, packed struct { + /// INAK + INAK: u1, + /// SLAK + SLAK: u1, + /// ERRI + ERRI: u1, + /// WKUI + WKUI: u1, + /// SLAKI + SLAKI: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// TXM + TXM: u1, + /// RXM + RXM: u1, + /// SAMP + SAMP: u1, + /// RX + RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x4); + + /// address: 0x40006408 + /// transmit status register + pub const TSR = @intToPtr(*volatile Mmio(32, packed struct { + /// RQCP0 + RQCP0: u1, + /// TXOK0 + TXOK0: u1, + /// ALST0 + ALST0: u1, + /// TERR0 + TERR0: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// ABRQ0 + ABRQ0: u1, + /// RQCP1 + RQCP1: u1, + /// TXOK1 + TXOK1: u1, + /// ALST1 + ALST1: u1, + /// TERR1 + TERR1: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// ABRQ1 + ABRQ1: u1, + /// RQCP2 + RQCP2: u1, + /// TXOK2 + TXOK2: u1, + /// ALST2 + ALST2: u1, + /// TERR2 + TERR2: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// ABRQ2 + ABRQ2: u1, + /// CODE + CODE: u2, + /// Lowest priority flag for mailbox + /// 0 + TME0: u1, + /// Lowest priority flag for mailbox + /// 1 + TME1: u1, + /// Lowest priority flag for mailbox + /// 2 + TME2: u1, + /// Lowest priority flag for mailbox + /// 0 + LOW0: u1, + /// Lowest priority flag for mailbox + /// 1 + LOW1: u1, + /// Lowest priority flag for mailbox + /// 2 + LOW2: u1, + }), base_address + 0x8); + + /// address: 0x4000640c + /// receive FIFO 0 register + pub const RF0R = @intToPtr(*volatile Mmio(32, packed struct { + /// FMP0 + FMP0: u2, + reserved0: u1, + /// FULL0 + FULL0: u1, + /// FOVR0 + FOVR0: u1, + /// RFOM0 + RFOM0: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0xc); + + /// address: 0x40006410 + /// receive FIFO 1 register + pub const RF1R = @intToPtr(*volatile Mmio(32, packed struct { + /// FMP1 + FMP1: u2, + reserved0: u1, + /// FULL1 + FULL1: u1, + /// FOVR1 + FOVR1: u1, + /// RFOM1 + RFOM1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x10); + + /// address: 0x40006414 + /// interrupt enable register + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { + /// TMEIE + TMEIE: u1, + /// FMPIE0 + FMPIE0: u1, + /// FFIE0 + FFIE0: u1, + /// FOVIE0 + FOVIE0: u1, + /// FMPIE1 + FMPIE1: u1, + /// FFIE1 + FFIE1: u1, + /// FOVIE1 + FOVIE1: u1, + reserved0: u1, + /// EWGIE + EWGIE: u1, + /// EPVIE + EPVIE: u1, + /// BOFIE + BOFIE: u1, + /// LECIE + LECIE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// ERRIE + ERRIE: u1, + /// WKUIE + WKUIE: u1, + /// SLKIE + SLKIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x14); + + /// address: 0x40006418 + /// interrupt enable register + pub const ESR = @intToPtr(*volatile Mmio(32, packed struct { + /// EWGF + EWGF: u1, + /// EPVF + EPVF: u1, + /// BOFF + BOFF: u1, + reserved0: u1, + /// LEC + LEC: u3, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// TEC + TEC: u8, + /// REC + REC: u8, + }), base_address + 0x18); + + /// address: 0x4000641c + /// bit timing register + pub const BTR = @intToPtr(*volatile Mmio(32, packed struct { + /// BRP + BRP: u10, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// TS1 + TS1: u4, + /// TS2 + TS2: u3, + reserved6: u1, + /// SJW + SJW: u2, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// LBKM + LBKM: u1, + /// SILM + SILM: u1, + }), base_address + 0x1c); + + /// address: 0x40006580 + /// TX mailbox identifier register + pub const TI0R = @intToPtr(*volatile Mmio(32, packed struct { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x180); + + /// address: 0x40006584 + /// mailbox data length control and time stamp + /// register + pub const TDT0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x184); + + /// address: 0x40006588 + /// mailbox data low register + pub const TDL0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x188); + + /// address: 0x4000658c + /// mailbox data high register + pub const TDH0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x18c); + + /// address: 0x40006590 + /// mailbox identifier register + pub const TI1R = @intToPtr(*volatile Mmio(32, packed struct { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x190); + + /// address: 0x40006594 + /// mailbox data length control and time stamp + /// register + pub const TDT1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x194); + + /// address: 0x40006598 + /// mailbox data low register + pub const TDL1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x198); + + /// address: 0x4000659c + /// mailbox data high register + pub const TDH1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x19c); + + /// address: 0x400065a0 + /// mailbox identifier register + pub const TI2R = @intToPtr(*volatile Mmio(32, packed struct { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1a0); + + /// address: 0x400065a4 + /// mailbox data length control and time stamp + /// register + pub const TDT2R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x1a4); + + /// address: 0x400065a8 + /// mailbox data low register + pub const TDL2R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1a8); + + /// address: 0x400065ac + /// mailbox data high register + pub const TDH2R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1ac); + + /// address: 0x400065b0 + /// receive FIFO mailbox identifier + /// register + pub const RI0R = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1b0); + + /// address: 0x400065b4 + /// mailbox data high register + pub const RDT0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// FMI + FMI: u8, + /// TIME + TIME: u16, + }), base_address + 0x1b4); + + /// address: 0x400065b8 + /// mailbox data high register + pub const RDL0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1b8); + + /// address: 0x400065bc + /// receive FIFO mailbox data high + /// register + pub const RDH0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1bc); + + /// address: 0x400065c0 + /// mailbox data high register + pub const RI1R = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1c0); + + /// address: 0x400065c4 + /// mailbox data high register + pub const RDT1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// FMI + FMI: u8, + /// TIME + TIME: u16, + }), base_address + 0x1c4); + + /// address: 0x400065c8 + /// mailbox data high register + pub const RDL1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1c8); + + /// address: 0x400065cc + /// mailbox data high register + pub const RDH1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1cc); + + /// address: 0x40006600 + /// filter master register + pub const FMR = @intToPtr(*volatile Mmio(32, packed struct { + /// FINIT + FINIT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// CAN2SB + CAN2SB: u6, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x200); + + /// address: 0x40006604 + /// filter mode register + pub const FM1R = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter mode + FBM0: u1, + /// Filter mode + FBM1: u1, + /// Filter mode + FBM2: u1, + /// Filter mode + FBM3: u1, + /// Filter mode + FBM4: u1, + /// Filter mode + FBM5: u1, + /// Filter mode + FBM6: u1, + /// Filter mode + FBM7: u1, + /// Filter mode + FBM8: u1, + /// Filter mode + FBM9: u1, + /// Filter mode + FBM10: u1, + /// Filter mode + FBM11: u1, + /// Filter mode + FBM12: u1, + /// Filter mode + FBM13: u1, + /// Filter mode + FBM14: u1, + /// Filter mode + FBM15: u1, + /// Filter mode + FBM16: u1, + /// Filter mode + FBM17: u1, + /// Filter mode + FBM18: u1, + /// Filter mode + FBM19: u1, + /// Filter mode + FBM20: u1, + /// Filter mode + FBM21: u1, + /// Filter mode + FBM22: u1, + /// Filter mode + FBM23: u1, + /// Filter mode + FBM24: u1, + /// Filter mode + FBM25: u1, + /// Filter mode + FBM26: u1, + /// Filter mode + FBM27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x204); + + /// address: 0x4000660c + /// filter scale register + pub const FS1R = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter scale configuration + FSC0: u1, + /// Filter scale configuration + FSC1: u1, + /// Filter scale configuration + FSC2: u1, + /// Filter scale configuration + FSC3: u1, + /// Filter scale configuration + FSC4: u1, + /// Filter scale configuration + FSC5: u1, + /// Filter scale configuration + FSC6: u1, + /// Filter scale configuration + FSC7: u1, + /// Filter scale configuration + FSC8: u1, + /// Filter scale configuration + FSC9: u1, + /// Filter scale configuration + FSC10: u1, + /// Filter scale configuration + FSC11: u1, + /// Filter scale configuration + FSC12: u1, + /// Filter scale configuration + FSC13: u1, + /// Filter scale configuration + FSC14: u1, + /// Filter scale configuration + FSC15: u1, + /// Filter scale configuration + FSC16: u1, + /// Filter scale configuration + FSC17: u1, + /// Filter scale configuration + FSC18: u1, + /// Filter scale configuration + FSC19: u1, + /// Filter scale configuration + FSC20: u1, + /// Filter scale configuration + FSC21: u1, + /// Filter scale configuration + FSC22: u1, + /// Filter scale configuration + FSC23: u1, + /// Filter scale configuration + FSC24: u1, + /// Filter scale configuration + FSC25: u1, + /// Filter scale configuration + FSC26: u1, + /// Filter scale configuration + FSC27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x20c); + + /// address: 0x40006614 + /// filter FIFO assignment + /// register + pub const FFA1R = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter FIFO assignment for filter + /// 0 + FFA0: u1, + /// Filter FIFO assignment for filter + /// 1 + FFA1: u1, + /// Filter FIFO assignment for filter + /// 2 + FFA2: u1, + /// Filter FIFO assignment for filter + /// 3 + FFA3: u1, + /// Filter FIFO assignment for filter + /// 4 + FFA4: u1, + /// Filter FIFO assignment for filter + /// 5 + FFA5: u1, + /// Filter FIFO assignment for filter + /// 6 + FFA6: u1, + /// Filter FIFO assignment for filter + /// 7 + FFA7: u1, + /// Filter FIFO assignment for filter + /// 8 + FFA8: u1, + /// Filter FIFO assignment for filter + /// 9 + FFA9: u1, + /// Filter FIFO assignment for filter + /// 10 + FFA10: u1, + /// Filter FIFO assignment for filter + /// 11 + FFA11: u1, + /// Filter FIFO assignment for filter + /// 12 + FFA12: u1, + /// Filter FIFO assignment for filter + /// 13 + FFA13: u1, + /// Filter FIFO assignment for filter + /// 14 + FFA14: u1, + /// Filter FIFO assignment for filter + /// 15 + FFA15: u1, + /// Filter FIFO assignment for filter + /// 16 + FFA16: u1, + /// Filter FIFO assignment for filter + /// 17 + FFA17: u1, + /// Filter FIFO assignment for filter + /// 18 + FFA18: u1, + /// Filter FIFO assignment for filter + /// 19 + FFA19: u1, + /// Filter FIFO assignment for filter + /// 20 + FFA20: u1, + /// Filter FIFO assignment for filter + /// 21 + FFA21: u1, + /// Filter FIFO assignment for filter + /// 22 + FFA22: u1, + /// Filter FIFO assignment for filter + /// 23 + FFA23: u1, + /// Filter FIFO assignment for filter + /// 24 + FFA24: u1, + /// Filter FIFO assignment for filter + /// 25 + FFA25: u1, + /// Filter FIFO assignment for filter + /// 26 + FFA26: u1, + /// Filter FIFO assignment for filter + /// 27 + FFA27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x214); + + /// address: 0x4000661c + /// filter activation register + pub const FA1R = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter active + FACT0: u1, + /// Filter active + FACT1: u1, + /// Filter active + FACT2: u1, + /// Filter active + FACT3: u1, + /// Filter active + FACT4: u1, + /// Filter active + FACT5: u1, + /// Filter active + FACT6: u1, + /// Filter active + FACT7: u1, + /// Filter active + FACT8: u1, + /// Filter active + FACT9: u1, + /// Filter active + FACT10: u1, + /// Filter active + FACT11: u1, + /// Filter active + FACT12: u1, + /// Filter active + FACT13: u1, + /// Filter active + FACT14: u1, + /// Filter active + FACT15: u1, + /// Filter active + FACT16: u1, + /// Filter active + FACT17: u1, + /// Filter active + FACT18: u1, + /// Filter active + FACT19: u1, + /// Filter active + FACT20: u1, + /// Filter active + FACT21: u1, + /// Filter active + FACT22: u1, + /// Filter active + FACT23: u1, + /// Filter active + FACT24: u1, + /// Filter active + FACT25: u1, + /// Filter active + FACT26: u1, + /// Filter active + FACT27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x21c); + + /// address: 0x40006640 + /// Filter bank 0 register 1 + pub const F0R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x240); + + /// address: 0x40006644 + /// Filter bank 0 register 2 + pub const F0R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x244); + + /// address: 0x40006648 + /// Filter bank 1 register 1 + pub const F1R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x248); + + /// address: 0x4000664c + /// Filter bank 1 register 2 + pub const F1R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x24c); + + /// address: 0x40006650 + /// Filter bank 2 register 1 + pub const F2R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x250); + + /// address: 0x40006654 + /// Filter bank 2 register 2 + pub const F2R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x254); + + /// address: 0x40006658 + /// Filter bank 3 register 1 + pub const F3R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x258); + + /// address: 0x4000665c + /// Filter bank 3 register 2 + pub const F3R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x25c); + + /// address: 0x40006660 + /// Filter bank 4 register 1 + pub const F4R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x260); + + /// address: 0x40006664 + /// Filter bank 4 register 2 + pub const F4R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x264); + + /// address: 0x40006668 + /// Filter bank 5 register 1 + pub const F5R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x268); + + /// address: 0x4000666c + /// Filter bank 5 register 2 + pub const F5R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x26c); + + /// address: 0x40006670 + /// Filter bank 6 register 1 + pub const F6R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x270); + + /// address: 0x40006674 + /// Filter bank 6 register 2 + pub const F6R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x274); + + /// address: 0x40006678 + /// Filter bank 7 register 1 + pub const F7R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x278); + + /// address: 0x4000667c + /// Filter bank 7 register 2 + pub const F7R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x27c); + + /// address: 0x40006680 + /// Filter bank 8 register 1 + pub const F8R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x280); + + /// address: 0x40006684 + /// Filter bank 8 register 2 + pub const F8R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x284); + + /// address: 0x40006688 + /// Filter bank 9 register 1 + pub const F9R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x288); + + /// address: 0x4000668c + /// Filter bank 9 register 2 + pub const F9R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x28c); + + /// address: 0x40006690 + /// Filter bank 10 register 1 + pub const F10R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x290); + + /// address: 0x40006694 + /// Filter bank 10 register 2 + pub const F10R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x294); + + /// address: 0x40006698 + /// Filter bank 11 register 1 + pub const F11R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x298); + + /// address: 0x4000669c + /// Filter bank 11 register 2 + pub const F11R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x29c); + + /// address: 0x400066a0 + /// Filter bank 4 register 1 + pub const F12R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a0); + + /// address: 0x400066a4 + /// Filter bank 12 register 2 + pub const F12R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a4); + + /// address: 0x400066a8 + /// Filter bank 13 register 1 + pub const F13R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a8); + + /// address: 0x400066ac + /// Filter bank 13 register 2 + pub const F13R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2ac); + + /// address: 0x400066b0 + /// Filter bank 14 register 1 + pub const F14R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2b0); + + /// address: 0x400066b4 + /// Filter bank 14 register 2 + pub const F14R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2b4); + + /// address: 0x400066b8 + /// Filter bank 15 register 1 + pub const F15R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2b8); + + /// address: 0x400066bc + /// Filter bank 15 register 2 + pub const F15R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2bc); + + /// address: 0x400066c0 + /// Filter bank 16 register 1 + pub const F16R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2c0); + + /// address: 0x400066c4 + /// Filter bank 16 register 2 + pub const F16R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2c4); + + /// address: 0x400066c8 + /// Filter bank 17 register 1 + pub const F17R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2c8); + + /// address: 0x400066cc + /// Filter bank 17 register 2 + pub const F17R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2cc); + + /// address: 0x400066d0 + /// Filter bank 18 register 1 + pub const F18R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2d0); + + /// address: 0x400066d4 + /// Filter bank 18 register 2 + pub const F18R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2d4); + + /// address: 0x400066d8 + /// Filter bank 19 register 1 + pub const F19R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2d8); + + /// address: 0x400066dc + /// Filter bank 19 register 2 + pub const F19R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2dc); + + /// address: 0x400066e0 + /// Filter bank 20 register 1 + pub const F20R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2e0); + + /// address: 0x400066e4 + /// Filter bank 20 register 2 + pub const F20R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2e4); + + /// address: 0x400066e8 + /// Filter bank 21 register 1 + pub const F21R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2e8); + + /// address: 0x400066ec + /// Filter bank 21 register 2 + pub const F21R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2ec); + + /// address: 0x400066f0 + /// Filter bank 22 register 1 + pub const F22R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2f0); + + /// address: 0x400066f4 + /// Filter bank 22 register 2 + pub const F22R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2f4); + + /// address: 0x400066f8 + /// Filter bank 23 register 1 + pub const F23R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2f8); + + /// address: 0x400066fc + /// Filter bank 23 register 2 + pub const F23R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2fc); + + /// address: 0x40006700 + /// Filter bank 24 register 1 + pub const F24R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x300); + + /// address: 0x40006704 + /// Filter bank 24 register 2 + pub const F24R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x304); + + /// address: 0x40006708 + /// Filter bank 25 register 1 + pub const F25R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x308); + + /// address: 0x4000670c + /// Filter bank 25 register 2 + pub const F25R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x30c); + + /// address: 0x40006710 + /// Filter bank 26 register 1 + pub const F26R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x310); + + /// address: 0x40006714 + /// Filter bank 26 register 2 + pub const F26R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x314); + + /// address: 0x40006718 + /// Filter bank 27 register 1 + pub const F27R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x318); + + /// address: 0x4000671c + /// Filter bank 27 register 2 + pub const F27R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x31c); + }; + pub const CAN2 = struct { + pub const base_address = 0x40006800; + + /// address: 0x40006800 + /// master control register + pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { + /// INRQ + INRQ: u1, + /// SLEEP + SLEEP: u1, + /// TXFP + TXFP: u1, + /// RFLM + RFLM: u1, + /// NART + NART: u1, + /// AWUM + AWUM: u1, + /// ABOM + ABOM: u1, + /// TTCM + TTCM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// RESET + RESET: u1, + /// DBF + DBF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x0); + + /// address: 0x40006804 + /// master status register + pub const MSR = @intToPtr(*volatile Mmio(32, packed struct { + /// INAK + INAK: u1, + /// SLAK + SLAK: u1, + /// ERRI + ERRI: u1, + /// WKUI + WKUI: u1, + /// SLAKI + SLAKI: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// TXM + TXM: u1, + /// RXM + RXM: u1, + /// SAMP + SAMP: u1, + /// RX + RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x4); + + /// address: 0x40006808 + /// transmit status register + pub const TSR = @intToPtr(*volatile Mmio(32, packed struct { + /// RQCP0 + RQCP0: u1, + /// TXOK0 + TXOK0: u1, + /// ALST0 + ALST0: u1, + /// TERR0 + TERR0: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// ABRQ0 + ABRQ0: u1, + /// RQCP1 + RQCP1: u1, + /// TXOK1 + TXOK1: u1, + /// ALST1 + ALST1: u1, + /// TERR1 + TERR1: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// ABRQ1 + ABRQ1: u1, + /// RQCP2 + RQCP2: u1, + /// TXOK2 + TXOK2: u1, + /// ALST2 + ALST2: u1, + /// TERR2 + TERR2: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// ABRQ2 + ABRQ2: u1, + /// CODE + CODE: u2, + /// Lowest priority flag for mailbox + /// 0 + TME0: u1, + /// Lowest priority flag for mailbox + /// 1 + TME1: u1, + /// Lowest priority flag for mailbox + /// 2 + TME2: u1, + /// Lowest priority flag for mailbox + /// 0 + LOW0: u1, + /// Lowest priority flag for mailbox + /// 1 + LOW1: u1, + /// Lowest priority flag for mailbox + /// 2 + LOW2: u1, + }), base_address + 0x8); + + /// address: 0x4000680c + /// receive FIFO 0 register + pub const RF0R = @intToPtr(*volatile Mmio(32, packed struct { + /// FMP0 + FMP0: u2, + reserved0: u1, + /// FULL0 + FULL0: u1, + /// FOVR0 + FOVR0: u1, + /// RFOM0 + RFOM0: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0xc); + + /// address: 0x40006810 + /// receive FIFO 1 register + pub const RF1R = @intToPtr(*volatile Mmio(32, packed struct { + /// FMP1 + FMP1: u2, + reserved0: u1, + /// FULL1 + FULL1: u1, + /// FOVR1 + FOVR1: u1, + /// RFOM1 + RFOM1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x10); + + /// address: 0x40006814 + /// interrupt enable register + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { + /// TMEIE + TMEIE: u1, + /// FMPIE0 + FMPIE0: u1, + /// FFIE0 + FFIE0: u1, + /// FOVIE0 + FOVIE0: u1, + /// FMPIE1 + FMPIE1: u1, + /// FFIE1 + FFIE1: u1, + /// FOVIE1 + FOVIE1: u1, + reserved0: u1, + /// EWGIE + EWGIE: u1, + /// EPVIE + EPVIE: u1, + /// BOFIE + BOFIE: u1, + /// LECIE + LECIE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// ERRIE + ERRIE: u1, + /// WKUIE + WKUIE: u1, + /// SLKIE + SLKIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x14); + + /// address: 0x40006818 + /// interrupt enable register + pub const ESR = @intToPtr(*volatile Mmio(32, packed struct { + /// EWGF + EWGF: u1, + /// EPVF + EPVF: u1, + /// BOFF + BOFF: u1, + reserved0: u1, + /// LEC + LEC: u3, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// TEC + TEC: u8, + /// REC + REC: u8, + }), base_address + 0x18); + + /// address: 0x4000681c + /// bit timing register + pub const BTR = @intToPtr(*volatile Mmio(32, packed struct { + /// BRP + BRP: u10, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// TS1 + TS1: u4, + /// TS2 + TS2: u3, + reserved6: u1, + /// SJW + SJW: u2, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// LBKM + LBKM: u1, + /// SILM + SILM: u1, + }), base_address + 0x1c); + + /// address: 0x40006980 + /// TX mailbox identifier register + pub const TI0R = @intToPtr(*volatile Mmio(32, packed struct { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x180); + + /// address: 0x40006984 + /// mailbox data length control and time stamp + /// register + pub const TDT0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x184); + + /// address: 0x40006988 + /// mailbox data low register + pub const TDL0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x188); + + /// address: 0x4000698c + /// mailbox data high register + pub const TDH0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x18c); + + /// address: 0x40006990 + /// mailbox identifier register + pub const TI1R = @intToPtr(*volatile Mmio(32, packed struct { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x190); + + /// address: 0x40006994 + /// mailbox data length control and time stamp + /// register + pub const TDT1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x194); + + /// address: 0x40006998 + /// mailbox data low register + pub const TDL1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x198); + + /// address: 0x4000699c + /// mailbox data high register + pub const TDH1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x19c); + + /// address: 0x400069a0 + /// mailbox identifier register + pub const TI2R = @intToPtr(*volatile Mmio(32, packed struct { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1a0); + + /// address: 0x400069a4 + /// mailbox data length control and time stamp + /// register + pub const TDT2R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x1a4); + + /// address: 0x400069a8 + /// mailbox data low register + pub const TDL2R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1a8); + + /// address: 0x400069ac + /// mailbox data high register + pub const TDH2R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1ac); + + /// address: 0x400069b0 + /// receive FIFO mailbox identifier + /// register + pub const RI0R = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1b0); + + /// address: 0x400069b4 + /// mailbox data high register + pub const RDT0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// FMI + FMI: u8, + /// TIME + TIME: u16, + }), base_address + 0x1b4); + + /// address: 0x400069b8 + /// mailbox data high register + pub const RDL0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1b8); + + /// address: 0x400069bc + /// receive FIFO mailbox data high + /// register + pub const RDH0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1bc); + + /// address: 0x400069c0 + /// mailbox data high register + pub const RI1R = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1c0); + + /// address: 0x400069c4 + /// mailbox data high register + pub const RDT1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// FMI + FMI: u8, + /// TIME + TIME: u16, + }), base_address + 0x1c4); + + /// address: 0x400069c8 + /// mailbox data high register + pub const RDL1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1c8); + + /// address: 0x400069cc + /// mailbox data high register + pub const RDH1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1cc); + + /// address: 0x40006a00 + /// filter master register + pub const FMR = @intToPtr(*volatile Mmio(32, packed struct { + /// FINIT + FINIT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// CAN2SB + CAN2SB: u6, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x200); + + /// address: 0x40006a04 + /// filter mode register + pub const FM1R = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter mode + FBM0: u1, + /// Filter mode + FBM1: u1, + /// Filter mode + FBM2: u1, + /// Filter mode + FBM3: u1, + /// Filter mode + FBM4: u1, + /// Filter mode + FBM5: u1, + /// Filter mode + FBM6: u1, + /// Filter mode + FBM7: u1, + /// Filter mode + FBM8: u1, + /// Filter mode + FBM9: u1, + /// Filter mode + FBM10: u1, + /// Filter mode + FBM11: u1, + /// Filter mode + FBM12: u1, + /// Filter mode + FBM13: u1, + /// Filter mode + FBM14: u1, + /// Filter mode + FBM15: u1, + /// Filter mode + FBM16: u1, + /// Filter mode + FBM17: u1, + /// Filter mode + FBM18: u1, + /// Filter mode + FBM19: u1, + /// Filter mode + FBM20: u1, + /// Filter mode + FBM21: u1, + /// Filter mode + FBM22: u1, + /// Filter mode + FBM23: u1, + /// Filter mode + FBM24: u1, + /// Filter mode + FBM25: u1, + /// Filter mode + FBM26: u1, + /// Filter mode + FBM27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x204); + + /// address: 0x40006a0c + /// filter scale register + pub const FS1R = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter scale configuration + FSC0: u1, + /// Filter scale configuration + FSC1: u1, + /// Filter scale configuration + FSC2: u1, + /// Filter scale configuration + FSC3: u1, + /// Filter scale configuration + FSC4: u1, + /// Filter scale configuration + FSC5: u1, + /// Filter scale configuration + FSC6: u1, + /// Filter scale configuration + FSC7: u1, + /// Filter scale configuration + FSC8: u1, + /// Filter scale configuration + FSC9: u1, + /// Filter scale configuration + FSC10: u1, + /// Filter scale configuration + FSC11: u1, + /// Filter scale configuration + FSC12: u1, + /// Filter scale configuration + FSC13: u1, + /// Filter scale configuration + FSC14: u1, + /// Filter scale configuration + FSC15: u1, + /// Filter scale configuration + FSC16: u1, + /// Filter scale configuration + FSC17: u1, + /// Filter scale configuration + FSC18: u1, + /// Filter scale configuration + FSC19: u1, + /// Filter scale configuration + FSC20: u1, + /// Filter scale configuration + FSC21: u1, + /// Filter scale configuration + FSC22: u1, + /// Filter scale configuration + FSC23: u1, + /// Filter scale configuration + FSC24: u1, + /// Filter scale configuration + FSC25: u1, + /// Filter scale configuration + FSC26: u1, + /// Filter scale configuration + FSC27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x20c); + + /// address: 0x40006a14 + /// filter FIFO assignment + /// register + pub const FFA1R = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter FIFO assignment for filter + /// 0 + FFA0: u1, + /// Filter FIFO assignment for filter + /// 1 + FFA1: u1, + /// Filter FIFO assignment for filter + /// 2 + FFA2: u1, + /// Filter FIFO assignment for filter + /// 3 + FFA3: u1, + /// Filter FIFO assignment for filter + /// 4 + FFA4: u1, + /// Filter FIFO assignment for filter + /// 5 + FFA5: u1, + /// Filter FIFO assignment for filter + /// 6 + FFA6: u1, + /// Filter FIFO assignment for filter + /// 7 + FFA7: u1, + /// Filter FIFO assignment for filter + /// 8 + FFA8: u1, + /// Filter FIFO assignment for filter + /// 9 + FFA9: u1, + /// Filter FIFO assignment for filter + /// 10 + FFA10: u1, + /// Filter FIFO assignment for filter + /// 11 + FFA11: u1, + /// Filter FIFO assignment for filter + /// 12 + FFA12: u1, + /// Filter FIFO assignment for filter + /// 13 + FFA13: u1, + /// Filter FIFO assignment for filter + /// 14 + FFA14: u1, + /// Filter FIFO assignment for filter + /// 15 + FFA15: u1, + /// Filter FIFO assignment for filter + /// 16 + FFA16: u1, + /// Filter FIFO assignment for filter + /// 17 + FFA17: u1, + /// Filter FIFO assignment for filter + /// 18 + FFA18: u1, + /// Filter FIFO assignment for filter + /// 19 + FFA19: u1, + /// Filter FIFO assignment for filter + /// 20 + FFA20: u1, + /// Filter FIFO assignment for filter + /// 21 + FFA21: u1, + /// Filter FIFO assignment for filter + /// 22 + FFA22: u1, + /// Filter FIFO assignment for filter + /// 23 + FFA23: u1, + /// Filter FIFO assignment for filter + /// 24 + FFA24: u1, + /// Filter FIFO assignment for filter + /// 25 + FFA25: u1, + /// Filter FIFO assignment for filter + /// 26 + FFA26: u1, + /// Filter FIFO assignment for filter + /// 27 + FFA27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x214); + + /// address: 0x40006a1c + /// filter activation register + pub const FA1R = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter active + FACT0: u1, + /// Filter active + FACT1: u1, + /// Filter active + FACT2: u1, + /// Filter active + FACT3: u1, + /// Filter active + FACT4: u1, + /// Filter active + FACT5: u1, + /// Filter active + FACT6: u1, + /// Filter active + FACT7: u1, + /// Filter active + FACT8: u1, + /// Filter active + FACT9: u1, + /// Filter active + FACT10: u1, + /// Filter active + FACT11: u1, + /// Filter active + FACT12: u1, + /// Filter active + FACT13: u1, + /// Filter active + FACT14: u1, + /// Filter active + FACT15: u1, + /// Filter active + FACT16: u1, + /// Filter active + FACT17: u1, + /// Filter active + FACT18: u1, + /// Filter active + FACT19: u1, + /// Filter active + FACT20: u1, + /// Filter active + FACT21: u1, + /// Filter active + FACT22: u1, + /// Filter active + FACT23: u1, + /// Filter active + FACT24: u1, + /// Filter active + FACT25: u1, + /// Filter active + FACT26: u1, + /// Filter active + FACT27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x21c); + + /// address: 0x40006a40 + /// Filter bank 0 register 1 + pub const F0R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x240); + + /// address: 0x40006a44 + /// Filter bank 0 register 2 + pub const F0R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x244); + + /// address: 0x40006a48 + /// Filter bank 1 register 1 + pub const F1R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x248); + + /// address: 0x40006a4c + /// Filter bank 1 register 2 + pub const F1R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x24c); + + /// address: 0x40006a50 + /// Filter bank 2 register 1 + pub const F2R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x250); + + /// address: 0x40006a54 + /// Filter bank 2 register 2 + pub const F2R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x254); + + /// address: 0x40006a58 + /// Filter bank 3 register 1 + pub const F3R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x258); + + /// address: 0x40006a5c + /// Filter bank 3 register 2 + pub const F3R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x25c); + + /// address: 0x40006a60 + /// Filter bank 4 register 1 + pub const F4R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x260); + + /// address: 0x40006a64 + /// Filter bank 4 register 2 + pub const F4R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x264); + + /// address: 0x40006a68 + /// Filter bank 5 register 1 + pub const F5R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x268); + + /// address: 0x40006a6c + /// Filter bank 5 register 2 + pub const F5R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x26c); + + /// address: 0x40006a70 + /// Filter bank 6 register 1 + pub const F6R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x270); + + /// address: 0x40006a74 + /// Filter bank 6 register 2 + pub const F6R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x274); + + /// address: 0x40006a78 + /// Filter bank 7 register 1 + pub const F7R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x278); + + /// address: 0x40006a7c + /// Filter bank 7 register 2 + pub const F7R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x27c); + + /// address: 0x40006a80 + /// Filter bank 8 register 1 + pub const F8R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x280); + + /// address: 0x40006a84 + /// Filter bank 8 register 2 + pub const F8R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x284); + + /// address: 0x40006a88 + /// Filter bank 9 register 1 + pub const F9R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x288); + + /// address: 0x40006a8c + /// Filter bank 9 register 2 + pub const F9R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x28c); + + /// address: 0x40006a90 + /// Filter bank 10 register 1 + pub const F10R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x290); + + /// address: 0x40006a94 + /// Filter bank 10 register 2 + pub const F10R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x294); + + /// address: 0x40006a98 + /// Filter bank 11 register 1 + pub const F11R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x298); + + /// address: 0x40006a9c + /// Filter bank 11 register 2 + pub const F11R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x29c); + + /// address: 0x40006aa0 + /// Filter bank 4 register 1 + pub const F12R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a0); + + /// address: 0x40006aa4 + /// Filter bank 12 register 2 + pub const F12R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a4); + + /// address: 0x40006aa8 + /// Filter bank 13 register 1 + pub const F13R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a8); + + /// address: 0x40006aac + /// Filter bank 13 register 2 + pub const F13R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2ac); + + /// address: 0x40006ab0 + /// Filter bank 14 register 1 + pub const F14R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2b0); + + /// address: 0x40006ab4 + /// Filter bank 14 register 2 + pub const F14R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2b4); + + /// address: 0x40006ab8 + /// Filter bank 15 register 1 + pub const F15R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2b8); + + /// address: 0x40006abc + /// Filter bank 15 register 2 + pub const F15R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2bc); + + /// address: 0x40006ac0 + /// Filter bank 16 register 1 + pub const F16R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2c0); + + /// address: 0x40006ac4 + /// Filter bank 16 register 2 + pub const F16R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2c4); + + /// address: 0x40006ac8 + /// Filter bank 17 register 1 + pub const F17R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2c8); + + /// address: 0x40006acc + /// Filter bank 17 register 2 + pub const F17R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2cc); + + /// address: 0x40006ad0 + /// Filter bank 18 register 1 + pub const F18R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2d0); + + /// address: 0x40006ad4 + /// Filter bank 18 register 2 + pub const F18R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2d4); + + /// address: 0x40006ad8 + /// Filter bank 19 register 1 + pub const F19R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2d8); + + /// address: 0x40006adc + /// Filter bank 19 register 2 + pub const F19R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2dc); + + /// address: 0x40006ae0 + /// Filter bank 20 register 1 + pub const F20R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2e0); + + /// address: 0x40006ae4 + /// Filter bank 20 register 2 + pub const F20R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2e4); + + /// address: 0x40006ae8 + /// Filter bank 21 register 1 + pub const F21R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2e8); + + /// address: 0x40006aec + /// Filter bank 21 register 2 + pub const F21R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2ec); + + /// address: 0x40006af0 + /// Filter bank 22 register 1 + pub const F22R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2f0); + + /// address: 0x40006af4 + /// Filter bank 22 register 2 + pub const F22R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2f4); + + /// address: 0x40006af8 + /// Filter bank 23 register 1 + pub const F23R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2f8); + + /// address: 0x40006afc + /// Filter bank 23 register 2 + pub const F23R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2fc); + + /// address: 0x40006b00 + /// Filter bank 24 register 1 + pub const F24R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x300); + + /// address: 0x40006b04 + /// Filter bank 24 register 2 + pub const F24R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x304); + + /// address: 0x40006b08 + /// Filter bank 25 register 1 + pub const F25R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x308); + + /// address: 0x40006b0c + /// Filter bank 25 register 2 + pub const F25R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x30c); + + /// address: 0x40006b10 + /// Filter bank 26 register 1 + pub const F26R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x310); + + /// address: 0x40006b14 + /// Filter bank 26 register 2 + pub const F26R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x314); + + /// address: 0x40006b18 + /// Filter bank 27 register 1 + pub const F27R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x318); + + /// address: 0x40006b1c + /// Filter bank 27 register 2 + pub const F27R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x31c); + }; + + /// Nested Vectored Interrupt + /// Controller + pub const NVIC = struct { + pub const base_address = 0xe000e100; + + /// address: 0xe000e100 + /// Interrupt Set-Enable Register + pub const ISER0 = @intToPtr(*volatile Mmio(32, packed struct { + /// SETENA + SETENA: u32, + }), base_address + 0x0); + + /// address: 0xe000e104 + /// Interrupt Set-Enable Register + pub const ISER1 = @intToPtr(*volatile Mmio(32, packed struct { + /// SETENA + SETENA: u32, + }), base_address + 0x4); + + /// address: 0xe000e108 + /// Interrupt Set-Enable Register + pub const ISER2 = @intToPtr(*volatile Mmio(32, packed struct { + /// SETENA + SETENA: u32, + }), base_address + 0x8); + + /// address: 0xe000e180 + /// Interrupt Clear-Enable + /// Register + pub const ICER0 = @intToPtr(*volatile Mmio(32, packed struct { + /// CLRENA + CLRENA: u32, + }), base_address + 0x80); + + /// address: 0xe000e184 + /// Interrupt Clear-Enable + /// Register + pub const ICER1 = @intToPtr(*volatile Mmio(32, packed struct { + /// CLRENA + CLRENA: u32, + }), base_address + 0x84); + + /// address: 0xe000e188 + /// Interrupt Clear-Enable + /// Register + pub const ICER2 = @intToPtr(*volatile Mmio(32, packed struct { + /// CLRENA + CLRENA: u32, + }), base_address + 0x88); + + /// address: 0xe000e200 + /// Interrupt Set-Pending Register + pub const ISPR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// SETPEND + SETPEND: u32, + }), base_address + 0x100); + + /// address: 0xe000e204 + /// Interrupt Set-Pending Register + pub const ISPR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// SETPEND + SETPEND: u32, + }), base_address + 0x104); + + /// address: 0xe000e208 + /// Interrupt Set-Pending Register + pub const ISPR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// SETPEND + SETPEND: u32, + }), base_address + 0x108); + + /// address: 0xe000e280 + /// Interrupt Clear-Pending + /// Register + pub const ICPR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// CLRPEND + CLRPEND: u32, + }), base_address + 0x180); + + /// address: 0xe000e284 + /// Interrupt Clear-Pending + /// Register + pub const ICPR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// CLRPEND + CLRPEND: u32, + }), base_address + 0x184); + + /// address: 0xe000e288 + /// Interrupt Clear-Pending + /// Register + pub const ICPR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// CLRPEND + CLRPEND: u32, + }), base_address + 0x188); + + /// address: 0xe000e300 + /// Interrupt Active Bit Register + pub const IABR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// ACTIVE + ACTIVE: u32, + }), base_address + 0x200); + + /// address: 0xe000e304 + /// Interrupt Active Bit Register + pub const IABR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// ACTIVE + ACTIVE: u32, + }), base_address + 0x204); + + /// address: 0xe000e308 + /// Interrupt Active Bit Register + pub const IABR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// ACTIVE + ACTIVE: u32, + }), base_address + 0x208); + + /// address: 0xe000e400 + /// Interrupt Priority Register + pub const IPR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x300); + + /// address: 0xe000e404 + /// Interrupt Priority Register + pub const IPR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x304); + + /// address: 0xe000e408 + /// Interrupt Priority Register + pub const IPR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x308); + + /// address: 0xe000e40c + /// Interrupt Priority Register + pub const IPR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x30c); + + /// address: 0xe000e410 + /// Interrupt Priority Register + pub const IPR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x310); + + /// address: 0xe000e414 + /// Interrupt Priority Register + pub const IPR5 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x314); + + /// address: 0xe000e418 + /// Interrupt Priority Register + pub const IPR6 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x318); + + /// address: 0xe000e41c + /// Interrupt Priority Register + pub const IPR7 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x31c); + + /// address: 0xe000e420 + /// Interrupt Priority Register + pub const IPR8 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x320); + + /// address: 0xe000e424 + /// Interrupt Priority Register + pub const IPR9 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x324); + + /// address: 0xe000e428 + /// Interrupt Priority Register + pub const IPR10 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x328); + + /// address: 0xe000e42c + /// Interrupt Priority Register + pub const IPR11 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x32c); + + /// address: 0xe000e430 + /// Interrupt Priority Register + pub const IPR12 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x330); + + /// address: 0xe000e434 + /// Interrupt Priority Register + pub const IPR13 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x334); + + /// address: 0xe000e438 + /// Interrupt Priority Register + pub const IPR14 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x338); + + /// address: 0xe000e43c + /// Interrupt Priority Register + pub const IPR15 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x33c); + + /// address: 0xe000e440 + /// Interrupt Priority Register + pub const IPR16 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x340); + + /// address: 0xe000e444 + /// Interrupt Priority Register + pub const IPR17 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x344); + + /// address: 0xe000e448 + /// Interrupt Priority Register + pub const IPR18 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x348); + + /// address: 0xe000e44c + /// Interrupt Priority Register + pub const IPR19 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x34c); + + /// address: 0xe000e450 + /// Interrupt Priority Register + pub const IPR20 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x350); + }; + + /// FLASH + pub const FLASH = struct { + pub const base_address = 0x40023c00; + + /// address: 0x40023c00 + /// Flash access control register + pub const ACR = @intToPtr(*volatile Mmio(32, packed struct { + /// Latency + LATENCY: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Prefetch enable + PRFTEN: u1, + /// Instruction cache enable + ICEN: u1, + /// Data cache enable + DCEN: u1, + /// Instruction cache reset + ICRST: u1, + /// Data cache reset + DCRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x0); + + /// address: 0x40023c04 + /// Flash key register + pub const KEYR = @intToPtr(*volatile Mmio(32, packed struct { + /// FPEC key + KEY: u32, + }), base_address + 0x4); + + /// address: 0x40023c08 + /// Flash option key register + pub const OPTKEYR = @intToPtr(*volatile Mmio(32, packed struct { + /// Option byte key + OPTKEY: u32, + }), base_address + 0x8); + + /// address: 0x40023c0c + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// End of operation + EOP: u1, + /// Operation error + OPERR: u1, + reserved0: u1, + reserved1: u1, + /// Write protection error + WRPERR: u1, + /// Programming alignment + /// error + PGAERR: u1, + /// Programming parallelism + /// error + PGPERR: u1, + /// Programming sequence error + PGSERR: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Busy + BSY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0xc); + + /// address: 0x40023c10 + /// Control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Programming + PG: u1, + /// Sector Erase + SER: u1, + /// Mass Erase of sectors 0 to + /// 11 + MER: u1, + /// Sector number + SNB: u5, + /// Program size + PSIZE: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Mass Erase of sectors 12 to + /// 23 + MER1: u1, + /// Start + STRT: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// End of operation interrupt + /// enable + EOPIE: u1, + /// Error interrupt enable + ERRIE: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + /// Lock + LOCK: u1, + }), base_address + 0x10); + + /// address: 0x40023c14 + /// Flash option control register + pub const OPTCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Option lock + OPTLOCK: u1, + /// Option start + OPTSTRT: u1, + /// BOR reset Level + BOR_LEV: u2, + reserved0: u1, + /// WDG_SW User option bytes + WDG_SW: u1, + /// nRST_STOP User option + /// bytes + nRST_STOP: u1, + /// nRST_STDBY User option + /// bytes + nRST_STDBY: u1, + /// Read protect + RDP: u8, + /// Not write protect + nWRP: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x14); + + /// address: 0x40023c18 + /// Flash option control register + /// 1 + pub const OPTCR1 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Not write protect + nWRP: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x18); + }; + + /// External interrupt/event + /// controller + pub const EXTI = struct { + pub const base_address = 0x40013c00; + + /// address: 0x40013c00 + /// Interrupt mask register + /// (EXTI_IMR) + pub const IMR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt Mask on line 0 + MR0: u1, + /// Interrupt Mask on line 1 + MR1: u1, + /// Interrupt Mask on line 2 + MR2: u1, + /// Interrupt Mask on line 3 + MR3: u1, + /// Interrupt Mask on line 4 + MR4: u1, + /// Interrupt Mask on line 5 + MR5: u1, + /// Interrupt Mask on line 6 + MR6: u1, + /// Interrupt Mask on line 7 + MR7: u1, + /// Interrupt Mask on line 8 + MR8: u1, + /// Interrupt Mask on line 9 + MR9: u1, + /// Interrupt Mask on line 10 + MR10: u1, + /// Interrupt Mask on line 11 + MR11: u1, + /// Interrupt Mask on line 12 + MR12: u1, + /// Interrupt Mask on line 13 + MR13: u1, + /// Interrupt Mask on line 14 + MR14: u1, + /// Interrupt Mask on line 15 + MR15: u1, + /// Interrupt Mask on line 16 + MR16: u1, + /// Interrupt Mask on line 17 + MR17: u1, + /// Interrupt Mask on line 18 + MR18: u1, + /// Interrupt Mask on line 19 + MR19: u1, + /// Interrupt Mask on line 20 + MR20: u1, + /// Interrupt Mask on line 21 + MR21: u1, + /// Interrupt Mask on line 22 + MR22: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x0); + + /// address: 0x40013c04 + /// Event mask register (EXTI_EMR) + pub const EMR = @intToPtr(*volatile Mmio(32, packed struct { + /// Event Mask on line 0 + MR0: u1, + /// Event Mask on line 1 + MR1: u1, + /// Event Mask on line 2 + MR2: u1, + /// Event Mask on line 3 + MR3: u1, + /// Event Mask on line 4 + MR4: u1, + /// Event Mask on line 5 + MR5: u1, + /// Event Mask on line 6 + MR6: u1, + /// Event Mask on line 7 + MR7: u1, + /// Event Mask on line 8 + MR8: u1, + /// Event Mask on line 9 + MR9: u1, + /// Event Mask on line 10 + MR10: u1, + /// Event Mask on line 11 + MR11: u1, + /// Event Mask on line 12 + MR12: u1, + /// Event Mask on line 13 + MR13: u1, + /// Event Mask on line 14 + MR14: u1, + /// Event Mask on line 15 + MR15: u1, + /// Event Mask on line 16 + MR16: u1, + /// Event Mask on line 17 + MR17: u1, + /// Event Mask on line 18 + MR18: u1, + /// Event Mask on line 19 + MR19: u1, + /// Event Mask on line 20 + MR20: u1, + /// Event Mask on line 21 + MR21: u1, + /// Event Mask on line 22 + MR22: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x4); + + /// address: 0x40013c08 + /// Rising Trigger selection register + /// (EXTI_RTSR) + pub const RTSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rising trigger event configuration of + /// line 0 + TR0: u1, + /// Rising trigger event configuration of + /// line 1 + TR1: u1, + /// Rising trigger event configuration of + /// line 2 + TR2: u1, + /// Rising trigger event configuration of + /// line 3 + TR3: u1, + /// Rising trigger event configuration of + /// line 4 + TR4: u1, + /// Rising trigger event configuration of + /// line 5 + TR5: u1, + /// Rising trigger event configuration of + /// line 6 + TR6: u1, + /// Rising trigger event configuration of + /// line 7 + TR7: u1, + /// Rising trigger event configuration of + /// line 8 + TR8: u1, + /// Rising trigger event configuration of + /// line 9 + TR9: u1, + /// Rising trigger event configuration of + /// line 10 + TR10: u1, + /// Rising trigger event configuration of + /// line 11 + TR11: u1, + /// Rising trigger event configuration of + /// line 12 + TR12: u1, + /// Rising trigger event configuration of + /// line 13 + TR13: u1, + /// Rising trigger event configuration of + /// line 14 + TR14: u1, + /// Rising trigger event configuration of + /// line 15 + TR15: u1, + /// Rising trigger event configuration of + /// line 16 + TR16: u1, + /// Rising trigger event configuration of + /// line 17 + TR17: u1, + /// Rising trigger event configuration of + /// line 18 + TR18: u1, + /// Rising trigger event configuration of + /// line 19 + TR19: u1, + /// Rising trigger event configuration of + /// line 20 + TR20: u1, + /// Rising trigger event configuration of + /// line 21 + TR21: u1, + /// Rising trigger event configuration of + /// line 22 + TR22: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x8); + + /// address: 0x40013c0c + /// Falling Trigger selection register + /// (EXTI_FTSR) + pub const FTSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Falling trigger event configuration of + /// line 0 + TR0: u1, + /// Falling trigger event configuration of + /// line 1 + TR1: u1, + /// Falling trigger event configuration of + /// line 2 + TR2: u1, + /// Falling trigger event configuration of + /// line 3 + TR3: u1, + /// Falling trigger event configuration of + /// line 4 + TR4: u1, + /// Falling trigger event configuration of + /// line 5 + TR5: u1, + /// Falling trigger event configuration of + /// line 6 + TR6: u1, + /// Falling trigger event configuration of + /// line 7 + TR7: u1, + /// Falling trigger event configuration of + /// line 8 + TR8: u1, + /// Falling trigger event configuration of + /// line 9 + TR9: u1, + /// Falling trigger event configuration of + /// line 10 + TR10: u1, + /// Falling trigger event configuration of + /// line 11 + TR11: u1, + /// Falling trigger event configuration of + /// line 12 + TR12: u1, + /// Falling trigger event configuration of + /// line 13 + TR13: u1, + /// Falling trigger event configuration of + /// line 14 + TR14: u1, + /// Falling trigger event configuration of + /// line 15 + TR15: u1, + /// Falling trigger event configuration of + /// line 16 + TR16: u1, + /// Falling trigger event configuration of + /// line 17 + TR17: u1, + /// Falling trigger event configuration of + /// line 18 + TR18: u1, + /// Falling trigger event configuration of + /// line 19 + TR19: u1, + /// Falling trigger event configuration of + /// line 20 + TR20: u1, + /// Falling trigger event configuration of + /// line 21 + TR21: u1, + /// Falling trigger event configuration of + /// line 22 + TR22: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0xc); + + /// address: 0x40013c10 + /// Software interrupt event register + /// (EXTI_SWIER) + pub const SWIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Interrupt on line + /// 0 + SWIER0: u1, + /// Software Interrupt on line + /// 1 + SWIER1: u1, + /// Software Interrupt on line + /// 2 + SWIER2: u1, + /// Software Interrupt on line + /// 3 + SWIER3: u1, + /// Software Interrupt on line + /// 4 + SWIER4: u1, + /// Software Interrupt on line + /// 5 + SWIER5: u1, + /// Software Interrupt on line + /// 6 + SWIER6: u1, + /// Software Interrupt on line + /// 7 + SWIER7: u1, + /// Software Interrupt on line + /// 8 + SWIER8: u1, + /// Software Interrupt on line + /// 9 + SWIER9: u1, + /// Software Interrupt on line + /// 10 + SWIER10: u1, + /// Software Interrupt on line + /// 11 + SWIER11: u1, + /// Software Interrupt on line + /// 12 + SWIER12: u1, + /// Software Interrupt on line + /// 13 + SWIER13: u1, + /// Software Interrupt on line + /// 14 + SWIER14: u1, + /// Software Interrupt on line + /// 15 + SWIER15: u1, + /// Software Interrupt on line + /// 16 + SWIER16: u1, + /// Software Interrupt on line + /// 17 + SWIER17: u1, + /// Software Interrupt on line + /// 18 + SWIER18: u1, + /// Software Interrupt on line + /// 19 + SWIER19: u1, + /// Software Interrupt on line + /// 20 + SWIER20: u1, + /// Software Interrupt on line + /// 21 + SWIER21: u1, + /// Software Interrupt on line + /// 22 + SWIER22: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x10); + + /// address: 0x40013c14 + /// Pending register (EXTI_PR) + pub const PR = @intToPtr(*volatile Mmio(32, packed struct { + /// Pending bit 0 + PR0: u1, + /// Pending bit 1 + PR1: u1, + /// Pending bit 2 + PR2: u1, + /// Pending bit 3 + PR3: u1, + /// Pending bit 4 + PR4: u1, + /// Pending bit 5 + PR5: u1, + /// Pending bit 6 + PR6: u1, + /// Pending bit 7 + PR7: u1, + /// Pending bit 8 + PR8: u1, + /// Pending bit 9 + PR9: u1, + /// Pending bit 10 + PR10: u1, + /// Pending bit 11 + PR11: u1, + /// Pending bit 12 + PR12: u1, + /// Pending bit 13 + PR13: u1, + /// Pending bit 14 + PR14: u1, + /// Pending bit 15 + PR15: u1, + /// Pending bit 16 + PR16: u1, + /// Pending bit 17 + PR17: u1, + /// Pending bit 18 + PR18: u1, + /// Pending bit 19 + PR19: u1, + /// Pending bit 20 + PR20: u1, + /// Pending bit 21 + PR21: u1, + /// Pending bit 22 + PR22: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x14); + }; + + /// USB on the go high speed + pub const OTG_HS_GLOBAL = struct { + pub const base_address = 0x40040000; + + /// address: 0x40040000 + /// OTG_HS control and status + /// register + pub const OTG_HS_GOTGCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Session request success + SRQSCS: u1, + /// Session request + SRQ: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Host negotiation success + HNGSCS: u1, + /// HNP request + HNPRQ: u1, + /// Host set HNP enable + HSHNPEN: u1, + /// Device HNP enabled + DHNPEN: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Connector ID status + CIDSTS: u1, + /// Long/short debounce time + DBCT: u1, + /// A-session valid + ASVLD: u1, + /// B-session valid + BSVLD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x0); + + /// address: 0x40040004 + /// OTG_HS interrupt register + pub const OTG_HS_GOTGINT = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + /// Session end detected + SEDET: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Session request success status + /// change + SRSSCHG: u1, + /// Host negotiation success status + /// change + HNSSCHG: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Host negotiation detected + HNGDET: u1, + /// A-device timeout change + ADTOCHG: u1, + /// Debounce done + DBCDNE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x4); + + /// address: 0x40040008 + /// OTG_HS AHB configuration + /// register + pub const OTG_HS_GAHBCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Global interrupt mask + GINT: u1, + /// Burst length/type + HBSTLEN: u4, + /// DMA enable + DMAEN: u1, + reserved0: u1, + /// TxFIFO empty level + TXFELVL: u1, + /// Periodic TxFIFO empty + /// level + PTXFELVL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x4004000c + /// OTG_HS USB configuration + /// register + pub const OTG_HS_GUSBCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// FS timeout calibration + TOCAL: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// USB 2.0 high-speed ULPI PHY or USB 1.1 + /// full-speed serial transceiver select + PHYSEL: u1, + reserved3: u1, + /// SRP-capable + SRPCAP: u1, + /// HNP-capable + HNPCAP: u1, + /// USB turnaround time + TRDT: u4, + reserved4: u1, + /// PHY Low-power clock select + PHYLPCS: u1, + reserved5: u1, + /// ULPI FS/LS select + ULPIFSLS: u1, + /// ULPI Auto-resume + ULPIAR: u1, + /// ULPI Clock SuspendM + ULPICSM: u1, + /// ULPI External VBUS Drive + ULPIEVBUSD: u1, + /// ULPI external VBUS + /// indicator + ULPIEVBUSI: u1, + /// TermSel DLine pulsing + /// selection + TSDPS: u1, + /// Indicator complement + PCCI: u1, + /// Indicator pass through + PTCI: u1, + /// ULPI interface protect + /// disable + ULPIIPD: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Forced host mode + FHMOD: u1, + /// Forced peripheral mode + FDMOD: u1, + /// Corrupt Tx packet + CTXPKT: u1, + }), base_address + 0xc); + + /// address: 0x40040010 + /// OTG_HS reset register + pub const OTG_HS_GRSTCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Core soft reset + CSRST: u1, + /// HCLK soft reset + HSRST: u1, + /// Host frame counter reset + FCRST: u1, + reserved0: u1, + /// RxFIFO flush + RXFFLSH: u1, + /// TxFIFO flush + TXFFLSH: u1, + /// TxFIFO number + TXFNUM: u5, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + /// DMA request signal + DMAREQ: u1, + /// AHB master idle + AHBIDL: u1, + }), base_address + 0x10); + + /// address: 0x40040014 + /// OTG_HS core interrupt register + pub const OTG_HS_GINTSTS = @intToPtr(*volatile Mmio(32, packed struct { + /// Current mode of operation + CMOD: u1, + /// Mode mismatch interrupt + MMIS: u1, + /// OTG interrupt + OTGINT: u1, + /// Start of frame + SOF: u1, + /// RxFIFO nonempty + RXFLVL: u1, + /// Nonperiodic TxFIFO empty + NPTXFE: u1, + /// Global IN nonperiodic NAK + /// effective + GINAKEFF: u1, + /// Global OUT NAK effective + BOUTNAKEFF: u1, + reserved0: u1, + reserved1: u1, + /// Early suspend + ESUSP: u1, + /// USB suspend + USBSUSP: u1, + /// USB reset + USBRST: u1, + /// Enumeration done + ENUMDNE: u1, + /// Isochronous OUT packet dropped + /// interrupt + ISOODRP: u1, + /// End of periodic frame + /// interrupt + EOPF: u1, + reserved2: u1, + reserved3: u1, + /// IN endpoint interrupt + IEPINT: u1, + /// OUT endpoint interrupt + OEPINT: u1, + /// Incomplete isochronous IN + /// transfer + IISOIXFR: u1, + /// Incomplete periodic + /// transfer + PXFR_INCOMPISOOUT: u1, + /// Data fetch suspended + DATAFSUSP: u1, + reserved4: u1, + /// Host port interrupt + HPRTINT: u1, + /// Host channels interrupt + HCINT: u1, + /// Periodic TxFIFO empty + PTXFE: u1, + reserved5: u1, + /// Connector ID status change + CIDSCHG: u1, + /// Disconnect detected + /// interrupt + DISCINT: u1, + /// Session request/new session detected + /// interrupt + SRQINT: u1, + /// Resume/remote wakeup detected + /// interrupt + WKUINT: u1, + }), base_address + 0x14); + + /// address: 0x40040018 + /// OTG_HS interrupt mask register + pub const OTG_HS_GINTMSK = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Mode mismatch interrupt + /// mask + MMISM: u1, + /// OTG interrupt mask + OTGINT: u1, + /// Start of frame mask + SOFM: u1, + /// Receive FIFO nonempty mask + RXFLVLM: u1, + /// Nonperiodic TxFIFO empty + /// mask + NPTXFEM: u1, + /// Global nonperiodic IN NAK effective + /// mask + GINAKEFFM: u1, + /// Global OUT NAK effective + /// mask + GONAKEFFM: u1, + reserved1: u1, + reserved2: u1, + /// Early suspend mask + ESUSPM: u1, + /// USB suspend mask + USBSUSPM: u1, + /// USB reset mask + USBRST: u1, + /// Enumeration done mask + ENUMDNEM: u1, + /// Isochronous OUT packet dropped interrupt + /// mask + ISOODRPM: u1, + /// End of periodic frame interrupt + /// mask + EOPFM: u1, + reserved3: u1, + /// Endpoint mismatch interrupt + /// mask + EPMISM: u1, + /// IN endpoints interrupt + /// mask + IEPINT: u1, + /// OUT endpoints interrupt + /// mask + OEPINT: u1, + /// Incomplete isochronous IN transfer + /// mask + IISOIXFRM: u1, + /// Incomplete periodic transfer + /// mask + PXFRM_IISOOXFRM: u1, + /// Data fetch suspended mask + FSUSPM: u1, + reserved4: u1, + /// Host port interrupt mask + PRTIM: u1, + /// Host channels interrupt + /// mask + HCIM: u1, + /// Periodic TxFIFO empty mask + PTXFEM: u1, + reserved5: u1, + /// Connector ID status change + /// mask + CIDSCHGM: u1, + /// Disconnect detected interrupt + /// mask + DISCINT: u1, + /// Session request/new session detected + /// interrupt mask + SRQIM: u1, + /// Resume/remote wakeup detected interrupt + /// mask + WUIM: u1, + }), base_address + 0x18); + + /// address: 0x4004001c + /// OTG_HS Receive status debug read register + /// (host mode) + pub const OTG_HS_GRXSTSR_Host = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel number + CHNUM: u4, + /// Byte count + BCNT: u11, + /// Data PID + DPID: u2, + /// Packet status + PKTSTS: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x1c); + + /// address: 0x40040020 + /// OTG_HS status read and pop register (host + /// mode) + pub const OTG_HS_GRXSTSP_Host = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel number + CHNUM: u4, + /// Byte count + BCNT: u11, + /// Data PID + DPID: u2, + /// Packet status + PKTSTS: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x20); + + /// address: 0x40040024 + /// OTG_HS Receive FIFO size + /// register + pub const OTG_HS_GRXFSIZ = @intToPtr(*volatile Mmio(32, packed struct { + /// RxFIFO depth + RXFD: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x24); + + /// address: 0x40040028 + /// OTG_HS nonperiodic transmit FIFO size + /// register (host mode) + pub const OTG_HS_GNPTXFSIZ_Host = @intToPtr(*volatile Mmio(32, packed struct { + /// Nonperiodic transmit RAM start + /// address + NPTXFSA: u16, + /// Nonperiodic TxFIFO depth + NPTXFD: u16, + }), base_address + 0x28); + + /// address: 0x40040028 + /// Endpoint 0 transmit FIFO size (peripheral + /// mode) + pub const OTG_HS_TX0FSIZ_Peripheral = @intToPtr(*volatile Mmio(32, packed struct { + /// Endpoint 0 transmit RAM start + /// address + TX0FSA: u16, + /// Endpoint 0 TxFIFO depth + TX0FD: u16, + }), base_address + 0x28); + + /// address: 0x4004002c + /// OTG_HS nonperiodic transmit FIFO/queue + /// status register + pub const OTG_HS_GNPTXSTS = @intToPtr(*volatile Mmio(32, packed struct { + /// Nonperiodic TxFIFO space + /// available + NPTXFSAV: u16, + /// Nonperiodic transmit request queue space + /// available + NPTQXSAV: u8, + /// Top of the nonperiodic transmit request + /// queue + NPTXQTOP: u7, + padding0: u1, + }), base_address + 0x2c); + + /// address: 0x40040038 + /// OTG_HS general core configuration + /// register + pub const OTG_HS_GCCFG = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Power down + PWRDWN: u1, + /// Enable I2C bus connection for the + /// external I2C PHY interface + I2CPADEN: u1, + /// Enable the VBUS sensing + /// device + VBUSASEN: u1, + /// Enable the VBUS sensing + /// device + VBUSBSEN: u1, + /// SOF output enable + SOFOUTEN: u1, + /// VBUS sensing disable + /// option + NOVBUSSENS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x38); + + /// address: 0x4004003c + /// OTG_HS core ID register + pub const OTG_HS_CID = @intToPtr(*volatile Mmio(32, packed struct { + /// Product ID field + PRODUCT_ID: u32, + }), base_address + 0x3c); + + /// address: 0x40040100 + /// OTG_HS Host periodic transmit FIFO size + /// register + pub const OTG_HS_HPTXFSIZ = @intToPtr(*volatile Mmio(32, packed struct { + /// Host periodic TxFIFO start + /// address + PTXSA: u16, + /// Host periodic TxFIFO depth + PTXFD: u16, + }), base_address + 0x100); + + /// address: 0x40040104 + /// OTG_HS device IN endpoint transmit FIFO size + /// register + pub const OTG_HS_DIEPTXF1 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFOx transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x104); + + /// address: 0x40040108 + /// OTG_HS device IN endpoint transmit FIFO size + /// register + pub const OTG_HS_DIEPTXF2 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFOx transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x108); + + /// address: 0x4004011c + /// OTG_HS device IN endpoint transmit FIFO size + /// register + pub const OTG_HS_DIEPTXF3 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFOx transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x11c); + + /// address: 0x40040120 + /// OTG_HS device IN endpoint transmit FIFO size + /// register + pub const OTG_HS_DIEPTXF4 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFOx transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x120); + + /// address: 0x40040124 + /// OTG_HS device IN endpoint transmit FIFO size + /// register + pub const OTG_HS_DIEPTXF5 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFOx transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x124); + + /// address: 0x40040128 + /// OTG_HS device IN endpoint transmit FIFO size + /// register + pub const OTG_HS_DIEPTXF6 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFOx transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x128); + + /// address: 0x4004012c + /// OTG_HS device IN endpoint transmit FIFO size + /// register + pub const OTG_HS_DIEPTXF7 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFOx transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x12c); + + /// address: 0x4004001c + /// OTG_HS Receive status debug read register + /// (peripheral mode mode) + pub const OTG_HS_GRXSTSR_Peripheral = @intToPtr(*volatile Mmio(32, packed struct { + /// Endpoint number + EPNUM: u4, + /// Byte count + BCNT: u11, + /// Data PID + DPID: u2, + /// Packet status + PKTSTS: u4, + /// Frame number + FRMNUM: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x1c); + + /// address: 0x40040020 + /// OTG_HS status read and pop register + /// (peripheral mode) + pub const OTG_HS_GRXSTSP_Peripheral = @intToPtr(*volatile Mmio(32, packed struct { + /// Endpoint number + EPNUM: u4, + /// Byte count + BCNT: u11, + /// Data PID + DPID: u2, + /// Packet status + PKTSTS: u4, + /// Frame number + FRMNUM: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x20); + }; + + /// USB on the go high speed + pub const OTG_HS_HOST = struct { + pub const base_address = 0x40040400; + + /// address: 0x40040400 + /// OTG_HS host configuration + /// register + pub const OTG_HS_HCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// FS/LS PHY clock select + FSLSPCS: u2, + /// FS- and LS-only support + FSLSS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x0); + + /// address: 0x40040404 + /// OTG_HS Host frame interval + /// register + pub const OTG_HS_HFIR = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame interval + FRIVL: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40040408 + /// OTG_HS host frame number/frame time + /// remaining register + pub const OTG_HS_HFNUM = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame number + FRNUM: u16, + /// Frame time remaining + FTREM: u16, + }), base_address + 0x8); + + /// address: 0x40040410 + /// OTG_HS_Host periodic transmit FIFO/queue + /// status register + pub const OTG_HS_HPTXSTS = @intToPtr(*volatile Mmio(32, packed struct { + /// Periodic transmit data FIFO space + /// available + PTXFSAVL: u16, + /// Periodic transmit request queue space + /// available + PTXQSAV: u8, + /// Top of the periodic transmit request + /// queue + PTXQTOP: u8, + }), base_address + 0x10); + + /// address: 0x40040414 + /// OTG_HS Host all channels interrupt + /// register + pub const OTG_HS_HAINT = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel interrupts + HAINT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40040418 + /// OTG_HS host all channels interrupt mask + /// register + pub const OTG_HS_HAINTMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel interrupt mask + HAINTM: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40040440 + /// OTG_HS host port control and status + /// register + pub const OTG_HS_HPRT = @intToPtr(*volatile Mmio(32, packed struct { + /// Port connect status + PCSTS: u1, + /// Port connect detected + PCDET: u1, + /// Port enable + PENA: u1, + /// Port enable/disable change + PENCHNG: u1, + /// Port overcurrent active + POCA: u1, + /// Port overcurrent change + POCCHNG: u1, + /// Port resume + PRES: u1, + /// Port suspend + PSUSP: u1, + /// Port reset + PRST: u1, + reserved0: u1, + /// Port line status + PLSTS: u2, + /// Port power + PPWR: u1, + /// Port test control + PTCTL: u4, + /// Port speed + PSPD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x40); + + /// address: 0x40040500 + /// OTG_HS host channel-0 characteristics + /// register + pub const OTG_HS_HCCHAR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x100); + + /// address: 0x40040520 + /// OTG_HS host channel-1 characteristics + /// register + pub const OTG_HS_HCCHAR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x120); + + /// address: 0x40040540 + /// OTG_HS host channel-2 characteristics + /// register + pub const OTG_HS_HCCHAR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x140); + + /// address: 0x40040560 + /// OTG_HS host channel-3 characteristics + /// register + pub const OTG_HS_HCCHAR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x160); + + /// address: 0x40040580 + /// OTG_HS host channel-4 characteristics + /// register + pub const OTG_HS_HCCHAR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x180); + + /// address: 0x400405a0 + /// OTG_HS host channel-5 characteristics + /// register + pub const OTG_HS_HCCHAR5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x1a0); + + /// address: 0x400405c0 + /// OTG_HS host channel-6 characteristics + /// register + pub const OTG_HS_HCCHAR6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x1c0); + + /// address: 0x400405e0 + /// OTG_HS host channel-7 characteristics + /// register + pub const OTG_HS_HCCHAR7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x1e0); + + /// address: 0x40040600 + /// OTG_HS host channel-8 characteristics + /// register + pub const OTG_HS_HCCHAR8 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x200); + + /// address: 0x40040620 + /// OTG_HS host channel-9 characteristics + /// register + pub const OTG_HS_HCCHAR9 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x220); + + /// address: 0x40040640 + /// OTG_HS host channel-10 characteristics + /// register + pub const OTG_HS_HCCHAR10 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x240); + + /// address: 0x40040660 + /// OTG_HS host channel-11 characteristics + /// register + pub const OTG_HS_HCCHAR11 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x260); + + /// address: 0x40040504 + /// OTG_HS host channel-0 split control + /// register + pub const OTG_HS_HCSPLT0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x104); + + /// address: 0x40040524 + /// OTG_HS host channel-1 split control + /// register + pub const OTG_HS_HCSPLT1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x124); + + /// address: 0x40040544 + /// OTG_HS host channel-2 split control + /// register + pub const OTG_HS_HCSPLT2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x144); + + /// address: 0x40040564 + /// OTG_HS host channel-3 split control + /// register + pub const OTG_HS_HCSPLT3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x164); + + /// address: 0x40040584 + /// OTG_HS host channel-4 split control + /// register + pub const OTG_HS_HCSPLT4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x184); + + /// address: 0x400405a4 + /// OTG_HS host channel-5 split control + /// register + pub const OTG_HS_HCSPLT5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x1a4); + + /// address: 0x400405c4 + /// OTG_HS host channel-6 split control + /// register + pub const OTG_HS_HCSPLT6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x1c4); + + /// address: 0x400405e4 + /// OTG_HS host channel-7 split control + /// register + pub const OTG_HS_HCSPLT7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x1e4); + + /// address: 0x40040604 + /// OTG_HS host channel-8 split control + /// register + pub const OTG_HS_HCSPLT8 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x204); + + /// address: 0x40040624 + /// OTG_HS host channel-9 split control + /// register + pub const OTG_HS_HCSPLT9 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x224); + + /// address: 0x40040644 + /// OTG_HS host channel-10 split control + /// register + pub const OTG_HS_HCSPLT10 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x244); + + /// address: 0x40040664 + /// OTG_HS host channel-11 split control + /// register + pub const OTG_HS_HCSPLT11 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x264); + + /// address: 0x40040508 + /// OTG_HS host channel-11 interrupt + /// register + pub const OTG_HS_HCINT0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x108); + + /// address: 0x40040528 + /// OTG_HS host channel-1 interrupt + /// register + pub const OTG_HS_HCINT1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x128); + + /// address: 0x40040548 + /// OTG_HS host channel-2 interrupt + /// register + pub const OTG_HS_HCINT2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x148); + + /// address: 0x40040568 + /// OTG_HS host channel-3 interrupt + /// register + pub const OTG_HS_HCINT3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x168); + + /// address: 0x40040588 + /// OTG_HS host channel-4 interrupt + /// register + pub const OTG_HS_HCINT4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x188); + + /// address: 0x400405a8 + /// OTG_HS host channel-5 interrupt + /// register + pub const OTG_HS_HCINT5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1a8); + + /// address: 0x400405c8 + /// OTG_HS host channel-6 interrupt + /// register + pub const OTG_HS_HCINT6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1c8); + + /// address: 0x400405e8 + /// OTG_HS host channel-7 interrupt + /// register + pub const OTG_HS_HCINT7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1e8); + + /// address: 0x40040608 + /// OTG_HS host channel-8 interrupt + /// register + pub const OTG_HS_HCINT8 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x208); + + /// address: 0x40040628 + /// OTG_HS host channel-9 interrupt + /// register + pub const OTG_HS_HCINT9 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x228); + + /// address: 0x40040648 + /// OTG_HS host channel-10 interrupt + /// register + pub const OTG_HS_HCINT10 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x248); + + /// address: 0x40040668 + /// OTG_HS host channel-11 interrupt + /// register + pub const OTG_HS_HCINT11 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x268); + + /// address: 0x4004050c + /// OTG_HS host channel-11 interrupt mask + /// register + pub const OTG_HS_HCINTMSK0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x10c); + + /// address: 0x4004052c + /// OTG_HS host channel-1 interrupt mask + /// register + pub const OTG_HS_HCINTMSK1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x12c); + + /// address: 0x4004054c + /// OTG_HS host channel-2 interrupt mask + /// register + pub const OTG_HS_HCINTMSK2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x14c); + + /// address: 0x4004056c + /// OTG_HS host channel-3 interrupt mask + /// register + pub const OTG_HS_HCINTMSK3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x16c); + + /// address: 0x4004058c + /// OTG_HS host channel-4 interrupt mask + /// register + pub const OTG_HS_HCINTMSK4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x18c); + + /// address: 0x400405ac + /// OTG_HS host channel-5 interrupt mask + /// register + pub const OTG_HS_HCINTMSK5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1ac); + + /// address: 0x400405cc + /// OTG_HS host channel-6 interrupt mask + /// register + pub const OTG_HS_HCINTMSK6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1cc); + + /// address: 0x400405ec + /// OTG_HS host channel-7 interrupt mask + /// register + pub const OTG_HS_HCINTMSK7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1ec); + + /// address: 0x4004060c + /// OTG_HS host channel-8 interrupt mask + /// register + pub const OTG_HS_HCINTMSK8 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x20c); + + /// address: 0x4004062c + /// OTG_HS host channel-9 interrupt mask + /// register + pub const OTG_HS_HCINTMSK9 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x22c); + + /// address: 0x4004064c + /// OTG_HS host channel-10 interrupt mask + /// register + pub const OTG_HS_HCINTMSK10 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x24c); + + /// address: 0x4004066c + /// OTG_HS host channel-11 interrupt mask + /// register + pub const OTG_HS_HCINTMSK11 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x26c); + + /// address: 0x40040510 + /// OTG_HS host channel-11 transfer size + /// register + pub const OTG_HS_HCTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x110); + + /// address: 0x40040530 + /// OTG_HS host channel-1 transfer size + /// register + pub const OTG_HS_HCTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x130); + + /// address: 0x40040550 + /// OTG_HS host channel-2 transfer size + /// register + pub const OTG_HS_HCTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x150); + + /// address: 0x40040570 + /// OTG_HS host channel-3 transfer size + /// register + pub const OTG_HS_HCTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x170); + + /// address: 0x40040590 + /// OTG_HS host channel-4 transfer size + /// register + pub const OTG_HS_HCTSIZ4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x190); + + /// address: 0x400405b0 + /// OTG_HS host channel-5 transfer size + /// register + pub const OTG_HS_HCTSIZ5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x1b0); + + /// address: 0x400405d0 + /// OTG_HS host channel-6 transfer size + /// register + pub const OTG_HS_HCTSIZ6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x1d0); + + /// address: 0x400405f0 + /// OTG_HS host channel-7 transfer size + /// register + pub const OTG_HS_HCTSIZ7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x1f0); + + /// address: 0x40040610 + /// OTG_HS host channel-8 transfer size + /// register + pub const OTG_HS_HCTSIZ8 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x210); + + /// address: 0x40040630 + /// OTG_HS host channel-9 transfer size + /// register + pub const OTG_HS_HCTSIZ9 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x230); + + /// address: 0x40040650 + /// OTG_HS host channel-10 transfer size + /// register + pub const OTG_HS_HCTSIZ10 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x250); + + /// address: 0x40040670 + /// OTG_HS host channel-11 transfer size + /// register + pub const OTG_HS_HCTSIZ11 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x270); + + /// address: 0x40040514 + /// OTG_HS host channel-0 DMA address + /// register + pub const OTG_HS_HCDMA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x114); + + /// address: 0x40040534 + /// OTG_HS host channel-1 DMA address + /// register + pub const OTG_HS_HCDMA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x134); + + /// address: 0x40040554 + /// OTG_HS host channel-2 DMA address + /// register + pub const OTG_HS_HCDMA2 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x154); + + /// address: 0x40040574 + /// OTG_HS host channel-3 DMA address + /// register + pub const OTG_HS_HCDMA3 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x174); + + /// address: 0x40040594 + /// OTG_HS host channel-4 DMA address + /// register + pub const OTG_HS_HCDMA4 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x194); + + /// address: 0x400405b4 + /// OTG_HS host channel-5 DMA address + /// register + pub const OTG_HS_HCDMA5 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x1b4); + + /// address: 0x400405d4 + /// OTG_HS host channel-6 DMA address + /// register + pub const OTG_HS_HCDMA6 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x1d4); + + /// address: 0x400405f4 + /// OTG_HS host channel-7 DMA address + /// register + pub const OTG_HS_HCDMA7 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x1f4); + + /// address: 0x40040614 + /// OTG_HS host channel-8 DMA address + /// register + pub const OTG_HS_HCDMA8 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x214); + + /// address: 0x40040634 + /// OTG_HS host channel-9 DMA address + /// register + pub const OTG_HS_HCDMA9 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x234); + + /// address: 0x40040654 + /// OTG_HS host channel-10 DMA address + /// register + pub const OTG_HS_HCDMA10 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x254); + + /// address: 0x40040674 + /// OTG_HS host channel-11 DMA address + /// register + pub const OTG_HS_HCDMA11 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x274); + }; + + /// USB on the go high speed + pub const OTG_HS_DEVICE = struct { + pub const base_address = 0x40040800; + + /// address: 0x40040800 + /// OTG_HS device configuration + /// register + pub const OTG_HS_DCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Device speed + DSPD: u2, + /// Nonzero-length status OUT + /// handshake + NZLSOHSK: u1, + reserved0: u1, + /// Device address + DAD: u7, + /// Periodic (micro)frame + /// interval + PFIVL: u2, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Periodic scheduling + /// interval + PERSCHIVL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x0); + + /// address: 0x40040804 + /// OTG_HS device control register + pub const OTG_HS_DCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Remote wakeup signaling + RWUSIG: u1, + /// Soft disconnect + SDIS: u1, + /// Global IN NAK status + GINSTS: u1, + /// Global OUT NAK status + GONSTS: u1, + /// Test control + TCTL: u3, + /// Set global IN NAK + SGINAK: u1, + /// Clear global IN NAK + CGINAK: u1, + /// Set global OUT NAK + SGONAK: u1, + /// Clear global OUT NAK + CGONAK: u1, + /// Power-on programming done + POPRGDNE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x4); + + /// address: 0x40040808 + /// OTG_HS device status register + pub const OTG_HS_DSTS = @intToPtr(*volatile Mmio(32, packed struct { + /// Suspend status + SUSPSTS: u1, + /// Enumerated speed + ENUMSPD: u2, + /// Erratic error + EERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Frame number of the received + /// SOF + FNSOF: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x8); + + /// address: 0x40040810 + /// OTG_HS device IN endpoint common interrupt + /// mask register + pub const OTG_HS_DIEPMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed interrupt + /// mask + XFRCM: u1, + /// Endpoint disabled interrupt + /// mask + EPDM: u1, + reserved0: u1, + /// Timeout condition mask (nonisochronous + /// endpoints) + TOM: u1, + /// IN token received when TxFIFO empty + /// mask + ITTXFEMSK: u1, + /// IN token received with EP mismatch + /// mask + INEPNMM: u1, + /// IN endpoint NAK effective + /// mask + INEPNEM: u1, + reserved1: u1, + /// FIFO underrun mask + TXFURM: u1, + /// BNA interrupt mask + BIM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x10); + + /// address: 0x40040814 + /// OTG_HS device OUT endpoint common interrupt + /// mask register + pub const OTG_HS_DOEPMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed interrupt + /// mask + XFRCM: u1, + /// Endpoint disabled interrupt + /// mask + EPDM: u1, + reserved0: u1, + /// SETUP phase done mask + STUPM: u1, + /// OUT token received when endpoint + /// disabled mask + OTEPDM: u1, + reserved1: u1, + /// Back-to-back SETUP packets received + /// mask + B2BSTUP: u1, + reserved2: u1, + /// OUT packet error mask + OPEM: u1, + /// BNA interrupt mask + BOIM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x14); + + /// address: 0x40040818 + /// OTG_HS device all endpoints interrupt + /// register + pub const OTG_HS_DAINT = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint interrupt bits + IEPINT: u16, + /// OUT endpoint interrupt + /// bits + OEPINT: u16, + }), base_address + 0x18); + + /// address: 0x4004081c + /// OTG_HS all endpoints interrupt mask + /// register + pub const OTG_HS_DAINTMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// IN EP interrupt mask bits + IEPM: u16, + /// OUT EP interrupt mask bits + OEPM: u16, + }), base_address + 0x1c); + + /// address: 0x40040828 + /// OTG_HS device VBUS discharge time + /// register + pub const OTG_HS_DVBUSDIS = @intToPtr(*volatile Mmio(32, packed struct { + /// Device VBUS discharge time + VBUSDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + + /// address: 0x4004082c + /// OTG_HS device VBUS pulsing time + /// register + pub const OTG_HS_DVBUSPULSE = @intToPtr(*volatile Mmio(32, packed struct { + /// Device VBUS pulsing time + DVBUSP: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x2c); + + /// address: 0x40040830 + /// OTG_HS Device threshold control + /// register + pub const OTG_HS_DTHRCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Nonisochronous IN endpoints threshold + /// enable + NONISOTHREN: u1, + /// ISO IN endpoint threshold + /// enable + ISOTHREN: u1, + /// Transmit threshold length + TXTHRLEN: u9, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Receive threshold enable + RXTHREN: u1, + /// Receive threshold length + RXTHRLEN: u9, + reserved5: u1, + /// Arbiter parking enable + ARPEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x30); + + /// address: 0x40040834 + /// OTG_HS device IN endpoint FIFO empty + /// interrupt mask register + pub const OTG_HS_DIEPEMPMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// IN EP Tx FIFO empty interrupt mask + /// bits + INEPTXFEM: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x34); + + /// address: 0x40040838 + /// OTG_HS device each endpoint interrupt + /// register + pub const OTG_HS_DEACHINT = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// IN endpoint 1interrupt bit + IEP1INT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// OUT endpoint 1 interrupt + /// bit + OEP1INT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x38); + + /// address: 0x4004083c + /// OTG_HS device each endpoint interrupt + /// register mask + pub const OTG_HS_DEACHINTMSK = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// IN Endpoint 1 interrupt mask + /// bit + IEP1INTM: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// OUT Endpoint 1 interrupt mask + /// bit + OEP1INTM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x3c); + + /// address: 0x40040840 + /// OTG_HS device each in endpoint-1 interrupt + /// register + pub const OTG_HS_DIEPEACHMSK1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed interrupt + /// mask + XFRCM: u1, + /// Endpoint disabled interrupt + /// mask + EPDM: u1, + reserved0: u1, + /// Timeout condition mask (nonisochronous + /// endpoints) + TOM: u1, + /// IN token received when TxFIFO empty + /// mask + ITTXFEMSK: u1, + /// IN token received with EP mismatch + /// mask + INEPNMM: u1, + /// IN endpoint NAK effective + /// mask + INEPNEM: u1, + reserved1: u1, + /// FIFO underrun mask + TXFURM: u1, + /// BNA interrupt mask + BIM: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// NAK interrupt mask + NAKM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x40); + + /// address: 0x40040880 + /// OTG_HS device each OUT endpoint-1 interrupt + /// register + pub const OTG_HS_DOEPEACHMSK1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed interrupt + /// mask + XFRCM: u1, + /// Endpoint disabled interrupt + /// mask + EPDM: u1, + reserved0: u1, + /// Timeout condition mask + TOM: u1, + /// IN token received when TxFIFO empty + /// mask + ITTXFEMSK: u1, + /// IN token received with EP mismatch + /// mask + INEPNMM: u1, + /// IN endpoint NAK effective + /// mask + INEPNEM: u1, + reserved1: u1, + /// OUT packet error mask + TXFURM: u1, + /// BNA interrupt mask + BIM: u1, + reserved2: u1, + reserved3: u1, + /// Bubble error interrupt + /// mask + BERRM: u1, + /// NAK interrupt mask + NAKM: u1, + /// NYET interrupt mask + NYETM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x80); + + /// address: 0x40040900 + /// OTG device endpoint-0 control + /// register + pub const OTG_HS_DIEPCTL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved4: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x100); + + /// address: 0x40040920 + /// OTG device endpoint-1 control + /// register + pub const OTG_HS_DIEPCTL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved4: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x120); + + /// address: 0x40040940 + /// OTG device endpoint-2 control + /// register + pub const OTG_HS_DIEPCTL2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved4: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x140); + + /// address: 0x40040960 + /// OTG device endpoint-3 control + /// register + pub const OTG_HS_DIEPCTL3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved4: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x160); + + /// address: 0x40040980 + /// OTG device endpoint-4 control + /// register + pub const OTG_HS_DIEPCTL4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved4: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x180); + + /// address: 0x400409a0 + /// OTG device endpoint-5 control + /// register + pub const OTG_HS_DIEPCTL5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved4: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x1a0); + + /// address: 0x400409c0 + /// OTG device endpoint-6 control + /// register + pub const OTG_HS_DIEPCTL6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved4: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x1c0); + + /// address: 0x400409e0 + /// OTG device endpoint-7 control + /// register + pub const OTG_HS_DIEPCTL7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved4: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x1e0); + + /// address: 0x40040908 + /// OTG device endpoint-0 interrupt + /// register + pub const OTG_HS_DIEPINT0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is + /// empty + ITTXFE: u1, + reserved1: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available + /// interrupt + BNA: u1, + reserved2: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x108); + + /// address: 0x40040928 + /// OTG device endpoint-1 interrupt + /// register + pub const OTG_HS_DIEPINT1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is + /// empty + ITTXFE: u1, + reserved1: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available + /// interrupt + BNA: u1, + reserved2: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x128); + + /// address: 0x40040948 + /// OTG device endpoint-2 interrupt + /// register + pub const OTG_HS_DIEPINT2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is + /// empty + ITTXFE: u1, + reserved1: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available + /// interrupt + BNA: u1, + reserved2: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x148); + + /// address: 0x40040968 + /// OTG device endpoint-3 interrupt + /// register + pub const OTG_HS_DIEPINT3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is + /// empty + ITTXFE: u1, + reserved1: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available + /// interrupt + BNA: u1, + reserved2: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x168); + + /// address: 0x40040988 + /// OTG device endpoint-4 interrupt + /// register + pub const OTG_HS_DIEPINT4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is + /// empty + ITTXFE: u1, + reserved1: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available + /// interrupt + BNA: u1, + reserved2: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x188); + + /// address: 0x400409a8 + /// OTG device endpoint-5 interrupt + /// register + pub const OTG_HS_DIEPINT5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is + /// empty + ITTXFE: u1, + reserved1: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available + /// interrupt + BNA: u1, + reserved2: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x1a8); + + /// address: 0x400409c8 + /// OTG device endpoint-6 interrupt + /// register + pub const OTG_HS_DIEPINT6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is + /// empty + ITTXFE: u1, + reserved1: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available + /// interrupt + BNA: u1, + reserved2: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x1c8); + + /// address: 0x400409e8 + /// OTG device endpoint-7 interrupt + /// register + pub const OTG_HS_DIEPINT7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is + /// empty + ITTXFE: u1, + reserved1: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available + /// interrupt + BNA: u1, + reserved2: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x1e8); + + /// address: 0x40040910 + /// OTG_HS device IN endpoint 0 transfer size + /// register + pub const OTG_HS_DIEPTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u7, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Packet count + PKTCNT: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x110); + + /// address: 0x40040914 + /// OTG_HS device endpoint-1 DMA address + /// register + pub const OTG_HS_DIEPDMA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x114); + + /// address: 0x40040934 + /// OTG_HS device endpoint-2 DMA address + /// register + pub const OTG_HS_DIEPDMA2 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x134); + + /// address: 0x40040954 + /// OTG_HS device endpoint-3 DMA address + /// register + pub const OTG_HS_DIEPDMA3 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x154); + + /// address: 0x40040974 + /// OTG_HS device endpoint-4 DMA address + /// register + pub const OTG_HS_DIEPDMA4 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x174); + + /// address: 0x40040994 + /// OTG_HS device endpoint-5 DMA address + /// register + pub const OTG_HS_DIEPDMA5 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x194); + + /// address: 0x40040918 + /// OTG_HS device IN endpoint transmit FIFO + /// status register + pub const OTG_HS_DTXFSTS0 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// avail + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x118); + + /// address: 0x40040938 + /// OTG_HS device IN endpoint transmit FIFO + /// status register + pub const OTG_HS_DTXFSTS1 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// avail + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x138); + + /// address: 0x40040958 + /// OTG_HS device IN endpoint transmit FIFO + /// status register + pub const OTG_HS_DTXFSTS2 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// avail + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x158); + + /// address: 0x40040978 + /// OTG_HS device IN endpoint transmit FIFO + /// status register + pub const OTG_HS_DTXFSTS3 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// avail + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x178); + + /// address: 0x40040998 + /// OTG_HS device IN endpoint transmit FIFO + /// status register + pub const OTG_HS_DTXFSTS4 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// avail + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x198); + + /// address: 0x400409b8 + /// OTG_HS device IN endpoint transmit FIFO + /// status register + pub const OTG_HS_DTXFSTS5 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// avail + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1b8); + + /// address: 0x40040930 + /// OTG_HS device endpoint transfer size + /// register + pub const OTG_HS_DIEPTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding0: u1, + }), base_address + 0x130); + + /// address: 0x40040950 + /// OTG_HS device endpoint transfer size + /// register + pub const OTG_HS_DIEPTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding0: u1, + }), base_address + 0x150); + + /// address: 0x40040970 + /// OTG_HS device endpoint transfer size + /// register + pub const OTG_HS_DIEPTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding0: u1, + }), base_address + 0x170); + + /// address: 0x40040990 + /// OTG_HS device endpoint transfer size + /// register + pub const OTG_HS_DIEPTSIZ4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding0: u1, + }), base_address + 0x190); + + /// address: 0x400409b0 + /// OTG_HS device endpoint transfer size + /// register + pub const OTG_HS_DIEPTSIZ5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding0: u1, + }), base_address + 0x1b0); + + /// address: 0x40040b00 + /// OTG_HS device control OUT endpoint 0 control + /// register + pub const OTG_HS_DOEPCTL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// USB active endpoint + USBAEP: u1, + reserved13: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + /// Snoop mode + SNPM: u1, + /// STALL handshake + Stall: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + reserved18: u1, + reserved19: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x300); + + /// address: 0x40040b20 + /// OTG device endpoint-1 control + /// register + pub const OTG_HS_DOEPCTL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even odd frame/Endpoint data + /// PID + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + /// Snoop mode + SNPM: u1, + /// STALL handshake + Stall: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID/Set even + /// frame + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x320); + + /// address: 0x40040b40 + /// OTG device endpoint-2 control + /// register + pub const OTG_HS_DOEPCTL2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even odd frame/Endpoint data + /// PID + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + /// Snoop mode + SNPM: u1, + /// STALL handshake + Stall: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID/Set even + /// frame + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x340); + + /// address: 0x40040b60 + /// OTG device endpoint-3 control + /// register + pub const OTG_HS_DOEPCTL3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even odd frame/Endpoint data + /// PID + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + /// Snoop mode + SNPM: u1, + /// STALL handshake + Stall: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID/Set even + /// frame + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x360); + + /// address: 0x40040b08 + /// OTG_HS device endpoint-0 interrupt + /// register + pub const OTG_HS_DOEPINT0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint + /// disabled + OTEPDIS: u1, + reserved1: u1, + /// Back-to-back SETUP packets + /// received + B2BSTUP: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// NYET interrupt + NYET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x308); + + /// address: 0x40040b28 + /// OTG_HS device endpoint-1 interrupt + /// register + pub const OTG_HS_DOEPINT1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint + /// disabled + OTEPDIS: u1, + reserved1: u1, + /// Back-to-back SETUP packets + /// received + B2BSTUP: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// NYET interrupt + NYET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x328); + + /// address: 0x40040b48 + /// OTG_HS device endpoint-2 interrupt + /// register + pub const OTG_HS_DOEPINT2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint + /// disabled + OTEPDIS: u1, + reserved1: u1, + /// Back-to-back SETUP packets + /// received + B2BSTUP: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// NYET interrupt + NYET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x348); + + /// address: 0x40040b68 + /// OTG_HS device endpoint-3 interrupt + /// register + pub const OTG_HS_DOEPINT3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint + /// disabled + OTEPDIS: u1, + reserved1: u1, + /// Back-to-back SETUP packets + /// received + B2BSTUP: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// NYET interrupt + NYET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x368); + + /// address: 0x40040b88 + /// OTG_HS device endpoint-4 interrupt + /// register + pub const OTG_HS_DOEPINT4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint + /// disabled + OTEPDIS: u1, + reserved1: u1, + /// Back-to-back SETUP packets + /// received + B2BSTUP: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// NYET interrupt + NYET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x388); + + /// address: 0x40040ba8 + /// OTG_HS device endpoint-5 interrupt + /// register + pub const OTG_HS_DOEPINT5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint + /// disabled + OTEPDIS: u1, + reserved1: u1, + /// Back-to-back SETUP packets + /// received + B2BSTUP: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// NYET interrupt + NYET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x3a8); + + /// address: 0x40040bc8 + /// OTG_HS device endpoint-6 interrupt + /// register + pub const OTG_HS_DOEPINT6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint + /// disabled + OTEPDIS: u1, + reserved1: u1, + /// Back-to-back SETUP packets + /// received + B2BSTUP: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// NYET interrupt + NYET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x3c8); + + /// address: 0x40040be8 + /// OTG_HS device endpoint-7 interrupt + /// register + pub const OTG_HS_DOEPINT7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint + /// disabled + OTEPDIS: u1, + reserved1: u1, + /// Back-to-back SETUP packets + /// received + B2BSTUP: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// NYET interrupt + NYET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x3e8); + + /// address: 0x40040b10 + /// OTG_HS device endpoint-1 transfer size + /// register + pub const OTG_HS_DOEPTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u7, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Packet count + PKTCNT: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + /// SETUP packet count + STUPCNT: u2, + padding0: u1, + }), base_address + 0x310); + + /// address: 0x40040b30 + /// OTG_HS device endpoint-2 transfer size + /// register + pub const OTG_HS_DOEPTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet + /// count + RXDPID_STUPCNT: u2, + padding0: u1, + }), base_address + 0x330); + + /// address: 0x40040b50 + /// OTG_HS device endpoint-3 transfer size + /// register + pub const OTG_HS_DOEPTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet + /// count + RXDPID_STUPCNT: u2, + padding0: u1, + }), base_address + 0x350); + + /// address: 0x40040b70 + /// OTG_HS device endpoint-4 transfer size + /// register + pub const OTG_HS_DOEPTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet + /// count + RXDPID_STUPCNT: u2, + padding0: u1, + }), base_address + 0x370); + + /// address: 0x40040b90 + /// OTG_HS device endpoint-5 transfer size + /// register + pub const OTG_HS_DOEPTSIZ4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet + /// count + RXDPID_STUPCNT: u2, + padding0: u1, + }), base_address + 0x390); + }; + + /// USB on the go high speed + pub const OTG_HS_PWRCLK = struct { + pub const base_address = 0x40040e00; + + /// address: 0x40040e00 + /// Power and clock gating control + /// register + pub const OTG_HS_PCGCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stop PHY clock + STPPCLK: u1, + /// Gate HCLK + GATEHCLK: u1, + reserved0: u1, + reserved1: u1, + /// PHY suspended + PHYSUSP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x0); + }; + + /// LCD-TFT Controller + pub const LTDC = struct { + pub const base_address = 0x40016800; + + /// address: 0x40016808 + /// Synchronization Size Configuration + /// Register + pub const SSCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Vertical Synchronization Height (in + /// units of horizontal scan line) + VSH: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Horizontal Synchronization Width (in + /// units of pixel clock period) + HSW: u10, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x8); + + /// address: 0x4001680c + /// Back Porch Configuration + /// Register + pub const BPCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Accumulated Vertical back porch (in + /// units of horizontal scan line) + AVBP: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Accumulated Horizontal back porch (in + /// units of pixel clock period) + AHBP: u10, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xc); + + /// address: 0x40016810 + /// Active Width Configuration + /// Register + pub const AWCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Accumulated Active Height (in units of + /// horizontal scan line) + AAH: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// AAV + AAV: u10, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x10); + + /// address: 0x40016814 + /// Total Width Configuration + /// Register + pub const TWCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Total Height (in units of horizontal + /// scan line) + TOTALH: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Total Width (in units of pixel clock + /// period) + TOTALW: u10, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x14); + + /// address: 0x40016818 + /// Global Control Register + pub const GCR = @intToPtr(*volatile Mmio(32, packed struct { + /// LCD-TFT controller enable + /// bit + LTDCEN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Dither Blue Width + DBW: u3, + reserved3: u1, + /// Dither Green Width + DGW: u3, + reserved4: u1, + /// Dither Red Width + DRW: u3, + reserved5: u1, + /// Dither Enable + DEN: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + /// Pixel Clock Polarity + PCPOL: u1, + /// Data Enable Polarity + DEPOL: u1, + /// Vertical Synchronization + /// Polarity + VSPOL: u1, + /// Horizontal Synchronization + /// Polarity + HSPOL: u1, + }), base_address + 0x18); + + /// address: 0x40016824 + /// Shadow Reload Configuration + /// Register + pub const SRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Immediate Reload + IMR: u1, + /// Vertical Blanking Reload + VBR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x24); + + /// address: 0x4001682c + /// Background Color Configuration + /// Register + pub const BCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Background Color Red value + BC: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x2c); + + /// address: 0x40016834 + /// Interrupt Enable Register + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { + /// Line Interrupt Enable + LIE: u1, + /// FIFO Underrun Interrupt + /// Enable + FUIE: u1, + /// Transfer Error Interrupt + /// Enable + TERRIE: u1, + /// Register Reload interrupt + /// enable + RRIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x34); + + /// address: 0x40016838 + /// Interrupt Status Register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Line Interrupt flag + LIF: u1, + /// FIFO Underrun Interrupt + /// flag + FUIF: u1, + /// Transfer Error interrupt + /// flag + TERRIF: u1, + /// Register Reload Interrupt + /// Flag + RRIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x38); + + /// address: 0x4001683c + /// Interrupt Clear Register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clears the Line Interrupt + /// Flag + CLIF: u1, + /// Clears the FIFO Underrun Interrupt + /// flag + CFUIF: u1, + /// Clears the Transfer Error Interrupt + /// Flag + CTERRIF: u1, + /// Clears Register Reload Interrupt + /// Flag + CRRIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x3c); + + /// address: 0x40016840 + /// Line Interrupt Position Configuration + /// Register + pub const LIPCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Line Interrupt Position + LIPOS: u11, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x40); + + /// address: 0x40016844 + /// Current Position Status + /// Register + pub const CPSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Current Y Position + CYPOS: u16, + /// Current X Position + CXPOS: u16, + }), base_address + 0x44); + + /// address: 0x40016848 + /// Current Display Status + /// Register + pub const CDSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Vertical Data Enable display + /// Status + VDES: u1, + /// Horizontal Data Enable display + /// Status + HDES: u1, + /// Vertical Synchronization display + /// Status + VSYNCS: u1, + /// Horizontal Synchronization display + /// Status + HSYNCS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x48); + + /// address: 0x40016884 + /// Layerx Control Register + pub const L1CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Layer Enable + LEN: u1, + /// Color Keying Enable + COLKEN: u1, + reserved0: u1, + reserved1: u1, + /// Color Look-Up Table Enable + CLUTEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x84); + + /// address: 0x40016888 + /// Layerx Window Horizontal Position + /// Configuration Register + pub const L1WHPCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Window Horizontal Start + /// Position + WHSTPOS: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Window Horizontal Stop + /// Position + WHSPPOS: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x88); + + /// address: 0x4001688c + /// Layerx Window Vertical Position + /// Configuration Register + pub const L1WVPCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Window Vertical Start + /// Position + WVSTPOS: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Window Vertical Stop + /// Position + WVSPPOS: u11, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x8c); + + /// address: 0x40016890 + /// Layerx Color Keying Configuration + /// Register + pub const L1CKCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Color Key Blue value + CKBLUE: u8, + /// Color Key Green value + CKGREEN: u8, + /// Color Key Red value + CKRED: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x90); + + /// address: 0x40016894 + /// Layerx Pixel Format Configuration + /// Register + pub const L1PFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Pixel Format + PF: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x94); + + /// address: 0x40016898 + /// Layerx Constant Alpha Configuration + /// Register + pub const L1CACR = @intToPtr(*volatile Mmio(32, packed struct { + /// Constant Alpha + CONSTA: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x98); + + /// address: 0x4001689c + /// Layerx Default Color Configuration + /// Register + pub const L1DCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Default Color Blue + DCBLUE: u8, + /// Default Color Green + DCGREEN: u8, + /// Default Color Red + DCRED: u8, + /// Default Color Alpha + DCALPHA: u8, + }), base_address + 0x9c); + + /// address: 0x400168a0 + /// Layerx Blending Factors Configuration + /// Register + pub const L1BFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Blending Factor 2 + BF2: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Blending Factor 1 + BF1: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0xa0); + + /// address: 0x400168ac + /// Layerx Color Frame Buffer Address + /// Register + pub const L1CFBAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Color Frame Buffer Start + /// Address + CFBADD: u32, + }), base_address + 0xac); + + /// address: 0x400168b0 + /// Layerx Color Frame Buffer Length + /// Register + pub const L1CFBLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Color Frame Buffer Line + /// Length + CFBLL: u13, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Color Frame Buffer Pitch in + /// bytes + CFBP: u13, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0xb0); + + /// address: 0x400168b4 + /// Layerx ColorFrame Buffer Line Number + /// Register + pub const L1CFBLNR = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame Buffer Line Number + CFBLNBR: u11, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0xb4); + + /// address: 0x400168c4 + /// Layerx CLUT Write Register + pub const L1CLUTWR = @intToPtr(*volatile Mmio(32, packed struct { + /// Blue value + BLUE: u8, + /// Green value + GREEN: u8, + /// Red value + RED: u8, + /// CLUT Address + CLUTADD: u8, + }), base_address + 0xc4); + + /// address: 0x40016904 + /// Layerx Control Register + pub const L2CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Layer Enable + LEN: u1, + /// Color Keying Enable + COLKEN: u1, + reserved0: u1, + reserved1: u1, + /// Color Look-Up Table Enable + CLUTEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x104); + + /// address: 0x40016908 + /// Layerx Window Horizontal Position + /// Configuration Register + pub const L2WHPCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Window Horizontal Start + /// Position + WHSTPOS: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Window Horizontal Stop + /// Position + WHSPPOS: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x108); + + /// address: 0x4001690c + /// Layerx Window Vertical Position + /// Configuration Register + pub const L2WVPCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Window Vertical Start + /// Position + WVSTPOS: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Window Vertical Stop + /// Position + WVSPPOS: u11, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x10c); + + /// address: 0x40016910 + /// Layerx Color Keying Configuration + /// Register + pub const L2CKCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Color Key Blue value + CKBLUE: u8, + /// Color Key Green value + CKGREEN: u7, + /// Color Key Red value + CKRED: u9, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x110); + + /// address: 0x40016914 + /// Layerx Pixel Format Configuration + /// Register + pub const L2PFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Pixel Format + PF: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x114); + + /// address: 0x40016918 + /// Layerx Constant Alpha Configuration + /// Register + pub const L2CACR = @intToPtr(*volatile Mmio(32, packed struct { + /// Constant Alpha + CONSTA: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x118); + + /// address: 0x4001691c + /// Layerx Default Color Configuration + /// Register + pub const L2DCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Default Color Blue + DCBLUE: u8, + /// Default Color Green + DCGREEN: u8, + /// Default Color Red + DCRED: u8, + /// Default Color Alpha + DCALPHA: u8, + }), base_address + 0x11c); + + /// address: 0x40016920 + /// Layerx Blending Factors Configuration + /// Register + pub const L2BFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Blending Factor 2 + BF2: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Blending Factor 1 + BF1: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x120); + + /// address: 0x4001692c + /// Layerx Color Frame Buffer Address + /// Register + pub const L2CFBAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Color Frame Buffer Start + /// Address + CFBADD: u32, + }), base_address + 0x12c); + + /// address: 0x40016930 + /// Layerx Color Frame Buffer Length + /// Register + pub const L2CFBLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Color Frame Buffer Line + /// Length + CFBLL: u13, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Color Frame Buffer Pitch in + /// bytes + CFBP: u13, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x130); + + /// address: 0x40016934 + /// Layerx ColorFrame Buffer Line Number + /// Register + pub const L2CFBLNR = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame Buffer Line Number + CFBLNBR: u11, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x134); + + /// address: 0x40016944 + /// Layerx CLUT Write Register + pub const L2CLUTWR = @intToPtr(*volatile Mmio(32, packed struct { + /// Blue value + BLUE: u8, + /// Green value + GREEN: u8, + /// Red value + RED: u8, + /// CLUT Address + CLUTADD: u8, + }), base_address + 0x144); + }; + + /// Serial audio interface + pub const SAI = struct { + pub const base_address = 0x40015800; + + /// address: 0x40015824 + /// BConfiguration register 1 + pub const BCR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Audio block mode + MODE: u2, + /// Protocol configuration + PRTCFG: u2, + reserved0: u1, + /// Data size + DS: u3, + /// Least significant bit + /// first + LSBFIRST: u1, + /// Clock strobing edge + CKSTR: u1, + /// Synchronization enable + SYNCEN: u2, + /// Mono mode + MONO: u1, + /// Output drive + OutDri: u1, + reserved1: u1, + reserved2: u1, + /// Audio block B enable + SAIBEN: u1, + /// DMA enable + DMAEN: u1, + reserved3: u1, + /// No divider + NODIV: u1, + /// Master clock divider + MCJDIV: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x24); + + /// address: 0x40015828 + /// BConfiguration register 2 + pub const BCR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold + FTH: u3, + /// FIFO flush + FFLUS: u1, + /// Tristate management on data + /// line + TRIS: u1, + /// Mute + MUTE: u1, + /// Mute value + MUTEVAL: u1, + /// Mute counter + MUTECN: u6, + /// Complement bit + CPL: u1, + /// Companding mode + COMP: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + + /// address: 0x4001582c + /// BFRCR + pub const BFRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame length + FRL: u8, + /// Frame synchronization active level + /// length + FSALL: u7, + reserved0: u1, + /// Frame synchronization + /// definition + FSDEF: u1, + /// Frame synchronization + /// polarity + FSPOL: u1, + /// Frame synchronization + /// offset + FSOFF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x2c); + + /// address: 0x40015830 + /// BSlot register + pub const BSLOTR = @intToPtr(*volatile Mmio(32, packed struct { + /// First bit offset + FBOFF: u5, + reserved0: u1, + /// Slot size + SLOTSZ: u2, + /// Number of slots in an audio + /// frame + NBSLOT: u4, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Slot enable + SLOTEN: u16, + }), base_address + 0x30); + + /// address: 0x40015834 + /// BInterrupt mask register2 + pub const BIM = @intToPtr(*volatile Mmio(32, packed struct { + /// Overrun/underrun interrupt + /// enable + OVRUDRIE: u1, + /// Mute detection interrupt + /// enable + MUTEDET: u1, + /// Wrong clock configuration interrupt + /// enable + WCKCFG: u1, + /// FIFO request interrupt + /// enable + FREQIE: u1, + /// Codec not ready interrupt + /// enable + CNRDYIE: u1, + /// Anticipated frame synchronization + /// detection interrupt enable + AFSDETIE: u1, + /// Late frame synchronization detection + /// interrupt enable + LFSDETIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x34); + + /// address: 0x40015838 + /// BStatus register + pub const BSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Overrun / underrun + OVRUDR: u1, + /// Mute detection + MUTEDET: u1, + /// Wrong clock configuration + /// flag + WCKCFG: u1, + /// FIFO request + FREQ: u1, + /// Codec not ready + CNRDY: u1, + /// Anticipated frame synchronization + /// detection + AFSDET: u1, + /// Late frame synchronization + /// detection + LFSDET: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// FIFO level threshold + FLVL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x38); + + /// address: 0x4001583c + /// BClear flag register + pub const BCLRFR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clear overrun / underrun + OVRUDR: u1, + /// Mute detection flag + MUTEDET: u1, + /// Clear wrong clock configuration + /// flag + WCKCFG: u1, + reserved0: u1, + /// Clear codec not ready flag + CNRDY: u1, + /// Clear anticipated frame synchronization + /// detection flag + CAFSDET: u1, + /// Clear late frame synchronization + /// detection flag + LFSDET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x3c); + + /// address: 0x40015840 + /// BData register + pub const BDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Data + DATA: u32, + }), base_address + 0x40); + + /// address: 0x40015804 + /// AConfiguration register 1 + pub const ACR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Audio block mode + MODE: u2, + /// Protocol configuration + PRTCFG: u2, + reserved0: u1, + /// Data size + DS: u3, + /// Least significant bit + /// first + LSBFIRST: u1, + /// Clock strobing edge + CKSTR: u1, + /// Synchronization enable + SYNCEN: u2, + /// Mono mode + MONO: u1, + /// Output drive + OutDri: u1, + reserved1: u1, + reserved2: u1, + /// Audio block A enable + SAIAEN: u1, + /// DMA enable + DMAEN: u1, + reserved3: u1, + /// No divider + NODIV: u1, + /// Master clock divider + MCJDIV: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40015808 + /// AConfiguration register 2 + pub const ACR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold + FTH: u3, + /// FIFO flush + FFLUS: u1, + /// Tristate management on data + /// line + TRIS: u1, + /// Mute + MUTE: u1, + /// Mute value + MUTEVAL: u1, + /// Mute counter + MUTECN: u6, + /// Complement bit + CPL: u1, + /// Companding mode + COMP: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001580c + /// AFRCR + pub const AFRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame length + FRL: u8, + /// Frame synchronization active level + /// length + FSALL: u7, + reserved0: u1, + /// Frame synchronization + /// definition + FSDEF: u1, + /// Frame synchronization + /// polarity + FSPOL: u1, + /// Frame synchronization + /// offset + FSOFF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xc); + + /// address: 0x40015810 + /// ASlot register + pub const ASLOTR = @intToPtr(*volatile Mmio(32, packed struct { + /// First bit offset + FBOFF: u5, + reserved0: u1, + /// Slot size + SLOTSZ: u2, + /// Number of slots in an audio + /// frame + NBSLOT: u4, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Slot enable + SLOTEN: u16, + }), base_address + 0x10); + + /// address: 0x40015814 + /// AInterrupt mask register2 + pub const AIM = @intToPtr(*volatile Mmio(32, packed struct { + /// Overrun/underrun interrupt + /// enable + OVRUDRIE: u1, + /// Mute detection interrupt + /// enable + MUTEDET: u1, + /// Wrong clock configuration interrupt + /// enable + WCKCFG: u1, + /// FIFO request interrupt + /// enable + FREQIE: u1, + /// Codec not ready interrupt + /// enable + CNRDYIE: u1, + /// Anticipated frame synchronization + /// detection interrupt enable + AFSDETIE: u1, + /// Late frame synchronization detection + /// interrupt enable + LFSDET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40015818 + /// AStatus register + pub const ASR = @intToPtr(*volatile Mmio(32, packed struct { + /// Overrun / underrun + OVRUDR: u1, + /// Mute detection + MUTEDET: u1, + /// Wrong clock configuration flag. This bit + /// is read only. + WCKCFG: u1, + /// FIFO request + FREQ: u1, + /// Codec not ready + CNRDY: u1, + /// Anticipated frame synchronization + /// detection + AFSDET: u1, + /// Late frame synchronization + /// detection + LFSDET: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// FIFO level threshold + FLVL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x18); + + /// address: 0x4001581c + /// AClear flag register + pub const ACLRFR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clear overrun / underrun + OVRUDR: u1, + /// Mute detection flag + MUTEDET: u1, + /// Clear wrong clock configuration + /// flag + WCKCFG: u1, + reserved0: u1, + /// Clear codec not ready flag + CNRDY: u1, + /// Clear anticipated frame synchronization + /// detection flag. + CAFSDET: u1, + /// Clear late frame synchronization + /// detection flag + LFSDET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x1c); + + /// address: 0x40015820 + /// AData register + pub const ADR = @intToPtr(*volatile Mmio(32, packed struct { + /// Data + DATA: u32, + }), base_address + 0x20); + }; + + /// DMA2D controller + pub const DMA2D = struct { + pub const base_address = 0x4002b000; + + /// address: 0x4002b000 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Start + START: u1, + /// Suspend + SUSP: u1, + /// Abort + ABORT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Transfer watermark interrupt + /// enable + TWIE: u1, + /// CLUT access error interrupt + /// enable + CAEIE: u1, + /// CLUT transfer complete interrupt + /// enable + CTCIE: u1, + /// Configuration Error Interrupt + /// Enable + CEIE: u1, + reserved5: u1, + reserved6: u1, + /// DMA2D mode + MODE: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x0); + + /// address: 0x4002b004 + /// Interrupt Status Register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer error interrupt + /// flag + TEIF: u1, + /// Transfer complete interrupt + /// flag + TCIF: u1, + /// Transfer watermark interrupt + /// flag + TWIF: u1, + /// CLUT access error interrupt + /// flag + CAEIF: u1, + /// CLUT transfer complete interrupt + /// flag + CTCIF: u1, + /// Configuration error interrupt + /// flag + CEIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x4); + + /// address: 0x4002b008 + /// interrupt flag clear register + pub const IFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clear Transfer error interrupt + /// flag + CTEIF: u1, + /// Clear transfer complete interrupt + /// flag + CTCIF: u1, + /// Clear transfer watermark interrupt + /// flag + CTWIF: u1, + /// Clear CLUT access error interrupt + /// flag + CAECIF: u1, + /// Clear CLUT transfer complete interrupt + /// flag + CCTCIF: u1, + /// Clear configuration error interrupt + /// flag + CCEIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x8); + + /// address: 0x4002b00c + /// foreground memory address + /// register + pub const FGMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory address + MA: u32, + }), base_address + 0xc); + + /// address: 0x4002b010 + /// foreground offset register + pub const FGOR = @intToPtr(*volatile Mmio(32, packed struct { + /// Line offset + LO: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x10); + + /// address: 0x4002b014 + /// background memory address + /// register + pub const BGMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory address + MA: u32, + }), base_address + 0x14); + + /// address: 0x4002b018 + /// background offset register + pub const BGOR = @intToPtr(*volatile Mmio(32, packed struct { + /// Line offset + LO: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x18); + + /// address: 0x4002b01c + /// foreground PFC control + /// register + pub const FGPFCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Color mode + CM: u4, + /// CLUT color mode + CCM: u1, + /// Start + START: u1, + reserved0: u1, + reserved1: u1, + /// CLUT size + CS: u8, + /// Alpha mode + AM: u2, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Alpha value + ALPHA: u8, + }), base_address + 0x1c); + + /// address: 0x4002b020 + /// foreground color register + pub const FGCOLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Blue Value + BLUE: u8, + /// Green Value + GREEN: u8, + /// Red Value + RED: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x20); + + /// address: 0x4002b024 + /// background PFC control + /// register + pub const BGPFCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Color mode + CM: u4, + /// CLUT Color mode + CCM: u1, + /// Start + START: u1, + reserved0: u1, + reserved1: u1, + /// CLUT size + CS: u8, + /// Alpha mode + AM: u2, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Alpha value + ALPHA: u8, + }), base_address + 0x24); + + /// address: 0x4002b028 + /// background color register + pub const BGCOLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Blue Value + BLUE: u8, + /// Green Value + GREEN: u8, + /// Red Value + RED: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x28); + + /// address: 0x4002b02c + /// foreground CLUT memory address + /// register + pub const FGCMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory Address + MA: u32, + }), base_address + 0x2c); + + /// address: 0x4002b030 + /// background CLUT memory address + /// register + pub const BGCMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory address + MA: u32, + }), base_address + 0x30); + + /// address: 0x4002b034 + /// output PFC control register + pub const OPFCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Color mode + CM: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x34); + + /// address: 0x4002b038 + /// output color register + pub const OCOLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Blue Value + BLUE: u8, + /// Green Value + GREEN: u8, + /// Red Value + RED: u8, + /// Alpha Channel Value + APLHA: u8, + }), base_address + 0x38); + + /// address: 0x4002b03c + /// output memory address register + pub const OMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory Address + MA: u32, + }), base_address + 0x3c); + + /// address: 0x4002b040 + /// output offset register + pub const OOR = @intToPtr(*volatile Mmio(32, packed struct { + /// Line Offset + LO: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x40); + + /// address: 0x4002b044 + /// number of line register + pub const NLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of lines + NL: u16, + /// Pixel per lines + PL: u14, + padding0: u1, + padding1: u1, + }), base_address + 0x44); + + /// address: 0x4002b048 + /// line watermark register + pub const LWR = @intToPtr(*volatile Mmio(32, packed struct { + /// Line watermark + LW: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x4002b04c + /// AHB master timer configuration + /// register + pub const AMTCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable + EN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Dead Time + DT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + + /// address: 0x4002b400 + /// FGCLUT + pub const FGCLUT = @intToPtr(*volatile Mmio(32, packed struct { + /// BLUE + BLUE: u8, + /// GREEN + GREEN: u8, + /// RED + RED: u8, + /// APLHA + APLHA: u8, + }), base_address + 0x400); + + /// address: 0x4002b800 + /// BGCLUT + pub const BGCLUT = @intToPtr(*volatile Mmio(32, packed struct { + /// BLUE + BLUE: u8, + /// GREEN + GREEN: u8, + /// RED + RED: u8, + /// APLHA + APLHA: u8, + }), base_address + 0x800); + }; + + /// Inter-integrated circuit + pub const I2C3 = struct { + pub const base_address = 0x40005c00; + + /// address: 0x40005c00 + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral enable + PE: u1, + /// SMBus mode + SMBUS: u1, + reserved0: u1, + /// SMBus type + SMBTYPE: u1, + /// ARP enable + ENARP: u1, + /// PEC enable + ENPEC: u1, + /// General call enable + ENGC: u1, + /// Clock stretching disable (Slave + /// mode) + NOSTRETCH: u1, + /// Start generation + START: u1, + /// Stop generation + STOP: u1, + /// Acknowledge enable + ACK: u1, + /// Acknowledge/PEC Position (for data + /// reception) + POS: u1, + /// Packet error checking + PEC: u1, + /// SMBus alert + ALERT: u1, + reserved1: u1, + /// Software reset + SWRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40005c04 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral clock frequency + FREQ: u6, + reserved0: u1, + reserved1: u1, + /// Error interrupt enable + ITERREN: u1, + /// Event interrupt enable + ITEVTEN: u1, + /// Buffer interrupt enable + ITBUFEN: u1, + /// DMA requests enable + DMAEN: u1, + /// DMA last transfer + LAST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x4); + + /// address: 0x40005c08 + /// Own address register 1 + pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Interface address + ADD0: u1, + /// Interface address + ADD7: u7, + /// Interface address + ADD10: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Addressing mode (slave + /// mode) + ADDMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40005c0c + /// Own address register 2 + pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Dual addressing mode + /// enable + ENDUAL: u1, + /// Interface address + ADD2: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xc); + + /// address: 0x40005c10 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x10); + + /// address: 0x40005c14 + /// Status register 1 + pub const SR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Start bit (Master mode) + SB: u1, + /// Address sent (master mode)/matched + /// (slave mode) + ADDR: u1, + /// Byte transfer finished + BTF: u1, + /// 10-bit header sent (Master + /// mode) + ADD10: u1, + /// Stop detection (slave + /// mode) + STOPF: u1, + reserved0: u1, + /// Data register not empty + /// (receivers) + RxNE: u1, + /// Data register empty + /// (transmitters) + TxE: u1, + /// Bus error + BERR: u1, + /// Arbitration lost (master + /// mode) + ARLO: u1, + /// Acknowledge failure + AF: u1, + /// Overrun/Underrun + OVR: u1, + /// PEC Error in reception + PECERR: u1, + reserved1: u1, + /// Timeout or Tlow error + TIMEOUT: u1, + /// SMBus alert + SMBALERT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40005c18 + /// Status register 2 + pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Master/slave + MSL: u1, + /// Bus busy + BUSY: u1, + /// Transmitter/receiver + TRA: u1, + reserved0: u1, + /// General call address (Slave + /// mode) + GENCALL: u1, + /// SMBus device default address (Slave + /// mode) + SMBDEFAULT: u1, + /// SMBus host header (Slave + /// mode) + SMBHOST: u1, + /// Dual flag (Slave mode) + DUALF: u1, + /// acket error checking + /// register + PEC: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40005c1c + /// Clock control register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock control register in Fast/Standard + /// mode (Master mode) + CCR: u12, + reserved0: u1, + reserved1: u1, + /// Fast mode duty cycle + DUTY: u1, + /// I2C master mode selection + F_S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40005c20 + /// TRISE register + pub const TRISE = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x20); + + /// address: 0x40005c24 + /// I2C FLTR register + pub const FLTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Digital noise filter + DNF: u4, + /// Analog noise filter OFF + ANOFF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x24); + }; + pub const I2C2 = struct { + pub const base_address = 0x40005800; + + /// address: 0x40005800 + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral enable + PE: u1, + /// SMBus mode + SMBUS: u1, + reserved0: u1, + /// SMBus type + SMBTYPE: u1, + /// ARP enable + ENARP: u1, + /// PEC enable + ENPEC: u1, + /// General call enable + ENGC: u1, + /// Clock stretching disable (Slave + /// mode) + NOSTRETCH: u1, + /// Start generation + START: u1, + /// Stop generation + STOP: u1, + /// Acknowledge enable + ACK: u1, + /// Acknowledge/PEC Position (for data + /// reception) + POS: u1, + /// Packet error checking + PEC: u1, + /// SMBus alert + ALERT: u1, + reserved1: u1, + /// Software reset + SWRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40005804 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral clock frequency + FREQ: u6, + reserved0: u1, + reserved1: u1, + /// Error interrupt enable + ITERREN: u1, + /// Event interrupt enable + ITEVTEN: u1, + /// Buffer interrupt enable + ITBUFEN: u1, + /// DMA requests enable + DMAEN: u1, + /// DMA last transfer + LAST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x4); + + /// address: 0x40005808 + /// Own address register 1 + pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Interface address + ADD0: u1, + /// Interface address + ADD7: u7, + /// Interface address + ADD10: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Addressing mode (slave + /// mode) + ADDMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000580c + /// Own address register 2 + pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Dual addressing mode + /// enable + ENDUAL: u1, + /// Interface address + ADD2: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xc); + + /// address: 0x40005810 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x10); + + /// address: 0x40005814 + /// Status register 1 + pub const SR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Start bit (Master mode) + SB: u1, + /// Address sent (master mode)/matched + /// (slave mode) + ADDR: u1, + /// Byte transfer finished + BTF: u1, + /// 10-bit header sent (Master + /// mode) + ADD10: u1, + /// Stop detection (slave + /// mode) + STOPF: u1, + reserved0: u1, + /// Data register not empty + /// (receivers) + RxNE: u1, + /// Data register empty + /// (transmitters) + TxE: u1, + /// Bus error + BERR: u1, + /// Arbitration lost (master + /// mode) + ARLO: u1, + /// Acknowledge failure + AF: u1, + /// Overrun/Underrun + OVR: u1, + /// PEC Error in reception + PECERR: u1, + reserved1: u1, + /// Timeout or Tlow error + TIMEOUT: u1, + /// SMBus alert + SMBALERT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40005818 + /// Status register 2 + pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Master/slave + MSL: u1, + /// Bus busy + BUSY: u1, + /// Transmitter/receiver + TRA: u1, + reserved0: u1, + /// General call address (Slave + /// mode) + GENCALL: u1, + /// SMBus device default address (Slave + /// mode) + SMBDEFAULT: u1, + /// SMBus host header (Slave + /// mode) + SMBHOST: u1, + /// Dual flag (Slave mode) + DUALF: u1, + /// acket error checking + /// register + PEC: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000581c + /// Clock control register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock control register in Fast/Standard + /// mode (Master mode) + CCR: u12, + reserved0: u1, + reserved1: u1, + /// Fast mode duty cycle + DUTY: u1, + /// I2C master mode selection + F_S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40005820 + /// TRISE register + pub const TRISE = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x20); + + /// address: 0x40005824 + /// I2C FLTR register + pub const FLTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Digital noise filter + DNF: u4, + /// Analog noise filter OFF + ANOFF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x24); + }; + pub const I2C1 = struct { + pub const base_address = 0x40005400; + + /// address: 0x40005400 + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral enable + PE: u1, + /// SMBus mode + SMBUS: u1, + reserved0: u1, + /// SMBus type + SMBTYPE: u1, + /// ARP enable + ENARP: u1, + /// PEC enable + ENPEC: u1, + /// General call enable + ENGC: u1, + /// Clock stretching disable (Slave + /// mode) + NOSTRETCH: u1, + /// Start generation + START: u1, + /// Stop generation + STOP: u1, + /// Acknowledge enable + ACK: u1, + /// Acknowledge/PEC Position (for data + /// reception) + POS: u1, + /// Packet error checking + PEC: u1, + /// SMBus alert + ALERT: u1, + reserved1: u1, + /// Software reset + SWRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40005404 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral clock frequency + FREQ: u6, + reserved0: u1, + reserved1: u1, + /// Error interrupt enable + ITERREN: u1, + /// Event interrupt enable + ITEVTEN: u1, + /// Buffer interrupt enable + ITBUFEN: u1, + /// DMA requests enable + DMAEN: u1, + /// DMA last transfer + LAST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x4); + + /// address: 0x40005408 + /// Own address register 1 + pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Interface address + ADD0: u1, + /// Interface address + ADD7: u7, + /// Interface address + ADD10: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Addressing mode (slave + /// mode) + ADDMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000540c + /// Own address register 2 + pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Dual addressing mode + /// enable + ENDUAL: u1, + /// Interface address + ADD2: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xc); + + /// address: 0x40005410 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x10); + + /// address: 0x40005414 + /// Status register 1 + pub const SR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Start bit (Master mode) + SB: u1, + /// Address sent (master mode)/matched + /// (slave mode) + ADDR: u1, + /// Byte transfer finished + BTF: u1, + /// 10-bit header sent (Master + /// mode) + ADD10: u1, + /// Stop detection (slave + /// mode) + STOPF: u1, + reserved0: u1, + /// Data register not empty + /// (receivers) + RxNE: u1, + /// Data register empty + /// (transmitters) + TxE: u1, + /// Bus error + BERR: u1, + /// Arbitration lost (master + /// mode) + ARLO: u1, + /// Acknowledge failure + AF: u1, + /// Overrun/Underrun + OVR: u1, + /// PEC Error in reception + PECERR: u1, + reserved1: u1, + /// Timeout or Tlow error + TIMEOUT: u1, + /// SMBus alert + SMBALERT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40005418 + /// Status register 2 + pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Master/slave + MSL: u1, + /// Bus busy + BUSY: u1, + /// Transmitter/receiver + TRA: u1, + reserved0: u1, + /// General call address (Slave + /// mode) + GENCALL: u1, + /// SMBus device default address (Slave + /// mode) + SMBDEFAULT: u1, + /// SMBus host header (Slave + /// mode) + SMBHOST: u1, + /// Dual flag (Slave mode) + DUALF: u1, + /// acket error checking + /// register + PEC: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000541c + /// Clock control register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock control register in Fast/Standard + /// mode (Master mode) + CCR: u12, + reserved0: u1, + reserved1: u1, + /// Fast mode duty cycle + DUTY: u1, + /// I2C master mode selection + F_S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40005420 + /// TRISE register + pub const TRISE = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x20); + + /// address: 0x40005424 + /// I2C FLTR register + pub const FLTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Digital noise filter + DNF: u4, + /// Analog noise filter OFF + ANOFF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x24); + }; + + /// Floting point unit + pub const FPU = struct { + pub const base_address = 0xe000ef34; + + /// address: 0xe000ef34 + /// Floating-point context control + /// register + pub const FPCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// LSPACT + LSPACT: u1, + /// USER + USER: u1, + reserved0: u1, + /// THREAD + THREAD: u1, + /// HFRDY + HFRDY: u1, + /// MMRDY + MMRDY: u1, + /// BFRDY + BFRDY: u1, + reserved1: u1, + /// MONRDY + MONRDY: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + /// LSPEN + LSPEN: u1, + /// ASPEN + ASPEN: u1, + }), base_address + 0x0); + + /// address: 0xe000ef38 + /// Floating-point context address + /// register + pub const FPCAR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Location of unpopulated + /// floating-point + ADDRESS: u29, + }), base_address + 0x4); + + /// address: 0xe000ef3c + /// Floating-point status control + /// register + pub const FPSCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Invalid operation cumulative exception + /// bit + IOC: u1, + /// Division by zero cumulative exception + /// bit. + DZC: u1, + /// Overflow cumulative exception + /// bit + OFC: u1, + /// Underflow cumulative exception + /// bit + UFC: u1, + /// Inexact cumulative exception + /// bit + IXC: u1, + reserved0: u1, + reserved1: u1, + /// Input denormal cumulative exception + /// bit. + IDC: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Rounding Mode control + /// field + RMode: u2, + /// Flush-to-zero mode control + /// bit: + FZ: u1, + /// Default NaN mode control + /// bit + DN: u1, + /// Alternative half-precision control + /// bit + AHP: u1, + reserved16: u1, + /// Overflow condition code + /// flag + V: u1, + /// Carry condition code flag + C: u1, + /// Zero condition code flag + Z: u1, + /// Negative condition code + /// flag + N: u1, + }), base_address + 0x8); + }; + + /// Memory protection unit + pub const MPU = struct { + pub const base_address = 0xe000ed90; + + /// address: 0xe000ed90 + /// MPU type register + pub const MPU_TYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Separate flag + SEPARATE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Number of MPU data regions + DREGION: u8, + /// Number of MPU instruction + /// regions + IREGION: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x0); + + /// address: 0xe000ed94 + /// MPU control register + pub const MPU_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Enables the MPU + ENABLE: u1, + /// Enables the operation of MPU during hard + /// fault + HFNMIENA: u1, + /// Enable priviliged software access to + /// default memory map + PRIVDEFENA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x4); + + /// address: 0xe000ed98 + /// MPU region number register + pub const MPU_RNR = @intToPtr(*volatile Mmio(32, packed struct { + /// MPU region + REGION: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x8); + + /// address: 0xe000ed9c + /// MPU region base address + /// register + pub const MPU_RBAR = @intToPtr(*volatile Mmio(32, packed struct { + /// MPU region field + REGION: u4, + /// MPU region number valid + VALID: u1, + /// Region base address field + ADDR: u27, + }), base_address + 0xc); + + /// address: 0xe000eda0 + /// MPU region attribute and size + /// register + pub const MPU_RASR = @intToPtr(*volatile Mmio(32, packed struct { + /// Region enable bit. + ENABLE: u1, + /// Size of the MPU protection + /// region + SIZE: u5, + reserved0: u1, + reserved1: u1, + /// Subregion disable bits + SRD: u8, + /// memory attribute + B: u1, + /// memory attribute + C: u1, + /// Shareable memory attribute + S: u1, + /// memory attribute + TEX: u3, + reserved2: u1, + reserved3: u1, + /// Access permission + AP: u3, + reserved4: u1, + /// Instruction access disable + /// bit + XN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x10); + }; + + /// SysTick timer + pub const STK = struct { + pub const base_address = 0xe000e010; + + /// address: 0xe000e010 + /// SysTick control and status + /// register + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + ENABLE: u1, + /// SysTick exception request + /// enable + TICKINT: u1, + /// Clock source selection + CLKSOURCE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// COUNTFLAG + COUNTFLAG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x0); + + /// address: 0xe000e014 + /// SysTick reload value register + pub const LOAD = @intToPtr(*volatile Mmio(32, packed struct { + /// RELOAD value + RELOAD: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0xe000e018 + /// SysTick current value register + pub const VAL = @intToPtr(*volatile Mmio(32, packed struct { + /// Current counter value + CURRENT: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x8); + + /// address: 0xe000e01c + /// SysTick calibration value + /// register + pub const CALIB = @intToPtr(*volatile Mmio(32, packed struct { + /// Calibration value + TENMS: u24, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// SKEW flag: Indicates whether the TENMS + /// value is exact + SKEW: u1, + /// NOREF flag. Reads as zero + NOREF: u1, + }), base_address + 0xc); + }; + + /// System control block + pub const SCB = struct { + pub const base_address = 0xe000ed00; + + /// address: 0xe000ed00 + /// CPUID base register + pub const CPUID = @intToPtr(*volatile Mmio(32, packed struct { + /// Revision number + Revision: u4, + /// Part number of the + /// processor + PartNo: u12, + /// Reads as 0xF + Constant: u4, + /// Variant number + Variant: u4, + /// Implementer code + Implementer: u8, + }), base_address + 0x0); + + /// address: 0xe000ed04 + /// Interrupt control and state + /// register + pub const ICSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Active vector + VECTACTIVE: u9, + reserved0: u1, + reserved1: u1, + /// Return to base level + RETTOBASE: u1, + /// Pending vector + VECTPENDING: u7, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Interrupt pending flag + ISRPENDING: u1, + reserved5: u1, + reserved6: u1, + /// SysTick exception clear-pending + /// bit + PENDSTCLR: u1, + /// SysTick exception set-pending + /// bit + PENDSTSET: u1, + /// PendSV clear-pending bit + PENDSVCLR: u1, + /// PendSV set-pending bit + PENDSVSET: u1, + reserved7: u1, + reserved8: u1, + /// NMI set-pending bit. + NMIPENDSET: u1, + }), base_address + 0x4); + + /// address: 0xe000ed08 + /// Vector table offset register + pub const VTOR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Vector table base offset + /// field + TBLOFF: u21, + padding0: u1, + padding1: u1, + }), base_address + 0x8); + + /// address: 0xe000ed0c + /// Application interrupt and reset control + /// register + pub const AIRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// VECTRESET + VECTRESET: u1, + /// VECTCLRACTIVE + VECTCLRACTIVE: u1, + /// SYSRESETREQ + SYSRESETREQ: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// PRIGROUP + PRIGROUP: u3, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// ENDIANESS + ENDIANESS: u1, + /// Register key + VECTKEYSTAT: u16, + }), base_address + 0xc); + + /// address: 0xe000ed10 + /// System control register + pub const SCR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// SLEEPONEXIT + SLEEPONEXIT: u1, + /// SLEEPDEEP + SLEEPDEEP: u1, + reserved1: u1, + /// Send Event on Pending bit + SEVEONPEND: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x10); + + /// address: 0xe000ed14 + /// Configuration and control + /// register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Configures how the processor enters + /// Thread mode + NONBASETHRDENA: u1, + /// USERSETMPEND + USERSETMPEND: u1, + reserved0: u1, + /// UNALIGN_ TRP + UNALIGN__TRP: u1, + /// DIV_0_TRP + DIV_0_TRP: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// BFHFNMIGN + BFHFNMIGN: u1, + /// STKALIGN + STKALIGN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x14); + + /// address: 0xe000ed18 + /// System handler priority + /// registers + pub const SHPR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Priority of system handler + /// 4 + PRI_4: u8, + /// Priority of system handler + /// 5 + PRI_5: u8, + /// Priority of system handler + /// 6 + PRI_6: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x18); + + /// address: 0xe000ed1c + /// System handler priority + /// registers + pub const SHPR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + /// Priority of system handler + /// 11 + PRI_11: u8, + }), base_address + 0x1c); + + /// address: 0xe000ed20 + /// System handler priority + /// registers + pub const SHPR3 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Priority of system handler + /// 14 + PRI_14: u8, + /// Priority of system handler + /// 15 + PRI_15: u8, + }), base_address + 0x20); + + /// address: 0xe000ed24 + /// System handler control and state + /// register + pub const SHCRS = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory management fault exception active + /// bit + MEMFAULTACT: u1, + /// Bus fault exception active + /// bit + BUSFAULTACT: u1, + reserved0: u1, + /// Usage fault exception active + /// bit + USGFAULTACT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// SVC call active bit + SVCALLACT: u1, + /// Debug monitor active bit + MONITORACT: u1, + reserved4: u1, + /// PendSV exception active + /// bit + PENDSVACT: u1, + /// SysTick exception active + /// bit + SYSTICKACT: u1, + /// Usage fault exception pending + /// bit + USGFAULTPENDED: u1, + /// Memory management fault exception + /// pending bit + MEMFAULTPENDED: u1, + /// Bus fault exception pending + /// bit + BUSFAULTPENDED: u1, + /// SVC call pending bit + SVCALLPENDED: u1, + /// Memory management fault enable + /// bit + MEMFAULTENA: u1, + /// Bus fault enable bit + BUSFAULTENA: u1, + /// Usage fault enable bit + USGFAULTENA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x24); + + /// address: 0xe000ed28 + /// Configurable fault status + /// register + pub const CFSR_UFSR_BFSR_MMFSR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Instruction access violation + /// flag + IACCVIOL: u1, + reserved1: u1, + /// Memory manager fault on unstacking for a + /// return from exception + MUNSTKERR: u1, + /// Memory manager fault on stacking for + /// exception entry. + MSTKERR: u1, + /// MLSPERR + MLSPERR: u1, + reserved2: u1, + /// Memory Management Fault Address Register + /// (MMAR) valid flag + MMARVALID: u1, + /// Instruction bus error + IBUSERR: u1, + /// Precise data bus error + PRECISERR: u1, + /// Imprecise data bus error + IMPRECISERR: u1, + /// Bus fault on unstacking for a return + /// from exception + UNSTKERR: u1, + /// Bus fault on stacking for exception + /// entry + STKERR: u1, + /// Bus fault on floating-point lazy state + /// preservation + LSPERR: u1, + reserved3: u1, + /// Bus Fault Address Register (BFAR) valid + /// flag + BFARVALID: u1, + /// Undefined instruction usage + /// fault + UNDEFINSTR: u1, + /// Invalid state usage fault + INVSTATE: u1, + /// Invalid PC load usage + /// fault + INVPC: u1, + /// No coprocessor usage + /// fault. + NOCP: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Unaligned access usage + /// fault + UNALIGNED: u1, + /// Divide by zero usage fault + DIVBYZERO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x28); + + /// address: 0xe000ed2c + /// Hard fault status register + pub const HFSR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Vector table hard fault + VECTTBL: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + reserved26: u1, + reserved27: u1, + reserved28: u1, + /// Forced hard fault + FORCED: u1, + /// Reserved for Debug use + DEBUG_VT: u1, + }), base_address + 0x2c); + + /// address: 0xe000ed34 + /// Memory management fault address + /// register + pub const MMFAR = @intToPtr(*volatile u32, base_address + 0x34); + + /// address: 0xe000ed38 + /// Bus fault address register + pub const BFAR = @intToPtr(*volatile u32, base_address + 0x38); + + /// address: 0xe000ed3c + /// Auxiliary fault status + /// register + pub const AFSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Implementation defined + IMPDEF: u32, + }), base_address + 0x3c); + }; + + /// Nested vectored interrupt + /// controller + pub const NVIC_STIR = struct { + pub const base_address = 0xe000ef00; + + /// address: 0xe000ef00 + /// Software trigger interrupt + /// register + pub const STIR = @intToPtr(*volatile Mmio(32, packed struct { + /// Software generated interrupt + /// ID + INTID: u9, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x0); + }; + + /// Floating point unit CPACR + pub const FPU_CPACR = struct { + pub const base_address = 0xe000ed88; + + /// address: 0xe000ed88 + /// Coprocessor access control + /// register + pub const CPACR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + /// CP + CP: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x0); + }; + + /// System control block ACTLR + pub const SCB_ACTRL = struct { + pub const base_address = 0xe000e008; + + /// address: 0xe000e008 + /// Auxiliary control register + pub const ACTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// DISMCYCINT + DISMCYCINT: u1, + /// DISDEFWBUF + DISDEFWBUF: u1, + /// DISFOLD + DISFOLD: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// DISFPCA + DISFPCA: u1, + /// DISOOFP + DISOOFP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + }; +}; + +const std = @import("std"); + +pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) { + return @intToPtr(*volatile Mmio(size, PackedT), addr); +} + +pub fn Mmio(comptime size: u8, comptime PackedT: type) type { + if ((size % 8) != 0) + @compileError("size must be divisible by 8!"); + + if (!std.math.isPowerOfTwo(size / 8)) + @compileError("size must encode a power of two number of bytes!"); + + const IntT = std.meta.Int(.unsigned, size); + + if (@sizeOf(PackedT) != (size / 8)) + @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) })); + + return extern struct { + const Self = @This(); + + raw: IntT, + + pub const underlying_type = PackedT; + + pub inline fn read(addr: *volatile Self) PackedT { + return @bitCast(PackedT, addr.raw); + } + + pub inline fn write(addr: *volatile Self, val: PackedT) void { + // This is a workaround for a compiler bug related to miscompilation + // If the tmp var is not used, result location will fuck things up + var tmp = @bitCast(IntT, val); + addr.raw = tmp; + } + + pub inline fn modify(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, field.name) = @field(fields, field.name); + } + write(addr, val); + } + + pub inline fn toggle(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?)); + } + write(addr, val); + } + }; +} + +pub fn MmioInt(comptime size: u8, comptime T: type) type { + return extern struct { + const Self = @This(); + + raw: std.meta.Int(.unsigned, size), + + pub inline fn read(addr: *volatile Self) T { + return @truncate(T, addr.raw); + } + + pub inline fn modify(addr: *volatile Self, val: T) void { + const Int = std.meta.Int(.unsigned, size); + const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1); + + var tmp = addr.raw; + addr.raw = (tmp & mask) | val; + } + }; +} + +pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) { + return @intToPtr(*volatile MmioInt(size, T), addr); +} + +const InterruptVector = extern union { + C: fn () callconv(.C) void, + Naked: fn () callconv(.Naked) void, + // Interrupt is not supported on arm +}; + +const unhandled = InterruptVector{ + .C = struct { + fn tmp() callconv(.C) noreturn { + @panic("unhandled interrupt"); + } + }.tmp, +}; diff --git a/src/modules/chips/stm32f429/stm32f429.zig b/src/modules/chips/stm32f429/stm32f429.zig new file mode 100644 index 0000000..737a83f --- /dev/null +++ b/src/modules/chips/stm32f429/stm32f429.zig @@ -0,0 +1,78 @@ +//! For now we keep all clock settings on the chip defaults. +//! This code should work with all the STM32F42xx line +//! +//! Specifically, TIM6 is running on a 16 MHz clock, +//! HSI = 16 MHz is the SYSCLK after reset +//! default AHB prescaler = /1 (= values 0..7): +//! +//! ``` +//! regs.RCC.CFGR.modify(.{ .HPRE = 0 }); +//! ``` +//! +//! so also HCLK = 16 MHz. +//! And with the default APB1 prescaler = /1: +//! +//! ``` +//! regs.RCC.CFGR.modify(.{ .PPRE1 = 0 }); +//! ``` +//! +//! results in PCLK1 = 16 MHz. +//! +//! TODO: add more clock calculations when adding Uart + +const std = @import("std"); +const micro = @import("microzig"); +const chip = @import("registers.zig"); +const regs = chip.registers; + +pub usingnamespace chip; + +pub fn parsePin(comptime spec: []const u8) type { + const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme."; + + if (spec[0] != 'P') + @compileError(invalid_format_msg); + if (spec[1] < 'A' or spec[1] > 'K') + @compileError(invalid_format_msg); + + const pin_number: comptime_int = std.fmt.parseInt(u4, spec[2..], 10) catch @compileError(invalid_format_msg); + + return struct { + /// 'A'...'K' + const gpio_port_name = spec[1..2]; + const gpio_port = @field(regs, "GPIO" ++ gpio_port_name); + const suffix = std.fmt.comptimePrint("{d}", .{pin_number}); + }; +} + +fn setRegField(reg: anytype, comptime field_name: anytype, value: anytype) void { + var temp = reg.read(); + @field(temp, field_name) = value; + reg.write(temp); +} + +pub const gpio = struct { + pub fn setOutput(comptime pin: type) void { + setRegField(regs.RCC.AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1); + setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b01); + } + + pub fn setInput(comptime pin: type) void { + setRegField(regs.RCC.AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1); + setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b00); + } + + pub fn read(comptime pin: type) micro.gpio.State { + const idr_reg = pin.gpio_port.IDR; + const reg_value = @field(idr_reg.read(), "IDR" ++ pin.suffix); // TODO extract to getRegField()? + return @intToEnum(micro.gpio.State, reg_value); + } + + pub fn write(comptime pin: type, state: micro.gpio.State) void { + _ = pin; + switch (state) { + .low => setRegField(pin.gpio_port.BSRR, "BR" ++ pin.suffix, 1), + .high => setRegField(pin.gpio_port.BSRR, "BS" ++ pin.suffix, 1), + } + } +}; diff --git a/tests/blinky.zig b/tests/blinky.zig index 543f4da..bac49c8 100644 --- a/tests/blinky.zig +++ b/tests/blinky.zig @@ -7,6 +7,7 @@ const led_pin = if (micro.config.has_board) .@"mbed LPC1768" => micro.Pin("LED-1"), .@"STM32F3DISCOVERY" => micro.Pin("LD3"), .@"STM32F4DISCOVERY" => micro.Pin("LD5"), + .@"STM32F429IDISCOVERY" => micro.Pin("LD4"), else => @compileError("unknown board"), } else switch (micro.config.chip_name) {