diff --git a/board-support/stmicro-stm32/LICENSE b/board-support/stmicro-stm32/LICENSE
new file mode 100644
index 0000000..4818f98
--- /dev/null
+++ b/board-support/stmicro-stm32/LICENSE
@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) 2022 Zig Embedded Group
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
diff --git a/board-support/stmicro-stm32/README.adoc b/board-support/stmicro-stm32/README.adoc
new file mode 100644
index 0000000..1635320
--- /dev/null
+++ b/board-support/stmicro-stm32/README.adoc
@@ -0,0 +1,14 @@
+= stm32
+
+HALs and register definitions for stm32 (STMicro) devices
+
+== What version of Zig to use
+
+Right now we are following https://ziglang.org/download/[master], but once 0.11.0 is released, we will be switching to the latest stable version of Zig.
+
+== stm32 boards that renode supports:
+
+- blue pill (stm32f103)
+- nucleo 64 (stm32f103)
+- f4 discovery
+- f7 discovery
diff --git a/board-support/stmicro-stm32/build.zig b/board-support/stmicro-stm32/build.zig
new file mode 100644
index 0000000..4105782
--- /dev/null
+++ b/board-support/stmicro-stm32/build.zig
@@ -0,0 +1,259 @@
+const std = @import("std");
+const microzig = @import("root").dependencies.imports.microzig; // HACK: Please import MicroZig always under the name `microzig`. Otherwise the RP2040 module will fail to be properly imported.
+
+fn root() []const u8 {
+ return comptime (std.fs.path.dirname(@src().file) orelse ".");
+}
+const build_root = root();
+
+const KiB = 1024;
+
+////////////////////////////////////////
+// MicroZig Gen 2 Interface //
+////////////////////////////////////////
+
+pub fn build(b: *std.Build) !void {
+ _ = b;
+ // Dummy func to make package manager happy
+}
+
+pub const chips = struct {
+ pub const stm32f103x8 = .{
+ .preferred_format = .elf,
+ .chip = .{
+ .name = "STM32F103",
+ .cpu = .cortex_m3,
+ .memory_regions = &.{
+ .{ .offset = 0x08000000, .length = 64 * KiB, .kind = .flash },
+ .{ .offset = 0x20000000, .length = 20 * KiB, .kind = .ram },
+ },
+ .register_definition = .{
+ .json = .{ .cwd_relative = build_root ++ "/src/chips/STM32F103.json" },
+ },
+ },
+ .hal = .{
+ .source_file = .{ .cwd_relative = build_root ++ "/src/hals/STM32F103/hal.zig" },
+ },
+ };
+
+ pub const stm32f303vc = .{
+ .preferred_format = .elf,
+ .chip = .{
+ .name = "STM32F303",
+ .cpu = .cortex_m4,
+ .memory_regions = &.{
+ .{ .offset = 0x08000000, .length = 256 * KiB, .kind = .flash },
+ .{ .offset = 0x20000000, .length = 40 * KiB, .kind = .ram },
+ },
+ .register_definition = .{
+ .json = .{ .cwd_relative = build_root ++ "/src/chips/STM32F303.json" },
+ },
+ },
+ };
+
+ pub const stm32f407vg = .{
+ .preferred_format = .elf,
+ .chip = .{
+ .name = "STM32F407",
+ .cpu = .cortex_m4,
+ .memory_regions = &.{
+ .{ .offset = 0x08000000, .length = 1024 * KiB, .kind = .flash },
+ .{ .offset = 0x20000000, .length = 128 * KiB, .kind = .ram },
+ .{ .offset = 0x10000000, .length = 64 * KiB, .kind = .ram }, // CCM RAM
+ },
+ .register_definition = .{
+ .json = .{ .cwd_relative = build_root ++ "/src/chips/STM32F407.json" },
+ },
+ },
+ };
+
+ pub const stm32f429zit6u = .{
+ .preferred_format = .elf,
+ .chip = .{
+ .name = "STM32F429",
+ .cpu = .cortex_m4,
+ .memory_regions = &.{
+ .{ .offset = 0x08000000, .length = 2048 * KiB, .kind = .flash },
+ .{ .offset = 0x20000000, .length = 192 * KiB, .kind = .ram },
+ .{ .offset = 0x10000000, .length = 64 * KiB, .kind = .ram }, // CCM RAM
+ },
+ .register_definition = .{
+ .json = .{ .cwd_relative = build_root ++ "/src/chips/STM32F429.json" },
+ },
+ },
+ };
+
+ // All STM32L0x1 series MCUs differ only in memory size. So we create a comptime function
+ // to generate all MCU variants as per https://www.st.com/en/microcontrollers-microprocessors/stm32l0x1.html
+ fn stm32l0x1(comptime rom_size: u64, comptime ram_size: u64) microzig.Target {
+ return microzig.Target{
+ .preferred_format = .elf,
+ .chip = .{
+ .name = "STM32L0x1",
+ .cpu = .cortex_m0plus,
+ .memory_regions = &.{
+ .{ .offset = 0x08000000, .length = rom_size, .kind = .flash },
+ .{ .offset = 0x20000000, .length = ram_size, .kind = .ram },
+ },
+ .register_definition = .{
+ .svd = .{ .cwd_relative = build_root ++ "/src/chips/STM32L0x1.svd" },
+ },
+ },
+ };
+ }
+
+ pub const stm32l011x3 = stm32l0x1(8 * KiB, 2 * KiB);
+
+ pub const stm32l011x4 = stm32l0x1(16 * KiB, 2 * KiB);
+ pub const stm32l021x4 = stm32l0x1(16 * KiB, 2 * KiB);
+ pub const stm32l031x4 = stm32l0x1(16 * KiB, 8 * KiB);
+
+ pub const stm32l031x6 = stm32l0x1(32 * KiB, 8 * KiB);
+ pub const stm32l041x6 = stm32l0x1(32 * KiB, 8 * KiB);
+ pub const stm32l051x6 = stm32l0x1(32 * KiB, 8 * KiB);
+
+ pub const stm32l051x8 = stm32l0x1(64 * KiB, 8 * KiB);
+ pub const stm32l071x8 = stm32l0x1(64 * KiB, 20 * KiB);
+
+ pub const stm32l071xb = stm32l0x1(128 * KiB, 20 * KiB);
+ pub const stm32l081cb = stm32l0x1(128 * KiB, 20 * KiB);
+
+ pub const stm32l071xz = stm32l0x1(192 * KiB, 20 * KiB);
+ pub const stm32l081xz = stm32l0x1(192 * KiB, 20 * KiB);
+
+ // All STM32L0x2 series MCUs differ only in memory size. So we create a comptime function
+ // to generate all MCU variants as per https://www.st.com/en/microcontrollers-microprocessors/stm32l0x2.html
+ fn stm32l0x2(comptime rom_size: u64, comptime ram_size: u64) microzig.Target {
+ return microzig.Target{
+ .preferred_format = .elf,
+ .chip = .{
+ .name = "STM32L0x2",
+ .cpu = .cortex_m0plus,
+ .memory_regions = &.{
+ .{ .offset = 0x08000000, .length = rom_size, .kind = .flash },
+ .{ .offset = 0x20000000, .length = ram_size, .kind = .ram },
+ },
+ .register_definition = .{
+ .svd = .{ .cwd_relative = build_root ++ "/src/chips/STM32L0x2.svd" },
+ },
+ },
+ };
+ }
+
+ pub const stm32l052x6 = stm32l0x2(32 * KiB, 8 * KiB);
+
+ pub const stm32l052x8 = stm32l0x2(64 * KiB, 8 * KiB);
+ pub const stm32l062x8 = stm32l0x2(64 * KiB, 8 * KiB);
+ pub const stm32l072v8 = stm32l0x2(64 * KiB, 20 * KiB);
+
+ pub const stm32l072xb = stm32l0x2(128 * KiB, 20 * KiB);
+ pub const stm32l082xb = stm32l0x2(128 * KiB, 20 * KiB);
+
+ pub const stm32l072xz = stm32l0x2(192 * KiB, 20 * KiB);
+ pub const stm32l082xz = stm32l0x2(192 * KiB, 20 * KiB);
+
+ // All STM32L0x2 series MCUs differ only in memory size. So we create a comptime function
+ // to generate all MCU variants as per https://www.st.com/en/microcontrollers-microprocessors/stm32l0x3.html
+ fn stm32l0x3(comptime rom_size: u64, comptime ram_size: u64) microzig.Target {
+ return microzig.Target{
+ .preferred_format = .elf,
+ .chip = .{
+ .name = "STM32L0x3",
+ .cpu = .cortex_m0plus,
+ .memory_regions = &.{
+ .{ .offset = 0x08000000, .length = rom_size, .kind = .flash },
+ .{ .offset = 0x20000000, .length = ram_size, .kind = .ram },
+ },
+ .register_definition = .{
+ .svd = .{ .cwd_relative = build_root ++ "/src/chips/STM32L0x3.svd" },
+ },
+ },
+ };
+ }
+
+ pub const stm32l053x6 = stm32l0x2(32 * KiB, 8 * KiB);
+
+ pub const stm32l053x8 = stm32l0x2(64 * KiB, 8 * KiB);
+ pub const stm32l063x8 = stm32l0x2(64 * KiB, 8 * KiB);
+
+ pub const stm32l073v8 = stm32l0x2(64 * KiB, 20 * KiB);
+ pub const stm32l083v8 = stm32l0x2(64 * KiB, 20 * KiB);
+
+ pub const stm32l073xb = stm32l0x2(128 * KiB, 20 * KiB);
+ pub const stm32l083xb = stm32l0x2(128 * KiB, 20 * KiB);
+
+ pub const stm32l073xz = stm32l0x2(192 * KiB, 20 * KiB);
+ pub const stm32l083xz = stm32l0x2(192 * KiB, 20 * KiB);
+};
+
+pub const boards = struct {
+ pub const stm32f3discovery = .{
+ .preferred_format = .elf,
+ .chip = chips.stm32f303vc.chip,
+ .board = .{
+ .name = "STM32F3DISCOVERY",
+ .source_file = .{ .path = build_root ++ "/src/boards/STM32F3DISCOVERY.zig" },
+ },
+ };
+
+ pub const stm32f4discovery = .{
+ .preferred_format = .elf,
+ .chip = chips.stm32f407vg.chip,
+ .board = .{
+ .name = "STM32F4DISCOVERY",
+ .source_file = .{ .path = build_root ++ "/src/boards/STM32F4DISCOVERY.zig" },
+ },
+ };
+
+ pub const stm3240geval = .{
+ .preferred_format = .elf,
+ .chip = chips.stm32f407vg.chip,
+ .board = .{
+ .name = "STM3240G_EVAL",
+ .source_file = .{ .path = build_root ++ "/src/boards/STM3240G_EVAL.zig" },
+ },
+ };
+
+ pub const stm32f429idiscovery = .{
+ .preferred_format = .elf,
+ .chip = chips.stm32f429zit6u.chip,
+ .board = .{
+ .name = "STM32F429IDISCOVERY",
+ .source_file = .{ .path = build_root ++ "/src/boards/STM32F429IDISCOVERY.zig" },
+ },
+ };
+};
+
+// pub fn build(b: *std.build.Builder) void {
+// _ = b;
+// const optimize = b.standardOptimizeOption(.{});
+// inline for (@typeInfo(boards).Struct.decls) |decl| {
+// if (!decl.is_pub)
+// continue;
+
+// const exe = microzig.addEmbeddedExecutable(b, .{
+// .name = @field(boards, decl.name).name ++ ".minimal",
+// .source_file = .{
+// .path = "test/programs/minimal.zig",
+// },
+// .backing = .{ .board = @field(boards, decl.name) },
+// .optimize = optimize,
+// });
+// exe.installArtifact(b);
+// }
+
+// inline for (@typeInfo(chips).Struct.decls) |decl| {
+// if (!decl.is_pub)
+// continue;
+
+// const exe = microzig.addEmbeddedExecutable(b, .{
+// .name = @field(chips, decl.name).name ++ ".minimal",
+// .source_file = .{
+// .path = "test/programs/minimal.zig",
+// },
+// .backing = .{ .chip = @field(chips, decl.name) },
+// .optimize = optimize,
+// });
+// exe.installArtifact(b);
+// }
+// }
diff --git a/board-support/stmicro-stm32/src/boards/STM3240G_EVAL.zig b/board-support/stmicro-stm32/src/boards/STM3240G_EVAL.zig
new file mode 100644
index 0000000..6261142
--- /dev/null
+++ b/board-support/stmicro-stm32/src/boards/STM3240G_EVAL.zig
@@ -0,0 +1,10 @@
+pub const pin_map = .{
+ // LD1 green
+ .LD1 = "PG6",
+ // LD2 orange
+ .LD2 = "PG8",
+ // LD3 red
+ .LD3 = "PI9",
+ // LD4 blue
+ .LD4 = "PC7",
+};
diff --git a/board-support/stmicro-stm32/src/boards/STM32F3DISCOVERY.zig b/board-support/stmicro-stm32/src/boards/STM32F3DISCOVERY.zig
new file mode 100644
index 0000000..9394bb8
--- /dev/null
+++ b/board-support/stmicro-stm32/src/boards/STM32F3DISCOVERY.zig
@@ -0,0 +1,37 @@
+pub const micro = @import("microzig");
+
+pub const cpu_frequency = 8_000_000;
+
+pub const pin_map = .{
+ // circle of LEDs, connected to GPIOE bits 8..15
+
+ // NW blue
+ .LD4 = "PE8",
+ // N red
+ .LD3 = "PE9",
+ // NE orange
+ .LD5 = "PE10",
+ // E green
+ .LD7 = "PE11",
+ // SE blue
+ .LD9 = "PE12",
+ // S red
+ .LD10 = "PE13",
+ // SW orange
+ .LD8 = "PE14",
+ // W green
+ .LD6 = "PE15",
+};
+
+pub fn debug_write(string: []const u8) void {
+ const uart1 = micro.core.experimental.Uart(1, .{}).get_or_init(.{
+ .baud_rate = 9600,
+ .data_bits = .eight,
+ .parity = null,
+ .stop_bits = .one,
+ }) catch unreachable;
+
+ const writer = uart1.writer();
+ _ = writer.write(string) catch unreachable;
+ uart1.internal.txflush();
+}
diff --git a/board-support/stmicro-stm32/src/boards/STM32F429IDISCOVERY.zig b/board-support/stmicro-stm32/src/boards/STM32F429IDISCOVERY.zig
new file mode 100644
index 0000000..034295a
--- /dev/null
+++ b/board-support/stmicro-stm32/src/boards/STM32F429IDISCOVERY.zig
@@ -0,0 +1,12 @@
+pub const cpu_frequency = 16_000_000;
+
+pub const pin_map = .{
+ // LEDs, connected to GPIOG bits 13, 14
+ // green
+ .LD3 = "PG13",
+ // red
+ .LD4 = "PG14",
+
+ // User button
+ .B1 = "PA0",
+};
diff --git a/board-support/stmicro-stm32/src/boards/STM32F4DISCOVERY.zig b/board-support/stmicro-stm32/src/boards/STM32F4DISCOVERY.zig
new file mode 100644
index 0000000..062f334
--- /dev/null
+++ b/board-support/stmicro-stm32/src/boards/STM32F4DISCOVERY.zig
@@ -0,0 +1,14 @@
+pub const pin_map = .{
+ // LED cross, connected to GPIOD bits 12..15
+ // N orange
+ .LD3 = "PD13",
+ // E red
+ .LD5 = "PD14",
+ // S blue
+ .LD6 = "PD15",
+ // W green
+ .LD4 = "PD12",
+
+ // User button
+ .B2 = "PA0",
+};
diff --git a/board-support/stmicro-stm32/src/chips/STM32F103.json b/board-support/stmicro-stm32/src/chips/STM32F103.json
new file mode 100644
index 0000000..45b99d1
--- /dev/null
+++ b/board-support/stmicro-stm32/src/chips/STM32F103.json
@@ -0,0 +1,27474 @@
+{
+ "version": "0.1.0",
+ "types": {
+ "peripherals": {
+ "FSMC": {
+ "description": "Flexible static memory controller",
+ "children": {
+ "registers": {
+ "BCR1": {
+ "description": "SRAM/NOR-Flash chip-select control register\n 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 12496,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CBURSTRW": {
+ "description": "CBURSTRW",
+ "offset": 19,
+ "size": 1
+ },
+ "ASYNCWAIT": {
+ "description": "ASYNCWAIT",
+ "offset": 15,
+ "size": 1
+ },
+ "EXTMOD": {
+ "description": "EXTMOD",
+ "offset": 14,
+ "size": 1
+ },
+ "WAITEN": {
+ "description": "WAITEN",
+ "offset": 13,
+ "size": 1
+ },
+ "WREN": {
+ "description": "WREN",
+ "offset": 12,
+ "size": 1
+ },
+ "WAITCFG": {
+ "description": "WAITCFG",
+ "offset": 11,
+ "size": 1
+ },
+ "WAITPOL": {
+ "description": "WAITPOL",
+ "offset": 9,
+ "size": 1
+ },
+ "BURSTEN": {
+ "description": "BURSTEN",
+ "offset": 8,
+ "size": 1
+ },
+ "FACCEN": {
+ "description": "FACCEN",
+ "offset": 6,
+ "size": 1
+ },
+ "MWID": {
+ "description": "MWID",
+ "offset": 4,
+ "size": 2
+ },
+ "MTYP": {
+ "description": "MTYP",
+ "offset": 2,
+ "size": 2
+ },
+ "MUXEN": {
+ "description": "MUXEN",
+ "offset": 1,
+ "size": 1
+ },
+ "MBKEN": {
+ "description": "MBKEN",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BTR1": {
+ "description": "SRAM/NOR-Flash chip-select timing register\n 1",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "BUSTURN": {
+ "description": "BUSTURN",
+ "offset": 16,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "BCR2": {
+ "description": "SRAM/NOR-Flash chip-select control register\n 2",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 12496,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CBURSTRW": {
+ "description": "CBURSTRW",
+ "offset": 19,
+ "size": 1
+ },
+ "ASYNCWAIT": {
+ "description": "ASYNCWAIT",
+ "offset": 15,
+ "size": 1
+ },
+ "EXTMOD": {
+ "description": "EXTMOD",
+ "offset": 14,
+ "size": 1
+ },
+ "WAITEN": {
+ "description": "WAITEN",
+ "offset": 13,
+ "size": 1
+ },
+ "WREN": {
+ "description": "WREN",
+ "offset": 12,
+ "size": 1
+ },
+ "WAITCFG": {
+ "description": "WAITCFG",
+ "offset": 11,
+ "size": 1
+ },
+ "WRAPMOD": {
+ "description": "WRAPMOD",
+ "offset": 10,
+ "size": 1
+ },
+ "WAITPOL": {
+ "description": "WAITPOL",
+ "offset": 9,
+ "size": 1
+ },
+ "BURSTEN": {
+ "description": "BURSTEN",
+ "offset": 8,
+ "size": 1
+ },
+ "FACCEN": {
+ "description": "FACCEN",
+ "offset": 6,
+ "size": 1
+ },
+ "MWID": {
+ "description": "MWID",
+ "offset": 4,
+ "size": 2
+ },
+ "MTYP": {
+ "description": "MTYP",
+ "offset": 2,
+ "size": 2
+ },
+ "MUXEN": {
+ "description": "MUXEN",
+ "offset": 1,
+ "size": 1
+ },
+ "MBKEN": {
+ "description": "MBKEN",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BTR2": {
+ "description": "SRAM/NOR-Flash chip-select timing register\n 2",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "BUSTURN": {
+ "description": "BUSTURN",
+ "offset": 16,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "BCR3": {
+ "description": "SRAM/NOR-Flash chip-select control register\n 3",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 12496,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CBURSTRW": {
+ "description": "CBURSTRW",
+ "offset": 19,
+ "size": 1
+ },
+ "ASYNCWAIT": {
+ "description": "ASYNCWAIT",
+ "offset": 15,
+ "size": 1
+ },
+ "EXTMOD": {
+ "description": "EXTMOD",
+ "offset": 14,
+ "size": 1
+ },
+ "WAITEN": {
+ "description": "WAITEN",
+ "offset": 13,
+ "size": 1
+ },
+ "WREN": {
+ "description": "WREN",
+ "offset": 12,
+ "size": 1
+ },
+ "WAITCFG": {
+ "description": "WAITCFG",
+ "offset": 11,
+ "size": 1
+ },
+ "WRAPMOD": {
+ "description": "WRAPMOD",
+ "offset": 10,
+ "size": 1
+ },
+ "WAITPOL": {
+ "description": "WAITPOL",
+ "offset": 9,
+ "size": 1
+ },
+ "BURSTEN": {
+ "description": "BURSTEN",
+ "offset": 8,
+ "size": 1
+ },
+ "FACCEN": {
+ "description": "FACCEN",
+ "offset": 6,
+ "size": 1
+ },
+ "MWID": {
+ "description": "MWID",
+ "offset": 4,
+ "size": 2
+ },
+ "MTYP": {
+ "description": "MTYP",
+ "offset": 2,
+ "size": 2
+ },
+ "MUXEN": {
+ "description": "MUXEN",
+ "offset": 1,
+ "size": 1
+ },
+ "MBKEN": {
+ "description": "MBKEN",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BTR3": {
+ "description": "SRAM/NOR-Flash chip-select timing register\n 3",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "BUSTURN": {
+ "description": "BUSTURN",
+ "offset": 16,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "BCR4": {
+ "description": "SRAM/NOR-Flash chip-select control register\n 4",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 12496,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CBURSTRW": {
+ "description": "CBURSTRW",
+ "offset": 19,
+ "size": 1
+ },
+ "ASYNCWAIT": {
+ "description": "ASYNCWAIT",
+ "offset": 15,
+ "size": 1
+ },
+ "EXTMOD": {
+ "description": "EXTMOD",
+ "offset": 14,
+ "size": 1
+ },
+ "WAITEN": {
+ "description": "WAITEN",
+ "offset": 13,
+ "size": 1
+ },
+ "WREN": {
+ "description": "WREN",
+ "offset": 12,
+ "size": 1
+ },
+ "WAITCFG": {
+ "description": "WAITCFG",
+ "offset": 11,
+ "size": 1
+ },
+ "WRAPMOD": {
+ "description": "WRAPMOD",
+ "offset": 10,
+ "size": 1
+ },
+ "WAITPOL": {
+ "description": "WAITPOL",
+ "offset": 9,
+ "size": 1
+ },
+ "BURSTEN": {
+ "description": "BURSTEN",
+ "offset": 8,
+ "size": 1
+ },
+ "FACCEN": {
+ "description": "FACCEN",
+ "offset": 6,
+ "size": 1
+ },
+ "MWID": {
+ "description": "MWID",
+ "offset": 4,
+ "size": 2
+ },
+ "MTYP": {
+ "description": "MTYP",
+ "offset": 2,
+ "size": 2
+ },
+ "MUXEN": {
+ "description": "MUXEN",
+ "offset": 1,
+ "size": 1
+ },
+ "MBKEN": {
+ "description": "MBKEN",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BTR4": {
+ "description": "SRAM/NOR-Flash chip-select timing register\n 4",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "BUSTURN": {
+ "description": "BUSTURN",
+ "offset": 16,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "PCR2": {
+ "description": "PC Card/NAND Flash control register\n 2",
+ "offset": 96,
+ "size": 32,
+ "reset_value": 24,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ECCPS": {
+ "description": "ECCPS",
+ "offset": 17,
+ "size": 3
+ },
+ "TAR": {
+ "description": "TAR",
+ "offset": 13,
+ "size": 4
+ },
+ "TCLR": {
+ "description": "TCLR",
+ "offset": 9,
+ "size": 4
+ },
+ "ECCEN": {
+ "description": "ECCEN",
+ "offset": 6,
+ "size": 1
+ },
+ "PWID": {
+ "description": "PWID",
+ "offset": 4,
+ "size": 2
+ },
+ "PTYP": {
+ "description": "PTYP",
+ "offset": 3,
+ "size": 1
+ },
+ "PBKEN": {
+ "description": "PBKEN",
+ "offset": 2,
+ "size": 1
+ },
+ "PWAITEN": {
+ "description": "PWAITEN",
+ "offset": 1,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR2": {
+ "description": "FIFO status and interrupt register\n 2",
+ "offset": 100,
+ "size": 32,
+ "reset_value": 64,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEMPT": {
+ "description": "FEMPT",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "IFEN": {
+ "description": "IFEN",
+ "offset": 5,
+ "size": 1
+ },
+ "ILEN": {
+ "description": "ILEN",
+ "offset": 4,
+ "size": 1
+ },
+ "IREN": {
+ "description": "IREN",
+ "offset": 3,
+ "size": 1
+ },
+ "IFS": {
+ "description": "IFS",
+ "offset": 2,
+ "size": 1
+ },
+ "ILS": {
+ "description": "ILS",
+ "offset": 1,
+ "size": 1
+ },
+ "IRS": {
+ "description": "IRS",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PMEM2": {
+ "description": "Common memory space timing register\n 2",
+ "offset": 104,
+ "size": 32,
+ "reset_value": 4244438268,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MEMHIZx": {
+ "description": "MEMHIZx",
+ "offset": 24,
+ "size": 8
+ },
+ "MEMHOLDx": {
+ "description": "MEMHOLDx",
+ "offset": 16,
+ "size": 8
+ },
+ "MEMWAITx": {
+ "description": "MEMWAITx",
+ "offset": 8,
+ "size": 8
+ },
+ "MEMSETx": {
+ "description": "MEMSETx",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "PATT2": {
+ "description": "Attribute memory space timing register\n 2",
+ "offset": 108,
+ "size": 32,
+ "reset_value": 4244438268,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ATTHIZx": {
+ "description": "Attribute memory x databus HiZ\n time",
+ "offset": 24,
+ "size": 8
+ },
+ "ATTHOLDx": {
+ "description": "Attribute memory x hold\n time",
+ "offset": 16,
+ "size": 8
+ },
+ "ATTWAITx": {
+ "description": "Attribute memory x wait\n time",
+ "offset": 8,
+ "size": 8
+ },
+ "ATTSETx": {
+ "description": "Attribute memory x setup\n time",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "ECCR2": {
+ "description": "ECC result register 2",
+ "offset": 116,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "ECCx": {
+ "description": "ECC result",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "PCR3": {
+ "description": "PC Card/NAND Flash control register\n 3",
+ "offset": 128,
+ "size": 32,
+ "reset_value": 24,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ECCPS": {
+ "description": "ECCPS",
+ "offset": 17,
+ "size": 3
+ },
+ "TAR": {
+ "description": "TAR",
+ "offset": 13,
+ "size": 4
+ },
+ "TCLR": {
+ "description": "TCLR",
+ "offset": 9,
+ "size": 4
+ },
+ "ECCEN": {
+ "description": "ECCEN",
+ "offset": 6,
+ "size": 1
+ },
+ "PWID": {
+ "description": "PWID",
+ "offset": 4,
+ "size": 2
+ },
+ "PTYP": {
+ "description": "PTYP",
+ "offset": 3,
+ "size": 1
+ },
+ "PBKEN": {
+ "description": "PBKEN",
+ "offset": 2,
+ "size": 1
+ },
+ "PWAITEN": {
+ "description": "PWAITEN",
+ "offset": 1,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR3": {
+ "description": "FIFO status and interrupt register\n 3",
+ "offset": 132,
+ "size": 32,
+ "reset_value": 64,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEMPT": {
+ "description": "FEMPT",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "IFEN": {
+ "description": "IFEN",
+ "offset": 5,
+ "size": 1
+ },
+ "ILEN": {
+ "description": "ILEN",
+ "offset": 4,
+ "size": 1
+ },
+ "IREN": {
+ "description": "IREN",
+ "offset": 3,
+ "size": 1
+ },
+ "IFS": {
+ "description": "IFS",
+ "offset": 2,
+ "size": 1
+ },
+ "ILS": {
+ "description": "ILS",
+ "offset": 1,
+ "size": 1
+ },
+ "IRS": {
+ "description": "IRS",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PMEM3": {
+ "description": "Common memory space timing register\n 3",
+ "offset": 136,
+ "size": 32,
+ "reset_value": 4244438268,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MEMHIZx": {
+ "description": "MEMHIZx",
+ "offset": 24,
+ "size": 8
+ },
+ "MEMHOLDx": {
+ "description": "MEMHOLDx",
+ "offset": 16,
+ "size": 8
+ },
+ "MEMWAITx": {
+ "description": "MEMWAITx",
+ "offset": 8,
+ "size": 8
+ },
+ "MEMSETx": {
+ "description": "MEMSETx",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "PATT3": {
+ "description": "Attribute memory space timing register\n 3",
+ "offset": 140,
+ "size": 32,
+ "reset_value": 4244438268,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ATTHIZx": {
+ "description": "ATTHIZx",
+ "offset": 24,
+ "size": 8
+ },
+ "ATTHOLDx": {
+ "description": "ATTHOLDx",
+ "offset": 16,
+ "size": 8
+ },
+ "ATTWAITx": {
+ "description": "ATTWAITx",
+ "offset": 8,
+ "size": 8
+ },
+ "ATTSETx": {
+ "description": "ATTSETx",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "ECCR3": {
+ "description": "ECC result register 3",
+ "offset": 148,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "ECCx": {
+ "description": "ECCx",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "PCR4": {
+ "description": "PC Card/NAND Flash control register\n 4",
+ "offset": 160,
+ "size": 32,
+ "reset_value": 24,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ECCPS": {
+ "description": "ECCPS",
+ "offset": 17,
+ "size": 3
+ },
+ "TAR": {
+ "description": "TAR",
+ "offset": 13,
+ "size": 4
+ },
+ "TCLR": {
+ "description": "TCLR",
+ "offset": 9,
+ "size": 4
+ },
+ "ECCEN": {
+ "description": "ECCEN",
+ "offset": 6,
+ "size": 1
+ },
+ "PWID": {
+ "description": "PWID",
+ "offset": 4,
+ "size": 2
+ },
+ "PTYP": {
+ "description": "PTYP",
+ "offset": 3,
+ "size": 1
+ },
+ "PBKEN": {
+ "description": "PBKEN",
+ "offset": 2,
+ "size": 1
+ },
+ "PWAITEN": {
+ "description": "PWAITEN",
+ "offset": 1,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR4": {
+ "description": "FIFO status and interrupt register\n 4",
+ "offset": 164,
+ "size": 32,
+ "reset_value": 64,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEMPT": {
+ "description": "FEMPT",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "IFEN": {
+ "description": "IFEN",
+ "offset": 5,
+ "size": 1
+ },
+ "ILEN": {
+ "description": "ILEN",
+ "offset": 4,
+ "size": 1
+ },
+ "IREN": {
+ "description": "IREN",
+ "offset": 3,
+ "size": 1
+ },
+ "IFS": {
+ "description": "IFS",
+ "offset": 2,
+ "size": 1
+ },
+ "ILS": {
+ "description": "ILS",
+ "offset": 1,
+ "size": 1
+ },
+ "IRS": {
+ "description": "IRS",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PMEM4": {
+ "description": "Common memory space timing register\n 4",
+ "offset": 168,
+ "size": 32,
+ "reset_value": 4244438268,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MEMHIZx": {
+ "description": "MEMHIZx",
+ "offset": 24,
+ "size": 8
+ },
+ "MEMHOLDx": {
+ "description": "MEMHOLDx",
+ "offset": 16,
+ "size": 8
+ },
+ "MEMWAITx": {
+ "description": "MEMWAITx",
+ "offset": 8,
+ "size": 8
+ },
+ "MEMSETx": {
+ "description": "MEMSETx",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "PATT4": {
+ "description": "Attribute memory space timing register\n 4",
+ "offset": 172,
+ "size": 32,
+ "reset_value": 4244438268,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ATTHIZx": {
+ "description": "ATTHIZx",
+ "offset": 24,
+ "size": 8
+ },
+ "ATTHOLDx": {
+ "description": "ATTHOLDx",
+ "offset": 16,
+ "size": 8
+ },
+ "ATTWAITx": {
+ "description": "ATTWAITx",
+ "offset": 8,
+ "size": 8
+ },
+ "ATTSETx": {
+ "description": "ATTSETx",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "PIO4": {
+ "description": "I/O space timing register 4",
+ "offset": 176,
+ "size": 32,
+ "reset_value": 4244438268,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IOHIZx": {
+ "description": "IOHIZx",
+ "offset": 24,
+ "size": 8
+ },
+ "IOHOLDx": {
+ "description": "IOHOLDx",
+ "offset": 16,
+ "size": 8
+ },
+ "IOWAITx": {
+ "description": "IOWAITx",
+ "offset": 8,
+ "size": 8
+ },
+ "IOSETx": {
+ "description": "IOSETx",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "BWTR1": {
+ "description": "SRAM/NOR-Flash write timing registers\n 1",
+ "offset": 260,
+ "size": 32,
+ "reset_value": 268435455,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "BWTR2": {
+ "description": "SRAM/NOR-Flash write timing registers\n 2",
+ "offset": 268,
+ "size": 32,
+ "reset_value": 268435455,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "BWTR3": {
+ "description": "SRAM/NOR-Flash write timing registers\n 3",
+ "offset": 276,
+ "size": 32,
+ "reset_value": 268435455,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "BWTR4": {
+ "description": "SRAM/NOR-Flash write timing registers\n 4",
+ "offset": 284,
+ "size": 32,
+ "reset_value": 268435455,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "PWR": {
+ "description": "Power control",
+ "children": {
+ "registers": {
+ "CR": {
+ "description": "Power control register\n (PWR_CR)",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LPDS": {
+ "description": "Low Power Deep Sleep",
+ "offset": 0,
+ "size": 1
+ },
+ "PDDS": {
+ "description": "Power Down Deep Sleep",
+ "offset": 1,
+ "size": 1
+ },
+ "CWUF": {
+ "description": "Clear Wake-up Flag",
+ "offset": 2,
+ "size": 1
+ },
+ "CSBF": {
+ "description": "Clear STANDBY Flag",
+ "offset": 3,
+ "size": 1
+ },
+ "PVDE": {
+ "description": "Power Voltage Detector\n Enable",
+ "offset": 4,
+ "size": 1
+ },
+ "PLS": {
+ "description": "PVD Level Selection",
+ "offset": 5,
+ "size": 3
+ },
+ "DBP": {
+ "description": "Disable Backup Domain write\n protection",
+ "offset": 8,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CSR": {
+ "description": "Power control register\n (PWR_CR)",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "WUF": {
+ "description": "Wake-Up Flag",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SBF": {
+ "description": "STANDBY Flag",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PVDO": {
+ "description": "PVD Output",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EWUP": {
+ "description": "Enable WKUP pin",
+ "offset": 8,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "RCC": {
+ "description": "Reset and clock control",
+ "children": {
+ "registers": {
+ "CR": {
+ "description": "Clock control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 131,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "HSION": {
+ "description": "Internal High Speed clock\n enable",
+ "offset": 0,
+ "size": 1
+ },
+ "HSIRDY": {
+ "description": "Internal High Speed clock ready\n flag",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HSITRIM": {
+ "description": "Internal High Speed clock\n trimming",
+ "offset": 3,
+ "size": 5
+ },
+ "HSICAL": {
+ "description": "Internal High Speed clock\n Calibration",
+ "offset": 8,
+ "size": 8,
+ "access": "read-only"
+ },
+ "HSEON": {
+ "description": "External High Speed clock\n enable",
+ "offset": 16,
+ "size": 1
+ },
+ "HSERDY": {
+ "description": "External High Speed clock ready\n flag",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HSEBYP": {
+ "description": "External High Speed clock\n Bypass",
+ "offset": 18,
+ "size": 1
+ },
+ "CSSON": {
+ "description": "Clock Security System\n enable",
+ "offset": 19,
+ "size": 1
+ },
+ "PLLON": {
+ "description": "PLL enable",
+ "offset": 24,
+ "size": 1
+ },
+ "PLLRDY": {
+ "description": "PLL clock ready flag",
+ "offset": 25,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "CFGR": {
+ "description": "Clock configuration register\n (RCC_CFGR)",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SW": {
+ "description": "System clock Switch",
+ "offset": 0,
+ "size": 2
+ },
+ "SWS": {
+ "description": "System Clock Switch Status",
+ "offset": 2,
+ "size": 2,
+ "access": "read-only"
+ },
+ "HPRE": {
+ "description": "AHB prescaler",
+ "offset": 4,
+ "size": 4
+ },
+ "PPRE1": {
+ "description": "APB Low speed prescaler\n (APB1)",
+ "offset": 8,
+ "size": 3
+ },
+ "PPRE2": {
+ "description": "APB High speed prescaler\n (APB2)",
+ "offset": 11,
+ "size": 3
+ },
+ "ADCPRE": {
+ "description": "ADC prescaler",
+ "offset": 14,
+ "size": 2
+ },
+ "PLLSRC": {
+ "description": "PLL entry clock source",
+ "offset": 16,
+ "size": 1
+ },
+ "PLLXTPRE": {
+ "description": "HSE divider for PLL entry",
+ "offset": 17,
+ "size": 1
+ },
+ "PLLMUL": {
+ "description": "PLL Multiplication Factor",
+ "offset": 18,
+ "size": 4
+ },
+ "OTGFSPRE": {
+ "description": "USB OTG FS prescaler",
+ "offset": 22,
+ "size": 1
+ },
+ "MCO": {
+ "description": "Microcontroller clock\n output",
+ "offset": 24,
+ "size": 3
+ }
+ }
+ }
+ },
+ "CIR": {
+ "description": "Clock interrupt register\n (RCC_CIR)",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LSIRDYF": {
+ "description": "LSI Ready Interrupt flag",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ },
+ "LSERDYF": {
+ "description": "LSE Ready Interrupt flag",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HSIRDYF": {
+ "description": "HSI Ready Interrupt flag",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HSERDYF": {
+ "description": "HSE Ready Interrupt flag",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PLLRDYF": {
+ "description": "PLL Ready Interrupt flag",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "CSSF": {
+ "description": "Clock Security System Interrupt\n flag",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "LSIRDYIE": {
+ "description": "LSI Ready Interrupt Enable",
+ "offset": 8,
+ "size": 1
+ },
+ "LSERDYIE": {
+ "description": "LSE Ready Interrupt Enable",
+ "offset": 9,
+ "size": 1
+ },
+ "HSIRDYIE": {
+ "description": "HSI Ready Interrupt Enable",
+ "offset": 10,
+ "size": 1
+ },
+ "HSERDYIE": {
+ "description": "HSE Ready Interrupt Enable",
+ "offset": 11,
+ "size": 1
+ },
+ "PLLRDYIE": {
+ "description": "PLL Ready Interrupt Enable",
+ "offset": 12,
+ "size": 1
+ },
+ "LSIRDYC": {
+ "description": "LSI Ready Interrupt Clear",
+ "offset": 16,
+ "size": 1,
+ "access": "write-only"
+ },
+ "LSERDYC": {
+ "description": "LSE Ready Interrupt Clear",
+ "offset": 17,
+ "size": 1,
+ "access": "write-only"
+ },
+ "HSIRDYC": {
+ "description": "HSI Ready Interrupt Clear",
+ "offset": 18,
+ "size": 1,
+ "access": "write-only"
+ },
+ "HSERDYC": {
+ "description": "HSE Ready Interrupt Clear",
+ "offset": 19,
+ "size": 1,
+ "access": "write-only"
+ },
+ "PLLRDYC": {
+ "description": "PLL Ready Interrupt Clear",
+ "offset": 20,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CSSC": {
+ "description": "Clock security system interrupt\n clear",
+ "offset": 23,
+ "size": 1,
+ "access": "write-only"
+ }
+ }
+ }
+ },
+ "APB2RSTR": {
+ "description": "APB2 peripheral reset register\n (RCC_APB2RSTR)",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "AFIORST": {
+ "description": "Alternate function I/O\n reset",
+ "offset": 0,
+ "size": 1
+ },
+ "IOPARST": {
+ "description": "IO port A reset",
+ "offset": 2,
+ "size": 1
+ },
+ "IOPBRST": {
+ "description": "IO port B reset",
+ "offset": 3,
+ "size": 1
+ },
+ "IOPCRST": {
+ "description": "IO port C reset",
+ "offset": 4,
+ "size": 1
+ },
+ "IOPDRST": {
+ "description": "IO port D reset",
+ "offset": 5,
+ "size": 1
+ },
+ "IOPERST": {
+ "description": "IO port E reset",
+ "offset": 6,
+ "size": 1
+ },
+ "IOPFRST": {
+ "description": "IO port F reset",
+ "offset": 7,
+ "size": 1
+ },
+ "IOPGRST": {
+ "description": "IO port G reset",
+ "offset": 8,
+ "size": 1
+ },
+ "ADC1RST": {
+ "description": "ADC 1 interface reset",
+ "offset": 9,
+ "size": 1
+ },
+ "ADC2RST": {
+ "description": "ADC 2 interface reset",
+ "offset": 10,
+ "size": 1
+ },
+ "TIM1RST": {
+ "description": "TIM1 timer reset",
+ "offset": 11,
+ "size": 1
+ },
+ "SPI1RST": {
+ "description": "SPI 1 reset",
+ "offset": 12,
+ "size": 1
+ },
+ "TIM8RST": {
+ "description": "TIM8 timer reset",
+ "offset": 13,
+ "size": 1
+ },
+ "USART1RST": {
+ "description": "USART1 reset",
+ "offset": 14,
+ "size": 1
+ },
+ "ADC3RST": {
+ "description": "ADC 3 interface reset",
+ "offset": 15,
+ "size": 1
+ },
+ "TIM9RST": {
+ "description": "TIM9 timer reset",
+ "offset": 19,
+ "size": 1
+ },
+ "TIM10RST": {
+ "description": "TIM10 timer reset",
+ "offset": 20,
+ "size": 1
+ },
+ "TIM11RST": {
+ "description": "TIM11 timer reset",
+ "offset": 21,
+ "size": 1
+ }
+ }
+ }
+ },
+ "APB1RSTR": {
+ "description": "APB1 peripheral reset register\n (RCC_APB1RSTR)",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIM2RST": {
+ "description": "Timer 2 reset",
+ "offset": 0,
+ "size": 1
+ },
+ "TIM3RST": {
+ "description": "Timer 3 reset",
+ "offset": 1,
+ "size": 1
+ },
+ "TIM4RST": {
+ "description": "Timer 4 reset",
+ "offset": 2,
+ "size": 1
+ },
+ "TIM5RST": {
+ "description": "Timer 5 reset",
+ "offset": 3,
+ "size": 1
+ },
+ "TIM6RST": {
+ "description": "Timer 6 reset",
+ "offset": 4,
+ "size": 1
+ },
+ "TIM7RST": {
+ "description": "Timer 7 reset",
+ "offset": 5,
+ "size": 1
+ },
+ "TIM12RST": {
+ "description": "Timer 12 reset",
+ "offset": 6,
+ "size": 1
+ },
+ "TIM13RST": {
+ "description": "Timer 13 reset",
+ "offset": 7,
+ "size": 1
+ },
+ "TIM14RST": {
+ "description": "Timer 14 reset",
+ "offset": 8,
+ "size": 1
+ },
+ "WWDGRST": {
+ "description": "Window watchdog reset",
+ "offset": 11,
+ "size": 1
+ },
+ "SPI2RST": {
+ "description": "SPI2 reset",
+ "offset": 14,
+ "size": 1
+ },
+ "SPI3RST": {
+ "description": "SPI3 reset",
+ "offset": 15,
+ "size": 1
+ },
+ "USART2RST": {
+ "description": "USART 2 reset",
+ "offset": 17,
+ "size": 1
+ },
+ "USART3RST": {
+ "description": "USART 3 reset",
+ "offset": 18,
+ "size": 1
+ },
+ "UART4RST": {
+ "description": "UART 4 reset",
+ "offset": 19,
+ "size": 1
+ },
+ "UART5RST": {
+ "description": "UART 5 reset",
+ "offset": 20,
+ "size": 1
+ },
+ "I2C1RST": {
+ "description": "I2C1 reset",
+ "offset": 21,
+ "size": 1
+ },
+ "I2C2RST": {
+ "description": "I2C2 reset",
+ "offset": 22,
+ "size": 1
+ },
+ "USBRST": {
+ "description": "USB reset",
+ "offset": 23,
+ "size": 1
+ },
+ "CANRST": {
+ "description": "CAN reset",
+ "offset": 25,
+ "size": 1
+ },
+ "BKPRST": {
+ "description": "Backup interface reset",
+ "offset": 27,
+ "size": 1
+ },
+ "PWRRST": {
+ "description": "Power interface reset",
+ "offset": 28,
+ "size": 1
+ },
+ "DACRST": {
+ "description": "DAC interface reset",
+ "offset": 29,
+ "size": 1
+ }
+ }
+ }
+ },
+ "AHBENR": {
+ "description": "AHB Peripheral Clock enable register\n (RCC_AHBENR)",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 20,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMA1EN": {
+ "description": "DMA1 clock enable",
+ "offset": 0,
+ "size": 1
+ },
+ "DMA2EN": {
+ "description": "DMA2 clock enable",
+ "offset": 1,
+ "size": 1
+ },
+ "SRAMEN": {
+ "description": "SRAM interface clock\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "FLITFEN": {
+ "description": "FLITF clock enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CRCEN": {
+ "description": "CRC clock enable",
+ "offset": 6,
+ "size": 1
+ },
+ "FSMCEN": {
+ "description": "FSMC clock enable",
+ "offset": 8,
+ "size": 1
+ },
+ "SDIOEN": {
+ "description": "SDIO clock enable",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "APB2ENR": {
+ "description": "APB2 peripheral clock enable register\n (RCC_APB2ENR)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "AFIOEN": {
+ "description": "Alternate function I/O clock\n enable",
+ "offset": 0,
+ "size": 1
+ },
+ "IOPAEN": {
+ "description": "I/O port A clock enable",
+ "offset": 2,
+ "size": 1
+ },
+ "IOPBEN": {
+ "description": "I/O port B clock enable",
+ "offset": 3,
+ "size": 1
+ },
+ "IOPCEN": {
+ "description": "I/O port C clock enable",
+ "offset": 4,
+ "size": 1
+ },
+ "IOPDEN": {
+ "description": "I/O port D clock enable",
+ "offset": 5,
+ "size": 1
+ },
+ "IOPEEN": {
+ "description": "I/O port E clock enable",
+ "offset": 6,
+ "size": 1
+ },
+ "IOPFEN": {
+ "description": "I/O port F clock enable",
+ "offset": 7,
+ "size": 1
+ },
+ "IOPGEN": {
+ "description": "I/O port G clock enable",
+ "offset": 8,
+ "size": 1
+ },
+ "ADC1EN": {
+ "description": "ADC 1 interface clock\n enable",
+ "offset": 9,
+ "size": 1
+ },
+ "ADC2EN": {
+ "description": "ADC 2 interface clock\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "TIM1EN": {
+ "description": "TIM1 Timer clock enable",
+ "offset": 11,
+ "size": 1
+ },
+ "SPI1EN": {
+ "description": "SPI 1 clock enable",
+ "offset": 12,
+ "size": 1
+ },
+ "TIM8EN": {
+ "description": "TIM8 Timer clock enable",
+ "offset": 13,
+ "size": 1
+ },
+ "USART1EN": {
+ "description": "USART1 clock enable",
+ "offset": 14,
+ "size": 1
+ },
+ "ADC3EN": {
+ "description": "ADC3 interface clock\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "TIM9EN": {
+ "description": "TIM9 Timer clock enable",
+ "offset": 19,
+ "size": 1
+ },
+ "TIM10EN": {
+ "description": "TIM10 Timer clock enable",
+ "offset": 20,
+ "size": 1
+ },
+ "TIM11EN": {
+ "description": "TIM11 Timer clock enable",
+ "offset": 21,
+ "size": 1
+ }
+ }
+ }
+ },
+ "APB1ENR": {
+ "description": "APB1 peripheral clock enable register\n (RCC_APB1ENR)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIM2EN": {
+ "description": "Timer 2 clock enable",
+ "offset": 0,
+ "size": 1
+ },
+ "TIM3EN": {
+ "description": "Timer 3 clock enable",
+ "offset": 1,
+ "size": 1
+ },
+ "TIM4EN": {
+ "description": "Timer 4 clock enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TIM5EN": {
+ "description": "Timer 5 clock enable",
+ "offset": 3,
+ "size": 1
+ },
+ "TIM6EN": {
+ "description": "Timer 6 clock enable",
+ "offset": 4,
+ "size": 1
+ },
+ "TIM7EN": {
+ "description": "Timer 7 clock enable",
+ "offset": 5,
+ "size": 1
+ },
+ "TIM12EN": {
+ "description": "Timer 12 clock enable",
+ "offset": 6,
+ "size": 1
+ },
+ "TIM13EN": {
+ "description": "Timer 13 clock enable",
+ "offset": 7,
+ "size": 1
+ },
+ "TIM14EN": {
+ "description": "Timer 14 clock enable",
+ "offset": 8,
+ "size": 1
+ },
+ "WWDGEN": {
+ "description": "Window watchdog clock\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "SPI2EN": {
+ "description": "SPI 2 clock enable",
+ "offset": 14,
+ "size": 1
+ },
+ "SPI3EN": {
+ "description": "SPI 3 clock enable",
+ "offset": 15,
+ "size": 1
+ },
+ "USART2EN": {
+ "description": "USART 2 clock enable",
+ "offset": 17,
+ "size": 1
+ },
+ "USART3EN": {
+ "description": "USART 3 clock enable",
+ "offset": 18,
+ "size": 1
+ },
+ "UART4EN": {
+ "description": "UART 4 clock enable",
+ "offset": 19,
+ "size": 1
+ },
+ "UART5EN": {
+ "description": "UART 5 clock enable",
+ "offset": 20,
+ "size": 1
+ },
+ "I2C1EN": {
+ "description": "I2C 1 clock enable",
+ "offset": 21,
+ "size": 1
+ },
+ "I2C2EN": {
+ "description": "I2C 2 clock enable",
+ "offset": 22,
+ "size": 1
+ },
+ "USBEN": {
+ "description": "USB clock enable",
+ "offset": 23,
+ "size": 1
+ },
+ "CANEN": {
+ "description": "CAN clock enable",
+ "offset": 25,
+ "size": 1
+ },
+ "BKPEN": {
+ "description": "Backup interface clock\n enable",
+ "offset": 27,
+ "size": 1
+ },
+ "PWREN": {
+ "description": "Power interface clock\n enable",
+ "offset": 28,
+ "size": 1
+ },
+ "DACEN": {
+ "description": "DAC interface clock enable",
+ "offset": 29,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BDCR": {
+ "description": "Backup domain control register\n (RCC_BDCR)",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LSEON": {
+ "description": "External Low Speed oscillator\n enable",
+ "offset": 0,
+ "size": 1
+ },
+ "LSERDY": {
+ "description": "External Low Speed oscillator\n ready",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "LSEBYP": {
+ "description": "External Low Speed oscillator\n bypass",
+ "offset": 2,
+ "size": 1
+ },
+ "RTCSEL": {
+ "description": "RTC clock source selection",
+ "offset": 8,
+ "size": 2
+ },
+ "RTCEN": {
+ "description": "RTC clock enable",
+ "offset": 15,
+ "size": 1
+ },
+ "BDRST": {
+ "description": "Backup domain software\n reset",
+ "offset": 16,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CSR": {
+ "description": "Control/status register\n (RCC_CSR)",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 201326592,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LSION": {
+ "description": "Internal low speed oscillator\n enable",
+ "offset": 0,
+ "size": 1
+ },
+ "LSIRDY": {
+ "description": "Internal low speed oscillator\n ready",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "RMVF": {
+ "description": "Remove reset flag",
+ "offset": 24,
+ "size": 1
+ },
+ "PINRSTF": {
+ "description": "PIN reset flag",
+ "offset": 26,
+ "size": 1
+ },
+ "PORRSTF": {
+ "description": "POR/PDR reset flag",
+ "offset": 27,
+ "size": 1
+ },
+ "SFTRSTF": {
+ "description": "Software reset flag",
+ "offset": 28,
+ "size": 1
+ },
+ "IWDGRSTF": {
+ "description": "Independent watchdog reset\n flag",
+ "offset": 29,
+ "size": 1
+ },
+ "WWDGRSTF": {
+ "description": "Window watchdog reset flag",
+ "offset": 30,
+ "size": 1
+ },
+ "LPWRRSTF": {
+ "description": "Low-power reset flag",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "GPIOA": {
+ "description": "General purpose I/O",
+ "children": {
+ "registers": {
+ "CRL": {
+ "description": "Port configuration register low\n (GPIOn_CRL)",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 1145324612,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MODE0": {
+ "description": "Port n.0 mode bits",
+ "offset": 0,
+ "size": 2
+ },
+ "CNF0": {
+ "description": "Port n.0 configuration\n bits",
+ "offset": 2,
+ "size": 2
+ },
+ "MODE1": {
+ "description": "Port n.1 mode bits",
+ "offset": 4,
+ "size": 2
+ },
+ "CNF1": {
+ "description": "Port n.1 configuration\n bits",
+ "offset": 6,
+ "size": 2
+ },
+ "MODE2": {
+ "description": "Port n.2 mode bits",
+ "offset": 8,
+ "size": 2
+ },
+ "CNF2": {
+ "description": "Port n.2 configuration\n bits",
+ "offset": 10,
+ "size": 2
+ },
+ "MODE3": {
+ "description": "Port n.3 mode bits",
+ "offset": 12,
+ "size": 2
+ },
+ "CNF3": {
+ "description": "Port n.3 configuration\n bits",
+ "offset": 14,
+ "size": 2
+ },
+ "MODE4": {
+ "description": "Port n.4 mode bits",
+ "offset": 16,
+ "size": 2
+ },
+ "CNF4": {
+ "description": "Port n.4 configuration\n bits",
+ "offset": 18,
+ "size": 2
+ },
+ "MODE5": {
+ "description": "Port n.5 mode bits",
+ "offset": 20,
+ "size": 2
+ },
+ "CNF5": {
+ "description": "Port n.5 configuration\n bits",
+ "offset": 22,
+ "size": 2
+ },
+ "MODE6": {
+ "description": "Port n.6 mode bits",
+ "offset": 24,
+ "size": 2
+ },
+ "CNF6": {
+ "description": "Port n.6 configuration\n bits",
+ "offset": 26,
+ "size": 2
+ },
+ "MODE7": {
+ "description": "Port n.7 mode bits",
+ "offset": 28,
+ "size": 2
+ },
+ "CNF7": {
+ "description": "Port n.7 configuration\n bits",
+ "offset": 30,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CRH": {
+ "description": "Port configuration register high\n (GPIOn_CRL)",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 1145324612,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MODE8": {
+ "description": "Port n.8 mode bits",
+ "offset": 0,
+ "size": 2
+ },
+ "CNF8": {
+ "description": "Port n.8 configuration\n bits",
+ "offset": 2,
+ "size": 2
+ },
+ "MODE9": {
+ "description": "Port n.9 mode bits",
+ "offset": 4,
+ "size": 2
+ },
+ "CNF9": {
+ "description": "Port n.9 configuration\n bits",
+ "offset": 6,
+ "size": 2
+ },
+ "MODE10": {
+ "description": "Port n.10 mode bits",
+ "offset": 8,
+ "size": 2
+ },
+ "CNF10": {
+ "description": "Port n.10 configuration\n bits",
+ "offset": 10,
+ "size": 2
+ },
+ "MODE11": {
+ "description": "Port n.11 mode bits",
+ "offset": 12,
+ "size": 2
+ },
+ "CNF11": {
+ "description": "Port n.11 configuration\n bits",
+ "offset": 14,
+ "size": 2
+ },
+ "MODE12": {
+ "description": "Port n.12 mode bits",
+ "offset": 16,
+ "size": 2
+ },
+ "CNF12": {
+ "description": "Port n.12 configuration\n bits",
+ "offset": 18,
+ "size": 2
+ },
+ "MODE13": {
+ "description": "Port n.13 mode bits",
+ "offset": 20,
+ "size": 2
+ },
+ "CNF13": {
+ "description": "Port n.13 configuration\n bits",
+ "offset": 22,
+ "size": 2
+ },
+ "MODE14": {
+ "description": "Port n.14 mode bits",
+ "offset": 24,
+ "size": 2
+ },
+ "CNF14": {
+ "description": "Port n.14 configuration\n bits",
+ "offset": 26,
+ "size": 2
+ },
+ "MODE15": {
+ "description": "Port n.15 mode bits",
+ "offset": 28,
+ "size": 2
+ },
+ "CNF15": {
+ "description": "Port n.15 configuration\n bits",
+ "offset": 30,
+ "size": 2
+ }
+ }
+ }
+ },
+ "IDR": {
+ "description": "Port input data register\n (GPIOn_IDR)",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "IDR0": {
+ "description": "Port input data",
+ "offset": 0,
+ "size": 1
+ },
+ "IDR1": {
+ "description": "Port input data",
+ "offset": 1,
+ "size": 1
+ },
+ "IDR2": {
+ "description": "Port input data",
+ "offset": 2,
+ "size": 1
+ },
+ "IDR3": {
+ "description": "Port input data",
+ "offset": 3,
+ "size": 1
+ },
+ "IDR4": {
+ "description": "Port input data",
+ "offset": 4,
+ "size": 1
+ },
+ "IDR5": {
+ "description": "Port input data",
+ "offset": 5,
+ "size": 1
+ },
+ "IDR6": {
+ "description": "Port input data",
+ "offset": 6,
+ "size": 1
+ },
+ "IDR7": {
+ "description": "Port input data",
+ "offset": 7,
+ "size": 1
+ },
+ "IDR8": {
+ "description": "Port input data",
+ "offset": 8,
+ "size": 1
+ },
+ "IDR9": {
+ "description": "Port input data",
+ "offset": 9,
+ "size": 1
+ },
+ "IDR10": {
+ "description": "Port input data",
+ "offset": 10,
+ "size": 1
+ },
+ "IDR11": {
+ "description": "Port input data",
+ "offset": 11,
+ "size": 1
+ },
+ "IDR12": {
+ "description": "Port input data",
+ "offset": 12,
+ "size": 1
+ },
+ "IDR13": {
+ "description": "Port input data",
+ "offset": 13,
+ "size": 1
+ },
+ "IDR14": {
+ "description": "Port input data",
+ "offset": 14,
+ "size": 1
+ },
+ "IDR15": {
+ "description": "Port input data",
+ "offset": 15,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ODR": {
+ "description": "Port output data register\n (GPIOn_ODR)",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ODR0": {
+ "description": "Port output data",
+ "offset": 0,
+ "size": 1
+ },
+ "ODR1": {
+ "description": "Port output data",
+ "offset": 1,
+ "size": 1
+ },
+ "ODR2": {
+ "description": "Port output data",
+ "offset": 2,
+ "size": 1
+ },
+ "ODR3": {
+ "description": "Port output data",
+ "offset": 3,
+ "size": 1
+ },
+ "ODR4": {
+ "description": "Port output data",
+ "offset": 4,
+ "size": 1
+ },
+ "ODR5": {
+ "description": "Port output data",
+ "offset": 5,
+ "size": 1
+ },
+ "ODR6": {
+ "description": "Port output data",
+ "offset": 6,
+ "size": 1
+ },
+ "ODR7": {
+ "description": "Port output data",
+ "offset": 7,
+ "size": 1
+ },
+ "ODR8": {
+ "description": "Port output data",
+ "offset": 8,
+ "size": 1
+ },
+ "ODR9": {
+ "description": "Port output data",
+ "offset": 9,
+ "size": 1
+ },
+ "ODR10": {
+ "description": "Port output data",
+ "offset": 10,
+ "size": 1
+ },
+ "ODR11": {
+ "description": "Port output data",
+ "offset": 11,
+ "size": 1
+ },
+ "ODR12": {
+ "description": "Port output data",
+ "offset": 12,
+ "size": 1
+ },
+ "ODR13": {
+ "description": "Port output data",
+ "offset": 13,
+ "size": 1
+ },
+ "ODR14": {
+ "description": "Port output data",
+ "offset": 14,
+ "size": 1
+ },
+ "ODR15": {
+ "description": "Port output data",
+ "offset": 15,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BSRR": {
+ "description": "Port bit set/reset register\n (GPIOn_BSRR)",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "BS0": {
+ "description": "Set bit 0",
+ "offset": 0,
+ "size": 1
+ },
+ "BS1": {
+ "description": "Set bit 1",
+ "offset": 1,
+ "size": 1
+ },
+ "BS2": {
+ "description": "Set bit 1",
+ "offset": 2,
+ "size": 1
+ },
+ "BS3": {
+ "description": "Set bit 3",
+ "offset": 3,
+ "size": 1
+ },
+ "BS4": {
+ "description": "Set bit 4",
+ "offset": 4,
+ "size": 1
+ },
+ "BS5": {
+ "description": "Set bit 5",
+ "offset": 5,
+ "size": 1
+ },
+ "BS6": {
+ "description": "Set bit 6",
+ "offset": 6,
+ "size": 1
+ },
+ "BS7": {
+ "description": "Set bit 7",
+ "offset": 7,
+ "size": 1
+ },
+ "BS8": {
+ "description": "Set bit 8",
+ "offset": 8,
+ "size": 1
+ },
+ "BS9": {
+ "description": "Set bit 9",
+ "offset": 9,
+ "size": 1
+ },
+ "BS10": {
+ "description": "Set bit 10",
+ "offset": 10,
+ "size": 1
+ },
+ "BS11": {
+ "description": "Set bit 11",
+ "offset": 11,
+ "size": 1
+ },
+ "BS12": {
+ "description": "Set bit 12",
+ "offset": 12,
+ "size": 1
+ },
+ "BS13": {
+ "description": "Set bit 13",
+ "offset": 13,
+ "size": 1
+ },
+ "BS14": {
+ "description": "Set bit 14",
+ "offset": 14,
+ "size": 1
+ },
+ "BS15": {
+ "description": "Set bit 15",
+ "offset": 15,
+ "size": 1
+ },
+ "BR0": {
+ "description": "Reset bit 0",
+ "offset": 16,
+ "size": 1
+ },
+ "BR1": {
+ "description": "Reset bit 1",
+ "offset": 17,
+ "size": 1
+ },
+ "BR2": {
+ "description": "Reset bit 2",
+ "offset": 18,
+ "size": 1
+ },
+ "BR3": {
+ "description": "Reset bit 3",
+ "offset": 19,
+ "size": 1
+ },
+ "BR4": {
+ "description": "Reset bit 4",
+ "offset": 20,
+ "size": 1
+ },
+ "BR5": {
+ "description": "Reset bit 5",
+ "offset": 21,
+ "size": 1
+ },
+ "BR6": {
+ "description": "Reset bit 6",
+ "offset": 22,
+ "size": 1
+ },
+ "BR7": {
+ "description": "Reset bit 7",
+ "offset": 23,
+ "size": 1
+ },
+ "BR8": {
+ "description": "Reset bit 8",
+ "offset": 24,
+ "size": 1
+ },
+ "BR9": {
+ "description": "Reset bit 9",
+ "offset": 25,
+ "size": 1
+ },
+ "BR10": {
+ "description": "Reset bit 10",
+ "offset": 26,
+ "size": 1
+ },
+ "BR11": {
+ "description": "Reset bit 11",
+ "offset": 27,
+ "size": 1
+ },
+ "BR12": {
+ "description": "Reset bit 12",
+ "offset": 28,
+ "size": 1
+ },
+ "BR13": {
+ "description": "Reset bit 13",
+ "offset": 29,
+ "size": 1
+ },
+ "BR14": {
+ "description": "Reset bit 14",
+ "offset": 30,
+ "size": 1
+ },
+ "BR15": {
+ "description": "Reset bit 15",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BRR": {
+ "description": "Port bit reset register\n (GPIOn_BRR)",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "BR0": {
+ "description": "Reset bit 0",
+ "offset": 0,
+ "size": 1
+ },
+ "BR1": {
+ "description": "Reset bit 1",
+ "offset": 1,
+ "size": 1
+ },
+ "BR2": {
+ "description": "Reset bit 1",
+ "offset": 2,
+ "size": 1
+ },
+ "BR3": {
+ "description": "Reset bit 3",
+ "offset": 3,
+ "size": 1
+ },
+ "BR4": {
+ "description": "Reset bit 4",
+ "offset": 4,
+ "size": 1
+ },
+ "BR5": {
+ "description": "Reset bit 5",
+ "offset": 5,
+ "size": 1
+ },
+ "BR6": {
+ "description": "Reset bit 6",
+ "offset": 6,
+ "size": 1
+ },
+ "BR7": {
+ "description": "Reset bit 7",
+ "offset": 7,
+ "size": 1
+ },
+ "BR8": {
+ "description": "Reset bit 8",
+ "offset": 8,
+ "size": 1
+ },
+ "BR9": {
+ "description": "Reset bit 9",
+ "offset": 9,
+ "size": 1
+ },
+ "BR10": {
+ "description": "Reset bit 10",
+ "offset": 10,
+ "size": 1
+ },
+ "BR11": {
+ "description": "Reset bit 11",
+ "offset": 11,
+ "size": 1
+ },
+ "BR12": {
+ "description": "Reset bit 12",
+ "offset": 12,
+ "size": 1
+ },
+ "BR13": {
+ "description": "Reset bit 13",
+ "offset": 13,
+ "size": 1
+ },
+ "BR14": {
+ "description": "Reset bit 14",
+ "offset": 14,
+ "size": 1
+ },
+ "BR15": {
+ "description": "Reset bit 15",
+ "offset": 15,
+ "size": 1
+ }
+ }
+ }
+ },
+ "LCKR": {
+ "description": "Port configuration lock\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LCK0": {
+ "description": "Port A Lock bit 0",
+ "offset": 0,
+ "size": 1
+ },
+ "LCK1": {
+ "description": "Port A Lock bit 1",
+ "offset": 1,
+ "size": 1
+ },
+ "LCK2": {
+ "description": "Port A Lock bit 2",
+ "offset": 2,
+ "size": 1
+ },
+ "LCK3": {
+ "description": "Port A Lock bit 3",
+ "offset": 3,
+ "size": 1
+ },
+ "LCK4": {
+ "description": "Port A Lock bit 4",
+ "offset": 4,
+ "size": 1
+ },
+ "LCK5": {
+ "description": "Port A Lock bit 5",
+ "offset": 5,
+ "size": 1
+ },
+ "LCK6": {
+ "description": "Port A Lock bit 6",
+ "offset": 6,
+ "size": 1
+ },
+ "LCK7": {
+ "description": "Port A Lock bit 7",
+ "offset": 7,
+ "size": 1
+ },
+ "LCK8": {
+ "description": "Port A Lock bit 8",
+ "offset": 8,
+ "size": 1
+ },
+ "LCK9": {
+ "description": "Port A Lock bit 9",
+ "offset": 9,
+ "size": 1
+ },
+ "LCK10": {
+ "description": "Port A Lock bit 10",
+ "offset": 10,
+ "size": 1
+ },
+ "LCK11": {
+ "description": "Port A Lock bit 11",
+ "offset": 11,
+ "size": 1
+ },
+ "LCK12": {
+ "description": "Port A Lock bit 12",
+ "offset": 12,
+ "size": 1
+ },
+ "LCK13": {
+ "description": "Port A Lock bit 13",
+ "offset": 13,
+ "size": 1
+ },
+ "LCK14": {
+ "description": "Port A Lock bit 14",
+ "offset": 14,
+ "size": 1
+ },
+ "LCK15": {
+ "description": "Port A Lock bit 15",
+ "offset": 15,
+ "size": 1
+ },
+ "LCKK": {
+ "description": "Lock key",
+ "offset": 16,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "STK": {
+ "description": "SysTick timer",
+ "children": {
+ "registers": {
+ "CTRL": {
+ "description": "SysTick control and status\n register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ENABLE": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ },
+ "TICKINT": {
+ "description": "SysTick exception request\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "CLKSOURCE": {
+ "description": "Clock source selection",
+ "offset": 2,
+ "size": 1
+ },
+ "COUNTFLAG": {
+ "description": "COUNTFLAG",
+ "offset": 16,
+ "size": 1
+ }
+ }
+ }
+ },
+ "LOAD_": {
+ "description": "SysTick reload value register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RELOAD": {
+ "description": "RELOAD value",
+ "offset": 0,
+ "size": 24
+ }
+ }
+ }
+ },
+ "VAL": {
+ "description": "SysTick current value register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CURRENT": {
+ "description": "Current counter value",
+ "offset": 0,
+ "size": 24
+ }
+ }
+ }
+ },
+ "CALIB": {
+ "description": "SysTick calibration value\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TENMS": {
+ "description": "Calibration value",
+ "offset": 0,
+ "size": 24
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "SCB": {
+ "description": "System control block",
+ "children": {
+ "registers": {
+ "CPUID": {
+ "description": "CPUID base register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 1091551809,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "Revision": {
+ "description": "Revision number",
+ "offset": 0,
+ "size": 4
+ },
+ "PartNo": {
+ "description": "Part number of the\n processor",
+ "offset": 4,
+ "size": 12
+ },
+ "Constant": {
+ "description": "Reads as 0xF",
+ "offset": 16,
+ "size": 4
+ },
+ "Variant": {
+ "description": "Variant number",
+ "offset": 20,
+ "size": 4
+ },
+ "Implementer": {
+ "description": "Implementer code",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "ICSR": {
+ "description": "Interrupt control and state\n register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "VECTACTIVE": {
+ "description": "Active vector",
+ "offset": 0,
+ "size": 9
+ },
+ "RETTOBASE": {
+ "description": "Return to base level",
+ "offset": 11,
+ "size": 1
+ },
+ "VECTPENDING": {
+ "description": "Pending vector",
+ "offset": 12,
+ "size": 7
+ },
+ "ISRPENDING": {
+ "description": "Interrupt pending flag",
+ "offset": 22,
+ "size": 1
+ },
+ "PENDSTCLR": {
+ "description": "SysTick exception clear-pending\n bit",
+ "offset": 25,
+ "size": 1
+ },
+ "PENDSTSET": {
+ "description": "SysTick exception set-pending\n bit",
+ "offset": 26,
+ "size": 1
+ },
+ "PENDSVCLR": {
+ "description": "PendSV clear-pending bit",
+ "offset": 27,
+ "size": 1
+ },
+ "PENDSVSET": {
+ "description": "PendSV set-pending bit",
+ "offset": 28,
+ "size": 1
+ },
+ "NMIPENDSET": {
+ "description": "NMI set-pending bit.",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "VTOR": {
+ "description": "Vector table offset register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TBLOFF": {
+ "description": "Vector table base offset\n field",
+ "offset": 9,
+ "size": 21
+ }
+ }
+ }
+ },
+ "AIRCR": {
+ "description": "Application interrupt and reset control\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "VECTRESET": {
+ "description": "VECTRESET",
+ "offset": 0,
+ "size": 1
+ },
+ "VECTCLRACTIVE": {
+ "description": "VECTCLRACTIVE",
+ "offset": 1,
+ "size": 1
+ },
+ "SYSRESETREQ": {
+ "description": "SYSRESETREQ",
+ "offset": 2,
+ "size": 1
+ },
+ "PRIGROUP": {
+ "description": "PRIGROUP",
+ "offset": 8,
+ "size": 3
+ },
+ "ENDIANESS": {
+ "description": "ENDIANESS",
+ "offset": 15,
+ "size": 1
+ },
+ "VECTKEYSTAT": {
+ "description": "Register key",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "SCR": {
+ "description": "System control register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SLEEPONEXIT": {
+ "description": "SLEEPONEXIT",
+ "offset": 1,
+ "size": 1
+ },
+ "SLEEPDEEP": {
+ "description": "SLEEPDEEP",
+ "offset": 2,
+ "size": 1
+ },
+ "SEVEONPEND": {
+ "description": "Send Event on Pending bit",
+ "offset": 4,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCR": {
+ "description": "Configuration and control\n register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NONBASETHRDENA": {
+ "description": "Configures how the processor enters\n Thread mode",
+ "offset": 0,
+ "size": 1
+ },
+ "USERSETMPEND": {
+ "description": "USERSETMPEND",
+ "offset": 1,
+ "size": 1
+ },
+ "UNALIGN__TRP": {
+ "description": "UNALIGN_ TRP",
+ "offset": 3,
+ "size": 1
+ },
+ "DIV_0_TRP": {
+ "description": "DIV_0_TRP",
+ "offset": 4,
+ "size": 1
+ },
+ "BFHFNMIGN": {
+ "description": "BFHFNMIGN",
+ "offset": 8,
+ "size": 1
+ },
+ "STKALIGN": {
+ "description": "STKALIGN",
+ "offset": 9,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SHPR1": {
+ "description": "System handler priority\n registers",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRI_4": {
+ "description": "Priority of system handler\n 4",
+ "offset": 0,
+ "size": 8
+ },
+ "PRI_5": {
+ "description": "Priority of system handler\n 5",
+ "offset": 8,
+ "size": 8
+ },
+ "PRI_6": {
+ "description": "Priority of system handler\n 6",
+ "offset": 16,
+ "size": 8
+ }
+ }
+ }
+ },
+ "SHPR2": {
+ "description": "System handler priority\n registers",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRI_11": {
+ "description": "Priority of system handler\n 11",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "SHPR3": {
+ "description": "System handler priority\n registers",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRI_14": {
+ "description": "Priority of system handler\n 14",
+ "offset": 16,
+ "size": 8
+ },
+ "PRI_15": {
+ "description": "Priority of system handler\n 15",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "SHCRS": {
+ "description": "System handler control and state\n register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MEMFAULTACT": {
+ "description": "Memory management fault exception active\n bit",
+ "offset": 0,
+ "size": 1
+ },
+ "BUSFAULTACT": {
+ "description": "Bus fault exception active\n bit",
+ "offset": 1,
+ "size": 1
+ },
+ "USGFAULTACT": {
+ "description": "Usage fault exception active\n bit",
+ "offset": 3,
+ "size": 1
+ },
+ "SVCALLACT": {
+ "description": "SVC call active bit",
+ "offset": 7,
+ "size": 1
+ },
+ "MONITORACT": {
+ "description": "Debug monitor active bit",
+ "offset": 8,
+ "size": 1
+ },
+ "PENDSVACT": {
+ "description": "PendSV exception active\n bit",
+ "offset": 10,
+ "size": 1
+ },
+ "SYSTICKACT": {
+ "description": "SysTick exception active\n bit",
+ "offset": 11,
+ "size": 1
+ },
+ "USGFAULTPENDED": {
+ "description": "Usage fault exception pending\n bit",
+ "offset": 12,
+ "size": 1
+ },
+ "MEMFAULTPENDED": {
+ "description": "Memory management fault exception\n pending bit",
+ "offset": 13,
+ "size": 1
+ },
+ "BUSFAULTPENDED": {
+ "description": "Bus fault exception pending\n bit",
+ "offset": 14,
+ "size": 1
+ },
+ "SVCALLPENDED": {
+ "description": "SVC call pending bit",
+ "offset": 15,
+ "size": 1
+ },
+ "MEMFAULTENA": {
+ "description": "Memory management fault enable\n bit",
+ "offset": 16,
+ "size": 1
+ },
+ "BUSFAULTENA": {
+ "description": "Bus fault enable bit",
+ "offset": 17,
+ "size": 1
+ },
+ "USGFAULTENA": {
+ "description": "Usage fault enable bit",
+ "offset": 18,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CFSR_UFSR_BFSR_MMFSR": {
+ "description": "Configurable fault status\n register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IACCVIOL": {
+ "description": "IACCVIOL",
+ "offset": 0,
+ "size": 1
+ },
+ "DACCVIOL": {
+ "description": "DACCVIOL",
+ "offset": 1,
+ "size": 1
+ },
+ "MUNSTKERR": {
+ "description": "MUNSTKERR",
+ "offset": 3,
+ "size": 1
+ },
+ "MSTKERR": {
+ "description": "MSTKERR",
+ "offset": 4,
+ "size": 1
+ },
+ "MLSPERR": {
+ "description": "MLSPERR",
+ "offset": 5,
+ "size": 1
+ },
+ "MMARVALID": {
+ "description": "MMARVALID",
+ "offset": 7,
+ "size": 1
+ },
+ "IBUSERR": {
+ "description": "Instruction bus error",
+ "offset": 8,
+ "size": 1
+ },
+ "PRECISERR": {
+ "description": "Precise data bus error",
+ "offset": 9,
+ "size": 1
+ },
+ "IMPRECISERR": {
+ "description": "Imprecise data bus error",
+ "offset": 10,
+ "size": 1
+ },
+ "UNSTKERR": {
+ "description": "Bus fault on unstacking for a return\n from exception",
+ "offset": 11,
+ "size": 1
+ },
+ "STKERR": {
+ "description": "Bus fault on stacking for exception\n entry",
+ "offset": 12,
+ "size": 1
+ },
+ "LSPERR": {
+ "description": "Bus fault on floating-point lazy state\n preservation",
+ "offset": 13,
+ "size": 1
+ },
+ "BFARVALID": {
+ "description": "Bus Fault Address Register (BFAR) valid\n flag",
+ "offset": 15,
+ "size": 1
+ },
+ "UNDEFINSTR": {
+ "description": "Undefined instruction usage\n fault",
+ "offset": 16,
+ "size": 1
+ },
+ "INVSTATE": {
+ "description": "Invalid state usage fault",
+ "offset": 17,
+ "size": 1
+ },
+ "INVPC": {
+ "description": "Invalid PC load usage\n fault",
+ "offset": 18,
+ "size": 1
+ },
+ "NOCP": {
+ "description": "No coprocessor usage\n fault.",
+ "offset": 19,
+ "size": 1
+ },
+ "UNALIGNED": {
+ "description": "Unaligned access usage\n fault",
+ "offset": 24,
+ "size": 1
+ },
+ "DIVBYZERO": {
+ "description": "Divide by zero usage fault",
+ "offset": 25,
+ "size": 1
+ }
+ }
+ }
+ },
+ "HFSR": {
+ "description": "Hard fault status register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "VECTTBL": {
+ "description": "Vector table hard fault",
+ "offset": 1,
+ "size": 1
+ },
+ "FORCED": {
+ "description": "Forced hard fault",
+ "offset": 30,
+ "size": 1
+ },
+ "DEBUG_VT": {
+ "description": "Reserved for Debug use",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MMFAR": {
+ "description": "Memory management fault address\n register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MMFAR": {
+ "description": "Memory management fault\n address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BFAR": {
+ "description": "Bus fault address register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BFAR": {
+ "description": "Bus fault address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "NVIC_STIR": {
+ "description": "Nested vectored interrupt\n controller",
+ "children": {
+ "registers": {
+ "STIR": {
+ "description": "Software trigger interrupt\n register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INTID": {
+ "description": "Software generated interrupt\n ID",
+ "offset": 0,
+ "size": 9
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "SCB_ACTRL": {
+ "description": "System control block ACTLR",
+ "children": {
+ "registers": {
+ "ACTRL": {
+ "description": "Auxiliary control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DISFOLD": {
+ "description": "DISFOLD",
+ "offset": 2,
+ "size": 1
+ },
+ "FPEXCODIS": {
+ "description": "FPEXCODIS",
+ "offset": 10,
+ "size": 1
+ },
+ "DISRAMODE": {
+ "description": "DISRAMODE",
+ "offset": 11,
+ "size": 1
+ },
+ "DISITMATBFLUSH": {
+ "description": "DISITMATBFLUSH",
+ "offset": 12,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "MPU": {
+ "description": "Memory protection unit",
+ "children": {
+ "registers": {
+ "MPU_TYPER": {
+ "description": "MPU type register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 2048,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "SEPARATE": {
+ "description": "Separate flag",
+ "offset": 0,
+ "size": 1
+ },
+ "DREGION": {
+ "description": "Number of MPU data regions",
+ "offset": 8,
+ "size": 8
+ },
+ "IREGION": {
+ "description": "Number of MPU instruction\n regions",
+ "offset": 16,
+ "size": 8
+ }
+ }
+ }
+ },
+ "MPU_CTRL": {
+ "description": "MPU control register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "ENABLE": {
+ "description": "Enables the MPU",
+ "offset": 0,
+ "size": 1
+ },
+ "HFNMIENA": {
+ "description": "Enables the operation of MPU during hard\n fault",
+ "offset": 1,
+ "size": 1
+ },
+ "PRIVDEFENA": {
+ "description": "Enable priviliged software access to\n default memory map",
+ "offset": 2,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MPU_RNR": {
+ "description": "MPU region number register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "REGION": {
+ "description": "MPU region",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "MPU_RBAR": {
+ "description": "MPU region base address\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "REGION": {
+ "description": "MPU region field",
+ "offset": 0,
+ "size": 4
+ },
+ "VALID": {
+ "description": "MPU region number valid",
+ "offset": 4,
+ "size": 1
+ },
+ "ADDR": {
+ "description": "Region base address field",
+ "offset": 5,
+ "size": 27
+ }
+ }
+ }
+ },
+ "MPU_RASR": {
+ "description": "MPU region attribute and size\n register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ENABLE": {
+ "description": "Region enable bit.",
+ "offset": 0,
+ "size": 1
+ },
+ "SIZE": {
+ "description": "Size of the MPU protection\n region",
+ "offset": 1,
+ "size": 5
+ },
+ "SRD": {
+ "description": "Subregion disable bits",
+ "offset": 8,
+ "size": 8
+ },
+ "B": {
+ "description": "memory attribute",
+ "offset": 16,
+ "size": 1
+ },
+ "C": {
+ "description": "memory attribute",
+ "offset": 17,
+ "size": 1
+ },
+ "S": {
+ "description": "Shareable memory attribute",
+ "offset": 18,
+ "size": 1
+ },
+ "TEX": {
+ "description": "memory attribute",
+ "offset": 19,
+ "size": 3
+ },
+ "AP": {
+ "description": "Access permission",
+ "offset": 24,
+ "size": 3
+ },
+ "XN": {
+ "description": "Instruction access disable\n bit",
+ "offset": 28,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "NVIC": {
+ "description": "Nested Vectored Interrupt\n Controller",
+ "children": {
+ "registers": {
+ "ISER0": {
+ "description": "Interrupt Set-Enable Register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SETENA": {
+ "description": "SETENA",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ISER1": {
+ "description": "Interrupt Set-Enable Register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SETENA": {
+ "description": "SETENA",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ICER0": {
+ "description": "Interrupt Clear-Enable\n Register",
+ "offset": 128,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CLRENA": {
+ "description": "CLRENA",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ICER1": {
+ "description": "Interrupt Clear-Enable\n Register",
+ "offset": 132,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CLRENA": {
+ "description": "CLRENA",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ISPR0": {
+ "description": "Interrupt Set-Pending Register",
+ "offset": 256,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SETPEND": {
+ "description": "SETPEND",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ISPR1": {
+ "description": "Interrupt Set-Pending Register",
+ "offset": 260,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SETPEND": {
+ "description": "SETPEND",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ICPR0": {
+ "description": "Interrupt Clear-Pending\n Register",
+ "offset": 384,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CLRPEND": {
+ "description": "CLRPEND",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ICPR1": {
+ "description": "Interrupt Clear-Pending\n Register",
+ "offset": 388,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CLRPEND": {
+ "description": "CLRPEND",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "IABR0": {
+ "description": "Interrupt Active Bit Register",
+ "offset": 512,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "ACTIVE": {
+ "description": "ACTIVE",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "IABR1": {
+ "description": "Interrupt Active Bit Register",
+ "offset": 516,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "ACTIVE": {
+ "description": "ACTIVE",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "IPR0": {
+ "description": "Interrupt Priority Register",
+ "offset": 768,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR1": {
+ "description": "Interrupt Priority Register",
+ "offset": 772,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR2": {
+ "description": "Interrupt Priority Register",
+ "offset": 776,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR3": {
+ "description": "Interrupt Priority Register",
+ "offset": 780,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR4": {
+ "description": "Interrupt Priority Register",
+ "offset": 784,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR5": {
+ "description": "Interrupt Priority Register",
+ "offset": 788,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR6": {
+ "description": "Interrupt Priority Register",
+ "offset": 792,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR7": {
+ "description": "Interrupt Priority Register",
+ "offset": 796,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR8": {
+ "description": "Interrupt Priority Register",
+ "offset": 800,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR9": {
+ "description": "Interrupt Priority Register",
+ "offset": 804,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR10": {
+ "description": "Interrupt Priority Register",
+ "offset": 808,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR11": {
+ "description": "Interrupt Priority Register",
+ "offset": 812,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR12": {
+ "description": "Interrupt Priority Register",
+ "offset": 816,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR13": {
+ "description": "Interrupt Priority Register",
+ "offset": 820,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR14": {
+ "description": "Interrupt Priority Register",
+ "offset": 824,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "AFIO": {
+ "description": "Alternate function I/O",
+ "children": {
+ "registers": {
+ "EVCR": {
+ "description": "Event Control Register\n (AFIO_EVCR)",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PIN": {
+ "description": "Pin selection",
+ "offset": 0,
+ "size": 4
+ },
+ "PORT": {
+ "description": "Port selection",
+ "offset": 4,
+ "size": 3
+ },
+ "EVOE": {
+ "description": "Event Output Enable",
+ "offset": 7,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MAPR": {
+ "description": "AF remap and debug I/O configuration\n register (AFIO_MAPR)",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SPI1_REMAP": {
+ "description": "SPI1 remapping",
+ "offset": 0,
+ "size": 1
+ },
+ "I2C1_REMAP": {
+ "description": "I2C1 remapping",
+ "offset": 1,
+ "size": 1
+ },
+ "USART1_REMAP": {
+ "description": "USART1 remapping",
+ "offset": 2,
+ "size": 1
+ },
+ "USART2_REMAP": {
+ "description": "USART2 remapping",
+ "offset": 3,
+ "size": 1
+ },
+ "USART3_REMAP": {
+ "description": "USART3 remapping",
+ "offset": 4,
+ "size": 2
+ },
+ "TIM1_REMAP": {
+ "description": "TIM1 remapping",
+ "offset": 6,
+ "size": 2
+ },
+ "TIM2_REMAP": {
+ "description": "TIM2 remapping",
+ "offset": 8,
+ "size": 2
+ },
+ "TIM3_REMAP": {
+ "description": "TIM3 remapping",
+ "offset": 10,
+ "size": 2
+ },
+ "TIM4_REMAP": {
+ "description": "TIM4 remapping",
+ "offset": 12,
+ "size": 1
+ },
+ "CAN_REMAP": {
+ "description": "CAN1 remapping",
+ "offset": 13,
+ "size": 2
+ },
+ "PD01_REMAP": {
+ "description": "Port D0/Port D1 mapping on\n OSCIN/OSCOUT",
+ "offset": 15,
+ "size": 1
+ },
+ "TIM5CH4_IREMAP": {
+ "description": "Set and cleared by\n software",
+ "offset": 16,
+ "size": 1
+ },
+ "ADC1_ETRGINJ_REMAP": {
+ "description": "ADC 1 External trigger injected\n conversion remapping",
+ "offset": 17,
+ "size": 1
+ },
+ "ADC1_ETRGREG_REMAP": {
+ "description": "ADC 1 external trigger regular\n conversion remapping",
+ "offset": 18,
+ "size": 1
+ },
+ "ADC2_ETRGINJ_REMAP": {
+ "description": "ADC 2 external trigger injected\n conversion remapping",
+ "offset": 19,
+ "size": 1
+ },
+ "ADC2_ETRGREG_REMAP": {
+ "description": "ADC 2 external trigger regular\n conversion remapping",
+ "offset": 20,
+ "size": 1
+ },
+ "SWJ_CFG": {
+ "description": "Serial wire JTAG\n configuration",
+ "offset": 24,
+ "size": 3,
+ "access": "write-only"
+ }
+ }
+ }
+ },
+ "EXTICR1": {
+ "description": "External interrupt configuration register 1\n (AFIO_EXTICR1)",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EXTI0": {
+ "description": "EXTI0 configuration",
+ "offset": 0,
+ "size": 4
+ },
+ "EXTI1": {
+ "description": "EXTI1 configuration",
+ "offset": 4,
+ "size": 4
+ },
+ "EXTI2": {
+ "description": "EXTI2 configuration",
+ "offset": 8,
+ "size": 4
+ },
+ "EXTI3": {
+ "description": "EXTI3 configuration",
+ "offset": 12,
+ "size": 4
+ }
+ }
+ }
+ },
+ "EXTICR2": {
+ "description": "External interrupt configuration register 2\n (AFIO_EXTICR2)",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EXTI4": {
+ "description": "EXTI4 configuration",
+ "offset": 0,
+ "size": 4
+ },
+ "EXTI5": {
+ "description": "EXTI5 configuration",
+ "offset": 4,
+ "size": 4
+ },
+ "EXTI6": {
+ "description": "EXTI6 configuration",
+ "offset": 8,
+ "size": 4
+ },
+ "EXTI7": {
+ "description": "EXTI7 configuration",
+ "offset": 12,
+ "size": 4
+ }
+ }
+ }
+ },
+ "EXTICR3": {
+ "description": "External interrupt configuration register 3\n (AFIO_EXTICR3)",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EXTI8": {
+ "description": "EXTI8 configuration",
+ "offset": 0,
+ "size": 4
+ },
+ "EXTI9": {
+ "description": "EXTI9 configuration",
+ "offset": 4,
+ "size": 4
+ },
+ "EXTI10": {
+ "description": "EXTI10 configuration",
+ "offset": 8,
+ "size": 4
+ },
+ "EXTI11": {
+ "description": "EXTI11 configuration",
+ "offset": 12,
+ "size": 4
+ }
+ }
+ }
+ },
+ "EXTICR4": {
+ "description": "External interrupt configuration register 4\n (AFIO_EXTICR4)",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EXTI12": {
+ "description": "EXTI12 configuration",
+ "offset": 0,
+ "size": 4
+ },
+ "EXTI13": {
+ "description": "EXTI13 configuration",
+ "offset": 4,
+ "size": 4
+ },
+ "EXTI14": {
+ "description": "EXTI14 configuration",
+ "offset": 8,
+ "size": 4
+ },
+ "EXTI15": {
+ "description": "EXTI15 configuration",
+ "offset": 12,
+ "size": 4
+ }
+ }
+ }
+ },
+ "MAPR2": {
+ "description": "AF remap and debug I/O configuration\n register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIM9_REMAP": {
+ "description": "TIM9 remapping",
+ "offset": 5,
+ "size": 1
+ },
+ "TIM10_REMAP": {
+ "description": "TIM10 remapping",
+ "offset": 6,
+ "size": 1
+ },
+ "TIM11_REMAP": {
+ "description": "TIM11 remapping",
+ "offset": 7,
+ "size": 1
+ },
+ "TIM13_REMAP": {
+ "description": "TIM13 remapping",
+ "offset": 8,
+ "size": 1
+ },
+ "TIM14_REMAP": {
+ "description": "TIM14 remapping",
+ "offset": 9,
+ "size": 1
+ },
+ "FSMC_NADV": {
+ "description": "NADV connect/disconnect",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "EXTI": {
+ "description": "EXTI",
+ "children": {
+ "registers": {
+ "IMR": {
+ "description": "Interrupt mask register\n (EXTI_IMR)",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MR0": {
+ "description": "Interrupt Mask on line 0",
+ "offset": 0,
+ "size": 1
+ },
+ "MR1": {
+ "description": "Interrupt Mask on line 1",
+ "offset": 1,
+ "size": 1
+ },
+ "MR2": {
+ "description": "Interrupt Mask on line 2",
+ "offset": 2,
+ "size": 1
+ },
+ "MR3": {
+ "description": "Interrupt Mask on line 3",
+ "offset": 3,
+ "size": 1
+ },
+ "MR4": {
+ "description": "Interrupt Mask on line 4",
+ "offset": 4,
+ "size": 1
+ },
+ "MR5": {
+ "description": "Interrupt Mask on line 5",
+ "offset": 5,
+ "size": 1
+ },
+ "MR6": {
+ "description": "Interrupt Mask on line 6",
+ "offset": 6,
+ "size": 1
+ },
+ "MR7": {
+ "description": "Interrupt Mask on line 7",
+ "offset": 7,
+ "size": 1
+ },
+ "MR8": {
+ "description": "Interrupt Mask on line 8",
+ "offset": 8,
+ "size": 1
+ },
+ "MR9": {
+ "description": "Interrupt Mask on line 9",
+ "offset": 9,
+ "size": 1
+ },
+ "MR10": {
+ "description": "Interrupt Mask on line 10",
+ "offset": 10,
+ "size": 1
+ },
+ "MR11": {
+ "description": "Interrupt Mask on line 11",
+ "offset": 11,
+ "size": 1
+ },
+ "MR12": {
+ "description": "Interrupt Mask on line 12",
+ "offset": 12,
+ "size": 1
+ },
+ "MR13": {
+ "description": "Interrupt Mask on line 13",
+ "offset": 13,
+ "size": 1
+ },
+ "MR14": {
+ "description": "Interrupt Mask on line 14",
+ "offset": 14,
+ "size": 1
+ },
+ "MR15": {
+ "description": "Interrupt Mask on line 15",
+ "offset": 15,
+ "size": 1
+ },
+ "MR16": {
+ "description": "Interrupt Mask on line 16",
+ "offset": 16,
+ "size": 1
+ },
+ "MR17": {
+ "description": "Interrupt Mask on line 17",
+ "offset": 17,
+ "size": 1
+ },
+ "MR18": {
+ "description": "Interrupt Mask on line 18",
+ "offset": 18,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EMR": {
+ "description": "Event mask register (EXTI_EMR)",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MR0": {
+ "description": "Event Mask on line 0",
+ "offset": 0,
+ "size": 1
+ },
+ "MR1": {
+ "description": "Event Mask on line 1",
+ "offset": 1,
+ "size": 1
+ },
+ "MR2": {
+ "description": "Event Mask on line 2",
+ "offset": 2,
+ "size": 1
+ },
+ "MR3": {
+ "description": "Event Mask on line 3",
+ "offset": 3,
+ "size": 1
+ },
+ "MR4": {
+ "description": "Event Mask on line 4",
+ "offset": 4,
+ "size": 1
+ },
+ "MR5": {
+ "description": "Event Mask on line 5",
+ "offset": 5,
+ "size": 1
+ },
+ "MR6": {
+ "description": "Event Mask on line 6",
+ "offset": 6,
+ "size": 1
+ },
+ "MR7": {
+ "description": "Event Mask on line 7",
+ "offset": 7,
+ "size": 1
+ },
+ "MR8": {
+ "description": "Event Mask on line 8",
+ "offset": 8,
+ "size": 1
+ },
+ "MR9": {
+ "description": "Event Mask on line 9",
+ "offset": 9,
+ "size": 1
+ },
+ "MR10": {
+ "description": "Event Mask on line 10",
+ "offset": 10,
+ "size": 1
+ },
+ "MR11": {
+ "description": "Event Mask on line 11",
+ "offset": 11,
+ "size": 1
+ },
+ "MR12": {
+ "description": "Event Mask on line 12",
+ "offset": 12,
+ "size": 1
+ },
+ "MR13": {
+ "description": "Event Mask on line 13",
+ "offset": 13,
+ "size": 1
+ },
+ "MR14": {
+ "description": "Event Mask on line 14",
+ "offset": 14,
+ "size": 1
+ },
+ "MR15": {
+ "description": "Event Mask on line 15",
+ "offset": 15,
+ "size": 1
+ },
+ "MR16": {
+ "description": "Event Mask on line 16",
+ "offset": 16,
+ "size": 1
+ },
+ "MR17": {
+ "description": "Event Mask on line 17",
+ "offset": 17,
+ "size": 1
+ },
+ "MR18": {
+ "description": "Event Mask on line 18",
+ "offset": 18,
+ "size": 1
+ }
+ }
+ }
+ },
+ "RTSR": {
+ "description": "Rising Trigger selection register\n (EXTI_RTSR)",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TR0": {
+ "description": "Rising trigger event configuration of\n line 0",
+ "offset": 0,
+ "size": 1
+ },
+ "TR1": {
+ "description": "Rising trigger event configuration of\n line 1",
+ "offset": 1,
+ "size": 1
+ },
+ "TR2": {
+ "description": "Rising trigger event configuration of\n line 2",
+ "offset": 2,
+ "size": 1
+ },
+ "TR3": {
+ "description": "Rising trigger event configuration of\n line 3",
+ "offset": 3,
+ "size": 1
+ },
+ "TR4": {
+ "description": "Rising trigger event configuration of\n line 4",
+ "offset": 4,
+ "size": 1
+ },
+ "TR5": {
+ "description": "Rising trigger event configuration of\n line 5",
+ "offset": 5,
+ "size": 1
+ },
+ "TR6": {
+ "description": "Rising trigger event configuration of\n line 6",
+ "offset": 6,
+ "size": 1
+ },
+ "TR7": {
+ "description": "Rising trigger event configuration of\n line 7",
+ "offset": 7,
+ "size": 1
+ },
+ "TR8": {
+ "description": "Rising trigger event configuration of\n line 8",
+ "offset": 8,
+ "size": 1
+ },
+ "TR9": {
+ "description": "Rising trigger event configuration of\n line 9",
+ "offset": 9,
+ "size": 1
+ },
+ "TR10": {
+ "description": "Rising trigger event configuration of\n line 10",
+ "offset": 10,
+ "size": 1
+ },
+ "TR11": {
+ "description": "Rising trigger event configuration of\n line 11",
+ "offset": 11,
+ "size": 1
+ },
+ "TR12": {
+ "description": "Rising trigger event configuration of\n line 12",
+ "offset": 12,
+ "size": 1
+ },
+ "TR13": {
+ "description": "Rising trigger event configuration of\n line 13",
+ "offset": 13,
+ "size": 1
+ },
+ "TR14": {
+ "description": "Rising trigger event configuration of\n line 14",
+ "offset": 14,
+ "size": 1
+ },
+ "TR15": {
+ "description": "Rising trigger event configuration of\n line 15",
+ "offset": 15,
+ "size": 1
+ },
+ "TR16": {
+ "description": "Rising trigger event configuration of\n line 16",
+ "offset": 16,
+ "size": 1
+ },
+ "TR17": {
+ "description": "Rising trigger event configuration of\n line 17",
+ "offset": 17,
+ "size": 1
+ },
+ "TR18": {
+ "description": "Rising trigger event configuration of\n line 18",
+ "offset": 18,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FTSR": {
+ "description": "Falling Trigger selection register\n (EXTI_FTSR)",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TR0": {
+ "description": "Falling trigger event configuration of\n line 0",
+ "offset": 0,
+ "size": 1
+ },
+ "TR1": {
+ "description": "Falling trigger event configuration of\n line 1",
+ "offset": 1,
+ "size": 1
+ },
+ "TR2": {
+ "description": "Falling trigger event configuration of\n line 2",
+ "offset": 2,
+ "size": 1
+ },
+ "TR3": {
+ "description": "Falling trigger event configuration of\n line 3",
+ "offset": 3,
+ "size": 1
+ },
+ "TR4": {
+ "description": "Falling trigger event configuration of\n line 4",
+ "offset": 4,
+ "size": 1
+ },
+ "TR5": {
+ "description": "Falling trigger event configuration of\n line 5",
+ "offset": 5,
+ "size": 1
+ },
+ "TR6": {
+ "description": "Falling trigger event configuration of\n line 6",
+ "offset": 6,
+ "size": 1
+ },
+ "TR7": {
+ "description": "Falling trigger event configuration of\n line 7",
+ "offset": 7,
+ "size": 1
+ },
+ "TR8": {
+ "description": "Falling trigger event configuration of\n line 8",
+ "offset": 8,
+ "size": 1
+ },
+ "TR9": {
+ "description": "Falling trigger event configuration of\n line 9",
+ "offset": 9,
+ "size": 1
+ },
+ "TR10": {
+ "description": "Falling trigger event configuration of\n line 10",
+ "offset": 10,
+ "size": 1
+ },
+ "TR11": {
+ "description": "Falling trigger event configuration of\n line 11",
+ "offset": 11,
+ "size": 1
+ },
+ "TR12": {
+ "description": "Falling trigger event configuration of\n line 12",
+ "offset": 12,
+ "size": 1
+ },
+ "TR13": {
+ "description": "Falling trigger event configuration of\n line 13",
+ "offset": 13,
+ "size": 1
+ },
+ "TR14": {
+ "description": "Falling trigger event configuration of\n line 14",
+ "offset": 14,
+ "size": 1
+ },
+ "TR15": {
+ "description": "Falling trigger event configuration of\n line 15",
+ "offset": 15,
+ "size": 1
+ },
+ "TR16": {
+ "description": "Falling trigger event configuration of\n line 16",
+ "offset": 16,
+ "size": 1
+ },
+ "TR17": {
+ "description": "Falling trigger event configuration of\n line 17",
+ "offset": 17,
+ "size": 1
+ },
+ "TR18": {
+ "description": "Falling trigger event configuration of\n line 18",
+ "offset": 18,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SWIER": {
+ "description": "Software interrupt event register\n (EXTI_SWIER)",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SWIER0": {
+ "description": "Software Interrupt on line\n 0",
+ "offset": 0,
+ "size": 1
+ },
+ "SWIER1": {
+ "description": "Software Interrupt on line\n 1",
+ "offset": 1,
+ "size": 1
+ },
+ "SWIER2": {
+ "description": "Software Interrupt on line\n 2",
+ "offset": 2,
+ "size": 1
+ },
+ "SWIER3": {
+ "description": "Software Interrupt on line\n 3",
+ "offset": 3,
+ "size": 1
+ },
+ "SWIER4": {
+ "description": "Software Interrupt on line\n 4",
+ "offset": 4,
+ "size": 1
+ },
+ "SWIER5": {
+ "description": "Software Interrupt on line\n 5",
+ "offset": 5,
+ "size": 1
+ },
+ "SWIER6": {
+ "description": "Software Interrupt on line\n 6",
+ "offset": 6,
+ "size": 1
+ },
+ "SWIER7": {
+ "description": "Software Interrupt on line\n 7",
+ "offset": 7,
+ "size": 1
+ },
+ "SWIER8": {
+ "description": "Software Interrupt on line\n 8",
+ "offset": 8,
+ "size": 1
+ },
+ "SWIER9": {
+ "description": "Software Interrupt on line\n 9",
+ "offset": 9,
+ "size": 1
+ },
+ "SWIER10": {
+ "description": "Software Interrupt on line\n 10",
+ "offset": 10,
+ "size": 1
+ },
+ "SWIER11": {
+ "description": "Software Interrupt on line\n 11",
+ "offset": 11,
+ "size": 1
+ },
+ "SWIER12": {
+ "description": "Software Interrupt on line\n 12",
+ "offset": 12,
+ "size": 1
+ },
+ "SWIER13": {
+ "description": "Software Interrupt on line\n 13",
+ "offset": 13,
+ "size": 1
+ },
+ "SWIER14": {
+ "description": "Software Interrupt on line\n 14",
+ "offset": 14,
+ "size": 1
+ },
+ "SWIER15": {
+ "description": "Software Interrupt on line\n 15",
+ "offset": 15,
+ "size": 1
+ },
+ "SWIER16": {
+ "description": "Software Interrupt on line\n 16",
+ "offset": 16,
+ "size": 1
+ },
+ "SWIER17": {
+ "description": "Software Interrupt on line\n 17",
+ "offset": 17,
+ "size": 1
+ },
+ "SWIER18": {
+ "description": "Software Interrupt on line\n 18",
+ "offset": 18,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PR": {
+ "description": "Pending register (EXTI_PR)",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PR0": {
+ "description": "Pending bit 0",
+ "offset": 0,
+ "size": 1
+ },
+ "PR1": {
+ "description": "Pending bit 1",
+ "offset": 1,
+ "size": 1
+ },
+ "PR2": {
+ "description": "Pending bit 2",
+ "offset": 2,
+ "size": 1
+ },
+ "PR3": {
+ "description": "Pending bit 3",
+ "offset": 3,
+ "size": 1
+ },
+ "PR4": {
+ "description": "Pending bit 4",
+ "offset": 4,
+ "size": 1
+ },
+ "PR5": {
+ "description": "Pending bit 5",
+ "offset": 5,
+ "size": 1
+ },
+ "PR6": {
+ "description": "Pending bit 6",
+ "offset": 6,
+ "size": 1
+ },
+ "PR7": {
+ "description": "Pending bit 7",
+ "offset": 7,
+ "size": 1
+ },
+ "PR8": {
+ "description": "Pending bit 8",
+ "offset": 8,
+ "size": 1
+ },
+ "PR9": {
+ "description": "Pending bit 9",
+ "offset": 9,
+ "size": 1
+ },
+ "PR10": {
+ "description": "Pending bit 10",
+ "offset": 10,
+ "size": 1
+ },
+ "PR11": {
+ "description": "Pending bit 11",
+ "offset": 11,
+ "size": 1
+ },
+ "PR12": {
+ "description": "Pending bit 12",
+ "offset": 12,
+ "size": 1
+ },
+ "PR13": {
+ "description": "Pending bit 13",
+ "offset": 13,
+ "size": 1
+ },
+ "PR14": {
+ "description": "Pending bit 14",
+ "offset": 14,
+ "size": 1
+ },
+ "PR15": {
+ "description": "Pending bit 15",
+ "offset": 15,
+ "size": 1
+ },
+ "PR16": {
+ "description": "Pending bit 16",
+ "offset": 16,
+ "size": 1
+ },
+ "PR17": {
+ "description": "Pending bit 17",
+ "offset": 17,
+ "size": 1
+ },
+ "PR18": {
+ "description": "Pending bit 18",
+ "offset": 18,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "DMA1": {
+ "description": "DMA controller",
+ "children": {
+ "registers": {
+ "ISR": {
+ "description": "DMA interrupt status register\n (DMA_ISR)",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "GIF1": {
+ "description": "Channel 1 Global interrupt\n flag",
+ "offset": 0,
+ "size": 1
+ },
+ "TCIF1": {
+ "description": "Channel 1 Transfer Complete\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "HTIF1": {
+ "description": "Channel 1 Half Transfer Complete\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "TEIF1": {
+ "description": "Channel 1 Transfer Error\n flag",
+ "offset": 3,
+ "size": 1
+ },
+ "GIF2": {
+ "description": "Channel 2 Global interrupt\n flag",
+ "offset": 4,
+ "size": 1
+ },
+ "TCIF2": {
+ "description": "Channel 2 Transfer Complete\n flag",
+ "offset": 5,
+ "size": 1
+ },
+ "HTIF2": {
+ "description": "Channel 2 Half Transfer Complete\n flag",
+ "offset": 6,
+ "size": 1
+ },
+ "TEIF2": {
+ "description": "Channel 2 Transfer Error\n flag",
+ "offset": 7,
+ "size": 1
+ },
+ "GIF3": {
+ "description": "Channel 3 Global interrupt\n flag",
+ "offset": 8,
+ "size": 1
+ },
+ "TCIF3": {
+ "description": "Channel 3 Transfer Complete\n flag",
+ "offset": 9,
+ "size": 1
+ },
+ "HTIF3": {
+ "description": "Channel 3 Half Transfer Complete\n flag",
+ "offset": 10,
+ "size": 1
+ },
+ "TEIF3": {
+ "description": "Channel 3 Transfer Error\n flag",
+ "offset": 11,
+ "size": 1
+ },
+ "GIF4": {
+ "description": "Channel 4 Global interrupt\n flag",
+ "offset": 12,
+ "size": 1
+ },
+ "TCIF4": {
+ "description": "Channel 4 Transfer Complete\n flag",
+ "offset": 13,
+ "size": 1
+ },
+ "HTIF4": {
+ "description": "Channel 4 Half Transfer Complete\n flag",
+ "offset": 14,
+ "size": 1
+ },
+ "TEIF4": {
+ "description": "Channel 4 Transfer Error\n flag",
+ "offset": 15,
+ "size": 1
+ },
+ "GIF5": {
+ "description": "Channel 5 Global interrupt\n flag",
+ "offset": 16,
+ "size": 1
+ },
+ "TCIF5": {
+ "description": "Channel 5 Transfer Complete\n flag",
+ "offset": 17,
+ "size": 1
+ },
+ "HTIF5": {
+ "description": "Channel 5 Half Transfer Complete\n flag",
+ "offset": 18,
+ "size": 1
+ },
+ "TEIF5": {
+ "description": "Channel 5 Transfer Error\n flag",
+ "offset": 19,
+ "size": 1
+ },
+ "GIF6": {
+ "description": "Channel 6 Global interrupt\n flag",
+ "offset": 20,
+ "size": 1
+ },
+ "TCIF6": {
+ "description": "Channel 6 Transfer Complete\n flag",
+ "offset": 21,
+ "size": 1
+ },
+ "HTIF6": {
+ "description": "Channel 6 Half Transfer Complete\n flag",
+ "offset": 22,
+ "size": 1
+ },
+ "TEIF6": {
+ "description": "Channel 6 Transfer Error\n flag",
+ "offset": 23,
+ "size": 1
+ },
+ "GIF7": {
+ "description": "Channel 7 Global interrupt\n flag",
+ "offset": 24,
+ "size": 1
+ },
+ "TCIF7": {
+ "description": "Channel 7 Transfer Complete\n flag",
+ "offset": 25,
+ "size": 1
+ },
+ "HTIF7": {
+ "description": "Channel 7 Half Transfer Complete\n flag",
+ "offset": 26,
+ "size": 1
+ },
+ "TEIF7": {
+ "description": "Channel 7 Transfer Error\n flag",
+ "offset": 27,
+ "size": 1
+ }
+ }
+ }
+ },
+ "IFCR": {
+ "description": "DMA interrupt flag clear register\n (DMA_IFCR)",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "CGIF1": {
+ "description": "Channel 1 Global interrupt\n clear",
+ "offset": 0,
+ "size": 1
+ },
+ "CGIF2": {
+ "description": "Channel 2 Global interrupt\n clear",
+ "offset": 4,
+ "size": 1
+ },
+ "CGIF3": {
+ "description": "Channel 3 Global interrupt\n clear",
+ "offset": 8,
+ "size": 1
+ },
+ "CGIF4": {
+ "description": "Channel 4 Global interrupt\n clear",
+ "offset": 12,
+ "size": 1
+ },
+ "CGIF5": {
+ "description": "Channel 5 Global interrupt\n clear",
+ "offset": 16,
+ "size": 1
+ },
+ "CGIF6": {
+ "description": "Channel 6 Global interrupt\n clear",
+ "offset": 20,
+ "size": 1
+ },
+ "CGIF7": {
+ "description": "Channel 7 Global interrupt\n clear",
+ "offset": 24,
+ "size": 1
+ },
+ "CTCIF1": {
+ "description": "Channel 1 Transfer Complete\n clear",
+ "offset": 1,
+ "size": 1
+ },
+ "CTCIF2": {
+ "description": "Channel 2 Transfer Complete\n clear",
+ "offset": 5,
+ "size": 1
+ },
+ "CTCIF3": {
+ "description": "Channel 3 Transfer Complete\n clear",
+ "offset": 9,
+ "size": 1
+ },
+ "CTCIF4": {
+ "description": "Channel 4 Transfer Complete\n clear",
+ "offset": 13,
+ "size": 1
+ },
+ "CTCIF5": {
+ "description": "Channel 5 Transfer Complete\n clear",
+ "offset": 17,
+ "size": 1
+ },
+ "CTCIF6": {
+ "description": "Channel 6 Transfer Complete\n clear",
+ "offset": 21,
+ "size": 1
+ },
+ "CTCIF7": {
+ "description": "Channel 7 Transfer Complete\n clear",
+ "offset": 25,
+ "size": 1
+ },
+ "CHTIF1": {
+ "description": "Channel 1 Half Transfer\n clear",
+ "offset": 2,
+ "size": 1
+ },
+ "CHTIF2": {
+ "description": "Channel 2 Half Transfer\n clear",
+ "offset": 6,
+ "size": 1
+ },
+ "CHTIF3": {
+ "description": "Channel 3 Half Transfer\n clear",
+ "offset": 10,
+ "size": 1
+ },
+ "CHTIF4": {
+ "description": "Channel 4 Half Transfer\n clear",
+ "offset": 14,
+ "size": 1
+ },
+ "CHTIF5": {
+ "description": "Channel 5 Half Transfer\n clear",
+ "offset": 18,
+ "size": 1
+ },
+ "CHTIF6": {
+ "description": "Channel 6 Half Transfer\n clear",
+ "offset": 22,
+ "size": 1
+ },
+ "CHTIF7": {
+ "description": "Channel 7 Half Transfer\n clear",
+ "offset": 26,
+ "size": 1
+ },
+ "CTEIF1": {
+ "description": "Channel 1 Transfer Error\n clear",
+ "offset": 3,
+ "size": 1
+ },
+ "CTEIF2": {
+ "description": "Channel 2 Transfer Error\n clear",
+ "offset": 7,
+ "size": 1
+ },
+ "CTEIF3": {
+ "description": "Channel 3 Transfer Error\n clear",
+ "offset": 11,
+ "size": 1
+ },
+ "CTEIF4": {
+ "description": "Channel 4 Transfer Error\n clear",
+ "offset": 15,
+ "size": 1
+ },
+ "CTEIF5": {
+ "description": "Channel 5 Transfer Error\n clear",
+ "offset": 19,
+ "size": 1
+ },
+ "CTEIF6": {
+ "description": "Channel 6 Transfer Error\n clear",
+ "offset": 23,
+ "size": 1
+ },
+ "CTEIF7": {
+ "description": "Channel 7 Transfer Error\n clear",
+ "offset": 27,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCR1": {
+ "description": "DMA channel configuration register\n (DMA_CCR)",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EN": {
+ "description": "Channel enable",
+ "offset": 0,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half Transfer interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 4,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 5,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 6,
+ "size": 1
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 7,
+ "size": 1
+ },
+ "PSIZE": {
+ "description": "Peripheral size",
+ "offset": 8,
+ "size": 2
+ },
+ "MSIZE": {
+ "description": "Memory size",
+ "offset": 10,
+ "size": 2
+ },
+ "PL": {
+ "description": "Channel Priority level",
+ "offset": 12,
+ "size": 2
+ },
+ "MEM2MEM": {
+ "description": "Memory to memory mode",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNDTR1": {
+ "description": "DMA channel 1 number of data\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data to transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CPAR1": {
+ "description": "DMA channel 1 peripheral address\n register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CMAR1": {
+ "description": "DMA channel 1 memory address\n register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MA": {
+ "description": "Memory address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CCR2": {
+ "description": "DMA channel configuration register\n (DMA_CCR)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EN": {
+ "description": "Channel enable",
+ "offset": 0,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half Transfer interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 4,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 5,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 6,
+ "size": 1
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 7,
+ "size": 1
+ },
+ "PSIZE": {
+ "description": "Peripheral size",
+ "offset": 8,
+ "size": 2
+ },
+ "MSIZE": {
+ "description": "Memory size",
+ "offset": 10,
+ "size": 2
+ },
+ "PL": {
+ "description": "Channel Priority level",
+ "offset": 12,
+ "size": 2
+ },
+ "MEM2MEM": {
+ "description": "Memory to memory mode",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNDTR2": {
+ "description": "DMA channel 2 number of data\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data to transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CPAR2": {
+ "description": "DMA channel 2 peripheral address\n register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CMAR2": {
+ "description": "DMA channel 2 memory address\n register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MA": {
+ "description": "Memory address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CCR3": {
+ "description": "DMA channel configuration register\n (DMA_CCR)",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EN": {
+ "description": "Channel enable",
+ "offset": 0,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half Transfer interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 4,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 5,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 6,
+ "size": 1
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 7,
+ "size": 1
+ },
+ "PSIZE": {
+ "description": "Peripheral size",
+ "offset": 8,
+ "size": 2
+ },
+ "MSIZE": {
+ "description": "Memory size",
+ "offset": 10,
+ "size": 2
+ },
+ "PL": {
+ "description": "Channel Priority level",
+ "offset": 12,
+ "size": 2
+ },
+ "MEM2MEM": {
+ "description": "Memory to memory mode",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNDTR3": {
+ "description": "DMA channel 3 number of data\n register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data to transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CPAR3": {
+ "description": "DMA channel 3 peripheral address\n register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CMAR3": {
+ "description": "DMA channel 3 memory address\n register",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MA": {
+ "description": "Memory address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CCR4": {
+ "description": "DMA channel configuration register\n (DMA_CCR)",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EN": {
+ "description": "Channel enable",
+ "offset": 0,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half Transfer interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 4,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 5,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 6,
+ "size": 1
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 7,
+ "size": 1
+ },
+ "PSIZE": {
+ "description": "Peripheral size",
+ "offset": 8,
+ "size": 2
+ },
+ "MSIZE": {
+ "description": "Memory size",
+ "offset": 10,
+ "size": 2
+ },
+ "PL": {
+ "description": "Channel Priority level",
+ "offset": 12,
+ "size": 2
+ },
+ "MEM2MEM": {
+ "description": "Memory to memory mode",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNDTR4": {
+ "description": "DMA channel 4 number of data\n register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data to transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CPAR4": {
+ "description": "DMA channel 4 peripheral address\n register",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CMAR4": {
+ "description": "DMA channel 4 memory address\n register",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MA": {
+ "description": "Memory address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CCR5": {
+ "description": "DMA channel configuration register\n (DMA_CCR)",
+ "offset": 88,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EN": {
+ "description": "Channel enable",
+ "offset": 0,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half Transfer interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 4,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 5,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 6,
+ "size": 1
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 7,
+ "size": 1
+ },
+ "PSIZE": {
+ "description": "Peripheral size",
+ "offset": 8,
+ "size": 2
+ },
+ "MSIZE": {
+ "description": "Memory size",
+ "offset": 10,
+ "size": 2
+ },
+ "PL": {
+ "description": "Channel Priority level",
+ "offset": 12,
+ "size": 2
+ },
+ "MEM2MEM": {
+ "description": "Memory to memory mode",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNDTR5": {
+ "description": "DMA channel 5 number of data\n register",
+ "offset": 92,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data to transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CPAR5": {
+ "description": "DMA channel 5 peripheral address\n register",
+ "offset": 96,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CMAR5": {
+ "description": "DMA channel 5 memory address\n register",
+ "offset": 100,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MA": {
+ "description": "Memory address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CCR6": {
+ "description": "DMA channel configuration register\n (DMA_CCR)",
+ "offset": 108,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EN": {
+ "description": "Channel enable",
+ "offset": 0,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half Transfer interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 4,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 5,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 6,
+ "size": 1
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 7,
+ "size": 1
+ },
+ "PSIZE": {
+ "description": "Peripheral size",
+ "offset": 8,
+ "size": 2
+ },
+ "MSIZE": {
+ "description": "Memory size",
+ "offset": 10,
+ "size": 2
+ },
+ "PL": {
+ "description": "Channel Priority level",
+ "offset": 12,
+ "size": 2
+ },
+ "MEM2MEM": {
+ "description": "Memory to memory mode",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNDTR6": {
+ "description": "DMA channel 6 number of data\n register",
+ "offset": 112,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data to transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CPAR6": {
+ "description": "DMA channel 6 peripheral address\n register",
+ "offset": 116,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CMAR6": {
+ "description": "DMA channel 6 memory address\n register",
+ "offset": 120,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MA": {
+ "description": "Memory address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CCR7": {
+ "description": "DMA channel configuration register\n (DMA_CCR)",
+ "offset": 128,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EN": {
+ "description": "Channel enable",
+ "offset": 0,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half Transfer interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 4,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 5,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 6,
+ "size": 1
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 7,
+ "size": 1
+ },
+ "PSIZE": {
+ "description": "Peripheral size",
+ "offset": 8,
+ "size": 2
+ },
+ "MSIZE": {
+ "description": "Memory size",
+ "offset": 10,
+ "size": 2
+ },
+ "PL": {
+ "description": "Channel Priority level",
+ "offset": 12,
+ "size": 2
+ },
+ "MEM2MEM": {
+ "description": "Memory to memory mode",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNDTR7": {
+ "description": "DMA channel 7 number of data\n register",
+ "offset": 132,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data to transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CPAR7": {
+ "description": "DMA channel 7 peripheral address\n register",
+ "offset": 136,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CMAR7": {
+ "description": "DMA channel 7 memory address\n register",
+ "offset": 140,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MA": {
+ "description": "Memory address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "ETHERNET_DMA": {
+ "description": "Ethernet: DMA controller operation",
+ "children": {
+ "registers": {
+ "DMABMR": {
+ "description": "Ethernet DMA bus mode register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 131329,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SR": {
+ "description": "Software reset",
+ "offset": 0,
+ "size": 1
+ },
+ "DA": {
+ "description": "DMA Arbitration",
+ "offset": 1,
+ "size": 1
+ },
+ "DSL": {
+ "description": "Descriptor skip length",
+ "offset": 2,
+ "size": 5
+ },
+ "PBL": {
+ "description": "Programmable burst length",
+ "offset": 8,
+ "size": 6
+ },
+ "RTPR": {
+ "description": "Rx Tx priority ratio",
+ "offset": 14,
+ "size": 2
+ },
+ "FB": {
+ "description": "Fixed burst",
+ "offset": 16,
+ "size": 1
+ },
+ "RDP": {
+ "description": "Rx DMA PBL",
+ "offset": 17,
+ "size": 6
+ },
+ "USP": {
+ "description": "Use separate PBL",
+ "offset": 23,
+ "size": 1
+ },
+ "FPM": {
+ "description": "4xPBL mode",
+ "offset": 24,
+ "size": 1
+ },
+ "AAB": {
+ "description": "Address-aligned beats",
+ "offset": 25,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DMATPDR": {
+ "description": "Ethernet DMA transmit poll demand\n register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TPD": {
+ "description": "Transmit poll demand",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DMARPDR": {
+ "description": "EHERNET DMA receive poll demand\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RPD": {
+ "description": "Receive poll demand",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DMARDLAR": {
+ "description": "Ethernet DMA receive descriptor list address\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SRL": {
+ "description": "Start of receive list",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DMATDLAR": {
+ "description": "Ethernet DMA transmit descriptor list\n address register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "STL": {
+ "description": "Start of transmit list",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DMASR": {
+ "description": "Ethernet DMA status register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TS": {
+ "description": "Transmit status",
+ "offset": 0,
+ "size": 1
+ },
+ "TPSS": {
+ "description": "Transmit process stopped\n status",
+ "offset": 1,
+ "size": 1
+ },
+ "TBUS": {
+ "description": "Transmit buffer unavailable\n status",
+ "offset": 2,
+ "size": 1
+ },
+ "TJTS": {
+ "description": "Transmit jabber timeout\n status",
+ "offset": 3,
+ "size": 1
+ },
+ "ROS": {
+ "description": "Receive overflow status",
+ "offset": 4,
+ "size": 1
+ },
+ "TUS": {
+ "description": "Transmit underflow status",
+ "offset": 5,
+ "size": 1
+ },
+ "RS": {
+ "description": "Receive status",
+ "offset": 6,
+ "size": 1
+ },
+ "RBUS": {
+ "description": "Receive buffer unavailable\n status",
+ "offset": 7,
+ "size": 1
+ },
+ "RPSS": {
+ "description": "Receive process stopped\n status",
+ "offset": 8,
+ "size": 1
+ },
+ "PWTS": {
+ "description": "Receive watchdog timeout\n status",
+ "offset": 9,
+ "size": 1
+ },
+ "ETS": {
+ "description": "Early transmit status",
+ "offset": 10,
+ "size": 1
+ },
+ "FBES": {
+ "description": "Fatal bus error status",
+ "offset": 13,
+ "size": 1
+ },
+ "ERS": {
+ "description": "Early receive status",
+ "offset": 14,
+ "size": 1
+ },
+ "AIS": {
+ "description": "Abnormal interrupt summary",
+ "offset": 15,
+ "size": 1
+ },
+ "NIS": {
+ "description": "Normal interrupt summary",
+ "offset": 16,
+ "size": 1
+ },
+ "RPS": {
+ "description": "Receive process state",
+ "offset": 17,
+ "size": 3,
+ "access": "read-only"
+ },
+ "TPS": {
+ "description": "Transmit process state",
+ "offset": 20,
+ "size": 3,
+ "access": "read-only"
+ },
+ "EBS": {
+ "description": "Error bits status",
+ "offset": 23,
+ "size": 3,
+ "access": "read-only"
+ },
+ "MMCS": {
+ "description": "MMC status",
+ "offset": 27,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PMTS": {
+ "description": "PMT status",
+ "offset": 28,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TSTS": {
+ "description": "Time stamp trigger status",
+ "offset": 29,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "DMAOMR": {
+ "description": "Ethernet DMA operation mode\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SR": {
+ "description": "SR",
+ "offset": 1,
+ "size": 1
+ },
+ "OSF": {
+ "description": "OSF",
+ "offset": 2,
+ "size": 1
+ },
+ "RTC": {
+ "description": "RTC",
+ "offset": 3,
+ "size": 2
+ },
+ "FUGF": {
+ "description": "FUGF",
+ "offset": 6,
+ "size": 1
+ },
+ "FEF": {
+ "description": "FEF",
+ "offset": 7,
+ "size": 1
+ },
+ "ST": {
+ "description": "ST",
+ "offset": 13,
+ "size": 1
+ },
+ "TTC": {
+ "description": "TTC",
+ "offset": 14,
+ "size": 3
+ },
+ "FTF": {
+ "description": "FTF",
+ "offset": 20,
+ "size": 1
+ },
+ "TSF": {
+ "description": "TSF",
+ "offset": 21,
+ "size": 1
+ },
+ "DFRF": {
+ "description": "DFRF",
+ "offset": 24,
+ "size": 1
+ },
+ "RSF": {
+ "description": "RSF",
+ "offset": 25,
+ "size": 1
+ },
+ "DTCEFD": {
+ "description": "DTCEFD",
+ "offset": 26,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DMAIER": {
+ "description": "Ethernet DMA interrupt enable\n register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIE": {
+ "description": "Transmit interrupt enable",
+ "offset": 0,
+ "size": 1
+ },
+ "TPSIE": {
+ "description": "Transmit process stopped interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "TBUIE": {
+ "description": "Transmit buffer unavailable interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TJTIE": {
+ "description": "Transmit jabber timeout interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "ROIE": {
+ "description": "Overflow interrupt enable",
+ "offset": 4,
+ "size": 1
+ },
+ "TUIE": {
+ "description": "Underflow interrupt enable",
+ "offset": 5,
+ "size": 1
+ },
+ "RIE": {
+ "description": "Receive interrupt enable",
+ "offset": 6,
+ "size": 1
+ },
+ "RBUIE": {
+ "description": "Receive buffer unavailable interrupt\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "RPSIE": {
+ "description": "Receive process stopped interrupt\n enable",
+ "offset": 8,
+ "size": 1
+ },
+ "RWTIE": {
+ "description": "receive watchdog timeout interrupt\n enable",
+ "offset": 9,
+ "size": 1
+ },
+ "ETIE": {
+ "description": "Early transmit interrupt\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "FBEIE": {
+ "description": "Fatal bus error interrupt\n enable",
+ "offset": 13,
+ "size": 1
+ },
+ "ERIE": {
+ "description": "Early receive interrupt\n enable",
+ "offset": 14,
+ "size": 1
+ },
+ "AISE": {
+ "description": "Abnormal interrupt summary\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "NISE": {
+ "description": "Normal interrupt summary\n enable",
+ "offset": 16,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DMAMFBOCR": {
+ "description": "Ethernet DMA missed frame and buffer\n overflow counter register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "MFC": {
+ "description": "Missed frames by the\n controller",
+ "offset": 0,
+ "size": 16
+ },
+ "OMFC": {
+ "description": "Overflow bit for missed frame\n counter",
+ "offset": 16,
+ "size": 1
+ },
+ "MFA": {
+ "description": "Missed frames by the\n application",
+ "offset": 17,
+ "size": 11
+ },
+ "OFOC": {
+ "description": "Overflow bit for FIFO overflow\n counter",
+ "offset": 28,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DMACHTDR": {
+ "description": "Ethernet DMA current host transmit\n descriptor register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "HTDAP": {
+ "description": "Host transmit descriptor address\n pointer",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DMACHRDR": {
+ "description": "Ethernet DMA current host receive descriptor\n register",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "HRDAP": {
+ "description": "Host receive descriptor address\n pointer",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DMACHTBAR": {
+ "description": "Ethernet DMA current host transmit buffer\n address register",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "HTBAP": {
+ "description": "Host transmit buffer address\n pointer",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DMACHRBAR": {
+ "description": "Ethernet DMA current host receive buffer\n address register",
+ "offset": 84,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "HRBAP": {
+ "description": "Host receive buffer address\n pointer",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "SDIO": {
+ "description": "Secure digital input/output\n interface",
+ "children": {
+ "registers": {
+ "POWER": {
+ "description": "Bits 1:0 = PWRCTRL: Power supply control\n bits",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PWRCTRL": {
+ "description": "PWRCTRL",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CLKCR": {
+ "description": "SDI clock control register\n (SDIO_CLKCR)",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CLKDIV": {
+ "description": "Clock divide factor",
+ "offset": 0,
+ "size": 8
+ },
+ "CLKEN": {
+ "description": "Clock enable bit",
+ "offset": 8,
+ "size": 1
+ },
+ "PWRSAV": {
+ "description": "Power saving configuration\n bit",
+ "offset": 9,
+ "size": 1
+ },
+ "BYPASS": {
+ "description": "Clock divider bypass enable\n bit",
+ "offset": 10,
+ "size": 1
+ },
+ "WIDBUS": {
+ "description": "Wide bus mode enable bit",
+ "offset": 11,
+ "size": 2
+ },
+ "NEGEDGE": {
+ "description": "SDIO_CK dephasing selection\n bit",
+ "offset": 13,
+ "size": 1
+ },
+ "HWFC_EN": {
+ "description": "HW Flow Control enable",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ARG": {
+ "description": "Bits 31:0 = : Command argument",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CMDARG": {
+ "description": "Command argument",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CMD": {
+ "description": "SDIO command register\n (SDIO_CMD)",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CMDINDEX": {
+ "description": "CMDINDEX",
+ "offset": 0,
+ "size": 6
+ },
+ "WAITRESP": {
+ "description": "WAITRESP",
+ "offset": 6,
+ "size": 2
+ },
+ "WAITINT": {
+ "description": "WAITINT",
+ "offset": 8,
+ "size": 1
+ },
+ "WAITPEND": {
+ "description": "WAITPEND",
+ "offset": 9,
+ "size": 1
+ },
+ "CPSMEN": {
+ "description": "CPSMEN",
+ "offset": 10,
+ "size": 1
+ },
+ "SDIOSuspend": {
+ "description": "SDIOSuspend",
+ "offset": 11,
+ "size": 1
+ },
+ "ENCMDcompl": {
+ "description": "ENCMDcompl",
+ "offset": 12,
+ "size": 1
+ },
+ "nIEN": {
+ "description": "nIEN",
+ "offset": 13,
+ "size": 1
+ },
+ "CE_ATACMD": {
+ "description": "CE_ATACMD",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "RESPCMD": {
+ "description": "SDIO command register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "RESPCMD": {
+ "description": "RESPCMD",
+ "offset": 0,
+ "size": 6
+ }
+ }
+ }
+ },
+ "RESPI1": {
+ "description": "Bits 31:0 = CARDSTATUS1",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CARDSTATUS1": {
+ "description": "CARDSTATUS1",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "RESP2": {
+ "description": "Bits 31:0 = CARDSTATUS2",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CARDSTATUS2": {
+ "description": "CARDSTATUS2",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "RESP3": {
+ "description": "Bits 31:0 = CARDSTATUS3",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CARDSTATUS3": {
+ "description": "CARDSTATUS3",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "RESP4": {
+ "description": "Bits 31:0 = CARDSTATUS4",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CARDSTATUS4": {
+ "description": "CARDSTATUS4",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DTIMER": {
+ "description": "Bits 31:0 = DATATIME: Data timeout\n period",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATATIME": {
+ "description": "Data timeout period",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DLEN": {
+ "description": "Bits 24:0 = DATALENGTH: Data length\n value",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATALENGTH": {
+ "description": "Data length value",
+ "offset": 0,
+ "size": 25
+ }
+ }
+ }
+ },
+ "DCTRL": {
+ "description": "SDIO data control register\n (SDIO_DCTRL)",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DTEN": {
+ "description": "DTEN",
+ "offset": 0,
+ "size": 1
+ },
+ "DTDIR": {
+ "description": "DTDIR",
+ "offset": 1,
+ "size": 1
+ },
+ "DTMODE": {
+ "description": "DTMODE",
+ "offset": 2,
+ "size": 1
+ },
+ "DMAEN": {
+ "description": "DMAEN",
+ "offset": 3,
+ "size": 1
+ },
+ "DBLOCKSIZE": {
+ "description": "DBLOCKSIZE",
+ "offset": 4,
+ "size": 4
+ },
+ "PWSTART": {
+ "description": "PWSTART",
+ "offset": 8,
+ "size": 1
+ },
+ "PWSTOP": {
+ "description": "PWSTOP",
+ "offset": 9,
+ "size": 1
+ },
+ "RWMOD": {
+ "description": "RWMOD",
+ "offset": 10,
+ "size": 1
+ },
+ "SDIOEN": {
+ "description": "SDIOEN",
+ "offset": 11,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DCOUNT": {
+ "description": "Bits 24:0 = DATACOUNT: Data count\n value",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DATACOUNT": {
+ "description": "Data count value",
+ "offset": 0,
+ "size": 25
+ }
+ }
+ }
+ },
+ "STA": {
+ "description": "SDIO status register\n (SDIO_STA)",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CCRCFAIL": {
+ "description": "CCRCFAIL",
+ "offset": 0,
+ "size": 1
+ },
+ "DCRCFAIL": {
+ "description": "DCRCFAIL",
+ "offset": 1,
+ "size": 1
+ },
+ "CTIMEOUT": {
+ "description": "CTIMEOUT",
+ "offset": 2,
+ "size": 1
+ },
+ "DTIMEOUT": {
+ "description": "DTIMEOUT",
+ "offset": 3,
+ "size": 1
+ },
+ "TXUNDERR": {
+ "description": "TXUNDERR",
+ "offset": 4,
+ "size": 1
+ },
+ "RXOVERR": {
+ "description": "RXOVERR",
+ "offset": 5,
+ "size": 1
+ },
+ "CMDREND": {
+ "description": "CMDREND",
+ "offset": 6,
+ "size": 1
+ },
+ "CMDSENT": {
+ "description": "CMDSENT",
+ "offset": 7,
+ "size": 1
+ },
+ "DATAEND": {
+ "description": "DATAEND",
+ "offset": 8,
+ "size": 1
+ },
+ "STBITERR": {
+ "description": "STBITERR",
+ "offset": 9,
+ "size": 1
+ },
+ "DBCKEND": {
+ "description": "DBCKEND",
+ "offset": 10,
+ "size": 1
+ },
+ "CMDACT": {
+ "description": "CMDACT",
+ "offset": 11,
+ "size": 1
+ },
+ "TXACT": {
+ "description": "TXACT",
+ "offset": 12,
+ "size": 1
+ },
+ "RXACT": {
+ "description": "RXACT",
+ "offset": 13,
+ "size": 1
+ },
+ "TXFIFOHE": {
+ "description": "TXFIFOHE",
+ "offset": 14,
+ "size": 1
+ },
+ "RXFIFOHF": {
+ "description": "RXFIFOHF",
+ "offset": 15,
+ "size": 1
+ },
+ "TXFIFOF": {
+ "description": "TXFIFOF",
+ "offset": 16,
+ "size": 1
+ },
+ "RXFIFOF": {
+ "description": "RXFIFOF",
+ "offset": 17,
+ "size": 1
+ },
+ "TXFIFOE": {
+ "description": "TXFIFOE",
+ "offset": 18,
+ "size": 1
+ },
+ "RXFIFOE": {
+ "description": "RXFIFOE",
+ "offset": 19,
+ "size": 1
+ },
+ "TXDAVL": {
+ "description": "TXDAVL",
+ "offset": 20,
+ "size": 1
+ },
+ "RXDAVL": {
+ "description": "RXDAVL",
+ "offset": 21,
+ "size": 1
+ },
+ "SDIOIT": {
+ "description": "SDIOIT",
+ "offset": 22,
+ "size": 1
+ },
+ "CEATAEND": {
+ "description": "CEATAEND",
+ "offset": 23,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ICR": {
+ "description": "SDIO interrupt clear register\n (SDIO_ICR)",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCRCFAILC": {
+ "description": "CCRCFAILC",
+ "offset": 0,
+ "size": 1
+ },
+ "DCRCFAILC": {
+ "description": "DCRCFAILC",
+ "offset": 1,
+ "size": 1
+ },
+ "CTIMEOUTC": {
+ "description": "CTIMEOUTC",
+ "offset": 2,
+ "size": 1
+ },
+ "DTIMEOUTC": {
+ "description": "DTIMEOUTC",
+ "offset": 3,
+ "size": 1
+ },
+ "TXUNDERRC": {
+ "description": "TXUNDERRC",
+ "offset": 4,
+ "size": 1
+ },
+ "RXOVERRC": {
+ "description": "RXOVERRC",
+ "offset": 5,
+ "size": 1
+ },
+ "CMDRENDC": {
+ "description": "CMDRENDC",
+ "offset": 6,
+ "size": 1
+ },
+ "CMDSENTC": {
+ "description": "CMDSENTC",
+ "offset": 7,
+ "size": 1
+ },
+ "DATAENDC": {
+ "description": "DATAENDC",
+ "offset": 8,
+ "size": 1
+ },
+ "STBITERRC": {
+ "description": "STBITERRC",
+ "offset": 9,
+ "size": 1
+ },
+ "DBCKENDC": {
+ "description": "DBCKENDC",
+ "offset": 10,
+ "size": 1
+ },
+ "SDIOITC": {
+ "description": "SDIOITC",
+ "offset": 22,
+ "size": 1
+ },
+ "CEATAENDC": {
+ "description": "CEATAENDC",
+ "offset": 23,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MASK": {
+ "description": "SDIO mask register (SDIO_MASK)",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCRCFAILIE": {
+ "description": "CCRCFAILIE",
+ "offset": 0,
+ "size": 1
+ },
+ "DCRCFAILIE": {
+ "description": "DCRCFAILIE",
+ "offset": 1,
+ "size": 1
+ },
+ "CTIMEOUTIE": {
+ "description": "CTIMEOUTIE",
+ "offset": 2,
+ "size": 1
+ },
+ "DTIMEOUTIE": {
+ "description": "DTIMEOUTIE",
+ "offset": 3,
+ "size": 1
+ },
+ "TXUNDERRIE": {
+ "description": "TXUNDERRIE",
+ "offset": 4,
+ "size": 1
+ },
+ "RXOVERRIE": {
+ "description": "RXOVERRIE",
+ "offset": 5,
+ "size": 1
+ },
+ "CMDRENDIE": {
+ "description": "CMDRENDIE",
+ "offset": 6,
+ "size": 1
+ },
+ "CMDSENTIE": {
+ "description": "CMDSENTIE",
+ "offset": 7,
+ "size": 1
+ },
+ "DATAENDIE": {
+ "description": "DATAENDIE",
+ "offset": 8,
+ "size": 1
+ },
+ "STBITERRIE": {
+ "description": "STBITERRIE",
+ "offset": 9,
+ "size": 1
+ },
+ "DBACKENDIE": {
+ "description": "DBACKENDIE",
+ "offset": 10,
+ "size": 1
+ },
+ "CMDACTIE": {
+ "description": "CMDACTIE",
+ "offset": 11,
+ "size": 1
+ },
+ "TXACTIE": {
+ "description": "TXACTIE",
+ "offset": 12,
+ "size": 1
+ },
+ "RXACTIE": {
+ "description": "RXACTIE",
+ "offset": 13,
+ "size": 1
+ },
+ "TXFIFOHEIE": {
+ "description": "TXFIFOHEIE",
+ "offset": 14,
+ "size": 1
+ },
+ "RXFIFOHFIE": {
+ "description": "RXFIFOHFIE",
+ "offset": 15,
+ "size": 1
+ },
+ "TXFIFOFIE": {
+ "description": "TXFIFOFIE",
+ "offset": 16,
+ "size": 1
+ },
+ "RXFIFOFIE": {
+ "description": "RXFIFOFIE",
+ "offset": 17,
+ "size": 1
+ },
+ "TXFIFOEIE": {
+ "description": "TXFIFOEIE",
+ "offset": 18,
+ "size": 1
+ },
+ "RXFIFOEIE": {
+ "description": "RXFIFOEIE",
+ "offset": 19,
+ "size": 1
+ },
+ "TXDAVLIE": {
+ "description": "TXDAVLIE",
+ "offset": 20,
+ "size": 1
+ },
+ "RXDAVLIE": {
+ "description": "RXDAVLIE",
+ "offset": 21,
+ "size": 1
+ },
+ "SDIOITIE": {
+ "description": "SDIOITIE",
+ "offset": 22,
+ "size": 1
+ },
+ "CEATENDIE": {
+ "description": "CEATENDIE",
+ "offset": 23,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FIFOCNT": {
+ "description": "Bits 23:0 = FIFOCOUNT: Remaining number of\n words to be written to or read from the\n FIFO",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "FIF0COUNT": {
+ "description": "FIF0COUNT",
+ "offset": 0,
+ "size": 24
+ }
+ }
+ }
+ },
+ "FIFO": {
+ "description": "bits 31:0 = FIFOData: Receive and transmit\n FIFO data",
+ "offset": 128,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FIFOData": {
+ "description": "FIFOData",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "RTC": {
+ "description": "Real time clock",
+ "children": {
+ "registers": {
+ "CRH": {
+ "description": "RTC Control Register High",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SECIE": {
+ "description": "Second interrupt Enable",
+ "offset": 0,
+ "size": 1
+ },
+ "ALRIE": {
+ "description": "Alarm interrupt Enable",
+ "offset": 1,
+ "size": 1
+ },
+ "OWIE": {
+ "description": "Overflow interrupt Enable",
+ "offset": 2,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CRL": {
+ "description": "RTC Control Register Low",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 32,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SECF": {
+ "description": "Second Flag",
+ "offset": 0,
+ "size": 1
+ },
+ "ALRF": {
+ "description": "Alarm Flag",
+ "offset": 1,
+ "size": 1
+ },
+ "OWF": {
+ "description": "Overflow Flag",
+ "offset": 2,
+ "size": 1
+ },
+ "RSF": {
+ "description": "Registers Synchronized\n Flag",
+ "offset": 3,
+ "size": 1
+ },
+ "CNF": {
+ "description": "Configuration Flag",
+ "offset": 4,
+ "size": 1
+ },
+ "RTOFF": {
+ "description": "RTC operation OFF",
+ "offset": 5,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "PRLH": {
+ "description": "RTC Prescaler Load Register\n High",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "PRLH": {
+ "description": "RTC Prescaler Load Register\n High",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "PRLL": {
+ "description": "RTC Prescaler Load Register\n Low",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 32768,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "PRLL": {
+ "description": "RTC Prescaler Divider Register\n Low",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DIVH": {
+ "description": "RTC Prescaler Divider Register\n High",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DIVH": {
+ "description": "RTC prescaler divider register\n high",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "DIVL": {
+ "description": "RTC Prescaler Divider Register\n Low",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 32768,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DIVL": {
+ "description": "RTC prescaler divider register\n Low",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CNTH": {
+ "description": "RTC Counter Register High",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNTH": {
+ "description": "RTC counter register high",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CNTL": {
+ "description": "RTC Counter Register Low",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNTL": {
+ "description": "RTC counter register Low",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ALRH": {
+ "description": "RTC Alarm Register High",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 65535,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "ALRH": {
+ "description": "RTC alarm register high",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ALRL": {
+ "description": "RTC Alarm Register Low",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 65535,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "ALRL": {
+ "description": "RTC alarm register low",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "BKP": {
+ "description": "Backup registers",
+ "children": {
+ "registers": {
+ "DR1": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D1": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR2": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D2": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR3": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D3": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR4": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D4": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR5": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D5": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR6": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D6": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR7": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D7": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR8": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D8": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR9": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D9": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR10": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D10": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR11": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DR11": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR12": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DR12": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR13": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DR13": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR14": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D14": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR15": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D15": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR16": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D16": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR17": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 84,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D17": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR18": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 88,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D18": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR19": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 92,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D19": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR20": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 96,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D20": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR21": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 100,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D21": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR22": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 104,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D22": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR23": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 108,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D23": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR24": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 112,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D24": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR25": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 116,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D25": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR26": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 120,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D26": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR27": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 124,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D27": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR28": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 128,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D28": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR29": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 132,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D29": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR30": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 136,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D30": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR31": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 140,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D31": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR32": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 144,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D32": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR33": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 148,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D33": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR34": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 152,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D34": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR35": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 156,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D35": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR36": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 160,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D36": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR37": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 164,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D37": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR38": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 168,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D38": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR39": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 172,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D39": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR40": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 176,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D40": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR41": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 180,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D41": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR42": {
+ "description": "Backup data register (BKP_DR)",
+ "offset": 184,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "D42": {
+ "description": "Backup data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "RTCCR": {
+ "description": "RTC clock calibration register\n (BKP_RTCCR)",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CAL": {
+ "description": "Calibration value",
+ "offset": 0,
+ "size": 7
+ },
+ "CCO": {
+ "description": "Calibration Clock Output",
+ "offset": 7,
+ "size": 1
+ },
+ "ASOE": {
+ "description": "Alarm or second output\n enable",
+ "offset": 8,
+ "size": 1
+ },
+ "ASOS": {
+ "description": "Alarm or second output\n selection",
+ "offset": 9,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR": {
+ "description": "Backup control register\n (BKP_CR)",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TPE": {
+ "description": "Tamper pin enable",
+ "offset": 0,
+ "size": 1
+ },
+ "TPAL": {
+ "description": "Tamper pin active level",
+ "offset": 1,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CSR": {
+ "description": "BKP_CSR control/status register\n (BKP_CSR)",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CTE": {
+ "description": "Clear Tamper event",
+ "offset": 0,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CTI": {
+ "description": "Clear Tamper Interrupt",
+ "offset": 1,
+ "size": 1,
+ "access": "write-only"
+ },
+ "TPIE": {
+ "description": "Tamper Pin interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TEF": {
+ "description": "Tamper Event Flag",
+ "offset": 8,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TIF": {
+ "description": "Tamper Interrupt Flag",
+ "offset": 9,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "IWDG": {
+ "description": "Independent watchdog",
+ "children": {
+ "registers": {
+ "KR": {
+ "description": "Key register (IWDG_KR)",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "KEY": {
+ "description": "Key value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "PR": {
+ "description": "Prescaler register (IWDG_PR)",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PR": {
+ "description": "Prescaler divider",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "RLR": {
+ "description": "Reload register (IWDG_RLR)",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 4095,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RL": {
+ "description": "Watchdog counter reload\n value",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "Status register (IWDG_SR)",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "PVU": {
+ "description": "Watchdog prescaler value\n update",
+ "offset": 0,
+ "size": 1
+ },
+ "RVU": {
+ "description": "Watchdog counter reload value\n update",
+ "offset": 1,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "WWDG": {
+ "description": "Window watchdog",
+ "children": {
+ "registers": {
+ "CR": {
+ "description": "Control register (WWDG_CR)",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 127,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "T": {
+ "description": "7-bit counter (MSB to LSB)",
+ "offset": 0,
+ "size": 7
+ },
+ "WDGA": {
+ "description": "Activation bit",
+ "offset": 7,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CFR": {
+ "description": "Configuration register\n (WWDG_CFR)",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 127,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "W": {
+ "description": "7-bit window value",
+ "offset": 0,
+ "size": 7
+ },
+ "WDGTB": {
+ "description": "Timer Base",
+ "offset": 7,
+ "size": 2
+ },
+ "EWI": {
+ "description": "Early Wakeup Interrupt",
+ "offset": 9,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "Status register (WWDG_SR)",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EWI": {
+ "description": "Early Wakeup Interrupt",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "TIM1": {
+ "description": "Advanced timer",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CKD": {
+ "description": "Clock division",
+ "offset": 8,
+ "size": 2
+ },
+ "ARPE": {
+ "description": "Auto-reload preload enable",
+ "offset": 7,
+ "size": 1
+ },
+ "CMS": {
+ "description": "Center-aligned mode\n selection",
+ "offset": 5,
+ "size": 2
+ },
+ "DIR": {
+ "description": "Direction",
+ "offset": 4,
+ "size": 1
+ },
+ "OPM": {
+ "description": "One-pulse mode",
+ "offset": 3,
+ "size": 1
+ },
+ "URS": {
+ "description": "Update request source",
+ "offset": 2,
+ "size": 1
+ },
+ "UDIS": {
+ "description": "Update disable",
+ "offset": 1,
+ "size": 1
+ },
+ "CEN": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OIS4": {
+ "description": "Output Idle state 4",
+ "offset": 14,
+ "size": 1
+ },
+ "OIS3N": {
+ "description": "Output Idle state 3",
+ "offset": 13,
+ "size": 1
+ },
+ "OIS3": {
+ "description": "Output Idle state 3",
+ "offset": 12,
+ "size": 1
+ },
+ "OIS2N": {
+ "description": "Output Idle state 2",
+ "offset": 11,
+ "size": 1
+ },
+ "OIS2": {
+ "description": "Output Idle state 2",
+ "offset": 10,
+ "size": 1
+ },
+ "OIS1N": {
+ "description": "Output Idle state 1",
+ "offset": 9,
+ "size": 1
+ },
+ "OIS1": {
+ "description": "Output Idle state 1",
+ "offset": 8,
+ "size": 1
+ },
+ "TI1S": {
+ "description": "TI1 selection",
+ "offset": 7,
+ "size": 1
+ },
+ "MMS": {
+ "description": "Master mode selection",
+ "offset": 4,
+ "size": 3
+ },
+ "CCDS": {
+ "description": "Capture/compare DMA\n selection",
+ "offset": 3,
+ "size": 1
+ },
+ "CCUS": {
+ "description": "Capture/compare control update\n selection",
+ "offset": 2,
+ "size": 1
+ },
+ "CCPC": {
+ "description": "Capture/compare preloaded\n control",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SMCR": {
+ "description": "slave mode control register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ETP": {
+ "description": "External trigger polarity",
+ "offset": 15,
+ "size": 1
+ },
+ "ECE": {
+ "description": "External clock enable",
+ "offset": 14,
+ "size": 1
+ },
+ "ETPS": {
+ "description": "External trigger prescaler",
+ "offset": 12,
+ "size": 2
+ },
+ "ETF": {
+ "description": "External trigger filter",
+ "offset": 8,
+ "size": 4
+ },
+ "MSM": {
+ "description": "Master/Slave mode",
+ "offset": 7,
+ "size": 1
+ },
+ "TS": {
+ "description": "Trigger selection",
+ "offset": 4,
+ "size": 3
+ },
+ "SMS": {
+ "description": "Slave mode selection",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "DIER": {
+ "description": "DMA/Interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TDE": {
+ "description": "Trigger DMA request enable",
+ "offset": 14,
+ "size": 1
+ },
+ "COMDE": {
+ "description": "COM DMA request enable",
+ "offset": 13,
+ "size": 1
+ },
+ "CC4DE": {
+ "description": "Capture/Compare 4 DMA request\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3DE": {
+ "description": "Capture/Compare 3 DMA request\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "CC2DE": {
+ "description": "Capture/Compare 2 DMA request\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC1DE": {
+ "description": "Capture/Compare 1 DMA request\n enable",
+ "offset": 9,
+ "size": 1
+ },
+ "UDE": {
+ "description": "Update DMA request enable",
+ "offset": 8,
+ "size": 1
+ },
+ "TIE": {
+ "description": "Trigger interrupt enable",
+ "offset": 6,
+ "size": 1
+ },
+ "CC4IE": {
+ "description": "Capture/Compare 4 interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3IE": {
+ "description": "Capture/Compare 3 interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2IE": {
+ "description": "Capture/Compare 2 interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IE": {
+ "description": "Capture/Compare 1 interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "UIE": {
+ "description": "Update interrupt enable",
+ "offset": 0,
+ "size": 1
+ },
+ "BIE": {
+ "description": "Break interrupt enable",
+ "offset": 7,
+ "size": 1
+ },
+ "COMIE": {
+ "description": "COM interrupt enable",
+ "offset": 5,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC4OF": {
+ "description": "Capture/Compare 4 overcapture\n flag",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3OF": {
+ "description": "Capture/Compare 3 overcapture\n flag",
+ "offset": 11,
+ "size": 1
+ },
+ "CC2OF": {
+ "description": "Capture/compare 2 overcapture\n flag",
+ "offset": 10,
+ "size": 1
+ },
+ "CC1OF": {
+ "description": "Capture/Compare 1 overcapture\n flag",
+ "offset": 9,
+ "size": 1
+ },
+ "BIF": {
+ "description": "Break interrupt flag",
+ "offset": 7,
+ "size": 1
+ },
+ "TIF": {
+ "description": "Trigger interrupt flag",
+ "offset": 6,
+ "size": 1
+ },
+ "COMIF": {
+ "description": "COM interrupt flag",
+ "offset": 5,
+ "size": 1
+ },
+ "CC4IF": {
+ "description": "Capture/Compare 4 interrupt\n flag",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3IF": {
+ "description": "Capture/Compare 3 interrupt\n flag",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2IF": {
+ "description": "Capture/Compare 2 interrupt\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IF": {
+ "description": "Capture/compare 1 interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "UIF": {
+ "description": "Update interrupt flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EGR": {
+ "description": "event generation register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "BG": {
+ "description": "Break generation",
+ "offset": 7,
+ "size": 1
+ },
+ "TG": {
+ "description": "Trigger generation",
+ "offset": 6,
+ "size": 1
+ },
+ "COMG": {
+ "description": "Capture/Compare control update\n generation",
+ "offset": 5,
+ "size": 1
+ },
+ "CC4G": {
+ "description": "Capture/compare 4\n generation",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3G": {
+ "description": "Capture/compare 3\n generation",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2G": {
+ "description": "Capture/compare 2\n generation",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1G": {
+ "description": "Capture/compare 1\n generation",
+ "offset": 1,
+ "size": 1
+ },
+ "UG": {
+ "description": "Update generation",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Output": {
+ "description": "capture/compare mode register (output\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OC2CE": {
+ "description": "Output Compare 2 clear\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "OC2M": {
+ "description": "Output Compare 2 mode",
+ "offset": 12,
+ "size": 3
+ },
+ "OC2PE": {
+ "description": "Output Compare 2 preload\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "OC2FE": {
+ "description": "Output Compare 2 fast\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC2S": {
+ "description": "Capture/Compare 2\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "OC1CE": {
+ "description": "Output Compare 1 clear\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "OC1M": {
+ "description": "Output Compare 1 mode",
+ "offset": 4,
+ "size": 3
+ },
+ "OC1PE": {
+ "description": "Output Compare 1 preload\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "OC1FE": {
+ "description": "Output Compare 1 fast\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR1_Input": {
+ "description": "capture/compare mode register 1 (input\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC2F": {
+ "description": "Input capture 2 filter",
+ "offset": 12,
+ "size": 4
+ },
+ "IC2PCS": {
+ "description": "Input capture 2 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC2S": {
+ "description": "Capture/Compare 2\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC1F": {
+ "description": "Input capture 1 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "ICPCS": {
+ "description": "Input capture 1 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR2_Output": {
+ "description": "capture/compare mode register (output\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OC4CE": {
+ "description": "Output compare 4 clear\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "OC4M": {
+ "description": "Output compare 4 mode",
+ "offset": 12,
+ "size": 3
+ },
+ "OC4PE": {
+ "description": "Output compare 4 preload\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "OC4FE": {
+ "description": "Output compare 4 fast\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC4S": {
+ "description": "Capture/Compare 4\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "OC3CE": {
+ "description": "Output compare 3 clear\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "OC3M": {
+ "description": "Output compare 3 mode",
+ "offset": 4,
+ "size": 3
+ },
+ "OC3PE": {
+ "description": "Output compare 3 preload\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "OC3FE": {
+ "description": "Output compare 3 fast\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC3S": {
+ "description": "Capture/Compare 3\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR2_Input": {
+ "description": "capture/compare mode register 2 (input\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC4F": {
+ "description": "Input capture 4 filter",
+ "offset": 12,
+ "size": 4
+ },
+ "IC4PSC": {
+ "description": "Input capture 4 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC4S": {
+ "description": "Capture/Compare 4\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC3F": {
+ "description": "Input capture 3 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "IC3PSC": {
+ "description": "Input capture 3 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC3S": {
+ "description": "Capture/compare 3\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCER": {
+ "description": "capture/compare enable\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC4P": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 13,
+ "size": 1
+ },
+ "CC4E": {
+ "description": "Capture/Compare 4 output\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3NP": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 11,
+ "size": 1
+ },
+ "CC3NE": {
+ "description": "Capture/Compare 3 complementary output\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC3P": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 9,
+ "size": 1
+ },
+ "CC3E": {
+ "description": "Capture/Compare 3 output\n enable",
+ "offset": 8,
+ "size": 1
+ },
+ "CC2NP": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 7,
+ "size": 1
+ },
+ "CC2NE": {
+ "description": "Capture/Compare 2 complementary output\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "CC2P": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 5,
+ "size": 1
+ },
+ "CC2E": {
+ "description": "Capture/Compare 2 output\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC1NP": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 3,
+ "size": 1
+ },
+ "CC1NE": {
+ "description": "Capture/Compare 1 complementary output\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1P": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 1,
+ "size": 1
+ },
+ "CC1E": {
+ "description": "Capture/Compare 1 output\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNT": {
+ "description": "counter",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNT": {
+ "description": "counter value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "PSC": {
+ "description": "prescaler",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ARR": {
+ "description": "auto-reload register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARR": {
+ "description": "Auto-reload value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR1": {
+ "description": "capture/compare register 1",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR1": {
+ "description": "Capture/Compare 1 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR2": {
+ "description": "capture/compare register 2",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR2": {
+ "description": "Capture/Compare 2 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR3": {
+ "description": "capture/compare register 3",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR3": {
+ "description": "Capture/Compare value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR4": {
+ "description": "capture/compare register 4",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR4": {
+ "description": "Capture/Compare value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DCR": {
+ "description": "DMA control register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBL": {
+ "description": "DMA burst length",
+ "offset": 8,
+ "size": 5
+ },
+ "DBA": {
+ "description": "DMA base address",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "DMAR": {
+ "description": "DMA address for full transfer",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAB": {
+ "description": "DMA register for burst\n accesses",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "RCR": {
+ "description": "repetition counter register",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "REP": {
+ "description": "Repetition counter value",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "BDTR": {
+ "description": "break and dead-time register",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MOE": {
+ "description": "Main output enable",
+ "offset": 15,
+ "size": 1
+ },
+ "AOE": {
+ "description": "Automatic output enable",
+ "offset": 14,
+ "size": 1
+ },
+ "BKP": {
+ "description": "Break polarity",
+ "offset": 13,
+ "size": 1
+ },
+ "BKE": {
+ "description": "Break enable",
+ "offset": 12,
+ "size": 1
+ },
+ "OSSR": {
+ "description": "Off-state selection for Run\n mode",
+ "offset": 11,
+ "size": 1
+ },
+ "OSSI": {
+ "description": "Off-state selection for Idle\n mode",
+ "offset": 10,
+ "size": 1
+ },
+ "LOCK": {
+ "description": "Lock configuration",
+ "offset": 8,
+ "size": 2
+ },
+ "DTG": {
+ "description": "Dead-time generator setup",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "ETHERNET_PTP": {
+ "description": "Ethernet: Precision time protocol",
+ "children": {
+ "registers": {
+ "PTPTSCR": {
+ "description": "Ethernet PTP time stamp control register\n (ETH_PTPTSCR)",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TSE": {
+ "description": "Time stamp enable",
+ "offset": 0,
+ "size": 1
+ },
+ "TSFCU": {
+ "description": "Time stamp fine or coarse\n update",
+ "offset": 1,
+ "size": 1
+ },
+ "TSSTI": {
+ "description": "Time stamp system time\n initialize",
+ "offset": 2,
+ "size": 1
+ },
+ "TSSTU": {
+ "description": "Time stamp system time\n update",
+ "offset": 3,
+ "size": 1
+ },
+ "TSITE": {
+ "description": "Time stamp interrupt trigger\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "TSARU": {
+ "description": "Time stamp addend register\n update",
+ "offset": 5,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PTPSSIR": {
+ "description": "Ethernet PTP subsecond increment\n register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "STSSI": {
+ "description": "System time subsecond\n increment",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "PTPTSHR": {
+ "description": "Ethernet PTP time stamp high\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "STS": {
+ "description": "System time second",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "PTPTSLR": {
+ "description": "Ethernet PTP time stamp low register\n (ETH_PTPTSLR)",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "STSS": {
+ "description": "System time subseconds",
+ "offset": 0,
+ "size": 31
+ },
+ "STPNS": {
+ "description": "System time positive or negative\n sign",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PTPTSHUR": {
+ "description": "Ethernet PTP time stamp high update\n register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TSUS": {
+ "description": "Time stamp update second",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "PTPTSLUR": {
+ "description": "Ethernet PTP time stamp low update register\n (ETH_PTPTSLUR)",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TSUSS": {
+ "description": "Time stamp update\n subseconds",
+ "offset": 0,
+ "size": 31
+ },
+ "TSUPNS": {
+ "description": "Time stamp update positive or negative\n sign",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PTPTSAR": {
+ "description": "Ethernet PTP time stamp addend\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TSA": {
+ "description": "Time stamp addend",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "PTPTTHR": {
+ "description": "Ethernet PTP target time high\n register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TTSH": {
+ "description": "Target time stamp high",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "PTPTTLR": {
+ "description": "Ethernet PTP target time low\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TTSL": {
+ "description": "Target time stamp low",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "TIM2": {
+ "description": "General purpose timer",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CKD": {
+ "description": "Clock division",
+ "offset": 8,
+ "size": 2
+ },
+ "ARPE": {
+ "description": "Auto-reload preload enable",
+ "offset": 7,
+ "size": 1
+ },
+ "CMS": {
+ "description": "Center-aligned mode\n selection",
+ "offset": 5,
+ "size": 2
+ },
+ "DIR": {
+ "description": "Direction",
+ "offset": 4,
+ "size": 1
+ },
+ "OPM": {
+ "description": "One-pulse mode",
+ "offset": 3,
+ "size": 1
+ },
+ "URS": {
+ "description": "Update request source",
+ "offset": 2,
+ "size": 1
+ },
+ "UDIS": {
+ "description": "Update disable",
+ "offset": 1,
+ "size": 1
+ },
+ "CEN": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TI1S": {
+ "description": "TI1 selection",
+ "offset": 7,
+ "size": 1
+ },
+ "MMS": {
+ "description": "Master mode selection",
+ "offset": 4,
+ "size": 3
+ },
+ "CCDS": {
+ "description": "Capture/compare DMA\n selection",
+ "offset": 3,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SMCR": {
+ "description": "slave mode control register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ETP": {
+ "description": "External trigger polarity",
+ "offset": 15,
+ "size": 1
+ },
+ "ECE": {
+ "description": "External clock enable",
+ "offset": 14,
+ "size": 1
+ },
+ "ETPS": {
+ "description": "External trigger prescaler",
+ "offset": 12,
+ "size": 2
+ },
+ "ETF": {
+ "description": "External trigger filter",
+ "offset": 8,
+ "size": 4
+ },
+ "MSM": {
+ "description": "Master/Slave mode",
+ "offset": 7,
+ "size": 1
+ },
+ "TS": {
+ "description": "Trigger selection",
+ "offset": 4,
+ "size": 3
+ },
+ "SMS": {
+ "description": "Slave mode selection",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "DIER": {
+ "description": "DMA/Interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TDE": {
+ "description": "Trigger DMA request enable",
+ "offset": 14,
+ "size": 1
+ },
+ "CC4DE": {
+ "description": "Capture/Compare 4 DMA request\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3DE": {
+ "description": "Capture/Compare 3 DMA request\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "CC2DE": {
+ "description": "Capture/Compare 2 DMA request\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC1DE": {
+ "description": "Capture/Compare 1 DMA request\n enable",
+ "offset": 9,
+ "size": 1
+ },
+ "UDE": {
+ "description": "Update DMA request enable",
+ "offset": 8,
+ "size": 1
+ },
+ "TIE": {
+ "description": "Trigger interrupt enable",
+ "offset": 6,
+ "size": 1
+ },
+ "CC4IE": {
+ "description": "Capture/Compare 4 interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3IE": {
+ "description": "Capture/Compare 3 interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2IE": {
+ "description": "Capture/Compare 2 interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IE": {
+ "description": "Capture/Compare 1 interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "UIE": {
+ "description": "Update interrupt enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC4OF": {
+ "description": "Capture/Compare 4 overcapture\n flag",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3OF": {
+ "description": "Capture/Compare 3 overcapture\n flag",
+ "offset": 11,
+ "size": 1
+ },
+ "CC2OF": {
+ "description": "Capture/compare 2 overcapture\n flag",
+ "offset": 10,
+ "size": 1
+ },
+ "CC1OF": {
+ "description": "Capture/Compare 1 overcapture\n flag",
+ "offset": 9,
+ "size": 1
+ },
+ "TIF": {
+ "description": "Trigger interrupt flag",
+ "offset": 6,
+ "size": 1
+ },
+ "CC4IF": {
+ "description": "Capture/Compare 4 interrupt\n flag",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3IF": {
+ "description": "Capture/Compare 3 interrupt\n flag",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2IF": {
+ "description": "Capture/Compare 2 interrupt\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IF": {
+ "description": "Capture/compare 1 interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "UIF": {
+ "description": "Update interrupt flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EGR": {
+ "description": "event generation register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "TG": {
+ "description": "Trigger generation",
+ "offset": 6,
+ "size": 1
+ },
+ "CC4G": {
+ "description": "Capture/compare 4\n generation",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3G": {
+ "description": "Capture/compare 3\n generation",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2G": {
+ "description": "Capture/compare 2\n generation",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1G": {
+ "description": "Capture/compare 1\n generation",
+ "offset": 1,
+ "size": 1
+ },
+ "UG": {
+ "description": "Update generation",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Output": {
+ "description": "capture/compare mode register 1 (output\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OC2CE": {
+ "description": "Output compare 2 clear\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "OC2M": {
+ "description": "Output compare 2 mode",
+ "offset": 12,
+ "size": 3
+ },
+ "OC2PE": {
+ "description": "Output compare 2 preload\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "OC2FE": {
+ "description": "Output compare 2 fast\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC2S": {
+ "description": "Capture/Compare 2\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "OC1CE": {
+ "description": "Output compare 1 clear\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "OC1M": {
+ "description": "Output compare 1 mode",
+ "offset": 4,
+ "size": 3
+ },
+ "OC1PE": {
+ "description": "Output compare 1 preload\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "OC1FE": {
+ "description": "Output compare 1 fast\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR1_Input": {
+ "description": "capture/compare mode register 1 (input\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC2F": {
+ "description": "Input capture 2 filter",
+ "offset": 12,
+ "size": 4
+ },
+ "IC2PSC": {
+ "description": "Input capture 2 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC2S": {
+ "description": "Capture/compare 2\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC1F": {
+ "description": "Input capture 1 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "IC1PSC": {
+ "description": "Input capture 1 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR2_Output": {
+ "description": "capture/compare mode register 2 (output\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "O24CE": {
+ "description": "Output compare 4 clear\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "OC4M": {
+ "description": "Output compare 4 mode",
+ "offset": 12,
+ "size": 3
+ },
+ "OC4PE": {
+ "description": "Output compare 4 preload\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "OC4FE": {
+ "description": "Output compare 4 fast\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC4S": {
+ "description": "Capture/Compare 4\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "OC3CE": {
+ "description": "Output compare 3 clear\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "OC3M": {
+ "description": "Output compare 3 mode",
+ "offset": 4,
+ "size": 3
+ },
+ "OC3PE": {
+ "description": "Output compare 3 preload\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "OC3FE": {
+ "description": "Output compare 3 fast\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC3S": {
+ "description": "Capture/Compare 3\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR2_Input": {
+ "description": "capture/compare mode register 2 (input\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC4F": {
+ "description": "Input capture 4 filter",
+ "offset": 12,
+ "size": 4
+ },
+ "IC4PSC": {
+ "description": "Input capture 4 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC4S": {
+ "description": "Capture/Compare 4\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC3F": {
+ "description": "Input capture 3 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "IC3PSC": {
+ "description": "Input capture 3 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC3S": {
+ "description": "Capture/Compare 3\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCER": {
+ "description": "capture/compare enable\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC4P": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 13,
+ "size": 1
+ },
+ "CC4E": {
+ "description": "Capture/Compare 4 output\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3P": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 9,
+ "size": 1
+ },
+ "CC3E": {
+ "description": "Capture/Compare 3 output\n enable",
+ "offset": 8,
+ "size": 1
+ },
+ "CC2P": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 5,
+ "size": 1
+ },
+ "CC2E": {
+ "description": "Capture/Compare 2 output\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC1P": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 1,
+ "size": 1
+ },
+ "CC1E": {
+ "description": "Capture/Compare 1 output\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNT": {
+ "description": "counter",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNT": {
+ "description": "counter value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "PSC": {
+ "description": "prescaler",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ARR": {
+ "description": "auto-reload register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARR": {
+ "description": "Auto-reload value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR1": {
+ "description": "capture/compare register 1",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR1": {
+ "description": "Capture/Compare 1 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR2": {
+ "description": "capture/compare register 2",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR2": {
+ "description": "Capture/Compare 2 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR3": {
+ "description": "capture/compare register 3",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR3": {
+ "description": "Capture/Compare value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR4": {
+ "description": "capture/compare register 4",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR4": {
+ "description": "Capture/Compare value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DCR": {
+ "description": "DMA control register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBL": {
+ "description": "DMA burst length",
+ "offset": 8,
+ "size": 5
+ },
+ "DBA": {
+ "description": "DMA base address",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "DMAR": {
+ "description": "DMA address for full transfer",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAB": {
+ "description": "DMA register for burst\n accesses",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "ETHERNET_MAC": {
+ "description": "Ethernet: media access control",
+ "children": {
+ "registers": {
+ "MACCR": {
+ "description": "Ethernet MAC configuration register\n (ETH_MACCR)",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 32768,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RE": {
+ "description": "Receiver enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TE": {
+ "description": "Transmitter enable",
+ "offset": 3,
+ "size": 1
+ },
+ "DC": {
+ "description": "Deferral check",
+ "offset": 4,
+ "size": 1
+ },
+ "BL": {
+ "description": "Back-off limit",
+ "offset": 5,
+ "size": 2
+ },
+ "APCS": {
+ "description": "Automatic pad/CRC\n stripping",
+ "offset": 7,
+ "size": 1
+ },
+ "RD": {
+ "description": "Retry disable",
+ "offset": 9,
+ "size": 1
+ },
+ "IPCO": {
+ "description": "IPv4 checksum offload",
+ "offset": 10,
+ "size": 1
+ },
+ "DM": {
+ "description": "Duplex mode",
+ "offset": 11,
+ "size": 1
+ },
+ "LM": {
+ "description": "Loopback mode",
+ "offset": 12,
+ "size": 1
+ },
+ "ROD": {
+ "description": "Receive own disable",
+ "offset": 13,
+ "size": 1
+ },
+ "FES": {
+ "description": "Fast Ethernet speed",
+ "offset": 14,
+ "size": 1
+ },
+ "CSD": {
+ "description": "Carrier sense disable",
+ "offset": 16,
+ "size": 1
+ },
+ "IFG": {
+ "description": "Interframe gap",
+ "offset": 17,
+ "size": 3
+ },
+ "JD": {
+ "description": "Jabber disable",
+ "offset": 22,
+ "size": 1
+ },
+ "WD": {
+ "description": "Watchdog disable",
+ "offset": 23,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MACFFR": {
+ "description": "Ethernet MAC frame filter register\n (ETH_MACCFFR)",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PM": {
+ "description": "Promiscuous mode",
+ "offset": 0,
+ "size": 1
+ },
+ "HU": {
+ "description": "Hash unicast",
+ "offset": 1,
+ "size": 1
+ },
+ "HM": {
+ "description": "Hash multicast",
+ "offset": 2,
+ "size": 1
+ },
+ "DAIF": {
+ "description": "Destination address inverse\n filtering",
+ "offset": 3,
+ "size": 1
+ },
+ "PAM": {
+ "description": "Pass all multicast",
+ "offset": 4,
+ "size": 1
+ },
+ "BFD": {
+ "description": "Broadcast frames disable",
+ "offset": 5,
+ "size": 1
+ },
+ "PCF": {
+ "description": "Pass control frames",
+ "offset": 6,
+ "size": 2
+ },
+ "SAIF": {
+ "description": "Source address inverse\n filtering",
+ "offset": 8,
+ "size": 1
+ },
+ "SAF": {
+ "description": "Source address filter",
+ "offset": 9,
+ "size": 1
+ },
+ "HPF": {
+ "description": "Hash or perfect filter",
+ "offset": 10,
+ "size": 1
+ },
+ "RA": {
+ "description": "Receive all",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MACHTHR": {
+ "description": "Ethernet MAC hash table high\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "HTH": {
+ "description": "Hash table high",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "MACHTLR": {
+ "description": "Ethernet MAC hash table low\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "HTL": {
+ "description": "Hash table low",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "MACMIIAR": {
+ "description": "Ethernet MAC MII address register\n (ETH_MACMIIAR)",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MB": {
+ "description": "MII busy",
+ "offset": 0,
+ "size": 1
+ },
+ "MW": {
+ "description": "MII write",
+ "offset": 1,
+ "size": 1
+ },
+ "CR": {
+ "description": "Clock range",
+ "offset": 2,
+ "size": 3
+ },
+ "MR": {
+ "description": "MII register",
+ "offset": 6,
+ "size": 5
+ },
+ "PA": {
+ "description": "PHY address",
+ "offset": 11,
+ "size": 5
+ }
+ }
+ }
+ },
+ "MACMIIDR": {
+ "description": "Ethernet MAC MII data register\n (ETH_MACMIIDR)",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MD": {
+ "description": "MII data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "MACFCR": {
+ "description": "Ethernet MAC flow control register\n (ETH_MACFCR)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FCB_BPA": {
+ "description": "Flow control busy/back pressure\n activate",
+ "offset": 0,
+ "size": 1
+ },
+ "TFCE": {
+ "description": "Transmit flow control\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "RFCE": {
+ "description": "Receive flow control\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "UPFD": {
+ "description": "Unicast pause frame detect",
+ "offset": 3,
+ "size": 1
+ },
+ "PLT": {
+ "description": "Pause low threshold",
+ "offset": 4,
+ "size": 2
+ },
+ "ZQPD": {
+ "description": "Zero-quanta pause disable",
+ "offset": 7,
+ "size": 1
+ },
+ "PT": {
+ "description": "Pass control frames",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "MACVLANTR": {
+ "description": "Ethernet MAC VLAN tag register\n (ETH_MACVLANTR)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "VLANTI": {
+ "description": "VLAN tag identifier (for receive\n frames)",
+ "offset": 0,
+ "size": 16
+ },
+ "VLANTC": {
+ "description": "12-bit VLAN tag comparison",
+ "offset": 16,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MACRWUFFR": {
+ "description": "Ethernet MAC remote wakeup frame filter\n register (ETH_MACRWUFFR)",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295
+ },
+ "MACPMTCSR": {
+ "description": "Ethernet MAC PMT control and status register\n (ETH_MACPMTCSR)",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PD": {
+ "description": "Power down",
+ "offset": 0,
+ "size": 1
+ },
+ "MPE": {
+ "description": "Magic Packet enable",
+ "offset": 1,
+ "size": 1
+ },
+ "WFE": {
+ "description": "Wakeup frame enable",
+ "offset": 2,
+ "size": 1
+ },
+ "MPR": {
+ "description": "Magic packet received",
+ "offset": 5,
+ "size": 1
+ },
+ "WFR": {
+ "description": "Wakeup frame received",
+ "offset": 6,
+ "size": 1
+ },
+ "GU": {
+ "description": "Global unicast",
+ "offset": 9,
+ "size": 1
+ },
+ "WFFRPR": {
+ "description": "Wakeup frame filter register pointer\n reset",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MACSR": {
+ "description": "Ethernet MAC interrupt status register\n (ETH_MACSR)",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PMTS": {
+ "description": "PMT status",
+ "offset": 3,
+ "size": 1
+ },
+ "MMCS": {
+ "description": "MMC status",
+ "offset": 4,
+ "size": 1
+ },
+ "MMCRS": {
+ "description": "MMC receive status",
+ "offset": 5,
+ "size": 1
+ },
+ "MMCTS": {
+ "description": "MMC transmit status",
+ "offset": 6,
+ "size": 1
+ },
+ "TSTS": {
+ "description": "Time stamp trigger status",
+ "offset": 9,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MACIMR": {
+ "description": "Ethernet MAC interrupt mask register\n (ETH_MACIMR)",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PMTIM": {
+ "description": "PMT interrupt mask",
+ "offset": 3,
+ "size": 1
+ },
+ "TSTIM": {
+ "description": "Time stamp trigger interrupt\n mask",
+ "offset": 9,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MACA0HR": {
+ "description": "Ethernet MAC address 0 high register\n (ETH_MACA0HR)",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 1114111,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MACA0H": {
+ "description": "MAC address0 high",
+ "offset": 0,
+ "size": 16
+ },
+ "MO": {
+ "description": "Always 1",
+ "offset": 31,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "MACA0LR": {
+ "description": "Ethernet MAC address 0 low\n register",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MACA0L": {
+ "description": "MAC address0 low",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "MACA1HR": {
+ "description": "Ethernet MAC address 1 high register\n (ETH_MACA1HR)",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 65535,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MACA1H": {
+ "description": "MAC address1 high",
+ "offset": 0,
+ "size": 16
+ },
+ "MBC": {
+ "description": "Mask byte control",
+ "offset": 24,
+ "size": 6
+ },
+ "SA": {
+ "description": "Source address",
+ "offset": 30,
+ "size": 1
+ },
+ "AE": {
+ "description": "Address enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MACA1LR": {
+ "description": "Ethernet MAC address1 low\n register",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MACA1L": {
+ "description": "MAC address1 low",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "MACA2HR": {
+ "description": "Ethernet MAC address 2 high register\n (ETH_MACA2HR)",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 80,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ETH_MACA2HR": {
+ "description": "Ethernet MAC address 2 high\n register",
+ "offset": 0,
+ "size": 16
+ },
+ "MBC": {
+ "description": "Mask byte control",
+ "offset": 24,
+ "size": 6
+ },
+ "SA": {
+ "description": "Source address",
+ "offset": 30,
+ "size": 1
+ },
+ "AE": {
+ "description": "Address enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MACA2LR": {
+ "description": "Ethernet MAC address 2 low\n register",
+ "offset": 84,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MACA2L": {
+ "description": "MAC address2 low",
+ "offset": 0,
+ "size": 31
+ }
+ }
+ }
+ },
+ "MACA3HR": {
+ "description": "Ethernet MAC address 3 high register\n (ETH_MACA3HR)",
+ "offset": 88,
+ "size": 32,
+ "reset_value": 65535,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MACA3H": {
+ "description": "MAC address3 high",
+ "offset": 0,
+ "size": 16
+ },
+ "MBC": {
+ "description": "Mask byte control",
+ "offset": 24,
+ "size": 6
+ },
+ "SA": {
+ "description": "Source address",
+ "offset": 30,
+ "size": 1
+ },
+ "AE": {
+ "description": "Address enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MACA3LR": {
+ "description": "Ethernet MAC address 3 low\n register",
+ "offset": 92,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MBCA3L": {
+ "description": "MAC address3 low",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "ETHERNET_MMC": {
+ "description": "Ethernet: MAC management counters",
+ "children": {
+ "registers": {
+ "MMCCR": {
+ "description": "Ethernet MMC control register\n (ETH_MMCCR)",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CR": {
+ "description": "Counter reset",
+ "offset": 0,
+ "size": 1
+ },
+ "CSR": {
+ "description": "Counter stop rollover",
+ "offset": 1,
+ "size": 1
+ },
+ "ROR": {
+ "description": "Reset on read",
+ "offset": 2,
+ "size": 1
+ },
+ "MCF": {
+ "description": "MMC counter freeze",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MMCRIR": {
+ "description": "Ethernet MMC receive interrupt register\n (ETH_MMCRIR)",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RFCES": {
+ "description": "Received frames CRC error\n status",
+ "offset": 5,
+ "size": 1
+ },
+ "RFAES": {
+ "description": "Received frames alignment error\n status",
+ "offset": 6,
+ "size": 1
+ },
+ "RGUFS": {
+ "description": "Received Good Unicast Frames\n Status",
+ "offset": 17,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MMCTIR": {
+ "description": "Ethernet MMC transmit interrupt register\n (ETH_MMCTIR)",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TGFSCS": {
+ "description": "Transmitted good frames single collision\n status",
+ "offset": 14,
+ "size": 1
+ },
+ "TGFMSCS": {
+ "description": "Transmitted good frames more single\n collision status",
+ "offset": 15,
+ "size": 1
+ },
+ "TGFS": {
+ "description": "Transmitted good frames\n status",
+ "offset": 21,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MMCRIMR": {
+ "description": "Ethernet MMC receive interrupt mask register\n (ETH_MMCRIMR)",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RFCEM": {
+ "description": "Received frame CRC error\n mask",
+ "offset": 5,
+ "size": 1
+ },
+ "RFAEM": {
+ "description": "Received frames alignment error\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "RGUFM": {
+ "description": "Received good unicast frames\n mask",
+ "offset": 17,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MMCTIMR": {
+ "description": "Ethernet MMC transmit interrupt mask\n register (ETH_MMCTIMR)",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TGFSCM": {
+ "description": "Transmitted good frames single collision\n mask",
+ "offset": 14,
+ "size": 1
+ },
+ "TGFMSCM": {
+ "description": "Transmitted good frames more single\n collision mask",
+ "offset": 15,
+ "size": 1
+ },
+ "TGFM": {
+ "description": "Transmitted good frames\n mask",
+ "offset": 21,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MMCTGFSCCR": {
+ "description": "Ethernet MMC transmitted good frames after a\n single collision counter",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "TGFSCC": {
+ "description": "Transmitted good frames after a single\n collision counter",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "MMCTGFMSCCR": {
+ "description": "Ethernet MMC transmitted good frames after\n more than a single collision",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "TGFMSCC": {
+ "description": "Transmitted good frames after more than\n a single collision counter",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "MMCTGFCR": {
+ "description": "Ethernet MMC transmitted good frames counter\n register",
+ "offset": 104,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "TGFC": {
+ "description": "Transmitted good frames\n counter",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "MMCRFCECR": {
+ "description": "Ethernet MMC received frames with CRC error\n counter register",
+ "offset": 148,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "RFCFC": {
+ "description": "Received frames with CRC error\n counter",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "MMCRFAECR": {
+ "description": "Ethernet MMC received frames with alignment\n error counter register",
+ "offset": 152,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "RFAEC": {
+ "description": "Received frames with alignment error\n counter",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "MMCRGUFCR": {
+ "description": "MMC received good unicast frames counter\n register",
+ "offset": 196,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "RGUFC": {
+ "description": "Received good unicast frames\n counter",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "OTG_FS_PWRCLK": {
+ "description": "USB on the go full speed",
+ "children": {
+ "registers": {
+ "FS_PCGCCTL": {
+ "description": "OTG_FS power and clock gating control\n register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "STPPCLK": {
+ "description": "Stop PHY clock",
+ "offset": 0,
+ "size": 1
+ },
+ "GATEHCLK": {
+ "description": "Gate HCLK",
+ "offset": 1,
+ "size": 1
+ },
+ "PHYSUSP": {
+ "description": "PHY Suspended",
+ "offset": 4,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "TIM9": {
+ "description": "General purpose timer",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CKD": {
+ "description": "Clock division",
+ "offset": 8,
+ "size": 2
+ },
+ "ARPE": {
+ "description": "Auto-reload preload enable",
+ "offset": 7,
+ "size": 1
+ },
+ "OPM": {
+ "description": "One-pulse mode",
+ "offset": 3,
+ "size": 1
+ },
+ "URS": {
+ "description": "Update request source",
+ "offset": 2,
+ "size": 1
+ },
+ "UDIS": {
+ "description": "Update disable",
+ "offset": 1,
+ "size": 1
+ },
+ "CEN": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MMS": {
+ "description": "Master mode selection",
+ "offset": 4,
+ "size": 3
+ }
+ }
+ }
+ },
+ "SMCR": {
+ "description": "slave mode control register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MSM": {
+ "description": "Master/Slave mode",
+ "offset": 7,
+ "size": 1
+ },
+ "TS": {
+ "description": "Trigger selection",
+ "offset": 4,
+ "size": 3
+ },
+ "SMS": {
+ "description": "Slave mode selection",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "DIER": {
+ "description": "DMA/Interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIE": {
+ "description": "Trigger interrupt enable",
+ "offset": 6,
+ "size": 1
+ },
+ "CC2IE": {
+ "description": "Capture/Compare 2 interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IE": {
+ "description": "Capture/Compare 1 interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "UIE": {
+ "description": "Update interrupt enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC2OF": {
+ "description": "Capture/compare 2 overcapture\n flag",
+ "offset": 10,
+ "size": 1
+ },
+ "CC1OF": {
+ "description": "Capture/Compare 1 overcapture\n flag",
+ "offset": 9,
+ "size": 1
+ },
+ "TIF": {
+ "description": "Trigger interrupt flag",
+ "offset": 6,
+ "size": 1
+ },
+ "CC2IF": {
+ "description": "Capture/Compare 2 interrupt\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IF": {
+ "description": "Capture/compare 1 interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "UIF": {
+ "description": "Update interrupt flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EGR": {
+ "description": "event generation register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "TG": {
+ "description": "Trigger generation",
+ "offset": 6,
+ "size": 1
+ },
+ "CC2G": {
+ "description": "Capture/compare 2\n generation",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1G": {
+ "description": "Capture/compare 1\n generation",
+ "offset": 1,
+ "size": 1
+ },
+ "UG": {
+ "description": "Update generation",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Output": {
+ "description": "capture/compare mode register 1 (output\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OC2M": {
+ "description": "Output Compare 2 mode",
+ "offset": 12,
+ "size": 3
+ },
+ "OC2PE": {
+ "description": "Output Compare 2 preload\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "OC2FE": {
+ "description": "Output Compare 2 fast\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC2S": {
+ "description": "Capture/Compare 2\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "OC1M": {
+ "description": "Output Compare 1 mode",
+ "offset": 4,
+ "size": 3
+ },
+ "OC1PE": {
+ "description": "Output Compare 1 preload\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "OC1FE": {
+ "description": "Output Compare 1 fast\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR1_Input": {
+ "description": "capture/compare mode register 1 (input\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC2F": {
+ "description": "Input capture 2 filter",
+ "offset": 12,
+ "size": 4
+ },
+ "IC2PSC": {
+ "description": "Input capture 2 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC2S": {
+ "description": "Capture/Compare 2\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC1F": {
+ "description": "Input capture 1 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "IC1PSC": {
+ "description": "Input capture 1 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCER": {
+ "description": "capture/compare enable\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC2NP": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 7,
+ "size": 1
+ },
+ "CC2P": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 5,
+ "size": 1
+ },
+ "CC2E": {
+ "description": "Capture/Compare 2 output\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC1NP": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 3,
+ "size": 1
+ },
+ "CC1P": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 1,
+ "size": 1
+ },
+ "CC1E": {
+ "description": "Capture/Compare 1 output\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNT": {
+ "description": "counter",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNT": {
+ "description": "counter value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "PSC": {
+ "description": "prescaler",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ARR": {
+ "description": "auto-reload register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARR": {
+ "description": "Auto-reload value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR1": {
+ "description": "capture/compare register 1",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR1": {
+ "description": "Capture/Compare 1 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR2": {
+ "description": "capture/compare register 2",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR2": {
+ "description": "Capture/Compare 2 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "OTG_FS_HOST": {
+ "description": "USB on the go full speed",
+ "children": {
+ "registers": {
+ "FS_HCFG": {
+ "description": "OTG_FS host configuration register\n (OTG_FS_HCFG)",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FSLSPCS": {
+ "description": "FS/LS PHY clock select",
+ "offset": 0,
+ "size": 2
+ },
+ "FSLSS": {
+ "description": "FS- and LS-only support",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "HFIR": {
+ "description": "OTG_FS Host frame interval\n register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 60000,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FRIVL": {
+ "description": "Frame interval",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_HFNUM": {
+ "description": "OTG_FS host frame number/frame time\n remaining register (OTG_FS_HFNUM)",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 16383,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "FRNUM": {
+ "description": "Frame number",
+ "offset": 0,
+ "size": 16
+ },
+ "FTREM": {
+ "description": "Frame time remaining",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_HPTXSTS": {
+ "description": "OTG_FS_Host periodic transmit FIFO/queue\n status register (OTG_FS_HPTXSTS)",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 524544,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PTXFSAVL": {
+ "description": "Periodic transmit data FIFO space\n available",
+ "offset": 0,
+ "size": 16
+ },
+ "PTXQSAV": {
+ "description": "Periodic transmit request queue space\n available",
+ "offset": 16,
+ "size": 8,
+ "access": "read-only"
+ },
+ "PTXQTOP": {
+ "description": "Top of the periodic transmit request\n queue",
+ "offset": 24,
+ "size": 8,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "HAINT": {
+ "description": "OTG_FS Host all channels interrupt\n register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "HAINT": {
+ "description": "Channel interrupts",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "HAINTMSK": {
+ "description": "OTG_FS host all channels interrupt mask\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "HAINTM": {
+ "description": "Channel interrupt mask",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_HPRT": {
+ "description": "OTG_FS host port control and status register\n (OTG_FS_HPRT)",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PCSTS": {
+ "description": "Port connect status",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PCDET": {
+ "description": "Port connect detected",
+ "offset": 1,
+ "size": 1
+ },
+ "PENA": {
+ "description": "Port enable",
+ "offset": 2,
+ "size": 1
+ },
+ "PENCHNG": {
+ "description": "Port enable/disable change",
+ "offset": 3,
+ "size": 1
+ },
+ "POCA": {
+ "description": "Port overcurrent active",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "POCCHNG": {
+ "description": "Port overcurrent change",
+ "offset": 5,
+ "size": 1
+ },
+ "PRES": {
+ "description": "Port resume",
+ "offset": 6,
+ "size": 1
+ },
+ "PSUSP": {
+ "description": "Port suspend",
+ "offset": 7,
+ "size": 1
+ },
+ "PRST": {
+ "description": "Port reset",
+ "offset": 8,
+ "size": 1
+ },
+ "PLSTS": {
+ "description": "Port line status",
+ "offset": 10,
+ "size": 2,
+ "access": "read-only"
+ },
+ "PPWR": {
+ "description": "Port power",
+ "offset": 12,
+ "size": 1
+ },
+ "PTCTL": {
+ "description": "Port test control",
+ "offset": 13,
+ "size": 4
+ },
+ "PSPD": {
+ "description": "Port speed",
+ "offset": 17,
+ "size": 2,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "FS_HCCHAR0": {
+ "description": "OTG_FS host channel-0 characteristics\n register (OTG_FS_HCCHAR0)",
+ "offset": 256,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MCNT": {
+ "description": "Multicount",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCCHAR1": {
+ "description": "OTG_FS host channel-1 characteristics\n register (OTG_FS_HCCHAR1)",
+ "offset": 288,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MCNT": {
+ "description": "Multicount",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCCHAR2": {
+ "description": "OTG_FS host channel-2 characteristics\n register (OTG_FS_HCCHAR2)",
+ "offset": 320,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MCNT": {
+ "description": "Multicount",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCCHAR3": {
+ "description": "OTG_FS host channel-3 characteristics\n register (OTG_FS_HCCHAR3)",
+ "offset": 352,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MCNT": {
+ "description": "Multicount",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCCHAR4": {
+ "description": "OTG_FS host channel-4 characteristics\n register (OTG_FS_HCCHAR4)",
+ "offset": 384,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MCNT": {
+ "description": "Multicount",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCCHAR5": {
+ "description": "OTG_FS host channel-5 characteristics\n register (OTG_FS_HCCHAR5)",
+ "offset": 416,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MCNT": {
+ "description": "Multicount",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCCHAR6": {
+ "description": "OTG_FS host channel-6 characteristics\n register (OTG_FS_HCCHAR6)",
+ "offset": 448,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MCNT": {
+ "description": "Multicount",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCCHAR7": {
+ "description": "OTG_FS host channel-7 characteristics\n register (OTG_FS_HCCHAR7)",
+ "offset": 480,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MCNT": {
+ "description": "Multicount",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINT0": {
+ "description": "OTG_FS host channel-0 interrupt register\n (OTG_FS_HCINT0)",
+ "offset": 264,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINT1": {
+ "description": "OTG_FS host channel-1 interrupt register\n (OTG_FS_HCINT1)",
+ "offset": 296,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINT2": {
+ "description": "OTG_FS host channel-2 interrupt register\n (OTG_FS_HCINT2)",
+ "offset": 328,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINT3": {
+ "description": "OTG_FS host channel-3 interrupt register\n (OTG_FS_HCINT3)",
+ "offset": 360,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINT4": {
+ "description": "OTG_FS host channel-4 interrupt register\n (OTG_FS_HCINT4)",
+ "offset": 392,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINT5": {
+ "description": "OTG_FS host channel-5 interrupt register\n (OTG_FS_HCINT5)",
+ "offset": 424,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINT6": {
+ "description": "OTG_FS host channel-6 interrupt register\n (OTG_FS_HCINT6)",
+ "offset": 456,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINT7": {
+ "description": "OTG_FS host channel-7 interrupt register\n (OTG_FS_HCINT7)",
+ "offset": 488,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINTMSK0": {
+ "description": "OTG_FS host channel-0 mask register\n (OTG_FS_HCINTMSK0)",
+ "offset": 268,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINTMSK1": {
+ "description": "OTG_FS host channel-1 mask register\n (OTG_FS_HCINTMSK1)",
+ "offset": 300,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINTMSK2": {
+ "description": "OTG_FS host channel-2 mask register\n (OTG_FS_HCINTMSK2)",
+ "offset": 332,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINTMSK3": {
+ "description": "OTG_FS host channel-3 mask register\n (OTG_FS_HCINTMSK3)",
+ "offset": 364,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINTMSK4": {
+ "description": "OTG_FS host channel-4 mask register\n (OTG_FS_HCINTMSK4)",
+ "offset": 396,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINTMSK5": {
+ "description": "OTG_FS host channel-5 mask register\n (OTG_FS_HCINTMSK5)",
+ "offset": 428,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINTMSK6": {
+ "description": "OTG_FS host channel-6 mask register\n (OTG_FS_HCINTMSK6)",
+ "offset": 460,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINTMSK7": {
+ "description": "OTG_FS host channel-7 mask register\n (OTG_FS_HCINTMSK7)",
+ "offset": 492,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCTSIZ0": {
+ "description": "OTG_FS host channel-0 transfer size\n register",
+ "offset": 272,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "FS_HCTSIZ1": {
+ "description": "OTG_FS host channel-1 transfer size\n register",
+ "offset": 304,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "FS_HCTSIZ2": {
+ "description": "OTG_FS host channel-2 transfer size\n register",
+ "offset": 336,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "FS_HCTSIZ3": {
+ "description": "OTG_FS host channel-3 transfer size\n register",
+ "offset": 368,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "FS_HCTSIZ4": {
+ "description": "OTG_FS host channel-x transfer size\n register",
+ "offset": 400,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "FS_HCTSIZ5": {
+ "description": "OTG_FS host channel-5 transfer size\n register",
+ "offset": 432,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "FS_HCTSIZ6": {
+ "description": "OTG_FS host channel-6 transfer size\n register",
+ "offset": 464,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "FS_HCTSIZ7": {
+ "description": "OTG_FS host channel-7 transfer size\n register",
+ "offset": 496,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "TIM10": {
+ "description": "General purpose timer",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CKD": {
+ "description": "Clock division",
+ "offset": 8,
+ "size": 2
+ },
+ "ARPE": {
+ "description": "Auto-reload preload enable",
+ "offset": 7,
+ "size": 1
+ },
+ "URS": {
+ "description": "Update request source",
+ "offset": 2,
+ "size": 1
+ },
+ "UDIS": {
+ "description": "Update disable",
+ "offset": 1,
+ "size": 1
+ },
+ "CEN": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MMS": {
+ "description": "Master mode selection",
+ "offset": 4,
+ "size": 3
+ }
+ }
+ }
+ },
+ "DIER": {
+ "description": "DMA/Interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC1IE": {
+ "description": "Capture/Compare 1 interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "UIE": {
+ "description": "Update interrupt enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC1OF": {
+ "description": "Capture/Compare 1 overcapture\n flag",
+ "offset": 9,
+ "size": 1
+ },
+ "CC1IF": {
+ "description": "Capture/compare 1 interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "UIF": {
+ "description": "Update interrupt flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EGR": {
+ "description": "event generation register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "CC1G": {
+ "description": "Capture/compare 1\n generation",
+ "offset": 1,
+ "size": 1
+ },
+ "UG": {
+ "description": "Update generation",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Output": {
+ "description": "capture/compare mode register (output\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OC1M": {
+ "description": "Output Compare 1 mode",
+ "offset": 4,
+ "size": 3
+ },
+ "OC1PE": {
+ "description": "Output Compare 1 preload\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR1_Input": {
+ "description": "capture/compare mode register (input\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC1F": {
+ "description": "Input capture 1 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "IC1PSC": {
+ "description": "Input capture 1 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCER": {
+ "description": "capture/compare enable\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC1NP": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 3,
+ "size": 1
+ },
+ "CC1P": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 1,
+ "size": 1
+ },
+ "CC1E": {
+ "description": "Capture/Compare 1 output\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNT": {
+ "description": "counter",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNT": {
+ "description": "counter value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "PSC": {
+ "description": "prescaler",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ARR": {
+ "description": "auto-reload register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARR": {
+ "description": "Auto-reload value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR1": {
+ "description": "capture/compare register 1",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR1": {
+ "description": "Capture/Compare 1 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "OTG_FS_GLOBAL": {
+ "description": "USB on the go full speed",
+ "children": {
+ "registers": {
+ "FS_GOTGCTL": {
+ "description": "OTG_FS control and status register\n (OTG_FS_GOTGCTL)",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 2048,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SRQSCS": {
+ "description": "Session request success",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SRQ": {
+ "description": "Session request",
+ "offset": 1,
+ "size": 1
+ },
+ "HNGSCS": {
+ "description": "Host negotiation success",
+ "offset": 8,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HNPRQ": {
+ "description": "HNP request",
+ "offset": 9,
+ "size": 1
+ },
+ "HSHNPEN": {
+ "description": "Host set HNP enable",
+ "offset": 10,
+ "size": 1
+ },
+ "DHNPEN": {
+ "description": "Device HNP enabled",
+ "offset": 11,
+ "size": 1
+ },
+ "CIDSTS": {
+ "description": "Connector ID status",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "DBCT": {
+ "description": "Long/short debounce time",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ASVLD": {
+ "description": "A-session valid",
+ "offset": 18,
+ "size": 1,
+ "access": "read-only"
+ },
+ "BSVLD": {
+ "description": "B-session valid",
+ "offset": 19,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "FS_GOTGINT": {
+ "description": "OTG_FS interrupt register\n (OTG_FS_GOTGINT)",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SEDET": {
+ "description": "Session end detected",
+ "offset": 2,
+ "size": 1
+ },
+ "SRSSCHG": {
+ "description": "Session request success status\n change",
+ "offset": 8,
+ "size": 1
+ },
+ "HNSSCHG": {
+ "description": "Host negotiation success status\n change",
+ "offset": 9,
+ "size": 1
+ },
+ "HNGDET": {
+ "description": "Host negotiation detected",
+ "offset": 17,
+ "size": 1
+ },
+ "ADTOCHG": {
+ "description": "A-device timeout change",
+ "offset": 18,
+ "size": 1
+ },
+ "DBCDNE": {
+ "description": "Debounce done",
+ "offset": 19,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_GAHBCFG": {
+ "description": "OTG_FS AHB configuration register\n (OTG_FS_GAHBCFG)",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "GINT": {
+ "description": "Global interrupt mask",
+ "offset": 0,
+ "size": 1
+ },
+ "TXFELVL": {
+ "description": "TxFIFO empty level",
+ "offset": 7,
+ "size": 1
+ },
+ "PTXFELVL": {
+ "description": "Periodic TxFIFO empty\n level",
+ "offset": 8,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_GUSBCFG": {
+ "description": "OTG_FS USB configuration register\n (OTG_FS_GUSBCFG)",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 2560,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TOCAL": {
+ "description": "FS timeout calibration",
+ "offset": 0,
+ "size": 3
+ },
+ "PHYSEL": {
+ "description": "Full Speed serial transceiver\n select",
+ "offset": 6,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SRPCAP": {
+ "description": "SRP-capable",
+ "offset": 8,
+ "size": 1
+ },
+ "HNPCAP": {
+ "description": "HNP-capable",
+ "offset": 9,
+ "size": 1
+ },
+ "TRDT": {
+ "description": "USB turnaround time",
+ "offset": 10,
+ "size": 4
+ },
+ "FHMOD": {
+ "description": "Force host mode",
+ "offset": 29,
+ "size": 1
+ },
+ "FDMOD": {
+ "description": "Force device mode",
+ "offset": 30,
+ "size": 1
+ },
+ "CTXPKT": {
+ "description": "Corrupt Tx packet",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_GRSTCTL": {
+ "description": "OTG_FS reset register\n (OTG_FS_GRSTCTL)",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 536870912,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSRST": {
+ "description": "Core soft reset",
+ "offset": 0,
+ "size": 1
+ },
+ "HSRST": {
+ "description": "HCLK soft reset",
+ "offset": 1,
+ "size": 1
+ },
+ "FCRST": {
+ "description": "Host frame counter reset",
+ "offset": 2,
+ "size": 1
+ },
+ "RXFFLSH": {
+ "description": "RxFIFO flush",
+ "offset": 4,
+ "size": 1
+ },
+ "TXFFLSH": {
+ "description": "TxFIFO flush",
+ "offset": 5,
+ "size": 1
+ },
+ "TXFNUM": {
+ "description": "TxFIFO number",
+ "offset": 6,
+ "size": 5
+ },
+ "AHBIDL": {
+ "description": "AHB master idle",
+ "offset": 31,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "FS_GINTSTS": {
+ "description": "OTG_FS core interrupt register\n (OTG_FS_GINTSTS)",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 67108896,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CMOD": {
+ "description": "Current mode of operation",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ },
+ "MMIS": {
+ "description": "Mode mismatch interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "OTGINT": {
+ "description": "OTG interrupt",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SOF": {
+ "description": "Start of frame",
+ "offset": 3,
+ "size": 1
+ },
+ "RXFLVL": {
+ "description": "RxFIFO non-empty",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NPTXFE": {
+ "description": "Non-periodic TxFIFO empty",
+ "offset": 5,
+ "size": 1,
+ "access": "read-only"
+ },
+ "GINAKEFF": {
+ "description": "Global IN non-periodic NAK\n effective",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "GOUTNAKEFF": {
+ "description": "Global OUT NAK effective",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ESUSP": {
+ "description": "Early suspend",
+ "offset": 10,
+ "size": 1
+ },
+ "USBSUSP": {
+ "description": "USB suspend",
+ "offset": 11,
+ "size": 1
+ },
+ "USBRST": {
+ "description": "USB reset",
+ "offset": 12,
+ "size": 1
+ },
+ "ENUMDNE": {
+ "description": "Enumeration done",
+ "offset": 13,
+ "size": 1
+ },
+ "ISOODRP": {
+ "description": "Isochronous OUT packet dropped\n interrupt",
+ "offset": 14,
+ "size": 1
+ },
+ "EOPF": {
+ "description": "End of periodic frame\n interrupt",
+ "offset": 15,
+ "size": 1
+ },
+ "IEPINT": {
+ "description": "IN endpoint interrupt",
+ "offset": 18,
+ "size": 1,
+ "access": "read-only"
+ },
+ "OEPINT": {
+ "description": "OUT endpoint interrupt",
+ "offset": 19,
+ "size": 1,
+ "access": "read-only"
+ },
+ "IISOIXFR": {
+ "description": "Incomplete isochronous IN\n transfer",
+ "offset": 20,
+ "size": 1
+ },
+ "IPXFR_INCOMPISOOUT": {
+ "description": "Incomplete periodic transfer(Host\n mode)/Incomplete isochronous OUT transfer(Device\n mode)",
+ "offset": 21,
+ "size": 1
+ },
+ "HPRTINT": {
+ "description": "Host port interrupt",
+ "offset": 24,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HCINT": {
+ "description": "Host channels interrupt",
+ "offset": 25,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PTXFE": {
+ "description": "Periodic TxFIFO empty",
+ "offset": 26,
+ "size": 1,
+ "access": "read-only"
+ },
+ "CIDSCHG": {
+ "description": "Connector ID status change",
+ "offset": 28,
+ "size": 1
+ },
+ "DISCINT": {
+ "description": "Disconnect detected\n interrupt",
+ "offset": 29,
+ "size": 1
+ },
+ "SRQINT": {
+ "description": "Session request/new session detected\n interrupt",
+ "offset": 30,
+ "size": 1
+ },
+ "WKUPINT": {
+ "description": "Resume/remote wakeup detected\n interrupt",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_GINTMSK": {
+ "description": "OTG_FS interrupt mask register\n (OTG_FS_GINTMSK)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MMISM": {
+ "description": "Mode mismatch interrupt\n mask",
+ "offset": 1,
+ "size": 1
+ },
+ "OTGINT": {
+ "description": "OTG interrupt mask",
+ "offset": 2,
+ "size": 1
+ },
+ "SOFM": {
+ "description": "Start of frame mask",
+ "offset": 3,
+ "size": 1
+ },
+ "RXFLVLM": {
+ "description": "Receive FIFO non-empty\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "NPTXFEM": {
+ "description": "Non-periodic TxFIFO empty\n mask",
+ "offset": 5,
+ "size": 1
+ },
+ "GINAKEFFM": {
+ "description": "Global non-periodic IN NAK effective\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "GONAKEFFM": {
+ "description": "Global OUT NAK effective\n mask",
+ "offset": 7,
+ "size": 1
+ },
+ "ESUSPM": {
+ "description": "Early suspend mask",
+ "offset": 10,
+ "size": 1
+ },
+ "USBSUSPM": {
+ "description": "USB suspend mask",
+ "offset": 11,
+ "size": 1
+ },
+ "USBRST": {
+ "description": "USB reset mask",
+ "offset": 12,
+ "size": 1
+ },
+ "ENUMDNEM": {
+ "description": "Enumeration done mask",
+ "offset": 13,
+ "size": 1
+ },
+ "ISOODRPM": {
+ "description": "Isochronous OUT packet dropped interrupt\n mask",
+ "offset": 14,
+ "size": 1
+ },
+ "EOPFM": {
+ "description": "End of periodic frame interrupt\n mask",
+ "offset": 15,
+ "size": 1
+ },
+ "EPMISM": {
+ "description": "Endpoint mismatch interrupt\n mask",
+ "offset": 17,
+ "size": 1
+ },
+ "IEPINT": {
+ "description": "IN endpoints interrupt\n mask",
+ "offset": 18,
+ "size": 1
+ },
+ "OEPINT": {
+ "description": "OUT endpoints interrupt\n mask",
+ "offset": 19,
+ "size": 1
+ },
+ "IISOIXFRM": {
+ "description": "Incomplete isochronous IN transfer\n mask",
+ "offset": 20,
+ "size": 1
+ },
+ "IPXFRM_IISOOXFRM": {
+ "description": "Incomplete periodic transfer mask(Host\n mode)/Incomplete isochronous OUT transfer mask(Device\n mode)",
+ "offset": 21,
+ "size": 1
+ },
+ "PRTIM": {
+ "description": "Host port interrupt mask",
+ "offset": 24,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HCIM": {
+ "description": "Host channels interrupt\n mask",
+ "offset": 25,
+ "size": 1
+ },
+ "PTXFEM": {
+ "description": "Periodic TxFIFO empty mask",
+ "offset": 26,
+ "size": 1
+ },
+ "CIDSCHGM": {
+ "description": "Connector ID status change\n mask",
+ "offset": 28,
+ "size": 1
+ },
+ "DISCINT": {
+ "description": "Disconnect detected interrupt\n mask",
+ "offset": 29,
+ "size": 1
+ },
+ "SRQIM": {
+ "description": "Session request/new session detected\n interrupt mask",
+ "offset": 30,
+ "size": 1
+ },
+ "WUIM": {
+ "description": "Resume/remote wakeup detected interrupt\n mask",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_GRXSTSR_Device": {
+ "description": "OTG_FS Receive status debug read(Device\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 0,
+ "size": 4
+ },
+ "BCNT": {
+ "description": "Byte count",
+ "offset": 4,
+ "size": 11
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 15,
+ "size": 2
+ },
+ "PKTSTS": {
+ "description": "Packet status",
+ "offset": 17,
+ "size": 4
+ },
+ "FRMNUM": {
+ "description": "Frame number",
+ "offset": 21,
+ "size": 4
+ }
+ }
+ }
+ },
+ "FS_GRXSTSR_Host": {
+ "description": "OTG_FS Receive status debug read(Host\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 0,
+ "size": 4
+ },
+ "BCNT": {
+ "description": "Byte count",
+ "offset": 4,
+ "size": 11
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 15,
+ "size": 2
+ },
+ "PKTSTS": {
+ "description": "Packet status",
+ "offset": 17,
+ "size": 4
+ },
+ "FRMNUM": {
+ "description": "Frame number",
+ "offset": 21,
+ "size": 4
+ }
+ }
+ }
+ },
+ "FS_GRXFSIZ": {
+ "description": "OTG_FS Receive FIFO size register\n (OTG_FS_GRXFSIZ)",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 512,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RXFD": {
+ "description": "RxFIFO depth",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_GNPTXFSIZ_Device": {
+ "description": "OTG_FS non-periodic transmit FIFO size\n register (Device mode)",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 512,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TX0FSA": {
+ "description": "Endpoint 0 transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "TX0FD": {
+ "description": "Endpoint 0 TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_GNPTXFSIZ_Host": {
+ "description": "OTG_FS non-periodic transmit FIFO size\n register (Host mode)",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 512,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NPTXFSA": {
+ "description": "Non-periodic transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "NPTXFD": {
+ "description": "Non-periodic TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_GNPTXSTS": {
+ "description": "OTG_FS non-periodic transmit FIFO/queue\n status register (OTG_FS_GNPTXSTS)",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 524800,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "NPTXFSAV": {
+ "description": "Non-periodic TxFIFO space\n available",
+ "offset": 0,
+ "size": 16
+ },
+ "NPTQXSAV": {
+ "description": "Non-periodic transmit request queue\n space available",
+ "offset": 16,
+ "size": 8
+ },
+ "NPTXQTOP": {
+ "description": "Top of the non-periodic transmit request\n queue",
+ "offset": 24,
+ "size": 7
+ }
+ }
+ }
+ },
+ "FS_GCCFG": {
+ "description": "OTG_FS general core configuration register\n (OTG_FS_GCCFG)",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PWRDWN": {
+ "description": "Power down",
+ "offset": 16,
+ "size": 1
+ },
+ "VBUSASEN": {
+ "description": "Enable the VBUS sensing\n device",
+ "offset": 18,
+ "size": 1
+ },
+ "VBUSBSEN": {
+ "description": "Enable the VBUS sensing\n device",
+ "offset": 19,
+ "size": 1
+ },
+ "SOFOUTEN": {
+ "description": "SOF output enable",
+ "offset": 20,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_CID": {
+ "description": "core ID register",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 4096,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRODUCT_ID": {
+ "description": "Product ID field",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "FS_HPTXFSIZ": {
+ "description": "OTG_FS Host periodic transmit FIFO size\n register (OTG_FS_HPTXFSIZ)",
+ "offset": 256,
+ "size": 32,
+ "reset_value": 33555968,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PTXSA": {
+ "description": "Host periodic TxFIFO start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "PTXFSIZ": {
+ "description": "Host periodic TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_DIEPTXF1": {
+ "description": "OTG_FS device IN endpoint transmit FIFO size\n register (OTG_FS_DIEPTXF2)",
+ "offset": 260,
+ "size": 32,
+ "reset_value": 33555456,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INEPTXSA": {
+ "description": "IN endpoint FIFO2 transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "INEPTXFD": {
+ "description": "IN endpoint TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_DIEPTXF2": {
+ "description": "OTG_FS device IN endpoint transmit FIFO size\n register (OTG_FS_DIEPTXF3)",
+ "offset": 264,
+ "size": 32,
+ "reset_value": 33555456,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INEPTXSA": {
+ "description": "IN endpoint FIFO3 transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "INEPTXFD": {
+ "description": "IN endpoint TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_DIEPTXF3": {
+ "description": "OTG_FS device IN endpoint transmit FIFO size\n register (OTG_FS_DIEPTXF4)",
+ "offset": 268,
+ "size": 32,
+ "reset_value": 33555456,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INEPTXSA": {
+ "description": "IN endpoint FIFO4 transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "INEPTXFD": {
+ "description": "IN endpoint TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "OTG_FS_DEVICE": {
+ "description": "USB on the go full speed",
+ "children": {
+ "registers": {
+ "FS_DCFG": {
+ "description": "OTG_FS device configuration register\n (OTG_FS_DCFG)",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 35651584,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DSPD": {
+ "description": "Device speed",
+ "offset": 0,
+ "size": 2
+ },
+ "NZLSOHSK": {
+ "description": "Non-zero-length status OUT\n handshake",
+ "offset": 2,
+ "size": 1
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 4,
+ "size": 7
+ },
+ "PFIVL": {
+ "description": "Periodic frame interval",
+ "offset": 11,
+ "size": 2
+ }
+ }
+ }
+ },
+ "FS_DCTL": {
+ "description": "OTG_FS device control register\n (OTG_FS_DCTL)",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RWUSIG": {
+ "description": "Remote wakeup signaling",
+ "offset": 0,
+ "size": 1
+ },
+ "SDIS": {
+ "description": "Soft disconnect",
+ "offset": 1,
+ "size": 1
+ },
+ "GINSTS": {
+ "description": "Global IN NAK status",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "GONSTS": {
+ "description": "Global OUT NAK status",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TCTL": {
+ "description": "Test control",
+ "offset": 4,
+ "size": 3
+ },
+ "SGINAK": {
+ "description": "Set global IN NAK",
+ "offset": 7,
+ "size": 1
+ },
+ "CGINAK": {
+ "description": "Clear global IN NAK",
+ "offset": 8,
+ "size": 1
+ },
+ "SGONAK": {
+ "description": "Set global OUT NAK",
+ "offset": 9,
+ "size": 1
+ },
+ "CGONAK": {
+ "description": "Clear global OUT NAK",
+ "offset": 10,
+ "size": 1
+ },
+ "POPRGDNE": {
+ "description": "Power-on programming done",
+ "offset": 11,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_DSTS": {
+ "description": "OTG_FS device status register\n (OTG_FS_DSTS)",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 16,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "SUSPSTS": {
+ "description": "Suspend status",
+ "offset": 0,
+ "size": 1
+ },
+ "ENUMSPD": {
+ "description": "Enumerated speed",
+ "offset": 1,
+ "size": 2
+ },
+ "EERR": {
+ "description": "Erratic error",
+ "offset": 3,
+ "size": 1
+ },
+ "FNSOF": {
+ "description": "Frame number of the received\n SOF",
+ "offset": 8,
+ "size": 14
+ }
+ }
+ }
+ },
+ "FS_DIEPMSK": {
+ "description": "OTG_FS device IN endpoint common interrupt\n mask register (OTG_FS_DIEPMSK)",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed interrupt\n mask",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDM": {
+ "description": "Endpoint disabled interrupt\n mask",
+ "offset": 1,
+ "size": 1
+ },
+ "TOM": {
+ "description": "Timeout condition mask (Non-isochronous\n endpoints)",
+ "offset": 3,
+ "size": 1
+ },
+ "ITTXFEMSK": {
+ "description": "IN token received when TxFIFO empty\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "INEPNMM": {
+ "description": "IN token received with EP mismatch\n mask",
+ "offset": 5,
+ "size": 1
+ },
+ "INEPNEM": {
+ "description": "IN endpoint NAK effective\n mask",
+ "offset": 6,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_DOEPMSK": {
+ "description": "OTG_FS device OUT endpoint common interrupt\n mask register (OTG_FS_DOEPMSK)",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed interrupt\n mask",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDM": {
+ "description": "Endpoint disabled interrupt\n mask",
+ "offset": 1,
+ "size": 1
+ },
+ "STUPM": {
+ "description": "SETUP phase done mask",
+ "offset": 3,
+ "size": 1
+ },
+ "OTEPDM": {
+ "description": "OUT token received when endpoint\n disabled mask",
+ "offset": 4,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_DAINT": {
+ "description": "OTG_FS device all endpoints interrupt\n register (OTG_FS_DAINT)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "IEPINT": {
+ "description": "IN endpoint interrupt bits",
+ "offset": 0,
+ "size": 16
+ },
+ "OEPINT": {
+ "description": "OUT endpoint interrupt\n bits",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_DAINTMSK": {
+ "description": "OTG_FS all endpoints interrupt mask register\n (OTG_FS_DAINTMSK)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IEPM": {
+ "description": "IN EP interrupt mask bits",
+ "offset": 0,
+ "size": 16
+ },
+ "OEPINT": {
+ "description": "OUT endpoint interrupt\n bits",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DVBUSDIS": {
+ "description": "OTG_FS device VBUS discharge time\n register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 6103,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "VBUSDT": {
+ "description": "Device VBUS discharge time",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DVBUSPULSE": {
+ "description": "OTG_FS device VBUS pulsing time\n register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 1464,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DVBUSP": {
+ "description": "Device VBUS pulsing time",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DIEPEMPMSK": {
+ "description": "OTG_FS device IN endpoint FIFO empty\n interrupt mask register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INEPTXFEM": {
+ "description": "IN EP Tx FIFO empty interrupt mask\n bits",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_DIEPCTL0": {
+ "description": "OTG_FS device control IN endpoint 0 control\n register (OTG_FS_DIEPCTL0)",
+ "offset": 256,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 2
+ },
+ "USBAEP": {
+ "description": "USB active endpoint",
+ "offset": 15,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAK status",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2,
+ "access": "read-only"
+ },
+ "STALL": {
+ "description": "STALL handshake",
+ "offset": 21,
+ "size": 1
+ },
+ "TXFNUM": {
+ "description": "TxFIFO number",
+ "offset": 22,
+ "size": 4
+ },
+ "CNAK": {
+ "description": "Clear NAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "Set NAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "Endpoint disable",
+ "offset": 30,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPENA": {
+ "description": "Endpoint enable",
+ "offset": 31,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "DIEPCTL1": {
+ "description": "OTG device endpoint-1 control\n register",
+ "offset": 288,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EPENA": {
+ "description": "EPENA",
+ "offset": 31,
+ "size": 1
+ },
+ "EPDIS": {
+ "description": "EPDIS",
+ "offset": 30,
+ "size": 1
+ },
+ "SODDFRM_SD1PID": {
+ "description": "SODDFRM/SD1PID",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "SD0PID/SEVNFRM",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "SNAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CNAK": {
+ "description": "CNAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "TXFNUM": {
+ "description": "TXFNUM",
+ "offset": 22,
+ "size": 4
+ },
+ "Stall": {
+ "description": "Stall",
+ "offset": 21,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "EPTYP",
+ "offset": 18,
+ "size": 2
+ },
+ "NAKSTS": {
+ "description": "NAKSTS",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EONUM_DPID": {
+ "description": "EONUM/DPID",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "USBAEP": {
+ "description": "USBAEP",
+ "offset": 15,
+ "size": 1
+ },
+ "MPSIZ": {
+ "description": "MPSIZ",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "DIEPCTL2": {
+ "description": "OTG device endpoint-2 control\n register",
+ "offset": 320,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EPENA": {
+ "description": "EPENA",
+ "offset": 31,
+ "size": 1
+ },
+ "EPDIS": {
+ "description": "EPDIS",
+ "offset": 30,
+ "size": 1
+ },
+ "SODDFRM": {
+ "description": "SODDFRM",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "SD0PID/SEVNFRM",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "SNAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CNAK": {
+ "description": "CNAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "TXFNUM": {
+ "description": "TXFNUM",
+ "offset": 22,
+ "size": 4
+ },
+ "Stall": {
+ "description": "Stall",
+ "offset": 21,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "EPTYP",
+ "offset": 18,
+ "size": 2
+ },
+ "NAKSTS": {
+ "description": "NAKSTS",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EONUM_DPID": {
+ "description": "EONUM/DPID",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "USBAEP": {
+ "description": "USBAEP",
+ "offset": 15,
+ "size": 1
+ },
+ "MPSIZ": {
+ "description": "MPSIZ",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "DIEPCTL3": {
+ "description": "OTG device endpoint-3 control\n register",
+ "offset": 352,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EPENA": {
+ "description": "EPENA",
+ "offset": 31,
+ "size": 1
+ },
+ "EPDIS": {
+ "description": "EPDIS",
+ "offset": 30,
+ "size": 1
+ },
+ "SODDFRM": {
+ "description": "SODDFRM",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "SD0PID/SEVNFRM",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "SNAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CNAK": {
+ "description": "CNAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "TXFNUM": {
+ "description": "TXFNUM",
+ "offset": 22,
+ "size": 4
+ },
+ "Stall": {
+ "description": "Stall",
+ "offset": 21,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "EPTYP",
+ "offset": 18,
+ "size": 2
+ },
+ "NAKSTS": {
+ "description": "NAKSTS",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EONUM_DPID": {
+ "description": "EONUM/DPID",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "USBAEP": {
+ "description": "USBAEP",
+ "offset": 15,
+ "size": 1
+ },
+ "MPSIZ": {
+ "description": "MPSIZ",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "DOEPCTL0": {
+ "description": "device endpoint-0 control\n register",
+ "offset": 768,
+ "size": 32,
+ "reset_value": 32768,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EPENA": {
+ "description": "EPENA",
+ "offset": 31,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "EPDIS",
+ "offset": 30,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SNAK": {
+ "description": "SNAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CNAK": {
+ "description": "CNAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "Stall": {
+ "description": "Stall",
+ "offset": 21,
+ "size": 1
+ },
+ "SNPM": {
+ "description": "SNPM",
+ "offset": 20,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "EPTYP",
+ "offset": 18,
+ "size": 2,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAKSTS",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "USBAEP": {
+ "description": "USBAEP",
+ "offset": 15,
+ "size": 1,
+ "access": "read-only"
+ },
+ "MPSIZ": {
+ "description": "MPSIZ",
+ "offset": 0,
+ "size": 2,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "DOEPCTL1": {
+ "description": "device endpoint-1 control\n register",
+ "offset": 800,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EPENA": {
+ "description": "EPENA",
+ "offset": 31,
+ "size": 1
+ },
+ "EPDIS": {
+ "description": "EPDIS",
+ "offset": 30,
+ "size": 1
+ },
+ "SODDFRM": {
+ "description": "SODDFRM",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "SD0PID/SEVNFRM",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "SNAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CNAK": {
+ "description": "CNAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "Stall": {
+ "description": "Stall",
+ "offset": 21,
+ "size": 1
+ },
+ "SNPM": {
+ "description": "SNPM",
+ "offset": 20,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "EPTYP",
+ "offset": 18,
+ "size": 2
+ },
+ "NAKSTS": {
+ "description": "NAKSTS",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EONUM_DPID": {
+ "description": "EONUM/DPID",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "USBAEP": {
+ "description": "USBAEP",
+ "offset": 15,
+ "size": 1
+ },
+ "MPSIZ": {
+ "description": "MPSIZ",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "DOEPCTL2": {
+ "description": "device endpoint-2 control\n register",
+ "offset": 832,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EPENA": {
+ "description": "EPENA",
+ "offset": 31,
+ "size": 1
+ },
+ "EPDIS": {
+ "description": "EPDIS",
+ "offset": 30,
+ "size": 1
+ },
+ "SODDFRM": {
+ "description": "SODDFRM",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "SD0PID/SEVNFRM",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "SNAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CNAK": {
+ "description": "CNAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "Stall": {
+ "description": "Stall",
+ "offset": 21,
+ "size": 1
+ },
+ "SNPM": {
+ "description": "SNPM",
+ "offset": 20,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "EPTYP",
+ "offset": 18,
+ "size": 2
+ },
+ "NAKSTS": {
+ "description": "NAKSTS",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EONUM_DPID": {
+ "description": "EONUM/DPID",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "USBAEP": {
+ "description": "USBAEP",
+ "offset": 15,
+ "size": 1
+ },
+ "MPSIZ": {
+ "description": "MPSIZ",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "DOEPCTL3": {
+ "description": "device endpoint-3 control\n register",
+ "offset": 864,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EPENA": {
+ "description": "EPENA",
+ "offset": 31,
+ "size": 1
+ },
+ "EPDIS": {
+ "description": "EPDIS",
+ "offset": 30,
+ "size": 1
+ },
+ "SODDFRM": {
+ "description": "SODDFRM",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "SD0PID/SEVNFRM",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "SNAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CNAK": {
+ "description": "CNAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "Stall": {
+ "description": "Stall",
+ "offset": 21,
+ "size": 1
+ },
+ "SNPM": {
+ "description": "SNPM",
+ "offset": 20,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "EPTYP",
+ "offset": 18,
+ "size": 2
+ },
+ "NAKSTS": {
+ "description": "NAKSTS",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EONUM_DPID": {
+ "description": "EONUM/DPID",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "USBAEP": {
+ "description": "USBAEP",
+ "offset": 15,
+ "size": 1
+ },
+ "MPSIZ": {
+ "description": "MPSIZ",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "DIEPINT0": {
+ "description": "device endpoint-x interrupt\n register",
+ "offset": 264,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TXFE": {
+ "description": "TXFE",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "INEPNE": {
+ "description": "INEPNE",
+ "offset": 6,
+ "size": 1
+ },
+ "ITTXFE": {
+ "description": "ITTXFE",
+ "offset": 4,
+ "size": 1
+ },
+ "TOC": {
+ "description": "TOC",
+ "offset": 3,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "EPDISD",
+ "offset": 1,
+ "size": 1
+ },
+ "XFRC": {
+ "description": "XFRC",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DIEPINT1": {
+ "description": "device endpoint-1 interrupt\n register",
+ "offset": 296,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TXFE": {
+ "description": "TXFE",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "INEPNE": {
+ "description": "INEPNE",
+ "offset": 6,
+ "size": 1
+ },
+ "ITTXFE": {
+ "description": "ITTXFE",
+ "offset": 4,
+ "size": 1
+ },
+ "TOC": {
+ "description": "TOC",
+ "offset": 3,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "EPDISD",
+ "offset": 1,
+ "size": 1
+ },
+ "XFRC": {
+ "description": "XFRC",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DIEPINT2": {
+ "description": "device endpoint-2 interrupt\n register",
+ "offset": 328,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TXFE": {
+ "description": "TXFE",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "INEPNE": {
+ "description": "INEPNE",
+ "offset": 6,
+ "size": 1
+ },
+ "ITTXFE": {
+ "description": "ITTXFE",
+ "offset": 4,
+ "size": 1
+ },
+ "TOC": {
+ "description": "TOC",
+ "offset": 3,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "EPDISD",
+ "offset": 1,
+ "size": 1
+ },
+ "XFRC": {
+ "description": "XFRC",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DIEPINT3": {
+ "description": "device endpoint-3 interrupt\n register",
+ "offset": 360,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TXFE": {
+ "description": "TXFE",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "INEPNE": {
+ "description": "INEPNE",
+ "offset": 6,
+ "size": 1
+ },
+ "ITTXFE": {
+ "description": "ITTXFE",
+ "offset": 4,
+ "size": 1
+ },
+ "TOC": {
+ "description": "TOC",
+ "offset": 3,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "EPDISD",
+ "offset": 1,
+ "size": 1
+ },
+ "XFRC": {
+ "description": "XFRC",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DOEPINT0": {
+ "description": "device endpoint-0 interrupt\n register",
+ "offset": 776,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "B2BSTUP": {
+ "description": "B2BSTUP",
+ "offset": 6,
+ "size": 1
+ },
+ "OTEPDIS": {
+ "description": "OTEPDIS",
+ "offset": 4,
+ "size": 1
+ },
+ "STUP": {
+ "description": "STUP",
+ "offset": 3,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "EPDISD",
+ "offset": 1,
+ "size": 1
+ },
+ "XFRC": {
+ "description": "XFRC",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DOEPINT1": {
+ "description": "device endpoint-1 interrupt\n register",
+ "offset": 808,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "B2BSTUP": {
+ "description": "B2BSTUP",
+ "offset": 6,
+ "size": 1
+ },
+ "OTEPDIS": {
+ "description": "OTEPDIS",
+ "offset": 4,
+ "size": 1
+ },
+ "STUP": {
+ "description": "STUP",
+ "offset": 3,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "EPDISD",
+ "offset": 1,
+ "size": 1
+ },
+ "XFRC": {
+ "description": "XFRC",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DOEPINT2": {
+ "description": "device endpoint-2 interrupt\n register",
+ "offset": 840,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "B2BSTUP": {
+ "description": "B2BSTUP",
+ "offset": 6,
+ "size": 1
+ },
+ "OTEPDIS": {
+ "description": "OTEPDIS",
+ "offset": 4,
+ "size": 1
+ },
+ "STUP": {
+ "description": "STUP",
+ "offset": 3,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "EPDISD",
+ "offset": 1,
+ "size": 1
+ },
+ "XFRC": {
+ "description": "XFRC",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DOEPINT3": {
+ "description": "device endpoint-3 interrupt\n register",
+ "offset": 872,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "B2BSTUP": {
+ "description": "B2BSTUP",
+ "offset": 6,
+ "size": 1
+ },
+ "OTEPDIS": {
+ "description": "OTEPDIS",
+ "offset": 4,
+ "size": 1
+ },
+ "STUP": {
+ "description": "STUP",
+ "offset": 3,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "EPDISD",
+ "offset": 1,
+ "size": 1
+ },
+ "XFRC": {
+ "description": "XFRC",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DIEPTSIZ0": {
+ "description": "device endpoint-0 transfer size\n register",
+ "offset": 272,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 2
+ },
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 7
+ }
+ }
+ }
+ },
+ "DOEPTSIZ0": {
+ "description": "device OUT endpoint-0 transfer size\n register",
+ "offset": 784,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "STUPCNT": {
+ "description": "SETUP packet count",
+ "offset": 29,
+ "size": 2
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 1
+ },
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 7
+ }
+ }
+ }
+ },
+ "DIEPTSIZ1": {
+ "description": "device endpoint-1 transfer size\n register",
+ "offset": 304,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MCNT": {
+ "description": "Multi count",
+ "offset": 29,
+ "size": 2
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ }
+ }
+ }
+ },
+ "DIEPTSIZ2": {
+ "description": "device endpoint-2 transfer size\n register",
+ "offset": 336,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MCNT": {
+ "description": "Multi count",
+ "offset": 29,
+ "size": 2
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ }
+ }
+ }
+ },
+ "DIEPTSIZ3": {
+ "description": "device endpoint-3 transfer size\n register",
+ "offset": 368,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MCNT": {
+ "description": "Multi count",
+ "offset": 29,
+ "size": 2
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ }
+ }
+ }
+ },
+ "DTXFSTS0": {
+ "description": "OTG_FS device IN endpoint transmit FIFO\n status register",
+ "offset": 280,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "INEPTFSAV": {
+ "description": "IN endpoint TxFIFO space\n available",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DTXFSTS1": {
+ "description": "OTG_FS device IN endpoint transmit FIFO\n status register",
+ "offset": 312,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "INEPTFSAV": {
+ "description": "IN endpoint TxFIFO space\n available",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DTXFSTS2": {
+ "description": "OTG_FS device IN endpoint transmit FIFO\n status register",
+ "offset": 344,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "INEPTFSAV": {
+ "description": "IN endpoint TxFIFO space\n available",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DTXFSTS3": {
+ "description": "OTG_FS device IN endpoint transmit FIFO\n status register",
+ "offset": 376,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "INEPTFSAV": {
+ "description": "IN endpoint TxFIFO space\n available",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DOEPTSIZ1": {
+ "description": "device OUT endpoint-1 transfer size\n register",
+ "offset": 816,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RXDPID_STUPCNT": {
+ "description": "Received data PID/SETUP packet\n count",
+ "offset": 29,
+ "size": 2
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ }
+ }
+ }
+ },
+ "DOEPTSIZ2": {
+ "description": "device OUT endpoint-2 transfer size\n register",
+ "offset": 848,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RXDPID_STUPCNT": {
+ "description": "Received data PID/SETUP packet\n count",
+ "offset": 29,
+ "size": 2
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ }
+ }
+ }
+ },
+ "DOEPTSIZ3": {
+ "description": "device OUT endpoint-3 transfer size\n register",
+ "offset": 880,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RXDPID_STUPCNT": {
+ "description": "Received data PID/SETUP packet\n count",
+ "offset": 29,
+ "size": 2
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "USB": {
+ "description": "Universal serial bus full-speed device\n interface",
+ "children": {
+ "registers": {
+ "EP0R": {
+ "description": "endpoint 0 register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EA": {
+ "description": "Endpoint address",
+ "offset": 0,
+ "size": 4
+ },
+ "STAT_TX": {
+ "description": "Status bits, for transmission\n transfers",
+ "offset": 4,
+ "size": 2
+ },
+ "DTOG_TX": {
+ "description": "Data Toggle, for transmission\n transfers",
+ "offset": 6,
+ "size": 1
+ },
+ "CTR_TX": {
+ "description": "Correct Transfer for\n transmission",
+ "offset": 7,
+ "size": 1
+ },
+ "EP_KIND": {
+ "description": "Endpoint kind",
+ "offset": 8,
+ "size": 1
+ },
+ "EP_TYPE": {
+ "description": "Endpoint type",
+ "offset": 9,
+ "size": 2
+ },
+ "SETUP": {
+ "description": "Setup transaction\n completed",
+ "offset": 11,
+ "size": 1
+ },
+ "STAT_RX": {
+ "description": "Status bits, for reception\n transfers",
+ "offset": 12,
+ "size": 2
+ },
+ "DTOG_RX": {
+ "description": "Data Toggle, for reception\n transfers",
+ "offset": 14,
+ "size": 1
+ },
+ "CTR_RX": {
+ "description": "Correct transfer for\n reception",
+ "offset": 15,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EP1R": {
+ "description": "endpoint 1 register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EA": {
+ "description": "Endpoint address",
+ "offset": 0,
+ "size": 4
+ },
+ "STAT_TX": {
+ "description": "Status bits, for transmission\n transfers",
+ "offset": 4,
+ "size": 2
+ },
+ "DTOG_TX": {
+ "description": "Data Toggle, for transmission\n transfers",
+ "offset": 6,
+ "size": 1
+ },
+ "CTR_TX": {
+ "description": "Correct Transfer for\n transmission",
+ "offset": 7,
+ "size": 1
+ },
+ "EP_KIND": {
+ "description": "Endpoint kind",
+ "offset": 8,
+ "size": 1
+ },
+ "EP_TYPE": {
+ "description": "Endpoint type",
+ "offset": 9,
+ "size": 2
+ },
+ "SETUP": {
+ "description": "Setup transaction\n completed",
+ "offset": 11,
+ "size": 1
+ },
+ "STAT_RX": {
+ "description": "Status bits, for reception\n transfers",
+ "offset": 12,
+ "size": 2
+ },
+ "DTOG_RX": {
+ "description": "Data Toggle, for reception\n transfers",
+ "offset": 14,
+ "size": 1
+ },
+ "CTR_RX": {
+ "description": "Correct transfer for\n reception",
+ "offset": 15,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EP2R": {
+ "description": "endpoint 2 register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EA": {
+ "description": "Endpoint address",
+ "offset": 0,
+ "size": 4
+ },
+ "STAT_TX": {
+ "description": "Status bits, for transmission\n transfers",
+ "offset": 4,
+ "size": 2
+ },
+ "DTOG_TX": {
+ "description": "Data Toggle, for transmission\n transfers",
+ "offset": 6,
+ "size": 1
+ },
+ "CTR_TX": {
+ "description": "Correct Transfer for\n transmission",
+ "offset": 7,
+ "size": 1
+ },
+ "EP_KIND": {
+ "description": "Endpoint kind",
+ "offset": 8,
+ "size": 1
+ },
+ "EP_TYPE": {
+ "description": "Endpoint type",
+ "offset": 9,
+ "size": 2
+ },
+ "SETUP": {
+ "description": "Setup transaction\n completed",
+ "offset": 11,
+ "size": 1
+ },
+ "STAT_RX": {
+ "description": "Status bits, for reception\n transfers",
+ "offset": 12,
+ "size": 2
+ },
+ "DTOG_RX": {
+ "description": "Data Toggle, for reception\n transfers",
+ "offset": 14,
+ "size": 1
+ },
+ "CTR_RX": {
+ "description": "Correct transfer for\n reception",
+ "offset": 15,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EP3R": {
+ "description": "endpoint 3 register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EA": {
+ "description": "Endpoint address",
+ "offset": 0,
+ "size": 4
+ },
+ "STAT_TX": {
+ "description": "Status bits, for transmission\n transfers",
+ "offset": 4,
+ "size": 2
+ },
+ "DTOG_TX": {
+ "description": "Data Toggle, for transmission\n transfers",
+ "offset": 6,
+ "size": 1
+ },
+ "CTR_TX": {
+ "description": "Correct Transfer for\n transmission",
+ "offset": 7,
+ "size": 1
+ },
+ "EP_KIND": {
+ "description": "Endpoint kind",
+ "offset": 8,
+ "size": 1
+ },
+ "EP_TYPE": {
+ "description": "Endpoint type",
+ "offset": 9,
+ "size": 2
+ },
+ "SETUP": {
+ "description": "Setup transaction\n completed",
+ "offset": 11,
+ "size": 1
+ },
+ "STAT_RX": {
+ "description": "Status bits, for reception\n transfers",
+ "offset": 12,
+ "size": 2
+ },
+ "DTOG_RX": {
+ "description": "Data Toggle, for reception\n transfers",
+ "offset": 14,
+ "size": 1
+ },
+ "CTR_RX": {
+ "description": "Correct transfer for\n reception",
+ "offset": 15,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EP4R": {
+ "description": "endpoint 4 register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EA": {
+ "description": "Endpoint address",
+ "offset": 0,
+ "size": 4
+ },
+ "STAT_TX": {
+ "description": "Status bits, for transmission\n transfers",
+ "offset": 4,
+ "size": 2
+ },
+ "DTOG_TX": {
+ "description": "Data Toggle, for transmission\n transfers",
+ "offset": 6,
+ "size": 1
+ },
+ "CTR_TX": {
+ "description": "Correct Transfer for\n transmission",
+ "offset": 7,
+ "size": 1
+ },
+ "EP_KIND": {
+ "description": "Endpoint kind",
+ "offset": 8,
+ "size": 1
+ },
+ "EP_TYPE": {
+ "description": "Endpoint type",
+ "offset": 9,
+ "size": 2
+ },
+ "SETUP": {
+ "description": "Setup transaction\n completed",
+ "offset": 11,
+ "size": 1
+ },
+ "STAT_RX": {
+ "description": "Status bits, for reception\n transfers",
+ "offset": 12,
+ "size": 2
+ },
+ "DTOG_RX": {
+ "description": "Data Toggle, for reception\n transfers",
+ "offset": 14,
+ "size": 1
+ },
+ "CTR_RX": {
+ "description": "Correct transfer for\n reception",
+ "offset": 15,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EP5R": {
+ "description": "endpoint 5 register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EA": {
+ "description": "Endpoint address",
+ "offset": 0,
+ "size": 4
+ },
+ "STAT_TX": {
+ "description": "Status bits, for transmission\n transfers",
+ "offset": 4,
+ "size": 2
+ },
+ "DTOG_TX": {
+ "description": "Data Toggle, for transmission\n transfers",
+ "offset": 6,
+ "size": 1
+ },
+ "CTR_TX": {
+ "description": "Correct Transfer for\n transmission",
+ "offset": 7,
+ "size": 1
+ },
+ "EP_KIND": {
+ "description": "Endpoint kind",
+ "offset": 8,
+ "size": 1
+ },
+ "EP_TYPE": {
+ "description": "Endpoint type",
+ "offset": 9,
+ "size": 2
+ },
+ "SETUP": {
+ "description": "Setup transaction\n completed",
+ "offset": 11,
+ "size": 1
+ },
+ "STAT_RX": {
+ "description": "Status bits, for reception\n transfers",
+ "offset": 12,
+ "size": 2
+ },
+ "DTOG_RX": {
+ "description": "Data Toggle, for reception\n transfers",
+ "offset": 14,
+ "size": 1
+ },
+ "CTR_RX": {
+ "description": "Correct transfer for\n reception",
+ "offset": 15,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EP6R": {
+ "description": "endpoint 6 register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EA": {
+ "description": "Endpoint address",
+ "offset": 0,
+ "size": 4
+ },
+ "STAT_TX": {
+ "description": "Status bits, for transmission\n transfers",
+ "offset": 4,
+ "size": 2
+ },
+ "DTOG_TX": {
+ "description": "Data Toggle, for transmission\n transfers",
+ "offset": 6,
+ "size": 1
+ },
+ "CTR_TX": {
+ "description": "Correct Transfer for\n transmission",
+ "offset": 7,
+ "size": 1
+ },
+ "EP_KIND": {
+ "description": "Endpoint kind",
+ "offset": 8,
+ "size": 1
+ },
+ "EP_TYPE": {
+ "description": "Endpoint type",
+ "offset": 9,
+ "size": 2
+ },
+ "SETUP": {
+ "description": "Setup transaction\n completed",
+ "offset": 11,
+ "size": 1
+ },
+ "STAT_RX": {
+ "description": "Status bits, for reception\n transfers",
+ "offset": 12,
+ "size": 2
+ },
+ "DTOG_RX": {
+ "description": "Data Toggle, for reception\n transfers",
+ "offset": 14,
+ "size": 1
+ },
+ "CTR_RX": {
+ "description": "Correct transfer for\n reception",
+ "offset": 15,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EP7R": {
+ "description": "endpoint 7 register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EA": {
+ "description": "Endpoint address",
+ "offset": 0,
+ "size": 4
+ },
+ "STAT_TX": {
+ "description": "Status bits, for transmission\n transfers",
+ "offset": 4,
+ "size": 2
+ },
+ "DTOG_TX": {
+ "description": "Data Toggle, for transmission\n transfers",
+ "offset": 6,
+ "size": 1
+ },
+ "CTR_TX": {
+ "description": "Correct Transfer for\n transmission",
+ "offset": 7,
+ "size": 1
+ },
+ "EP_KIND": {
+ "description": "Endpoint kind",
+ "offset": 8,
+ "size": 1
+ },
+ "EP_TYPE": {
+ "description": "Endpoint type",
+ "offset": 9,
+ "size": 2
+ },
+ "SETUP": {
+ "description": "Setup transaction\n completed",
+ "offset": 11,
+ "size": 1
+ },
+ "STAT_RX": {
+ "description": "Status bits, for reception\n transfers",
+ "offset": 12,
+ "size": 2
+ },
+ "DTOG_RX": {
+ "description": "Data Toggle, for reception\n transfers",
+ "offset": 14,
+ "size": 1
+ },
+ "CTR_RX": {
+ "description": "Correct transfer for\n reception",
+ "offset": 15,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNTR": {
+ "description": "control register",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 3,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FRES": {
+ "description": "Force USB Reset",
+ "offset": 0,
+ "size": 1
+ },
+ "PDWN": {
+ "description": "Power down",
+ "offset": 1,
+ "size": 1
+ },
+ "LPMODE": {
+ "description": "Low-power mode",
+ "offset": 2,
+ "size": 1
+ },
+ "FSUSP": {
+ "description": "Force suspend",
+ "offset": 3,
+ "size": 1
+ },
+ "RESUME": {
+ "description": "Resume request",
+ "offset": 4,
+ "size": 1
+ },
+ "ESOFM": {
+ "description": "Expected start of frame interrupt\n mask",
+ "offset": 8,
+ "size": 1
+ },
+ "SOFM": {
+ "description": "Start of frame interrupt\n mask",
+ "offset": 9,
+ "size": 1
+ },
+ "RESETM": {
+ "description": "USB reset interrupt mask",
+ "offset": 10,
+ "size": 1
+ },
+ "SUSPM": {
+ "description": "Suspend mode interrupt\n mask",
+ "offset": 11,
+ "size": 1
+ },
+ "WKUPM": {
+ "description": "Wakeup interrupt mask",
+ "offset": 12,
+ "size": 1
+ },
+ "ERRM": {
+ "description": "Error interrupt mask",
+ "offset": 13,
+ "size": 1
+ },
+ "PMAOVRM": {
+ "description": "Packet memory area over / underrun\n interrupt mask",
+ "offset": 14,
+ "size": 1
+ },
+ "CTRM": {
+ "description": "Correct transfer interrupt\n mask",
+ "offset": 15,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ISTR": {
+ "description": "interrupt status register",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EP_ID": {
+ "description": "Endpoint Identifier",
+ "offset": 0,
+ "size": 4
+ },
+ "DIR": {
+ "description": "Direction of transaction",
+ "offset": 4,
+ "size": 1
+ },
+ "ESOF": {
+ "description": "Expected start frame",
+ "offset": 8,
+ "size": 1
+ },
+ "SOF": {
+ "description": "start of frame",
+ "offset": 9,
+ "size": 1
+ },
+ "RESET": {
+ "description": "reset request",
+ "offset": 10,
+ "size": 1
+ },
+ "SUSP": {
+ "description": "Suspend mode request",
+ "offset": 11,
+ "size": 1
+ },
+ "WKUP": {
+ "description": "Wakeup",
+ "offset": 12,
+ "size": 1
+ },
+ "ERR": {
+ "description": "Error",
+ "offset": 13,
+ "size": 1
+ },
+ "PMAOVR": {
+ "description": "Packet memory area over /\n underrun",
+ "offset": 14,
+ "size": 1
+ },
+ "CTR": {
+ "description": "Correct transfer",
+ "offset": 15,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FNR": {
+ "description": "frame number register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "FN": {
+ "description": "Frame number",
+ "offset": 0,
+ "size": 11
+ },
+ "LSOF": {
+ "description": "Lost SOF",
+ "offset": 11,
+ "size": 2
+ },
+ "LCK": {
+ "description": "Locked",
+ "offset": 13,
+ "size": 1
+ },
+ "RXDM": {
+ "description": "Receive data - line status",
+ "offset": 14,
+ "size": 1
+ },
+ "RXDP": {
+ "description": "Receive data + line status",
+ "offset": 15,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DADDR": {
+ "description": "device address",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ADD": {
+ "description": "Device address",
+ "offset": 0,
+ "size": 7
+ },
+ "EF": {
+ "description": "Enable function",
+ "offset": 7,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BTABLE": {
+ "description": "Buffer table address",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BTABLE": {
+ "description": "Buffer table",
+ "offset": 3,
+ "size": 13
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "TIM6": {
+ "description": "Basic timer",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARPE": {
+ "description": "Auto-reload preload enable",
+ "offset": 7,
+ "size": 1
+ },
+ "OPM": {
+ "description": "One-pulse mode",
+ "offset": 3,
+ "size": 1
+ },
+ "URS": {
+ "description": "Update request source",
+ "offset": 2,
+ "size": 1
+ },
+ "UDIS": {
+ "description": "Update disable",
+ "offset": 1,
+ "size": 1
+ },
+ "CEN": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MMS": {
+ "description": "Master mode selection",
+ "offset": 4,
+ "size": 3
+ }
+ }
+ }
+ },
+ "DIER": {
+ "description": "DMA/Interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "UDE": {
+ "description": "Update DMA request enable",
+ "offset": 8,
+ "size": 1
+ },
+ "UIE": {
+ "description": "Update interrupt enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "UIF": {
+ "description": "Update interrupt flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EGR": {
+ "description": "event generation register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "UG": {
+ "description": "Update generation",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNT": {
+ "description": "counter",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNT": {
+ "description": "Low counter value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "PSC": {
+ "description": "prescaler",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ARR": {
+ "description": "auto-reload register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARR": {
+ "description": "Low Auto-reload value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "FLASH": {
+ "description": "FLASH",
+ "children": {
+ "registers": {
+ "ACR": {
+ "description": "Flash access control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 48,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LATENCY": {
+ "description": "Latency",
+ "offset": 0,
+ "size": 3
+ },
+ "HLFCYA": {
+ "description": "Flash half cycle access\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "PRFTBE": {
+ "description": "Prefetch buffer enable",
+ "offset": 4,
+ "size": 1
+ },
+ "PRFTBS": {
+ "description": "Prefetch buffer status",
+ "offset": 5,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "KEYR": {
+ "description": "Flash key register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "KEY": {
+ "description": "FPEC key",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OPTKEYR": {
+ "description": "Flash option key register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "OPTKEY": {
+ "description": "Option byte key",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "Status register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EOP": {
+ "description": "End of operation",
+ "offset": 5,
+ "size": 1
+ },
+ "WRPRTERR": {
+ "description": "Write protection error",
+ "offset": 4,
+ "size": 1
+ },
+ "PGERR": {
+ "description": "Programming error",
+ "offset": 2,
+ "size": 1
+ },
+ "BSY": {
+ "description": "Busy",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "CR": {
+ "description": "Control register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PG": {
+ "description": "Programming",
+ "offset": 0,
+ "size": 1
+ },
+ "PER": {
+ "description": "Page Erase",
+ "offset": 1,
+ "size": 1
+ },
+ "MER": {
+ "description": "Mass Erase",
+ "offset": 2,
+ "size": 1
+ },
+ "OPTPG": {
+ "description": "Option byte programming",
+ "offset": 4,
+ "size": 1
+ },
+ "OPTER": {
+ "description": "Option byte erase",
+ "offset": 5,
+ "size": 1
+ },
+ "STRT": {
+ "description": "Start",
+ "offset": 6,
+ "size": 1
+ },
+ "LOCK": {
+ "description": "Lock",
+ "offset": 7,
+ "size": 1
+ },
+ "OPTWRE": {
+ "description": "Option bytes write enable",
+ "offset": 9,
+ "size": 1
+ },
+ "ERRIE": {
+ "description": "Error interrupt enable",
+ "offset": 10,
+ "size": 1
+ },
+ "EOPIE": {
+ "description": "End of operation interrupt\n enable",
+ "offset": 12,
+ "size": 1
+ }
+ }
+ }
+ },
+ "AR": {
+ "description": "Flash address register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "FAR": {
+ "description": "Flash Address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OBR": {
+ "description": "Option byte register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 67108860,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "OPTERR": {
+ "description": "Option byte error",
+ "offset": 0,
+ "size": 1
+ },
+ "RDPRT": {
+ "description": "Read protection",
+ "offset": 1,
+ "size": 1
+ },
+ "WDG_SW": {
+ "description": "WDG_SW",
+ "offset": 2,
+ "size": 1
+ },
+ "nRST_STOP": {
+ "description": "nRST_STOP",
+ "offset": 3,
+ "size": 1
+ },
+ "nRST_STDBY": {
+ "description": "nRST_STDBY",
+ "offset": 4,
+ "size": 1
+ },
+ "Data0": {
+ "description": "Data0",
+ "offset": 10,
+ "size": 8
+ },
+ "Data1": {
+ "description": "Data1",
+ "offset": 18,
+ "size": 8
+ }
+ }
+ }
+ },
+ "WRPR": {
+ "description": "Write protection register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "WRP": {
+ "description": "Write protect",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "I2C1": {
+ "description": "Inter integrated circuit",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "Control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SWRST": {
+ "description": "Software reset",
+ "offset": 15,
+ "size": 1
+ },
+ "ALERT": {
+ "description": "SMBus alert",
+ "offset": 13,
+ "size": 1
+ },
+ "PEC": {
+ "description": "Packet error checking",
+ "offset": 12,
+ "size": 1
+ },
+ "POS": {
+ "description": "Acknowledge/PEC Position (for data\n reception)",
+ "offset": 11,
+ "size": 1
+ },
+ "ACK": {
+ "description": "Acknowledge enable",
+ "offset": 10,
+ "size": 1
+ },
+ "STOP": {
+ "description": "Stop generation",
+ "offset": 9,
+ "size": 1
+ },
+ "START": {
+ "description": "Start generation",
+ "offset": 8,
+ "size": 1
+ },
+ "NOSTRETCH": {
+ "description": "Clock stretching disable (Slave\n mode)",
+ "offset": 7,
+ "size": 1
+ },
+ "ENGC": {
+ "description": "General call enable",
+ "offset": 6,
+ "size": 1
+ },
+ "ENPEC": {
+ "description": "PEC enable",
+ "offset": 5,
+ "size": 1
+ },
+ "ENARP": {
+ "description": "ARP enable",
+ "offset": 4,
+ "size": 1
+ },
+ "SMBTYPE": {
+ "description": "SMBus type",
+ "offset": 3,
+ "size": 1
+ },
+ "SMBUS": {
+ "description": "SMBus mode",
+ "offset": 1,
+ "size": 1
+ },
+ "PE": {
+ "description": "Peripheral enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "Control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LAST": {
+ "description": "DMA last transfer",
+ "offset": 12,
+ "size": 1
+ },
+ "DMAEN": {
+ "description": "DMA requests enable",
+ "offset": 11,
+ "size": 1
+ },
+ "ITBUFEN": {
+ "description": "Buffer interrupt enable",
+ "offset": 10,
+ "size": 1
+ },
+ "ITEVTEN": {
+ "description": "Event interrupt enable",
+ "offset": 9,
+ "size": 1
+ },
+ "ITERREN": {
+ "description": "Error interrupt enable",
+ "offset": 8,
+ "size": 1
+ },
+ "FREQ": {
+ "description": "Peripheral clock frequency",
+ "offset": 0,
+ "size": 6
+ }
+ }
+ }
+ },
+ "OAR1": {
+ "description": "Own address register 1",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ADDMODE": {
+ "description": "Addressing mode (slave\n mode)",
+ "offset": 15,
+ "size": 1
+ },
+ "ADD10": {
+ "description": "Interface address",
+ "offset": 8,
+ "size": 2
+ },
+ "ADD7": {
+ "description": "Interface address",
+ "offset": 1,
+ "size": 7
+ },
+ "ADD0": {
+ "description": "Interface address",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OAR2": {
+ "description": "Own address register 2",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ADD2": {
+ "description": "Interface address",
+ "offset": 1,
+ "size": 7
+ },
+ "ENDUAL": {
+ "description": "Dual addressing mode\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DR": {
+ "description": "Data register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DR": {
+ "description": "8-bit data register",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "SR1": {
+ "description": "Status register 1",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SMBALERT": {
+ "description": "SMBus alert",
+ "offset": 15,
+ "size": 1
+ },
+ "TIMEOUT": {
+ "description": "Timeout or Tlow error",
+ "offset": 14,
+ "size": 1
+ },
+ "PECERR": {
+ "description": "PEC Error in reception",
+ "offset": 12,
+ "size": 1
+ },
+ "OVR": {
+ "description": "Overrun/Underrun",
+ "offset": 11,
+ "size": 1
+ },
+ "AF": {
+ "description": "Acknowledge failure",
+ "offset": 10,
+ "size": 1
+ },
+ "ARLO": {
+ "description": "Arbitration lost (master\n mode)",
+ "offset": 9,
+ "size": 1
+ },
+ "BERR": {
+ "description": "Bus error",
+ "offset": 8,
+ "size": 1
+ },
+ "TxE": {
+ "description": "Data register empty\n (transmitters)",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "RxNE": {
+ "description": "Data register not empty\n (receivers)",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "STOPF": {
+ "description": "Stop detection (slave\n mode)",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ADD10": {
+ "description": "10-bit header sent (Master\n mode)",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "BTF": {
+ "description": "Byte transfer finished",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ADDR": {
+ "description": "Address sent (master mode)/matched\n (slave mode)",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SB": {
+ "description": "Start bit (Master mode)",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "SR2": {
+ "description": "Status register 2",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "PEC": {
+ "description": "acket error checking\n register",
+ "offset": 8,
+ "size": 8
+ },
+ "DUALF": {
+ "description": "Dual flag (Slave mode)",
+ "offset": 7,
+ "size": 1
+ },
+ "SMBHOST": {
+ "description": "SMBus host header (Slave\n mode)",
+ "offset": 6,
+ "size": 1
+ },
+ "SMBDEFAULT": {
+ "description": "SMBus device default address (Slave\n mode)",
+ "offset": 5,
+ "size": 1
+ },
+ "GENCALL": {
+ "description": "General call address (Slave\n mode)",
+ "offset": 4,
+ "size": 1
+ },
+ "TRA": {
+ "description": "Transmitter/receiver",
+ "offset": 2,
+ "size": 1
+ },
+ "BUSY": {
+ "description": "Bus busy",
+ "offset": 1,
+ "size": 1
+ },
+ "MSL": {
+ "description": "Master/slave",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCR": {
+ "description": "Clock control register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "F_S": {
+ "description": "I2C master mode selection",
+ "offset": 15,
+ "size": 1
+ },
+ "DUTY": {
+ "description": "Fast mode duty cycle",
+ "offset": 14,
+ "size": 1
+ },
+ "CCR": {
+ "description": "Clock control register in Fast/Standard\n mode (Master mode)",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "TRISE": {
+ "description": "TRISE register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 2,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TRISE": {
+ "description": "Maximum rise time in Fast/Standard mode\n (Master mode)",
+ "offset": 0,
+ "size": 6
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "CRC": {
+ "description": "CRC calculation unit",
+ "children": {
+ "registers": {
+ "DR": {
+ "description": "Data register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DR": {
+ "description": "Data Register",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "IDR": {
+ "description": "Independent Data register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IDR": {
+ "description": "Independent Data register",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "CR": {
+ "description": "Control register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "RESET": {
+ "description": "Reset bit",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "SPI1": {
+ "description": "Serial peripheral interface",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BIDIMODE": {
+ "description": "Bidirectional data mode\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "BIDIOE": {
+ "description": "Output enable in bidirectional\n mode",
+ "offset": 14,
+ "size": 1
+ },
+ "CRCEN": {
+ "description": "Hardware CRC calculation\n enable",
+ "offset": 13,
+ "size": 1
+ },
+ "CRCNEXT": {
+ "description": "CRC transfer next",
+ "offset": 12,
+ "size": 1
+ },
+ "DFF": {
+ "description": "Data frame format",
+ "offset": 11,
+ "size": 1
+ },
+ "RXONLY": {
+ "description": "Receive only",
+ "offset": 10,
+ "size": 1
+ },
+ "SSM": {
+ "description": "Software slave management",
+ "offset": 9,
+ "size": 1
+ },
+ "SSI": {
+ "description": "Internal slave select",
+ "offset": 8,
+ "size": 1
+ },
+ "LSBFIRST": {
+ "description": "Frame format",
+ "offset": 7,
+ "size": 1
+ },
+ "SPE": {
+ "description": "SPI enable",
+ "offset": 6,
+ "size": 1
+ },
+ "BR": {
+ "description": "Baud rate control",
+ "offset": 3,
+ "size": 3
+ },
+ "MSTR": {
+ "description": "Master selection",
+ "offset": 2,
+ "size": 1
+ },
+ "CPOL": {
+ "description": "Clock polarity",
+ "offset": 1,
+ "size": 1
+ },
+ "CPHA": {
+ "description": "Clock phase",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TXEIE": {
+ "description": "Tx buffer empty interrupt\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "RXNEIE": {
+ "description": "RX buffer not empty interrupt\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "ERRIE": {
+ "description": "Error interrupt enable",
+ "offset": 5,
+ "size": 1
+ },
+ "SSOE": {
+ "description": "SS output enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TXDMAEN": {
+ "description": "Tx buffer DMA enable",
+ "offset": 1,
+ "size": 1
+ },
+ "RXDMAEN": {
+ "description": "Rx buffer DMA enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 2,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BSY": {
+ "description": "Busy flag",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "OVR": {
+ "description": "Overrun flag",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "MODF": {
+ "description": "Mode fault",
+ "offset": 5,
+ "size": 1,
+ "access": "read-only"
+ },
+ "CRCERR": {
+ "description": "CRC error flag",
+ "offset": 4,
+ "size": 1
+ },
+ "UDR": {
+ "description": "Underrun flag",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "CHSIDE": {
+ "description": "Channel side",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TXE": {
+ "description": "Transmit buffer empty",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "RXNE": {
+ "description": "Receive buffer not empty",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "DR": {
+ "description": "data register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DR": {
+ "description": "Data register",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CRCPR": {
+ "description": "CRC polynomial register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 7,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CRCPOLY": {
+ "description": "CRC polynomial register",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "RXCRCR": {
+ "description": "RX CRC register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "RxCRC": {
+ "description": "Rx CRC register",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "TXCRCR": {
+ "description": "TX CRC register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "TxCRC": {
+ "description": "Tx CRC register",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "I2SCFGR": {
+ "description": "I2S configuration register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "I2SMOD": {
+ "description": "I2S mode selection",
+ "offset": 11,
+ "size": 1
+ },
+ "I2SE": {
+ "description": "I2S Enable",
+ "offset": 10,
+ "size": 1
+ },
+ "I2SCFG": {
+ "description": "I2S configuration mode",
+ "offset": 8,
+ "size": 2
+ },
+ "PCMSYNC": {
+ "description": "PCM frame synchronization",
+ "offset": 7,
+ "size": 1
+ },
+ "I2SSTD": {
+ "description": "I2S standard selection",
+ "offset": 4,
+ "size": 2
+ },
+ "CKPOL": {
+ "description": "Steady state clock\n polarity",
+ "offset": 3,
+ "size": 1
+ },
+ "DATLEN": {
+ "description": "Data length to be\n transferred",
+ "offset": 1,
+ "size": 2
+ },
+ "CHLEN": {
+ "description": "Channel length (number of bits per audio\n channel)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "I2SPR": {
+ "description": "I2S prescaler register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 10,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MCKOE": {
+ "description": "Master clock output enable",
+ "offset": 9,
+ "size": 1
+ },
+ "ODD": {
+ "description": "Odd factor for the\n prescaler",
+ "offset": 8,
+ "size": 1
+ },
+ "I2SDIV": {
+ "description": "I2S Linear prescaler",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "UART5": {
+ "description": "Universal asynchronous receiver\n transmitter",
+ "children": {
+ "registers": {
+ "SR": {
+ "description": "UART4_SR",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PE": {
+ "description": "PE",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ },
+ "FE": {
+ "description": "FE",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NE": {
+ "description": "NE",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ORE": {
+ "description": "ORE",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "IDLE": {
+ "description": "IDLE",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "RXNE": {
+ "description": "RXNE",
+ "offset": 5,
+ "size": 1
+ },
+ "TC": {
+ "description": "TC",
+ "offset": 6,
+ "size": 1
+ },
+ "TXE": {
+ "description": "TXE",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "LBD": {
+ "description": "LBD",
+ "offset": 8,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DR": {
+ "description": "UART4_DR",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DR": {
+ "description": "DR",
+ "offset": 0,
+ "size": 9
+ }
+ }
+ }
+ },
+ "BRR": {
+ "description": "UART4_BRR",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DIV_Fraction": {
+ "description": "DIV_Fraction",
+ "offset": 0,
+ "size": 4
+ },
+ "DIV_Mantissa": {
+ "description": "DIV_Mantissa",
+ "offset": 4,
+ "size": 12
+ }
+ }
+ }
+ },
+ "CR1": {
+ "description": "UART4_CR1",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SBK": {
+ "description": "SBK",
+ "offset": 0,
+ "size": 1
+ },
+ "RWU": {
+ "description": "RWU",
+ "offset": 1,
+ "size": 1
+ },
+ "RE": {
+ "description": "RE",
+ "offset": 2,
+ "size": 1
+ },
+ "TE": {
+ "description": "TE",
+ "offset": 3,
+ "size": 1
+ },
+ "IDLEIE": {
+ "description": "IDLEIE",
+ "offset": 4,
+ "size": 1
+ },
+ "RXNEIE": {
+ "description": "RXNEIE",
+ "offset": 5,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "TCIE",
+ "offset": 6,
+ "size": 1
+ },
+ "TXEIE": {
+ "description": "TXEIE",
+ "offset": 7,
+ "size": 1
+ },
+ "PEIE": {
+ "description": "PEIE",
+ "offset": 8,
+ "size": 1
+ },
+ "PS": {
+ "description": "PS",
+ "offset": 9,
+ "size": 1
+ },
+ "PCE": {
+ "description": "PCE",
+ "offset": 10,
+ "size": 1
+ },
+ "WAKE": {
+ "description": "WAKE",
+ "offset": 11,
+ "size": 1
+ },
+ "M": {
+ "description": "M",
+ "offset": 12,
+ "size": 1
+ },
+ "UE": {
+ "description": "UE",
+ "offset": 13,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "UART4_CR2",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ADD": {
+ "description": "ADD",
+ "offset": 0,
+ "size": 4
+ },
+ "LBDL": {
+ "description": "LBDL",
+ "offset": 5,
+ "size": 1
+ },
+ "LBDIE": {
+ "description": "LBDIE",
+ "offset": 6,
+ "size": 1
+ },
+ "STOP": {
+ "description": "STOP",
+ "offset": 12,
+ "size": 2
+ },
+ "LINEN": {
+ "description": "LINEN",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR3": {
+ "description": "UART4_CR3",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EIE": {
+ "description": "Error interrupt enable",
+ "offset": 0,
+ "size": 1
+ },
+ "IREN": {
+ "description": "IrDA mode enable",
+ "offset": 1,
+ "size": 1
+ },
+ "IRLP": {
+ "description": "IrDA low-power",
+ "offset": 2,
+ "size": 1
+ },
+ "HDSEL": {
+ "description": "Half-duplex selection",
+ "offset": 3,
+ "size": 1
+ },
+ "DMAT": {
+ "description": "DMA enable transmitter",
+ "offset": 7,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "UART4": {
+ "description": "Universal asynchronous receiver\n transmitter",
+ "children": {
+ "registers": {
+ "SR": {
+ "description": "UART4_SR",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PE": {
+ "description": "Parity error",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ },
+ "FE": {
+ "description": "Framing error",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NE": {
+ "description": "Noise error flag",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ORE": {
+ "description": "Overrun error",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "IDLE": {
+ "description": "IDLE line detected",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "RXNE": {
+ "description": "Read data register not\n empty",
+ "offset": 5,
+ "size": 1
+ },
+ "TC": {
+ "description": "Transmission complete",
+ "offset": 6,
+ "size": 1
+ },
+ "TXE": {
+ "description": "Transmit data register\n empty",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "LBD": {
+ "description": "LIN break detection flag",
+ "offset": 8,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DR": {
+ "description": "UART4_DR",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DR": {
+ "description": "DR",
+ "offset": 0,
+ "size": 9
+ }
+ }
+ }
+ },
+ "BRR": {
+ "description": "UART4_BRR",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DIV_Fraction": {
+ "description": "DIV_Fraction",
+ "offset": 0,
+ "size": 4
+ },
+ "DIV_Mantissa": {
+ "description": "DIV_Mantissa",
+ "offset": 4,
+ "size": 12
+ }
+ }
+ }
+ },
+ "CR1": {
+ "description": "UART4_CR1",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SBK": {
+ "description": "Send break",
+ "offset": 0,
+ "size": 1
+ },
+ "RWU": {
+ "description": "Receiver wakeup",
+ "offset": 1,
+ "size": 1
+ },
+ "RE": {
+ "description": "Receiver enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TE": {
+ "description": "Transmitter enable",
+ "offset": 3,
+ "size": 1
+ },
+ "IDLEIE": {
+ "description": "IDLE interrupt enable",
+ "offset": 4,
+ "size": 1
+ },
+ "RXNEIE": {
+ "description": "RXNE interrupt enable",
+ "offset": 5,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transmission complete interrupt\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "TXEIE": {
+ "description": "TXE interrupt enable",
+ "offset": 7,
+ "size": 1
+ },
+ "PEIE": {
+ "description": "PE interrupt enable",
+ "offset": 8,
+ "size": 1
+ },
+ "PS": {
+ "description": "Parity selection",
+ "offset": 9,
+ "size": 1
+ },
+ "PCE": {
+ "description": "Parity control enable",
+ "offset": 10,
+ "size": 1
+ },
+ "WAKE": {
+ "description": "Wakeup method",
+ "offset": 11,
+ "size": 1
+ },
+ "M": {
+ "description": "Word length",
+ "offset": 12,
+ "size": 1
+ },
+ "UE": {
+ "description": "USART enable",
+ "offset": 13,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "UART4_CR2",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ADD": {
+ "description": "Address of the USART node",
+ "offset": 0,
+ "size": 4
+ },
+ "LBDL": {
+ "description": "lin break detection length",
+ "offset": 5,
+ "size": 1
+ },
+ "LBDIE": {
+ "description": "LIN break detection interrupt\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "STOP": {
+ "description": "STOP bits",
+ "offset": 12,
+ "size": 2
+ },
+ "LINEN": {
+ "description": "LIN mode enable",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR3": {
+ "description": "UART4_CR3",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EIE": {
+ "description": "Error interrupt enable",
+ "offset": 0,
+ "size": 1
+ },
+ "IREN": {
+ "description": "IrDA mode enable",
+ "offset": 1,
+ "size": 1
+ },
+ "IRLP": {
+ "description": "IrDA low-power",
+ "offset": 2,
+ "size": 1
+ },
+ "HDSEL": {
+ "description": "Half-duplex selection",
+ "offset": 3,
+ "size": 1
+ },
+ "DMAR": {
+ "description": "DMA enable receiver",
+ "offset": 6,
+ "size": 1
+ },
+ "DMAT": {
+ "description": "DMA enable transmitter",
+ "offset": 7,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "USART1": {
+ "description": "Universal synchronous asynchronous receiver\n transmitter",
+ "children": {
+ "registers": {
+ "SR": {
+ "description": "Status register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 192,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CTS": {
+ "description": "CTS flag",
+ "offset": 9,
+ "size": 1
+ },
+ "LBD": {
+ "description": "LIN break detection flag",
+ "offset": 8,
+ "size": 1
+ },
+ "TXE": {
+ "description": "Transmit data register\n empty",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TC": {
+ "description": "Transmission complete",
+ "offset": 6,
+ "size": 1
+ },
+ "RXNE": {
+ "description": "Read data register not\n empty",
+ "offset": 5,
+ "size": 1
+ },
+ "IDLE": {
+ "description": "IDLE line detected",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ORE": {
+ "description": "Overrun error",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NE": {
+ "description": "Noise error flag",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "FE": {
+ "description": "Framing error",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PE": {
+ "description": "Parity error",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "DR": {
+ "description": "Data register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DR": {
+ "description": "Data value",
+ "offset": 0,
+ "size": 9
+ }
+ }
+ }
+ },
+ "BRR": {
+ "description": "Baud rate register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DIV_Mantissa": {
+ "description": "mantissa of USARTDIV",
+ "offset": 4,
+ "size": 12
+ },
+ "DIV_Fraction": {
+ "description": "fraction of USARTDIV",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "CR1": {
+ "description": "Control register 1",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "UE": {
+ "description": "USART enable",
+ "offset": 13,
+ "size": 1
+ },
+ "M": {
+ "description": "Word length",
+ "offset": 12,
+ "size": 1
+ },
+ "WAKE": {
+ "description": "Wakeup method",
+ "offset": 11,
+ "size": 1
+ },
+ "PCE": {
+ "description": "Parity control enable",
+ "offset": 10,
+ "size": 1
+ },
+ "PS": {
+ "description": "Parity selection",
+ "offset": 9,
+ "size": 1
+ },
+ "PEIE": {
+ "description": "PE interrupt enable",
+ "offset": 8,
+ "size": 1
+ },
+ "TXEIE": {
+ "description": "TXE interrupt enable",
+ "offset": 7,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transmission complete interrupt\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "RXNEIE": {
+ "description": "RXNE interrupt enable",
+ "offset": 5,
+ "size": 1
+ },
+ "IDLEIE": {
+ "description": "IDLE interrupt enable",
+ "offset": 4,
+ "size": 1
+ },
+ "TE": {
+ "description": "Transmitter enable",
+ "offset": 3,
+ "size": 1
+ },
+ "RE": {
+ "description": "Receiver enable",
+ "offset": 2,
+ "size": 1
+ },
+ "RWU": {
+ "description": "Receiver wakeup",
+ "offset": 1,
+ "size": 1
+ },
+ "SBK": {
+ "description": "Send break",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "Control register 2",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LINEN": {
+ "description": "LIN mode enable",
+ "offset": 14,
+ "size": 1
+ },
+ "STOP": {
+ "description": "STOP bits",
+ "offset": 12,
+ "size": 2
+ },
+ "CLKEN": {
+ "description": "Clock enable",
+ "offset": 11,
+ "size": 1
+ },
+ "CPOL": {
+ "description": "Clock polarity",
+ "offset": 10,
+ "size": 1
+ },
+ "CPHA": {
+ "description": "Clock phase",
+ "offset": 9,
+ "size": 1
+ },
+ "LBCL": {
+ "description": "Last bit clock pulse",
+ "offset": 8,
+ "size": 1
+ },
+ "LBDIE": {
+ "description": "LIN break detection interrupt\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "LBDL": {
+ "description": "lin break detection length",
+ "offset": 5,
+ "size": 1
+ },
+ "ADD": {
+ "description": "Address of the USART node",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "CR3": {
+ "description": "Control register 3",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CTSIE": {
+ "description": "CTS interrupt enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CTSE": {
+ "description": "CTS enable",
+ "offset": 9,
+ "size": 1
+ },
+ "RTSE": {
+ "description": "RTS enable",
+ "offset": 8,
+ "size": 1
+ },
+ "DMAT": {
+ "description": "DMA enable transmitter",
+ "offset": 7,
+ "size": 1
+ },
+ "DMAR": {
+ "description": "DMA enable receiver",
+ "offset": 6,
+ "size": 1
+ },
+ "SCEN": {
+ "description": "Smartcard mode enable",
+ "offset": 5,
+ "size": 1
+ },
+ "NACK": {
+ "description": "Smartcard NACK enable",
+ "offset": 4,
+ "size": 1
+ },
+ "HDSEL": {
+ "description": "Half-duplex selection",
+ "offset": 3,
+ "size": 1
+ },
+ "IRLP": {
+ "description": "IrDA low-power",
+ "offset": 2,
+ "size": 1
+ },
+ "IREN": {
+ "description": "IrDA mode enable",
+ "offset": 1,
+ "size": 1
+ },
+ "EIE": {
+ "description": "Error interrupt enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "GTPR": {
+ "description": "Guard time and prescaler\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "GT": {
+ "description": "Guard time value",
+ "offset": 8,
+ "size": 8
+ },
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "DBG": {
+ "description": "Debug support",
+ "children": {
+ "registers": {
+ "IDCODE": {
+ "description": "DBGMCU_IDCODE",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DEV_ID": {
+ "description": "DEV_ID",
+ "offset": 0,
+ "size": 12
+ },
+ "REV_ID": {
+ "description": "REV_ID",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CR": {
+ "description": "DBGMCU_CR",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBG_SLEEP": {
+ "description": "DBG_SLEEP",
+ "offset": 0,
+ "size": 1
+ },
+ "DBG_STOP": {
+ "description": "DBG_STOP",
+ "offset": 1,
+ "size": 1
+ },
+ "DBG_STANDBY": {
+ "description": "DBG_STANDBY",
+ "offset": 2,
+ "size": 1
+ },
+ "TRACE_IOEN": {
+ "description": "TRACE_IOEN",
+ "offset": 5,
+ "size": 1
+ },
+ "TRACE_MODE": {
+ "description": "TRACE_MODE",
+ "offset": 6,
+ "size": 2
+ },
+ "DBG_IWDG_STOP": {
+ "description": "DBG_IWDG_STOP",
+ "offset": 8,
+ "size": 1
+ },
+ "DBG_WWDG_STOP": {
+ "description": "DBG_WWDG_STOP",
+ "offset": 9,
+ "size": 1
+ },
+ "DBG_TIM1_STOP": {
+ "description": "DBG_TIM1_STOP",
+ "offset": 10,
+ "size": 1
+ },
+ "DBG_TIM2_STOP": {
+ "description": "DBG_TIM2_STOP",
+ "offset": 11,
+ "size": 1
+ },
+ "DBG_TIM3_STOP": {
+ "description": "DBG_TIM3_STOP",
+ "offset": 12,
+ "size": 1
+ },
+ "DBG_TIM4_STOP": {
+ "description": "DBG_TIM4_STOP",
+ "offset": 13,
+ "size": 1
+ },
+ "DBG_CAN1_STOP": {
+ "description": "DBG_CAN1_STOP",
+ "offset": 14,
+ "size": 1
+ },
+ "DBG_I2C1_SMBUS_TIMEOUT": {
+ "description": "DBG_I2C1_SMBUS_TIMEOUT",
+ "offset": 15,
+ "size": 1
+ },
+ "DBG_I2C2_SMBUS_TIMEOUT": {
+ "description": "DBG_I2C2_SMBUS_TIMEOUT",
+ "offset": 16,
+ "size": 1
+ },
+ "DBG_TIM8_STOP": {
+ "description": "DBG_TIM8_STOP",
+ "offset": 17,
+ "size": 1
+ },
+ "DBG_TIM5_STOP": {
+ "description": "DBG_TIM5_STOP",
+ "offset": 18,
+ "size": 1
+ },
+ "DBG_TIM6_STOP": {
+ "description": "DBG_TIM6_STOP",
+ "offset": 19,
+ "size": 1
+ },
+ "DBG_TIM7_STOP": {
+ "description": "DBG_TIM7_STOP",
+ "offset": 20,
+ "size": 1
+ },
+ "DBG_CAN2_STOP": {
+ "description": "DBG_CAN2_STOP",
+ "offset": 21,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "DAC": {
+ "description": "Digital to analog converter",
+ "children": {
+ "registers": {
+ "CR": {
+ "description": "Control register (DAC_CR)",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EN1": {
+ "description": "DAC channel1 enable",
+ "offset": 0,
+ "size": 1
+ },
+ "BOFF1": {
+ "description": "DAC channel1 output buffer\n disable",
+ "offset": 1,
+ "size": 1
+ },
+ "TEN1": {
+ "description": "DAC channel1 trigger\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TSEL1": {
+ "description": "DAC channel1 trigger\n selection",
+ "offset": 3,
+ "size": 3
+ },
+ "WAVE1": {
+ "description": "DAC channel1 noise/triangle wave\n generation enable",
+ "offset": 6,
+ "size": 2
+ },
+ "MAMP1": {
+ "description": "DAC channel1 mask/amplitude\n selector",
+ "offset": 8,
+ "size": 4
+ },
+ "DMAEN1": {
+ "description": "DAC channel1 DMA enable",
+ "offset": 12,
+ "size": 1
+ },
+ "EN2": {
+ "description": "DAC channel2 enable",
+ "offset": 16,
+ "size": 1
+ },
+ "BOFF2": {
+ "description": "DAC channel2 output buffer\n disable",
+ "offset": 17,
+ "size": 1
+ },
+ "TEN2": {
+ "description": "DAC channel2 trigger\n enable",
+ "offset": 18,
+ "size": 1
+ },
+ "TSEL2": {
+ "description": "DAC channel2 trigger\n selection",
+ "offset": 19,
+ "size": 3
+ },
+ "WAVE2": {
+ "description": "DAC channel2 noise/triangle wave\n generation enable",
+ "offset": 22,
+ "size": 2
+ },
+ "MAMP2": {
+ "description": "DAC channel2 mask/amplitude\n selector",
+ "offset": 24,
+ "size": 4
+ },
+ "DMAEN2": {
+ "description": "DAC channel2 DMA enable",
+ "offset": 28,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SWTRIGR": {
+ "description": "DAC software trigger register\n (DAC_SWTRIGR)",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "SWTRIG1": {
+ "description": "DAC channel1 software\n trigger",
+ "offset": 0,
+ "size": 1
+ },
+ "SWTRIG2": {
+ "description": "DAC channel2 software\n trigger",
+ "offset": 1,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DHR12R1": {
+ "description": "DAC channel1 12-bit right-aligned data\n holding register(DAC_DHR12R1)",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC1DHR": {
+ "description": "DAC channel1 12-bit right-aligned\n data",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DHR12L1": {
+ "description": "DAC channel1 12-bit left aligned data\n holding register (DAC_DHR12L1)",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC1DHR": {
+ "description": "DAC channel1 12-bit left-aligned\n data",
+ "offset": 4,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DHR8R1": {
+ "description": "DAC channel1 8-bit right aligned data\n holding register (DAC_DHR8R1)",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC1DHR": {
+ "description": "DAC channel1 8-bit right-aligned\n data",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "DHR12R2": {
+ "description": "DAC channel2 12-bit right aligned data\n holding register (DAC_DHR12R2)",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC2DHR": {
+ "description": "DAC channel2 12-bit right-aligned\n data",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DHR12L2": {
+ "description": "DAC channel2 12-bit left aligned data\n holding register (DAC_DHR12L2)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC2DHR": {
+ "description": "DAC channel2 12-bit left-aligned\n data",
+ "offset": 4,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DHR8R2": {
+ "description": "DAC channel2 8-bit right-aligned data\n holding register (DAC_DHR8R2)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC2DHR": {
+ "description": "DAC channel2 8-bit right-aligned\n data",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "DHR12RD": {
+ "description": "Dual DAC 12-bit right-aligned data holding\n register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12\n Reserved",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC1DHR": {
+ "description": "DAC channel1 12-bit right-aligned\n data",
+ "offset": 0,
+ "size": 12
+ },
+ "DACC2DHR": {
+ "description": "DAC channel2 12-bit right-aligned\n data",
+ "offset": 16,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DHR12LD": {
+ "description": "DUAL DAC 12-bit left aligned data holding\n register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0\n Reserved",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC1DHR": {
+ "description": "DAC channel1 12-bit left-aligned\n data",
+ "offset": 4,
+ "size": 12
+ },
+ "DACC2DHR": {
+ "description": "DAC channel2 12-bit right-aligned\n data",
+ "offset": 20,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DHR8RD": {
+ "description": "DUAL DAC 8-bit right aligned data holding\n register (DAC_DHR8RD), Bits 31:16 Reserved",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC1DHR": {
+ "description": "DAC channel1 8-bit right-aligned\n data",
+ "offset": 0,
+ "size": 8
+ },
+ "DACC2DHR": {
+ "description": "DAC channel2 8-bit right-aligned\n data",
+ "offset": 8,
+ "size": 8
+ }
+ }
+ }
+ },
+ "DOR1": {
+ "description": "DAC channel1 data output register\n (DAC_DOR1)",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DACC1DOR": {
+ "description": "DAC channel1 data output",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DOR2": {
+ "description": "DAC channel2 data output register\n (DAC_DOR2)",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DACC2DOR": {
+ "description": "DAC channel2 data output",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "ADC1": {
+ "description": "Analog to digital converter",
+ "children": {
+ "registers": {
+ "SR": {
+ "description": "status register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "STRT": {
+ "description": "Regular channel start flag",
+ "offset": 4,
+ "size": 1
+ },
+ "JSTRT": {
+ "description": "Injected channel start\n flag",
+ "offset": 3,
+ "size": 1
+ },
+ "JEOC": {
+ "description": "Injected channel end of\n conversion",
+ "offset": 2,
+ "size": 1
+ },
+ "EOC": {
+ "description": "Regular channel end of\n conversion",
+ "offset": 1,
+ "size": 1
+ },
+ "AWD": {
+ "description": "Analog watchdog flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR1": {
+ "description": "control register 1",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "AWDEN": {
+ "description": "Analog watchdog enable on regular\n channels",
+ "offset": 23,
+ "size": 1
+ },
+ "JAWDEN": {
+ "description": "Analog watchdog enable on injected\n channels",
+ "offset": 22,
+ "size": 1
+ },
+ "DUALMOD": {
+ "description": "Dual mode selection",
+ "offset": 16,
+ "size": 4
+ },
+ "DISCNUM": {
+ "description": "Discontinuous mode channel\n count",
+ "offset": 13,
+ "size": 3
+ },
+ "JDISCEN": {
+ "description": "Discontinuous mode on injected\n channels",
+ "offset": 12,
+ "size": 1
+ },
+ "DISCEN": {
+ "description": "Discontinuous mode on regular\n channels",
+ "offset": 11,
+ "size": 1
+ },
+ "JAUTO": {
+ "description": "Automatic injected group\n conversion",
+ "offset": 10,
+ "size": 1
+ },
+ "AWDSGL": {
+ "description": "Enable the watchdog on a single channel\n in scan mode",
+ "offset": 9,
+ "size": 1
+ },
+ "SCAN": {
+ "description": "Scan mode",
+ "offset": 8,
+ "size": 1
+ },
+ "JEOCIE": {
+ "description": "Interrupt enable for injected\n channels",
+ "offset": 7,
+ "size": 1
+ },
+ "AWDIE": {
+ "description": "Analog watchdog interrupt\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "EOCIE": {
+ "description": "Interrupt enable for EOC",
+ "offset": 5,
+ "size": 1
+ },
+ "AWDCH": {
+ "description": "Analog watchdog channel select\n bits",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TSVREFE": {
+ "description": "Temperature sensor and VREFINT\n enable",
+ "offset": 23,
+ "size": 1
+ },
+ "SWSTART": {
+ "description": "Start conversion of regular\n channels",
+ "offset": 22,
+ "size": 1
+ },
+ "JSWSTART": {
+ "description": "Start conversion of injected\n channels",
+ "offset": 21,
+ "size": 1
+ },
+ "EXTTRIG": {
+ "description": "External trigger conversion mode for\n regular channels",
+ "offset": 20,
+ "size": 1
+ },
+ "EXTSEL": {
+ "description": "External event select for regular\n group",
+ "offset": 17,
+ "size": 3
+ },
+ "JEXTTRIG": {
+ "description": "External trigger conversion mode for\n injected channels",
+ "offset": 15,
+ "size": 1
+ },
+ "JEXTSEL": {
+ "description": "External event select for injected\n group",
+ "offset": 12,
+ "size": 3
+ },
+ "ALIGN": {
+ "description": "Data alignment",
+ "offset": 11,
+ "size": 1
+ },
+ "DMA": {
+ "description": "Direct memory access mode",
+ "offset": 8,
+ "size": 1
+ },
+ "RSTCAL": {
+ "description": "Reset calibration",
+ "offset": 3,
+ "size": 1
+ },
+ "CAL": {
+ "description": "A/D calibration",
+ "offset": 2,
+ "size": 1
+ },
+ "CONT": {
+ "description": "Continuous conversion",
+ "offset": 1,
+ "size": 1
+ },
+ "ADON": {
+ "description": "A/D converter ON / OFF",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SMPR1": {
+ "description": "sample time register 1",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SMP10": {
+ "description": "Channel 10 sample time\n selection",
+ "offset": 0,
+ "size": 3
+ },
+ "SMP11": {
+ "description": "Channel 11 sample time\n selection",
+ "offset": 3,
+ "size": 3
+ },
+ "SMP12": {
+ "description": "Channel 12 sample time\n selection",
+ "offset": 6,
+ "size": 3
+ },
+ "SMP13": {
+ "description": "Channel 13 sample time\n selection",
+ "offset": 9,
+ "size": 3
+ },
+ "SMP14": {
+ "description": "Channel 14 sample time\n selection",
+ "offset": 12,
+ "size": 3
+ },
+ "SMP15": {
+ "description": "Channel 15 sample time\n selection",
+ "offset": 15,
+ "size": 3
+ },
+ "SMP16": {
+ "description": "Channel 16 sample time\n selection",
+ "offset": 18,
+ "size": 3
+ },
+ "SMP17": {
+ "description": "Channel 17 sample time\n selection",
+ "offset": 21,
+ "size": 3
+ }
+ }
+ }
+ },
+ "SMPR2": {
+ "description": "sample time register 2",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SMP0": {
+ "description": "Channel 0 sample time\n selection",
+ "offset": 0,
+ "size": 3
+ },
+ "SMP1": {
+ "description": "Channel 1 sample time\n selection",
+ "offset": 3,
+ "size": 3
+ },
+ "SMP2": {
+ "description": "Channel 2 sample time\n selection",
+ "offset": 6,
+ "size": 3
+ },
+ "SMP3": {
+ "description": "Channel 3 sample time\n selection",
+ "offset": 9,
+ "size": 3
+ },
+ "SMP4": {
+ "description": "Channel 4 sample time\n selection",
+ "offset": 12,
+ "size": 3
+ },
+ "SMP5": {
+ "description": "Channel 5 sample time\n selection",
+ "offset": 15,
+ "size": 3
+ },
+ "SMP6": {
+ "description": "Channel 6 sample time\n selection",
+ "offset": 18,
+ "size": 3
+ },
+ "SMP7": {
+ "description": "Channel 7 sample time\n selection",
+ "offset": 21,
+ "size": 3
+ },
+ "SMP8": {
+ "description": "Channel 8 sample time\n selection",
+ "offset": 24,
+ "size": 3
+ },
+ "SMP9": {
+ "description": "Channel 9 sample time\n selection",
+ "offset": 27,
+ "size": 3
+ }
+ }
+ }
+ },
+ "JOFR1": {
+ "description": "injected channel data offset register\n x",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "JOFFSET1": {
+ "description": "Data offset for injected channel\n x",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "JOFR2": {
+ "description": "injected channel data offset register\n x",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "JOFFSET2": {
+ "description": "Data offset for injected channel\n x",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "JOFR3": {
+ "description": "injected channel data offset register\n x",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "JOFFSET3": {
+ "description": "Data offset for injected channel\n x",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "JOFR4": {
+ "description": "injected channel data offset register\n x",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "JOFFSET4": {
+ "description": "Data offset for injected channel\n x",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "HTR": {
+ "description": "watchdog higher threshold\n register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 4095,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "HT": {
+ "description": "Analog watchdog higher\n threshold",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "LTR": {
+ "description": "watchdog lower threshold\n register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LT": {
+ "description": "Analog watchdog lower\n threshold",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "SQR1": {
+ "description": "regular sequence register 1",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "L": {
+ "description": "Regular channel sequence\n length",
+ "offset": 20,
+ "size": 4
+ },
+ "SQ16": {
+ "description": "16th conversion in regular\n sequence",
+ "offset": 15,
+ "size": 5
+ },
+ "SQ15": {
+ "description": "15th conversion in regular\n sequence",
+ "offset": 10,
+ "size": 5
+ },
+ "SQ14": {
+ "description": "14th conversion in regular\n sequence",
+ "offset": 5,
+ "size": 5
+ },
+ "SQ13": {
+ "description": "13th conversion in regular\n sequence",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "SQR2": {
+ "description": "regular sequence register 2",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SQ12": {
+ "description": "12th conversion in regular\n sequence",
+ "offset": 25,
+ "size": 5
+ },
+ "SQ11": {
+ "description": "11th conversion in regular\n sequence",
+ "offset": 20,
+ "size": 5
+ },
+ "SQ10": {
+ "description": "10th conversion in regular\n sequence",
+ "offset": 15,
+ "size": 5
+ },
+ "SQ9": {
+ "description": "9th conversion in regular\n sequence",
+ "offset": 10,
+ "size": 5
+ },
+ "SQ8": {
+ "description": "8th conversion in regular\n sequence",
+ "offset": 5,
+ "size": 5
+ },
+ "SQ7": {
+ "description": "7th conversion in regular\n sequence",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "SQR3": {
+ "description": "regular sequence register 3",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SQ6": {
+ "description": "6th conversion in regular\n sequence",
+ "offset": 25,
+ "size": 5
+ },
+ "SQ5": {
+ "description": "5th conversion in regular\n sequence",
+ "offset": 20,
+ "size": 5
+ },
+ "SQ4": {
+ "description": "4th conversion in regular\n sequence",
+ "offset": 15,
+ "size": 5
+ },
+ "SQ3": {
+ "description": "3rd conversion in regular\n sequence",
+ "offset": 10,
+ "size": 5
+ },
+ "SQ2": {
+ "description": "2nd conversion in regular\n sequence",
+ "offset": 5,
+ "size": 5
+ },
+ "SQ1": {
+ "description": "1st conversion in regular\n sequence",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "JSQR": {
+ "description": "injected sequence register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "JL": {
+ "description": "Injected sequence length",
+ "offset": 20,
+ "size": 2
+ },
+ "JSQ4": {
+ "description": "4th conversion in injected\n sequence",
+ "offset": 15,
+ "size": 5
+ },
+ "JSQ3": {
+ "description": "3rd conversion in injected\n sequence",
+ "offset": 10,
+ "size": 5
+ },
+ "JSQ2": {
+ "description": "2nd conversion in injected\n sequence",
+ "offset": 5,
+ "size": 5
+ },
+ "JSQ1": {
+ "description": "1st conversion in injected\n sequence",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "JDR1": {
+ "description": "injected data register x",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "JDATA": {
+ "description": "Injected data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "JDR2": {
+ "description": "injected data register x",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "JDATA": {
+ "description": "Injected data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "JDR3": {
+ "description": "injected data register x",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "JDATA": {
+ "description": "Injected data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "JDR4": {
+ "description": "injected data register x",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "JDATA": {
+ "description": "Injected data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR": {
+ "description": "regular data register",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DATA": {
+ "description": "Regular data",
+ "offset": 0,
+ "size": 16
+ },
+ "ADC2DATA": {
+ "description": "ADC2 data",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "ADC2": {
+ "description": "Analog to digital converter",
+ "children": {
+ "registers": {
+ "SR": {
+ "description": "status register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "STRT": {
+ "description": "Regular channel start flag",
+ "offset": 4,
+ "size": 1
+ },
+ "JSTRT": {
+ "description": "Injected channel start\n flag",
+ "offset": 3,
+ "size": 1
+ },
+ "JEOC": {
+ "description": "Injected channel end of\n conversion",
+ "offset": 2,
+ "size": 1
+ },
+ "EOC": {
+ "description": "Regular channel end of\n conversion",
+ "offset": 1,
+ "size": 1
+ },
+ "AWD": {
+ "description": "Analog watchdog flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR1": {
+ "description": "control register 1",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "AWDEN": {
+ "description": "Analog watchdog enable on regular\n channels",
+ "offset": 23,
+ "size": 1
+ },
+ "JAWDEN": {
+ "description": "Analog watchdog enable on injected\n channels",
+ "offset": 22,
+ "size": 1
+ },
+ "DISCNUM": {
+ "description": "Discontinuous mode channel\n count",
+ "offset": 13,
+ "size": 3
+ },
+ "JDISCEN": {
+ "description": "Discontinuous mode on injected\n channels",
+ "offset": 12,
+ "size": 1
+ },
+ "DISCEN": {
+ "description": "Discontinuous mode on regular\n channels",
+ "offset": 11,
+ "size": 1
+ },
+ "JAUTO": {
+ "description": "Automatic injected group\n conversion",
+ "offset": 10,
+ "size": 1
+ },
+ "AWDSGL": {
+ "description": "Enable the watchdog on a single channel\n in scan mode",
+ "offset": 9,
+ "size": 1
+ },
+ "SCAN": {
+ "description": "Scan mode",
+ "offset": 8,
+ "size": 1
+ },
+ "JEOCIE": {
+ "description": "Interrupt enable for injected\n channels",
+ "offset": 7,
+ "size": 1
+ },
+ "AWDIE": {
+ "description": "Analog watchdog interrupt\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "EOCIE": {
+ "description": "Interrupt enable for EOC",
+ "offset": 5,
+ "size": 1
+ },
+ "AWDCH": {
+ "description": "Analog watchdog channel select\n bits",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TSVREFE": {
+ "description": "Temperature sensor and VREFINT\n enable",
+ "offset": 23,
+ "size": 1
+ },
+ "SWSTART": {
+ "description": "Start conversion of regular\n channels",
+ "offset": 22,
+ "size": 1
+ },
+ "JSWSTART": {
+ "description": "Start conversion of injected\n channels",
+ "offset": 21,
+ "size": 1
+ },
+ "EXTTRIG": {
+ "description": "External trigger conversion mode for\n regular channels",
+ "offset": 20,
+ "size": 1
+ },
+ "EXTSEL": {
+ "description": "External event select for regular\n group",
+ "offset": 17,
+ "size": 3
+ },
+ "JEXTTRIG": {
+ "description": "External trigger conversion mode for\n injected channels",
+ "offset": 15,
+ "size": 1
+ },
+ "JEXTSEL": {
+ "description": "External event select for injected\n group",
+ "offset": 12,
+ "size": 3
+ },
+ "ALIGN": {
+ "description": "Data alignment",
+ "offset": 11,
+ "size": 1
+ },
+ "DMA": {
+ "description": "Direct memory access mode",
+ "offset": 8,
+ "size": 1
+ },
+ "RSTCAL": {
+ "description": "Reset calibration",
+ "offset": 3,
+ "size": 1
+ },
+ "CAL": {
+ "description": "A/D calibration",
+ "offset": 2,
+ "size": 1
+ },
+ "CONT": {
+ "description": "Continuous conversion",
+ "offset": 1,
+ "size": 1
+ },
+ "ADON": {
+ "description": "A/D converter ON / OFF",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SMPR1": {
+ "description": "sample time register 1",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SMP10": {
+ "description": "Channel 10 sample time\n selection",
+ "offset": 0,
+ "size": 3
+ },
+ "SMP11": {
+ "description": "Channel 11 sample time\n selection",
+ "offset": 3,
+ "size": 3
+ },
+ "SMP12": {
+ "description": "Channel 12 sample time\n selection",
+ "offset": 6,
+ "size": 3
+ },
+ "SMP13": {
+ "description": "Channel 13 sample time\n selection",
+ "offset": 9,
+ "size": 3
+ },
+ "SMP14": {
+ "description": "Channel 14 sample time\n selection",
+ "offset": 12,
+ "size": 3
+ },
+ "SMP15": {
+ "description": "Channel 15 sample time\n selection",
+ "offset": 15,
+ "size": 3
+ },
+ "SMP16": {
+ "description": "Channel 16 sample time\n selection",
+ "offset": 18,
+ "size": 3
+ },
+ "SMP17": {
+ "description": "Channel 17 sample time\n selection",
+ "offset": 21,
+ "size": 3
+ }
+ }
+ }
+ },
+ "SMPR2": {
+ "description": "sample time register 2",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SMP0": {
+ "description": "Channel 0 sample time\n selection",
+ "offset": 0,
+ "size": 3
+ },
+ "SMP1": {
+ "description": "Channel 1 sample time\n selection",
+ "offset": 3,
+ "size": 3
+ },
+ "SMP2": {
+ "description": "Channel 2 sample time\n selection",
+ "offset": 6,
+ "size": 3
+ },
+ "SMP3": {
+ "description": "Channel 3 sample time\n selection",
+ "offset": 9,
+ "size": 3
+ },
+ "SMP4": {
+ "description": "Channel 4 sample time\n selection",
+ "offset": 12,
+ "size": 3
+ },
+ "SMP5": {
+ "description": "Channel 5 sample time\n selection",
+ "offset": 15,
+ "size": 3
+ },
+ "SMP6": {
+ "description": "Channel 6 sample time\n selection",
+ "offset": 18,
+ "size": 3
+ },
+ "SMP7": {
+ "description": "Channel 7 sample time\n selection",
+ "offset": 21,
+ "size": 3
+ },
+ "SMP8": {
+ "description": "Channel 8 sample time\n selection",
+ "offset": 24,
+ "size": 3
+ },
+ "SMP9": {
+ "description": "Channel 9 sample time\n selection",
+ "offset": 27,
+ "size": 3
+ }
+ }
+ }
+ },
+ "JOFR1": {
+ "description": "injected channel data offset register\n x",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "JOFFSET1": {
+ "description": "Data offset for injected channel\n x",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "JOFR2": {
+ "description": "injected channel data offset register\n x",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "JOFFSET2": {
+ "description": "Data offset for injected channel\n x",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "JOFR3": {
+ "description": "injected channel data offset register\n x",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "JOFFSET3": {
+ "description": "Data offset for injected channel\n x",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "JOFR4": {
+ "description": "injected channel data offset register\n x",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "JOFFSET4": {
+ "description": "Data offset for injected channel\n x",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "HTR": {
+ "description": "watchdog higher threshold\n register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 4095,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "HT": {
+ "description": "Analog watchdog higher\n threshold",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "LTR": {
+ "description": "watchdog lower threshold\n register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LT": {
+ "description": "Analog watchdog lower\n threshold",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "SQR1": {
+ "description": "regular sequence register 1",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "L": {
+ "description": "Regular channel sequence\n length",
+ "offset": 20,
+ "size": 4
+ },
+ "SQ16": {
+ "description": "16th conversion in regular\n sequence",
+ "offset": 15,
+ "size": 5
+ },
+ "SQ15": {
+ "description": "15th conversion in regular\n sequence",
+ "offset": 10,
+ "size": 5
+ },
+ "SQ14": {
+ "description": "14th conversion in regular\n sequence",
+ "offset": 5,
+ "size": 5
+ },
+ "SQ13": {
+ "description": "13th conversion in regular\n sequence",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "SQR2": {
+ "description": "regular sequence register 2",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SQ12": {
+ "description": "12th conversion in regular\n sequence",
+ "offset": 25,
+ "size": 5
+ },
+ "SQ11": {
+ "description": "11th conversion in regular\n sequence",
+ "offset": 20,
+ "size": 5
+ },
+ "SQ10": {
+ "description": "10th conversion in regular\n sequence",
+ "offset": 15,
+ "size": 5
+ },
+ "SQ9": {
+ "description": "9th conversion in regular\n sequence",
+ "offset": 10,
+ "size": 5
+ },
+ "SQ8": {
+ "description": "8th conversion in regular\n sequence",
+ "offset": 5,
+ "size": 5
+ },
+ "SQ7": {
+ "description": "7th conversion in regular\n sequence",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "SQR3": {
+ "description": "regular sequence register 3",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SQ6": {
+ "description": "6th conversion in regular\n sequence",
+ "offset": 25,
+ "size": 5
+ },
+ "SQ5": {
+ "description": "5th conversion in regular\n sequence",
+ "offset": 20,
+ "size": 5
+ },
+ "SQ4": {
+ "description": "4th conversion in regular\n sequence",
+ "offset": 15,
+ "size": 5
+ },
+ "SQ3": {
+ "description": "3rd conversion in regular\n sequence",
+ "offset": 10,
+ "size": 5
+ },
+ "SQ2": {
+ "description": "2nd conversion in regular\n sequence",
+ "offset": 5,
+ "size": 5
+ },
+ "SQ1": {
+ "description": "1st conversion in regular\n sequence",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "JSQR": {
+ "description": "injected sequence register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "JL": {
+ "description": "Injected sequence length",
+ "offset": 20,
+ "size": 2
+ },
+ "JSQ4": {
+ "description": "4th conversion in injected\n sequence",
+ "offset": 15,
+ "size": 5
+ },
+ "JSQ3": {
+ "description": "3rd conversion in injected\n sequence",
+ "offset": 10,
+ "size": 5
+ },
+ "JSQ2": {
+ "description": "2nd conversion in injected\n sequence",
+ "offset": 5,
+ "size": 5
+ },
+ "JSQ1": {
+ "description": "1st conversion in injected\n sequence",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "JDR1": {
+ "description": "injected data register x",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "JDATA": {
+ "description": "Injected data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "JDR2": {
+ "description": "injected data register x",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "JDATA": {
+ "description": "Injected data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "JDR3": {
+ "description": "injected data register x",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "JDATA": {
+ "description": "Injected data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "JDR4": {
+ "description": "injected data register x",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "JDATA": {
+ "description": "Injected data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR": {
+ "description": "regular data register",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DATA": {
+ "description": "Regular data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "CAN1": {
+ "description": "Controller area network",
+ "children": {
+ "registers": {
+ "CAN_MCR": {
+ "description": "CAN_MCR",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBF": {
+ "description": "DBF",
+ "offset": 16,
+ "size": 1
+ },
+ "RESET": {
+ "description": "RESET",
+ "offset": 15,
+ "size": 1
+ },
+ "TTCM": {
+ "description": "TTCM",
+ "offset": 7,
+ "size": 1
+ },
+ "ABOM": {
+ "description": "ABOM",
+ "offset": 6,
+ "size": 1
+ },
+ "AWUM": {
+ "description": "AWUM",
+ "offset": 5,
+ "size": 1
+ },
+ "NART": {
+ "description": "NART",
+ "offset": 4,
+ "size": 1
+ },
+ "RFLM": {
+ "description": "RFLM",
+ "offset": 3,
+ "size": 1
+ },
+ "TXFP": {
+ "description": "TXFP",
+ "offset": 2,
+ "size": 1
+ },
+ "SLEEP": {
+ "description": "SLEEP",
+ "offset": 1,
+ "size": 1
+ },
+ "INRQ": {
+ "description": "INRQ",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CAN_MSR": {
+ "description": "CAN_MSR",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RX": {
+ "description": "RX",
+ "offset": 11,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SAMP": {
+ "description": "SAMP",
+ "offset": 10,
+ "size": 1,
+ "access": "read-only"
+ },
+ "RXM": {
+ "description": "RXM",
+ "offset": 9,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TXM": {
+ "description": "TXM",
+ "offset": 8,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SLAKI": {
+ "description": "SLAKI",
+ "offset": 4,
+ "size": 1
+ },
+ "WKUI": {
+ "description": "WKUI",
+ "offset": 3,
+ "size": 1
+ },
+ "ERRI": {
+ "description": "ERRI",
+ "offset": 2,
+ "size": 1
+ },
+ "SLAK": {
+ "description": "SLAK",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "INAK": {
+ "description": "INAK",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "CAN_TSR": {
+ "description": "CAN_TSR",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LOW2": {
+ "description": "Lowest priority flag for mailbox\n 2",
+ "offset": 31,
+ "size": 1,
+ "access": "read-only"
+ },
+ "LOW1": {
+ "description": "Lowest priority flag for mailbox\n 1",
+ "offset": 30,
+ "size": 1,
+ "access": "read-only"
+ },
+ "LOW0": {
+ "description": "Lowest priority flag for mailbox\n 0",
+ "offset": 29,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TME2": {
+ "description": "Lowest priority flag for mailbox\n 2",
+ "offset": 28,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TME1": {
+ "description": "Lowest priority flag for mailbox\n 1",
+ "offset": 27,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TME0": {
+ "description": "Lowest priority flag for mailbox\n 0",
+ "offset": 26,
+ "size": 1,
+ "access": "read-only"
+ },
+ "CODE": {
+ "description": "CODE",
+ "offset": 24,
+ "size": 2,
+ "access": "read-only"
+ },
+ "ABRQ2": {
+ "description": "ABRQ2",
+ "offset": 23,
+ "size": 1
+ },
+ "TERR2": {
+ "description": "TERR2",
+ "offset": 19,
+ "size": 1
+ },
+ "ALST2": {
+ "description": "ALST2",
+ "offset": 18,
+ "size": 1
+ },
+ "TXOK2": {
+ "description": "TXOK2",
+ "offset": 17,
+ "size": 1
+ },
+ "RQCP2": {
+ "description": "RQCP2",
+ "offset": 16,
+ "size": 1
+ },
+ "ABRQ1": {
+ "description": "ABRQ1",
+ "offset": 15,
+ "size": 1
+ },
+ "TERR1": {
+ "description": "TERR1",
+ "offset": 11,
+ "size": 1
+ },
+ "ALST1": {
+ "description": "ALST1",
+ "offset": 10,
+ "size": 1
+ },
+ "TXOK1": {
+ "description": "TXOK1",
+ "offset": 9,
+ "size": 1
+ },
+ "RQCP1": {
+ "description": "RQCP1",
+ "offset": 8,
+ "size": 1
+ },
+ "ABRQ0": {
+ "description": "ABRQ0",
+ "offset": 7,
+ "size": 1
+ },
+ "TERR0": {
+ "description": "TERR0",
+ "offset": 3,
+ "size": 1
+ },
+ "ALST0": {
+ "description": "ALST0",
+ "offset": 2,
+ "size": 1
+ },
+ "TXOK0": {
+ "description": "TXOK0",
+ "offset": 1,
+ "size": 1
+ },
+ "RQCP0": {
+ "description": "RQCP0",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CAN_RF0R": {
+ "description": "CAN_RF0R",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RFOM0": {
+ "description": "RFOM0",
+ "offset": 5,
+ "size": 1
+ },
+ "FOVR0": {
+ "description": "FOVR0",
+ "offset": 4,
+ "size": 1
+ },
+ "FULL0": {
+ "description": "FULL0",
+ "offset": 3,
+ "size": 1
+ },
+ "FMP0": {
+ "description": "FMP0",
+ "offset": 0,
+ "size": 2,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "CAN_RF1R": {
+ "description": "CAN_RF1R",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RFOM1": {
+ "description": "RFOM1",
+ "offset": 5,
+ "size": 1
+ },
+ "FOVR1": {
+ "description": "FOVR1",
+ "offset": 4,
+ "size": 1
+ },
+ "FULL1": {
+ "description": "FULL1",
+ "offset": 3,
+ "size": 1
+ },
+ "FMP1": {
+ "description": "FMP1",
+ "offset": 0,
+ "size": 2,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "CAN_IER": {
+ "description": "CAN_IER",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SLKIE": {
+ "description": "SLKIE",
+ "offset": 17,
+ "size": 1
+ },
+ "WKUIE": {
+ "description": "WKUIE",
+ "offset": 16,
+ "size": 1
+ },
+ "ERRIE": {
+ "description": "ERRIE",
+ "offset": 15,
+ "size": 1
+ },
+ "LECIE": {
+ "description": "LECIE",
+ "offset": 11,
+ "size": 1
+ },
+ "BOFIE": {
+ "description": "BOFIE",
+ "offset": 10,
+ "size": 1
+ },
+ "EPVIE": {
+ "description": "EPVIE",
+ "offset": 9,
+ "size": 1
+ },
+ "EWGIE": {
+ "description": "EWGIE",
+ "offset": 8,
+ "size": 1
+ },
+ "FOVIE1": {
+ "description": "FOVIE1",
+ "offset": 6,
+ "size": 1
+ },
+ "FFIE1": {
+ "description": "FFIE1",
+ "offset": 5,
+ "size": 1
+ },
+ "FMPIE1": {
+ "description": "FMPIE1",
+ "offset": 4,
+ "size": 1
+ },
+ "FOVIE0": {
+ "description": "FOVIE0",
+ "offset": 3,
+ "size": 1
+ },
+ "FFIE0": {
+ "description": "FFIE0",
+ "offset": 2,
+ "size": 1
+ },
+ "FMPIE0": {
+ "description": "FMPIE0",
+ "offset": 1,
+ "size": 1
+ },
+ "TMEIE": {
+ "description": "TMEIE",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CAN_ESR": {
+ "description": "CAN_ESR",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "REC": {
+ "description": "REC",
+ "offset": 24,
+ "size": 8,
+ "access": "read-only"
+ },
+ "TEC": {
+ "description": "TEC",
+ "offset": 16,
+ "size": 8,
+ "access": "read-only"
+ },
+ "LEC": {
+ "description": "LEC",
+ "offset": 4,
+ "size": 3
+ },
+ "BOFF": {
+ "description": "BOFF",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPVF": {
+ "description": "EPVF",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EWGF": {
+ "description": "EWGF",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "CAN_BTR": {
+ "description": "CAN_BTR",
+ "offset": 28,
+ "size": 32,
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+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F0R2": {
+ "description": "Filter bank 0 register 2",
+ "offset": 580,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F1R1": {
+ "description": "Filter bank 1 register 1",
+ "offset": 584,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F1R2": {
+ "description": "Filter bank 1 register 2",
+ "offset": 588,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F2R1": {
+ "description": "Filter bank 2 register 1",
+ "offset": 592,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F2R2": {
+ "description": "Filter bank 2 register 2",
+ "offset": 596,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F3R1": {
+ "description": "Filter bank 3 register 1",
+ "offset": 600,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F3R2": {
+ "description": "Filter bank 3 register 2",
+ "offset": 604,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F4R1": {
+ "description": "Filter bank 4 register 1",
+ "offset": 608,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F4R2": {
+ "description": "Filter bank 4 register 2",
+ "offset": 612,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F5R1": {
+ "description": "Filter bank 5 register 1",
+ "offset": 616,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F5R2": {
+ "description": "Filter bank 5 register 2",
+ "offset": 620,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F6R1": {
+ "description": "Filter bank 6 register 1",
+ "offset": 624,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F6R2": {
+ "description": "Filter bank 6 register 2",
+ "offset": 628,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F7R1": {
+ "description": "Filter bank 7 register 1",
+ "offset": 632,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F7R2": {
+ "description": "Filter bank 7 register 2",
+ "offset": 636,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F8R1": {
+ "description": "Filter bank 8 register 1",
+ "offset": 640,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F8R2": {
+ "description": "Filter bank 8 register 2",
+ "offset": 644,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F9R1": {
+ "description": "Filter bank 9 register 1",
+ "offset": 648,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F9R2": {
+ "description": "Filter bank 9 register 2",
+ "offset": 652,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F10R1": {
+ "description": "Filter bank 10 register 1",
+ "offset": 656,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F10R2": {
+ "description": "Filter bank 10 register 2",
+ "offset": 660,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F11R1": {
+ "description": "Filter bank 11 register 1",
+ "offset": 664,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F11R2": {
+ "description": "Filter bank 11 register 2",
+ "offset": 668,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F12R1": {
+ "description": "Filter bank 4 register 1",
+ "offset": 672,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F12R2": {
+ "description": "Filter bank 12 register 2",
+ "offset": 676,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F13R1": {
+ "description": "Filter bank 13 register 1",
+ "offset": 680,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F13R2": {
+ "description": "Filter bank 13 register 2",
+ "offset": 684,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "devices": {
+ "STM32F103": {
+ "arch": "cortex_m3",
+ "description": "STM32F103",
+ "properties": {
+ "cpu.nvic_prio_bits": "4",
+ "cpu.mpu": "false",
+ "cpu.fpu": "false",
+ "cpu.revision": "r1p1",
+ "cpu.vendor_systick_config": "false",
+ "cpu.endian": "little",
+ "cpu.name": "CM3"
+ },
+ "children": {
+ "interrupts": {
+ "MemManageFault": {
+ "index": -12
+ },
+ "BusFault": {
+ "index": -11
+ },
+ "UsageFault": {
+ "index": -10
+ },
+ "DebugMonitor": {
+ "index": -4
+ },
+ "NMI": {
+ "index": -14
+ },
+ "HardFault": {
+ "index": -13
+ },
+ "SVCall": {
+ "index": -5
+ },
+ "PendSV": {
+ "index": -2
+ },
+ "SysTick": {
+ "index": -1
+ },
+ "FSMC": {
+ "index": 48,
+ "description": "FSMC global interrupt"
+ },
+ "PVD": {
+ "index": 1,
+ "description": "PVD through EXTI line detection\n interrupt"
+ },
+ "RCC": {
+ "index": 5,
+ "description": "RCC global interrupt"
+ },
+ "TAMPER": {
+ "index": 2,
+ "description": "Tamper interrupt"
+ },
+ "DMA1_Channel1": {
+ "index": 11,
+ "description": "DMA1 Channel1 global interrupt"
+ },
+ "DMA2_Channel1": {
+ "index": 56,
+ "description": "DMA2 Channel1 global interrupt"
+ },
+ "SDIO": {
+ "index": 49,
+ "description": "SDIO global interrupt"
+ },
+ "RTC": {
+ "index": 3,
+ "description": "RTC global interrupt"
+ },
+ "WWDG": {
+ "index": 0,
+ "description": "Window Watchdog interrupt"
+ },
+ "TIM1_BRK": {
+ "index": 24,
+ "description": "TIM1 Break interrupt"
+ },
+ "TIM8_BRK": {
+ "index": 43,
+ "description": "TIM8 Break interrupt"
+ },
+ "TIM2": {
+ "index": 28,
+ "description": "TIM2 global interrupt"
+ },
+ "TIM3": {
+ "index": 29,
+ "description": "TIM3 global interrupt"
+ },
+ "TIM4": {
+ "index": 30,
+ "description": "TIM4 global interrupt"
+ },
+ "TIM5": {
+ "index": 50,
+ "description": "TIM5 global interrupt"
+ },
+ "TIM1_UP": {
+ "index": 25,
+ "description": "TIM1 Update interrupt"
+ },
+ "TIM1_TRG_COM": {
+ "index": 26,
+ "description": "TIM1 Trigger and Commutation\n interrupts"
+ },
+ "TIM6": {
+ "index": 54,
+ "description": "TIM6 global interrupt"
+ },
+ "TIM7": {
+ "index": 55,
+ "description": "TIM7 global interrupt"
+ },
+ "I2C1_EV": {
+ "index": 31,
+ "description": "I2C1 event interrupt"
+ },
+ "I2C2_EV": {
+ "index": 33,
+ "description": "I2C2 event interrupt"
+ },
+ "SPI1": {
+ "index": 35,
+ "description": "SPI1 global interrupt"
+ },
+ "SPI2": {
+ "index": 36,
+ "description": "SPI2 global interrupt"
+ },
+ "SPI3": {
+ "index": 51,
+ "description": "SPI3 global interrupt"
+ },
+ "USART1": {
+ "index": 37,
+ "description": "USART1 global interrupt"
+ },
+ "USART2": {
+ "index": 38,
+ "description": "USART2 global interrupt"
+ },
+ "USART3": {
+ "index": 39,
+ "description": "USART3 global interrupt"
+ },
+ "ADC1_2": {
+ "index": 18,
+ "description": "ADC1 and ADC2 global interrupt"
+ },
+ "ADC3": {
+ "index": 47,
+ "description": "ADC3 global interrupt"
+ },
+ "CAN_RX1": {
+ "index": 21,
+ "description": "CAN RX1 interrupt"
+ },
+ "UART4": {
+ "index": 52,
+ "description": "UART4 global interrupt"
+ },
+ "UART5": {
+ "index": 53,
+ "description": "UART5 global interrupt"
+ },
+ "FLASH": {
+ "index": 4,
+ "description": "Flash global interrupt"
+ },
+ "USB_HP_CAN_TX": {
+ "index": 19,
+ "description": "USB High Priority or CAN TX\n interrupts"
+ }
+ },
+ "peripheral_instances": {
+ "FSMC": {
+ "description": "Flexible static memory controller",
+ "offset": 2684354560,
+ "type": "types.peripherals.FSMC"
+ },
+ "PWR": {
+ "description": "Power control",
+ "offset": 1073770496,
+ "type": "types.peripherals.PWR"
+ },
+ "RCC": {
+ "description": "Reset and clock control",
+ "offset": 1073876992,
+ "type": "types.peripherals.RCC"
+ },
+ "GPIOA": {
+ "description": "General purpose I/O",
+ "offset": 1073809408,
+ "type": "types.peripherals.GPIOA"
+ },
+ "GPIOB": {
+ "offset": 1073810432,
+ "type": "types.peripherals.GPIOA"
+ },
+ "GPIOC": {
+ "offset": 1073811456,
+ "type": "types.peripherals.GPIOA"
+ },
+ "GPIOD": {
+ "offset": 1073812480,
+ "type": "types.peripherals.GPIOA"
+ },
+ "GPIOE": {
+ "offset": 1073813504,
+ "type": "types.peripherals.GPIOA"
+ },
+ "GPIOF": {
+ "offset": 1073814528,
+ "type": "types.peripherals.GPIOA"
+ },
+ "GPIOG": {
+ "offset": 1073815552,
+ "type": "types.peripherals.GPIOA"
+ },
+ "AFIO": {
+ "description": "Alternate function I/O",
+ "offset": 1073807360,
+ "type": "types.peripherals.AFIO"
+ },
+ "EXTI": {
+ "description": "EXTI",
+ "offset": 1073808384,
+ "type": "types.peripherals.EXTI"
+ },
+ "DMA1": {
+ "description": "DMA controller",
+ "offset": 1073872896,
+ "type": "types.peripherals.DMA1"
+ },
+ "DMA2": {
+ "offset": 1073873920,
+ "type": "types.peripherals.DMA1"
+ },
+ "SDIO": {
+ "description": "Secure digital input/output\n interface",
+ "offset": 1073840128,
+ "type": "types.peripherals.SDIO"
+ },
+ "RTC": {
+ "description": "Real time clock",
+ "offset": 1073752064,
+ "type": "types.peripherals.RTC"
+ },
+ "BKP": {
+ "description": "Backup registers",
+ "offset": 1073769472,
+ "type": "types.peripherals.BKP"
+ },
+ "IWDG": {
+ "description": "Independent watchdog",
+ "offset": 1073754112,
+ "type": "types.peripherals.IWDG"
+ },
+ "WWDG": {
+ "description": "Window watchdog",
+ "offset": 1073753088,
+ "type": "types.peripherals.WWDG"
+ },
+ "TIM1": {
+ "description": "Advanced timer",
+ "offset": 1073818624,
+ "type": "types.peripherals.TIM1"
+ },
+ "TIM8": {
+ "offset": 1073820672,
+ "type": "types.peripherals.TIM1"
+ },
+ "TIM2": {
+ "description": "General purpose timer",
+ "offset": 1073741824,
+ "type": "types.peripherals.TIM2"
+ },
+ "TIM3": {
+ "offset": 1073742848,
+ "type": "types.peripherals.TIM2"
+ },
+ "TIM4": {
+ "offset": 1073743872,
+ "type": "types.peripherals.TIM2"
+ },
+ "TIM5": {
+ "offset": 1073744896,
+ "type": "types.peripherals.TIM2"
+ },
+ "TIM9": {
+ "description": "General purpose timer",
+ "offset": 1073826816,
+ "type": "types.peripherals.TIM9"
+ },
+ "TIM12": {
+ "offset": 1073747968,
+ "type": "types.peripherals.TIM9"
+ },
+ "TIM10": {
+ "description": "General purpose timer",
+ "offset": 1073827840,
+ "type": "types.peripherals.TIM10"
+ },
+ "TIM11": {
+ "offset": 1073828864,
+ "type": "types.peripherals.TIM10"
+ },
+ "TIM13": {
+ "offset": 1073748992,
+ "type": "types.peripherals.TIM10"
+ },
+ "TIM14": {
+ "offset": 1073750016,
+ "type": "types.peripherals.TIM10"
+ },
+ "TIM6": {
+ "description": "Basic timer",
+ "offset": 1073745920,
+ "type": "types.peripherals.TIM6"
+ },
+ "TIM7": {
+ "offset": 1073746944,
+ "type": "types.peripherals.TIM6"
+ },
+ "I2C1": {
+ "description": "Inter integrated circuit",
+ "offset": 1073763328,
+ "type": "types.peripherals.I2C1"
+ },
+ "I2C2": {
+ "offset": 1073764352,
+ "type": "types.peripherals.I2C1"
+ },
+ "SPI1": {
+ "description": "Serial peripheral interface",
+ "offset": 1073819648,
+ "type": "types.peripherals.SPI1"
+ },
+ "SPI2": {
+ "offset": 1073756160,
+ "type": "types.peripherals.SPI1"
+ },
+ "SPI3": {
+ "offset": 1073757184,
+ "type": "types.peripherals.SPI1"
+ },
+ "USART1": {
+ "description": "Universal synchronous asynchronous receiver\n transmitter",
+ "offset": 1073821696,
+ "type": "types.peripherals.USART1"
+ },
+ "USART2": {
+ "offset": 1073759232,
+ "type": "types.peripherals.USART1"
+ },
+ "USART3": {
+ "offset": 1073760256,
+ "type": "types.peripherals.USART1"
+ },
+ "ADC1": {
+ "description": "Analog to digital converter",
+ "offset": 1073816576,
+ "type": "types.peripherals.ADC1"
+ },
+ "ADC2": {
+ "description": "Analog to digital converter",
+ "offset": 1073817600,
+ "type": "types.peripherals.ADC2"
+ },
+ "ADC3": {
+ "offset": 1073822720,
+ "type": "types.peripherals.ADC2"
+ },
+ "CAN1": {
+ "description": "Controller area network",
+ "offset": 1073767424,
+ "type": "types.peripherals.CAN1"
+ },
+ "CAN2": {
+ "offset": 1073768448,
+ "type": "types.peripherals.CAN1"
+ },
+ "DAC": {
+ "description": "Digital to analog converter",
+ "offset": 1073771520,
+ "type": "types.peripherals.DAC"
+ },
+ "DBG": {
+ "description": "Debug support",
+ "offset": 3758366720,
+ "type": "types.peripherals.DBG"
+ },
+ "UART4": {
+ "description": "Universal asynchronous receiver\n transmitter",
+ "offset": 1073761280,
+ "type": "types.peripherals.UART4"
+ },
+ "UART5": {
+ "description": "Universal asynchronous receiver\n transmitter",
+ "offset": 1073762304,
+ "type": "types.peripherals.UART5"
+ },
+ "CRC": {
+ "description": "CRC calculation unit",
+ "offset": 1073885184,
+ "type": "types.peripherals.CRC"
+ },
+ "FLASH": {
+ "description": "FLASH",
+ "offset": 1073881088,
+ "type": "types.peripherals.FLASH"
+ },
+ "USB": {
+ "description": "Universal serial bus full-speed device\n interface",
+ "offset": 1073765376,
+ "type": "types.peripherals.USB"
+ },
+ "OTG_FS_DEVICE": {
+ "description": "USB on the go full speed",
+ "offset": 1342179328,
+ "type": "types.peripherals.OTG_FS_DEVICE"
+ },
+ "OTG_FS_GLOBAL": {
+ "description": "USB on the go full speed",
+ "offset": 1342177280,
+ "type": "types.peripherals.OTG_FS_GLOBAL"
+ },
+ "OTG_FS_HOST": {
+ "description": "USB on the go full speed",
+ "offset": 1342178304,
+ "type": "types.peripherals.OTG_FS_HOST"
+ },
+ "OTG_FS_PWRCLK": {
+ "description": "USB on the go full speed",
+ "offset": 1342180864,
+ "type": "types.peripherals.OTG_FS_PWRCLK"
+ },
+ "ETHERNET_MMC": {
+ "description": "Ethernet: MAC management counters",
+ "offset": 1073905920,
+ "type": "types.peripherals.ETHERNET_MMC"
+ },
+ "ETHERNET_MAC": {
+ "description": "Ethernet: media access control",
+ "offset": 1073905664,
+ "type": "types.peripherals.ETHERNET_MAC"
+ },
+ "ETHERNET_PTP": {
+ "description": "Ethernet: Precision time protocol",
+ "offset": 1073907456,
+ "type": "types.peripherals.ETHERNET_PTP"
+ },
+ "ETHERNET_DMA": {
+ "description": "Ethernet: DMA controller operation",
+ "offset": 1073909760,
+ "type": "types.peripherals.ETHERNET_DMA"
+ },
+ "NVIC": {
+ "description": "Nested Vectored Interrupt\n Controller",
+ "offset": 3758153984,
+ "type": "types.peripherals.NVIC"
+ },
+ "MPU": {
+ "description": "Memory protection unit",
+ "offset": 3758157200,
+ "type": "types.peripherals.MPU"
+ },
+ "SCB_ACTRL": {
+ "description": "System control block ACTLR",
+ "offset": 3758153736,
+ "type": "types.peripherals.SCB_ACTRL"
+ },
+ "NVIC_STIR": {
+ "description": "Nested vectored interrupt\n controller",
+ "offset": 3758157568,
+ "type": "types.peripherals.NVIC_STIR"
+ },
+ "SCB": {
+ "description": "System control block",
+ "offset": 3758157056,
+ "type": "types.peripherals.SCB"
+ },
+ "STK": {
+ "description": "SysTick timer",
+ "offset": 3758153744,
+ "type": "types.peripherals.STK"
+ }
+ }
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/board-support/stmicro-stm32/src/chips/STM32F303.json b/board-support/stmicro-stm32/src/chips/STM32F303.json
new file mode 100644
index 0000000..6468498
--- /dev/null
+++ b/board-support/stmicro-stm32/src/chips/STM32F303.json
@@ -0,0 +1,33184 @@
+{
+ "version": "0.1.0",
+ "types": {
+ "peripherals": {
+ "GPIOA": {
+ "description": "General-purpose I/Os",
+ "children": {
+ "registers": {
+ "MODER": {
+ "description": "GPIO port mode register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 671088640,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MODER15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 30,
+ "size": 2
+ },
+ "MODER14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 28,
+ "size": 2
+ },
+ "MODER13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 26,
+ "size": 2
+ },
+ "MODER12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 24,
+ "size": 2
+ },
+ "MODER11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 22,
+ "size": 2
+ },
+ "MODER10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 20,
+ "size": 2
+ },
+ "MODER9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 18,
+ "size": 2
+ },
+ "MODER8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 16,
+ "size": 2
+ },
+ "MODER7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 2
+ },
+ "MODER6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 2
+ },
+ "MODER5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 2
+ },
+ "MODER4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 2
+ },
+ "MODER3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 2
+ },
+ "MODER2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 2
+ },
+ "MODER1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 2
+ },
+ "MODER0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTYPER": {
+ "description": "GPIO port output type register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OT15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "OT14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "OT13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "OT12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "OT11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "OT10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "OT9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "OT8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "OT7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "OT6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "OT5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "OT4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "OT3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "OT2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "OT1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "OT0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OSPEEDR": {
+ "description": "GPIO port output speed\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OSPEEDR15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 30,
+ "size": 2
+ },
+ "OSPEEDR14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 28,
+ "size": 2
+ },
+ "OSPEEDR13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 26,
+ "size": 2
+ },
+ "OSPEEDR12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 24,
+ "size": 2
+ },
+ "OSPEEDR11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 22,
+ "size": 2
+ },
+ "OSPEEDR10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 20,
+ "size": 2
+ },
+ "OSPEEDR9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 18,
+ "size": 2
+ },
+ "OSPEEDR8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 16,
+ "size": 2
+ },
+ "OSPEEDR7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 2
+ },
+ "OSPEEDR6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 2
+ },
+ "OSPEEDR5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 2
+ },
+ "OSPEEDR4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 2
+ },
+ "OSPEEDR3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 2
+ },
+ "OSPEEDR2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 2
+ },
+ "OSPEEDR1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 2
+ },
+ "OSPEEDR0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "PUPDR": {
+ "description": "GPIO port pull-up/pull-down\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 603979776,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PUPDR15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 30,
+ "size": 2
+ },
+ "PUPDR14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 28,
+ "size": 2
+ },
+ "PUPDR13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 26,
+ "size": 2
+ },
+ "PUPDR12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 24,
+ "size": 2
+ },
+ "PUPDR11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 22,
+ "size": 2
+ },
+ "PUPDR10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 20,
+ "size": 2
+ },
+ "PUPDR9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 18,
+ "size": 2
+ },
+ "PUPDR8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 16,
+ "size": 2
+ },
+ "PUPDR7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 2
+ },
+ "PUPDR6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 2
+ },
+ "PUPDR5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 2
+ },
+ "PUPDR4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 2
+ },
+ "PUPDR3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 2
+ },
+ "PUPDR2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 2
+ },
+ "PUPDR1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 2
+ },
+ "PUPDR0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "IDR": {
+ "description": "GPIO port input data register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "IDR15": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "IDR14": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "IDR13": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "IDR12": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "IDR11": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "IDR10": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "IDR9": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "IDR8": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "IDR7": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "IDR6": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "IDR5": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "IDR4": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "IDR3": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "IDR2": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "IDR1": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "IDR0": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ODR": {
+ "description": "GPIO port output data register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ODR15": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "ODR14": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "ODR13": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "ODR12": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "ODR11": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "ODR10": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "ODR9": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "ODR8": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "ODR7": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "ODR6": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "ODR5": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "ODR4": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "ODR3": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "ODR2": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "ODR1": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "ODR0": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BSRR": {
+ "description": "GPIO port bit set/reset\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "BR15": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 31,
+ "size": 1
+ },
+ "BR14": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 30,
+ "size": 1
+ },
+ "BR13": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 29,
+ "size": 1
+ },
+ "BR12": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 28,
+ "size": 1
+ },
+ "BR11": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 27,
+ "size": 1
+ },
+ "BR10": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 26,
+ "size": 1
+ },
+ "BR9": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 25,
+ "size": 1
+ },
+ "BR8": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 24,
+ "size": 1
+ },
+ "BR7": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 23,
+ "size": 1
+ },
+ "BR6": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 22,
+ "size": 1
+ },
+ "BR5": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 21,
+ "size": 1
+ },
+ "BR4": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 20,
+ "size": 1
+ },
+ "BR3": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 19,
+ "size": 1
+ },
+ "BR2": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 18,
+ "size": 1
+ },
+ "BR1": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 17,
+ "size": 1
+ },
+ "BR0": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 16,
+ "size": 1
+ },
+ "BS15": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "BS14": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "BS13": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "BS12": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "BS11": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "BS10": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "BS9": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "BS8": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "BS7": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "BS6": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "BS5": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "BS4": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "BS3": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "BS2": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "BS1": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "BS0": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "LCKR": {
+ "description": "GPIO port configuration lock\n register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LCKK": {
+ "description": "Lok Key",
+ "offset": 16,
+ "size": 1
+ },
+ "LCK15": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "LCK14": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "LCK13": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "LCK12": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "LCK11": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "LCK10": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "LCK9": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "LCK8": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "LCK7": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "LCK6": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "LCK5": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "LCK4": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "LCK3": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "LCK2": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "LCK1": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "LCK0": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "AFRL": {
+ "description": "GPIO alternate function low\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "AFRL7": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 28,
+ "size": 4
+ },
+ "AFRL6": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 24,
+ "size": 4
+ },
+ "AFRL5": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 20,
+ "size": 4
+ },
+ "AFRL4": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 16,
+ "size": 4
+ },
+ "AFRL3": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 12,
+ "size": 4
+ },
+ "AFRL2": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 8,
+ "size": 4
+ },
+ "AFRL1": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 4,
+ "size": 4
+ },
+ "AFRL0": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "AFRH": {
+ "description": "GPIO alternate function high\n register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "AFRH15": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 28,
+ "size": 4
+ },
+ "AFRH14": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 24,
+ "size": 4
+ },
+ "AFRH13": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 20,
+ "size": 4
+ },
+ "AFRH12": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 16,
+ "size": 4
+ },
+ "AFRH11": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 12,
+ "size": 4
+ },
+ "AFRH10": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 8,
+ "size": 4
+ },
+ "AFRH9": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 4,
+ "size": 4
+ },
+ "AFRH8": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "BRR": {
+ "description": "Port bit reset register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "BR0": {
+ "description": "Port x Reset bit y",
+ "offset": 0,
+ "size": 1
+ },
+ "BR1": {
+ "description": "Port x Reset bit y",
+ "offset": 1,
+ "size": 1
+ },
+ "BR2": {
+ "description": "Port x Reset bit y",
+ "offset": 2,
+ "size": 1
+ },
+ "BR3": {
+ "description": "Port x Reset bit y",
+ "offset": 3,
+ "size": 1
+ },
+ "BR4": {
+ "description": "Port x Reset bit y",
+ "offset": 4,
+ "size": 1
+ },
+ "BR5": {
+ "description": "Port x Reset bit y",
+ "offset": 5,
+ "size": 1
+ },
+ "BR6": {
+ "description": "Port x Reset bit y",
+ "offset": 6,
+ "size": 1
+ },
+ "BR7": {
+ "description": "Port x Reset bit y",
+ "offset": 7,
+ "size": 1
+ },
+ "BR8": {
+ "description": "Port x Reset bit y",
+ "offset": 8,
+ "size": 1
+ },
+ "BR9": {
+ "description": "Port x Reset bit y",
+ "offset": 9,
+ "size": 1
+ },
+ "BR10": {
+ "description": "Port x Reset bit y",
+ "offset": 10,
+ "size": 1
+ },
+ "BR11": {
+ "description": "Port x Reset bit y",
+ "offset": 11,
+ "size": 1
+ },
+ "BR12": {
+ "description": "Port x Reset bit y",
+ "offset": 12,
+ "size": 1
+ },
+ "BR13": {
+ "description": "Port x Reset bit y",
+ "offset": 13,
+ "size": 1
+ },
+ "BR14": {
+ "description": "Port x Reset bit y",
+ "offset": 14,
+ "size": 1
+ },
+ "BR15": {
+ "description": "Port x Reset bit y",
+ "offset": 15,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "GPIOB": {
+ "description": "General-purpose I/Os",
+ "children": {
+ "registers": {
+ "MODER": {
+ "description": "GPIO port mode register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MODER15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 30,
+ "size": 2
+ },
+ "MODER14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 28,
+ "size": 2
+ },
+ "MODER13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 26,
+ "size": 2
+ },
+ "MODER12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 24,
+ "size": 2
+ },
+ "MODER11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 22,
+ "size": 2
+ },
+ "MODER10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 20,
+ "size": 2
+ },
+ "MODER9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 18,
+ "size": 2
+ },
+ "MODER8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 16,
+ "size": 2
+ },
+ "MODER7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 2
+ },
+ "MODER6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 2
+ },
+ "MODER5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 2
+ },
+ "MODER4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 2
+ },
+ "MODER3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 2
+ },
+ "MODER2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 2
+ },
+ "MODER1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 2
+ },
+ "MODER0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTYPER": {
+ "description": "GPIO port output type register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OT15": {
+ "description": "Port x configuration bit\n 15",
+ "offset": 15,
+ "size": 1
+ },
+ "OT14": {
+ "description": "Port x configuration bit\n 14",
+ "offset": 14,
+ "size": 1
+ },
+ "OT13": {
+ "description": "Port x configuration bit\n 13",
+ "offset": 13,
+ "size": 1
+ },
+ "OT12": {
+ "description": "Port x configuration bit\n 12",
+ "offset": 12,
+ "size": 1
+ },
+ "OT11": {
+ "description": "Port x configuration bit\n 11",
+ "offset": 11,
+ "size": 1
+ },
+ "OT10": {
+ "description": "Port x configuration bit\n 10",
+ "offset": 10,
+ "size": 1
+ },
+ "OT9": {
+ "description": "Port x configuration bit 9",
+ "offset": 9,
+ "size": 1
+ },
+ "OT8": {
+ "description": "Port x configuration bit 8",
+ "offset": 8,
+ "size": 1
+ },
+ "OT7": {
+ "description": "Port x configuration bit 7",
+ "offset": 7,
+ "size": 1
+ },
+ "OT6": {
+ "description": "Port x configuration bit 6",
+ "offset": 6,
+ "size": 1
+ },
+ "OT5": {
+ "description": "Port x configuration bit 5",
+ "offset": 5,
+ "size": 1
+ },
+ "OT4": {
+ "description": "Port x configuration bit 4",
+ "offset": 4,
+ "size": 1
+ },
+ "OT3": {
+ "description": "Port x configuration bit 3",
+ "offset": 3,
+ "size": 1
+ },
+ "OT2": {
+ "description": "Port x configuration bit 2",
+ "offset": 2,
+ "size": 1
+ },
+ "OT1": {
+ "description": "Port x configuration bit 1",
+ "offset": 1,
+ "size": 1
+ },
+ "OT0": {
+ "description": "Port x configuration bit 0",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OSPEEDR": {
+ "description": "GPIO port output speed\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OSPEEDR15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 30,
+ "size": 2
+ },
+ "OSPEEDR14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 28,
+ "size": 2
+ },
+ "OSPEEDR13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 26,
+ "size": 2
+ },
+ "OSPEEDR12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 24,
+ "size": 2
+ },
+ "OSPEEDR11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 22,
+ "size": 2
+ },
+ "OSPEEDR10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 20,
+ "size": 2
+ },
+ "OSPEEDR9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 18,
+ "size": 2
+ },
+ "OSPEEDR8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 16,
+ "size": 2
+ },
+ "OSPEEDR7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 2
+ },
+ "OSPEEDR6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 2
+ },
+ "OSPEEDR5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 2
+ },
+ "OSPEEDR4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 2
+ },
+ "OSPEEDR3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 2
+ },
+ "OSPEEDR2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 2
+ },
+ "OSPEEDR1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 2
+ },
+ "OSPEEDR0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "PUPDR": {
+ "description": "GPIO port pull-up/pull-down\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PUPDR15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 30,
+ "size": 2
+ },
+ "PUPDR14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 28,
+ "size": 2
+ },
+ "PUPDR13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 26,
+ "size": 2
+ },
+ "PUPDR12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 24,
+ "size": 2
+ },
+ "PUPDR11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 22,
+ "size": 2
+ },
+ "PUPDR10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 20,
+ "size": 2
+ },
+ "PUPDR9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 18,
+ "size": 2
+ },
+ "PUPDR8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 16,
+ "size": 2
+ },
+ "PUPDR7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 2
+ },
+ "PUPDR6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 2
+ },
+ "PUPDR5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 2
+ },
+ "PUPDR4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 2
+ },
+ "PUPDR3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 2
+ },
+ "PUPDR2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 2
+ },
+ "PUPDR1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 2
+ },
+ "PUPDR0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "IDR": {
+ "description": "GPIO port input data register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "IDR15": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "IDR14": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "IDR13": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "IDR12": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "IDR11": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "IDR10": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "IDR9": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "IDR8": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "IDR7": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "IDR6": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "IDR5": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "IDR4": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "IDR3": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "IDR2": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "IDR1": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "IDR0": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ODR": {
+ "description": "GPIO port output data register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ODR15": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "ODR14": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "ODR13": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "ODR12": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "ODR11": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "ODR10": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "ODR9": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "ODR8": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "ODR7": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "ODR6": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "ODR5": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "ODR4": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "ODR3": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "ODR2": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "ODR1": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "ODR0": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BSRR": {
+ "description": "GPIO port bit set/reset\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "BR15": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 31,
+ "size": 1
+ },
+ "BR14": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 30,
+ "size": 1
+ },
+ "BR13": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 29,
+ "size": 1
+ },
+ "BR12": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 28,
+ "size": 1
+ },
+ "BR11": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 27,
+ "size": 1
+ },
+ "BR10": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 26,
+ "size": 1
+ },
+ "BR9": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 25,
+ "size": 1
+ },
+ "BR8": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 24,
+ "size": 1
+ },
+ "BR7": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 23,
+ "size": 1
+ },
+ "BR6": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 22,
+ "size": 1
+ },
+ "BR5": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 21,
+ "size": 1
+ },
+ "BR4": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 20,
+ "size": 1
+ },
+ "BR3": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 19,
+ "size": 1
+ },
+ "BR2": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 18,
+ "size": 1
+ },
+ "BR1": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 17,
+ "size": 1
+ },
+ "BR0": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 16,
+ "size": 1
+ },
+ "BS15": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "BS14": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "BS13": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "BS12": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "BS11": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "BS10": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "BS9": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "BS8": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "BS7": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "BS6": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "BS5": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "BS4": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "BS3": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "BS2": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "BS1": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "BS0": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "LCKR": {
+ "description": "GPIO port configuration lock\n register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LCKK": {
+ "description": "Lok Key",
+ "offset": 16,
+ "size": 1
+ },
+ "LCK15": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "LCK14": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "LCK13": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "LCK12": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "LCK11": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "LCK10": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "LCK9": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "LCK8": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "LCK7": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "LCK6": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "LCK5": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "LCK4": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "LCK3": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "LCK2": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "LCK1": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "LCK0": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "AFRL": {
+ "description": "GPIO alternate function low\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "AFRL7": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 28,
+ "size": 4
+ },
+ "AFRL6": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 24,
+ "size": 4
+ },
+ "AFRL5": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 20,
+ "size": 4
+ },
+ "AFRL4": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 16,
+ "size": 4
+ },
+ "AFRL3": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 12,
+ "size": 4
+ },
+ "AFRL2": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 8,
+ "size": 4
+ },
+ "AFRL1": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 4,
+ "size": 4
+ },
+ "AFRL0": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "AFRH": {
+ "description": "GPIO alternate function high\n register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "AFRH15": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 28,
+ "size": 4
+ },
+ "AFRH14": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 24,
+ "size": 4
+ },
+ "AFRH13": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 20,
+ "size": 4
+ },
+ "AFRH12": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 16,
+ "size": 4
+ },
+ "AFRH11": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 12,
+ "size": 4
+ },
+ "AFRH10": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 8,
+ "size": 4
+ },
+ "AFRH9": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 4,
+ "size": 4
+ },
+ "AFRH8": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "BRR": {
+ "description": "Port bit reset register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "BR0": {
+ "description": "Port x Reset bit y",
+ "offset": 0,
+ "size": 1
+ },
+ "BR1": {
+ "description": "Port x Reset bit y",
+ "offset": 1,
+ "size": 1
+ },
+ "BR2": {
+ "description": "Port x Reset bit y",
+ "offset": 2,
+ "size": 1
+ },
+ "BR3": {
+ "description": "Port x Reset bit y",
+ "offset": 3,
+ "size": 1
+ },
+ "BR4": {
+ "description": "Port x Reset bit y",
+ "offset": 4,
+ "size": 1
+ },
+ "BR5": {
+ "description": "Port x Reset bit y",
+ "offset": 5,
+ "size": 1
+ },
+ "BR6": {
+ "description": "Port x Reset bit y",
+ "offset": 6,
+ "size": 1
+ },
+ "BR7": {
+ "description": "Port x Reset bit y",
+ "offset": 7,
+ "size": 1
+ },
+ "BR8": {
+ "description": "Port x Reset bit y",
+ "offset": 8,
+ "size": 1
+ },
+ "BR9": {
+ "description": "Port x Reset bit y",
+ "offset": 9,
+ "size": 1
+ },
+ "BR10": {
+ "description": "Port x Reset bit y",
+ "offset": 10,
+ "size": 1
+ },
+ "BR11": {
+ "description": "Port x Reset bit y",
+ "offset": 11,
+ "size": 1
+ },
+ "BR12": {
+ "description": "Port x Reset bit y",
+ "offset": 12,
+ "size": 1
+ },
+ "BR13": {
+ "description": "Port x Reset bit y",
+ "offset": 13,
+ "size": 1
+ },
+ "BR14": {
+ "description": "Port x Reset bit y",
+ "offset": 14,
+ "size": 1
+ },
+ "BR15": {
+ "description": "Port x Reset bit y",
+ "offset": 15,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "SCB_ACTRL": {
+ "description": "System control block ACTLR",
+ "children": {
+ "registers": {
+ "ACTRL": {
+ "description": "Auxiliary control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DISMCYCINT": {
+ "description": "DISMCYCINT",
+ "offset": 0,
+ "size": 1
+ },
+ "DISDEFWBUF": {
+ "description": "DISDEFWBUF",
+ "offset": 1,
+ "size": 1
+ },
+ "DISFOLD": {
+ "description": "DISFOLD",
+ "offset": 2,
+ "size": 1
+ },
+ "DISFPCA": {
+ "description": "DISFPCA",
+ "offset": 8,
+ "size": 1
+ },
+ "DISOOFP": {
+ "description": "DISOOFP",
+ "offset": 9,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "FPU_CPACR": {
+ "description": "Floating point unit CPACR",
+ "children": {
+ "registers": {
+ "CPACR": {
+ "description": "Coprocessor access control\n register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CP": {
+ "description": "CP",
+ "offset": 20,
+ "size": 4
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "NVIC_STIR": {
+ "description": "Nested vectored interrupt\n controller",
+ "children": {
+ "registers": {
+ "STIR": {
+ "description": "Software trigger interrupt\n register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INTID": {
+ "description": "Software generated interrupt\n ID",
+ "offset": 0,
+ "size": 9
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "SCB": {
+ "description": "System control block",
+ "children": {
+ "registers": {
+ "CPUID": {
+ "description": "CPUID base register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 1091551809,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "Revision": {
+ "description": "Revision number",
+ "offset": 0,
+ "size": 4
+ },
+ "PartNo": {
+ "description": "Part number of the\n processor",
+ "offset": 4,
+ "size": 12
+ },
+ "Constant": {
+ "description": "Reads as 0xF",
+ "offset": 16,
+ "size": 4
+ },
+ "Variant": {
+ "description": "Variant number",
+ "offset": 20,
+ "size": 4
+ },
+ "Implementer": {
+ "description": "Implementer code",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "ICSR": {
+ "description": "Interrupt control and state\n register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "VECTACTIVE": {
+ "description": "Active vector",
+ "offset": 0,
+ "size": 9
+ },
+ "RETTOBASE": {
+ "description": "Return to base level",
+ "offset": 11,
+ "size": 1
+ },
+ "VECTPENDING": {
+ "description": "Pending vector",
+ "offset": 12,
+ "size": 7
+ },
+ "ISRPENDING": {
+ "description": "Interrupt pending flag",
+ "offset": 22,
+ "size": 1
+ },
+ "PENDSTCLR": {
+ "description": "SysTick exception clear-pending\n bit",
+ "offset": 25,
+ "size": 1
+ },
+ "PENDSTSET": {
+ "description": "SysTick exception set-pending\n bit",
+ "offset": 26,
+ "size": 1
+ },
+ "PENDSVCLR": {
+ "description": "PendSV clear-pending bit",
+ "offset": 27,
+ "size": 1
+ },
+ "PENDSVSET": {
+ "description": "PendSV set-pending bit",
+ "offset": 28,
+ "size": 1
+ },
+ "NMIPENDSET": {
+ "description": "NMI set-pending bit.",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "VTOR": {
+ "description": "Vector table offset register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TBLOFF": {
+ "description": "Vector table base offset\n field",
+ "offset": 9,
+ "size": 21
+ }
+ }
+ }
+ },
+ "AIRCR": {
+ "description": "Application interrupt and reset control\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "VECTRESET": {
+ "description": "VECTRESET",
+ "offset": 0,
+ "size": 1
+ },
+ "VECTCLRACTIVE": {
+ "description": "VECTCLRACTIVE",
+ "offset": 1,
+ "size": 1
+ },
+ "SYSRESETREQ": {
+ "description": "SYSRESETREQ",
+ "offset": 2,
+ "size": 1
+ },
+ "PRIGROUP": {
+ "description": "PRIGROUP",
+ "offset": 8,
+ "size": 3
+ },
+ "ENDIANESS": {
+ "description": "ENDIANESS",
+ "offset": 15,
+ "size": 1
+ },
+ "VECTKEYSTAT": {
+ "description": "Register key",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "SCR": {
+ "description": "System control register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SLEEPONEXIT": {
+ "description": "SLEEPONEXIT",
+ "offset": 1,
+ "size": 1
+ },
+ "SLEEPDEEP": {
+ "description": "SLEEPDEEP",
+ "offset": 2,
+ "size": 1
+ },
+ "SEVEONPEND": {
+ "description": "Send Event on Pending bit",
+ "offset": 4,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCR": {
+ "description": "Configuration and control\n register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NONBASETHRDENA": {
+ "description": "Configures how the processor enters\n Thread mode",
+ "offset": 0,
+ "size": 1
+ },
+ "USERSETMPEND": {
+ "description": "USERSETMPEND",
+ "offset": 1,
+ "size": 1
+ },
+ "UNALIGN__TRP": {
+ "description": "UNALIGN_ TRP",
+ "offset": 3,
+ "size": 1
+ },
+ "DIV_0_TRP": {
+ "description": "DIV_0_TRP",
+ "offset": 4,
+ "size": 1
+ },
+ "BFHFNMIGN": {
+ "description": "BFHFNMIGN",
+ "offset": 8,
+ "size": 1
+ },
+ "STKALIGN": {
+ "description": "STKALIGN",
+ "offset": 9,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SHPR1": {
+ "description": "System handler priority\n registers",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRI_4": {
+ "description": "Priority of system handler\n 4",
+ "offset": 0,
+ "size": 8
+ },
+ "PRI_5": {
+ "description": "Priority of system handler\n 5",
+ "offset": 8,
+ "size": 8
+ },
+ "PRI_6": {
+ "description": "Priority of system handler\n 6",
+ "offset": 16,
+ "size": 8
+ }
+ }
+ }
+ },
+ "SHPR2": {
+ "description": "System handler priority\n registers",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRI_11": {
+ "description": "Priority of system handler\n 11",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "SHPR3": {
+ "description": "System handler priority\n registers",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRI_14": {
+ "description": "Priority of system handler\n 14",
+ "offset": 16,
+ "size": 8
+ },
+ "PRI_15": {
+ "description": "Priority of system handler\n 15",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "SHCRS": {
+ "description": "System handler control and state\n register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MEMFAULTACT": {
+ "description": "Memory management fault exception active\n bit",
+ "offset": 0,
+ "size": 1
+ },
+ "BUSFAULTACT": {
+ "description": "Bus fault exception active\n bit",
+ "offset": 1,
+ "size": 1
+ },
+ "USGFAULTACT": {
+ "description": "Usage fault exception active\n bit",
+ "offset": 3,
+ "size": 1
+ },
+ "SVCALLACT": {
+ "description": "SVC call active bit",
+ "offset": 7,
+ "size": 1
+ },
+ "MONITORACT": {
+ "description": "Debug monitor active bit",
+ "offset": 8,
+ "size": 1
+ },
+ "PENDSVACT": {
+ "description": "PendSV exception active\n bit",
+ "offset": 10,
+ "size": 1
+ },
+ "SYSTICKACT": {
+ "description": "SysTick exception active\n bit",
+ "offset": 11,
+ "size": 1
+ },
+ "USGFAULTPENDED": {
+ "description": "Usage fault exception pending\n bit",
+ "offset": 12,
+ "size": 1
+ },
+ "MEMFAULTPENDED": {
+ "description": "Memory management fault exception\n pending bit",
+ "offset": 13,
+ "size": 1
+ },
+ "BUSFAULTPENDED": {
+ "description": "Bus fault exception pending\n bit",
+ "offset": 14,
+ "size": 1
+ },
+ "SVCALLPENDED": {
+ "description": "SVC call pending bit",
+ "offset": 15,
+ "size": 1
+ },
+ "MEMFAULTENA": {
+ "description": "Memory management fault enable\n bit",
+ "offset": 16,
+ "size": 1
+ },
+ "BUSFAULTENA": {
+ "description": "Bus fault enable bit",
+ "offset": 17,
+ "size": 1
+ },
+ "USGFAULTENA": {
+ "description": "Usage fault enable bit",
+ "offset": 18,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CFSR_UFSR_BFSR_MMFSR": {
+ "description": "Configurable fault status\n register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IACCVIOL": {
+ "description": "Instruction access violation\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "MUNSTKERR": {
+ "description": "Memory manager fault on unstacking for a\n return from exception",
+ "offset": 3,
+ "size": 1
+ },
+ "MSTKERR": {
+ "description": "Memory manager fault on stacking for\n exception entry.",
+ "offset": 4,
+ "size": 1
+ },
+ "MLSPERR": {
+ "description": "MLSPERR",
+ "offset": 5,
+ "size": 1
+ },
+ "MMARVALID": {
+ "description": "Memory Management Fault Address Register\n (MMAR) valid flag",
+ "offset": 7,
+ "size": 1
+ },
+ "IBUSERR": {
+ "description": "Instruction bus error",
+ "offset": 8,
+ "size": 1
+ },
+ "PRECISERR": {
+ "description": "Precise data bus error",
+ "offset": 9,
+ "size": 1
+ },
+ "IMPRECISERR": {
+ "description": "Imprecise data bus error",
+ "offset": 10,
+ "size": 1
+ },
+ "UNSTKERR": {
+ "description": "Bus fault on unstacking for a return\n from exception",
+ "offset": 11,
+ "size": 1
+ },
+ "STKERR": {
+ "description": "Bus fault on stacking for exception\n entry",
+ "offset": 12,
+ "size": 1
+ },
+ "LSPERR": {
+ "description": "Bus fault on floating-point lazy state\n preservation",
+ "offset": 13,
+ "size": 1
+ },
+ "BFARVALID": {
+ "description": "Bus Fault Address Register (BFAR) valid\n flag",
+ "offset": 15,
+ "size": 1
+ },
+ "UNDEFINSTR": {
+ "description": "Undefined instruction usage\n fault",
+ "offset": 16,
+ "size": 1
+ },
+ "INVSTATE": {
+ "description": "Invalid state usage fault",
+ "offset": 17,
+ "size": 1
+ },
+ "INVPC": {
+ "description": "Invalid PC load usage\n fault",
+ "offset": 18,
+ "size": 1
+ },
+ "NOCP": {
+ "description": "No coprocessor usage\n fault.",
+ "offset": 19,
+ "size": 1
+ },
+ "UNALIGNED": {
+ "description": "Unaligned access usage\n fault",
+ "offset": 24,
+ "size": 1
+ },
+ "DIVBYZERO": {
+ "description": "Divide by zero usage fault",
+ "offset": 25,
+ "size": 1
+ }
+ }
+ }
+ },
+ "HFSR": {
+ "description": "Hard fault status register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "VECTTBL": {
+ "description": "Vector table hard fault",
+ "offset": 1,
+ "size": 1
+ },
+ "FORCED": {
+ "description": "Forced hard fault",
+ "offset": 30,
+ "size": 1
+ },
+ "DEBUG_VT": {
+ "description": "Reserved for Debug use",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MMFAR": {
+ "description": "Memory management fault address\n register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MMFAR": {
+ "description": "Memory management fault\n address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BFAR": {
+ "description": "Bus fault address register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BFAR": {
+ "description": "Bus fault address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "AFSR": {
+ "description": "Auxiliary fault status\n register",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IMPDEF": {
+ "description": "Implementation defined",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "STK": {
+ "description": "SysTick timer",
+ "children": {
+ "registers": {
+ "CTRL": {
+ "description": "SysTick control and status\n register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ENABLE": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ },
+ "TICKINT": {
+ "description": "SysTick exception request\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "CLKSOURCE": {
+ "description": "Clock source selection",
+ "offset": 2,
+ "size": 1
+ },
+ "COUNTFLAG": {
+ "description": "COUNTFLAG",
+ "offset": 16,
+ "size": 1
+ }
+ }
+ }
+ },
+ "LOAD": {
+ "description": "SysTick reload value register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RELOAD": {
+ "description": "RELOAD value",
+ "offset": 0,
+ "size": 24
+ }
+ }
+ }
+ },
+ "VAL": {
+ "description": "SysTick current value register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CURRENT": {
+ "description": "Current counter value",
+ "offset": 0,
+ "size": 24
+ }
+ }
+ }
+ },
+ "CALIB": {
+ "description": "SysTick calibration value\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TENMS": {
+ "description": "Calibration value",
+ "offset": 0,
+ "size": 24
+ },
+ "SKEW": {
+ "description": "SKEW flag: Indicates whether the TENMS\n value is exact",
+ "offset": 30,
+ "size": 1
+ },
+ "NOREF": {
+ "description": "NOREF flag. Reads as zero",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "MPU": {
+ "description": "Memory protection unit",
+ "children": {
+ "registers": {
+ "MPU_TYPER": {
+ "description": "MPU type register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 2048,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "SEPARATE": {
+ "description": "Separate flag",
+ "offset": 0,
+ "size": 1
+ },
+ "DREGION": {
+ "description": "Number of MPU data regions",
+ "offset": 8,
+ "size": 8
+ },
+ "IREGION": {
+ "description": "Number of MPU instruction\n regions",
+ "offset": 16,
+ "size": 8
+ }
+ }
+ }
+ },
+ "MPU_CTRL": {
+ "description": "MPU control register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "ENABLE": {
+ "description": "Enables the MPU",
+ "offset": 0,
+ "size": 1
+ },
+ "HFNMIENA": {
+ "description": "Enables the operation of MPU during hard\n fault",
+ "offset": 1,
+ "size": 1
+ },
+ "PRIVDEFENA": {
+ "description": "Enable priviliged software access to\n default memory map",
+ "offset": 2,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MPU_RNR": {
+ "description": "MPU region number register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "REGION": {
+ "description": "MPU region",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "MPU_RBAR": {
+ "description": "MPU region base address\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "REGION": {
+ "description": "MPU region field",
+ "offset": 0,
+ "size": 4
+ },
+ "VALID": {
+ "description": "MPU region number valid",
+ "offset": 4,
+ "size": 1
+ },
+ "ADDR": {
+ "description": "Region base address field",
+ "offset": 5,
+ "size": 27
+ }
+ }
+ }
+ },
+ "MPU_RASR": {
+ "description": "MPU region attribute and size\n register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ENABLE": {
+ "description": "Region enable bit.",
+ "offset": 0,
+ "size": 1
+ },
+ "SIZE": {
+ "description": "Size of the MPU protection\n region",
+ "offset": 1,
+ "size": 5
+ },
+ "SRD": {
+ "description": "Subregion disable bits",
+ "offset": 8,
+ "size": 8
+ },
+ "B": {
+ "description": "memory attribute",
+ "offset": 16,
+ "size": 1
+ },
+ "C": {
+ "description": "memory attribute",
+ "offset": 17,
+ "size": 1
+ },
+ "S": {
+ "description": "Shareable memory attribute",
+ "offset": 18,
+ "size": 1
+ },
+ "TEX": {
+ "description": "memory attribute",
+ "offset": 19,
+ "size": 3
+ },
+ "AP": {
+ "description": "Access permission",
+ "offset": 24,
+ "size": 3
+ },
+ "XN": {
+ "description": "Instruction access disable\n bit",
+ "offset": 28,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "TSC": {
+ "description": "Touch sensing controller",
+ "children": {
+ "registers": {
+ "CR": {
+ "description": "control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CTPH": {
+ "description": "Charge transfer pulse high",
+ "offset": 28,
+ "size": 4
+ },
+ "CTPL": {
+ "description": "Charge transfer pulse low",
+ "offset": 24,
+ "size": 4
+ },
+ "SSD": {
+ "description": "Spread spectrum deviation",
+ "offset": 17,
+ "size": 7
+ },
+ "SSE": {
+ "description": "Spread spectrum enable",
+ "offset": 16,
+ "size": 1
+ },
+ "SSPSC": {
+ "description": "Spread spectrum prescaler",
+ "offset": 15,
+ "size": 1
+ },
+ "PGPSC": {
+ "description": "pulse generator prescaler",
+ "offset": 12,
+ "size": 3
+ },
+ "MCV": {
+ "description": "Max count value",
+ "offset": 5,
+ "size": 3
+ },
+ "IODEF": {
+ "description": "I/O Default mode",
+ "offset": 4,
+ "size": 1
+ },
+ "SYNCPOL": {
+ "description": "Synchronization pin\n polarity",
+ "offset": 3,
+ "size": 1
+ },
+ "AM": {
+ "description": "Acquisition mode",
+ "offset": 2,
+ "size": 1
+ },
+ "START": {
+ "description": "Start a new acquisition",
+ "offset": 1,
+ "size": 1
+ },
+ "TSCE": {
+ "description": "Touch sensing controller\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "IER": {
+ "description": "interrupt enable register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MCEIE": {
+ "description": "Max count error interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "EOAIE": {
+ "description": "End of acquisition interrupt\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ICR": {
+ "description": "interrupt clear register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MCEIC": {
+ "description": "Max count error interrupt\n clear",
+ "offset": 1,
+ "size": 1
+ },
+ "EOAIC": {
+ "description": "End of acquisition interrupt\n clear",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ISR": {
+ "description": "interrupt status register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MCEF": {
+ "description": "Max count error flag",
+ "offset": 1,
+ "size": 1
+ },
+ "EOAF": {
+ "description": "End of acquisition flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "IOHCR": {
+ "description": "I/O hysteresis control\n register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "G1_IO1": {
+ "description": "G1_IO1 Schmitt trigger hysteresis\n mode",
+ "offset": 0,
+ "size": 1
+ },
+ "G1_IO2": {
+ "description": "G1_IO2 Schmitt trigger hysteresis\n mode",
+ "offset": 1,
+ "size": 1
+ },
+ "G1_IO3": {
+ "description": "G1_IO3 Schmitt trigger hysteresis\n mode",
+ "offset": 2,
+ "size": 1
+ },
+ "G1_IO4": {
+ "description": "G1_IO4 Schmitt trigger hysteresis\n mode",
+ "offset": 3,
+ "size": 1
+ },
+ "G2_IO1": {
+ "description": "G2_IO1 Schmitt trigger hysteresis\n mode",
+ "offset": 4,
+ "size": 1
+ },
+ "G2_IO2": {
+ "description": "G2_IO2 Schmitt trigger hysteresis\n mode",
+ "offset": 5,
+ "size": 1
+ },
+ "G2_IO3": {
+ "description": "G2_IO3 Schmitt trigger hysteresis\n mode",
+ "offset": 6,
+ "size": 1
+ },
+ "G2_IO4": {
+ "description": "G2_IO4 Schmitt trigger hysteresis\n mode",
+ "offset": 7,
+ "size": 1
+ },
+ "G3_IO1": {
+ "description": "G3_IO1 Schmitt trigger hysteresis\n mode",
+ "offset": 8,
+ "size": 1
+ },
+ "G3_IO2": {
+ "description": "G3_IO2 Schmitt trigger hysteresis\n mode",
+ "offset": 9,
+ "size": 1
+ },
+ "G3_IO3": {
+ "description": "G3_IO3 Schmitt trigger hysteresis\n mode",
+ "offset": 10,
+ "size": 1
+ },
+ "G3_IO4": {
+ "description": "G3_IO4 Schmitt trigger hysteresis\n mode",
+ "offset": 11,
+ "size": 1
+ },
+ "G4_IO1": {
+ "description": "G4_IO1 Schmitt trigger hysteresis\n mode",
+ "offset": 12,
+ "size": 1
+ },
+ "G4_IO2": {
+ "description": "G4_IO2 Schmitt trigger hysteresis\n mode",
+ "offset": 13,
+ "size": 1
+ },
+ "G4_IO3": {
+ "description": "G4_IO3 Schmitt trigger hysteresis\n mode",
+ "offset": 14,
+ "size": 1
+ },
+ "G4_IO4": {
+ "description": "G4_IO4 Schmitt trigger hysteresis\n mode",
+ "offset": 15,
+ "size": 1
+ },
+ "G5_IO1": {
+ "description": "G5_IO1 Schmitt trigger hysteresis\n mode",
+ "offset": 16,
+ "size": 1
+ },
+ "G5_IO2": {
+ "description": "G5_IO2 Schmitt trigger hysteresis\n mode",
+ "offset": 17,
+ "size": 1
+ },
+ "G5_IO3": {
+ "description": "G5_IO3 Schmitt trigger hysteresis\n mode",
+ "offset": 18,
+ "size": 1
+ },
+ "G5_IO4": {
+ "description": "G5_IO4 Schmitt trigger hysteresis\n mode",
+ "offset": 19,
+ "size": 1
+ },
+ "G6_IO1": {
+ "description": "G6_IO1 Schmitt trigger hysteresis\n mode",
+ "offset": 20,
+ "size": 1
+ },
+ "G6_IO2": {
+ "description": "G6_IO2 Schmitt trigger hysteresis\n mode",
+ "offset": 21,
+ "size": 1
+ },
+ "G6_IO3": {
+ "description": "G6_IO3 Schmitt trigger hysteresis\n mode",
+ "offset": 22,
+ "size": 1
+ },
+ "G6_IO4": {
+ "description": "G6_IO4 Schmitt trigger hysteresis\n mode",
+ "offset": 23,
+ "size": 1
+ },
+ "G7_IO1": {
+ "description": "G7_IO1 Schmitt trigger hysteresis\n mode",
+ "offset": 24,
+ "size": 1
+ },
+ "G7_IO2": {
+ "description": "G7_IO2 Schmitt trigger hysteresis\n mode",
+ "offset": 25,
+ "size": 1
+ },
+ "G7_IO3": {
+ "description": "G7_IO3 Schmitt trigger hysteresis\n mode",
+ "offset": 26,
+ "size": 1
+ },
+ "G7_IO4": {
+ "description": "G7_IO4 Schmitt trigger hysteresis\n mode",
+ "offset": 27,
+ "size": 1
+ },
+ "G8_IO1": {
+ "description": "G8_IO1 Schmitt trigger hysteresis\n mode",
+ "offset": 28,
+ "size": 1
+ },
+ "G8_IO2": {
+ "description": "G8_IO2 Schmitt trigger hysteresis\n mode",
+ "offset": 29,
+ "size": 1
+ },
+ "G8_IO3": {
+ "description": "G8_IO3 Schmitt trigger hysteresis\n mode",
+ "offset": 30,
+ "size": 1
+ },
+ "G8_IO4": {
+ "description": "G8_IO4 Schmitt trigger hysteresis\n mode",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "IOASCR": {
+ "description": "I/O analog switch control\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "G1_IO1": {
+ "description": "G1_IO1 analog switch\n enable",
+ "offset": 0,
+ "size": 1
+ },
+ "G1_IO2": {
+ "description": "G1_IO2 analog switch\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "G1_IO3": {
+ "description": "G1_IO3 analog switch\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "G1_IO4": {
+ "description": "G1_IO4 analog switch\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "G2_IO1": {
+ "description": "G2_IO1 analog switch\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "G2_IO2": {
+ "description": "G2_IO2 analog switch\n enable",
+ "offset": 5,
+ "size": 1
+ },
+ "G2_IO3": {
+ "description": "G2_IO3 analog switch\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "G2_IO4": {
+ "description": "G2_IO4 analog switch\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "G3_IO1": {
+ "description": "G3_IO1 analog switch\n enable",
+ "offset": 8,
+ "size": 1
+ },
+ "G3_IO2": {
+ "description": "G3_IO2 analog switch\n enable",
+ "offset": 9,
+ "size": 1
+ },
+ "G3_IO3": {
+ "description": "G3_IO3 analog switch\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "G3_IO4": {
+ "description": "G3_IO4 analog switch\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "G4_IO1": {
+ "description": "G4_IO1 analog switch\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "G4_IO2": {
+ "description": "G4_IO2 analog switch\n enable",
+ "offset": 13,
+ "size": 1
+ },
+ "G4_IO3": {
+ "description": "G4_IO3 analog switch\n enable",
+ "offset": 14,
+ "size": 1
+ },
+ "G4_IO4": {
+ "description": "G4_IO4 analog switch\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "G5_IO1": {
+ "description": "G5_IO1 analog switch\n enable",
+ "offset": 16,
+ "size": 1
+ },
+ "G5_IO2": {
+ "description": "G5_IO2 analog switch\n enable",
+ "offset": 17,
+ "size": 1
+ },
+ "G5_IO3": {
+ "description": "G5_IO3 analog switch\n enable",
+ "offset": 18,
+ "size": 1
+ },
+ "G5_IO4": {
+ "description": "G5_IO4 analog switch\n enable",
+ "offset": 19,
+ "size": 1
+ },
+ "G6_IO1": {
+ "description": "G6_IO1 analog switch\n enable",
+ "offset": 20,
+ "size": 1
+ },
+ "G6_IO2": {
+ "description": "G6_IO2 analog switch\n enable",
+ "offset": 21,
+ "size": 1
+ },
+ "G6_IO3": {
+ "description": "G6_IO3 analog switch\n enable",
+ "offset": 22,
+ "size": 1
+ },
+ "G6_IO4": {
+ "description": "G6_IO4 analog switch\n enable",
+ "offset": 23,
+ "size": 1
+ },
+ "G7_IO1": {
+ "description": "G7_IO1 analog switch\n enable",
+ "offset": 24,
+ "size": 1
+ },
+ "G7_IO2": {
+ "description": "G7_IO2 analog switch\n enable",
+ "offset": 25,
+ "size": 1
+ },
+ "G7_IO3": {
+ "description": "G7_IO3 analog switch\n enable",
+ "offset": 26,
+ "size": 1
+ },
+ "G7_IO4": {
+ "description": "G7_IO4 analog switch\n enable",
+ "offset": 27,
+ "size": 1
+ },
+ "G8_IO1": {
+ "description": "G8_IO1 analog switch\n enable",
+ "offset": 28,
+ "size": 1
+ },
+ "G8_IO2": {
+ "description": "G8_IO2 analog switch\n enable",
+ "offset": 29,
+ "size": 1
+ },
+ "G8_IO3": {
+ "description": "G8_IO3 analog switch\n enable",
+ "offset": 30,
+ "size": 1
+ },
+ "G8_IO4": {
+ "description": "G8_IO4 analog switch\n enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "IOSCR": {
+ "description": "I/O sampling control register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "G1_IO1": {
+ "description": "G1_IO1 sampling mode",
+ "offset": 0,
+ "size": 1
+ },
+ "G1_IO2": {
+ "description": "G1_IO2 sampling mode",
+ "offset": 1,
+ "size": 1
+ },
+ "G1_IO3": {
+ "description": "G1_IO3 sampling mode",
+ "offset": 2,
+ "size": 1
+ },
+ "G1_IO4": {
+ "description": "G1_IO4 sampling mode",
+ "offset": 3,
+ "size": 1
+ },
+ "G2_IO1": {
+ "description": "G2_IO1 sampling mode",
+ "offset": 4,
+ "size": 1
+ },
+ "G2_IO2": {
+ "description": "G2_IO2 sampling mode",
+ "offset": 5,
+ "size": 1
+ },
+ "G2_IO3": {
+ "description": "G2_IO3 sampling mode",
+ "offset": 6,
+ "size": 1
+ },
+ "G2_IO4": {
+ "description": "G2_IO4 sampling mode",
+ "offset": 7,
+ "size": 1
+ },
+ "G3_IO1": {
+ "description": "G3_IO1 sampling mode",
+ "offset": 8,
+ "size": 1
+ },
+ "G3_IO2": {
+ "description": "G3_IO2 sampling mode",
+ "offset": 9,
+ "size": 1
+ },
+ "G3_IO3": {
+ "description": "G3_IO3 sampling mode",
+ "offset": 10,
+ "size": 1
+ },
+ "G3_IO4": {
+ "description": "G3_IO4 sampling mode",
+ "offset": 11,
+ "size": 1
+ },
+ "G4_IO1": {
+ "description": "G4_IO1 sampling mode",
+ "offset": 12,
+ "size": 1
+ },
+ "G4_IO2": {
+ "description": "G4_IO2 sampling mode",
+ "offset": 13,
+ "size": 1
+ },
+ "G4_IO3": {
+ "description": "G4_IO3 sampling mode",
+ "offset": 14,
+ "size": 1
+ },
+ "G4_IO4": {
+ "description": "G4_IO4 sampling mode",
+ "offset": 15,
+ "size": 1
+ },
+ "G5_IO1": {
+ "description": "G5_IO1 sampling mode",
+ "offset": 16,
+ "size": 1
+ },
+ "G5_IO2": {
+ "description": "G5_IO2 sampling mode",
+ "offset": 17,
+ "size": 1
+ },
+ "G5_IO3": {
+ "description": "G5_IO3 sampling mode",
+ "offset": 18,
+ "size": 1
+ },
+ "G5_IO4": {
+ "description": "G5_IO4 sampling mode",
+ "offset": 19,
+ "size": 1
+ },
+ "G6_IO1": {
+ "description": "G6_IO1 sampling mode",
+ "offset": 20,
+ "size": 1
+ },
+ "G6_IO2": {
+ "description": "G6_IO2 sampling mode",
+ "offset": 21,
+ "size": 1
+ },
+ "G6_IO3": {
+ "description": "G6_IO3 sampling mode",
+ "offset": 22,
+ "size": 1
+ },
+ "G6_IO4": {
+ "description": "G6_IO4 sampling mode",
+ "offset": 23,
+ "size": 1
+ },
+ "G7_IO1": {
+ "description": "G7_IO1 sampling mode",
+ "offset": 24,
+ "size": 1
+ },
+ "G7_IO2": {
+ "description": "G7_IO2 sampling mode",
+ "offset": 25,
+ "size": 1
+ },
+ "G7_IO3": {
+ "description": "G7_IO3 sampling mode",
+ "offset": 26,
+ "size": 1
+ },
+ "G7_IO4": {
+ "description": "G7_IO4 sampling mode",
+ "offset": 27,
+ "size": 1
+ },
+ "G8_IO1": {
+ "description": "G8_IO1 sampling mode",
+ "offset": 28,
+ "size": 1
+ },
+ "G8_IO2": {
+ "description": "G8_IO2 sampling mode",
+ "offset": 29,
+ "size": 1
+ },
+ "G8_IO3": {
+ "description": "G8_IO3 sampling mode",
+ "offset": 30,
+ "size": 1
+ },
+ "G8_IO4": {
+ "description": "G8_IO4 sampling mode",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "IOCCR": {
+ "description": "I/O channel control register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "G1_IO1": {
+ "description": "G1_IO1 channel mode",
+ "offset": 0,
+ "size": 1
+ },
+ "G1_IO2": {
+ "description": "G1_IO2 channel mode",
+ "offset": 1,
+ "size": 1
+ },
+ "G1_IO3": {
+ "description": "G1_IO3 channel mode",
+ "offset": 2,
+ "size": 1
+ },
+ "G1_IO4": {
+ "description": "G1_IO4 channel mode",
+ "offset": 3,
+ "size": 1
+ },
+ "G2_IO1": {
+ "description": "G2_IO1 channel mode",
+ "offset": 4,
+ "size": 1
+ },
+ "G2_IO2": {
+ "description": "G2_IO2 channel mode",
+ "offset": 5,
+ "size": 1
+ },
+ "G2_IO3": {
+ "description": "G2_IO3 channel mode",
+ "offset": 6,
+ "size": 1
+ },
+ "G2_IO4": {
+ "description": "G2_IO4 channel mode",
+ "offset": 7,
+ "size": 1
+ },
+ "G3_IO1": {
+ "description": "G3_IO1 channel mode",
+ "offset": 8,
+ "size": 1
+ },
+ "G3_IO2": {
+ "description": "G3_IO2 channel mode",
+ "offset": 9,
+ "size": 1
+ },
+ "G3_IO3": {
+ "description": "G3_IO3 channel mode",
+ "offset": 10,
+ "size": 1
+ },
+ "G3_IO4": {
+ "description": "G3_IO4 channel mode",
+ "offset": 11,
+ "size": 1
+ },
+ "G4_IO1": {
+ "description": "G4_IO1 channel mode",
+ "offset": 12,
+ "size": 1
+ },
+ "G4_IO2": {
+ "description": "G4_IO2 channel mode",
+ "offset": 13,
+ "size": 1
+ },
+ "G4_IO3": {
+ "description": "G4_IO3 channel mode",
+ "offset": 14,
+ "size": 1
+ },
+ "G4_IO4": {
+ "description": "G4_IO4 channel mode",
+ "offset": 15,
+ "size": 1
+ },
+ "G5_IO1": {
+ "description": "G5_IO1 channel mode",
+ "offset": 16,
+ "size": 1
+ },
+ "G5_IO2": {
+ "description": "G5_IO2 channel mode",
+ "offset": 17,
+ "size": 1
+ },
+ "G5_IO3": {
+ "description": "G5_IO3 channel mode",
+ "offset": 18,
+ "size": 1
+ },
+ "G5_IO4": {
+ "description": "G5_IO4 channel mode",
+ "offset": 19,
+ "size": 1
+ },
+ "G6_IO1": {
+ "description": "G6_IO1 channel mode",
+ "offset": 20,
+ "size": 1
+ },
+ "G6_IO2": {
+ "description": "G6_IO2 channel mode",
+ "offset": 21,
+ "size": 1
+ },
+ "G6_IO3": {
+ "description": "G6_IO3 channel mode",
+ "offset": 22,
+ "size": 1
+ },
+ "G6_IO4": {
+ "description": "G6_IO4 channel mode",
+ "offset": 23,
+ "size": 1
+ },
+ "G7_IO1": {
+ "description": "G7_IO1 channel mode",
+ "offset": 24,
+ "size": 1
+ },
+ "G7_IO2": {
+ "description": "G7_IO2 channel mode",
+ "offset": 25,
+ "size": 1
+ },
+ "G7_IO3": {
+ "description": "G7_IO3 channel mode",
+ "offset": 26,
+ "size": 1
+ },
+ "G7_IO4": {
+ "description": "G7_IO4 channel mode",
+ "offset": 27,
+ "size": 1
+ },
+ "G8_IO1": {
+ "description": "G8_IO1 channel mode",
+ "offset": 28,
+ "size": 1
+ },
+ "G8_IO2": {
+ "description": "G8_IO2 channel mode",
+ "offset": 29,
+ "size": 1
+ },
+ "G8_IO3": {
+ "description": "G8_IO3 channel mode",
+ "offset": 30,
+ "size": 1
+ },
+ "G8_IO4": {
+ "description": "G8_IO4 channel mode",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "IOGCSR": {
+ "description": "I/O group control status\n register",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "G8S": {
+ "description": "Analog I/O group x status",
+ "offset": 23,
+ "size": 1
+ },
+ "G7S": {
+ "description": "Analog I/O group x status",
+ "offset": 22,
+ "size": 1
+ },
+ "G6S": {
+ "description": "Analog I/O group x status",
+ "offset": 21,
+ "size": 1,
+ "access": "read-only"
+ },
+ "G5S": {
+ "description": "Analog I/O group x status",
+ "offset": 20,
+ "size": 1,
+ "access": "read-only"
+ },
+ "G4S": {
+ "description": "Analog I/O group x status",
+ "offset": 19,
+ "size": 1,
+ "access": "read-only"
+ },
+ "G3S": {
+ "description": "Analog I/O group x status",
+ "offset": 18,
+ "size": 1,
+ "access": "read-only"
+ },
+ "G2S": {
+ "description": "Analog I/O group x status",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "G1S": {
+ "description": "Analog I/O group x status",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "G8E": {
+ "description": "Analog I/O group x enable",
+ "offset": 7,
+ "size": 1
+ },
+ "G7E": {
+ "description": "Analog I/O group x enable",
+ "offset": 6,
+ "size": 1
+ },
+ "G6E": {
+ "description": "Analog I/O group x enable",
+ "offset": 5,
+ "size": 1
+ },
+ "G5E": {
+ "description": "Analog I/O group x enable",
+ "offset": 4,
+ "size": 1
+ },
+ "G4E": {
+ "description": "Analog I/O group x enable",
+ "offset": 3,
+ "size": 1
+ },
+ "G3E": {
+ "description": "Analog I/O group x enable",
+ "offset": 2,
+ "size": 1
+ },
+ "G2E": {
+ "description": "Analog I/O group x enable",
+ "offset": 1,
+ "size": 1
+ },
+ "G1E": {
+ "description": "Analog I/O group x enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "IOG1CR": {
+ "description": "I/O group x counter register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CNT": {
+ "description": "Counter value",
+ "offset": 0,
+ "size": 14
+ }
+ }
+ }
+ },
+ "IOG2CR": {
+ "description": "I/O group x counter register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CNT": {
+ "description": "Counter value",
+ "offset": 0,
+ "size": 14
+ }
+ }
+ }
+ },
+ "IOG3CR": {
+ "description": "I/O group x counter register",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CNT": {
+ "description": "Counter value",
+ "offset": 0,
+ "size": 14
+ }
+ }
+ }
+ },
+ "IOG4CR": {
+ "description": "I/O group x counter register",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CNT": {
+ "description": "Counter value",
+ "offset": 0,
+ "size": 14
+ }
+ }
+ }
+ },
+ "IOG5CR": {
+ "description": "I/O group x counter register",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CNT": {
+ "description": "Counter value",
+ "offset": 0,
+ "size": 14
+ }
+ }
+ }
+ },
+ "IOG6CR": {
+ "description": "I/O group x counter register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CNT": {
+ "description": "Counter value",
+ "offset": 0,
+ "size": 14
+ }
+ }
+ }
+ },
+ "IOG7CR": {
+ "description": "I/O group x counter register",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CNT": {
+ "description": "Counter value",
+ "offset": 0,
+ "size": 14
+ }
+ }
+ }
+ },
+ "IOG8CR": {
+ "description": "I/O group x counter register",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CNT": {
+ "description": "Counter value",
+ "offset": 0,
+ "size": 14
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "CRC": {
+ "description": "cyclic redundancy check calculation\n unit",
+ "children": {
+ "registers": {
+ "DR": {
+ "description": "Data register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DR": {
+ "description": "Data register bits",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "IDR": {
+ "description": "Independent data register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IDR": {
+ "description": "General-purpose 8-bit data register\n bits",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "CR": {
+ "description": "Control register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RESET": {
+ "description": "reset bit",
+ "offset": 0,
+ "size": 1
+ },
+ "POLYSIZE": {
+ "description": "Polynomial size",
+ "offset": 3,
+ "size": 2
+ },
+ "REV_IN": {
+ "description": "Reverse input data",
+ "offset": 5,
+ "size": 2
+ },
+ "REV_OUT": {
+ "description": "Reverse output data",
+ "offset": 7,
+ "size": 1
+ }
+ }
+ }
+ },
+ "INIT": {
+ "description": "Initial CRC value",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INIT": {
+ "description": "Programmable initial CRC\n value",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "POL": {
+ "description": "CRC polynomial",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 79764919,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "POL": {
+ "description": "Programmable polynomial",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "Flash": {
+ "description": "Flash",
+ "children": {
+ "registers": {
+ "ACR": {
+ "description": "Flash access control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 48,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LATENCY": {
+ "description": "LATENCY",
+ "offset": 0,
+ "size": 3
+ },
+ "PRFTBE": {
+ "description": "PRFTBE",
+ "offset": 4,
+ "size": 1
+ },
+ "PRFTBS": {
+ "description": "PRFTBS",
+ "offset": 5,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "KEYR": {
+ "description": "Flash key register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "FKEYR": {
+ "description": "Flash Key",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OPTKEYR": {
+ "description": "Flash option key register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "OPTKEYR": {
+ "description": "Option byte key",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "Flash status register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EOP": {
+ "description": "End of operation",
+ "offset": 5,
+ "size": 1
+ },
+ "WRPRT": {
+ "description": "Write protection error",
+ "offset": 4,
+ "size": 1
+ },
+ "PGERR": {
+ "description": "Programming error",
+ "offset": 2,
+ "size": 1
+ },
+ "BSY": {
+ "description": "Busy",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "CR": {
+ "description": "Flash control register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FORCE_OPTLOAD": {
+ "description": "Force option byte loading",
+ "offset": 13,
+ "size": 1
+ },
+ "EOPIE": {
+ "description": "End of operation interrupt\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "ERRIE": {
+ "description": "Error interrupt enable",
+ "offset": 10,
+ "size": 1
+ },
+ "OPTWRE": {
+ "description": "Option bytes write enable",
+ "offset": 9,
+ "size": 1
+ },
+ "LOCK": {
+ "description": "Lock",
+ "offset": 7,
+ "size": 1
+ },
+ "STRT": {
+ "description": "Start",
+ "offset": 6,
+ "size": 1
+ },
+ "OPTER": {
+ "description": "Option byte erase",
+ "offset": 5,
+ "size": 1
+ },
+ "OPTPG": {
+ "description": "Option byte programming",
+ "offset": 4,
+ "size": 1
+ },
+ "MER": {
+ "description": "Mass erase",
+ "offset": 2,
+ "size": 1
+ },
+ "PER": {
+ "description": "Page erase",
+ "offset": 1,
+ "size": 1
+ },
+ "PG": {
+ "description": "Programming",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "AR": {
+ "description": "Flash address register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "FAR": {
+ "description": "Flash address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OBR": {
+ "description": "Option byte register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 4294967042,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "OPTERR": {
+ "description": "Option byte error",
+ "offset": 0,
+ "size": 1
+ },
+ "LEVEL1_PROT": {
+ "description": "Level 1 protection status",
+ "offset": 1,
+ "size": 1
+ },
+ "LEVEL2_PROT": {
+ "description": "Level 2 protection status",
+ "offset": 2,
+ "size": 1
+ },
+ "WDG_SW": {
+ "description": "WDG_SW",
+ "offset": 8,
+ "size": 1
+ },
+ "nRST_STOP": {
+ "description": "nRST_STOP",
+ "offset": 9,
+ "size": 1
+ },
+ "nRST_STDBY": {
+ "description": "nRST_STDBY",
+ "offset": 10,
+ "size": 1
+ },
+ "BOOT1": {
+ "description": "BOOT1",
+ "offset": 12,
+ "size": 1
+ },
+ "VDDA_MONITOR": {
+ "description": "VDDA_MONITOR",
+ "offset": 13,
+ "size": 1
+ },
+ "SRAM_PARITY_CHECK": {
+ "description": "SRAM_PARITY_CHECK",
+ "offset": 14,
+ "size": 1
+ },
+ "Data0": {
+ "description": "Data0",
+ "offset": 16,
+ "size": 8
+ },
+ "Data1": {
+ "description": "Data1",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "WRPR": {
+ "description": "Write protection register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "WRP": {
+ "description": "Write protect",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "RCC": {
+ "description": "Reset and clock control",
+ "children": {
+ "registers": {
+ "CR": {
+ "description": "Clock control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 131,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "HSION": {
+ "description": "Internal High Speed clock\n enable",
+ "offset": 0,
+ "size": 1
+ },
+ "HSIRDY": {
+ "description": "Internal High Speed clock ready\n flag",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HSITRIM": {
+ "description": "Internal High Speed clock\n trimming",
+ "offset": 3,
+ "size": 5
+ },
+ "HSICAL": {
+ "description": "Internal High Speed clock\n Calibration",
+ "offset": 8,
+ "size": 8,
+ "access": "read-only"
+ },
+ "HSEON": {
+ "description": "External High Speed clock\n enable",
+ "offset": 16,
+ "size": 1
+ },
+ "HSERDY": {
+ "description": "External High Speed clock ready\n flag",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HSEBYP": {
+ "description": "External High Speed clock\n Bypass",
+ "offset": 18,
+ "size": 1
+ },
+ "CSSON": {
+ "description": "Clock Security System\n enable",
+ "offset": 19,
+ "size": 1
+ },
+ "PLLON": {
+ "description": "PLL enable",
+ "offset": 24,
+ "size": 1
+ },
+ "PLLRDY": {
+ "description": "PLL clock ready flag",
+ "offset": 25,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "CFGR": {
+ "description": "Clock configuration register\n (RCC_CFGR)",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SW": {
+ "description": "System clock Switch",
+ "offset": 0,
+ "size": 2
+ },
+ "SWS": {
+ "description": "System Clock Switch Status",
+ "offset": 2,
+ "size": 2,
+ "access": "read-only"
+ },
+ "HPRE": {
+ "description": "AHB prescaler",
+ "offset": 4,
+ "size": 4
+ },
+ "PPRE1": {
+ "description": "APB Low speed prescaler\n (APB1)",
+ "offset": 8,
+ "size": 3
+ },
+ "PPRE2": {
+ "description": "APB high speed prescaler\n (APB2)",
+ "offset": 11,
+ "size": 3
+ },
+ "PLLSRC": {
+ "description": "PLL entry clock source",
+ "offset": 15,
+ "size": 2
+ },
+ "PLLXTPRE": {
+ "description": "HSE divider for PLL entry",
+ "offset": 17,
+ "size": 1
+ },
+ "PLLMUL": {
+ "description": "PLL Multiplication Factor",
+ "offset": 18,
+ "size": 4
+ },
+ "USBPRES": {
+ "description": "USB prescaler",
+ "offset": 22,
+ "size": 1
+ },
+ "MCO": {
+ "description": "Microcontroller clock\n output",
+ "offset": 24,
+ "size": 3
+ },
+ "MCOF": {
+ "description": "Microcontroller Clock Output\n Flag",
+ "offset": 28,
+ "size": 1,
+ "access": "read-only"
+ },
+ "I2SSRC": {
+ "description": "I2S external clock source\n selection",
+ "offset": 23,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CIR": {
+ "description": "Clock interrupt register\n (RCC_CIR)",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LSIRDYF": {
+ "description": "LSI Ready Interrupt flag",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ },
+ "LSERDYF": {
+ "description": "LSE Ready Interrupt flag",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HSIRDYF": {
+ "description": "HSI Ready Interrupt flag",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HSERDYF": {
+ "description": "HSE Ready Interrupt flag",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PLLRDYF": {
+ "description": "PLL Ready Interrupt flag",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "CSSF": {
+ "description": "Clock Security System Interrupt\n flag",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "LSIRDYIE": {
+ "description": "LSI Ready Interrupt Enable",
+ "offset": 8,
+ "size": 1
+ },
+ "LSERDYIE": {
+ "description": "LSE Ready Interrupt Enable",
+ "offset": 9,
+ "size": 1
+ },
+ "HSIRDYIE": {
+ "description": "HSI Ready Interrupt Enable",
+ "offset": 10,
+ "size": 1
+ },
+ "HSERDYIE": {
+ "description": "HSE Ready Interrupt Enable",
+ "offset": 11,
+ "size": 1
+ },
+ "PLLRDYIE": {
+ "description": "PLL Ready Interrupt Enable",
+ "offset": 12,
+ "size": 1
+ },
+ "LSIRDYC": {
+ "description": "LSI Ready Interrupt Clear",
+ "offset": 16,
+ "size": 1,
+ "access": "write-only"
+ },
+ "LSERDYC": {
+ "description": "LSE Ready Interrupt Clear",
+ "offset": 17,
+ "size": 1,
+ "access": "write-only"
+ },
+ "HSIRDYC": {
+ "description": "HSI Ready Interrupt Clear",
+ "offset": 18,
+ "size": 1,
+ "access": "write-only"
+ },
+ "HSERDYC": {
+ "description": "HSE Ready Interrupt Clear",
+ "offset": 19,
+ "size": 1,
+ "access": "write-only"
+ },
+ "PLLRDYC": {
+ "description": "PLL Ready Interrupt Clear",
+ "offset": 20,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CSSC": {
+ "description": "Clock security system interrupt\n clear",
+ "offset": 23,
+ "size": 1,
+ "access": "write-only"
+ }
+ }
+ }
+ },
+ "APB2RSTR": {
+ "description": "APB2 peripheral reset register\n (RCC_APB2RSTR)",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SYSCFGRST": {
+ "description": "SYSCFG and COMP reset",
+ "offset": 0,
+ "size": 1
+ },
+ "TIM1RST": {
+ "description": "TIM1 timer reset",
+ "offset": 11,
+ "size": 1
+ },
+ "SPI1RST": {
+ "description": "SPI 1 reset",
+ "offset": 12,
+ "size": 1
+ },
+ "TIM8RST": {
+ "description": "TIM8 timer reset",
+ "offset": 13,
+ "size": 1
+ },
+ "USART1RST": {
+ "description": "USART1 reset",
+ "offset": 14,
+ "size": 1
+ },
+ "TIM15RST": {
+ "description": "TIM15 timer reset",
+ "offset": 16,
+ "size": 1
+ },
+ "TIM16RST": {
+ "description": "TIM16 timer reset",
+ "offset": 17,
+ "size": 1
+ },
+ "TIM17RST": {
+ "description": "TIM17 timer reset",
+ "offset": 18,
+ "size": 1
+ }
+ }
+ }
+ },
+ "APB1RSTR": {
+ "description": "APB1 peripheral reset register\n (RCC_APB1RSTR)",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIM2RST": {
+ "description": "Timer 2 reset",
+ "offset": 0,
+ "size": 1
+ },
+ "TIM3RST": {
+ "description": "Timer 3 reset",
+ "offset": 1,
+ "size": 1
+ },
+ "TIM4RST": {
+ "description": "Timer 14 reset",
+ "offset": 2,
+ "size": 1
+ },
+ "TIM6RST": {
+ "description": "Timer 6 reset",
+ "offset": 4,
+ "size": 1
+ },
+ "TIM7RST": {
+ "description": "Timer 7 reset",
+ "offset": 5,
+ "size": 1
+ },
+ "WWDGRST": {
+ "description": "Window watchdog reset",
+ "offset": 11,
+ "size": 1
+ },
+ "SPI2RST": {
+ "description": "SPI2 reset",
+ "offset": 14,
+ "size": 1
+ },
+ "SPI3RST": {
+ "description": "SPI3 reset",
+ "offset": 15,
+ "size": 1
+ },
+ "USART2RST": {
+ "description": "USART 2 reset",
+ "offset": 17,
+ "size": 1
+ },
+ "USART3RST": {
+ "description": "USART3 reset",
+ "offset": 18,
+ "size": 1
+ },
+ "UART4RST": {
+ "description": "UART 4 reset",
+ "offset": 19,
+ "size": 1
+ },
+ "UART5RST": {
+ "description": "UART 5 reset",
+ "offset": 20,
+ "size": 1
+ },
+ "I2C1RST": {
+ "description": "I2C1 reset",
+ "offset": 21,
+ "size": 1
+ },
+ "I2C2RST": {
+ "description": "I2C2 reset",
+ "offset": 22,
+ "size": 1
+ },
+ "USBRST": {
+ "description": "USB reset",
+ "offset": 23,
+ "size": 1
+ },
+ "CANRST": {
+ "description": "CAN reset",
+ "offset": 25,
+ "size": 1
+ },
+ "PWRRST": {
+ "description": "Power interface reset",
+ "offset": 28,
+ "size": 1
+ },
+ "DACRST": {
+ "description": "DAC interface reset",
+ "offset": 29,
+ "size": 1
+ },
+ "I2C3RST": {
+ "description": "I2C3 reset",
+ "offset": 30,
+ "size": 1
+ }
+ }
+ }
+ },
+ "AHBENR": {
+ "description": "AHB Peripheral Clock enable register\n (RCC_AHBENR)",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 20,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAEN": {
+ "description": "DMA1 clock enable",
+ "offset": 0,
+ "size": 1
+ },
+ "DMA2EN": {
+ "description": "DMA2 clock enable",
+ "offset": 1,
+ "size": 1
+ },
+ "SRAMEN": {
+ "description": "SRAM interface clock\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "FLITFEN": {
+ "description": "FLITF clock enable",
+ "offset": 4,
+ "size": 1
+ },
+ "FMCEN": {
+ "description": "FMC clock enable",
+ "offset": 5,
+ "size": 1
+ },
+ "CRCEN": {
+ "description": "CRC clock enable",
+ "offset": 6,
+ "size": 1
+ },
+ "IOPHEN": {
+ "description": "IO port H clock enable",
+ "offset": 16,
+ "size": 1
+ },
+ "IOPAEN": {
+ "description": "I/O port A clock enable",
+ "offset": 17,
+ "size": 1
+ },
+ "IOPBEN": {
+ "description": "I/O port B clock enable",
+ "offset": 18,
+ "size": 1
+ },
+ "IOPCEN": {
+ "description": "I/O port C clock enable",
+ "offset": 19,
+ "size": 1
+ },
+ "IOPDEN": {
+ "description": "I/O port D clock enable",
+ "offset": 20,
+ "size": 1
+ },
+ "IOPEEN": {
+ "description": "I/O port E clock enable",
+ "offset": 21,
+ "size": 1
+ },
+ "IOPFEN": {
+ "description": "I/O port F clock enable",
+ "offset": 22,
+ "size": 1
+ },
+ "IOPGEN": {
+ "description": "I/O port G clock enable",
+ "offset": 23,
+ "size": 1
+ },
+ "TSCEN": {
+ "description": "Touch sensing controller clock\n enable",
+ "offset": 24,
+ "size": 1
+ },
+ "ADC12EN": {
+ "description": "ADC1 and ADC2 clock enable",
+ "offset": 28,
+ "size": 1
+ },
+ "ADC34EN": {
+ "description": "ADC3 and ADC4 clock enable",
+ "offset": 29,
+ "size": 1
+ }
+ }
+ }
+ },
+ "APB2ENR": {
+ "description": "APB2 peripheral clock enable register\n (RCC_APB2ENR)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SYSCFGEN": {
+ "description": "SYSCFG clock enable",
+ "offset": 0,
+ "size": 1
+ },
+ "TIM1EN": {
+ "description": "TIM1 Timer clock enable",
+ "offset": 11,
+ "size": 1
+ },
+ "SPI1EN": {
+ "description": "SPI 1 clock enable",
+ "offset": 12,
+ "size": 1
+ },
+ "TIM8EN": {
+ "description": "TIM8 Timer clock enable",
+ "offset": 13,
+ "size": 1
+ },
+ "USART1EN": {
+ "description": "USART1 clock enable",
+ "offset": 14,
+ "size": 1
+ },
+ "TIM15EN": {
+ "description": "TIM15 timer clock enable",
+ "offset": 16,
+ "size": 1
+ },
+ "TIM16EN": {
+ "description": "TIM16 timer clock enable",
+ "offset": 17,
+ "size": 1
+ },
+ "TIM17EN": {
+ "description": "TIM17 timer clock enable",
+ "offset": 18,
+ "size": 1
+ }
+ }
+ }
+ },
+ "APB1ENR": {
+ "description": "APB1 peripheral clock enable register\n (RCC_APB1ENR)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIM2EN": {
+ "description": "Timer 2 clock enable",
+ "offset": 0,
+ "size": 1
+ },
+ "TIM3EN": {
+ "description": "Timer 3 clock enable",
+ "offset": 1,
+ "size": 1
+ },
+ "TIM4EN": {
+ "description": "Timer 4 clock enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TIM6EN": {
+ "description": "Timer 6 clock enable",
+ "offset": 4,
+ "size": 1
+ },
+ "TIM7EN": {
+ "description": "Timer 7 clock enable",
+ "offset": 5,
+ "size": 1
+ },
+ "WWDGEN": {
+ "description": "Window watchdog clock\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "SPI2EN": {
+ "description": "SPI 2 clock enable",
+ "offset": 14,
+ "size": 1
+ },
+ "SPI3EN": {
+ "description": "SPI 3 clock enable",
+ "offset": 15,
+ "size": 1
+ },
+ "USART2EN": {
+ "description": "USART 2 clock enable",
+ "offset": 17,
+ "size": 1
+ },
+ "USART3EN": {
+ "description": "USART 3 clock enable",
+ "offset": 18,
+ "size": 1
+ },
+ "USART4EN": {
+ "description": "USART 4 clock enable",
+ "offset": 19,
+ "size": 1
+ },
+ "USART5EN": {
+ "description": "USART 5 clock enable",
+ "offset": 20,
+ "size": 1
+ },
+ "I2C1EN": {
+ "description": "I2C 1 clock enable",
+ "offset": 21,
+ "size": 1
+ },
+ "I2C2EN": {
+ "description": "I2C 2 clock enable",
+ "offset": 22,
+ "size": 1
+ },
+ "USBEN": {
+ "description": "USB clock enable",
+ "offset": 23,
+ "size": 1
+ },
+ "CANEN": {
+ "description": "CAN clock enable",
+ "offset": 25,
+ "size": 1
+ },
+ "DAC2EN": {
+ "description": "DAC2 interface clock\n enable",
+ "offset": 26,
+ "size": 1
+ },
+ "PWREN": {
+ "description": "Power interface clock\n enable",
+ "offset": 28,
+ "size": 1
+ },
+ "DACEN": {
+ "description": "DAC interface clock enable",
+ "offset": 29,
+ "size": 1
+ },
+ "I2C3EN": {
+ "description": "I2C3 clock enable",
+ "offset": 30,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BDCR": {
+ "description": "Backup domain control register\n (RCC_BDCR)",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LSEON": {
+ "description": "External Low Speed oscillator\n enable",
+ "offset": 0,
+ "size": 1
+ },
+ "LSERDY": {
+ "description": "External Low Speed oscillator\n ready",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "LSEBYP": {
+ "description": "External Low Speed oscillator\n bypass",
+ "offset": 2,
+ "size": 1
+ },
+ "LSEDRV": {
+ "description": "LSE oscillator drive\n capability",
+ "offset": 3,
+ "size": 2
+ },
+ "RTCSEL": {
+ "description": "RTC clock source selection",
+ "offset": 8,
+ "size": 2
+ },
+ "RTCEN": {
+ "description": "RTC clock enable",
+ "offset": 15,
+ "size": 1
+ },
+ "BDRST": {
+ "description": "Backup domain software\n reset",
+ "offset": 16,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CSR": {
+ "description": "Control/status register\n (RCC_CSR)",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 201326592,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LSION": {
+ "description": "Internal low speed oscillator\n enable",
+ "offset": 0,
+ "size": 1
+ },
+ "LSIRDY": {
+ "description": "Internal low speed oscillator\n ready",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "RMVF": {
+ "description": "Remove reset flag",
+ "offset": 24,
+ "size": 1
+ },
+ "OBLRSTF": {
+ "description": "Option byte loader reset\n flag",
+ "offset": 25,
+ "size": 1
+ },
+ "PINRSTF": {
+ "description": "PIN reset flag",
+ "offset": 26,
+ "size": 1
+ },
+ "PORRSTF": {
+ "description": "POR/PDR reset flag",
+ "offset": 27,
+ "size": 1
+ },
+ "SFTRSTF": {
+ "description": "Software reset flag",
+ "offset": 28,
+ "size": 1
+ },
+ "IWDGRSTF": {
+ "description": "Independent watchdog reset\n flag",
+ "offset": 29,
+ "size": 1
+ },
+ "WWDGRSTF": {
+ "description": "Window watchdog reset flag",
+ "offset": 30,
+ "size": 1
+ },
+ "LPWRRSTF": {
+ "description": "Low-power reset flag",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "AHBRSTR": {
+ "description": "AHB peripheral reset register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FMCRST": {
+ "description": "FMC reset",
+ "offset": 5,
+ "size": 1
+ },
+ "IOPHRST": {
+ "description": "I/O port H reset",
+ "offset": 16,
+ "size": 1
+ },
+ "IOPARST": {
+ "description": "I/O port A reset",
+ "offset": 17,
+ "size": 1
+ },
+ "IOPBRST": {
+ "description": "I/O port B reset",
+ "offset": 18,
+ "size": 1
+ },
+ "IOPCRST": {
+ "description": "I/O port C reset",
+ "offset": 19,
+ "size": 1
+ },
+ "IOPDRST": {
+ "description": "I/O port D reset",
+ "offset": 20,
+ "size": 1
+ },
+ "IOPERST": {
+ "description": "I/O port E reset",
+ "offset": 21,
+ "size": 1
+ },
+ "IOPFRST": {
+ "description": "I/O port F reset",
+ "offset": 22,
+ "size": 1
+ },
+ "IOPGRST": {
+ "description": "Touch sensing controller\n reset",
+ "offset": 23,
+ "size": 1
+ },
+ "TSCRST": {
+ "description": "Touch sensing controller\n reset",
+ "offset": 24,
+ "size": 1
+ },
+ "ADC12RST": {
+ "description": "ADC1 and ADC2 reset",
+ "offset": 28,
+ "size": 1
+ },
+ "ADC34RST": {
+ "description": "ADC3 and ADC4 reset",
+ "offset": 29,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CFGR2": {
+ "description": "Clock configuration register 2",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PREDIV": {
+ "description": "PREDIV division factor",
+ "offset": 0,
+ "size": 4
+ },
+ "ADC12PRES": {
+ "description": "ADC1 and ADC2 prescaler",
+ "offset": 4,
+ "size": 5
+ },
+ "ADC34PRES": {
+ "description": "ADC3 and ADC4 prescaler",
+ "offset": 9,
+ "size": 5
+ }
+ }
+ }
+ },
+ "CFGR3": {
+ "description": "Clock configuration register 3",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "USART1SW": {
+ "description": "USART1 clock source\n selection",
+ "offset": 0,
+ "size": 2
+ },
+ "I2C1SW": {
+ "description": "I2C1 clock source\n selection",
+ "offset": 4,
+ "size": 1
+ },
+ "I2C2SW": {
+ "description": "I2C2 clock source\n selection",
+ "offset": 5,
+ "size": 1
+ },
+ "I2C3SW": {
+ "description": "I2C3 clock source\n selection",
+ "offset": 6,
+ "size": 1
+ },
+ "USART2SW": {
+ "description": "USART2 clock source\n selection",
+ "offset": 16,
+ "size": 2
+ },
+ "USART3SW": {
+ "description": "USART3 clock source\n selection",
+ "offset": 18,
+ "size": 2
+ },
+ "TIM1SW": {
+ "description": "Timer1 clock source\n selection",
+ "offset": 8,
+ "size": 1
+ },
+ "TIM8SW": {
+ "description": "Timer8 clock source\n selection",
+ "offset": 9,
+ "size": 1
+ },
+ "UART4SW": {
+ "description": "UART4 clock source\n selection",
+ "offset": 20,
+ "size": 2
+ },
+ "UART5SW": {
+ "description": "UART5 clock source\n selection",
+ "offset": 22,
+ "size": 2
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "DMA1": {
+ "description": "DMA controller 1",
+ "children": {
+ "registers": {
+ "ISR": {
+ "description": "DMA interrupt status register\n (DMA_ISR)",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "GIF1": {
+ "description": "Channel 1 Global interrupt\n flag",
+ "offset": 0,
+ "size": 1
+ },
+ "TCIF1": {
+ "description": "Channel 1 Transfer Complete\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "HTIF1": {
+ "description": "Channel 1 Half Transfer Complete\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "TEIF1": {
+ "description": "Channel 1 Transfer Error\n flag",
+ "offset": 3,
+ "size": 1
+ },
+ "GIF2": {
+ "description": "Channel 2 Global interrupt\n flag",
+ "offset": 4,
+ "size": 1
+ },
+ "TCIF2": {
+ "description": "Channel 2 Transfer Complete\n flag",
+ "offset": 5,
+ "size": 1
+ },
+ "HTIF2": {
+ "description": "Channel 2 Half Transfer Complete\n flag",
+ "offset": 6,
+ "size": 1
+ },
+ "TEIF2": {
+ "description": "Channel 2 Transfer Error\n flag",
+ "offset": 7,
+ "size": 1
+ },
+ "GIF3": {
+ "description": "Channel 3 Global interrupt\n flag",
+ "offset": 8,
+ "size": 1
+ },
+ "TCIF3": {
+ "description": "Channel 3 Transfer Complete\n flag",
+ "offset": 9,
+ "size": 1
+ },
+ "HTIF3": {
+ "description": "Channel 3 Half Transfer Complete\n flag",
+ "offset": 10,
+ "size": 1
+ },
+ "TEIF3": {
+ "description": "Channel 3 Transfer Error\n flag",
+ "offset": 11,
+ "size": 1
+ },
+ "GIF4": {
+ "description": "Channel 4 Global interrupt\n flag",
+ "offset": 12,
+ "size": 1
+ },
+ "TCIF4": {
+ "description": "Channel 4 Transfer Complete\n flag",
+ "offset": 13,
+ "size": 1
+ },
+ "HTIF4": {
+ "description": "Channel 4 Half Transfer Complete\n flag",
+ "offset": 14,
+ "size": 1
+ },
+ "TEIF4": {
+ "description": "Channel 4 Transfer Error\n flag",
+ "offset": 15,
+ "size": 1
+ },
+ "GIF5": {
+ "description": "Channel 5 Global interrupt\n flag",
+ "offset": 16,
+ "size": 1
+ },
+ "TCIF5": {
+ "description": "Channel 5 Transfer Complete\n flag",
+ "offset": 17,
+ "size": 1
+ },
+ "HTIF5": {
+ "description": "Channel 5 Half Transfer Complete\n flag",
+ "offset": 18,
+ "size": 1
+ },
+ "TEIF5": {
+ "description": "Channel 5 Transfer Error\n flag",
+ "offset": 19,
+ "size": 1
+ },
+ "GIF6": {
+ "description": "Channel 6 Global interrupt\n flag",
+ "offset": 20,
+ "size": 1
+ },
+ "TCIF6": {
+ "description": "Channel 6 Transfer Complete\n flag",
+ "offset": 21,
+ "size": 1
+ },
+ "HTIF6": {
+ "description": "Channel 6 Half Transfer Complete\n flag",
+ "offset": 22,
+ "size": 1
+ },
+ "TEIF6": {
+ "description": "Channel 6 Transfer Error\n flag",
+ "offset": 23,
+ "size": 1
+ },
+ "GIF7": {
+ "description": "Channel 7 Global interrupt\n flag",
+ "offset": 24,
+ "size": 1
+ },
+ "TCIF7": {
+ "description": "Channel 7 Transfer Complete\n flag",
+ "offset": 25,
+ "size": 1
+ },
+ "HTIF7": {
+ "description": "Channel 7 Half Transfer Complete\n flag",
+ "offset": 26,
+ "size": 1
+ },
+ "TEIF7": {
+ "description": "Channel 7 Transfer Error\n flag",
+ "offset": 27,
+ "size": 1
+ }
+ }
+ }
+ },
+ "IFCR": {
+ "description": "DMA interrupt flag clear register\n (DMA_IFCR)",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "CGIF1": {
+ "description": "Channel 1 Global interrupt\n clear",
+ "offset": 0,
+ "size": 1
+ },
+ "CTCIF1": {
+ "description": "Channel 1 Transfer Complete\n clear",
+ "offset": 1,
+ "size": 1
+ },
+ "CHTIF1": {
+ "description": "Channel 1 Half Transfer\n clear",
+ "offset": 2,
+ "size": 1
+ },
+ "CTEIF1": {
+ "description": "Channel 1 Transfer Error\n clear",
+ "offset": 3,
+ "size": 1
+ },
+ "CGIF2": {
+ "description": "Channel 2 Global interrupt\n clear",
+ "offset": 4,
+ "size": 1
+ },
+ "CTCIF2": {
+ "description": "Channel 2 Transfer Complete\n clear",
+ "offset": 5,
+ "size": 1
+ },
+ "CHTIF2": {
+ "description": "Channel 2 Half Transfer\n clear",
+ "offset": 6,
+ "size": 1
+ },
+ "CTEIF2": {
+ "description": "Channel 2 Transfer Error\n clear",
+ "offset": 7,
+ "size": 1
+ },
+ "CGIF3": {
+ "description": "Channel 3 Global interrupt\n clear",
+ "offset": 8,
+ "size": 1
+ },
+ "CTCIF3": {
+ "description": "Channel 3 Transfer Complete\n clear",
+ "offset": 9,
+ "size": 1
+ },
+ "CHTIF3": {
+ "description": "Channel 3 Half Transfer\n clear",
+ "offset": 10,
+ "size": 1
+ },
+ "CTEIF3": {
+ "description": "Channel 3 Transfer Error\n clear",
+ "offset": 11,
+ "size": 1
+ },
+ "CGIF4": {
+ "description": "Channel 4 Global interrupt\n clear",
+ "offset": 12,
+ "size": 1
+ },
+ "CTCIF4": {
+ "description": "Channel 4 Transfer Complete\n clear",
+ "offset": 13,
+ "size": 1
+ },
+ "CHTIF4": {
+ "description": "Channel 4 Half Transfer\n clear",
+ "offset": 14,
+ "size": 1
+ },
+ "CTEIF4": {
+ "description": "Channel 4 Transfer Error\n clear",
+ "offset": 15,
+ "size": 1
+ },
+ "CGIF5": {
+ "description": "Channel 5 Global interrupt\n clear",
+ "offset": 16,
+ "size": 1
+ },
+ "CTCIF5": {
+ "description": "Channel 5 Transfer Complete\n clear",
+ "offset": 17,
+ "size": 1
+ },
+ "CHTIF5": {
+ "description": "Channel 5 Half Transfer\n clear",
+ "offset": 18,
+ "size": 1
+ },
+ "CTEIF5": {
+ "description": "Channel 5 Transfer Error\n clear",
+ "offset": 19,
+ "size": 1
+ },
+ "CGIF6": {
+ "description": "Channel 6 Global interrupt\n clear",
+ "offset": 20,
+ "size": 1
+ },
+ "CTCIF6": {
+ "description": "Channel 6 Transfer Complete\n clear",
+ "offset": 21,
+ "size": 1
+ },
+ "CHTIF6": {
+ "description": "Channel 6 Half Transfer\n clear",
+ "offset": 22,
+ "size": 1
+ },
+ "CTEIF6": {
+ "description": "Channel 6 Transfer Error\n clear",
+ "offset": 23,
+ "size": 1
+ },
+ "CGIF7": {
+ "description": "Channel 7 Global interrupt\n clear",
+ "offset": 24,
+ "size": 1
+ },
+ "CTCIF7": {
+ "description": "Channel 7 Transfer Complete\n clear",
+ "offset": 25,
+ "size": 1
+ },
+ "CHTIF7": {
+ "description": "Channel 7 Half Transfer\n clear",
+ "offset": 26,
+ "size": 1
+ },
+ "CTEIF7": {
+ "description": "Channel 7 Transfer Error\n clear",
+ "offset": 27,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCR1": {
+ "description": "DMA channel configuration register\n (DMA_CCR)",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EN": {
+ "description": "Channel enable",
+ "offset": 0,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half Transfer interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 4,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 5,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 6,
+ "size": 1
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 7,
+ "size": 1
+ },
+ "PSIZE": {
+ "description": "Peripheral size",
+ "offset": 8,
+ "size": 2
+ },
+ "MSIZE": {
+ "description": "Memory size",
+ "offset": 10,
+ "size": 2
+ },
+ "PL": {
+ "description": "Channel Priority level",
+ "offset": 12,
+ "size": 2
+ },
+ "MEM2MEM": {
+ "description": "Memory to memory mode",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNDTR1": {
+ "description": "DMA channel 1 number of data\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data to transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CPAR1": {
+ "description": "DMA channel 1 peripheral address\n register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CMAR1": {
+ "description": "DMA channel 1 memory address\n register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MA": {
+ "description": "Memory address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CCR2": {
+ "description": "DMA channel configuration register\n (DMA_CCR)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EN": {
+ "description": "Channel enable",
+ "offset": 0,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half Transfer interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 4,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 5,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 6,
+ "size": 1
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 7,
+ "size": 1
+ },
+ "PSIZE": {
+ "description": "Peripheral size",
+ "offset": 8,
+ "size": 2
+ },
+ "MSIZE": {
+ "description": "Memory size",
+ "offset": 10,
+ "size": 2
+ },
+ "PL": {
+ "description": "Channel Priority level",
+ "offset": 12,
+ "size": 2
+ },
+ "MEM2MEM": {
+ "description": "Memory to memory mode",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNDTR2": {
+ "description": "DMA channel 2 number of data\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data to transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CPAR2": {
+ "description": "DMA channel 2 peripheral address\n register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CMAR2": {
+ "description": "DMA channel 2 memory address\n register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MA": {
+ "description": "Memory address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CCR3": {
+ "description": "DMA channel configuration register\n (DMA_CCR)",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EN": {
+ "description": "Channel enable",
+ "offset": 0,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half Transfer interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 4,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 5,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 6,
+ "size": 1
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 7,
+ "size": 1
+ },
+ "PSIZE": {
+ "description": "Peripheral size",
+ "offset": 8,
+ "size": 2
+ },
+ "MSIZE": {
+ "description": "Memory size",
+ "offset": 10,
+ "size": 2
+ },
+ "PL": {
+ "description": "Channel Priority level",
+ "offset": 12,
+ "size": 2
+ },
+ "MEM2MEM": {
+ "description": "Memory to memory mode",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNDTR3": {
+ "description": "DMA channel 3 number of data\n register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data to transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CPAR3": {
+ "description": "DMA channel 3 peripheral address\n register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CMAR3": {
+ "description": "DMA channel 3 memory address\n register",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MA": {
+ "description": "Memory address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CCR4": {
+ "description": "DMA channel configuration register\n (DMA_CCR)",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EN": {
+ "description": "Channel enable",
+ "offset": 0,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half Transfer interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 4,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 5,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 6,
+ "size": 1
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 7,
+ "size": 1
+ },
+ "PSIZE": {
+ "description": "Peripheral size",
+ "offset": 8,
+ "size": 2
+ },
+ "MSIZE": {
+ "description": "Memory size",
+ "offset": 10,
+ "size": 2
+ },
+ "PL": {
+ "description": "Channel Priority level",
+ "offset": 12,
+ "size": 2
+ },
+ "MEM2MEM": {
+ "description": "Memory to memory mode",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNDTR4": {
+ "description": "DMA channel 4 number of data\n register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data to transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CPAR4": {
+ "description": "DMA channel 4 peripheral address\n register",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CMAR4": {
+ "description": "DMA channel 4 memory address\n register",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MA": {
+ "description": "Memory address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CCR5": {
+ "description": "DMA channel configuration register\n (DMA_CCR)",
+ "offset": 88,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EN": {
+ "description": "Channel enable",
+ "offset": 0,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half Transfer interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 4,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 5,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 6,
+ "size": 1
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 7,
+ "size": 1
+ },
+ "PSIZE": {
+ "description": "Peripheral size",
+ "offset": 8,
+ "size": 2
+ },
+ "MSIZE": {
+ "description": "Memory size",
+ "offset": 10,
+ "size": 2
+ },
+ "PL": {
+ "description": "Channel Priority level",
+ "offset": 12,
+ "size": 2
+ },
+ "MEM2MEM": {
+ "description": "Memory to memory mode",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNDTR5": {
+ "description": "DMA channel 5 number of data\n register",
+ "offset": 92,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data to transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CPAR5": {
+ "description": "DMA channel 5 peripheral address\n register",
+ "offset": 96,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CMAR5": {
+ "description": "DMA channel 5 memory address\n register",
+ "offset": 100,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MA": {
+ "description": "Memory address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CCR6": {
+ "description": "DMA channel configuration register\n (DMA_CCR)",
+ "offset": 108,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EN": {
+ "description": "Channel enable",
+ "offset": 0,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half Transfer interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 4,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 5,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 6,
+ "size": 1
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 7,
+ "size": 1
+ },
+ "PSIZE": {
+ "description": "Peripheral size",
+ "offset": 8,
+ "size": 2
+ },
+ "MSIZE": {
+ "description": "Memory size",
+ "offset": 10,
+ "size": 2
+ },
+ "PL": {
+ "description": "Channel Priority level",
+ "offset": 12,
+ "size": 2
+ },
+ "MEM2MEM": {
+ "description": "Memory to memory mode",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNDTR6": {
+ "description": "DMA channel 6 number of data\n register",
+ "offset": 112,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data to transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CPAR6": {
+ "description": "DMA channel 6 peripheral address\n register",
+ "offset": 116,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CMAR6": {
+ "description": "DMA channel 6 memory address\n register",
+ "offset": 120,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MA": {
+ "description": "Memory address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CCR7": {
+ "description": "DMA channel configuration register\n (DMA_CCR)",
+ "offset": 128,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EN": {
+ "description": "Channel enable",
+ "offset": 0,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half Transfer interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 4,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 5,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 6,
+ "size": 1
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 7,
+ "size": 1
+ },
+ "PSIZE": {
+ "description": "Peripheral size",
+ "offset": 8,
+ "size": 2
+ },
+ "MSIZE": {
+ "description": "Memory size",
+ "offset": 10,
+ "size": 2
+ },
+ "PL": {
+ "description": "Channel Priority level",
+ "offset": 12,
+ "size": 2
+ },
+ "MEM2MEM": {
+ "description": "Memory to memory mode",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNDTR7": {
+ "description": "DMA channel 7 number of data\n register",
+ "offset": 132,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data to transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CPAR7": {
+ "description": "DMA channel 7 peripheral address\n register",
+ "offset": 136,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CMAR7": {
+ "description": "DMA channel 7 memory address\n register",
+ "offset": 140,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MA": {
+ "description": "Memory address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "FPU": {
+ "description": "Floting point unit",
+ "children": {
+ "registers": {
+ "FPCCR": {
+ "description": "Floating-point context control\n register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LSPACT": {
+ "description": "LSPACT",
+ "offset": 0,
+ "size": 1
+ },
+ "USER": {
+ "description": "USER",
+ "offset": 1,
+ "size": 1
+ },
+ "THREAD": {
+ "description": "THREAD",
+ "offset": 3,
+ "size": 1
+ },
+ "HFRDY": {
+ "description": "HFRDY",
+ "offset": 4,
+ "size": 1
+ },
+ "MMRDY": {
+ "description": "MMRDY",
+ "offset": 5,
+ "size": 1
+ },
+ "BFRDY": {
+ "description": "BFRDY",
+ "offset": 6,
+ "size": 1
+ },
+ "MONRDY": {
+ "description": "MONRDY",
+ "offset": 8,
+ "size": 1
+ },
+ "LSPEN": {
+ "description": "LSPEN",
+ "offset": 30,
+ "size": 1
+ },
+ "ASPEN": {
+ "description": "ASPEN",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FPCAR": {
+ "description": "Floating-point context address\n register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ADDRESS": {
+ "description": "Location of unpopulated\n floating-point",
+ "offset": 3,
+ "size": 29
+ }
+ }
+ }
+ },
+ "FPSCR": {
+ "description": "Floating-point status control\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IOC": {
+ "description": "Invalid operation cumulative exception\n bit",
+ "offset": 0,
+ "size": 1
+ },
+ "DZC": {
+ "description": "Division by zero cumulative exception\n bit.",
+ "offset": 1,
+ "size": 1
+ },
+ "OFC": {
+ "description": "Overflow cumulative exception\n bit",
+ "offset": 2,
+ "size": 1
+ },
+ "UFC": {
+ "description": "Underflow cumulative exception\n bit",
+ "offset": 3,
+ "size": 1
+ },
+ "IXC": {
+ "description": "Inexact cumulative exception\n bit",
+ "offset": 4,
+ "size": 1
+ },
+ "IDC": {
+ "description": "Input denormal cumulative exception\n bit.",
+ "offset": 7,
+ "size": 1
+ },
+ "RMode": {
+ "description": "Rounding Mode control\n field",
+ "offset": 22,
+ "size": 2
+ },
+ "FZ": {
+ "description": "Flush-to-zero mode control\n bit:",
+ "offset": 24,
+ "size": 1
+ },
+ "DN": {
+ "description": "Default NaN mode control\n bit",
+ "offset": 25,
+ "size": 1
+ },
+ "AHP": {
+ "description": "Alternative half-precision control\n bit",
+ "offset": 26,
+ "size": 1
+ },
+ "V": {
+ "description": "Overflow condition code\n flag",
+ "offset": 28,
+ "size": 1
+ },
+ "C": {
+ "description": "Carry condition code flag",
+ "offset": 29,
+ "size": 1
+ },
+ "Z": {
+ "description": "Zero condition code flag",
+ "offset": 30,
+ "size": 1
+ },
+ "N": {
+ "description": "Negative condition code\n flag",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "TIM2": {
+ "description": "General purpose timer",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CEN": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ },
+ "UDIS": {
+ "description": "Update disable",
+ "offset": 1,
+ "size": 1
+ },
+ "URS": {
+ "description": "Update request source",
+ "offset": 2,
+ "size": 1
+ },
+ "OPM": {
+ "description": "One-pulse mode",
+ "offset": 3,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Direction",
+ "offset": 4,
+ "size": 1
+ },
+ "CMS": {
+ "description": "Center-aligned mode\n selection",
+ "offset": 5,
+ "size": 2
+ },
+ "ARPE": {
+ "description": "Auto-reload preload enable",
+ "offset": 7,
+ "size": 1
+ },
+ "CKD": {
+ "description": "Clock division",
+ "offset": 8,
+ "size": 2
+ },
+ "UIFREMAP": {
+ "description": "UIF status bit remapping",
+ "offset": 11,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TI1S": {
+ "description": "TI1 selection",
+ "offset": 7,
+ "size": 1
+ },
+ "MMS": {
+ "description": "Master mode selection",
+ "offset": 4,
+ "size": 3
+ },
+ "CCDS": {
+ "description": "Capture/compare DMA\n selection",
+ "offset": 3,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SMCR": {
+ "description": "slave mode control register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SMS": {
+ "description": "Slave mode selection",
+ "offset": 0,
+ "size": 3
+ },
+ "OCCS": {
+ "description": "OCREF clear selection",
+ "offset": 3,
+ "size": 1
+ },
+ "TS": {
+ "description": "Trigger selection",
+ "offset": 4,
+ "size": 3
+ },
+ "MSM": {
+ "description": "Master/Slave mode",
+ "offset": 7,
+ "size": 1
+ },
+ "ETF": {
+ "description": "External trigger filter",
+ "offset": 8,
+ "size": 4
+ },
+ "ETPS": {
+ "description": "External trigger prescaler",
+ "offset": 12,
+ "size": 2
+ },
+ "ECE": {
+ "description": "External clock enable",
+ "offset": 14,
+ "size": 1
+ },
+ "ETP": {
+ "description": "External trigger polarity",
+ "offset": 15,
+ "size": 1
+ },
+ "SMS_3": {
+ "description": "Slave mode selection bit3",
+ "offset": 16,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DIER": {
+ "description": "DMA/Interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TDE": {
+ "description": "Trigger DMA request enable",
+ "offset": 14,
+ "size": 1
+ },
+ "CC4DE": {
+ "description": "Capture/Compare 4 DMA request\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3DE": {
+ "description": "Capture/Compare 3 DMA request\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "CC2DE": {
+ "description": "Capture/Compare 2 DMA request\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC1DE": {
+ "description": "Capture/Compare 1 DMA request\n enable",
+ "offset": 9,
+ "size": 1
+ },
+ "UDE": {
+ "description": "Update DMA request enable",
+ "offset": 8,
+ "size": 1
+ },
+ "TIE": {
+ "description": "Trigger interrupt enable",
+ "offset": 6,
+ "size": 1
+ },
+ "CC4IE": {
+ "description": "Capture/Compare 4 interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3IE": {
+ "description": "Capture/Compare 3 interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2IE": {
+ "description": "Capture/Compare 2 interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IE": {
+ "description": "Capture/Compare 1 interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "UIE": {
+ "description": "Update interrupt enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC4OF": {
+ "description": "Capture/Compare 4 overcapture\n flag",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3OF": {
+ "description": "Capture/Compare 3 overcapture\n flag",
+ "offset": 11,
+ "size": 1
+ },
+ "CC2OF": {
+ "description": "Capture/compare 2 overcapture\n flag",
+ "offset": 10,
+ "size": 1
+ },
+ "CC1OF": {
+ "description": "Capture/Compare 1 overcapture\n flag",
+ "offset": 9,
+ "size": 1
+ },
+ "TIF": {
+ "description": "Trigger interrupt flag",
+ "offset": 6,
+ "size": 1
+ },
+ "CC4IF": {
+ "description": "Capture/Compare 4 interrupt\n flag",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3IF": {
+ "description": "Capture/Compare 3 interrupt\n flag",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2IF": {
+ "description": "Capture/Compare 2 interrupt\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IF": {
+ "description": "Capture/compare 1 interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "UIF": {
+ "description": "Update interrupt flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EGR": {
+ "description": "event generation register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "TG": {
+ "description": "Trigger generation",
+ "offset": 6,
+ "size": 1
+ },
+ "CC4G": {
+ "description": "Capture/compare 4\n generation",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3G": {
+ "description": "Capture/compare 3\n generation",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2G": {
+ "description": "Capture/compare 2\n generation",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1G": {
+ "description": "Capture/compare 1\n generation",
+ "offset": 1,
+ "size": 1
+ },
+ "UG": {
+ "description": "Update generation",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Output": {
+ "description": "capture/compare mode register 1 (output\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ },
+ "OC1FE": {
+ "description": "Output compare 1 fast\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "OC1PE": {
+ "description": "Output compare 1 preload\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "OC1M": {
+ "description": "Output compare 1 mode",
+ "offset": 4,
+ "size": 3
+ },
+ "OC1CE": {
+ "description": "Output compare 1 clear\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "CC2S": {
+ "description": "Capture/Compare 2\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "OC2FE": {
+ "description": "Output compare 2 fast\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "OC2PE": {
+ "description": "Output compare 2 preload\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "OC2M": {
+ "description": "Output compare 2 mode",
+ "offset": 12,
+ "size": 3
+ },
+ "OC2CE": {
+ "description": "Output compare 2 clear\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "OC1M_3": {
+ "description": "Output compare 1 mode bit\n 3",
+ "offset": 16,
+ "size": 1
+ },
+ "OC2M_3": {
+ "description": "Output compare 2 mode bit\n 3",
+ "offset": 24,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Input": {
+ "description": "capture/compare mode register 1 (input\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC2F": {
+ "description": "Input capture 2 filter",
+ "offset": 12,
+ "size": 4
+ },
+ "IC2PSC": {
+ "description": "Input capture 2 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC2S": {
+ "description": "Capture/compare 2\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC1F": {
+ "description": "Input capture 1 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "IC1PSC": {
+ "description": "Input capture 1 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR2_Output": {
+ "description": "capture/compare mode register 2 (output\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC3S": {
+ "description": "Capture/Compare 3\n selection",
+ "offset": 0,
+ "size": 2
+ },
+ "OC3FE": {
+ "description": "Output compare 3 fast\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "OC3PE": {
+ "description": "Output compare 3 preload\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "OC3M": {
+ "description": "Output compare 3 mode",
+ "offset": 4,
+ "size": 3
+ },
+ "OC3CE": {
+ "description": "Output compare 3 clear\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "CC4S": {
+ "description": "Capture/Compare 4\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "OC4FE": {
+ "description": "Output compare 4 fast\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "OC4PE": {
+ "description": "Output compare 4 preload\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "OC4M": {
+ "description": "Output compare 4 mode",
+ "offset": 12,
+ "size": 3
+ },
+ "O24CE": {
+ "description": "Output compare 4 clear\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "OC3M_3": {
+ "description": "Output compare 3 mode bit3",
+ "offset": 16,
+ "size": 1
+ },
+ "OC4M_3": {
+ "description": "Output compare 4 mode bit3",
+ "offset": 24,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR2_Input": {
+ "description": "capture/compare mode register 2 (input\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC4F": {
+ "description": "Input capture 4 filter",
+ "offset": 12,
+ "size": 4
+ },
+ "IC4PSC": {
+ "description": "Input capture 4 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC4S": {
+ "description": "Capture/Compare 4\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC3F": {
+ "description": "Input capture 3 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "IC3PSC": {
+ "description": "Input capture 3 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC3S": {
+ "description": "Capture/Compare 3\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCER": {
+ "description": "capture/compare enable\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC1E": {
+ "description": "Capture/Compare 1 output\n enable",
+ "offset": 0,
+ "size": 1
+ },
+ "CC1P": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 1,
+ "size": 1
+ },
+ "CC1NP": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2E": {
+ "description": "Capture/Compare 2 output\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC2P": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 5,
+ "size": 1
+ },
+ "CC2NP": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 7,
+ "size": 1
+ },
+ "CC3E": {
+ "description": "Capture/Compare 3 output\n enable",
+ "offset": 8,
+ "size": 1
+ },
+ "CC3P": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 9,
+ "size": 1
+ },
+ "CC3NP": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 11,
+ "size": 1
+ },
+ "CC4E": {
+ "description": "Capture/Compare 4 output\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "CC4P": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 13,
+ "size": 1
+ },
+ "CC4NP": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 15,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNT": {
+ "description": "counter",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNTL": {
+ "description": "Low counter value",
+ "offset": 0,
+ "size": 16
+ },
+ "CNTH": {
+ "description": "High counter value",
+ "offset": 16,
+ "size": 15
+ },
+ "CNT_or_UIFCPY": {
+ "description": "if IUFREMAP=0 than CNT with read write\n access else UIFCPY with read only\n access",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PSC": {
+ "description": "prescaler",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ARR": {
+ "description": "auto-reload register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARRL": {
+ "description": "Low Auto-reload value",
+ "offset": 0,
+ "size": 16
+ },
+ "ARRH": {
+ "description": "High Auto-reload value",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR1": {
+ "description": "capture/compare register 1",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR1L": {
+ "description": "Low Capture/Compare 1\n value",
+ "offset": 0,
+ "size": 16
+ },
+ "CCR1H": {
+ "description": "High Capture/Compare 1 value (on\n TIM2)",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR2": {
+ "description": "capture/compare register 2",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR2L": {
+ "description": "Low Capture/Compare 2\n value",
+ "offset": 0,
+ "size": 16
+ },
+ "CCR2H": {
+ "description": "High Capture/Compare 2 value (on\n TIM2)",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR3": {
+ "description": "capture/compare register 3",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR3L": {
+ "description": "Low Capture/Compare value",
+ "offset": 0,
+ "size": 16
+ },
+ "CCR3H": {
+ "description": "High Capture/Compare value (on\n TIM2)",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR4": {
+ "description": "capture/compare register 4",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR4L": {
+ "description": "Low Capture/Compare value",
+ "offset": 0,
+ "size": 16
+ },
+ "CCR4H": {
+ "description": "High Capture/Compare value (on\n TIM2)",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DCR": {
+ "description": "DMA control register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBL": {
+ "description": "DMA burst length",
+ "offset": 8,
+ "size": 5
+ },
+ "DBA": {
+ "description": "DMA base address",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "DMAR": {
+ "description": "DMA address for full transfer",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAB": {
+ "description": "DMA register for burst\n accesses",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "NVIC": {
+ "description": "Nested Vectored Interrupt\n Controller",
+ "children": {
+ "registers": {
+ "ISER0": {
+ "description": "Interrupt Set-Enable Register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SETENA": {
+ "description": "SETENA",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ISER1": {
+ "description": "Interrupt Set-Enable Register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SETENA": {
+ "description": "SETENA",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ISER2": {
+ "description": "Interrupt Set-Enable Register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SETENA": {
+ "description": "SETENA",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ICER0": {
+ "description": "Interrupt Clear-Enable\n Register",
+ "offset": 128,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CLRENA": {
+ "description": "CLRENA",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ICER1": {
+ "description": "Interrupt Clear-Enable\n Register",
+ "offset": 132,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CLRENA": {
+ "description": "CLRENA",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ICER2": {
+ "description": "Interrupt Clear-Enable\n Register",
+ "offset": 136,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CLRENA": {
+ "description": "CLRENA",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ISPR0": {
+ "description": "Interrupt Set-Pending Register",
+ "offset": 256,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SETPEND": {
+ "description": "SETPEND",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ISPR1": {
+ "description": "Interrupt Set-Pending Register",
+ "offset": 260,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SETPEND": {
+ "description": "SETPEND",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ISPR2": {
+ "description": "Interrupt Set-Pending Register",
+ "offset": 264,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SETPEND": {
+ "description": "SETPEND",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ICPR0": {
+ "description": "Interrupt Clear-Pending\n Register",
+ "offset": 384,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CLRPEND": {
+ "description": "CLRPEND",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ICPR1": {
+ "description": "Interrupt Clear-Pending\n Register",
+ "offset": 388,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CLRPEND": {
+ "description": "CLRPEND",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ICPR2": {
+ "description": "Interrupt Clear-Pending\n Register",
+ "offset": 392,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CLRPEND": {
+ "description": "CLRPEND",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "IABR0": {
+ "description": "Interrupt Active Bit Register",
+ "offset": 512,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "ACTIVE": {
+ "description": "ACTIVE",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "IABR1": {
+ "description": "Interrupt Active Bit Register",
+ "offset": 516,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "ACTIVE": {
+ "description": "ACTIVE",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "IABR2": {
+ "description": "Interrupt Active Bit Register",
+ "offset": 520,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "ACTIVE": {
+ "description": "ACTIVE",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "IPR0": {
+ "description": "Interrupt Priority Register",
+ "offset": 768,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR1": {
+ "description": "Interrupt Priority Register",
+ "offset": 772,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR2": {
+ "description": "Interrupt Priority Register",
+ "offset": 776,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR3": {
+ "description": "Interrupt Priority Register",
+ "offset": 780,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR4": {
+ "description": "Interrupt Priority Register",
+ "offset": 784,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR5": {
+ "description": "Interrupt Priority Register",
+ "offset": 788,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR6": {
+ "description": "Interrupt Priority Register",
+ "offset": 792,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR7": {
+ "description": "Interrupt Priority Register",
+ "offset": 796,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR8": {
+ "description": "Interrupt Priority Register",
+ "offset": 800,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR9": {
+ "description": "Interrupt Priority Register",
+ "offset": 804,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR10": {
+ "description": "Interrupt Priority Register",
+ "offset": 808,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR11": {
+ "description": "Interrupt Priority Register",
+ "offset": 812,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR12": {
+ "description": "Interrupt Priority Register",
+ "offset": 816,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR13": {
+ "description": "Interrupt Priority Register",
+ "offset": 820,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR14": {
+ "description": "Interrupt Priority Register",
+ "offset": 824,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR15": {
+ "description": "Interrupt Priority Register",
+ "offset": 828,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR16": {
+ "description": "Interrupt Priority Register",
+ "offset": 832,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR17": {
+ "description": "Interrupt Priority Register",
+ "offset": 836,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR18": {
+ "description": "Interrupt Priority Register",
+ "offset": 840,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR19": {
+ "description": "Interrupt Priority Register",
+ "offset": 844,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR20": {
+ "description": "Interrupt Priority Register",
+ "offset": 848,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "FMC": {
+ "description": "Flexible memory controller",
+ "children": {
+ "registers": {
+ "BCR1": {
+ "description": "SRAM/NOR-Flash chip-select control register\n 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 12496,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCLKEN": {
+ "description": "CCLKEN",
+ "offset": 20,
+ "size": 1
+ },
+ "CBURSTRW": {
+ "description": "CBURSTRW",
+ "offset": 19,
+ "size": 1
+ },
+ "ASYNCWAIT": {
+ "description": "ASYNCWAIT",
+ "offset": 15,
+ "size": 1
+ },
+ "EXTMOD": {
+ "description": "EXTMOD",
+ "offset": 14,
+ "size": 1
+ },
+ "WAITEN": {
+ "description": "WAITEN",
+ "offset": 13,
+ "size": 1
+ },
+ "WREN": {
+ "description": "WREN",
+ "offset": 12,
+ "size": 1
+ },
+ "WAITCFG": {
+ "description": "WAITCFG",
+ "offset": 11,
+ "size": 1
+ },
+ "WAITPOL": {
+ "description": "WAITPOL",
+ "offset": 9,
+ "size": 1
+ },
+ "BURSTEN": {
+ "description": "BURSTEN",
+ "offset": 8,
+ "size": 1
+ },
+ "FACCEN": {
+ "description": "FACCEN",
+ "offset": 6,
+ "size": 1
+ },
+ "MWID": {
+ "description": "MWID",
+ "offset": 4,
+ "size": 2
+ },
+ "MTYP": {
+ "description": "MTYP",
+ "offset": 2,
+ "size": 2
+ },
+ "MUXEN": {
+ "description": "MUXEN",
+ "offset": 1,
+ "size": 1
+ },
+ "MBKEN": {
+ "description": "MBKEN",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BTR1": {
+ "description": "SRAM/NOR-Flash chip-select timing register\n 1",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "BUSTURN": {
+ "description": "BUSTURN",
+ "offset": 16,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "BCR2": {
+ "description": "SRAM/NOR-Flash chip-select control register\n 2",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 12496,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CBURSTRW": {
+ "description": "CBURSTRW",
+ "offset": 19,
+ "size": 1
+ },
+ "ASYNCWAIT": {
+ "description": "ASYNCWAIT",
+ "offset": 15,
+ "size": 1
+ },
+ "EXTMOD": {
+ "description": "EXTMOD",
+ "offset": 14,
+ "size": 1
+ },
+ "WAITEN": {
+ "description": "WAITEN",
+ "offset": 13,
+ "size": 1
+ },
+ "WREN": {
+ "description": "WREN",
+ "offset": 12,
+ "size": 1
+ },
+ "WAITCFG": {
+ "description": "WAITCFG",
+ "offset": 11,
+ "size": 1
+ },
+ "WRAPMOD": {
+ "description": "WRAPMOD",
+ "offset": 10,
+ "size": 1
+ },
+ "WAITPOL": {
+ "description": "WAITPOL",
+ "offset": 9,
+ "size": 1
+ },
+ "BURSTEN": {
+ "description": "BURSTEN",
+ "offset": 8,
+ "size": 1
+ },
+ "FACCEN": {
+ "description": "FACCEN",
+ "offset": 6,
+ "size": 1
+ },
+ "MWID": {
+ "description": "MWID",
+ "offset": 4,
+ "size": 2
+ },
+ "MTYP": {
+ "description": "MTYP",
+ "offset": 2,
+ "size": 2
+ },
+ "MUXEN": {
+ "description": "MUXEN",
+ "offset": 1,
+ "size": 1
+ },
+ "MBKEN": {
+ "description": "MBKEN",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BTR2": {
+ "description": "SRAM/NOR-Flash chip-select timing register\n 2",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "BUSTURN": {
+ "description": "BUSTURN",
+ "offset": 16,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "BCR3": {
+ "description": "SRAM/NOR-Flash chip-select control register\n 3",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 12496,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CBURSTRW": {
+ "description": "CBURSTRW",
+ "offset": 19,
+ "size": 1
+ },
+ "ASYNCWAIT": {
+ "description": "ASYNCWAIT",
+ "offset": 15,
+ "size": 1
+ },
+ "EXTMOD": {
+ "description": "EXTMOD",
+ "offset": 14,
+ "size": 1
+ },
+ "WAITEN": {
+ "description": "WAITEN",
+ "offset": 13,
+ "size": 1
+ },
+ "WREN": {
+ "description": "WREN",
+ "offset": 12,
+ "size": 1
+ },
+ "WAITCFG": {
+ "description": "WAITCFG",
+ "offset": 11,
+ "size": 1
+ },
+ "WRAPMOD": {
+ "description": "WRAPMOD",
+ "offset": 10,
+ "size": 1
+ },
+ "WAITPOL": {
+ "description": "WAITPOL",
+ "offset": 9,
+ "size": 1
+ },
+ "BURSTEN": {
+ "description": "BURSTEN",
+ "offset": 8,
+ "size": 1
+ },
+ "FACCEN": {
+ "description": "FACCEN",
+ "offset": 6,
+ "size": 1
+ },
+ "MWID": {
+ "description": "MWID",
+ "offset": 4,
+ "size": 2
+ },
+ "MTYP": {
+ "description": "MTYP",
+ "offset": 2,
+ "size": 2
+ },
+ "MUXEN": {
+ "description": "MUXEN",
+ "offset": 1,
+ "size": 1
+ },
+ "MBKEN": {
+ "description": "MBKEN",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BTR3": {
+ "description": "SRAM/NOR-Flash chip-select timing register\n 3",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "BUSTURN": {
+ "description": "BUSTURN",
+ "offset": 16,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "BCR4": {
+ "description": "SRAM/NOR-Flash chip-select control register\n 4",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 12496,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CBURSTRW": {
+ "description": "CBURSTRW",
+ "offset": 19,
+ "size": 1
+ },
+ "ASYNCWAIT": {
+ "description": "ASYNCWAIT",
+ "offset": 15,
+ "size": 1
+ },
+ "EXTMOD": {
+ "description": "EXTMOD",
+ "offset": 14,
+ "size": 1
+ },
+ "WAITEN": {
+ "description": "WAITEN",
+ "offset": 13,
+ "size": 1
+ },
+ "WREN": {
+ "description": "WREN",
+ "offset": 12,
+ "size": 1
+ },
+ "WAITCFG": {
+ "description": "WAITCFG",
+ "offset": 11,
+ "size": 1
+ },
+ "WRAPMOD": {
+ "description": "WRAPMOD",
+ "offset": 10,
+ "size": 1
+ },
+ "WAITPOL": {
+ "description": "WAITPOL",
+ "offset": 9,
+ "size": 1
+ },
+ "BURSTEN": {
+ "description": "BURSTEN",
+ "offset": 8,
+ "size": 1
+ },
+ "FACCEN": {
+ "description": "FACCEN",
+ "offset": 6,
+ "size": 1
+ },
+ "MWID": {
+ "description": "MWID",
+ "offset": 4,
+ "size": 2
+ },
+ "MTYP": {
+ "description": "MTYP",
+ "offset": 2,
+ "size": 2
+ },
+ "MUXEN": {
+ "description": "MUXEN",
+ "offset": 1,
+ "size": 1
+ },
+ "MBKEN": {
+ "description": "MBKEN",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BTR4": {
+ "description": "SRAM/NOR-Flash chip-select timing register\n 4",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "BUSTURN": {
+ "description": "BUSTURN",
+ "offset": 16,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "PCR2": {
+ "description": "PC Card/NAND Flash control register\n 2",
+ "offset": 96,
+ "size": 32,
+ "reset_value": 24,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ECCPS": {
+ "description": "ECCPS",
+ "offset": 17,
+ "size": 3
+ },
+ "TAR": {
+ "description": "TAR",
+ "offset": 13,
+ "size": 4
+ },
+ "TCLR": {
+ "description": "TCLR",
+ "offset": 9,
+ "size": 4
+ },
+ "ECCEN": {
+ "description": "ECCEN",
+ "offset": 6,
+ "size": 1
+ },
+ "PWID": {
+ "description": "PWID",
+ "offset": 4,
+ "size": 2
+ },
+ "PTYP": {
+ "description": "PTYP",
+ "offset": 3,
+ "size": 1
+ },
+ "PBKEN": {
+ "description": "PBKEN",
+ "offset": 2,
+ "size": 1
+ },
+ "PWAITEN": {
+ "description": "PWAITEN",
+ "offset": 1,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR2": {
+ "description": "FIFO status and interrupt register\n 2",
+ "offset": 100,
+ "size": 32,
+ "reset_value": 64,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEMPT": {
+ "description": "FEMPT",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "IFEN": {
+ "description": "IFEN",
+ "offset": 5,
+ "size": 1
+ },
+ "ILEN": {
+ "description": "ILEN",
+ "offset": 4,
+ "size": 1
+ },
+ "IREN": {
+ "description": "IREN",
+ "offset": 3,
+ "size": 1
+ },
+ "IFS": {
+ "description": "IFS",
+ "offset": 2,
+ "size": 1
+ },
+ "ILS": {
+ "description": "ILS",
+ "offset": 1,
+ "size": 1
+ },
+ "IRS": {
+ "description": "IRS",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PMEM2": {
+ "description": "Common memory space timing register\n 2",
+ "offset": 104,
+ "size": 32,
+ "reset_value": 4244438268,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MEMHIZx": {
+ "description": "MEMHIZx",
+ "offset": 24,
+ "size": 8
+ },
+ "MEMHOLDx": {
+ "description": "MEMHOLDx",
+ "offset": 16,
+ "size": 8
+ },
+ "MEMWAITx": {
+ "description": "MEMWAITx",
+ "offset": 8,
+ "size": 8
+ },
+ "MEMSETx": {
+ "description": "MEMSETx",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "PATT2": {
+ "description": "Attribute memory space timing register\n 2",
+ "offset": 108,
+ "size": 32,
+ "reset_value": 4244438268,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ATTHIZx": {
+ "description": "ATTHIZx",
+ "offset": 24,
+ "size": 8
+ },
+ "ATTHOLDx": {
+ "description": "ATTHOLDx",
+ "offset": 16,
+ "size": 8
+ },
+ "ATTWAITx": {
+ "description": "ATTWAITx",
+ "offset": 8,
+ "size": 8
+ },
+ "ATTSETx": {
+ "description": "ATTSETx",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "ECCR2": {
+ "description": "ECC result register 2",
+ "offset": 116,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "ECCx": {
+ "description": "ECCx",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "PCR3": {
+ "description": "PC Card/NAND Flash control register\n 3",
+ "offset": 128,
+ "size": 32,
+ "reset_value": 24,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ECCPS": {
+ "description": "ECCPS",
+ "offset": 17,
+ "size": 3
+ },
+ "TAR": {
+ "description": "TAR",
+ "offset": 13,
+ "size": 4
+ },
+ "TCLR": {
+ "description": "TCLR",
+ "offset": 9,
+ "size": 4
+ },
+ "ECCEN": {
+ "description": "ECCEN",
+ "offset": 6,
+ "size": 1
+ },
+ "PWID": {
+ "description": "PWID",
+ "offset": 4,
+ "size": 2
+ },
+ "PTYP": {
+ "description": "PTYP",
+ "offset": 3,
+ "size": 1
+ },
+ "PBKEN": {
+ "description": "PBKEN",
+ "offset": 2,
+ "size": 1
+ },
+ "PWAITEN": {
+ "description": "PWAITEN",
+ "offset": 1,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR3": {
+ "description": "FIFO status and interrupt register\n 3",
+ "offset": 132,
+ "size": 32,
+ "reset_value": 64,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEMPT": {
+ "description": "FEMPT",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "IFEN": {
+ "description": "IFEN",
+ "offset": 5,
+ "size": 1
+ },
+ "ILEN": {
+ "description": "ILEN",
+ "offset": 4,
+ "size": 1
+ },
+ "IREN": {
+ "description": "IREN",
+ "offset": 3,
+ "size": 1
+ },
+ "IFS": {
+ "description": "IFS",
+ "offset": 2,
+ "size": 1
+ },
+ "ILS": {
+ "description": "ILS",
+ "offset": 1,
+ "size": 1
+ },
+ "IRS": {
+ "description": "IRS",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PMEM3": {
+ "description": "Common memory space timing register\n 3",
+ "offset": 136,
+ "size": 32,
+ "reset_value": 4244438268,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MEMHIZx": {
+ "description": "MEMHIZx",
+ "offset": 24,
+ "size": 8
+ },
+ "MEMHOLDx": {
+ "description": "MEMHOLDx",
+ "offset": 16,
+ "size": 8
+ },
+ "MEMWAITx": {
+ "description": "MEMWAITx",
+ "offset": 8,
+ "size": 8
+ },
+ "MEMSETx": {
+ "description": "MEMSETx",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "PATT3": {
+ "description": "Attribute memory space timing register\n 3",
+ "offset": 140,
+ "size": 32,
+ "reset_value": 4244438268,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ATTHIZx": {
+ "description": "ATTHIZx",
+ "offset": 24,
+ "size": 8
+ },
+ "ATTHOLDx": {
+ "description": "ATTHOLDx",
+ "offset": 16,
+ "size": 8
+ },
+ "ATTWAITx": {
+ "description": "ATTWAITx",
+ "offset": 8,
+ "size": 8
+ },
+ "ATTSETx": {
+ "description": "ATTSETx",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "ECCR3": {
+ "description": "ECC result register 3",
+ "offset": 148,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "ECCx": {
+ "description": "ECCx",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "PCR4": {
+ "description": "PC Card/NAND Flash control register\n 4",
+ "offset": 160,
+ "size": 32,
+ "reset_value": 24,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ECCPS": {
+ "description": "ECCPS",
+ "offset": 17,
+ "size": 3
+ },
+ "TAR": {
+ "description": "TAR",
+ "offset": 13,
+ "size": 4
+ },
+ "TCLR": {
+ "description": "TCLR",
+ "offset": 9,
+ "size": 4
+ },
+ "ECCEN": {
+ "description": "ECCEN",
+ "offset": 6,
+ "size": 1
+ },
+ "PWID": {
+ "description": "PWID",
+ "offset": 4,
+ "size": 2
+ },
+ "PTYP": {
+ "description": "PTYP",
+ "offset": 3,
+ "size": 1
+ },
+ "PBKEN": {
+ "description": "PBKEN",
+ "offset": 2,
+ "size": 1
+ },
+ "PWAITEN": {
+ "description": "PWAITEN",
+ "offset": 1,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR4": {
+ "description": "FIFO status and interrupt register\n 4",
+ "offset": 164,
+ "size": 32,
+ "reset_value": 64,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEMPT": {
+ "description": "FEMPT",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "IFEN": {
+ "description": "IFEN",
+ "offset": 5,
+ "size": 1
+ },
+ "ILEN": {
+ "description": "ILEN",
+ "offset": 4,
+ "size": 1
+ },
+ "IREN": {
+ "description": "IREN",
+ "offset": 3,
+ "size": 1
+ },
+ "IFS": {
+ "description": "IFS",
+ "offset": 2,
+ "size": 1
+ },
+ "ILS": {
+ "description": "ILS",
+ "offset": 1,
+ "size": 1
+ },
+ "IRS": {
+ "description": "IRS",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PMEM4": {
+ "description": "Common memory space timing register\n 4",
+ "offset": 168,
+ "size": 32,
+ "reset_value": 4244438268,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MEMHIZx": {
+ "description": "MEMHIZx",
+ "offset": 24,
+ "size": 8
+ },
+ "MEMHOLDx": {
+ "description": "MEMHOLDx",
+ "offset": 16,
+ "size": 8
+ },
+ "MEMWAITx": {
+ "description": "MEMWAITx",
+ "offset": 8,
+ "size": 8
+ },
+ "MEMSETx": {
+ "description": "MEMSETx",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "PATT4": {
+ "description": "Attribute memory space timing register\n 4",
+ "offset": 172,
+ "size": 32,
+ "reset_value": 4244438268,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ATTHIZx": {
+ "description": "ATTHIZx",
+ "offset": 24,
+ "size": 8
+ },
+ "ATTHOLDx": {
+ "description": "ATTHOLDx",
+ "offset": 16,
+ "size": 8
+ },
+ "ATTWAITx": {
+ "description": "ATTWAITx",
+ "offset": 8,
+ "size": 8
+ },
+ "ATTSETx": {
+ "description": "ATTSETx",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "PIO4": {
+ "description": "I/O space timing register 4",
+ "offset": 176,
+ "size": 32,
+ "reset_value": 4244438268,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IOHIZx": {
+ "description": "IOHIZx",
+ "offset": 24,
+ "size": 8
+ },
+ "IOHOLDx": {
+ "description": "IOHOLDx",
+ "offset": 16,
+ "size": 8
+ },
+ "IOWAITx": {
+ "description": "IOWAITx",
+ "offset": 8,
+ "size": 8
+ },
+ "IOSETx": {
+ "description": "IOSETx",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "BWTR1": {
+ "description": "SRAM/NOR-Flash write timing registers\n 1",
+ "offset": 260,
+ "size": 32,
+ "reset_value": 268435455,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "BUSTURN": {
+ "description": "Bus turnaround phase\n duration",
+ "offset": 16,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "BWTR2": {
+ "description": "SRAM/NOR-Flash write timing registers\n 2",
+ "offset": 268,
+ "size": 32,
+ "reset_value": 268435455,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "BUSTURN": {
+ "description": "Bus turnaround phase\n duration",
+ "offset": 16,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "BWTR3": {
+ "description": "SRAM/NOR-Flash write timing registers\n 3",
+ "offset": 276,
+ "size": 32,
+ "reset_value": 268435455,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "BUSTURN": {
+ "description": "Bus turnaround phase\n duration",
+ "offset": 16,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "BWTR4": {
+ "description": "SRAM/NOR-Flash write timing registers\n 4",
+ "offset": 284,
+ "size": 32,
+ "reset_value": 268435455,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "BUSTURN": {
+ "description": "Bus turnaround phase\n duration",
+ "offset": 16,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "TIM15": {
+ "description": "General purpose timers",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CEN": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ },
+ "UDIS": {
+ "description": "Update disable",
+ "offset": 1,
+ "size": 1
+ },
+ "URS": {
+ "description": "Update request source",
+ "offset": 2,
+ "size": 1
+ },
+ "OPM": {
+ "description": "One-pulse mode",
+ "offset": 3,
+ "size": 1
+ },
+ "ARPE": {
+ "description": "Auto-reload preload enable",
+ "offset": 7,
+ "size": 1
+ },
+ "CKD": {
+ "description": "Clock division",
+ "offset": 8,
+ "size": 2
+ },
+ "UIFREMAP": {
+ "description": "UIF status bit remapping",
+ "offset": 11,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCPC": {
+ "description": "Capture/compare preloaded\n control",
+ "offset": 0,
+ "size": 1
+ },
+ "CCUS": {
+ "description": "Capture/compare control update\n selection",
+ "offset": 2,
+ "size": 1
+ },
+ "CCDS": {
+ "description": "Capture/compare DMA\n selection",
+ "offset": 3,
+ "size": 1
+ },
+ "MMS": {
+ "description": "Master mode selection",
+ "offset": 4,
+ "size": 3
+ },
+ "TI1S": {
+ "description": "TI1 selection",
+ "offset": 7,
+ "size": 1
+ },
+ "OIS1": {
+ "description": "Output Idle state 1",
+ "offset": 8,
+ "size": 1
+ },
+ "OIS1N": {
+ "description": "Output Idle state 1",
+ "offset": 9,
+ "size": 1
+ },
+ "OIS2": {
+ "description": "Output Idle state 2",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SMCR": {
+ "description": "slave mode control register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SMS": {
+ "description": "Slave mode selection",
+ "offset": 0,
+ "size": 3
+ },
+ "TS": {
+ "description": "Trigger selection",
+ "offset": 4,
+ "size": 3
+ },
+ "MSM": {
+ "description": "Master/Slave mode",
+ "offset": 7,
+ "size": 1
+ },
+ "SMS_3": {
+ "description": "Slave mode selection bit 3",
+ "offset": 16,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DIER": {
+ "description": "DMA/Interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "UIE": {
+ "description": "Update interrupt enable",
+ "offset": 0,
+ "size": 1
+ },
+ "CC1IE": {
+ "description": "Capture/Compare 1 interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "CC2IE": {
+ "description": "Capture/Compare 2 interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "COMIE": {
+ "description": "COM interrupt enable",
+ "offset": 5,
+ "size": 1
+ },
+ "TIE": {
+ "description": "Trigger interrupt enable",
+ "offset": 6,
+ "size": 1
+ },
+ "BIE": {
+ "description": "Break interrupt enable",
+ "offset": 7,
+ "size": 1
+ },
+ "UDE": {
+ "description": "Update DMA request enable",
+ "offset": 8,
+ "size": 1
+ },
+ "CC1DE": {
+ "description": "Capture/Compare 1 DMA request\n enable",
+ "offset": 9,
+ "size": 1
+ },
+ "CC2DE": {
+ "description": "Capture/Compare 2 DMA request\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "COMDE": {
+ "description": "COM DMA request enable",
+ "offset": 13,
+ "size": 1
+ },
+ "TDE": {
+ "description": "Trigger DMA request enable",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC2OF": {
+ "description": "Capture/compare 2 overcapture\n flag",
+ "offset": 10,
+ "size": 1
+ },
+ "CC1OF": {
+ "description": "Capture/Compare 1 overcapture\n flag",
+ "offset": 9,
+ "size": 1
+ },
+ "BIF": {
+ "description": "Break interrupt flag",
+ "offset": 7,
+ "size": 1
+ },
+ "TIF": {
+ "description": "Trigger interrupt flag",
+ "offset": 6,
+ "size": 1
+ },
+ "COMIF": {
+ "description": "COM interrupt flag",
+ "offset": 5,
+ "size": 1
+ },
+ "CC2IF": {
+ "description": "Capture/Compare 2 interrupt\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IF": {
+ "description": "Capture/compare 1 interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "UIF": {
+ "description": "Update interrupt flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EGR": {
+ "description": "event generation register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "BG": {
+ "description": "Break generation",
+ "offset": 7,
+ "size": 1
+ },
+ "TG": {
+ "description": "Trigger generation",
+ "offset": 6,
+ "size": 1
+ },
+ "COMG": {
+ "description": "Capture/Compare control update\n generation",
+ "offset": 5,
+ "size": 1
+ },
+ "CC2G": {
+ "description": "Capture/compare 2\n generation",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1G": {
+ "description": "Capture/compare 1\n generation",
+ "offset": 1,
+ "size": 1
+ },
+ "UG": {
+ "description": "Update generation",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Output": {
+ "description": "capture/compare mode register (output\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ },
+ "OC1FE": {
+ "description": "Output Compare 1 fast\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "OC1PE": {
+ "description": "Output Compare 1 preload\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "OC1M": {
+ "description": "Output Compare 1 mode",
+ "offset": 4,
+ "size": 3
+ },
+ "CC2S": {
+ "description": "Capture/Compare 2\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "OC2FE": {
+ "description": "Output Compare 2 fast\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "OC2PE": {
+ "description": "Output Compare 2 preload\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "OC2M": {
+ "description": "Output Compare 2 mode",
+ "offset": 12,
+ "size": 3
+ },
+ "OC1M_3": {
+ "description": "Output Compare 1 mode bit\n 3",
+ "offset": 16,
+ "size": 1
+ },
+ "OC2M_3": {
+ "description": "Output Compare 2 mode bit\n 3",
+ "offset": 24,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Input": {
+ "description": "capture/compare mode register 1 (input\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC2F": {
+ "description": "Input capture 2 filter",
+ "offset": 12,
+ "size": 4
+ },
+ "IC2PSC": {
+ "description": "Input capture 2 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC2S": {
+ "description": "Capture/Compare 2\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC1F": {
+ "description": "Input capture 1 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "IC1PSC": {
+ "description": "Input capture 1 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCER": {
+ "description": "capture/compare enable\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC2NP": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 7,
+ "size": 1
+ },
+ "CC2P": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 5,
+ "size": 1
+ },
+ "CC2E": {
+ "description": "Capture/Compare 2 output\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC1NP": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 3,
+ "size": 1
+ },
+ "CC1NE": {
+ "description": "Capture/Compare 1 complementary output\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1P": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 1,
+ "size": 1
+ },
+ "CC1E": {
+ "description": "Capture/Compare 1 output\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNT": {
+ "description": "counter",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNT": {
+ "description": "counter value",
+ "offset": 0,
+ "size": 16
+ },
+ "UIFCPY": {
+ "description": "UIF copy",
+ "offset": 31,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "PSC": {
+ "description": "prescaler",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ARR": {
+ "description": "auto-reload register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARR": {
+ "description": "Auto-reload value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "RCR": {
+ "description": "repetition counter register",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "REP": {
+ "description": "Repetition counter value",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "CCR1": {
+ "description": "capture/compare register 1",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR1": {
+ "description": "Capture/Compare 1 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR2": {
+ "description": "capture/compare register 2",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR2": {
+ "description": "Capture/Compare 2 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "BDTR": {
+ "description": "break and dead-time register",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MOE": {
+ "description": "Main output enable",
+ "offset": 15,
+ "size": 1
+ },
+ "AOE": {
+ "description": "Automatic output enable",
+ "offset": 14,
+ "size": 1
+ },
+ "BKP": {
+ "description": "Break polarity",
+ "offset": 13,
+ "size": 1
+ },
+ "BKE": {
+ "description": "Break enable",
+ "offset": 12,
+ "size": 1
+ },
+ "OSSR": {
+ "description": "Off-state selection for Run\n mode",
+ "offset": 11,
+ "size": 1
+ },
+ "OSSI": {
+ "description": "Off-state selection for Idle\n mode",
+ "offset": 10,
+ "size": 1
+ },
+ "LOCK": {
+ "description": "Lock configuration",
+ "offset": 8,
+ "size": 2
+ },
+ "DTG": {
+ "description": "Dead-time generator setup",
+ "offset": 0,
+ "size": 8
+ },
+ "BKF": {
+ "description": "Break filter",
+ "offset": 16,
+ "size": 4
+ }
+ }
+ }
+ },
+ "DCR": {
+ "description": "DMA control register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBL": {
+ "description": "DMA burst length",
+ "offset": 8,
+ "size": 5
+ },
+ "DBA": {
+ "description": "DMA base address",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "DMAR": {
+ "description": "DMA address for full transfer",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAB": {
+ "description": "DMA register for burst\n accesses",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "TIM16": {
+ "description": "General-purpose-timers",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CEN": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ },
+ "UDIS": {
+ "description": "Update disable",
+ "offset": 1,
+ "size": 1
+ },
+ "URS": {
+ "description": "Update request source",
+ "offset": 2,
+ "size": 1
+ },
+ "OPM": {
+ "description": "One-pulse mode",
+ "offset": 3,
+ "size": 1
+ },
+ "ARPE": {
+ "description": "Auto-reload preload enable",
+ "offset": 7,
+ "size": 1
+ },
+ "CKD": {
+ "description": "Clock division",
+ "offset": 8,
+ "size": 2
+ },
+ "UIFREMAP": {
+ "description": "UIF status bit remapping",
+ "offset": 11,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OIS1N": {
+ "description": "Output Idle state 1",
+ "offset": 9,
+ "size": 1
+ },
+ "OIS1": {
+ "description": "Output Idle state 1",
+ "offset": 8,
+ "size": 1
+ },
+ "CCDS": {
+ "description": "Capture/compare DMA\n selection",
+ "offset": 3,
+ "size": 1
+ },
+ "CCUS": {
+ "description": "Capture/compare control update\n selection",
+ "offset": 2,
+ "size": 1
+ },
+ "CCPC": {
+ "description": "Capture/compare preloaded\n control",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DIER": {
+ "description": "DMA/Interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "UIE": {
+ "description": "Update interrupt enable",
+ "offset": 0,
+ "size": 1
+ },
+ "CC1IE": {
+ "description": "Capture/Compare 1 interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "COMIE": {
+ "description": "COM interrupt enable",
+ "offset": 5,
+ "size": 1
+ },
+ "TIE": {
+ "description": "Trigger interrupt enable",
+ "offset": 6,
+ "size": 1
+ },
+ "BIE": {
+ "description": "Break interrupt enable",
+ "offset": 7,
+ "size": 1
+ },
+ "UDE": {
+ "description": "Update DMA request enable",
+ "offset": 8,
+ "size": 1
+ },
+ "CC1DE": {
+ "description": "Capture/Compare 1 DMA request\n enable",
+ "offset": 9,
+ "size": 1
+ },
+ "COMDE": {
+ "description": "COM DMA request enable",
+ "offset": 13,
+ "size": 1
+ },
+ "TDE": {
+ "description": "Trigger DMA request enable",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC1OF": {
+ "description": "Capture/Compare 1 overcapture\n flag",
+ "offset": 9,
+ "size": 1
+ },
+ "BIF": {
+ "description": "Break interrupt flag",
+ "offset": 7,
+ "size": 1
+ },
+ "TIF": {
+ "description": "Trigger interrupt flag",
+ "offset": 6,
+ "size": 1
+ },
+ "COMIF": {
+ "description": "COM interrupt flag",
+ "offset": 5,
+ "size": 1
+ },
+ "CC1IF": {
+ "description": "Capture/compare 1 interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "UIF": {
+ "description": "Update interrupt flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EGR": {
+ "description": "event generation register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "BG": {
+ "description": "Break generation",
+ "offset": 7,
+ "size": 1
+ },
+ "TG": {
+ "description": "Trigger generation",
+ "offset": 6,
+ "size": 1
+ },
+ "COMG": {
+ "description": "Capture/Compare control update\n generation",
+ "offset": 5,
+ "size": 1
+ },
+ "CC1G": {
+ "description": "Capture/compare 1\n generation",
+ "offset": 1,
+ "size": 1
+ },
+ "UG": {
+ "description": "Update generation",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Output": {
+ "description": "capture/compare mode register (output\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ },
+ "OC1FE": {
+ "description": "Output Compare 1 fast\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "OC1PE": {
+ "description": "Output Compare 1 preload\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "OC1M": {
+ "description": "Output Compare 1 mode",
+ "offset": 4,
+ "size": 3
+ },
+ "OC1M_3": {
+ "description": "Output Compare 1 mode",
+ "offset": 16,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Input": {
+ "description": "capture/compare mode register 1 (input\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC1F": {
+ "description": "Input capture 1 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "IC1PSC": {
+ "description": "Input capture 1 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCER": {
+ "description": "capture/compare enable\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC1NP": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 3,
+ "size": 1
+ },
+ "CC1NE": {
+ "description": "Capture/Compare 1 complementary output\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1P": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 1,
+ "size": 1
+ },
+ "CC1E": {
+ "description": "Capture/Compare 1 output\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNT": {
+ "description": "counter",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNT": {
+ "description": "counter value",
+ "offset": 0,
+ "size": 16
+ },
+ "UIFCPY": {
+ "description": "UIF Copy",
+ "offset": 31,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "PSC": {
+ "description": "prescaler",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ARR": {
+ "description": "auto-reload register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARR": {
+ "description": "Auto-reload value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "RCR": {
+ "description": "repetition counter register",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "REP": {
+ "description": "Repetition counter value",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "CCR1": {
+ "description": "capture/compare register 1",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR1": {
+ "description": "Capture/Compare 1 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "BDTR": {
+ "description": "break and dead-time register",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DTG": {
+ "description": "Dead-time generator setup",
+ "offset": 0,
+ "size": 8
+ },
+ "LOCK": {
+ "description": "Lock configuration",
+ "offset": 8,
+ "size": 2
+ },
+ "OSSI": {
+ "description": "Off-state selection for Idle\n mode",
+ "offset": 10,
+ "size": 1
+ },
+ "OSSR": {
+ "description": "Off-state selection for Run\n mode",
+ "offset": 11,
+ "size": 1
+ },
+ "BKE": {
+ "description": "Break enable",
+ "offset": 12,
+ "size": 1
+ },
+ "BKP": {
+ "description": "Break polarity",
+ "offset": 13,
+ "size": 1
+ },
+ "AOE": {
+ "description": "Automatic output enable",
+ "offset": 14,
+ "size": 1
+ },
+ "MOE": {
+ "description": "Main output enable",
+ "offset": 15,
+ "size": 1
+ },
+ "BKF": {
+ "description": "Break filter",
+ "offset": 16,
+ "size": 4
+ }
+ }
+ }
+ },
+ "DCR": {
+ "description": "DMA control register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBL": {
+ "description": "DMA burst length",
+ "offset": 8,
+ "size": 5
+ },
+ "DBA": {
+ "description": "DMA base address",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "DMAR": {
+ "description": "DMA address for full transfer",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAB": {
+ "description": "DMA register for burst\n accesses",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OR": {
+ "description": "option register",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295
+ }
+ }
+ }
+ },
+ "TIM17": {
+ "description": "General purpose timer",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CEN": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ },
+ "UDIS": {
+ "description": "Update disable",
+ "offset": 1,
+ "size": 1
+ },
+ "URS": {
+ "description": "Update request source",
+ "offset": 2,
+ "size": 1
+ },
+ "OPM": {
+ "description": "One-pulse mode",
+ "offset": 3,
+ "size": 1
+ },
+ "ARPE": {
+ "description": "Auto-reload preload enable",
+ "offset": 7,
+ "size": 1
+ },
+ "CKD": {
+ "description": "Clock division",
+ "offset": 8,
+ "size": 2
+ },
+ "UIFREMAP": {
+ "description": "UIF status bit remapping",
+ "offset": 11,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OIS1N": {
+ "description": "Output Idle state 1",
+ "offset": 9,
+ "size": 1
+ },
+ "OIS1": {
+ "description": "Output Idle state 1",
+ "offset": 8,
+ "size": 1
+ },
+ "CCDS": {
+ "description": "Capture/compare DMA\n selection",
+ "offset": 3,
+ "size": 1
+ },
+ "CCUS": {
+ "description": "Capture/compare control update\n selection",
+ "offset": 2,
+ "size": 1
+ },
+ "CCPC": {
+ "description": "Capture/compare preloaded\n control",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DIER": {
+ "description": "DMA/Interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "UIE": {
+ "description": "Update interrupt enable",
+ "offset": 0,
+ "size": 1
+ },
+ "CC1IE": {
+ "description": "Capture/Compare 1 interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "COMIE": {
+ "description": "COM interrupt enable",
+ "offset": 5,
+ "size": 1
+ },
+ "TIE": {
+ "description": "Trigger interrupt enable",
+ "offset": 6,
+ "size": 1
+ },
+ "BIE": {
+ "description": "Break interrupt enable",
+ "offset": 7,
+ "size": 1
+ },
+ "UDE": {
+ "description": "Update DMA request enable",
+ "offset": 8,
+ "size": 1
+ },
+ "CC1DE": {
+ "description": "Capture/Compare 1 DMA request\n enable",
+ "offset": 9,
+ "size": 1
+ },
+ "COMDE": {
+ "description": "COM DMA request enable",
+ "offset": 13,
+ "size": 1
+ },
+ "TDE": {
+ "description": "Trigger DMA request enable",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC1OF": {
+ "description": "Capture/Compare 1 overcapture\n flag",
+ "offset": 9,
+ "size": 1
+ },
+ "BIF": {
+ "description": "Break interrupt flag",
+ "offset": 7,
+ "size": 1
+ },
+ "TIF": {
+ "description": "Trigger interrupt flag",
+ "offset": 6,
+ "size": 1
+ },
+ "COMIF": {
+ "description": "COM interrupt flag",
+ "offset": 5,
+ "size": 1
+ },
+ "CC1IF": {
+ "description": "Capture/compare 1 interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "UIF": {
+ "description": "Update interrupt flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EGR": {
+ "description": "event generation register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "BG": {
+ "description": "Break generation",
+ "offset": 7,
+ "size": 1
+ },
+ "TG": {
+ "description": "Trigger generation",
+ "offset": 6,
+ "size": 1
+ },
+ "COMG": {
+ "description": "Capture/Compare control update\n generation",
+ "offset": 5,
+ "size": 1
+ },
+ "CC1G": {
+ "description": "Capture/compare 1\n generation",
+ "offset": 1,
+ "size": 1
+ },
+ "UG": {
+ "description": "Update generation",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Output": {
+ "description": "capture/compare mode register (output\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ },
+ "OC1FE": {
+ "description": "Output Compare 1 fast\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "OC1PE": {
+ "description": "Output Compare 1 preload\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "OC1M": {
+ "description": "Output Compare 1 mode",
+ "offset": 4,
+ "size": 3
+ },
+ "OC1M_3": {
+ "description": "Output Compare 1 mode",
+ "offset": 16,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Input": {
+ "description": "capture/compare mode register 1 (input\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC1F": {
+ "description": "Input capture 1 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "IC1PSC": {
+ "description": "Input capture 1 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCER": {
+ "description": "capture/compare enable\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC1NP": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 3,
+ "size": 1
+ },
+ "CC1NE": {
+ "description": "Capture/Compare 1 complementary output\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1P": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 1,
+ "size": 1
+ },
+ "CC1E": {
+ "description": "Capture/Compare 1 output\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNT": {
+ "description": "counter",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNT": {
+ "description": "counter value",
+ "offset": 0,
+ "size": 16
+ },
+ "UIFCPY": {
+ "description": "UIF Copy",
+ "offset": 31,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "PSC": {
+ "description": "prescaler",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ARR": {
+ "description": "auto-reload register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARR": {
+ "description": "Auto-reload value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "RCR": {
+ "description": "repetition counter register",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "REP": {
+ "description": "Repetition counter value",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "CCR1": {
+ "description": "capture/compare register 1",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR1": {
+ "description": "Capture/Compare 1 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "BDTR": {
+ "description": "break and dead-time register",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DTG": {
+ "description": "Dead-time generator setup",
+ "offset": 0,
+ "size": 8
+ },
+ "LOCK": {
+ "description": "Lock configuration",
+ "offset": 8,
+ "size": 2
+ },
+ "OSSI": {
+ "description": "Off-state selection for Idle\n mode",
+ "offset": 10,
+ "size": 1
+ },
+ "OSSR": {
+ "description": "Off-state selection for Run\n mode",
+ "offset": 11,
+ "size": 1
+ },
+ "BKE": {
+ "description": "Break enable",
+ "offset": 12,
+ "size": 1
+ },
+ "BKP": {
+ "description": "Break polarity",
+ "offset": 13,
+ "size": 1
+ },
+ "AOE": {
+ "description": "Automatic output enable",
+ "offset": 14,
+ "size": 1
+ },
+ "MOE": {
+ "description": "Main output enable",
+ "offset": 15,
+ "size": 1
+ },
+ "BKF": {
+ "description": "Break filter",
+ "offset": 16,
+ "size": 4
+ }
+ }
+ }
+ },
+ "DCR": {
+ "description": "DMA control register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBL": {
+ "description": "DMA burst length",
+ "offset": 8,
+ "size": 5
+ },
+ "DBA": {
+ "description": "DMA base address",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "DMAR": {
+ "description": "DMA address for full transfer",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAB": {
+ "description": "DMA register for burst\n accesses",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "USART1": {
+ "description": "Universal synchronous asynchronous receiver\n transmitter",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "Control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EOBIE": {
+ "description": "End of Block interrupt\n enable",
+ "offset": 27,
+ "size": 1
+ },
+ "RTOIE": {
+ "description": "Receiver timeout interrupt\n enable",
+ "offset": 26,
+ "size": 1
+ },
+ "DEAT": {
+ "description": "Driver Enable assertion\n time",
+ "offset": 21,
+ "size": 5
+ },
+ "DEDT": {
+ "description": "Driver Enable deassertion\n time",
+ "offset": 16,
+ "size": 5
+ },
+ "OVER8": {
+ "description": "Oversampling mode",
+ "offset": 15,
+ "size": 1
+ },
+ "CMIE": {
+ "description": "Character match interrupt\n enable",
+ "offset": 14,
+ "size": 1
+ },
+ "MME": {
+ "description": "Mute mode enable",
+ "offset": 13,
+ "size": 1
+ },
+ "M": {
+ "description": "Word length",
+ "offset": 12,
+ "size": 1
+ },
+ "WAKE": {
+ "description": "Receiver wakeup method",
+ "offset": 11,
+ "size": 1
+ },
+ "PCE": {
+ "description": "Parity control enable",
+ "offset": 10,
+ "size": 1
+ },
+ "PS": {
+ "description": "Parity selection",
+ "offset": 9,
+ "size": 1
+ },
+ "PEIE": {
+ "description": "PE interrupt enable",
+ "offset": 8,
+ "size": 1
+ },
+ "TXEIE": {
+ "description": "interrupt enable",
+ "offset": 7,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transmission complete interrupt\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "RXNEIE": {
+ "description": "RXNE interrupt enable",
+ "offset": 5,
+ "size": 1
+ },
+ "IDLEIE": {
+ "description": "IDLE interrupt enable",
+ "offset": 4,
+ "size": 1
+ },
+ "TE": {
+ "description": "Transmitter enable",
+ "offset": 3,
+ "size": 1
+ },
+ "RE": {
+ "description": "Receiver enable",
+ "offset": 2,
+ "size": 1
+ },
+ "UESM": {
+ "description": "USART enable in Stop mode",
+ "offset": 1,
+ "size": 1
+ },
+ "UE": {
+ "description": "USART enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "Control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ADD4": {
+ "description": "Address of the USART node",
+ "offset": 28,
+ "size": 4
+ },
+ "ADD0": {
+ "description": "Address of the USART node",
+ "offset": 24,
+ "size": 4
+ },
+ "RTOEN": {
+ "description": "Receiver timeout enable",
+ "offset": 23,
+ "size": 1
+ },
+ "ABRMOD": {
+ "description": "Auto baud rate mode",
+ "offset": 21,
+ "size": 2
+ },
+ "ABREN": {
+ "description": "Auto baud rate enable",
+ "offset": 20,
+ "size": 1
+ },
+ "MSBFIRST": {
+ "description": "Most significant bit first",
+ "offset": 19,
+ "size": 1
+ },
+ "DATAINV": {
+ "description": "Binary data inversion",
+ "offset": 18,
+ "size": 1
+ },
+ "TXINV": {
+ "description": "TX pin active level\n inversion",
+ "offset": 17,
+ "size": 1
+ },
+ "RXINV": {
+ "description": "RX pin active level\n inversion",
+ "offset": 16,
+ "size": 1
+ },
+ "SWAP": {
+ "description": "Swap TX/RX pins",
+ "offset": 15,
+ "size": 1
+ },
+ "LINEN": {
+ "description": "LIN mode enable",
+ "offset": 14,
+ "size": 1
+ },
+ "STOP": {
+ "description": "STOP bits",
+ "offset": 12,
+ "size": 2
+ },
+ "CLKEN": {
+ "description": "Clock enable",
+ "offset": 11,
+ "size": 1
+ },
+ "CPOL": {
+ "description": "Clock polarity",
+ "offset": 10,
+ "size": 1
+ },
+ "CPHA": {
+ "description": "Clock phase",
+ "offset": 9,
+ "size": 1
+ },
+ "LBCL": {
+ "description": "Last bit clock pulse",
+ "offset": 8,
+ "size": 1
+ },
+ "LBDIE": {
+ "description": "LIN break detection interrupt\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "LBDL": {
+ "description": "LIN break detection length",
+ "offset": 5,
+ "size": 1
+ },
+ "ADDM7": {
+ "description": "7-bit Address Detection/4-bit Address\n Detection",
+ "offset": 4,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR3": {
+ "description": "Control register 3",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "WUFIE": {
+ "description": "Wakeup from Stop mode interrupt\n enable",
+ "offset": 22,
+ "size": 1
+ },
+ "WUS": {
+ "description": "Wakeup from Stop mode interrupt flag\n selection",
+ "offset": 20,
+ "size": 2
+ },
+ "SCARCNT": {
+ "description": "Smartcard auto-retry count",
+ "offset": 17,
+ "size": 3
+ },
+ "DEP": {
+ "description": "Driver enable polarity\n selection",
+ "offset": 15,
+ "size": 1
+ },
+ "DEM": {
+ "description": "Driver enable mode",
+ "offset": 14,
+ "size": 1
+ },
+ "DDRE": {
+ "description": "DMA Disable on Reception\n Error",
+ "offset": 13,
+ "size": 1
+ },
+ "OVRDIS": {
+ "description": "Overrun Disable",
+ "offset": 12,
+ "size": 1
+ },
+ "ONEBIT": {
+ "description": "One sample bit method\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "CTSIE": {
+ "description": "CTS interrupt enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CTSE": {
+ "description": "CTS enable",
+ "offset": 9,
+ "size": 1
+ },
+ "RTSE": {
+ "description": "RTS enable",
+ "offset": 8,
+ "size": 1
+ },
+ "DMAT": {
+ "description": "DMA enable transmitter",
+ "offset": 7,
+ "size": 1
+ },
+ "DMAR": {
+ "description": "DMA enable receiver",
+ "offset": 6,
+ "size": 1
+ },
+ "SCEN": {
+ "description": "Smartcard mode enable",
+ "offset": 5,
+ "size": 1
+ },
+ "NACK": {
+ "description": "Smartcard NACK enable",
+ "offset": 4,
+ "size": 1
+ },
+ "HDSEL": {
+ "description": "Half-duplex selection",
+ "offset": 3,
+ "size": 1
+ },
+ "IRLP": {
+ "description": "IrDA low-power",
+ "offset": 2,
+ "size": 1
+ },
+ "IREN": {
+ "description": "IrDA mode enable",
+ "offset": 1,
+ "size": 1
+ },
+ "EIE": {
+ "description": "Error interrupt enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BRR": {
+ "description": "Baud rate register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DIV_Mantissa": {
+ "description": "mantissa of USARTDIV",
+ "offset": 4,
+ "size": 12
+ },
+ "DIV_Fraction": {
+ "description": "fraction of USARTDIV",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "GTPR": {
+ "description": "Guard time and prescaler\n register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "GT": {
+ "description": "Guard time value",
+ "offset": 8,
+ "size": 8
+ },
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "RTOR": {
+ "description": "Receiver timeout register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BLEN": {
+ "description": "Block Length",
+ "offset": 24,
+ "size": 8
+ },
+ "RTO": {
+ "description": "Receiver timeout value",
+ "offset": 0,
+ "size": 24
+ }
+ }
+ }
+ },
+ "RQR": {
+ "description": "Request register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TXFRQ": {
+ "description": "Transmit data flush\n request",
+ "offset": 4,
+ "size": 1
+ },
+ "RXFRQ": {
+ "description": "Receive data flush request",
+ "offset": 3,
+ "size": 1
+ },
+ "MMRQ": {
+ "description": "Mute mode request",
+ "offset": 2,
+ "size": 1
+ },
+ "SBKRQ": {
+ "description": "Send break request",
+ "offset": 1,
+ "size": 1
+ },
+ "ABRRQ": {
+ "description": "Auto baud rate request",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ISR": {
+ "description": "Interrupt & status\n register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 192,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "REACK": {
+ "description": "Receive enable acknowledge\n flag",
+ "offset": 22,
+ "size": 1
+ },
+ "TEACK": {
+ "description": "Transmit enable acknowledge\n flag",
+ "offset": 21,
+ "size": 1
+ },
+ "WUF": {
+ "description": "Wakeup from Stop mode flag",
+ "offset": 20,
+ "size": 1
+ },
+ "RWU": {
+ "description": "Receiver wakeup from Mute\n mode",
+ "offset": 19,
+ "size": 1
+ },
+ "SBKF": {
+ "description": "Send break flag",
+ "offset": 18,
+ "size": 1
+ },
+ "CMF": {
+ "description": "character match flag",
+ "offset": 17,
+ "size": 1
+ },
+ "BUSY": {
+ "description": "Busy flag",
+ "offset": 16,
+ "size": 1
+ },
+ "ABRF": {
+ "description": "Auto baud rate flag",
+ "offset": 15,
+ "size": 1
+ },
+ "ABRE": {
+ "description": "Auto baud rate error",
+ "offset": 14,
+ "size": 1
+ },
+ "EOBF": {
+ "description": "End of block flag",
+ "offset": 12,
+ "size": 1
+ },
+ "RTOF": {
+ "description": "Receiver timeout",
+ "offset": 11,
+ "size": 1
+ },
+ "CTS": {
+ "description": "CTS flag",
+ "offset": 10,
+ "size": 1
+ },
+ "CTSIF": {
+ "description": "CTS interrupt flag",
+ "offset": 9,
+ "size": 1
+ },
+ "LBDF": {
+ "description": "LIN break detection flag",
+ "offset": 8,
+ "size": 1
+ },
+ "TXE": {
+ "description": "Transmit data register\n empty",
+ "offset": 7,
+ "size": 1
+ },
+ "TC": {
+ "description": "Transmission complete",
+ "offset": 6,
+ "size": 1
+ },
+ "RXNE": {
+ "description": "Read data register not\n empty",
+ "offset": 5,
+ "size": 1
+ },
+ "IDLE": {
+ "description": "Idle line detected",
+ "offset": 4,
+ "size": 1
+ },
+ "ORE": {
+ "description": "Overrun error",
+ "offset": 3,
+ "size": 1
+ },
+ "NF": {
+ "description": "Noise detected flag",
+ "offset": 2,
+ "size": 1
+ },
+ "FE": {
+ "description": "Framing error",
+ "offset": 1,
+ "size": 1
+ },
+ "PE": {
+ "description": "Parity error",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ICR": {
+ "description": "Interrupt flag clear register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "WUCF": {
+ "description": "Wakeup from Stop mode clear\n flag",
+ "offset": 20,
+ "size": 1
+ },
+ "CMCF": {
+ "description": "Character match clear flag",
+ "offset": 17,
+ "size": 1
+ },
+ "EOBCF": {
+ "description": "End of timeout clear flag",
+ "offset": 12,
+ "size": 1
+ },
+ "RTOCF": {
+ "description": "Receiver timeout clear\n flag",
+ "offset": 11,
+ "size": 1
+ },
+ "CTSCF": {
+ "description": "CTS clear flag",
+ "offset": 9,
+ "size": 1
+ },
+ "LBDCF": {
+ "description": "LIN break detection clear\n flag",
+ "offset": 8,
+ "size": 1
+ },
+ "TCCF": {
+ "description": "Transmission complete clear\n flag",
+ "offset": 6,
+ "size": 1
+ },
+ "IDLECF": {
+ "description": "Idle line detected clear\n flag",
+ "offset": 4,
+ "size": 1
+ },
+ "ORECF": {
+ "description": "Overrun error clear flag",
+ "offset": 3,
+ "size": 1
+ },
+ "NCF": {
+ "description": "Noise detected clear flag",
+ "offset": 2,
+ "size": 1
+ },
+ "FECF": {
+ "description": "Framing error clear flag",
+ "offset": 1,
+ "size": 1
+ },
+ "PECF": {
+ "description": "Parity error clear flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "RDR": {
+ "description": "Receive data register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "RDR": {
+ "description": "Receive data value",
+ "offset": 0,
+ "size": 9
+ }
+ }
+ }
+ },
+ "TDR": {
+ "description": "Transmit data register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TDR": {
+ "description": "Transmit data value",
+ "offset": 0,
+ "size": 9
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "SYSCFG_COMP_OPAMP": {
+ "description": "System configuration controller _Comparator and\n Operational amplifier",
+ "children": {
+ "registers": {
+ "SYSCFG_CFGR1": {
+ "description": "configuration register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MEM_MODE": {
+ "description": "Memory mapping selection\n bits",
+ "offset": 0,
+ "size": 2
+ },
+ "USB_IT_RMP": {
+ "description": "USB interrupt remap",
+ "offset": 5,
+ "size": 1
+ },
+ "TIM1_ITR_RMP": {
+ "description": "Timer 1 ITR3 selection",
+ "offset": 6,
+ "size": 1
+ },
+ "DAC_TRIG_RMP": {
+ "description": "DAC trigger remap (when TSEL =\n 001)",
+ "offset": 7,
+ "size": 1
+ },
+ "ADC24_DMA_RMP": {
+ "description": "ADC24 DMA remapping bit",
+ "offset": 8,
+ "size": 1
+ },
+ "TIM16_DMA_RMP": {
+ "description": "TIM16 DMA request remapping\n bit",
+ "offset": 11,
+ "size": 1
+ },
+ "TIM17_DMA_RMP": {
+ "description": "TIM17 DMA request remapping\n bit",
+ "offset": 12,
+ "size": 1
+ },
+ "TIM6_DAC1_DMA_RMP": {
+ "description": "TIM6 and DAC1 DMA request remapping\n bit",
+ "offset": 13,
+ "size": 1
+ },
+ "TIM7_DAC2_DMA_RMP": {
+ "description": "TIM7 and DAC2 DMA request remapping\n bit",
+ "offset": 14,
+ "size": 1
+ },
+ "I2C_PB6_FM": {
+ "description": "Fast Mode Plus (FM+) driving capability\n activation bits.",
+ "offset": 16,
+ "size": 1
+ },
+ "I2C_PB7_FM": {
+ "description": "Fast Mode Plus (FM+) driving capability\n activation bits.",
+ "offset": 17,
+ "size": 1
+ },
+ "I2C_PB8_FM": {
+ "description": "Fast Mode Plus (FM+) driving capability\n activation bits.",
+ "offset": 18,
+ "size": 1
+ },
+ "I2C_PB9_FM": {
+ "description": "Fast Mode Plus (FM+) driving capability\n activation bits.",
+ "offset": 19,
+ "size": 1
+ },
+ "I2C1_FM": {
+ "description": "I2C1 Fast Mode Plus",
+ "offset": 20,
+ "size": 1
+ },
+ "I2C2_FM": {
+ "description": "I2C2 Fast Mode Plus",
+ "offset": 21,
+ "size": 1
+ },
+ "ENCODER_MODE": {
+ "description": "Encoder mode",
+ "offset": 22,
+ "size": 2
+ },
+ "FPU_IT": {
+ "description": "Interrupt enable bits from\n FPU",
+ "offset": 26,
+ "size": 6
+ }
+ }
+ }
+ },
+ "SYSCFG_EXTICR1": {
+ "description": "external interrupt configuration register\n 1",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EXTI3": {
+ "description": "EXTI 3 configuration bits",
+ "offset": 12,
+ "size": 4
+ },
+ "EXTI2": {
+ "description": "EXTI 2 configuration bits",
+ "offset": 8,
+ "size": 4
+ },
+ "EXTI1": {
+ "description": "EXTI 1 configuration bits",
+ "offset": 4,
+ "size": 4
+ },
+ "EXTI0": {
+ "description": "EXTI 0 configuration bits",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "SYSCFG_EXTICR2": {
+ "description": "external interrupt configuration register\n 2",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EXTI7": {
+ "description": "EXTI 7 configuration bits",
+ "offset": 12,
+ "size": 4
+ },
+ "EXTI6": {
+ "description": "EXTI 6 configuration bits",
+ "offset": 8,
+ "size": 4
+ },
+ "EXTI5": {
+ "description": "EXTI 5 configuration bits",
+ "offset": 4,
+ "size": 4
+ },
+ "EXTI4": {
+ "description": "EXTI 4 configuration bits",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "SYSCFG_EXTICR3": {
+ "description": "external interrupt configuration register\n 3",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EXTI11": {
+ "description": "EXTI 11 configuration bits",
+ "offset": 12,
+ "size": 4
+ },
+ "EXTI10": {
+ "description": "EXTI 10 configuration bits",
+ "offset": 8,
+ "size": 4
+ },
+ "EXTI9": {
+ "description": "EXTI 9 configuration bits",
+ "offset": 4,
+ "size": 4
+ },
+ "EXTI8": {
+ "description": "EXTI 8 configuration bits",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "SYSCFG_EXTICR4": {
+ "description": "external interrupt configuration register\n 4",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EXTI15": {
+ "description": "EXTI 15 configuration bits",
+ "offset": 12,
+ "size": 4
+ },
+ "EXTI14": {
+ "description": "EXTI 14 configuration bits",
+ "offset": 8,
+ "size": 4
+ },
+ "EXTI13": {
+ "description": "EXTI 13 configuration bits",
+ "offset": 4,
+ "size": 4
+ },
+ "EXTI12": {
+ "description": "EXTI 12 configuration bits",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "SYSCFG_CFGR2": {
+ "description": "configuration register 2",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LOCUP_LOCK": {
+ "description": "Cortex-M0 LOCKUP bit enable\n bit",
+ "offset": 0,
+ "size": 1
+ },
+ "SRAM_PARITY_LOCK": {
+ "description": "SRAM parity lock bit",
+ "offset": 1,
+ "size": 1
+ },
+ "PVD_LOCK": {
+ "description": "PVD lock enable bit",
+ "offset": 2,
+ "size": 1
+ },
+ "BYP_ADD_PAR": {
+ "description": "Bypass address bit 29 in parity\n calculation",
+ "offset": 4,
+ "size": 1
+ },
+ "SRAM_PEF": {
+ "description": "SRAM parity flag",
+ "offset": 8,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SYSCFG_RCR": {
+ "description": "CCM SRAM protection register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PAGE0_WP": {
+ "description": "CCM SRAM page write protection\n bit",
+ "offset": 0,
+ "size": 1
+ },
+ "PAGE1_WP": {
+ "description": "CCM SRAM page write protection\n bit",
+ "offset": 1,
+ "size": 1
+ },
+ "PAGE2_WP": {
+ "description": "CCM SRAM page write protection\n bit",
+ "offset": 2,
+ "size": 1
+ },
+ "PAGE3_WP": {
+ "description": "CCM SRAM page write protection\n bit",
+ "offset": 3,
+ "size": 1
+ },
+ "PAGE4_WP": {
+ "description": "CCM SRAM page write protection\n bit",
+ "offset": 4,
+ "size": 1
+ },
+ "PAGE5_WP": {
+ "description": "CCM SRAM page write protection\n bit",
+ "offset": 5,
+ "size": 1
+ },
+ "PAGE6_WP": {
+ "description": "CCM SRAM page write protection\n bit",
+ "offset": 6,
+ "size": 1
+ },
+ "PAGE7_WP": {
+ "description": "CCM SRAM page write protection\n bit",
+ "offset": 7,
+ "size": 1
+ }
+ }
+ }
+ },
+ "COMP1_CSR": {
+ "description": "control and status register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "COMP1EN": {
+ "description": "Comparator 1 enable",
+ "offset": 0,
+ "size": 1
+ },
+ "COMP1_INP_DAC": {
+ "description": "COMP1_INP_DAC",
+ "offset": 1,
+ "size": 1
+ },
+ "COMP1MODE": {
+ "description": "Comparator 1 mode",
+ "offset": 2,
+ "size": 2
+ },
+ "COMP1INSEL": {
+ "description": "Comparator 1 inverting input\n selection",
+ "offset": 4,
+ "size": 3
+ },
+ "COMP1_OUT_SEL": {
+ "description": "Comparator 1 output\n selection",
+ "offset": 10,
+ "size": 4
+ },
+ "COMP1POL": {
+ "description": "Comparator 1 output\n polarity",
+ "offset": 15,
+ "size": 1
+ },
+ "COMP1HYST": {
+ "description": "Comparator 1 hysteresis",
+ "offset": 16,
+ "size": 2
+ },
+ "COMP1_BLANKING": {
+ "description": "Comparator 1 blanking\n source",
+ "offset": 18,
+ "size": 3
+ },
+ "COMP1OUT": {
+ "description": "Comparator 1 output",
+ "offset": 30,
+ "size": 1,
+ "access": "read-only"
+ },
+ "COMP1LOCK": {
+ "description": "Comparator 1 lock",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "COMP2_CSR": {
+ "description": "control and status register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "COMP2EN": {
+ "description": "Comparator 2 enable",
+ "offset": 0,
+ "size": 1
+ },
+ "COMP2MODE": {
+ "description": "Comparator 2 mode",
+ "offset": 2,
+ "size": 2
+ },
+ "COMP2INSEL": {
+ "description": "Comparator 2 inverting input\n selection",
+ "offset": 4,
+ "size": 3
+ },
+ "COMP2INPSEL": {
+ "description": "Comparator 2 non inverted input\n selection",
+ "offset": 7,
+ "size": 1
+ },
+ "COMP2INMSEL": {
+ "description": "Comparator 1inverting input\n selection",
+ "offset": 9,
+ "size": 1
+ },
+ "COMP2_OUT_SEL": {
+ "description": "Comparator 2 output\n selection",
+ "offset": 10,
+ "size": 4
+ },
+ "COMP2POL": {
+ "description": "Comparator 2 output\n polarity",
+ "offset": 15,
+ "size": 1
+ },
+ "COMP2HYST": {
+ "description": "Comparator 2 hysteresis",
+ "offset": 16,
+ "size": 2
+ },
+ "COMP2_BLANKING": {
+ "description": "Comparator 2 blanking\n source",
+ "offset": 18,
+ "size": 3
+ },
+ "COMP2LOCK": {
+ "description": "Comparator 2 lock",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "COMP3_CSR": {
+ "description": "control and status register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "COMP3EN": {
+ "description": "Comparator 3 enable",
+ "offset": 0,
+ "size": 1
+ },
+ "COMP3MODE": {
+ "description": "Comparator 3 mode",
+ "offset": 2,
+ "size": 2
+ },
+ "COMP3INSEL": {
+ "description": "Comparator 3 inverting input\n selection",
+ "offset": 4,
+ "size": 3
+ },
+ "COMP3INPSEL": {
+ "description": "Comparator 3 non inverted input\n selection",
+ "offset": 7,
+ "size": 1
+ },
+ "COMP3_OUT_SEL": {
+ "description": "Comparator 3 output\n selection",
+ "offset": 10,
+ "size": 4
+ },
+ "COMP3POL": {
+ "description": "Comparator 3 output\n polarity",
+ "offset": 15,
+ "size": 1
+ },
+ "COMP3HYST": {
+ "description": "Comparator 3 hysteresis",
+ "offset": 16,
+ "size": 2
+ },
+ "COMP3_BLANKING": {
+ "description": "Comparator 3 blanking\n source",
+ "offset": 18,
+ "size": 3
+ },
+ "COMP3OUT": {
+ "description": "Comparator 3 output",
+ "offset": 30,
+ "size": 1,
+ "access": "read-only"
+ },
+ "COMP3LOCK": {
+ "description": "Comparator 3 lock",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "COMP4_CSR": {
+ "description": "control and status register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "COMP4EN": {
+ "description": "Comparator 4 enable",
+ "offset": 0,
+ "size": 1
+ },
+ "COMP4MODE": {
+ "description": "Comparator 4 mode",
+ "offset": 2,
+ "size": 2
+ },
+ "COMP4INSEL": {
+ "description": "Comparator 4 inverting input\n selection",
+ "offset": 4,
+ "size": 3
+ },
+ "COMP4INPSEL": {
+ "description": "Comparator 4 non inverted input\n selection",
+ "offset": 7,
+ "size": 1
+ },
+ "COM4WINMODE": {
+ "description": "Comparator 4 window mode",
+ "offset": 9,
+ "size": 1
+ },
+ "COMP4_OUT_SEL": {
+ "description": "Comparator 4 output\n selection",
+ "offset": 10,
+ "size": 4
+ },
+ "COMP4POL": {
+ "description": "Comparator 4 output\n polarity",
+ "offset": 15,
+ "size": 1
+ },
+ "COMP4HYST": {
+ "description": "Comparator 4 hysteresis",
+ "offset": 16,
+ "size": 2
+ },
+ "COMP4_BLANKING": {
+ "description": "Comparator 4 blanking\n source",
+ "offset": 18,
+ "size": 3
+ },
+ "COMP4OUT": {
+ "description": "Comparator 4 output",
+ "offset": 30,
+ "size": 1,
+ "access": "read-only"
+ },
+ "COMP4LOCK": {
+ "description": "Comparator 4 lock",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "COMP5_CSR": {
+ "description": "control and status register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "COMP5EN": {
+ "description": "Comparator 5 enable",
+ "offset": 0,
+ "size": 1
+ },
+ "COMP5MODE": {
+ "description": "Comparator 5 mode",
+ "offset": 2,
+ "size": 2
+ },
+ "COMP5INSEL": {
+ "description": "Comparator 5 inverting input\n selection",
+ "offset": 4,
+ "size": 3
+ },
+ "COMP5INPSEL": {
+ "description": "Comparator 5 non inverted input\n selection",
+ "offset": 7,
+ "size": 1
+ },
+ "COMP5_OUT_SEL": {
+ "description": "Comparator 5 output\n selection",
+ "offset": 10,
+ "size": 4
+ },
+ "COMP5POL": {
+ "description": "Comparator 5 output\n polarity",
+ "offset": 15,
+ "size": 1
+ },
+ "COMP5HYST": {
+ "description": "Comparator 5 hysteresis",
+ "offset": 16,
+ "size": 2
+ },
+ "COMP5_BLANKING": {
+ "description": "Comparator 5 blanking\n source",
+ "offset": 18,
+ "size": 3
+ },
+ "COMP5OUT": {
+ "description": "Comparator51 output",
+ "offset": 30,
+ "size": 1,
+ "access": "read-only"
+ },
+ "COMP5LOCK": {
+ "description": "Comparator 5 lock",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "COMP6_CSR": {
+ "description": "control and status register",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "COMP6EN": {
+ "description": "Comparator 6 enable",
+ "offset": 0,
+ "size": 1
+ },
+ "COMP6MODE": {
+ "description": "Comparator 6 mode",
+ "offset": 2,
+ "size": 2
+ },
+ "COMP6INSEL": {
+ "description": "Comparator 6 inverting input\n selection",
+ "offset": 4,
+ "size": 3
+ },
+ "COMP6INPSEL": {
+ "description": "Comparator 6 non inverted input\n selection",
+ "offset": 7,
+ "size": 1
+ },
+ "COM6WINMODE": {
+ "description": "Comparator 6 window mode",
+ "offset": 9,
+ "size": 1
+ },
+ "COMP6_OUT_SEL": {
+ "description": "Comparator 6 output\n selection",
+ "offset": 10,
+ "size": 4
+ },
+ "COMP6POL": {
+ "description": "Comparator 6 output\n polarity",
+ "offset": 15,
+ "size": 1
+ },
+ "COMP6HYST": {
+ "description": "Comparator 6 hysteresis",
+ "offset": 16,
+ "size": 2
+ },
+ "COMP6_BLANKING": {
+ "description": "Comparator 6 blanking\n source",
+ "offset": 18,
+ "size": 3
+ },
+ "COMP6OUT": {
+ "description": "Comparator 6 output",
+ "offset": 30,
+ "size": 1,
+ "access": "read-only"
+ },
+ "COMP6LOCK": {
+ "description": "Comparator 6 lock",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "COMP7_CSR": {
+ "description": "control and status register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "COMP7EN": {
+ "description": "Comparator 7 enable",
+ "offset": 0,
+ "size": 1
+ },
+ "COMP7MODE": {
+ "description": "Comparator 7 mode",
+ "offset": 2,
+ "size": 2
+ },
+ "COMP7INSEL": {
+ "description": "Comparator 7 inverting input\n selection",
+ "offset": 4,
+ "size": 3
+ },
+ "COMP7INPSEL": {
+ "description": "Comparator 7 non inverted input\n selection",
+ "offset": 7,
+ "size": 1
+ },
+ "COMP7_OUT_SEL": {
+ "description": "Comparator 7 output\n selection",
+ "offset": 10,
+ "size": 4
+ },
+ "COMP7POL": {
+ "description": "Comparator 7 output\n polarity",
+ "offset": 15,
+ "size": 1
+ },
+ "COMP7HYST": {
+ "description": "Comparator 7 hysteresis",
+ "offset": 16,
+ "size": 2
+ },
+ "COMP7_BLANKING": {
+ "description": "Comparator 7 blanking\n source",
+ "offset": 18,
+ "size": 3
+ },
+ "COMP7OUT": {
+ "description": "Comparator 7 output",
+ "offset": 30,
+ "size": 1,
+ "access": "read-only"
+ },
+ "COMP7LOCK": {
+ "description": "Comparator 7 lock",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OPAMP1_CSR": {
+ "description": "control register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OPAMP1_EN": {
+ "description": "OPAMP1 enable",
+ "offset": 0,
+ "size": 1
+ },
+ "FORCE_VP": {
+ "description": "FORCE_VP",
+ "offset": 1,
+ "size": 1
+ },
+ "VP_SEL": {
+ "description": "OPAMP1 Non inverting input\n selection",
+ "offset": 2,
+ "size": 2
+ },
+ "VM_SEL": {
+ "description": "OPAMP1 inverting input\n selection",
+ "offset": 5,
+ "size": 2
+ },
+ "TCM_EN": {
+ "description": "Timer controlled Mux mode\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "VMS_SEL": {
+ "description": "OPAMP1 inverting input secondary\n selection",
+ "offset": 8,
+ "size": 1
+ },
+ "VPS_SEL": {
+ "description": "OPAMP1 Non inverting input secondary\n selection",
+ "offset": 9,
+ "size": 2
+ },
+ "CALON": {
+ "description": "Calibration mode enable",
+ "offset": 11,
+ "size": 1
+ },
+ "CALSEL": {
+ "description": "Calibration selection",
+ "offset": 12,
+ "size": 2
+ },
+ "PGA_GAIN": {
+ "description": "Gain in PGA mode",
+ "offset": 14,
+ "size": 4
+ },
+ "USER_TRIM": {
+ "description": "User trimming enable",
+ "offset": 18,
+ "size": 1
+ },
+ "TRIMOFFSETP": {
+ "description": "Offset trimming value\n (PMOS)",
+ "offset": 19,
+ "size": 5
+ },
+ "TRIMOFFSETN": {
+ "description": "Offset trimming value\n (NMOS)",
+ "offset": 24,
+ "size": 5
+ },
+ "TSTREF": {
+ "description": "TSTREF",
+ "offset": 29,
+ "size": 1
+ },
+ "OUTCAL": {
+ "description": "OPAMP 1 ouput status flag",
+ "offset": 30,
+ "size": 1,
+ "access": "read-only"
+ },
+ "LOCK": {
+ "description": "OPAMP 1 lock",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OPAMP2_CSR": {
+ "description": "control register",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OPAMP2EN": {
+ "description": "OPAMP2 enable",
+ "offset": 0,
+ "size": 1
+ },
+ "FORCE_VP": {
+ "description": "FORCE_VP",
+ "offset": 1,
+ "size": 1
+ },
+ "VP_SEL": {
+ "description": "OPAMP2 Non inverting input\n selection",
+ "offset": 2,
+ "size": 2
+ },
+ "VM_SEL": {
+ "description": "OPAMP2 inverting input\n selection",
+ "offset": 5,
+ "size": 2
+ },
+ "TCM_EN": {
+ "description": "Timer controlled Mux mode\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "VMS_SEL": {
+ "description": "OPAMP2 inverting input secondary\n selection",
+ "offset": 8,
+ "size": 1
+ },
+ "VPS_SEL": {
+ "description": "OPAMP2 Non inverting input secondary\n selection",
+ "offset": 9,
+ "size": 2
+ },
+ "CALON": {
+ "description": "Calibration mode enable",
+ "offset": 11,
+ "size": 1
+ },
+ "CAL_SEL": {
+ "description": "Calibration selection",
+ "offset": 12,
+ "size": 2
+ },
+ "PGA_GAIN": {
+ "description": "Gain in PGA mode",
+ "offset": 14,
+ "size": 4
+ },
+ "USER_TRIM": {
+ "description": "User trimming enable",
+ "offset": 18,
+ "size": 1
+ },
+ "TRIMOFFSETP": {
+ "description": "Offset trimming value\n (PMOS)",
+ "offset": 19,
+ "size": 5
+ },
+ "TRIMOFFSETN": {
+ "description": "Offset trimming value\n (NMOS)",
+ "offset": 24,
+ "size": 5
+ },
+ "TSTREF": {
+ "description": "TSTREF",
+ "offset": 29,
+ "size": 1
+ },
+ "OUTCAL": {
+ "description": "OPAMP 2 ouput status flag",
+ "offset": 30,
+ "size": 1,
+ "access": "read-only"
+ },
+ "LOCK": {
+ "description": "OPAMP 2 lock",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OPAMP3_CSR": {
+ "description": "control register",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OPAMP3EN": {
+ "description": "OPAMP3 enable",
+ "offset": 0,
+ "size": 1
+ },
+ "FORCE_VP": {
+ "description": "FORCE_VP",
+ "offset": 1,
+ "size": 1
+ },
+ "VP_SEL": {
+ "description": "OPAMP3 Non inverting input\n selection",
+ "offset": 2,
+ "size": 2
+ },
+ "VM_SEL": {
+ "description": "OPAMP3 inverting input\n selection",
+ "offset": 5,
+ "size": 2
+ },
+ "TCM_EN": {
+ "description": "Timer controlled Mux mode\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "VMS_SEL": {
+ "description": "OPAMP3 inverting input secondary\n selection",
+ "offset": 8,
+ "size": 1
+ },
+ "VPS_SEL": {
+ "description": "OPAMP3 Non inverting input secondary\n selection",
+ "offset": 9,
+ "size": 2
+ },
+ "CALON": {
+ "description": "Calibration mode enable",
+ "offset": 11,
+ "size": 1
+ },
+ "CALSEL": {
+ "description": "Calibration selection",
+ "offset": 12,
+ "size": 2
+ },
+ "PGA_GAIN": {
+ "description": "Gain in PGA mode",
+ "offset": 14,
+ "size": 4
+ },
+ "USER_TRIM": {
+ "description": "User trimming enable",
+ "offset": 18,
+ "size": 1
+ },
+ "TRIMOFFSETP": {
+ "description": "Offset trimming value\n (PMOS)",
+ "offset": 19,
+ "size": 5
+ },
+ "TRIMOFFSETN": {
+ "description": "Offset trimming value\n (NMOS)",
+ "offset": 24,
+ "size": 5
+ },
+ "TSTREF": {
+ "description": "TSTREF",
+ "offset": 29,
+ "size": 1
+ },
+ "OUTCAL": {
+ "description": "OPAMP 3 ouput status flag",
+ "offset": 30,
+ "size": 1,
+ "access": "read-only"
+ },
+ "LOCK": {
+ "description": "OPAMP 3 lock",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OPAMP4_CSR": {
+ "description": "control register",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OPAMP4EN": {
+ "description": "OPAMP4 enable",
+ "offset": 0,
+ "size": 1
+ },
+ "FORCE_VP": {
+ "description": "FORCE_VP",
+ "offset": 1,
+ "size": 1
+ },
+ "VP_SEL": {
+ "description": "OPAMP4 Non inverting input\n selection",
+ "offset": 2,
+ "size": 2
+ },
+ "VM_SEL": {
+ "description": "OPAMP4 inverting input\n selection",
+ "offset": 5,
+ "size": 2
+ },
+ "TCM_EN": {
+ "description": "Timer controlled Mux mode\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "VMS_SEL": {
+ "description": "OPAMP4 inverting input secondary\n selection",
+ "offset": 8,
+ "size": 1
+ },
+ "VPS_SEL": {
+ "description": "OPAMP4 Non inverting input secondary\n selection",
+ "offset": 9,
+ "size": 2
+ },
+ "CALON": {
+ "description": "Calibration mode enable",
+ "offset": 11,
+ "size": 1
+ },
+ "CALSEL": {
+ "description": "Calibration selection",
+ "offset": 12,
+ "size": 2
+ },
+ "PGA_GAIN": {
+ "description": "Gain in PGA mode",
+ "offset": 14,
+ "size": 4
+ },
+ "USER_TRIM": {
+ "description": "User trimming enable",
+ "offset": 18,
+ "size": 1
+ },
+ "TRIMOFFSETP": {
+ "description": "Offset trimming value\n (PMOS)",
+ "offset": 19,
+ "size": 5
+ },
+ "TRIMOFFSETN": {
+ "description": "Offset trimming value\n (NMOS)",
+ "offset": 24,
+ "size": 5
+ },
+ "TSTREF": {
+ "description": "TSTREF",
+ "offset": 29,
+ "size": 1
+ },
+ "OUTCAL": {
+ "description": "OPAMP 4 ouput status flag",
+ "offset": 30,
+ "size": 1,
+ "access": "read-only"
+ },
+ "LOCK": {
+ "description": "OPAMP 4 lock",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "IWDG": {
+ "description": "Independent watchdog",
+ "children": {
+ "registers": {
+ "KR": {
+ "description": "Key register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "KEY": {
+ "description": "Key value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "PR": {
+ "description": "Prescaler register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PR": {
+ "description": "Prescaler divider",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "RLR": {
+ "description": "Reload register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 4095,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RL": {
+ "description": "Watchdog counter reload\n value",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "Status register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "PVU": {
+ "description": "Watchdog prescaler value\n update",
+ "offset": 0,
+ "size": 1
+ },
+ "RVU": {
+ "description": "Watchdog counter reload value\n update",
+ "offset": 1,
+ "size": 1
+ },
+ "WVU": {
+ "description": "Watchdog counter window value\n update",
+ "offset": 2,
+ "size": 1
+ }
+ }
+ }
+ },
+ "WINR": {
+ "description": "Window register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 4095,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "WIN": {
+ "description": "Watchdog counter window\n value",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "ADC1_2": {
+ "description": "Analog-to-Digital Converter",
+ "children": {
+ "registers": {
+ "CSR": {
+ "description": "ADC Common status register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "ADDRDY_MST": {
+ "description": "ADDRDY_MST",
+ "offset": 0,
+ "size": 1
+ },
+ "EOSMP_MST": {
+ "description": "EOSMP_MST",
+ "offset": 1,
+ "size": 1
+ },
+ "EOC_MST": {
+ "description": "EOC_MST",
+ "offset": 2,
+ "size": 1
+ },
+ "EOS_MST": {
+ "description": "EOS_MST",
+ "offset": 3,
+ "size": 1
+ },
+ "OVR_MST": {
+ "description": "OVR_MST",
+ "offset": 4,
+ "size": 1
+ },
+ "JEOC_MST": {
+ "description": "JEOC_MST",
+ "offset": 5,
+ "size": 1
+ },
+ "JEOS_MST": {
+ "description": "JEOS_MST",
+ "offset": 6,
+ "size": 1
+ },
+ "AWD1_MST": {
+ "description": "AWD1_MST",
+ "offset": 7,
+ "size": 1
+ },
+ "AWD2_MST": {
+ "description": "AWD2_MST",
+ "offset": 8,
+ "size": 1
+ },
+ "AWD3_MST": {
+ "description": "AWD3_MST",
+ "offset": 9,
+ "size": 1
+ },
+ "JQOVF_MST": {
+ "description": "JQOVF_MST",
+ "offset": 10,
+ "size": 1
+ },
+ "ADRDY_SLV": {
+ "description": "ADRDY_SLV",
+ "offset": 16,
+ "size": 1
+ },
+ "EOSMP_SLV": {
+ "description": "EOSMP_SLV",
+ "offset": 17,
+ "size": 1
+ },
+ "EOC_SLV": {
+ "description": "End of regular conversion of the slave\n ADC",
+ "offset": 18,
+ "size": 1
+ },
+ "EOS_SLV": {
+ "description": "End of regular sequence flag of the\n slave ADC",
+ "offset": 19,
+ "size": 1
+ },
+ "OVR_SLV": {
+ "description": "Overrun flag of the slave\n ADC",
+ "offset": 20,
+ "size": 1
+ },
+ "JEOC_SLV": {
+ "description": "End of injected conversion flag of the\n slave ADC",
+ "offset": 21,
+ "size": 1
+ },
+ "JEOS_SLV": {
+ "description": "End of injected sequence flag of the\n slave ADC",
+ "offset": 22,
+ "size": 1
+ },
+ "AWD1_SLV": {
+ "description": "Analog watchdog 1 flag of the slave\n ADC",
+ "offset": 23,
+ "size": 1
+ },
+ "AWD2_SLV": {
+ "description": "Analog watchdog 2 flag of the slave\n ADC",
+ "offset": 24,
+ "size": 1
+ },
+ "AWD3_SLV": {
+ "description": "Analog watchdog 3 flag of the slave\n ADC",
+ "offset": 25,
+ "size": 1
+ },
+ "JQOVF_SLV": {
+ "description": "Injected Context Queue Overflow flag of\n the slave ADC",
+ "offset": 26,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCR": {
+ "description": "ADC common control register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MULT": {
+ "description": "Multi ADC mode selection",
+ "offset": 0,
+ "size": 5
+ },
+ "DELAY": {
+ "description": "Delay between 2 sampling\n phases",
+ "offset": 8,
+ "size": 4
+ },
+ "DMACFG": {
+ "description": "DMA configuration (for multi-ADC\n mode)",
+ "offset": 13,
+ "size": 1
+ },
+ "MDMA": {
+ "description": "Direct memory access mode for multi ADC\n mode",
+ "offset": 14,
+ "size": 2
+ },
+ "CKMODE": {
+ "description": "ADC clock mode",
+ "offset": 16,
+ "size": 2
+ },
+ "VREFEN": {
+ "description": "VREFINT enable",
+ "offset": 22,
+ "size": 1
+ },
+ "TSEN": {
+ "description": "Temperature sensor enable",
+ "offset": 23,
+ "size": 1
+ },
+ "VBATEN": {
+ "description": "VBAT enable",
+ "offset": 24,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CDR": {
+ "description": "ADC common regular data register for dual\n and triple modes",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "RDATA_SLV": {
+ "description": "Regular data of the slave\n ADC",
+ "offset": 16,
+ "size": 16
+ },
+ "RDATA_MST": {
+ "description": "Regular data of the master\n ADC",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "WWDG": {
+ "description": "Window watchdog",
+ "children": {
+ "registers": {
+ "CR": {
+ "description": "Control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 127,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "T": {
+ "description": "7-bit counter",
+ "offset": 0,
+ "size": 7
+ },
+ "WDGA": {
+ "description": "Activation bit",
+ "offset": 7,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CFR": {
+ "description": "Configuration register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 127,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EWI": {
+ "description": "Early wakeup interrupt",
+ "offset": 9,
+ "size": 1
+ },
+ "WDGTB": {
+ "description": "Timer base",
+ "offset": 7,
+ "size": 2
+ },
+ "W": {
+ "description": "7-bit window value",
+ "offset": 0,
+ "size": 7
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "Status register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EWIF": {
+ "description": "Early wakeup interrupt\n flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "SPI1": {
+ "description": "Serial peripheral interface/Inter-IC\n sound",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BIDIMODE": {
+ "description": "Bidirectional data mode\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "BIDIOE": {
+ "description": "Output enable in bidirectional\n mode",
+ "offset": 14,
+ "size": 1
+ },
+ "CRCEN": {
+ "description": "Hardware CRC calculation\n enable",
+ "offset": 13,
+ "size": 1
+ },
+ "CRCNEXT": {
+ "description": "CRC transfer next",
+ "offset": 12,
+ "size": 1
+ },
+ "CRCL": {
+ "description": "CRC length",
+ "offset": 11,
+ "size": 1
+ },
+ "RXONLY": {
+ "description": "Receive only",
+ "offset": 10,
+ "size": 1
+ },
+ "SSM": {
+ "description": "Software slave management",
+ "offset": 9,
+ "size": 1
+ },
+ "SSI": {
+ "description": "Internal slave select",
+ "offset": 8,
+ "size": 1
+ },
+ "LSBFIRST": {
+ "description": "Frame format",
+ "offset": 7,
+ "size": 1
+ },
+ "SPE": {
+ "description": "SPI enable",
+ "offset": 6,
+ "size": 1
+ },
+ "BR": {
+ "description": "Baud rate control",
+ "offset": 3,
+ "size": 3
+ },
+ "MSTR": {
+ "description": "Master selection",
+ "offset": 2,
+ "size": 1
+ },
+ "CPOL": {
+ "description": "Clock polarity",
+ "offset": 1,
+ "size": 1
+ },
+ "CPHA": {
+ "description": "Clock phase",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RXDMAEN": {
+ "description": "Rx buffer DMA enable",
+ "offset": 0,
+ "size": 1
+ },
+ "TXDMAEN": {
+ "description": "Tx buffer DMA enable",
+ "offset": 1,
+ "size": 1
+ },
+ "SSOE": {
+ "description": "SS output enable",
+ "offset": 2,
+ "size": 1
+ },
+ "NSSP": {
+ "description": "NSS pulse management",
+ "offset": 3,
+ "size": 1
+ },
+ "FRF": {
+ "description": "Frame format",
+ "offset": 4,
+ "size": 1
+ },
+ "ERRIE": {
+ "description": "Error interrupt enable",
+ "offset": 5,
+ "size": 1
+ },
+ "RXNEIE": {
+ "description": "RX buffer not empty interrupt\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "TXEIE": {
+ "description": "Tx buffer empty interrupt\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "DS": {
+ "description": "Data size",
+ "offset": 8,
+ "size": 4
+ },
+ "FRXTH": {
+ "description": "FIFO reception threshold",
+ "offset": 12,
+ "size": 1
+ },
+ "LDMA_RX": {
+ "description": "Last DMA transfer for\n reception",
+ "offset": 13,
+ "size": 1
+ },
+ "LDMA_TX": {
+ "description": "Last DMA transfer for\n transmission",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 2,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RXNE": {
+ "description": "Receive buffer not empty",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TXE": {
+ "description": "Transmit buffer empty",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "CHSIDE": {
+ "description": "Channel side",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "UDR": {
+ "description": "Underrun flag",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "CRCERR": {
+ "description": "CRC error flag",
+ "offset": 4,
+ "size": 1
+ },
+ "MODF": {
+ "description": "Mode fault",
+ "offset": 5,
+ "size": 1,
+ "access": "read-only"
+ },
+ "OVR": {
+ "description": "Overrun flag",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "BSY": {
+ "description": "Busy flag",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TIFRFE": {
+ "description": "TI frame format error",
+ "offset": 8,
+ "size": 1,
+ "access": "read-only"
+ },
+ "FRLVL": {
+ "description": "FIFO reception level",
+ "offset": 9,
+ "size": 2,
+ "access": "read-only"
+ },
+ "FTLVL": {
+ "description": "FIFO transmission level",
+ "offset": 11,
+ "size": 2,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "DR": {
+ "description": "data register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DR": {
+ "description": "Data register",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CRCPR": {
+ "description": "CRC polynomial register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 7,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CRCPOLY": {
+ "description": "CRC polynomial register",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "RXCRCR": {
+ "description": "RX CRC register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "RxCRC": {
+ "description": "Rx CRC register",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "TXCRCR": {
+ "description": "TX CRC register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "TxCRC": {
+ "description": "Tx CRC register",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "I2SCFGR": {
+ "description": "I2S configuration register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "I2SMOD": {
+ "description": "I2S mode selection",
+ "offset": 11,
+ "size": 1
+ },
+ "I2SE": {
+ "description": "I2S Enable",
+ "offset": 10,
+ "size": 1
+ },
+ "I2SCFG": {
+ "description": "I2S configuration mode",
+ "offset": 8,
+ "size": 2
+ },
+ "PCMSYNC": {
+ "description": "PCM frame synchronization",
+ "offset": 7,
+ "size": 1
+ },
+ "I2SSTD": {
+ "description": "I2S standard selection",
+ "offset": 4,
+ "size": 2
+ },
+ "CKPOL": {
+ "description": "Steady state clock\n polarity",
+ "offset": 3,
+ "size": 1
+ },
+ "DATLEN": {
+ "description": "Data length to be\n transferred",
+ "offset": 1,
+ "size": 2
+ },
+ "CHLEN": {
+ "description": "Channel length (number of bits per audio\n channel)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "I2SPR": {
+ "description": "I2S prescaler register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 16,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MCKOE": {
+ "description": "Master clock output enable",
+ "offset": 9,
+ "size": 1
+ },
+ "ODD": {
+ "description": "Odd factor for the\n prescaler",
+ "offset": 8,
+ "size": 1
+ },
+ "I2SDIV": {
+ "description": "I2S Linear prescaler",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "RTC": {
+ "description": "Real-time clock",
+ "children": {
+ "registers": {
+ "TR": {
+ "description": "time register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PM": {
+ "description": "AM/PM notation",
+ "offset": 22,
+ "size": 1
+ },
+ "HT": {
+ "description": "Hour tens in BCD format",
+ "offset": 20,
+ "size": 2
+ },
+ "HU": {
+ "description": "Hour units in BCD format",
+ "offset": 16,
+ "size": 4
+ },
+ "MNT": {
+ "description": "Minute tens in BCD format",
+ "offset": 12,
+ "size": 3
+ },
+ "MNU": {
+ "description": "Minute units in BCD format",
+ "offset": 8,
+ "size": 4
+ },
+ "ST": {
+ "description": "Second tens in BCD format",
+ "offset": 4,
+ "size": 3
+ },
+ "SU": {
+ "description": "Second units in BCD format",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "DR": {
+ "description": "date register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 8449,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "YT": {
+ "description": "Year tens in BCD format",
+ "offset": 20,
+ "size": 4
+ },
+ "YU": {
+ "description": "Year units in BCD format",
+ "offset": 16,
+ "size": 4
+ },
+ "WDU": {
+ "description": "Week day units",
+ "offset": 13,
+ "size": 3
+ },
+ "MT": {
+ "description": "Month tens in BCD format",
+ "offset": 12,
+ "size": 1
+ },
+ "MU": {
+ "description": "Month units in BCD format",
+ "offset": 8,
+ "size": 4
+ },
+ "DT": {
+ "description": "Date tens in BCD format",
+ "offset": 4,
+ "size": 2
+ },
+ "DU": {
+ "description": "Date units in BCD format",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "CR": {
+ "description": "control register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "WCKSEL": {
+ "description": "Wakeup clock selection",
+ "offset": 0,
+ "size": 3
+ },
+ "TSEDGE": {
+ "description": "Time-stamp event active\n edge",
+ "offset": 3,
+ "size": 1
+ },
+ "REFCKON": {
+ "description": "Reference clock detection enable (50 or\n 60 Hz)",
+ "offset": 4,
+ "size": 1
+ },
+ "BYPSHAD": {
+ "description": "Bypass the shadow\n registers",
+ "offset": 5,
+ "size": 1
+ },
+ "FMT": {
+ "description": "Hour format",
+ "offset": 6,
+ "size": 1
+ },
+ "ALRAE": {
+ "description": "Alarm A enable",
+ "offset": 8,
+ "size": 1
+ },
+ "ALRBE": {
+ "description": "Alarm B enable",
+ "offset": 9,
+ "size": 1
+ },
+ "WUTE": {
+ "description": "Wakeup timer enable",
+ "offset": 10,
+ "size": 1
+ },
+ "TSE": {
+ "description": "Time stamp enable",
+ "offset": 11,
+ "size": 1
+ },
+ "ALRAIE": {
+ "description": "Alarm A interrupt enable",
+ "offset": 12,
+ "size": 1
+ },
+ "ALRBIE": {
+ "description": "Alarm B interrupt enable",
+ "offset": 13,
+ "size": 1
+ },
+ "WUTIE": {
+ "description": "Wakeup timer interrupt\n enable",
+ "offset": 14,
+ "size": 1
+ },
+ "TSIE": {
+ "description": "Time-stamp interrupt\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "ADD1H": {
+ "description": "Add 1 hour (summer time\n change)",
+ "offset": 16,
+ "size": 1
+ },
+ "SUB1H": {
+ "description": "Subtract 1 hour (winter time\n change)",
+ "offset": 17,
+ "size": 1
+ },
+ "BKP": {
+ "description": "Backup",
+ "offset": 18,
+ "size": 1
+ },
+ "COSEL": {
+ "description": "Calibration output\n selection",
+ "offset": 19,
+ "size": 1
+ },
+ "POL": {
+ "description": "Output polarity",
+ "offset": 20,
+ "size": 1
+ },
+ "OSEL": {
+ "description": "Output selection",
+ "offset": 21,
+ "size": 2
+ },
+ "COE": {
+ "description": "Calibration output enable",
+ "offset": 23,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ISR": {
+ "description": "initialization and status\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 7,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ALRAWF": {
+ "description": "Alarm A write flag",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ALRBWF": {
+ "description": "Alarm B write flag",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "WUTWF": {
+ "description": "Wakeup timer write flag",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SHPF": {
+ "description": "Shift operation pending",
+ "offset": 3,
+ "size": 1
+ },
+ "INITS": {
+ "description": "Initialization status flag",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "RSF": {
+ "description": "Registers synchronization\n flag",
+ "offset": 5,
+ "size": 1
+ },
+ "INITF": {
+ "description": "Initialization flag",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "INIT": {
+ "description": "Initialization mode",
+ "offset": 7,
+ "size": 1
+ },
+ "ALRAF": {
+ "description": "Alarm A flag",
+ "offset": 8,
+ "size": 1
+ },
+ "ALRBF": {
+ "description": "Alarm B flag",
+ "offset": 9,
+ "size": 1
+ },
+ "WUTF": {
+ "description": "Wakeup timer flag",
+ "offset": 10,
+ "size": 1
+ },
+ "TSF": {
+ "description": "Time-stamp flag",
+ "offset": 11,
+ "size": 1
+ },
+ "TSOVF": {
+ "description": "Time-stamp overflow flag",
+ "offset": 12,
+ "size": 1
+ },
+ "TAMP1F": {
+ "description": "Tamper detection flag",
+ "offset": 13,
+ "size": 1
+ },
+ "TAMP2F": {
+ "description": "RTC_TAMP2 detection flag",
+ "offset": 14,
+ "size": 1
+ },
+ "TAMP3F": {
+ "description": "RTC_TAMP3 detection flag",
+ "offset": 15,
+ "size": 1
+ },
+ "RECALPF": {
+ "description": "Recalibration pending Flag",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "PRER": {
+ "description": "prescaler register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 8323327,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PREDIV_A": {
+ "description": "Asynchronous prescaler\n factor",
+ "offset": 16,
+ "size": 7
+ },
+ "PREDIV_S": {
+ "description": "Synchronous prescaler\n factor",
+ "offset": 0,
+ "size": 15
+ }
+ }
+ }
+ },
+ "WUTR": {
+ "description": "wakeup timer register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 65535,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "WUT": {
+ "description": "Wakeup auto-reload value\n bits",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ALRMAR": {
+ "description": "alarm A register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MSK4": {
+ "description": "Alarm A date mask",
+ "offset": 31,
+ "size": 1
+ },
+ "WDSEL": {
+ "description": "Week day selection",
+ "offset": 30,
+ "size": 1
+ },
+ "DT": {
+ "description": "Date tens in BCD format",
+ "offset": 28,
+ "size": 2
+ },
+ "DU": {
+ "description": "Date units or day in BCD\n format",
+ "offset": 24,
+ "size": 4
+ },
+ "MSK3": {
+ "description": "Alarm A hours mask",
+ "offset": 23,
+ "size": 1
+ },
+ "PM": {
+ "description": "AM/PM notation",
+ "offset": 22,
+ "size": 1
+ },
+ "HT": {
+ "description": "Hour tens in BCD format",
+ "offset": 20,
+ "size": 2
+ },
+ "HU": {
+ "description": "Hour units in BCD format",
+ "offset": 16,
+ "size": 4
+ },
+ "MSK2": {
+ "description": "Alarm A minutes mask",
+ "offset": 15,
+ "size": 1
+ },
+ "MNT": {
+ "description": "Minute tens in BCD format",
+ "offset": 12,
+ "size": 3
+ },
+ "MNU": {
+ "description": "Minute units in BCD format",
+ "offset": 8,
+ "size": 4
+ },
+ "MSK1": {
+ "description": "Alarm A seconds mask",
+ "offset": 7,
+ "size": 1
+ },
+ "ST": {
+ "description": "Second tens in BCD format",
+ "offset": 4,
+ "size": 3
+ },
+ "SU": {
+ "description": "Second units in BCD format",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "ALRMBR": {
+ "description": "alarm B register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MSK4": {
+ "description": "Alarm B date mask",
+ "offset": 31,
+ "size": 1
+ },
+ "WDSEL": {
+ "description": "Week day selection",
+ "offset": 30,
+ "size": 1
+ },
+ "DT": {
+ "description": "Date tens in BCD format",
+ "offset": 28,
+ "size": 2
+ },
+ "DU": {
+ "description": "Date units or day in BCD\n format",
+ "offset": 24,
+ "size": 4
+ },
+ "MSK3": {
+ "description": "Alarm B hours mask",
+ "offset": 23,
+ "size": 1
+ },
+ "PM": {
+ "description": "AM/PM notation",
+ "offset": 22,
+ "size": 1
+ },
+ "HT": {
+ "description": "Hour tens in BCD format",
+ "offset": 20,
+ "size": 2
+ },
+ "HU": {
+ "description": "Hour units in BCD format",
+ "offset": 16,
+ "size": 4
+ },
+ "MSK2": {
+ "description": "Alarm B minutes mask",
+ "offset": 15,
+ "size": 1
+ },
+ "MNT": {
+ "description": "Minute tens in BCD format",
+ "offset": 12,
+ "size": 3
+ },
+ "MNU": {
+ "description": "Minute units in BCD format",
+ "offset": 8,
+ "size": 4
+ },
+ "MSK1": {
+ "description": "Alarm B seconds mask",
+ "offset": 7,
+ "size": 1
+ },
+ "ST": {
+ "description": "Second tens in BCD format",
+ "offset": 4,
+ "size": 3
+ },
+ "SU": {
+ "description": "Second units in BCD format",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "WPR": {
+ "description": "write protection register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "KEY": {
+ "description": "Write protection key",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "SSR": {
+ "description": "sub second register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "SS": {
+ "description": "Sub second value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "SHIFTR": {
+ "description": "shift control register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "ADD1S": {
+ "description": "Add one second",
+ "offset": 31,
+ "size": 1
+ },
+ "SUBFS": {
+ "description": "Subtract a fraction of a\n second",
+ "offset": 0,
+ "size": 15
+ }
+ }
+ }
+ },
+ "TSTR": {
+ "description": "time stamp time register",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "SU": {
+ "description": "Second units in BCD format",
+ "offset": 0,
+ "size": 4
+ },
+ "ST": {
+ "description": "Second tens in BCD format",
+ "offset": 4,
+ "size": 3
+ },
+ "MNU": {
+ "description": "Minute units in BCD format",
+ "offset": 8,
+ "size": 4
+ },
+ "MNT": {
+ "description": "Minute tens in BCD format",
+ "offset": 12,
+ "size": 3
+ },
+ "HU": {
+ "description": "Hour units in BCD format",
+ "offset": 16,
+ "size": 4
+ },
+ "HT": {
+ "description": "Hour tens in BCD format",
+ "offset": 20,
+ "size": 2
+ },
+ "PM": {
+ "description": "AM/PM notation",
+ "offset": 22,
+ "size": 1
+ }
+ }
+ }
+ },
+ "TSDR": {
+ "description": "time stamp date register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "WDU": {
+ "description": "Week day units",
+ "offset": 13,
+ "size": 3
+ },
+ "MT": {
+ "description": "Month tens in BCD format",
+ "offset": 12,
+ "size": 1
+ },
+ "MU": {
+ "description": "Month units in BCD format",
+ "offset": 8,
+ "size": 4
+ },
+ "DT": {
+ "description": "Date tens in BCD format",
+ "offset": 4,
+ "size": 2
+ },
+ "DU": {
+ "description": "Date units in BCD format",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "TSSSR": {
+ "description": "timestamp sub second register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "SS": {
+ "description": "Sub second value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CALR": {
+ "description": "calibration register",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CALP": {
+ "description": "Increase frequency of RTC by 488.5\n ppm",
+ "offset": 15,
+ "size": 1
+ },
+ "CALW8": {
+ "description": "Use an 8-second calibration cycle\n period",
+ "offset": 14,
+ "size": 1
+ },
+ "CALW16": {
+ "description": "Use a 16-second calibration cycle\n period",
+ "offset": 13,
+ "size": 1
+ },
+ "CALM": {
+ "description": "Calibration minus",
+ "offset": 0,
+ "size": 9
+ }
+ }
+ }
+ },
+ "TAFCR": {
+ "description": "tamper and alternate function configuration\n register",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TAMP1E": {
+ "description": "Tamper 1 detection enable",
+ "offset": 0,
+ "size": 1
+ },
+ "TAMP1TRG": {
+ "description": "Active level for tamper 1",
+ "offset": 1,
+ "size": 1
+ },
+ "TAMPIE": {
+ "description": "Tamper interrupt enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TAMP2E": {
+ "description": "Tamper 2 detection enable",
+ "offset": 3,
+ "size": 1
+ },
+ "TAMP2TRG": {
+ "description": "Active level for tamper 2",
+ "offset": 4,
+ "size": 1
+ },
+ "TAMP3E": {
+ "description": "Tamper 3 detection enable",
+ "offset": 5,
+ "size": 1
+ },
+ "TAMP3TRG": {
+ "description": "Active level for tamper 3",
+ "offset": 6,
+ "size": 1
+ },
+ "TAMPTS": {
+ "description": "Activate timestamp on tamper detection\n event",
+ "offset": 7,
+ "size": 1
+ },
+ "TAMPFREQ": {
+ "description": "Tamper sampling frequency",
+ "offset": 8,
+ "size": 3
+ },
+ "TAMPFLT": {
+ "description": "Tamper filter count",
+ "offset": 11,
+ "size": 2
+ },
+ "TAMPPRCH": {
+ "description": "Tamper precharge duration",
+ "offset": 13,
+ "size": 2
+ },
+ "TAMPPUDIS": {
+ "description": "TAMPER pull-up disable",
+ "offset": 15,
+ "size": 1
+ },
+ "PC13VALUE": {
+ "description": "PC13 value",
+ "offset": 18,
+ "size": 1
+ },
+ "PC13MODE": {
+ "description": "PC13 mode",
+ "offset": 19,
+ "size": 1
+ },
+ "PC14VALUE": {
+ "description": "PC14 value",
+ "offset": 20,
+ "size": 1
+ },
+ "PC14MODE": {
+ "description": "PC 14 mode",
+ "offset": 21,
+ "size": 1
+ },
+ "PC15VALUE": {
+ "description": "PC15 value",
+ "offset": 22,
+ "size": 1
+ },
+ "PC15MODE": {
+ "description": "PC15 mode",
+ "offset": 23,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ALRMASSR": {
+ "description": "alarm A sub second register",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MASKSS": {
+ "description": "Mask the most-significant bits starting\n at this bit",
+ "offset": 24,
+ "size": 4
+ },
+ "SS": {
+ "description": "Sub seconds value",
+ "offset": 0,
+ "size": 15
+ }
+ }
+ }
+ },
+ "ALRMBSSR": {
+ "description": "alarm B sub second register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MASKSS": {
+ "description": "Mask the most-significant bits starting\n at this bit",
+ "offset": 24,
+ "size": 4
+ },
+ "SS": {
+ "description": "Sub seconds value",
+ "offset": 0,
+ "size": 15
+ }
+ }
+ }
+ },
+ "BKP0R": {
+ "description": "backup register",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP1R": {
+ "description": "backup register",
+ "offset": 84,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP2R": {
+ "description": "backup register",
+ "offset": 88,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP3R": {
+ "description": "backup register",
+ "offset": 92,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP4R": {
+ "description": "backup register",
+ "offset": 96,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP5R": {
+ "description": "backup register",
+ "offset": 100,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP6R": {
+ "description": "backup register",
+ "offset": 104,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP7R": {
+ "description": "backup register",
+ "offset": 108,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP8R": {
+ "description": "backup register",
+ "offset": 112,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP9R": {
+ "description": "backup register",
+ "offset": 116,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP10R": {
+ "description": "backup register",
+ "offset": 120,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP11R": {
+ "description": "backup register",
+ "offset": 124,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP12R": {
+ "description": "backup register",
+ "offset": 128,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP13R": {
+ "description": "backup register",
+ "offset": 132,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP14R": {
+ "description": "backup register",
+ "offset": 136,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP15R": {
+ "description": "backup register",
+ "offset": 140,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP16R": {
+ "description": "backup register",
+ "offset": 144,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP17R": {
+ "description": "backup register",
+ "offset": 148,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP18R": {
+ "description": "backup register",
+ "offset": 152,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP19R": {
+ "description": "backup register",
+ "offset": 156,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP20R": {
+ "description": "backup register",
+ "offset": 160,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP21R": {
+ "description": "backup register",
+ "offset": 164,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP22R": {
+ "description": "backup register",
+ "offset": 168,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP23R": {
+ "description": "backup register",
+ "offset": 172,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP24R": {
+ "description": "backup register",
+ "offset": 176,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP25R": {
+ "description": "backup register",
+ "offset": 180,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP26R": {
+ "description": "backup register",
+ "offset": 184,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP27R": {
+ "description": "backup register",
+ "offset": 188,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP28R": {
+ "description": "backup register",
+ "offset": 192,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP29R": {
+ "description": "backup register",
+ "offset": 196,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP30R": {
+ "description": "backup register",
+ "offset": 200,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP31R": {
+ "description": "backup register",
+ "offset": 204,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "TIM6": {
+ "description": "Basic timers",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CEN": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ },
+ "UDIS": {
+ "description": "Update disable",
+ "offset": 1,
+ "size": 1
+ },
+ "URS": {
+ "description": "Update request source",
+ "offset": 2,
+ "size": 1
+ },
+ "OPM": {
+ "description": "One-pulse mode",
+ "offset": 3,
+ "size": 1
+ },
+ "ARPE": {
+ "description": "Auto-reload preload enable",
+ "offset": 7,
+ "size": 1
+ },
+ "UIFREMAP": {
+ "description": "UIF status bit remapping",
+ "offset": 11,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MMS": {
+ "description": "Master mode selection",
+ "offset": 4,
+ "size": 3
+ }
+ }
+ }
+ },
+ "DIER": {
+ "description": "DMA/Interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "UDE": {
+ "description": "Update DMA request enable",
+ "offset": 8,
+ "size": 1
+ },
+ "UIE": {
+ "description": "Update interrupt enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "UIF": {
+ "description": "Update interrupt flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EGR": {
+ "description": "event generation register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "UG": {
+ "description": "Update generation",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNT": {
+ "description": "counter",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNT": {
+ "description": "Low counter value",
+ "offset": 0,
+ "size": 16
+ },
+ "UIFCPY": {
+ "description": "UIF Copy",
+ "offset": 31,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "PSC": {
+ "description": "prescaler",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ARR": {
+ "description": "auto-reload register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARR": {
+ "description": "Low Auto-reload value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "ADC1": {
+ "description": "Analog-to-Digital Converter",
+ "children": {
+ "registers": {
+ "ISR": {
+ "description": "interrupt and status register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "JQOVF": {
+ "description": "JQOVF",
+ "offset": 10,
+ "size": 1
+ },
+ "AWD3": {
+ "description": "AWD3",
+ "offset": 9,
+ "size": 1
+ },
+ "AWD2": {
+ "description": "AWD2",
+ "offset": 8,
+ "size": 1
+ },
+ "AWD1": {
+ "description": "AWD1",
+ "offset": 7,
+ "size": 1
+ },
+ "JEOS": {
+ "description": "JEOS",
+ "offset": 6,
+ "size": 1
+ },
+ "JEOC": {
+ "description": "JEOC",
+ "offset": 5,
+ "size": 1
+ },
+ "OVR": {
+ "description": "OVR",
+ "offset": 4,
+ "size": 1
+ },
+ "EOS": {
+ "description": "EOS",
+ "offset": 3,
+ "size": 1
+ },
+ "EOC": {
+ "description": "EOC",
+ "offset": 2,
+ "size": 1
+ },
+ "EOSMP": {
+ "description": "EOSMP",
+ "offset": 1,
+ "size": 1
+ },
+ "ADRDY": {
+ "description": "ADRDY",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "IER": {
+ "description": "interrupt enable register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "JQOVFIE": {
+ "description": "JQOVFIE",
+ "offset": 10,
+ "size": 1
+ },
+ "AWD3IE": {
+ "description": "AWD3IE",
+ "offset": 9,
+ "size": 1
+ },
+ "AWD2IE": {
+ "description": "AWD2IE",
+ "offset": 8,
+ "size": 1
+ },
+ "AWD1IE": {
+ "description": "AWD1IE",
+ "offset": 7,
+ "size": 1
+ },
+ "JEOSIE": {
+ "description": "JEOSIE",
+ "offset": 6,
+ "size": 1
+ },
+ "JEOCIE": {
+ "description": "JEOCIE",
+ "offset": 5,
+ "size": 1
+ },
+ "OVRIE": {
+ "description": "OVRIE",
+ "offset": 4,
+ "size": 1
+ },
+ "EOSIE": {
+ "description": "EOSIE",
+ "offset": 3,
+ "size": 1
+ },
+ "EOCIE": {
+ "description": "EOCIE",
+ "offset": 2,
+ "size": 1
+ },
+ "EOSMPIE": {
+ "description": "EOSMPIE",
+ "offset": 1,
+ "size": 1
+ },
+ "ADRDYIE": {
+ "description": "ADRDYIE",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR": {
+ "description": "control register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ADCAL": {
+ "description": "ADCAL",
+ "offset": 31,
+ "size": 1
+ },
+ "ADCALDIF": {
+ "description": "ADCALDIF",
+ "offset": 30,
+ "size": 1
+ },
+ "DEEPPWD": {
+ "description": "DEEPPWD",
+ "offset": 29,
+ "size": 1
+ },
+ "ADVREGEN": {
+ "description": "ADVREGEN",
+ "offset": 28,
+ "size": 1
+ },
+ "JADSTP": {
+ "description": "JADSTP",
+ "offset": 5,
+ "size": 1
+ },
+ "ADSTP": {
+ "description": "ADSTP",
+ "offset": 4,
+ "size": 1
+ },
+ "JADSTART": {
+ "description": "JADSTART",
+ "offset": 3,
+ "size": 1
+ },
+ "ADSTART": {
+ "description": "ADSTART",
+ "offset": 2,
+ "size": 1
+ },
+ "ADDIS": {
+ "description": "ADDIS",
+ "offset": 1,
+ "size": 1
+ },
+ "ADEN": {
+ "description": "ADEN",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CFGR": {
+ "description": "configuration register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "AWDCH1CH": {
+ "description": "AWDCH1CH",
+ "offset": 26,
+ "size": 5
+ },
+ "JAUTO": {
+ "description": "JAUTO",
+ "offset": 25,
+ "size": 1
+ },
+ "JAWD1EN": {
+ "description": "JAWD1EN",
+ "offset": 24,
+ "size": 1
+ },
+ "AWD1EN": {
+ "description": "AWD1EN",
+ "offset": 23,
+ "size": 1
+ },
+ "AWD1SGL": {
+ "description": "AWD1SGL",
+ "offset": 22,
+ "size": 1
+ },
+ "JQM": {
+ "description": "JQM",
+ "offset": 21,
+ "size": 1
+ },
+ "JDISCEN": {
+ "description": "JDISCEN",
+ "offset": 20,
+ "size": 1
+ },
+ "DISCNUM": {
+ "description": "DISCNUM",
+ "offset": 17,
+ "size": 3
+ },
+ "DISCEN": {
+ "description": "DISCEN",
+ "offset": 16,
+ "size": 1
+ },
+ "AUTOFF": {
+ "description": "AUTOFF",
+ "offset": 15,
+ "size": 1
+ },
+ "AUTDLY": {
+ "description": "AUTDLY",
+ "offset": 14,
+ "size": 1
+ },
+ "CONT": {
+ "description": "CONT",
+ "offset": 13,
+ "size": 1
+ },
+ "OVRMOD": {
+ "description": "OVRMOD",
+ "offset": 12,
+ "size": 1
+ },
+ "EXTEN": {
+ "description": "EXTEN",
+ "offset": 10,
+ "size": 2
+ },
+ "EXTSEL": {
+ "description": "EXTSEL",
+ "offset": 6,
+ "size": 4
+ },
+ "ALIGN": {
+ "description": "ALIGN",
+ "offset": 5,
+ "size": 1
+ },
+ "RES": {
+ "description": "RES",
+ "offset": 3,
+ "size": 2
+ },
+ "DMACFG": {
+ "description": "DMACFG",
+ "offset": 1,
+ "size": 1
+ },
+ "DMAEN": {
+ "description": "DMAEN",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SMPR1": {
+ "description": "sample time register 1",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SMP9": {
+ "description": "SMP9",
+ "offset": 27,
+ "size": 3
+ },
+ "SMP8": {
+ "description": "SMP8",
+ "offset": 24,
+ "size": 3
+ },
+ "SMP7": {
+ "description": "SMP7",
+ "offset": 21,
+ "size": 3
+ },
+ "SMP6": {
+ "description": "SMP6",
+ "offset": 18,
+ "size": 3
+ },
+ "SMP5": {
+ "description": "SMP5",
+ "offset": 15,
+ "size": 3
+ },
+ "SMP4": {
+ "description": "SMP4",
+ "offset": 12,
+ "size": 3
+ },
+ "SMP3": {
+ "description": "SMP3",
+ "offset": 9,
+ "size": 3
+ },
+ "SMP2": {
+ "description": "SMP2",
+ "offset": 6,
+ "size": 3
+ },
+ "SMP1": {
+ "description": "SMP1",
+ "offset": 3,
+ "size": 3
+ }
+ }
+ }
+ },
+ "SMPR2": {
+ "description": "sample time register 2",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SMP18": {
+ "description": "SMP18",
+ "offset": 24,
+ "size": 3
+ },
+ "SMP17": {
+ "description": "SMP17",
+ "offset": 21,
+ "size": 3
+ },
+ "SMP16": {
+ "description": "SMP16",
+ "offset": 18,
+ "size": 3
+ },
+ "SMP15": {
+ "description": "SMP15",
+ "offset": 15,
+ "size": 3
+ },
+ "SMP14": {
+ "description": "SMP14",
+ "offset": 12,
+ "size": 3
+ },
+ "SMP13": {
+ "description": "SMP13",
+ "offset": 9,
+ "size": 3
+ },
+ "SMP12": {
+ "description": "SMP12",
+ "offset": 6,
+ "size": 3
+ },
+ "SMP11": {
+ "description": "SMP11",
+ "offset": 3,
+ "size": 3
+ },
+ "SMP10": {
+ "description": "SMP10",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "TR1": {
+ "description": "watchdog threshold register 1",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 268369920,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "HT1": {
+ "description": "HT1",
+ "offset": 16,
+ "size": 12
+ },
+ "LT1": {
+ "description": "LT1",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "TR2": {
+ "description": "watchdog threshold register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 268369920,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "HT2": {
+ "description": "HT2",
+ "offset": 16,
+ "size": 8
+ },
+ "LT2": {
+ "description": "LT2",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "TR3": {
+ "description": "watchdog threshold register 3",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 268369920,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "HT3": {
+ "description": "HT3",
+ "offset": 16,
+ "size": 8
+ },
+ "LT3": {
+ "description": "LT3",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "SQR1": {
+ "description": "regular sequence register 1",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SQ4": {
+ "description": "SQ4",
+ "offset": 24,
+ "size": 5
+ },
+ "SQ3": {
+ "description": "SQ3",
+ "offset": 18,
+ "size": 5
+ },
+ "SQ2": {
+ "description": "SQ2",
+ "offset": 12,
+ "size": 5
+ },
+ "SQ1": {
+ "description": "SQ1",
+ "offset": 6,
+ "size": 5
+ },
+ "L3": {
+ "description": "L3",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "SQR2": {
+ "description": "regular sequence register 2",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SQ9": {
+ "description": "SQ9",
+ "offset": 24,
+ "size": 5
+ },
+ "SQ8": {
+ "description": "SQ8",
+ "offset": 18,
+ "size": 5
+ },
+ "SQ7": {
+ "description": "SQ7",
+ "offset": 12,
+ "size": 5
+ },
+ "SQ6": {
+ "description": "SQ6",
+ "offset": 6,
+ "size": 5
+ },
+ "SQ5": {
+ "description": "SQ5",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "SQR3": {
+ "description": "regular sequence register 3",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SQ14": {
+ "description": "SQ14",
+ "offset": 24,
+ "size": 5
+ },
+ "SQ13": {
+ "description": "SQ13",
+ "offset": 18,
+ "size": 5
+ },
+ "SQ12": {
+ "description": "SQ12",
+ "offset": 12,
+ "size": 5
+ },
+ "SQ11": {
+ "description": "SQ11",
+ "offset": 6,
+ "size": 5
+ },
+ "SQ10": {
+ "description": "SQ10",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "SQR4": {
+ "description": "regular sequence register 4",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SQ16": {
+ "description": "SQ16",
+ "offset": 6,
+ "size": 5
+ },
+ "SQ15": {
+ "description": "SQ15",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "DR": {
+ "description": "regular Data Register",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "regularDATA": {
+ "description": "regularDATA",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "JSQR": {
+ "description": "injected sequence register",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "JSQ4": {
+ "description": "JSQ4",
+ "offset": 26,
+ "size": 5
+ },
+ "JSQ3": {
+ "description": "JSQ3",
+ "offset": 20,
+ "size": 5
+ },
+ "JSQ2": {
+ "description": "JSQ2",
+ "offset": 14,
+ "size": 5
+ },
+ "JSQ1": {
+ "description": "JSQ1",
+ "offset": 8,
+ "size": 5
+ },
+ "JEXTEN": {
+ "description": "JEXTEN",
+ "offset": 6,
+ "size": 2
+ },
+ "JEXTSEL": {
+ "description": "JEXTSEL",
+ "offset": 2,
+ "size": 4
+ },
+ "JL": {
+ "description": "JL",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OFR1": {
+ "description": "offset register 1",
+ "offset": 96,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OFFSET1_EN": {
+ "description": "OFFSET1_EN",
+ "offset": 31,
+ "size": 1
+ },
+ "OFFSET1_CH": {
+ "description": "OFFSET1_CH",
+ "offset": 26,
+ "size": 5
+ },
+ "OFFSET1": {
+ "description": "OFFSET1",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "OFR2": {
+ "description": "offset register 2",
+ "offset": 100,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OFFSET2_EN": {
+ "description": "OFFSET2_EN",
+ "offset": 31,
+ "size": 1
+ },
+ "OFFSET2_CH": {
+ "description": "OFFSET2_CH",
+ "offset": 26,
+ "size": 5
+ },
+ "OFFSET2": {
+ "description": "OFFSET2",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "OFR3": {
+ "description": "offset register 3",
+ "offset": 104,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OFFSET3_EN": {
+ "description": "OFFSET3_EN",
+ "offset": 31,
+ "size": 1
+ },
+ "OFFSET3_CH": {
+ "description": "OFFSET3_CH",
+ "offset": 26,
+ "size": 5
+ },
+ "OFFSET3": {
+ "description": "OFFSET3",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "OFR4": {
+ "description": "offset register 4",
+ "offset": 108,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OFFSET4_EN": {
+ "description": "OFFSET4_EN",
+ "offset": 31,
+ "size": 1
+ },
+ "OFFSET4_CH": {
+ "description": "OFFSET4_CH",
+ "offset": 26,
+ "size": 5
+ },
+ "OFFSET4": {
+ "description": "OFFSET4",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "JDR1": {
+ "description": "injected data register 1",
+ "offset": 128,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "JDATA1": {
+ "description": "JDATA1",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "JDR2": {
+ "description": "injected data register 2",
+ "offset": 132,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "JDATA2": {
+ "description": "JDATA2",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "JDR3": {
+ "description": "injected data register 3",
+ "offset": 136,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "JDATA3": {
+ "description": "JDATA3",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "JDR4": {
+ "description": "injected data register 4",
+ "offset": 140,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "JDATA4": {
+ "description": "JDATA4",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "AWD2CR": {
+ "description": "Analog Watchdog 2 Configuration\n Register",
+ "offset": 160,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "AWD2CH": {
+ "description": "AWD2CH",
+ "offset": 1,
+ "size": 18
+ }
+ }
+ }
+ },
+ "AWD3CR": {
+ "description": "Analog Watchdog 3 Configuration\n Register",
+ "offset": 164,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "AWD3CH": {
+ "description": "AWD3CH",
+ "offset": 1,
+ "size": 18
+ }
+ }
+ }
+ },
+ "DIFSEL": {
+ "description": "Differential Mode Selection Register\n 2",
+ "offset": 176,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DIFSEL_1_15": {
+ "description": "Differential mode for channels 15 to\n 1",
+ "offset": 1,
+ "size": 15
+ },
+ "DIFSEL_16_18": {
+ "description": "Differential mode for channels 18 to\n 16",
+ "offset": 16,
+ "size": 3,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "CALFACT": {
+ "description": "Calibration Factors",
+ "offset": 180,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CALFACT_D": {
+ "description": "CALFACT_D",
+ "offset": 16,
+ "size": 7
+ },
+ "CALFACT_S": {
+ "description": "CALFACT_S",
+ "offset": 0,
+ "size": 7
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "TIM8": {
+ "description": "Advanced-timers",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CEN": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ },
+ "UDIS": {
+ "description": "Update disable",
+ "offset": 1,
+ "size": 1
+ },
+ "URS": {
+ "description": "Update request source",
+ "offset": 2,
+ "size": 1
+ },
+ "OPM": {
+ "description": "One-pulse mode",
+ "offset": 3,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Direction",
+ "offset": 4,
+ "size": 1
+ },
+ "CMS": {
+ "description": "Center-aligned mode\n selection",
+ "offset": 5,
+ "size": 2
+ },
+ "ARPE": {
+ "description": "Auto-reload preload enable",
+ "offset": 7,
+ "size": 1
+ },
+ "CKD": {
+ "description": "Clock division",
+ "offset": 8,
+ "size": 2
+ },
+ "UIFREMAP": {
+ "description": "UIF status bit remapping",
+ "offset": 11,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCPC": {
+ "description": "Capture/compare preloaded\n control",
+ "offset": 0,
+ "size": 1
+ },
+ "CCUS": {
+ "description": "Capture/compare control update\n selection",
+ "offset": 2,
+ "size": 1
+ },
+ "CCDS": {
+ "description": "Capture/compare DMA\n selection",
+ "offset": 3,
+ "size": 1
+ },
+ "MMS": {
+ "description": "Master mode selection",
+ "offset": 4,
+ "size": 3
+ },
+ "TI1S": {
+ "description": "TI1 selection",
+ "offset": 7,
+ "size": 1
+ },
+ "OIS1": {
+ "description": "Output Idle state 1",
+ "offset": 8,
+ "size": 1
+ },
+ "OIS1N": {
+ "description": "Output Idle state 1",
+ "offset": 9,
+ "size": 1
+ },
+ "OIS2": {
+ "description": "Output Idle state 2",
+ "offset": 10,
+ "size": 1
+ },
+ "OIS2N": {
+ "description": "Output Idle state 2",
+ "offset": 11,
+ "size": 1
+ },
+ "OIS3": {
+ "description": "Output Idle state 3",
+ "offset": 12,
+ "size": 1
+ },
+ "OIS3N": {
+ "description": "Output Idle state 3",
+ "offset": 13,
+ "size": 1
+ },
+ "OIS4": {
+ "description": "Output Idle state 4",
+ "offset": 14,
+ "size": 1
+ },
+ "OIS5": {
+ "description": "Output Idle state 5",
+ "offset": 16,
+ "size": 1
+ },
+ "OIS6": {
+ "description": "Output Idle state 6",
+ "offset": 18,
+ "size": 1
+ },
+ "MMS2": {
+ "description": "Master mode selection 2",
+ "offset": 20,
+ "size": 4
+ }
+ }
+ }
+ },
+ "SMCR": {
+ "description": "slave mode control register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SMS": {
+ "description": "Slave mode selection",
+ "offset": 0,
+ "size": 3
+ },
+ "OCCS": {
+ "description": "OCREF clear selection",
+ "offset": 3,
+ "size": 1
+ },
+ "TS": {
+ "description": "Trigger selection",
+ "offset": 4,
+ "size": 3
+ },
+ "MSM": {
+ "description": "Master/Slave mode",
+ "offset": 7,
+ "size": 1
+ },
+ "ETF": {
+ "description": "External trigger filter",
+ "offset": 8,
+ "size": 4
+ },
+ "ETPS": {
+ "description": "External trigger prescaler",
+ "offset": 12,
+ "size": 2
+ },
+ "ECE": {
+ "description": "External clock enable",
+ "offset": 14,
+ "size": 1
+ },
+ "ETP": {
+ "description": "External trigger polarity",
+ "offset": 15,
+ "size": 1
+ },
+ "SMS3": {
+ "description": "Slave mode selection bit 3",
+ "offset": 16,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DIER": {
+ "description": "DMA/Interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TDE": {
+ "description": "Trigger DMA request enable",
+ "offset": 14,
+ "size": 1
+ },
+ "COMDE": {
+ "description": "COM DMA request enable",
+ "offset": 13,
+ "size": 1
+ },
+ "CC4DE": {
+ "description": "Capture/Compare 4 DMA request\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3DE": {
+ "description": "Capture/Compare 3 DMA request\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "CC2DE": {
+ "description": "Capture/Compare 2 DMA request\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC1DE": {
+ "description": "Capture/Compare 1 DMA request\n enable",
+ "offset": 9,
+ "size": 1
+ },
+ "UDE": {
+ "description": "Update DMA request enable",
+ "offset": 8,
+ "size": 1
+ },
+ "BIE": {
+ "description": "Break interrupt enable",
+ "offset": 7,
+ "size": 1
+ },
+ "TIE": {
+ "description": "Trigger interrupt enable",
+ "offset": 6,
+ "size": 1
+ },
+ "COMIE": {
+ "description": "COM interrupt enable",
+ "offset": 5,
+ "size": 1
+ },
+ "CC4IE": {
+ "description": "Capture/Compare 4 interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3IE": {
+ "description": "Capture/Compare 3 interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2IE": {
+ "description": "Capture/Compare 2 interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IE": {
+ "description": "Capture/Compare 1 interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "UIE": {
+ "description": "Update interrupt enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "UIF": {
+ "description": "Update interrupt flag",
+ "offset": 0,
+ "size": 1
+ },
+ "CC1IF": {
+ "description": "Capture/compare 1 interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "CC2IF": {
+ "description": "Capture/Compare 2 interrupt\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "CC3IF": {
+ "description": "Capture/Compare 3 interrupt\n flag",
+ "offset": 3,
+ "size": 1
+ },
+ "CC4IF": {
+ "description": "Capture/Compare 4 interrupt\n flag",
+ "offset": 4,
+ "size": 1
+ },
+ "COMIF": {
+ "description": "COM interrupt flag",
+ "offset": 5,
+ "size": 1
+ },
+ "TIF": {
+ "description": "Trigger interrupt flag",
+ "offset": 6,
+ "size": 1
+ },
+ "BIF": {
+ "description": "Break interrupt flag",
+ "offset": 7,
+ "size": 1
+ },
+ "B2IF": {
+ "description": "Break 2 interrupt flag",
+ "offset": 8,
+ "size": 1
+ },
+ "CC1OF": {
+ "description": "Capture/Compare 1 overcapture\n flag",
+ "offset": 9,
+ "size": 1
+ },
+ "CC2OF": {
+ "description": "Capture/compare 2 overcapture\n flag",
+ "offset": 10,
+ "size": 1
+ },
+ "CC3OF": {
+ "description": "Capture/Compare 3 overcapture\n flag",
+ "offset": 11,
+ "size": 1
+ },
+ "CC4OF": {
+ "description": "Capture/Compare 4 overcapture\n flag",
+ "offset": 12,
+ "size": 1
+ },
+ "C5IF": {
+ "description": "Capture/Compare 5 interrupt\n flag",
+ "offset": 16,
+ "size": 1
+ },
+ "C6IF": {
+ "description": "Capture/Compare 6 interrupt\n flag",
+ "offset": 17,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EGR": {
+ "description": "event generation register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "UG": {
+ "description": "Update generation",
+ "offset": 0,
+ "size": 1
+ },
+ "CC1G": {
+ "description": "Capture/compare 1\n generation",
+ "offset": 1,
+ "size": 1
+ },
+ "CC2G": {
+ "description": "Capture/compare 2\n generation",
+ "offset": 2,
+ "size": 1
+ },
+ "CC3G": {
+ "description": "Capture/compare 3\n generation",
+ "offset": 3,
+ "size": 1
+ },
+ "CC4G": {
+ "description": "Capture/compare 4\n generation",
+ "offset": 4,
+ "size": 1
+ },
+ "COMG": {
+ "description": "Capture/Compare control update\n generation",
+ "offset": 5,
+ "size": 1
+ },
+ "TG": {
+ "description": "Trigger generation",
+ "offset": 6,
+ "size": 1
+ },
+ "BG": {
+ "description": "Break generation",
+ "offset": 7,
+ "size": 1
+ },
+ "B2G": {
+ "description": "Break 2 generation",
+ "offset": 8,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Output": {
+ "description": "capture/compare mode register (output\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OC2CE": {
+ "description": "Output Compare 2 clear\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "OC2M": {
+ "description": "Output Compare 2 mode",
+ "offset": 12,
+ "size": 3
+ },
+ "OC2PE": {
+ "description": "Output Compare 2 preload\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "OC2FE": {
+ "description": "Output Compare 2 fast\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC2S": {
+ "description": "Capture/Compare 2\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "OC1CE": {
+ "description": "Output Compare 1 clear\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "OC1M": {
+ "description": "Output Compare 1 mode",
+ "offset": 4,
+ "size": 3
+ },
+ "OC1PE": {
+ "description": "Output Compare 1 preload\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "OC1FE": {
+ "description": "Output Compare 1 fast\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ },
+ "OC1M_3": {
+ "description": "Output Compare 1 mode bit\n 3",
+ "offset": 16,
+ "size": 1
+ },
+ "OC2M_3": {
+ "description": "Output Compare 2 mode bit\n 3",
+ "offset": 24,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Input": {
+ "description": "capture/compare mode register 1 (input\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC2F": {
+ "description": "Input capture 2 filter",
+ "offset": 12,
+ "size": 4
+ },
+ "IC2PCS": {
+ "description": "Input capture 2 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC2S": {
+ "description": "Capture/Compare 2\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC1F": {
+ "description": "Input capture 1 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "IC1PCS": {
+ "description": "Input capture 1 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR2_Output": {
+ "description": "capture/compare mode register (output\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OC4CE": {
+ "description": "Output compare 4 clear\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "OC4M": {
+ "description": "Output compare 4 mode",
+ "offset": 12,
+ "size": 3
+ },
+ "OC4PE": {
+ "description": "Output compare 4 preload\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "OC4FE": {
+ "description": "Output compare 4 fast\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC4S": {
+ "description": "Capture/Compare 4\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "OC3CE": {
+ "description": "Output compare 3 clear\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "OC3M": {
+ "description": "Output compare 3 mode",
+ "offset": 4,
+ "size": 3
+ },
+ "OC3PE": {
+ "description": "Output compare 3 preload\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "OC3FE": {
+ "description": "Output compare 3 fast\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC3S": {
+ "description": "Capture/Compare 3\n selection",
+ "offset": 0,
+ "size": 2
+ },
+ "OC3M_3": {
+ "description": "Output Compare 3 mode bit\n 3",
+ "offset": 16,
+ "size": 1
+ },
+ "OC4M_3": {
+ "description": "Output Compare 4 mode bit\n 3",
+ "offset": 24,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR2_Input": {
+ "description": "capture/compare mode register 2 (input\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC4F": {
+ "description": "Input capture 4 filter",
+ "offset": 12,
+ "size": 4
+ },
+ "IC4PSC": {
+ "description": "Input capture 4 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC4S": {
+ "description": "Capture/Compare 4\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC3F": {
+ "description": "Input capture 3 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "IC3PSC": {
+ "description": "Input capture 3 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC3S": {
+ "description": "Capture/compare 3\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCER": {
+ "description": "capture/compare enable\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC1E": {
+ "description": "Capture/Compare 1 output\n enable",
+ "offset": 0,
+ "size": 1
+ },
+ "CC1P": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 1,
+ "size": 1
+ },
+ "CC1NE": {
+ "description": "Capture/Compare 1 complementary output\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1NP": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2E": {
+ "description": "Capture/Compare 2 output\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC2P": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 5,
+ "size": 1
+ },
+ "CC2NE": {
+ "description": "Capture/Compare 2 complementary output\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "CC2NP": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 7,
+ "size": 1
+ },
+ "CC3E": {
+ "description": "Capture/Compare 3 output\n enable",
+ "offset": 8,
+ "size": 1
+ },
+ "CC3P": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 9,
+ "size": 1
+ },
+ "CC3NE": {
+ "description": "Capture/Compare 3 complementary output\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC3NP": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 11,
+ "size": 1
+ },
+ "CC4E": {
+ "description": "Capture/Compare 4 output\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "CC4P": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 13,
+ "size": 1
+ },
+ "CC4NP": {
+ "description": "Capture/Compare 4 output\n Polarity",
+ "offset": 15,
+ "size": 1
+ },
+ "CC5E": {
+ "description": "Capture/Compare 5 output\n enable",
+ "offset": 16,
+ "size": 1
+ },
+ "CC5P": {
+ "description": "Capture/Compare 5 output\n Polarity",
+ "offset": 17,
+ "size": 1
+ },
+ "CC6E": {
+ "description": "Capture/Compare 6 output\n enable",
+ "offset": 20,
+ "size": 1
+ },
+ "CC6P": {
+ "description": "Capture/Compare 6 output\n Polarity",
+ "offset": 21,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNT": {
+ "description": "counter",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNT": {
+ "description": "counter value",
+ "offset": 0,
+ "size": 16
+ },
+ "UIFCPY": {
+ "description": "UIF copy",
+ "offset": 31,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "PSC": {
+ "description": "prescaler",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ARR": {
+ "description": "auto-reload register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARR": {
+ "description": "Auto-reload value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "RCR": {
+ "description": "repetition counter register",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "REP": {
+ "description": "Repetition counter value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR1": {
+ "description": "capture/compare register 1",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR1": {
+ "description": "Capture/Compare 1 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR2": {
+ "description": "capture/compare register 2",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR2": {
+ "description": "Capture/Compare 2 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR3": {
+ "description": "capture/compare register 3",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR3": {
+ "description": "Capture/Compare 3 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR4": {
+ "description": "capture/compare register 4",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR4": {
+ "description": "Capture/Compare 3 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "BDTR": {
+ "description": "break and dead-time register",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DTG": {
+ "description": "Dead-time generator setup",
+ "offset": 0,
+ "size": 8
+ },
+ "LOCK": {
+ "description": "Lock configuration",
+ "offset": 8,
+ "size": 2
+ },
+ "OSSI": {
+ "description": "Off-state selection for Idle\n mode",
+ "offset": 10,
+ "size": 1
+ },
+ "OSSR": {
+ "description": "Off-state selection for Run\n mode",
+ "offset": 11,
+ "size": 1
+ },
+ "BKE": {
+ "description": "Break enable",
+ "offset": 12,
+ "size": 1
+ },
+ "BKP": {
+ "description": "Break polarity",
+ "offset": 13,
+ "size": 1
+ },
+ "AOE": {
+ "description": "Automatic output enable",
+ "offset": 14,
+ "size": 1
+ },
+ "MOE": {
+ "description": "Main output enable",
+ "offset": 15,
+ "size": 1
+ },
+ "BKF": {
+ "description": "Break filter",
+ "offset": 16,
+ "size": 4
+ },
+ "BK2F": {
+ "description": "Break 2 filter",
+ "offset": 20,
+ "size": 4
+ },
+ "BK2E": {
+ "description": "Break 2 enable",
+ "offset": 24,
+ "size": 1
+ },
+ "BK2P": {
+ "description": "Break 2 polarity",
+ "offset": 25,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DCR": {
+ "description": "DMA control register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBL": {
+ "description": "DMA burst length",
+ "offset": 8,
+ "size": 5
+ },
+ "DBA": {
+ "description": "DMA base address",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "DMAR": {
+ "description": "DMA address for full transfer",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAB": {
+ "description": "DMA register for burst\n accesses",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCMR3_Output": {
+ "description": "capture/compare mode register 3 (output\n mode)",
+ "offset": 84,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OC5FE": {
+ "description": "Output compare 5 fast\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "OC5PE": {
+ "description": "Output compare 5 preload\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "OC5M": {
+ "description": "Output compare 5 mode",
+ "offset": 4,
+ "size": 3
+ },
+ "OC5CE": {
+ "description": "Output compare 5 clear\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "OC6FE": {
+ "description": "Output compare 6 fast\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "OC6PE": {
+ "description": "Output compare 6 preload\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "OC6M": {
+ "description": "Output compare 6 mode",
+ "offset": 12,
+ "size": 3
+ },
+ "OC6CE": {
+ "description": "Output compare 6 clear\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "OC5M_3": {
+ "description": "Outout Compare 5 mode bit\n 3",
+ "offset": 16,
+ "size": 1
+ },
+ "OC6M_3": {
+ "description": "Outout Compare 6 mode bit\n 3",
+ "offset": 24,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCR5": {
+ "description": "capture/compare register 5",
+ "offset": 88,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR5": {
+ "description": "Capture/Compare 5 value",
+ "offset": 0,
+ "size": 16
+ },
+ "GC5C1": {
+ "description": "Group Channel 5 and Channel\n 1",
+ "offset": 29,
+ "size": 1
+ },
+ "GC5C2": {
+ "description": "Group Channel 5 and Channel\n 2",
+ "offset": 30,
+ "size": 1
+ },
+ "GC5C3": {
+ "description": "Group Channel 5 and Channel\n 3",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCR6": {
+ "description": "capture/compare register 6",
+ "offset": 92,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR6": {
+ "description": "Capture/Compare 6 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OR": {
+ "description": "option registers",
+ "offset": 96,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIM8_ETR_ADC2_RMP": {
+ "description": "TIM8_ETR_ADC2 remapping\n capability",
+ "offset": 0,
+ "size": 2
+ },
+ "TIM8_ETR_ADC3_RMP": {
+ "description": "TIM8_ETR_ADC3 remapping\n capability",
+ "offset": 2,
+ "size": 2
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "DAC": {
+ "description": "Digital-to-analog converter",
+ "children": {
+ "registers": {
+ "CR": {
+ "description": "control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAUDRIE2": {
+ "description": "DAC channel2 DMA underrun interrupt\n enable",
+ "offset": 29,
+ "size": 1
+ },
+ "DMAEN2": {
+ "description": "DAC channel2 DMA enable",
+ "offset": 28,
+ "size": 1
+ },
+ "MAMP2": {
+ "description": "DAC channel2 mask/amplitude\n selector",
+ "offset": 24,
+ "size": 4
+ },
+ "WAVE2": {
+ "description": "DAC channel2 noise/triangle wave\n generation enable",
+ "offset": 22,
+ "size": 2
+ },
+ "TSEL2": {
+ "description": "DAC channel2 trigger\n selection",
+ "offset": 19,
+ "size": 3
+ },
+ "TEN2": {
+ "description": "DAC channel2 trigger\n enable",
+ "offset": 18,
+ "size": 1
+ },
+ "BOFF2": {
+ "description": "DAC channel2 output buffer\n disable",
+ "offset": 17,
+ "size": 1
+ },
+ "EN2": {
+ "description": "DAC channel2 enable",
+ "offset": 16,
+ "size": 1
+ },
+ "DMAUDRIE1": {
+ "description": "DAC channel1 DMA Underrun Interrupt\n enable",
+ "offset": 13,
+ "size": 1
+ },
+ "DMAEN1": {
+ "description": "DAC channel1 DMA enable",
+ "offset": 12,
+ "size": 1
+ },
+ "MAMP1": {
+ "description": "DAC channel1 mask/amplitude\n selector",
+ "offset": 8,
+ "size": 4
+ },
+ "WAVE1": {
+ "description": "DAC channel1 noise/triangle wave\n generation enable",
+ "offset": 6,
+ "size": 2
+ },
+ "TSEL1": {
+ "description": "DAC channel1 trigger\n selection",
+ "offset": 3,
+ "size": 3
+ },
+ "TEN1": {
+ "description": "DAC channel1 trigger\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "BOFF1": {
+ "description": "DAC channel1 output buffer\n disable",
+ "offset": 1,
+ "size": 1
+ },
+ "EN1": {
+ "description": "DAC channel1 enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SWTRIGR": {
+ "description": "software trigger register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "SWTRIG2": {
+ "description": "DAC channel2 software\n trigger",
+ "offset": 1,
+ "size": 1
+ },
+ "SWTRIG1": {
+ "description": "DAC channel1 software\n trigger",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DHR12R1": {
+ "description": "channel1 12-bit right-aligned data holding\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC1DHR": {
+ "description": "DAC channel1 12-bit right-aligned\n data",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DHR12L1": {
+ "description": "channel1 12-bit left aligned data holding\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC1DHR": {
+ "description": "DAC channel1 12-bit left-aligned\n data",
+ "offset": 4,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DHR8R1": {
+ "description": "channel1 8-bit right aligned data holding\n register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC1DHR": {
+ "description": "DAC channel1 8-bit right-aligned\n data",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "DHR12R2": {
+ "description": "channel2 12-bit right aligned data holding\n register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC2DHR": {
+ "description": "DAC channel2 12-bit right-aligned\n data",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DHR12L2": {
+ "description": "channel2 12-bit left aligned data holding\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC2DHR": {
+ "description": "DAC channel2 12-bit left-aligned\n data",
+ "offset": 4,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DHR8R2": {
+ "description": "channel2 8-bit right-aligned data holding\n register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC2DHR": {
+ "description": "DAC channel2 8-bit right-aligned\n data",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "DHR12RD": {
+ "description": "Dual DAC 12-bit right-aligned data holding\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC2DHR": {
+ "description": "DAC channel2 12-bit right-aligned\n data",
+ "offset": 16,
+ "size": 12
+ },
+ "DACC1DHR": {
+ "description": "DAC channel1 12-bit right-aligned\n data",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DHR12LD": {
+ "description": "DUAL DAC 12-bit left aligned data holding\n register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC2DHR": {
+ "description": "DAC channel2 12-bit left-aligned\n data",
+ "offset": 20,
+ "size": 12
+ },
+ "DACC1DHR": {
+ "description": "DAC channel1 12-bit left-aligned\n data",
+ "offset": 4,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DHR8RD": {
+ "description": "DUAL DAC 8-bit right aligned data holding\n register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC2DHR": {
+ "description": "DAC channel2 8-bit right-aligned\n data",
+ "offset": 8,
+ "size": 8
+ },
+ "DACC1DHR": {
+ "description": "DAC channel1 8-bit right-aligned\n data",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "DOR1": {
+ "description": "channel1 data output register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DACC1DOR": {
+ "description": "DAC channel1 data output",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DOR2": {
+ "description": "channel2 data output register",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DACC2DOR": {
+ "description": "DAC channel2 data output",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAUDR2": {
+ "description": "DAC channel2 DMA underrun\n flag",
+ "offset": 29,
+ "size": 1
+ },
+ "DMAUDR1": {
+ "description": "DAC channel1 DMA underrun\n flag",
+ "offset": 13,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "EXTI": {
+ "description": "External interrupt/event\n controller",
+ "children": {
+ "registers": {
+ "IMR1": {
+ "description": "Interrupt mask register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 528482304,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MR0": {
+ "description": "Interrupt Mask on line 0",
+ "offset": 0,
+ "size": 1
+ },
+ "MR1": {
+ "description": "Interrupt Mask on line 1",
+ "offset": 1,
+ "size": 1
+ },
+ "MR2": {
+ "description": "Interrupt Mask on line 2",
+ "offset": 2,
+ "size": 1
+ },
+ "MR3": {
+ "description": "Interrupt Mask on line 3",
+ "offset": 3,
+ "size": 1
+ },
+ "MR4": {
+ "description": "Interrupt Mask on line 4",
+ "offset": 4,
+ "size": 1
+ },
+ "MR5": {
+ "description": "Interrupt Mask on line 5",
+ "offset": 5,
+ "size": 1
+ },
+ "MR6": {
+ "description": "Interrupt Mask on line 6",
+ "offset": 6,
+ "size": 1
+ },
+ "MR7": {
+ "description": "Interrupt Mask on line 7",
+ "offset": 7,
+ "size": 1
+ },
+ "MR8": {
+ "description": "Interrupt Mask on line 8",
+ "offset": 8,
+ "size": 1
+ },
+ "MR9": {
+ "description": "Interrupt Mask on line 9",
+ "offset": 9,
+ "size": 1
+ },
+ "MR10": {
+ "description": "Interrupt Mask on line 10",
+ "offset": 10,
+ "size": 1
+ },
+ "MR11": {
+ "description": "Interrupt Mask on line 11",
+ "offset": 11,
+ "size": 1
+ },
+ "MR12": {
+ "description": "Interrupt Mask on line 12",
+ "offset": 12,
+ "size": 1
+ },
+ "MR13": {
+ "description": "Interrupt Mask on line 13",
+ "offset": 13,
+ "size": 1
+ },
+ "MR14": {
+ "description": "Interrupt Mask on line 14",
+ "offset": 14,
+ "size": 1
+ },
+ "MR15": {
+ "description": "Interrupt Mask on line 15",
+ "offset": 15,
+ "size": 1
+ },
+ "MR16": {
+ "description": "Interrupt Mask on line 16",
+ "offset": 16,
+ "size": 1
+ },
+ "MR17": {
+ "description": "Interrupt Mask on line 17",
+ "offset": 17,
+ "size": 1
+ },
+ "MR18": {
+ "description": "Interrupt Mask on line 18",
+ "offset": 18,
+ "size": 1
+ },
+ "MR19": {
+ "description": "Interrupt Mask on line 19",
+ "offset": 19,
+ "size": 1
+ },
+ "MR20": {
+ "description": "Interrupt Mask on line 20",
+ "offset": 20,
+ "size": 1
+ },
+ "MR21": {
+ "description": "Interrupt Mask on line 21",
+ "offset": 21,
+ "size": 1
+ },
+ "MR22": {
+ "description": "Interrupt Mask on line 22",
+ "offset": 22,
+ "size": 1
+ },
+ "MR23": {
+ "description": "Interrupt Mask on line 23",
+ "offset": 23,
+ "size": 1
+ },
+ "MR24": {
+ "description": "Interrupt Mask on line 24",
+ "offset": 24,
+ "size": 1
+ },
+ "MR25": {
+ "description": "Interrupt Mask on line 25",
+ "offset": 25,
+ "size": 1
+ },
+ "MR26": {
+ "description": "Interrupt Mask on line 26",
+ "offset": 26,
+ "size": 1
+ },
+ "MR27": {
+ "description": "Interrupt Mask on line 27",
+ "offset": 27,
+ "size": 1
+ },
+ "MR28": {
+ "description": "Interrupt Mask on line 28",
+ "offset": 28,
+ "size": 1
+ },
+ "MR29": {
+ "description": "Interrupt Mask on line 29",
+ "offset": 29,
+ "size": 1
+ },
+ "MR30": {
+ "description": "Interrupt Mask on line 30",
+ "offset": 30,
+ "size": 1
+ },
+ "MR31": {
+ "description": "Interrupt Mask on line 31",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EMR1": {
+ "description": "Event mask register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MR0": {
+ "description": "Event Mask on line 0",
+ "offset": 0,
+ "size": 1
+ },
+ "MR1": {
+ "description": "Event Mask on line 1",
+ "offset": 1,
+ "size": 1
+ },
+ "MR2": {
+ "description": "Event Mask on line 2",
+ "offset": 2,
+ "size": 1
+ },
+ "MR3": {
+ "description": "Event Mask on line 3",
+ "offset": 3,
+ "size": 1
+ },
+ "MR4": {
+ "description": "Event Mask on line 4",
+ "offset": 4,
+ "size": 1
+ },
+ "MR5": {
+ "description": "Event Mask on line 5",
+ "offset": 5,
+ "size": 1
+ },
+ "MR6": {
+ "description": "Event Mask on line 6",
+ "offset": 6,
+ "size": 1
+ },
+ "MR7": {
+ "description": "Event Mask on line 7",
+ "offset": 7,
+ "size": 1
+ },
+ "MR8": {
+ "description": "Event Mask on line 8",
+ "offset": 8,
+ "size": 1
+ },
+ "MR9": {
+ "description": "Event Mask on line 9",
+ "offset": 9,
+ "size": 1
+ },
+ "MR10": {
+ "description": "Event Mask on line 10",
+ "offset": 10,
+ "size": 1
+ },
+ "MR11": {
+ "description": "Event Mask on line 11",
+ "offset": 11,
+ "size": 1
+ },
+ "MR12": {
+ "description": "Event Mask on line 12",
+ "offset": 12,
+ "size": 1
+ },
+ "MR13": {
+ "description": "Event Mask on line 13",
+ "offset": 13,
+ "size": 1
+ },
+ "MR14": {
+ "description": "Event Mask on line 14",
+ "offset": 14,
+ "size": 1
+ },
+ "MR15": {
+ "description": "Event Mask on line 15",
+ "offset": 15,
+ "size": 1
+ },
+ "MR16": {
+ "description": "Event Mask on line 16",
+ "offset": 16,
+ "size": 1
+ },
+ "MR17": {
+ "description": "Event Mask on line 17",
+ "offset": 17,
+ "size": 1
+ },
+ "MR18": {
+ "description": "Event Mask on line 18",
+ "offset": 18,
+ "size": 1
+ },
+ "MR19": {
+ "description": "Event Mask on line 19",
+ "offset": 19,
+ "size": 1
+ },
+ "MR20": {
+ "description": "Event Mask on line 20",
+ "offset": 20,
+ "size": 1
+ },
+ "MR21": {
+ "description": "Event Mask on line 21",
+ "offset": 21,
+ "size": 1
+ },
+ "MR22": {
+ "description": "Event Mask on line 22",
+ "offset": 22,
+ "size": 1
+ },
+ "MR23": {
+ "description": "Event Mask on line 23",
+ "offset": 23,
+ "size": 1
+ },
+ "MR24": {
+ "description": "Event Mask on line 24",
+ "offset": 24,
+ "size": 1
+ },
+ "MR25": {
+ "description": "Event Mask on line 25",
+ "offset": 25,
+ "size": 1
+ },
+ "MR26": {
+ "description": "Event Mask on line 26",
+ "offset": 26,
+ "size": 1
+ },
+ "MR27": {
+ "description": "Event Mask on line 27",
+ "offset": 27,
+ "size": 1
+ },
+ "MR28": {
+ "description": "Event Mask on line 28",
+ "offset": 28,
+ "size": 1
+ },
+ "MR29": {
+ "description": "Event Mask on line 29",
+ "offset": 29,
+ "size": 1
+ },
+ "MR30": {
+ "description": "Event Mask on line 30",
+ "offset": 30,
+ "size": 1
+ },
+ "MR31": {
+ "description": "Event Mask on line 31",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "RTSR1": {
+ "description": "Rising Trigger selection\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TR0": {
+ "description": "Rising trigger event configuration of\n line 0",
+ "offset": 0,
+ "size": 1
+ },
+ "TR1": {
+ "description": "Rising trigger event configuration of\n line 1",
+ "offset": 1,
+ "size": 1
+ },
+ "TR2": {
+ "description": "Rising trigger event configuration of\n line 2",
+ "offset": 2,
+ "size": 1
+ },
+ "TR3": {
+ "description": "Rising trigger event configuration of\n line 3",
+ "offset": 3,
+ "size": 1
+ },
+ "TR4": {
+ "description": "Rising trigger event configuration of\n line 4",
+ "offset": 4,
+ "size": 1
+ },
+ "TR5": {
+ "description": "Rising trigger event configuration of\n line 5",
+ "offset": 5,
+ "size": 1
+ },
+ "TR6": {
+ "description": "Rising trigger event configuration of\n line 6",
+ "offset": 6,
+ "size": 1
+ },
+ "TR7": {
+ "description": "Rising trigger event configuration of\n line 7",
+ "offset": 7,
+ "size": 1
+ },
+ "TR8": {
+ "description": "Rising trigger event configuration of\n line 8",
+ "offset": 8,
+ "size": 1
+ },
+ "TR9": {
+ "description": "Rising trigger event configuration of\n line 9",
+ "offset": 9,
+ "size": 1
+ },
+ "TR10": {
+ "description": "Rising trigger event configuration of\n line 10",
+ "offset": 10,
+ "size": 1
+ },
+ "TR11": {
+ "description": "Rising trigger event configuration of\n line 11",
+ "offset": 11,
+ "size": 1
+ },
+ "TR12": {
+ "description": "Rising trigger event configuration of\n line 12",
+ "offset": 12,
+ "size": 1
+ },
+ "TR13": {
+ "description": "Rising trigger event configuration of\n line 13",
+ "offset": 13,
+ "size": 1
+ },
+ "TR14": {
+ "description": "Rising trigger event configuration of\n line 14",
+ "offset": 14,
+ "size": 1
+ },
+ "TR15": {
+ "description": "Rising trigger event configuration of\n line 15",
+ "offset": 15,
+ "size": 1
+ },
+ "TR16": {
+ "description": "Rising trigger event configuration of\n line 16",
+ "offset": 16,
+ "size": 1
+ },
+ "TR17": {
+ "description": "Rising trigger event configuration of\n line 17",
+ "offset": 17,
+ "size": 1
+ },
+ "TR18": {
+ "description": "Rising trigger event configuration of\n line 18",
+ "offset": 18,
+ "size": 1
+ },
+ "TR19": {
+ "description": "Rising trigger event configuration of\n line 19",
+ "offset": 19,
+ "size": 1
+ },
+ "TR20": {
+ "description": "Rising trigger event configuration of\n line 20",
+ "offset": 20,
+ "size": 1
+ },
+ "TR21": {
+ "description": "Rising trigger event configuration of\n line 21",
+ "offset": 21,
+ "size": 1
+ },
+ "TR22": {
+ "description": "Rising trigger event configuration of\n line 22",
+ "offset": 22,
+ "size": 1
+ },
+ "TR29": {
+ "description": "Rising trigger event configuration of\n line 29",
+ "offset": 29,
+ "size": 1
+ },
+ "TR30": {
+ "description": "Rising trigger event configuration of\n line 30",
+ "offset": 30,
+ "size": 1
+ },
+ "TR31": {
+ "description": "Rising trigger event configuration of\n line 31",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FTSR1": {
+ "description": "Falling Trigger selection\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TR0": {
+ "description": "Falling trigger event configuration of\n line 0",
+ "offset": 0,
+ "size": 1
+ },
+ "TR1": {
+ "description": "Falling trigger event configuration of\n line 1",
+ "offset": 1,
+ "size": 1
+ },
+ "TR2": {
+ "description": "Falling trigger event configuration of\n line 2",
+ "offset": 2,
+ "size": 1
+ },
+ "TR3": {
+ "description": "Falling trigger event configuration of\n line 3",
+ "offset": 3,
+ "size": 1
+ },
+ "TR4": {
+ "description": "Falling trigger event configuration of\n line 4",
+ "offset": 4,
+ "size": 1
+ },
+ "TR5": {
+ "description": "Falling trigger event configuration of\n line 5",
+ "offset": 5,
+ "size": 1
+ },
+ "TR6": {
+ "description": "Falling trigger event configuration of\n line 6",
+ "offset": 6,
+ "size": 1
+ },
+ "TR7": {
+ "description": "Falling trigger event configuration of\n line 7",
+ "offset": 7,
+ "size": 1
+ },
+ "TR8": {
+ "description": "Falling trigger event configuration of\n line 8",
+ "offset": 8,
+ "size": 1
+ },
+ "TR9": {
+ "description": "Falling trigger event configuration of\n line 9",
+ "offset": 9,
+ "size": 1
+ },
+ "TR10": {
+ "description": "Falling trigger event configuration of\n line 10",
+ "offset": 10,
+ "size": 1
+ },
+ "TR11": {
+ "description": "Falling trigger event configuration of\n line 11",
+ "offset": 11,
+ "size": 1
+ },
+ "TR12": {
+ "description": "Falling trigger event configuration of\n line 12",
+ "offset": 12,
+ "size": 1
+ },
+ "TR13": {
+ "description": "Falling trigger event configuration of\n line 13",
+ "offset": 13,
+ "size": 1
+ },
+ "TR14": {
+ "description": "Falling trigger event configuration of\n line 14",
+ "offset": 14,
+ "size": 1
+ },
+ "TR15": {
+ "description": "Falling trigger event configuration of\n line 15",
+ "offset": 15,
+ "size": 1
+ },
+ "TR16": {
+ "description": "Falling trigger event configuration of\n line 16",
+ "offset": 16,
+ "size": 1
+ },
+ "TR17": {
+ "description": "Falling trigger event configuration of\n line 17",
+ "offset": 17,
+ "size": 1
+ },
+ "TR18": {
+ "description": "Falling trigger event configuration of\n line 18",
+ "offset": 18,
+ "size": 1
+ },
+ "TR19": {
+ "description": "Falling trigger event configuration of\n line 19",
+ "offset": 19,
+ "size": 1
+ },
+ "TR20": {
+ "description": "Falling trigger event configuration of\n line 20",
+ "offset": 20,
+ "size": 1
+ },
+ "TR21": {
+ "description": "Falling trigger event configuration of\n line 21",
+ "offset": 21,
+ "size": 1
+ },
+ "TR22": {
+ "description": "Falling trigger event configuration of\n line 22",
+ "offset": 22,
+ "size": 1
+ },
+ "TR29": {
+ "description": "Falling trigger event configuration of\n line 29",
+ "offset": 29,
+ "size": 1
+ },
+ "TR30": {
+ "description": "Falling trigger event configuration of\n line 30.",
+ "offset": 30,
+ "size": 1
+ },
+ "TR31": {
+ "description": "Falling trigger event configuration of\n line 31",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SWIER1": {
+ "description": "Software interrupt event\n register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SWIER0": {
+ "description": "Software Interrupt on line\n 0",
+ "offset": 0,
+ "size": 1
+ },
+ "SWIER1": {
+ "description": "Software Interrupt on line\n 1",
+ "offset": 1,
+ "size": 1
+ },
+ "SWIER2": {
+ "description": "Software Interrupt on line\n 2",
+ "offset": 2,
+ "size": 1
+ },
+ "SWIER3": {
+ "description": "Software Interrupt on line\n 3",
+ "offset": 3,
+ "size": 1
+ },
+ "SWIER4": {
+ "description": "Software Interrupt on line\n 4",
+ "offset": 4,
+ "size": 1
+ },
+ "SWIER5": {
+ "description": "Software Interrupt on line\n 5",
+ "offset": 5,
+ "size": 1
+ },
+ "SWIER6": {
+ "description": "Software Interrupt on line\n 6",
+ "offset": 6,
+ "size": 1
+ },
+ "SWIER7": {
+ "description": "Software Interrupt on line\n 7",
+ "offset": 7,
+ "size": 1
+ },
+ "SWIER8": {
+ "description": "Software Interrupt on line\n 8",
+ "offset": 8,
+ "size": 1
+ },
+ "SWIER9": {
+ "description": "Software Interrupt on line\n 9",
+ "offset": 9,
+ "size": 1
+ },
+ "SWIER10": {
+ "description": "Software Interrupt on line\n 10",
+ "offset": 10,
+ "size": 1
+ },
+ "SWIER11": {
+ "description": "Software Interrupt on line\n 11",
+ "offset": 11,
+ "size": 1
+ },
+ "SWIER12": {
+ "description": "Software Interrupt on line\n 12",
+ "offset": 12,
+ "size": 1
+ },
+ "SWIER13": {
+ "description": "Software Interrupt on line\n 13",
+ "offset": 13,
+ "size": 1
+ },
+ "SWIER14": {
+ "description": "Software Interrupt on line\n 14",
+ "offset": 14,
+ "size": 1
+ },
+ "SWIER15": {
+ "description": "Software Interrupt on line\n 15",
+ "offset": 15,
+ "size": 1
+ },
+ "SWIER16": {
+ "description": "Software Interrupt on line\n 16",
+ "offset": 16,
+ "size": 1
+ },
+ "SWIER17": {
+ "description": "Software Interrupt on line\n 17",
+ "offset": 17,
+ "size": 1
+ },
+ "SWIER18": {
+ "description": "Software Interrupt on line\n 18",
+ "offset": 18,
+ "size": 1
+ },
+ "SWIER19": {
+ "description": "Software Interrupt on line\n 19",
+ "offset": 19,
+ "size": 1
+ },
+ "SWIER20": {
+ "description": "Software Interrupt on line\n 20",
+ "offset": 20,
+ "size": 1
+ },
+ "SWIER21": {
+ "description": "Software Interrupt on line\n 21",
+ "offset": 21,
+ "size": 1
+ },
+ "SWIER22": {
+ "description": "Software Interrupt on line\n 22",
+ "offset": 22,
+ "size": 1
+ },
+ "SWIER29": {
+ "description": "Software Interrupt on line\n 29",
+ "offset": 29,
+ "size": 1
+ },
+ "SWIER30": {
+ "description": "Software Interrupt on line\n 309",
+ "offset": 30,
+ "size": 1
+ },
+ "SWIER31": {
+ "description": "Software Interrupt on line\n 319",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PR1": {
+ "description": "Pending register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PR0": {
+ "description": "Pending bit 0",
+ "offset": 0,
+ "size": 1
+ },
+ "PR1": {
+ "description": "Pending bit 1",
+ "offset": 1,
+ "size": 1
+ },
+ "PR2": {
+ "description": "Pending bit 2",
+ "offset": 2,
+ "size": 1
+ },
+ "PR3": {
+ "description": "Pending bit 3",
+ "offset": 3,
+ "size": 1
+ },
+ "PR4": {
+ "description": "Pending bit 4",
+ "offset": 4,
+ "size": 1
+ },
+ "PR5": {
+ "description": "Pending bit 5",
+ "offset": 5,
+ "size": 1
+ },
+ "PR6": {
+ "description": "Pending bit 6",
+ "offset": 6,
+ "size": 1
+ },
+ "PR7": {
+ "description": "Pending bit 7",
+ "offset": 7,
+ "size": 1
+ },
+ "PR8": {
+ "description": "Pending bit 8",
+ "offset": 8,
+ "size": 1
+ },
+ "PR9": {
+ "description": "Pending bit 9",
+ "offset": 9,
+ "size": 1
+ },
+ "PR10": {
+ "description": "Pending bit 10",
+ "offset": 10,
+ "size": 1
+ },
+ "PR11": {
+ "description": "Pending bit 11",
+ "offset": 11,
+ "size": 1
+ },
+ "PR12": {
+ "description": "Pending bit 12",
+ "offset": 12,
+ "size": 1
+ },
+ "PR13": {
+ "description": "Pending bit 13",
+ "offset": 13,
+ "size": 1
+ },
+ "PR14": {
+ "description": "Pending bit 14",
+ "offset": 14,
+ "size": 1
+ },
+ "PR15": {
+ "description": "Pending bit 15",
+ "offset": 15,
+ "size": 1
+ },
+ "PR16": {
+ "description": "Pending bit 16",
+ "offset": 16,
+ "size": 1
+ },
+ "PR17": {
+ "description": "Pending bit 17",
+ "offset": 17,
+ "size": 1
+ },
+ "PR18": {
+ "description": "Pending bit 18",
+ "offset": 18,
+ "size": 1
+ },
+ "PR19": {
+ "description": "Pending bit 19",
+ "offset": 19,
+ "size": 1
+ },
+ "PR20": {
+ "description": "Pending bit 20",
+ "offset": 20,
+ "size": 1
+ },
+ "PR21": {
+ "description": "Pending bit 21",
+ "offset": 21,
+ "size": 1
+ },
+ "PR22": {
+ "description": "Pending bit 22",
+ "offset": 22,
+ "size": 1
+ },
+ "PR29": {
+ "description": "Pending bit 29",
+ "offset": 29,
+ "size": 1
+ },
+ "PR30": {
+ "description": "Pending bit 30",
+ "offset": 30,
+ "size": 1
+ },
+ "PR31": {
+ "description": "Pending bit 31",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "IMR2": {
+ "description": "Interrupt mask register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 4294967292,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MR32": {
+ "description": "Interrupt Mask on external/internal line\n 32",
+ "offset": 0,
+ "size": 1
+ },
+ "MR33": {
+ "description": "Interrupt Mask on external/internal line\n 33",
+ "offset": 1,
+ "size": 1
+ },
+ "MR34": {
+ "description": "Interrupt Mask on external/internal line\n 34",
+ "offset": 2,
+ "size": 1
+ },
+ "MR35": {
+ "description": "Interrupt Mask on external/internal line\n 35",
+ "offset": 3,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EMR2": {
+ "description": "Event mask register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MR32": {
+ "description": "Event mask on external/internal line\n 32",
+ "offset": 0,
+ "size": 1
+ },
+ "MR33": {
+ "description": "Event mask on external/internal line\n 33",
+ "offset": 1,
+ "size": 1
+ },
+ "MR34": {
+ "description": "Event mask on external/internal line\n 34",
+ "offset": 2,
+ "size": 1
+ },
+ "MR35": {
+ "description": "Event mask on external/internal line\n 35",
+ "offset": 3,
+ "size": 1
+ }
+ }
+ }
+ },
+ "RTSR2": {
+ "description": "Rising Trigger selection\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TR32": {
+ "description": "Rising trigger event configuration bit\n of line 32",
+ "offset": 0,
+ "size": 1
+ },
+ "TR33": {
+ "description": "Rising trigger event configuration bit\n of line 33",
+ "offset": 1,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FTSR2": {
+ "description": "Falling Trigger selection\n register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TR32": {
+ "description": "Falling trigger event configuration bit\n of line 32",
+ "offset": 0,
+ "size": 1
+ },
+ "TR33": {
+ "description": "Falling trigger event configuration bit\n of line 33",
+ "offset": 1,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SWIER2": {
+ "description": "Software interrupt event\n register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SWIER32": {
+ "description": "Software interrupt on line\n 32",
+ "offset": 0,
+ "size": 1
+ },
+ "SWIER33": {
+ "description": "Software interrupt on line\n 33",
+ "offset": 1,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PR2": {
+ "description": "Pending register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PR32": {
+ "description": "Pending bit on line 32",
+ "offset": 0,
+ "size": 1
+ },
+ "PR33": {
+ "description": "Pending bit on line 33",
+ "offset": 1,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "PWR": {
+ "description": "Power control",
+ "children": {
+ "registers": {
+ "CR": {
+ "description": "power control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LPDS": {
+ "description": "Low-power deep sleep",
+ "offset": 0,
+ "size": 1
+ },
+ "PDDS": {
+ "description": "Power down deepsleep",
+ "offset": 1,
+ "size": 1
+ },
+ "CWUF": {
+ "description": "Clear wakeup flag",
+ "offset": 2,
+ "size": 1
+ },
+ "CSBF": {
+ "description": "Clear standby flag",
+ "offset": 3,
+ "size": 1
+ },
+ "PVDE": {
+ "description": "Power voltage detector\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "PLS": {
+ "description": "PVD level selection",
+ "offset": 5,
+ "size": 3
+ },
+ "DBP": {
+ "description": "Disable backup domain write\n protection",
+ "offset": 8,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CSR": {
+ "description": "power control/status register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "WUF": {
+ "description": "Wakeup flag",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SBF": {
+ "description": "Standby flag",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PVDO": {
+ "description": "PVD output",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EWUP1": {
+ "description": "Enable WKUP1 pin",
+ "offset": 8,
+ "size": 1
+ },
+ "EWUP2": {
+ "description": "Enable WKUP2 pin",
+ "offset": 9,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "CAN": {
+ "description": "Controller area network",
+ "children": {
+ "registers": {
+ "MCR": {
+ "description": "master control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 65538,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBF": {
+ "description": "DBF",
+ "offset": 16,
+ "size": 1
+ },
+ "RESET": {
+ "description": "RESET",
+ "offset": 15,
+ "size": 1
+ },
+ "TTCM": {
+ "description": "TTCM",
+ "offset": 7,
+ "size": 1
+ },
+ "ABOM": {
+ "description": "ABOM",
+ "offset": 6,
+ "size": 1
+ },
+ "AWUM": {
+ "description": "AWUM",
+ "offset": 5,
+ "size": 1
+ },
+ "NART": {
+ "description": "NART",
+ "offset": 4,
+ "size": 1
+ },
+ "RFLM": {
+ "description": "RFLM",
+ "offset": 3,
+ "size": 1
+ },
+ "TXFP": {
+ "description": "TXFP",
+ "offset": 2,
+ "size": 1
+ },
+ "SLEEP": {
+ "description": "SLEEP",
+ "offset": 1,
+ "size": 1
+ },
+ "INRQ": {
+ "description": "INRQ",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MSR": {
+ "description": "master status register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 3074,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RX": {
+ "description": "RX",
+ "offset": 11,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SAMP": {
+ "description": "SAMP",
+ "offset": 10,
+ "size": 1,
+ "access": "read-only"
+ },
+ "RXM": {
+ "description": "RXM",
+ "offset": 9,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TXM": {
+ "description": "TXM",
+ "offset": 8,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SLAKI": {
+ "description": "SLAKI",
+ "offset": 4,
+ "size": 1
+ },
+ "WKUI": {
+ "description": "WKUI",
+ "offset": 3,
+ "size": 1
+ },
+ "ERRI": {
+ "description": "ERRI",
+ "offset": 2,
+ "size": 1
+ },
+ "SLAK": {
+ "description": "SLAK",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "INAK": {
+ "description": "INAK",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "TSR": {
+ "description": "transmit status register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 469762048,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LOW2": {
+ "description": "Lowest priority flag for mailbox\n 2",
+ "offset": 31,
+ "size": 1,
+ "access": "read-only"
+ },
+ "LOW1": {
+ "description": "Lowest priority flag for mailbox\n 1",
+ "offset": 30,
+ "size": 1,
+ "access": "read-only"
+ },
+ "LOW0": {
+ "description": "Lowest priority flag for mailbox\n 0",
+ "offset": 29,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TME2": {
+ "description": "Lowest priority flag for mailbox\n 2",
+ "offset": 28,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TME1": {
+ "description": "Lowest priority flag for mailbox\n 1",
+ "offset": 27,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TME0": {
+ "description": "Lowest priority flag for mailbox\n 0",
+ "offset": 26,
+ "size": 1,
+ "access": "read-only"
+ },
+ "CODE": {
+ "description": "CODE",
+ "offset": 24,
+ "size": 2,
+ "access": "read-only"
+ },
+ "ABRQ2": {
+ "description": "ABRQ2",
+ "offset": 23,
+ "size": 1
+ },
+ "TERR2": {
+ "description": "TERR2",
+ "offset": 19,
+ "size": 1
+ },
+ "ALST2": {
+ "description": "ALST2",
+ "offset": 18,
+ "size": 1
+ },
+ "TXOK2": {
+ "description": "TXOK2",
+ "offset": 17,
+ "size": 1
+ },
+ "RQCP2": {
+ "description": "RQCP2",
+ "offset": 16,
+ "size": 1
+ },
+ "ABRQ1": {
+ "description": "ABRQ1",
+ "offset": 15,
+ "size": 1
+ },
+ "TERR1": {
+ "description": "TERR1",
+ "offset": 11,
+ "size": 1
+ },
+ "ALST1": {
+ "description": "ALST1",
+ "offset": 10,
+ "size": 1
+ },
+ "TXOK1": {
+ "description": "TXOK1",
+ "offset": 9,
+ "size": 1
+ },
+ "RQCP1": {
+ "description": "RQCP1",
+ "offset": 8,
+ "size": 1
+ },
+ "ABRQ0": {
+ "description": "ABRQ0",
+ "offset": 7,
+ "size": 1
+ },
+ "TERR0": {
+ "description": "TERR0",
+ "offset": 3,
+ "size": 1
+ },
+ "ALST0": {
+ "description": "ALST0",
+ "offset": 2,
+ "size": 1
+ },
+ "TXOK0": {
+ "description": "TXOK0",
+ "offset": 1,
+ "size": 1
+ },
+ "RQCP0": {
+ "description": "RQCP0",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "RF0R": {
+ "description": "receive FIFO 0 register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RFOM0": {
+ "description": "RFOM0",
+ "offset": 5,
+ "size": 1
+ },
+ "FOVR0": {
+ "description": "FOVR0",
+ "offset": 4,
+ "size": 1
+ },
+ "FULL0": {
+ "description": "FULL0",
+ "offset": 3,
+ "size": 1
+ },
+ "FMP0": {
+ "description": "FMP0",
+ "offset": 0,
+ "size": 2,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "RF1R": {
+ "description": "receive FIFO 1 register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RFOM1": {
+ "description": "RFOM1",
+ "offset": 5,
+ "size": 1
+ },
+ "FOVR1": {
+ "description": "FOVR1",
+ "offset": 4,
+ "size": 1
+ },
+ "FULL1": {
+ "description": "FULL1",
+ "offset": 3,
+ "size": 1
+ },
+ "FMP1": {
+ "description": "FMP1",
+ "offset": 0,
+ "size": 2,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "IER": {
+ "description": "interrupt enable register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SLKIE": {
+ "description": "SLKIE",
+ "offset": 17,
+ "size": 1
+ },
+ "WKUIE": {
+ "description": "WKUIE",
+ "offset": 16,
+ "size": 1
+ },
+ "ERRIE": {
+ "description": "ERRIE",
+ "offset": 15,
+ "size": 1
+ },
+ "LECIE": {
+ "description": "LECIE",
+ "offset": 11,
+ "size": 1
+ },
+ "BOFIE": {
+ "description": "BOFIE",
+ "offset": 10,
+ "size": 1
+ },
+ "EPVIE": {
+ "description": "EPVIE",
+ "offset": 9,
+ "size": 1
+ },
+ "EWGIE": {
+ "description": "EWGIE",
+ "offset": 8,
+ "size": 1
+ },
+ "FOVIE1": {
+ "description": "FOVIE1",
+ "offset": 6,
+ "size": 1
+ },
+ "FFIE1": {
+ "description": "FFIE1",
+ "offset": 5,
+ "size": 1
+ },
+ "FMPIE1": {
+ "description": "FMPIE1",
+ "offset": 4,
+ "size": 1
+ },
+ "FOVIE0": {
+ "description": "FOVIE0",
+ "offset": 3,
+ "size": 1
+ },
+ "FFIE0": {
+ "description": "FFIE0",
+ "offset": 2,
+ "size": 1
+ },
+ "FMPIE0": {
+ "description": "FMPIE0",
+ "offset": 1,
+ "size": 1
+ },
+ "TMEIE": {
+ "description": "TMEIE",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ESR": {
+ "description": "error status register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "REC": {
+ "description": "REC",
+ "offset": 24,
+ "size": 8,
+ "access": "read-only"
+ },
+ "TEC": {
+ "description": "TEC",
+ "offset": 16,
+ "size": 8,
+ "access": "read-only"
+ },
+ "LEC": {
+ "description": "LEC",
+ "offset": 4,
+ "size": 3
+ },
+ "BOFF": {
+ "description": "BOFF",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPVF": {
+ "description": "EPVF",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EWGF": {
+ "description": "EWGF",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "BTR": {
+ "description": "bit timing register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 19070976,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SILM": {
+ "description": "SILM",
+ "offset": 31,
+ "size": 1
+ },
+ "LBKM": {
+ "description": "LBKM",
+ "offset": 30,
+ "size": 1
+ },
+ "SJW": {
+ "description": "SJW",
+ "offset": 24,
+ "size": 2
+ },
+ "TS2": {
+ "description": "TS2",
+ "offset": 20,
+ "size": 3
+ },
+ "TS1": {
+ "description": "TS1",
+ "offset": 16,
+ "size": 4
+ },
+ "BRP": {
+ "description": "BRP",
+ "offset": 0,
+ "size": 10
+ }
+ }
+ }
+ },
+ "TI0R": {
+ "description": "TX mailbox identifier register",
+ "offset": 384,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "STID": {
+ "description": "STID",
+ "offset": 21,
+ "size": 11
+ },
+ "EXID": {
+ "description": "EXID",
+ "offset": 3,
+ "size": 18
+ },
+ "IDE": {
+ "description": "IDE",
+ "offset": 2,
+ "size": 1
+ },
+ "RTR": {
+ "description": "RTR",
+ "offset": 1,
+ "size": 1
+ },
+ "TXRQ": {
+ "description": "TXRQ",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "TDT0R": {
+ "description": "mailbox data length control and time stamp\n register",
+ "offset": 388,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIME": {
+ "description": "TIME",
+ "offset": 16,
+ "size": 16
+ },
+ "TGT": {
+ "description": "TGT",
+ "offset": 8,
+ "size": 1
+ },
+ "DLC": {
+ "description": "DLC",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "TDL0R": {
+ "description": "mailbox data low register",
+ "offset": 392,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATA3": {
+ "description": "DATA3",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA2": {
+ "description": "DATA2",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA1": {
+ "description": "DATA1",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA0": {
+ "description": "DATA0",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "TDH0R": {
+ "description": "mailbox data high register",
+ "offset": 396,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATA7": {
+ "description": "DATA7",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA6": {
+ "description": "DATA6",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA5": {
+ "description": "DATA5",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA4": {
+ "description": "DATA4",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "TI1R": {
+ "description": "TX mailbox identifier register",
+ "offset": 400,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "STID": {
+ "description": "STID",
+ "offset": 21,
+ "size": 11
+ },
+ "EXID": {
+ "description": "EXID",
+ "offset": 3,
+ "size": 18
+ },
+ "IDE": {
+ "description": "IDE",
+ "offset": 2,
+ "size": 1
+ },
+ "RTR": {
+ "description": "RTR",
+ "offset": 1,
+ "size": 1
+ },
+ "TXRQ": {
+ "description": "TXRQ",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "TDT1R": {
+ "description": "mailbox data length control and time stamp\n register",
+ "offset": 404,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIME": {
+ "description": "TIME",
+ "offset": 16,
+ "size": 16
+ },
+ "TGT": {
+ "description": "TGT",
+ "offset": 8,
+ "size": 1
+ },
+ "DLC": {
+ "description": "DLC",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "TDL1R": {
+ "description": "mailbox data low register",
+ "offset": 408,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATA3": {
+ "description": "DATA3",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA2": {
+ "description": "DATA2",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA1": {
+ "description": "DATA1",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA0": {
+ "description": "DATA0",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "TDH1R": {
+ "description": "mailbox data high register",
+ "offset": 412,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATA7": {
+ "description": "DATA7",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA6": {
+ "description": "DATA6",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA5": {
+ "description": "DATA5",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA4": {
+ "description": "DATA4",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "TI2R": {
+ "description": "TX mailbox identifier register",
+ "offset": 416,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "STID": {
+ "description": "STID",
+ "offset": 21,
+ "size": 11
+ },
+ "EXID": {
+ "description": "EXID",
+ "offset": 3,
+ "size": 18
+ },
+ "IDE": {
+ "description": "IDE",
+ "offset": 2,
+ "size": 1
+ },
+ "RTR": {
+ "description": "RTR",
+ "offset": 1,
+ "size": 1
+ },
+ "TXRQ": {
+ "description": "TXRQ",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "TDT2R": {
+ "description": "mailbox data length control and time stamp\n register",
+ "offset": 420,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIME": {
+ "description": "TIME",
+ "offset": 16,
+ "size": 16
+ },
+ "TGT": {
+ "description": "TGT",
+ "offset": 8,
+ "size": 1
+ },
+ "DLC": {
+ "description": "DLC",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "TDL2R": {
+ "description": "mailbox data low register",
+ "offset": 424,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATA3": {
+ "description": "DATA3",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA2": {
+ "description": "DATA2",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA1": {
+ "description": "DATA1",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA0": {
+ "description": "DATA0",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "TDH2R": {
+ "description": "mailbox data high register",
+ "offset": 428,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATA7": {
+ "description": "DATA7",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA6": {
+ "description": "DATA6",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA5": {
+ "description": "DATA5",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA4": {
+ "description": "DATA4",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "RI0R": {
+ "description": "receive FIFO mailbox identifier\n register",
+ "offset": 432,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "STID": {
+ "description": "STID",
+ "offset": 21,
+ "size": 11
+ },
+ "EXID": {
+ "description": "EXID",
+ "offset": 3,
+ "size": 18
+ },
+ "IDE": {
+ "description": "IDE",
+ "offset": 2,
+ "size": 1
+ },
+ "RTR": {
+ "description": "RTR",
+ "offset": 1,
+ "size": 1
+ }
+ }
+ }
+ },
+ "RDT0R": {
+ "description": "receive FIFO mailbox data length control and\n time stamp register",
+ "offset": 436,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "TIME": {
+ "description": "TIME",
+ "offset": 16,
+ "size": 16
+ },
+ "FMI": {
+ "description": "FMI",
+ "offset": 8,
+ "size": 8
+ },
+ "DLC": {
+ "description": "DLC",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "RDL0R": {
+ "description": "receive FIFO mailbox data low\n register",
+ "offset": 440,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DATA3": {
+ "description": "DATA3",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA2": {
+ "description": "DATA2",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA1": {
+ "description": "DATA1",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA0": {
+ "description": "DATA0",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "RDH0R": {
+ "description": "receive FIFO mailbox data high\n register",
+ "offset": 444,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DATA7": {
+ "description": "DATA7",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA6": {
+ "description": "DATA6",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA5": {
+ "description": "DATA5",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA4": {
+ "description": "DATA4",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "RI1R": {
+ "description": "receive FIFO mailbox identifier\n register",
+ "offset": 448,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "STID": {
+ "description": "STID",
+ "offset": 21,
+ "size": 11
+ },
+ "EXID": {
+ "description": "EXID",
+ "offset": 3,
+ "size": 18
+ },
+ "IDE": {
+ "description": "IDE",
+ "offset": 2,
+ "size": 1
+ },
+ "RTR": {
+ "description": "RTR",
+ "offset": 1,
+ "size": 1
+ }
+ }
+ }
+ },
+ "RDT1R": {
+ "description": "receive FIFO mailbox data length control and\n time stamp register",
+ "offset": 452,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "TIME": {
+ "description": "TIME",
+ "offset": 16,
+ "size": 16
+ },
+ "FMI": {
+ "description": "FMI",
+ "offset": 8,
+ "size": 8
+ },
+ "DLC": {
+ "description": "DLC",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "RDL1R": {
+ "description": "receive FIFO mailbox data low\n register",
+ "offset": 456,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DATA3": {
+ "description": "DATA3",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA2": {
+ "description": "DATA2",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA1": {
+ "description": "DATA1",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA0": {
+ "description": "DATA0",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "RDH1R": {
+ "description": "receive FIFO mailbox data high\n register",
+ "offset": 460,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DATA7": {
+ "description": "DATA7",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA6": {
+ "description": "DATA6",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA5": {
+ "description": "DATA5",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA4": {
+ "description": "DATA4",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "FMR": {
+ "description": "filter master register",
+ "offset": 512,
+ "size": 32,
+ "reset_value": 706481665,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CAN2SB": {
+ "description": "CAN2 start bank",
+ "offset": 8,
+ "size": 6
+ },
+ "FINIT": {
+ "description": "Filter init mode",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FM1R": {
+ "description": "filter mode register",
+ "offset": 516,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FBM0": {
+ "description": "Filter mode",
+ "offset": 0,
+ "size": 1
+ },
+ "FBM1": {
+ "description": "Filter mode",
+ "offset": 1,
+ "size": 1
+ },
+ "FBM2": {
+ "description": "Filter mode",
+ "offset": 2,
+ "size": 1
+ },
+ "FBM3": {
+ "description": "Filter mode",
+ "offset": 3,
+ "size": 1
+ },
+ "FBM4": {
+ "description": "Filter mode",
+ "offset": 4,
+ "size": 1
+ },
+ "FBM5": {
+ "description": "Filter mode",
+ "offset": 5,
+ "size": 1
+ },
+ "FBM6": {
+ "description": "Filter mode",
+ "offset": 6,
+ "size": 1
+ },
+ "FBM7": {
+ "description": "Filter mode",
+ "offset": 7,
+ "size": 1
+ },
+ "FBM8": {
+ "description": "Filter mode",
+ "offset": 8,
+ "size": 1
+ },
+ "FBM9": {
+ "description": "Filter mode",
+ "offset": 9,
+ "size": 1
+ },
+ "FBM10": {
+ "description": "Filter mode",
+ "offset": 10,
+ "size": 1
+ },
+ "FBM11": {
+ "description": "Filter mode",
+ "offset": 11,
+ "size": 1
+ },
+ "FBM12": {
+ "description": "Filter mode",
+ "offset": 12,
+ "size": 1
+ },
+ "FBM13": {
+ "description": "Filter mode",
+ "offset": 13,
+ "size": 1
+ },
+ "FBM14": {
+ "description": "Filter mode",
+ "offset": 14,
+ "size": 1
+ },
+ "FBM15": {
+ "description": "Filter mode",
+ "offset": 15,
+ "size": 1
+ },
+ "FBM16": {
+ "description": "Filter mode",
+ "offset": 16,
+ "size": 1
+ },
+ "FBM17": {
+ "description": "Filter mode",
+ "offset": 17,
+ "size": 1
+ },
+ "FBM18": {
+ "description": "Filter mode",
+ "offset": 18,
+ "size": 1
+ },
+ "FBM19": {
+ "description": "Filter mode",
+ "offset": 19,
+ "size": 1
+ },
+ "FBM20": {
+ "description": "Filter mode",
+ "offset": 20,
+ "size": 1
+ },
+ "FBM21": {
+ "description": "Filter mode",
+ "offset": 21,
+ "size": 1
+ },
+ "FBM22": {
+ "description": "Filter mode",
+ "offset": 22,
+ "size": 1
+ },
+ "FBM23": {
+ "description": "Filter mode",
+ "offset": 23,
+ "size": 1
+ },
+ "FBM24": {
+ "description": "Filter mode",
+ "offset": 24,
+ "size": 1
+ },
+ "FBM25": {
+ "description": "Filter mode",
+ "offset": 25,
+ "size": 1
+ },
+ "FBM26": {
+ "description": "Filter mode",
+ "offset": 26,
+ "size": 1
+ },
+ "FBM27": {
+ "description": "Filter mode",
+ "offset": 27,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS1R": {
+ "description": "filter scale register",
+ "offset": 524,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FSC0": {
+ "description": "Filter scale configuration",
+ "offset": 0,
+ "size": 1
+ },
+ "FSC1": {
+ "description": "Filter scale configuration",
+ "offset": 1,
+ "size": 1
+ },
+ "FSC2": {
+ "description": "Filter scale configuration",
+ "offset": 2,
+ "size": 1
+ },
+ "FSC3": {
+ "description": "Filter scale configuration",
+ "offset": 3,
+ "size": 1
+ },
+ "FSC4": {
+ "description": "Filter scale configuration",
+ "offset": 4,
+ "size": 1
+ },
+ "FSC5": {
+ "description": "Filter scale configuration",
+ "offset": 5,
+ "size": 1
+ },
+ "FSC6": {
+ "description": "Filter scale configuration",
+ "offset": 6,
+ "size": 1
+ },
+ "FSC7": {
+ "description": "Filter scale configuration",
+ "offset": 7,
+ "size": 1
+ },
+ "FSC8": {
+ "description": "Filter scale configuration",
+ "offset": 8,
+ "size": 1
+ },
+ "FSC9": {
+ "description": "Filter scale configuration",
+ "offset": 9,
+ "size": 1
+ },
+ "FSC10": {
+ "description": "Filter scale configuration",
+ "offset": 10,
+ "size": 1
+ },
+ "FSC11": {
+ "description": "Filter scale configuration",
+ "offset": 11,
+ "size": 1
+ },
+ "FSC12": {
+ "description": "Filter scale configuration",
+ "offset": 12,
+ "size": 1
+ },
+ "FSC13": {
+ "description": "Filter scale configuration",
+ "offset": 13,
+ "size": 1
+ },
+ "FSC14": {
+ "description": "Filter scale configuration",
+ "offset": 14,
+ "size": 1
+ },
+ "FSC15": {
+ "description": "Filter scale configuration",
+ "offset": 15,
+ "size": 1
+ },
+ "FSC16": {
+ "description": "Filter scale configuration",
+ "offset": 16,
+ "size": 1
+ },
+ "FSC17": {
+ "description": "Filter scale configuration",
+ "offset": 17,
+ "size": 1
+ },
+ "FSC18": {
+ "description": "Filter scale configuration",
+ "offset": 18,
+ "size": 1
+ },
+ "FSC19": {
+ "description": "Filter scale configuration",
+ "offset": 19,
+ "size": 1
+ },
+ "FSC20": {
+ "description": "Filter scale configuration",
+ "offset": 20,
+ "size": 1
+ },
+ "FSC21": {
+ "description": "Filter scale configuration",
+ "offset": 21,
+ "size": 1
+ },
+ "FSC22": {
+ "description": "Filter scale configuration",
+ "offset": 22,
+ "size": 1
+ },
+ "FSC23": {
+ "description": "Filter scale configuration",
+ "offset": 23,
+ "size": 1
+ },
+ "FSC24": {
+ "description": "Filter scale configuration",
+ "offset": 24,
+ "size": 1
+ },
+ "FSC25": {
+ "description": "Filter scale configuration",
+ "offset": 25,
+ "size": 1
+ },
+ "FSC26": {
+ "description": "Filter scale configuration",
+ "offset": 26,
+ "size": 1
+ },
+ "FSC27": {
+ "description": "Filter scale configuration",
+ "offset": 27,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FFA1R": {
+ "description": "filter FIFO assignment\n register",
+ "offset": 532,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FFA0": {
+ "description": "Filter FIFO assignment for filter\n 0",
+ "offset": 0,
+ "size": 1
+ },
+ "FFA1": {
+ "description": "Filter FIFO assignment for filter\n 1",
+ "offset": 1,
+ "size": 1
+ },
+ "FFA2": {
+ "description": "Filter FIFO assignment for filter\n 2",
+ "offset": 2,
+ "size": 1
+ },
+ "FFA3": {
+ "description": "Filter FIFO assignment for filter\n 3",
+ "offset": 3,
+ "size": 1
+ },
+ "FFA4": {
+ "description": "Filter FIFO assignment for filter\n 4",
+ "offset": 4,
+ "size": 1
+ },
+ "FFA5": {
+ "description": "Filter FIFO assignment for filter\n 5",
+ "offset": 5,
+ "size": 1
+ },
+ "FFA6": {
+ "description": "Filter FIFO assignment for filter\n 6",
+ "offset": 6,
+ "size": 1
+ },
+ "FFA7": {
+ "description": "Filter FIFO assignment for filter\n 7",
+ "offset": 7,
+ "size": 1
+ },
+ "FFA8": {
+ "description": "Filter FIFO assignment for filter\n 8",
+ "offset": 8,
+ "size": 1
+ },
+ "FFA9": {
+ "description": "Filter FIFO assignment for filter\n 9",
+ "offset": 9,
+ "size": 1
+ },
+ "FFA10": {
+ "description": "Filter FIFO assignment for filter\n 10",
+ "offset": 10,
+ "size": 1
+ },
+ "FFA11": {
+ "description": "Filter FIFO assignment for filter\n 11",
+ "offset": 11,
+ "size": 1
+ },
+ "FFA12": {
+ "description": "Filter FIFO assignment for filter\n 12",
+ "offset": 12,
+ "size": 1
+ },
+ "FFA13": {
+ "description": "Filter FIFO assignment for filter\n 13",
+ "offset": 13,
+ "size": 1
+ },
+ "FFA14": {
+ "description": "Filter FIFO assignment for filter\n 14",
+ "offset": 14,
+ "size": 1
+ },
+ "FFA15": {
+ "description": "Filter FIFO assignment for filter\n 15",
+ "offset": 15,
+ "size": 1
+ },
+ "FFA16": {
+ "description": "Filter FIFO assignment for filter\n 16",
+ "offset": 16,
+ "size": 1
+ },
+ "FFA17": {
+ "description": "Filter FIFO assignment for filter\n 17",
+ "offset": 17,
+ "size": 1
+ },
+ "FFA18": {
+ "description": "Filter FIFO assignment for filter\n 18",
+ "offset": 18,
+ "size": 1
+ },
+ "FFA19": {
+ "description": "Filter FIFO assignment for filter\n 19",
+ "offset": 19,
+ "size": 1
+ },
+ "FFA20": {
+ "description": "Filter FIFO assignment for filter\n 20",
+ "offset": 20,
+ "size": 1
+ },
+ "FFA21": {
+ "description": "Filter FIFO assignment for filter\n 21",
+ "offset": 21,
+ "size": 1
+ },
+ "FFA22": {
+ "description": "Filter FIFO assignment for filter\n 22",
+ "offset": 22,
+ "size": 1
+ },
+ "FFA23": {
+ "description": "Filter FIFO assignment for filter\n 23",
+ "offset": 23,
+ "size": 1
+ },
+ "FFA24": {
+ "description": "Filter FIFO assignment for filter\n 24",
+ "offset": 24,
+ "size": 1
+ },
+ "FFA25": {
+ "description": "Filter FIFO assignment for filter\n 25",
+ "offset": 25,
+ "size": 1
+ },
+ "FFA26": {
+ "description": "Filter FIFO assignment for filter\n 26",
+ "offset": 26,
+ "size": 1
+ },
+ "FFA27": {
+ "description": "Filter FIFO assignment for filter\n 27",
+ "offset": 27,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FA1R": {
+ "description": "CAN filter activation register",
+ "offset": 540,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FACT0": {
+ "description": "Filter active",
+ "offset": 0,
+ "size": 1
+ },
+ "FACT1": {
+ "description": "Filter active",
+ "offset": 1,
+ "size": 1
+ },
+ "FACT2": {
+ "description": "Filter active",
+ "offset": 2,
+ "size": 1
+ },
+ "FACT3": {
+ "description": "Filter active",
+ "offset": 3,
+ "size": 1
+ },
+ "FACT4": {
+ "description": "Filter active",
+ "offset": 4,
+ "size": 1
+ },
+ "FACT5": {
+ "description": "Filter active",
+ "offset": 5,
+ "size": 1
+ },
+ "FACT6": {
+ "description": "Filter active",
+ "offset": 6,
+ "size": 1
+ },
+ "FACT7": {
+ "description": "Filter active",
+ "offset": 7,
+ "size": 1
+ },
+ "FACT8": {
+ "description": "Filter active",
+ "offset": 8,
+ "size": 1
+ },
+ "FACT9": {
+ "description": "Filter active",
+ "offset": 9,
+ "size": 1
+ },
+ "FACT10": {
+ "description": "Filter active",
+ "offset": 10,
+ "size": 1
+ },
+ "FACT11": {
+ "description": "Filter active",
+ "offset": 11,
+ "size": 1
+ },
+ "FACT12": {
+ "description": "Filter active",
+ "offset": 12,
+ "size": 1
+ },
+ "FACT13": {
+ "description": "Filter active",
+ "offset": 13,
+ "size": 1
+ },
+ "FACT14": {
+ "description": "Filter active",
+ "offset": 14,
+ "size": 1
+ },
+ "FACT15": {
+ "description": "Filter active",
+ "offset": 15,
+ "size": 1
+ },
+ "FACT16": {
+ "description": "Filter active",
+ "offset": 16,
+ "size": 1
+ },
+ "FACT17": {
+ "description": "Filter active",
+ "offset": 17,
+ "size": 1
+ },
+ "FACT18": {
+ "description": "Filter active",
+ "offset": 18,
+ "size": 1
+ },
+ "FACT19": {
+ "description": "Filter active",
+ "offset": 19,
+ "size": 1
+ },
+ "FACT20": {
+ "description": "Filter active",
+ "offset": 20,
+ "size": 1
+ },
+ "FACT21": {
+ "description": "Filter active",
+ "offset": 21,
+ "size": 1
+ },
+ "FACT22": {
+ "description": "Filter active",
+ "offset": 22,
+ "size": 1
+ },
+ "FACT23": {
+ "description": "Filter active",
+ "offset": 23,
+ "size": 1
+ },
+ "FACT24": {
+ "description": "Filter active",
+ "offset": 24,
+ "size": 1
+ },
+ "FACT25": {
+ "description": "Filter active",
+ "offset": 25,
+ "size": 1
+ },
+ "FACT26": {
+ "description": "Filter active",
+ "offset": 26,
+ "size": 1
+ },
+ "FACT27": {
+ "description": "Filter active",
+ "offset": 27,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F0R1": {
+ "description": "Filter bank 0 register 1",
+ "offset": 576,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F0R2": {
+ "description": "Filter bank 0 register 2",
+ "offset": 580,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F1R1": {
+ "description": "Filter bank 1 register 1",
+ "offset": 584,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F1R2": {
+ "description": "Filter bank 1 register 2",
+ "offset": 588,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F2R1": {
+ "description": "Filter bank 2 register 1",
+ "offset": 592,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F2R2": {
+ "description": "Filter bank 2 register 2",
+ "offset": 596,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F3R1": {
+ "description": "Filter bank 3 register 1",
+ "offset": 600,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F3R2": {
+ "description": "Filter bank 3 register 2",
+ "offset": 604,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F4R1": {
+ "description": "Filter bank 4 register 1",
+ "offset": 608,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F4R2": {
+ "description": "Filter bank 4 register 2",
+ "offset": 612,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F5R1": {
+ "description": "Filter bank 5 register 1",
+ "offset": 616,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F5R2": {
+ "description": "Filter bank 5 register 2",
+ "offset": 620,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F6R1": {
+ "description": "Filter bank 6 register 1",
+ "offset": 624,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F6R2": {
+ "description": "Filter bank 6 register 2",
+ "offset": 628,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F7R1": {
+ "description": "Filter bank 7 register 1",
+ "offset": 632,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F7R2": {
+ "description": "Filter bank 7 register 2",
+ "offset": 636,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F8R1": {
+ "description": "Filter bank 8 register 1",
+ "offset": 640,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F8R2": {
+ "description": "Filter bank 8 register 2",
+ "offset": 644,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F9R1": {
+ "description": "Filter bank 9 register 1",
+ "offset": 648,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F9R2": {
+ "description": "Filter bank 9 register 2",
+ "offset": 652,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F10R1": {
+ "description": "Filter bank 10 register 1",
+ "offset": 656,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F10R2": {
+ "description": "Filter bank 10 register 2",
+ "offset": 660,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F11R1": {
+ "description": "Filter bank 11 register 1",
+ "offset": 664,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F11R2": {
+ "description": "Filter bank 11 register 2",
+ "offset": 668,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F12R1": {
+ "description": "Filter bank 4 register 1",
+ "offset": 672,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F12R2": {
+ "description": "Filter bank 12 register 2",
+ "offset": 676,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F13R1": {
+ "description": "Filter bank 13 register 1",
+ "offset": 680,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F13R2": {
+ "description": "Filter bank 13 register 2",
+ "offset": 684,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F14R1": {
+ "description": "Filter bank 14 register 1",
+ "offset": 688,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F14R2": {
+ "description": "Filter bank 14 register 2",
+ "offset": 692,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F15R1": {
+ "description": "Filter bank 15 register 1",
+ "offset": 696,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F15R2": {
+ "description": "Filter bank 15 register 2",
+ "offset": 700,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F16R1": {
+ "description": "Filter bank 16 register 1",
+ "offset": 704,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F16R2": {
+ "description": "Filter bank 16 register 2",
+ "offset": 708,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F17R1": {
+ "description": "Filter bank 17 register 1",
+ "offset": 712,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F17R2": {
+ "description": "Filter bank 17 register 2",
+ "offset": 716,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F18R1": {
+ "description": "Filter bank 18 register 1",
+ "offset": 720,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F18R2": {
+ "description": "Filter bank 18 register 2",
+ "offset": 724,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F19R1": {
+ "description": "Filter bank 19 register 1",
+ "offset": 728,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F19R2": {
+ "description": "Filter bank 19 register 2",
+ "offset": 732,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F20R1": {
+ "description": "Filter bank 20 register 1",
+ "offset": 736,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F20R2": {
+ "description": "Filter bank 20 register 2",
+ "offset": 740,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F21R1": {
+ "description": "Filter bank 21 register 1",
+ "offset": 744,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F21R2": {
+ "description": "Filter bank 21 register 2",
+ "offset": 748,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F22R1": {
+ "description": "Filter bank 22 register 1",
+ "offset": 752,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F22R2": {
+ "description": "Filter bank 22 register 2",
+ "offset": 756,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F23R1": {
+ "description": "Filter bank 23 register 1",
+ "offset": 760,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F23R2": {
+ "description": "Filter bank 23 register 2",
+ "offset": 764,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F24R1": {
+ "description": "Filter bank 24 register 1",
+ "offset": 768,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F24R2": {
+ "description": "Filter bank 24 register 2",
+ "offset": 772,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F25R1": {
+ "description": "Filter bank 25 register 1",
+ "offset": 776,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F25R2": {
+ "description": "Filter bank 25 register 2",
+ "offset": 780,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F26R1": {
+ "description": "Filter bank 26 register 1",
+ "offset": 784,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F26R2": {
+ "description": "Filter bank 26 register 2",
+ "offset": 788,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F27R1": {
+ "description": "Filter bank 27 register 1",
+ "offset": 792,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F27R2": {
+ "description": "Filter bank 27 register 2",
+ "offset": 796,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "USB_FS": {
+ "description": "Universal serial bus full-speed device\n interface",
+ "children": {
+ "registers": {
+ "USB_EP0R": {
+ "description": "endpoint 0 register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EA": {
+ "description": "Endpoint address",
+ "offset": 0,
+ "size": 4
+ },
+ "STAT_TX": {
+ "description": "Status bits, for transmission\n transfers",
+ "offset": 4,
+ "size": 2
+ },
+ "DTOG_TX": {
+ "description": "Data Toggle, for transmission\n transfers",
+ "offset": 6,
+ "size": 1
+ },
+ "CTR_TX": {
+ "description": "Correct Transfer for\n transmission",
+ "offset": 7,
+ "size": 1
+ },
+ "EP_KIND": {
+ "description": "Endpoint kind",
+ "offset": 8,
+ "size": 1
+ },
+ "EP_TYPE": {
+ "description": "Endpoint type",
+ "offset": 9,
+ "size": 2
+ },
+ "SETUP": {
+ "description": "Setup transaction\n completed",
+ "offset": 11,
+ "size": 1,
+ "access": "read-only"
+ },
+ "STAT_RX": {
+ "description": "Status bits, for reception\n transfers",
+ "offset": 12,
+ "size": 2
+ },
+ "DTOG_RX": {
+ "description": "Data Toggle, for reception\n transfers",
+ "offset": 14,
+ "size": 1
+ },
+ "CTR_RX": {
+ "description": "Correct transfer for\n reception",
+ "offset": 15,
+ "size": 1
+ }
+ }
+ }
+ },
+ "USB_EP1R": {
+ "description": "endpoint 1 register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EA": {
+ "description": "Endpoint address",
+ "offset": 0,
+ "size": 4
+ },
+ "STAT_TX": {
+ "description": "Status bits, for transmission\n transfers",
+ "offset": 4,
+ "size": 2
+ },
+ "DTOG_TX": {
+ "description": "Data Toggle, for transmission\n transfers",
+ "offset": 6,
+ "size": 1
+ },
+ "CTR_TX": {
+ "description": "Correct Transfer for\n transmission",
+ "offset": 7,
+ "size": 1
+ },
+ "EP_KIND": {
+ "description": "Endpoint kind",
+ "offset": 8,
+ "size": 1
+ },
+ "EP_TYPE": {
+ "description": "Endpoint type",
+ "offset": 9,
+ "size": 2
+ },
+ "SETUP": {
+ "description": "Setup transaction\n completed",
+ "offset": 11,
+ "size": 1,
+ "access": "read-only"
+ },
+ "STAT_RX": {
+ "description": "Status bits, for reception\n transfers",
+ "offset": 12,
+ "size": 2
+ },
+ "DTOG_RX": {
+ "description": "Data Toggle, for reception\n transfers",
+ "offset": 14,
+ "size": 1
+ },
+ "CTR_RX": {
+ "description": "Correct transfer for\n reception",
+ "offset": 15,
+ "size": 1
+ }
+ }
+ }
+ },
+ "USB_EP2R": {
+ "description": "endpoint 2 register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EA": {
+ "description": "Endpoint address",
+ "offset": 0,
+ "size": 4
+ },
+ "STAT_TX": {
+ "description": "Status bits, for transmission\n transfers",
+ "offset": 4,
+ "size": 2
+ },
+ "DTOG_TX": {
+ "description": "Data Toggle, for transmission\n transfers",
+ "offset": 6,
+ "size": 1
+ },
+ "CTR_TX": {
+ "description": "Correct Transfer for\n transmission",
+ "offset": 7,
+ "size": 1
+ },
+ "EP_KIND": {
+ "description": "Endpoint kind",
+ "offset": 8,
+ "size": 1
+ },
+ "EP_TYPE": {
+ "description": "Endpoint type",
+ "offset": 9,
+ "size": 2
+ },
+ "SETUP": {
+ "description": "Setup transaction\n completed",
+ "offset": 11,
+ "size": 1,
+ "access": "read-only"
+ },
+ "STAT_RX": {
+ "description": "Status bits, for reception\n transfers",
+ "offset": 12,
+ "size": 2
+ },
+ "DTOG_RX": {
+ "description": "Data Toggle, for reception\n transfers",
+ "offset": 14,
+ "size": 1
+ },
+ "CTR_RX": {
+ "description": "Correct transfer for\n reception",
+ "offset": 15,
+ "size": 1
+ }
+ }
+ }
+ },
+ "USB_EP3R": {
+ "description": "endpoint 3 register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EA": {
+ "description": "Endpoint address",
+ "offset": 0,
+ "size": 4
+ },
+ "STAT_TX": {
+ "description": "Status bits, for transmission\n transfers",
+ "offset": 4,
+ "size": 2
+ },
+ "DTOG_TX": {
+ "description": "Data Toggle, for transmission\n transfers",
+ "offset": 6,
+ "size": 1
+ },
+ "CTR_TX": {
+ "description": "Correct Transfer for\n transmission",
+ "offset": 7,
+ "size": 1
+ },
+ "EP_KIND": {
+ "description": "Endpoint kind",
+ "offset": 8,
+ "size": 1
+ },
+ "EP_TYPE": {
+ "description": "Endpoint type",
+ "offset": 9,
+ "size": 2
+ },
+ "SETUP": {
+ "description": "Setup transaction\n completed",
+ "offset": 11,
+ "size": 1,
+ "access": "read-only"
+ },
+ "STAT_RX": {
+ "description": "Status bits, for reception\n transfers",
+ "offset": 12,
+ "size": 2
+ },
+ "DTOG_RX": {
+ "description": "Data Toggle, for reception\n transfers",
+ "offset": 14,
+ "size": 1
+ },
+ "CTR_RX": {
+ "description": "Correct transfer for\n reception",
+ "offset": 15,
+ "size": 1
+ }
+ }
+ }
+ },
+ "USB_EP4R": {
+ "description": "endpoint 4 register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EA": {
+ "description": "Endpoint address",
+ "offset": 0,
+ "size": 4
+ },
+ "STAT_TX": {
+ "description": "Status bits, for transmission\n transfers",
+ "offset": 4,
+ "size": 2
+ },
+ "DTOG_TX": {
+ "description": "Data Toggle, for transmission\n transfers",
+ "offset": 6,
+ "size": 1
+ },
+ "CTR_TX": {
+ "description": "Correct Transfer for\n transmission",
+ "offset": 7,
+ "size": 1
+ },
+ "EP_KIND": {
+ "description": "Endpoint kind",
+ "offset": 8,
+ "size": 1
+ },
+ "EP_TYPE": {
+ "description": "Endpoint type",
+ "offset": 9,
+ "size": 2
+ },
+ "SETUP": {
+ "description": "Setup transaction\n completed",
+ "offset": 11,
+ "size": 1,
+ "access": "read-only"
+ },
+ "STAT_RX": {
+ "description": "Status bits, for reception\n transfers",
+ "offset": 12,
+ "size": 2
+ },
+ "DTOG_RX": {
+ "description": "Data Toggle, for reception\n transfers",
+ "offset": 14,
+ "size": 1
+ },
+ "CTR_RX": {
+ "description": "Correct transfer for\n reception",
+ "offset": 15,
+ "size": 1
+ }
+ }
+ }
+ },
+ "USB_EP5R": {
+ "description": "endpoint 5 register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EA": {
+ "description": "Endpoint address",
+ "offset": 0,
+ "size": 4
+ },
+ "STAT_TX": {
+ "description": "Status bits, for transmission\n transfers",
+ "offset": 4,
+ "size": 2
+ },
+ "DTOG_TX": {
+ "description": "Data Toggle, for transmission\n transfers",
+ "offset": 6,
+ "size": 1
+ },
+ "CTR_TX": {
+ "description": "Correct Transfer for\n transmission",
+ "offset": 7,
+ "size": 1
+ },
+ "EP_KIND": {
+ "description": "Endpoint kind",
+ "offset": 8,
+ "size": 1
+ },
+ "EP_TYPE": {
+ "description": "Endpoint type",
+ "offset": 9,
+ "size": 2
+ },
+ "SETUP": {
+ "description": "Setup transaction\n completed",
+ "offset": 11,
+ "size": 1,
+ "access": "read-only"
+ },
+ "STAT_RX": {
+ "description": "Status bits, for reception\n transfers",
+ "offset": 12,
+ "size": 2
+ },
+ "DTOG_RX": {
+ "description": "Data Toggle, for reception\n transfers",
+ "offset": 14,
+ "size": 1
+ },
+ "CTR_RX": {
+ "description": "Correct transfer for\n reception",
+ "offset": 15,
+ "size": 1
+ }
+ }
+ }
+ },
+ "USB_EP6R": {
+ "description": "endpoint 6 register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EA": {
+ "description": "Endpoint address",
+ "offset": 0,
+ "size": 4
+ },
+ "STAT_TX": {
+ "description": "Status bits, for transmission\n transfers",
+ "offset": 4,
+ "size": 2
+ },
+ "DTOG_TX": {
+ "description": "Data Toggle, for transmission\n transfers",
+ "offset": 6,
+ "size": 1
+ },
+ "CTR_TX": {
+ "description": "Correct Transfer for\n transmission",
+ "offset": 7,
+ "size": 1
+ },
+ "EP_KIND": {
+ "description": "Endpoint kind",
+ "offset": 8,
+ "size": 1
+ },
+ "EP_TYPE": {
+ "description": "Endpoint type",
+ "offset": 9,
+ "size": 2
+ },
+ "SETUP": {
+ "description": "Setup transaction\n completed",
+ "offset": 11,
+ "size": 1,
+ "access": "read-only"
+ },
+ "STAT_RX": {
+ "description": "Status bits, for reception\n transfers",
+ "offset": 12,
+ "size": 2
+ },
+ "DTOG_RX": {
+ "description": "Data Toggle, for reception\n transfers",
+ "offset": 14,
+ "size": 1
+ },
+ "CTR_RX": {
+ "description": "Correct transfer for\n reception",
+ "offset": 15,
+ "size": 1
+ }
+ }
+ }
+ },
+ "USB_EP7R": {
+ "description": "endpoint 7 register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EA": {
+ "description": "Endpoint address",
+ "offset": 0,
+ "size": 4
+ },
+ "STAT_TX": {
+ "description": "Status bits, for transmission\n transfers",
+ "offset": 4,
+ "size": 2
+ },
+ "DTOG_TX": {
+ "description": "Data Toggle, for transmission\n transfers",
+ "offset": 6,
+ "size": 1
+ },
+ "CTR_TX": {
+ "description": "Correct Transfer for\n transmission",
+ "offset": 7,
+ "size": 1
+ },
+ "EP_KIND": {
+ "description": "Endpoint kind",
+ "offset": 8,
+ "size": 1
+ },
+ "EP_TYPE": {
+ "description": "Endpoint type",
+ "offset": 9,
+ "size": 2
+ },
+ "SETUP": {
+ "description": "Setup transaction\n completed",
+ "offset": 11,
+ "size": 1,
+ "access": "read-only"
+ },
+ "STAT_RX": {
+ "description": "Status bits, for reception\n transfers",
+ "offset": 12,
+ "size": 2
+ },
+ "DTOG_RX": {
+ "description": "Data Toggle, for reception\n transfers",
+ "offset": 14,
+ "size": 1
+ },
+ "CTR_RX": {
+ "description": "Correct transfer for\n reception",
+ "offset": 15,
+ "size": 1
+ }
+ }
+ }
+ },
+ "USB_CNTR": {
+ "description": "control register",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 3,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FRES": {
+ "description": "Force USB Reset",
+ "offset": 0,
+ "size": 1
+ },
+ "PDWN": {
+ "description": "Power down",
+ "offset": 1,
+ "size": 1
+ },
+ "LPMODE": {
+ "description": "Low-power mode",
+ "offset": 2,
+ "size": 1
+ },
+ "FSUSP": {
+ "description": "Force suspend",
+ "offset": 3,
+ "size": 1
+ },
+ "RESUME": {
+ "description": "Resume request",
+ "offset": 4,
+ "size": 1
+ },
+ "ESOFM": {
+ "description": "Expected start of frame interrupt\n mask",
+ "offset": 8,
+ "size": 1
+ },
+ "SOFM": {
+ "description": "Start of frame interrupt\n mask",
+ "offset": 9,
+ "size": 1
+ },
+ "RESETM": {
+ "description": "USB reset interrupt mask",
+ "offset": 10,
+ "size": 1
+ },
+ "SUSPM": {
+ "description": "Suspend mode interrupt\n mask",
+ "offset": 11,
+ "size": 1
+ },
+ "WKUPM": {
+ "description": "Wakeup interrupt mask",
+ "offset": 12,
+ "size": 1
+ },
+ "ERRM": {
+ "description": "Error interrupt mask",
+ "offset": 13,
+ "size": 1
+ },
+ "PMAOVRM": {
+ "description": "Packet memory area over / underrun\n interrupt mask",
+ "offset": 14,
+ "size": 1
+ },
+ "CTRM": {
+ "description": "Correct transfer interrupt\n mask",
+ "offset": 15,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ISTR": {
+ "description": "interrupt status register",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EP_ID": {
+ "description": "Endpoint Identifier",
+ "offset": 0,
+ "size": 4,
+ "access": "read-only"
+ },
+ "DIR": {
+ "description": "Direction of transaction",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ESOF": {
+ "description": "Expected start frame",
+ "offset": 8,
+ "size": 1
+ },
+ "SOF": {
+ "description": "start of frame",
+ "offset": 9,
+ "size": 1
+ },
+ "RESET": {
+ "description": "reset request",
+ "offset": 10,
+ "size": 1
+ },
+ "SUSP": {
+ "description": "Suspend mode request",
+ "offset": 11,
+ "size": 1
+ },
+ "WKUP": {
+ "description": "Wakeup",
+ "offset": 12,
+ "size": 1
+ },
+ "ERR": {
+ "description": "Error",
+ "offset": 13,
+ "size": 1
+ },
+ "PMAOVR": {
+ "description": "Packet memory area over /\n underrun",
+ "offset": 14,
+ "size": 1
+ },
+ "CTR": {
+ "description": "Correct transfer",
+ "offset": 15,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "FNR": {
+ "description": "frame number register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "FN": {
+ "description": "Frame number",
+ "offset": 0,
+ "size": 11
+ },
+ "LSOF": {
+ "description": "Lost SOF",
+ "offset": 11,
+ "size": 2
+ },
+ "LCK": {
+ "description": "Locked",
+ "offset": 13,
+ "size": 1
+ },
+ "RXDM": {
+ "description": "Receive data - line status",
+ "offset": 14,
+ "size": 1
+ },
+ "RXDP": {
+ "description": "Receive data + line status",
+ "offset": 15,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DADDR": {
+ "description": "device address",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ADD": {
+ "description": "Device address",
+ "offset": 0,
+ "size": 1
+ },
+ "ADD1": {
+ "description": "Device address",
+ "offset": 1,
+ "size": 1
+ },
+ "ADD2": {
+ "description": "Device address",
+ "offset": 2,
+ "size": 1
+ },
+ "ADD3": {
+ "description": "Device address",
+ "offset": 3,
+ "size": 1
+ },
+ "ADD4": {
+ "description": "Device address",
+ "offset": 4,
+ "size": 1
+ },
+ "ADD5": {
+ "description": "Device address",
+ "offset": 5,
+ "size": 1
+ },
+ "ADD6": {
+ "description": "Device address",
+ "offset": 6,
+ "size": 1
+ },
+ "EF": {
+ "description": "Enable function",
+ "offset": 7,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BTABLE": {
+ "description": "Buffer table address",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BTABLE": {
+ "description": "Buffer table",
+ "offset": 3,
+ "size": 13
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "I2C1": {
+ "description": "Inter-integrated circuit",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "Control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PE": {
+ "description": "Peripheral enable",
+ "offset": 0,
+ "size": 1
+ },
+ "TXIE": {
+ "description": "TX Interrupt enable",
+ "offset": 1,
+ "size": 1
+ },
+ "RXIE": {
+ "description": "RX Interrupt enable",
+ "offset": 2,
+ "size": 1
+ },
+ "ADDRIE": {
+ "description": "Address match interrupt enable (slave\n only)",
+ "offset": 3,
+ "size": 1
+ },
+ "NACKIE": {
+ "description": "Not acknowledge received interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "STOPIE": {
+ "description": "STOP detection Interrupt\n enable",
+ "offset": 5,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer Complete interrupt\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "ERRIE": {
+ "description": "Error interrupts enable",
+ "offset": 7,
+ "size": 1
+ },
+ "DNF": {
+ "description": "Digital noise filter",
+ "offset": 8,
+ "size": 4
+ },
+ "ANFOFF": {
+ "description": "Analog noise filter OFF",
+ "offset": 12,
+ "size": 1
+ },
+ "SWRST": {
+ "description": "Software reset",
+ "offset": 13,
+ "size": 1,
+ "access": "write-only"
+ },
+ "TXDMAEN": {
+ "description": "DMA transmission requests\n enable",
+ "offset": 14,
+ "size": 1
+ },
+ "RXDMAEN": {
+ "description": "DMA reception requests\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "SBC": {
+ "description": "Slave byte control",
+ "offset": 16,
+ "size": 1
+ },
+ "NOSTRETCH": {
+ "description": "Clock stretching disable",
+ "offset": 17,
+ "size": 1
+ },
+ "WUPEN": {
+ "description": "Wakeup from STOP enable",
+ "offset": 18,
+ "size": 1
+ },
+ "GCEN": {
+ "description": "General call enable",
+ "offset": 19,
+ "size": 1
+ },
+ "SMBHEN": {
+ "description": "SMBus Host address enable",
+ "offset": 20,
+ "size": 1
+ },
+ "SMBDEN": {
+ "description": "SMBus Device Default address\n enable",
+ "offset": 21,
+ "size": 1
+ },
+ "ALERTEN": {
+ "description": "SMBUS alert enable",
+ "offset": 22,
+ "size": 1
+ },
+ "PECEN": {
+ "description": "PEC enable",
+ "offset": 23,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "Control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PECBYTE": {
+ "description": "Packet error checking byte",
+ "offset": 26,
+ "size": 1
+ },
+ "AUTOEND": {
+ "description": "Automatic end mode (master\n mode)",
+ "offset": 25,
+ "size": 1
+ },
+ "RELOAD": {
+ "description": "NBYTES reload mode",
+ "offset": 24,
+ "size": 1
+ },
+ "NBYTES": {
+ "description": "Number of bytes",
+ "offset": 16,
+ "size": 8
+ },
+ "NACK": {
+ "description": "NACK generation (slave\n mode)",
+ "offset": 15,
+ "size": 1
+ },
+ "STOP": {
+ "description": "Stop generation (master\n mode)",
+ "offset": 14,
+ "size": 1
+ },
+ "START": {
+ "description": "Start generation",
+ "offset": 13,
+ "size": 1
+ },
+ "HEAD10R": {
+ "description": "10-bit address header only read\n direction (master receiver mode)",
+ "offset": 12,
+ "size": 1
+ },
+ "ADD10": {
+ "description": "10-bit addressing mode (master\n mode)",
+ "offset": 11,
+ "size": 1
+ },
+ "RD_WRN": {
+ "description": "Transfer direction (master\n mode)",
+ "offset": 10,
+ "size": 1
+ },
+ "SADD8": {
+ "description": "Slave address bit 9:8 (master\n mode)",
+ "offset": 8,
+ "size": 2
+ },
+ "SADD1": {
+ "description": "Slave address bit 7:1 (master\n mode)",
+ "offset": 1,
+ "size": 7
+ },
+ "SADD0": {
+ "description": "Slave address bit 0 (master\n mode)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OAR1": {
+ "description": "Own address register 1",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OA1_0": {
+ "description": "Interface address",
+ "offset": 0,
+ "size": 1
+ },
+ "OA1_1": {
+ "description": "Interface address",
+ "offset": 1,
+ "size": 7
+ },
+ "OA1_8": {
+ "description": "Interface address",
+ "offset": 8,
+ "size": 2
+ },
+ "OA1MODE": {
+ "description": "Own Address 1 10-bit mode",
+ "offset": 10,
+ "size": 1
+ },
+ "OA1EN": {
+ "description": "Own Address 1 enable",
+ "offset": 15,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OAR2": {
+ "description": "Own address register 2",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OA2": {
+ "description": "Interface address",
+ "offset": 1,
+ "size": 7
+ },
+ "OA2MSK": {
+ "description": "Own Address 2 masks",
+ "offset": 8,
+ "size": 3
+ },
+ "OA2EN": {
+ "description": "Own Address 2 enable",
+ "offset": 15,
+ "size": 1
+ }
+ }
+ }
+ },
+ "TIMINGR": {
+ "description": "Timing register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SCLL": {
+ "description": "SCL low period (master\n mode)",
+ "offset": 0,
+ "size": 8
+ },
+ "SCLH": {
+ "description": "SCL high period (master\n mode)",
+ "offset": 8,
+ "size": 8
+ },
+ "SDADEL": {
+ "description": "Data hold time",
+ "offset": 16,
+ "size": 4
+ },
+ "SCLDEL": {
+ "description": "Data setup time",
+ "offset": 20,
+ "size": 4
+ },
+ "PRESC": {
+ "description": "Timing prescaler",
+ "offset": 28,
+ "size": 4
+ }
+ }
+ }
+ },
+ "TIMEOUTR": {
+ "description": "Status register 1",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIMEOUTA": {
+ "description": "Bus timeout A",
+ "offset": 0,
+ "size": 12
+ },
+ "TIDLE": {
+ "description": "Idle clock timeout\n detection",
+ "offset": 12,
+ "size": 1
+ },
+ "TIMOUTEN": {
+ "description": "Clock timeout enable",
+ "offset": 15,
+ "size": 1
+ },
+ "TIMEOUTB": {
+ "description": "Bus timeout B",
+ "offset": 16,
+ "size": 12
+ },
+ "TEXTEN": {
+ "description": "Extended clock timeout\n enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ISR": {
+ "description": "Interrupt and Status register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 1,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ADDCODE": {
+ "description": "Address match code (Slave\n mode)",
+ "offset": 17,
+ "size": 7,
+ "access": "read-only"
+ },
+ "DIR": {
+ "description": "Transfer direction (Slave\n mode)",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "BUSY": {
+ "description": "Bus busy",
+ "offset": 15,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ALERT": {
+ "description": "SMBus alert",
+ "offset": 13,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TIMEOUT": {
+ "description": "Timeout or t_low detection\n flag",
+ "offset": 12,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PECERR": {
+ "description": "PEC Error in reception",
+ "offset": 11,
+ "size": 1,
+ "access": "read-only"
+ },
+ "OVR": {
+ "description": "Overrun/Underrun (slave\n mode)",
+ "offset": 10,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ARLO": {
+ "description": "Arbitration lost",
+ "offset": 9,
+ "size": 1,
+ "access": "read-only"
+ },
+ "BERR": {
+ "description": "Bus error",
+ "offset": 8,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TCR": {
+ "description": "Transfer Complete Reload",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TC": {
+ "description": "Transfer Complete (master\n mode)",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "STOPF": {
+ "description": "Stop detection flag",
+ "offset": 5,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NACKF": {
+ "description": "Not acknowledge received\n flag",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ADDR": {
+ "description": "Address matched (slave\n mode)",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "RXNE": {
+ "description": "Receive data register not empty\n (receivers)",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TXIS": {
+ "description": "Transmit interrupt status\n (transmitters)",
+ "offset": 1,
+ "size": 1
+ },
+ "TXE": {
+ "description": "Transmit data register empty\n (transmitters)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ICR": {
+ "description": "Interrupt clear register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "ALERTCF": {
+ "description": "Alert flag clear",
+ "offset": 13,
+ "size": 1
+ },
+ "TIMOUTCF": {
+ "description": "Timeout detection flag\n clear",
+ "offset": 12,
+ "size": 1
+ },
+ "PECCF": {
+ "description": "PEC Error flag clear",
+ "offset": 11,
+ "size": 1
+ },
+ "OVRCF": {
+ "description": "Overrun/Underrun flag\n clear",
+ "offset": 10,
+ "size": 1
+ },
+ "ARLOCF": {
+ "description": "Arbitration lost flag\n clear",
+ "offset": 9,
+ "size": 1
+ },
+ "BERRCF": {
+ "description": "Bus error flag clear",
+ "offset": 8,
+ "size": 1
+ },
+ "STOPCF": {
+ "description": "Stop detection flag clear",
+ "offset": 5,
+ "size": 1
+ },
+ "NACKCF": {
+ "description": "Not Acknowledge flag clear",
+ "offset": 4,
+ "size": 1
+ },
+ "ADDRCF": {
+ "description": "Address Matched flag clear",
+ "offset": 3,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PECR": {
+ "description": "PEC register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "PEC": {
+ "description": "Packet error checking\n register",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "RXDR": {
+ "description": "Receive data register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "RXDATA": {
+ "description": "8-bit receive data",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "TXDR": {
+ "description": "Transmit data register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TXDATA": {
+ "description": "8-bit transmit data",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "TIM1": {
+ "description": "Advanced timer",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CEN": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ },
+ "UDIS": {
+ "description": "Update disable",
+ "offset": 1,
+ "size": 1
+ },
+ "URS": {
+ "description": "Update request source",
+ "offset": 2,
+ "size": 1
+ },
+ "OPM": {
+ "description": "One-pulse mode",
+ "offset": 3,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Direction",
+ "offset": 4,
+ "size": 1
+ },
+ "CMS": {
+ "description": "Center-aligned mode\n selection",
+ "offset": 5,
+ "size": 2
+ },
+ "ARPE": {
+ "description": "Auto-reload preload enable",
+ "offset": 7,
+ "size": 1
+ },
+ "CKD": {
+ "description": "Clock division",
+ "offset": 8,
+ "size": 2
+ },
+ "UIFREMAP": {
+ "description": "UIF status bit remapping",
+ "offset": 11,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCPC": {
+ "description": "Capture/compare preloaded\n control",
+ "offset": 0,
+ "size": 1
+ },
+ "CCUS": {
+ "description": "Capture/compare control update\n selection",
+ "offset": 2,
+ "size": 1
+ },
+ "CCDS": {
+ "description": "Capture/compare DMA\n selection",
+ "offset": 3,
+ "size": 1
+ },
+ "MMS": {
+ "description": "Master mode selection",
+ "offset": 4,
+ "size": 3
+ },
+ "TI1S": {
+ "description": "TI1 selection",
+ "offset": 7,
+ "size": 1
+ },
+ "OIS1": {
+ "description": "Output Idle state 1",
+ "offset": 8,
+ "size": 1
+ },
+ "OIS1N": {
+ "description": "Output Idle state 1",
+ "offset": 9,
+ "size": 1
+ },
+ "OIS2": {
+ "description": "Output Idle state 2",
+ "offset": 10,
+ "size": 1
+ },
+ "OIS2N": {
+ "description": "Output Idle state 2",
+ "offset": 11,
+ "size": 1
+ },
+ "OIS3": {
+ "description": "Output Idle state 3",
+ "offset": 12,
+ "size": 1
+ },
+ "OIS3N": {
+ "description": "Output Idle state 3",
+ "offset": 13,
+ "size": 1
+ },
+ "OIS4": {
+ "description": "Output Idle state 4",
+ "offset": 14,
+ "size": 1
+ },
+ "OIS5": {
+ "description": "Output Idle state 5",
+ "offset": 16,
+ "size": 1
+ },
+ "OIS6": {
+ "description": "Output Idle state 6",
+ "offset": 18,
+ "size": 1
+ },
+ "MMS2": {
+ "description": "Master mode selection 2",
+ "offset": 20,
+ "size": 4
+ }
+ }
+ }
+ },
+ "SMCR": {
+ "description": "slave mode control register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SMS": {
+ "description": "Slave mode selection",
+ "offset": 0,
+ "size": 3
+ },
+ "OCCS": {
+ "description": "OCREF clear selection",
+ "offset": 3,
+ "size": 1
+ },
+ "TS": {
+ "description": "Trigger selection",
+ "offset": 4,
+ "size": 3
+ },
+ "MSM": {
+ "description": "Master/Slave mode",
+ "offset": 7,
+ "size": 1
+ },
+ "ETF": {
+ "description": "External trigger filter",
+ "offset": 8,
+ "size": 4
+ },
+ "ETPS": {
+ "description": "External trigger prescaler",
+ "offset": 12,
+ "size": 2
+ },
+ "ECE": {
+ "description": "External clock enable",
+ "offset": 14,
+ "size": 1
+ },
+ "ETP": {
+ "description": "External trigger polarity",
+ "offset": 15,
+ "size": 1
+ },
+ "SMS3": {
+ "description": "Slave mode selection bit 3",
+ "offset": 16,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DIER": {
+ "description": "DMA/Interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TDE": {
+ "description": "Trigger DMA request enable",
+ "offset": 14,
+ "size": 1
+ },
+ "COMDE": {
+ "description": "COM DMA request enable",
+ "offset": 13,
+ "size": 1
+ },
+ "CC4DE": {
+ "description": "Capture/Compare 4 DMA request\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3DE": {
+ "description": "Capture/Compare 3 DMA request\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "CC2DE": {
+ "description": "Capture/Compare 2 DMA request\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC1DE": {
+ "description": "Capture/Compare 1 DMA request\n enable",
+ "offset": 9,
+ "size": 1
+ },
+ "UDE": {
+ "description": "Update DMA request enable",
+ "offset": 8,
+ "size": 1
+ },
+ "BIE": {
+ "description": "Break interrupt enable",
+ "offset": 7,
+ "size": 1
+ },
+ "TIE": {
+ "description": "Trigger interrupt enable",
+ "offset": 6,
+ "size": 1
+ },
+ "COMIE": {
+ "description": "COM interrupt enable",
+ "offset": 5,
+ "size": 1
+ },
+ "CC4IE": {
+ "description": "Capture/Compare 4 interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3IE": {
+ "description": "Capture/Compare 3 interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2IE": {
+ "description": "Capture/Compare 2 interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IE": {
+ "description": "Capture/Compare 1 interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "UIE": {
+ "description": "Update interrupt enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "UIF": {
+ "description": "Update interrupt flag",
+ "offset": 0,
+ "size": 1
+ },
+ "CC1IF": {
+ "description": "Capture/compare 1 interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "CC2IF": {
+ "description": "Capture/Compare 2 interrupt\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "CC3IF": {
+ "description": "Capture/Compare 3 interrupt\n flag",
+ "offset": 3,
+ "size": 1
+ },
+ "CC4IF": {
+ "description": "Capture/Compare 4 interrupt\n flag",
+ "offset": 4,
+ "size": 1
+ },
+ "COMIF": {
+ "description": "COM interrupt flag",
+ "offset": 5,
+ "size": 1
+ },
+ "TIF": {
+ "description": "Trigger interrupt flag",
+ "offset": 6,
+ "size": 1
+ },
+ "BIF": {
+ "description": "Break interrupt flag",
+ "offset": 7,
+ "size": 1
+ },
+ "B2IF": {
+ "description": "Break 2 interrupt flag",
+ "offset": 8,
+ "size": 1
+ },
+ "CC1OF": {
+ "description": "Capture/Compare 1 overcapture\n flag",
+ "offset": 9,
+ "size": 1
+ },
+ "CC2OF": {
+ "description": "Capture/compare 2 overcapture\n flag",
+ "offset": 10,
+ "size": 1
+ },
+ "CC3OF": {
+ "description": "Capture/Compare 3 overcapture\n flag",
+ "offset": 11,
+ "size": 1
+ },
+ "CC4OF": {
+ "description": "Capture/Compare 4 overcapture\n flag",
+ "offset": 12,
+ "size": 1
+ },
+ "C5IF": {
+ "description": "Capture/Compare 5 interrupt\n flag",
+ "offset": 16,
+ "size": 1
+ },
+ "C6IF": {
+ "description": "Capture/Compare 6 interrupt\n flag",
+ "offset": 17,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EGR": {
+ "description": "event generation register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "UG": {
+ "description": "Update generation",
+ "offset": 0,
+ "size": 1
+ },
+ "CC1G": {
+ "description": "Capture/compare 1\n generation",
+ "offset": 1,
+ "size": 1
+ },
+ "CC2G": {
+ "description": "Capture/compare 2\n generation",
+ "offset": 2,
+ "size": 1
+ },
+ "CC3G": {
+ "description": "Capture/compare 3\n generation",
+ "offset": 3,
+ "size": 1
+ },
+ "CC4G": {
+ "description": "Capture/compare 4\n generation",
+ "offset": 4,
+ "size": 1
+ },
+ "COMG": {
+ "description": "Capture/Compare control update\n generation",
+ "offset": 5,
+ "size": 1
+ },
+ "TG": {
+ "description": "Trigger generation",
+ "offset": 6,
+ "size": 1
+ },
+ "BG": {
+ "description": "Break generation",
+ "offset": 7,
+ "size": 1
+ },
+ "B2G": {
+ "description": "Break 2 generation",
+ "offset": 8,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Output": {
+ "description": "capture/compare mode register (output\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OC2CE": {
+ "description": "Output Compare 2 clear\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "OC2M": {
+ "description": "Output Compare 2 mode",
+ "offset": 12,
+ "size": 3
+ },
+ "OC2PE": {
+ "description": "Output Compare 2 preload\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "OC2FE": {
+ "description": "Output Compare 2 fast\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC2S": {
+ "description": "Capture/Compare 2\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "OC1CE": {
+ "description": "Output Compare 1 clear\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "OC1M": {
+ "description": "Output Compare 1 mode",
+ "offset": 4,
+ "size": 3
+ },
+ "OC1PE": {
+ "description": "Output Compare 1 preload\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "OC1FE": {
+ "description": "Output Compare 1 fast\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ },
+ "OC1M_3": {
+ "description": "Output Compare 1 mode bit\n 3",
+ "offset": 16,
+ "size": 1
+ },
+ "OC2M_3": {
+ "description": "Output Compare 2 mode bit\n 3",
+ "offset": 24,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Input": {
+ "description": "capture/compare mode register 1 (input\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC2F": {
+ "description": "Input capture 2 filter",
+ "offset": 12,
+ "size": 4
+ },
+ "IC2PCS": {
+ "description": "Input capture 2 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC2S": {
+ "description": "Capture/Compare 2\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC1F": {
+ "description": "Input capture 1 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "IC1PCS": {
+ "description": "Input capture 1 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR2_Output": {
+ "description": "capture/compare mode register (output\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OC4CE": {
+ "description": "Output compare 4 clear\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "OC4M": {
+ "description": "Output compare 4 mode",
+ "offset": 12,
+ "size": 3
+ },
+ "OC4PE": {
+ "description": "Output compare 4 preload\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "OC4FE": {
+ "description": "Output compare 4 fast\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC4S": {
+ "description": "Capture/Compare 4\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "OC3CE": {
+ "description": "Output compare 3 clear\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "OC3M": {
+ "description": "Output compare 3 mode",
+ "offset": 4,
+ "size": 3
+ },
+ "OC3PE": {
+ "description": "Output compare 3 preload\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "OC3FE": {
+ "description": "Output compare 3 fast\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC3S": {
+ "description": "Capture/Compare 3\n selection",
+ "offset": 0,
+ "size": 2
+ },
+ "OC3M_3": {
+ "description": "Output Compare 3 mode bit\n 3",
+ "offset": 16,
+ "size": 1
+ },
+ "OC4M_3": {
+ "description": "Output Compare 4 mode bit\n 3",
+ "offset": 24,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR2_Input": {
+ "description": "capture/compare mode register 2 (input\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC4F": {
+ "description": "Input capture 4 filter",
+ "offset": 12,
+ "size": 4
+ },
+ "IC4PSC": {
+ "description": "Input capture 4 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC4S": {
+ "description": "Capture/Compare 4\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC3F": {
+ "description": "Input capture 3 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "IC3PSC": {
+ "description": "Input capture 3 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC3S": {
+ "description": "Capture/compare 3\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCER": {
+ "description": "capture/compare enable\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC1E": {
+ "description": "Capture/Compare 1 output\n enable",
+ "offset": 0,
+ "size": 1
+ },
+ "CC1P": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 1,
+ "size": 1
+ },
+ "CC1NE": {
+ "description": "Capture/Compare 1 complementary output\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1NP": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2E": {
+ "description": "Capture/Compare 2 output\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC2P": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 5,
+ "size": 1
+ },
+ "CC2NE": {
+ "description": "Capture/Compare 2 complementary output\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "CC2NP": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 7,
+ "size": 1
+ },
+ "CC3E": {
+ "description": "Capture/Compare 3 output\n enable",
+ "offset": 8,
+ "size": 1
+ },
+ "CC3P": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 9,
+ "size": 1
+ },
+ "CC3NE": {
+ "description": "Capture/Compare 3 complementary output\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC3NP": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 11,
+ "size": 1
+ },
+ "CC4E": {
+ "description": "Capture/Compare 4 output\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "CC4P": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 13,
+ "size": 1
+ },
+ "CC4NP": {
+ "description": "Capture/Compare 4 output\n Polarity",
+ "offset": 15,
+ "size": 1
+ },
+ "CC5E": {
+ "description": "Capture/Compare 5 output\n enable",
+ "offset": 16,
+ "size": 1
+ },
+ "CC5P": {
+ "description": "Capture/Compare 5 output\n Polarity",
+ "offset": 17,
+ "size": 1
+ },
+ "CC6E": {
+ "description": "Capture/Compare 6 output\n enable",
+ "offset": 20,
+ "size": 1
+ },
+ "CC6P": {
+ "description": "Capture/Compare 6 output\n Polarity",
+ "offset": 21,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNT": {
+ "description": "counter",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNT": {
+ "description": "counter value",
+ "offset": 0,
+ "size": 16
+ },
+ "UIFCPY": {
+ "description": "UIF copy",
+ "offset": 31,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "PSC": {
+ "description": "prescaler",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ARR": {
+ "description": "auto-reload register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARR": {
+ "description": "Auto-reload value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "RCR": {
+ "description": "repetition counter register",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "REP": {
+ "description": "Repetition counter value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR1": {
+ "description": "capture/compare register 1",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR1": {
+ "description": "Capture/Compare 1 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR2": {
+ "description": "capture/compare register 2",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR2": {
+ "description": "Capture/Compare 2 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR3": {
+ "description": "capture/compare register 3",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR3": {
+ "description": "Capture/Compare 3 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR4": {
+ "description": "capture/compare register 4",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR4": {
+ "description": "Capture/Compare 3 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "BDTR": {
+ "description": "break and dead-time register",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DTG": {
+ "description": "Dead-time generator setup",
+ "offset": 0,
+ "size": 8
+ },
+ "LOCK": {
+ "description": "Lock configuration",
+ "offset": 8,
+ "size": 2
+ },
+ "OSSI": {
+ "description": "Off-state selection for Idle\n mode",
+ "offset": 10,
+ "size": 1
+ },
+ "OSSR": {
+ "description": "Off-state selection for Run\n mode",
+ "offset": 11,
+ "size": 1
+ },
+ "BKE": {
+ "description": "Break enable",
+ "offset": 12,
+ "size": 1
+ },
+ "BKP": {
+ "description": "Break polarity",
+ "offset": 13,
+ "size": 1
+ },
+ "AOE": {
+ "description": "Automatic output enable",
+ "offset": 14,
+ "size": 1
+ },
+ "MOE": {
+ "description": "Main output enable",
+ "offset": 15,
+ "size": 1
+ },
+ "BKF": {
+ "description": "Break filter",
+ "offset": 16,
+ "size": 4
+ },
+ "BK2F": {
+ "description": "Break 2 filter",
+ "offset": 20,
+ "size": 4
+ },
+ "BK2E": {
+ "description": "Break 2 enable",
+ "offset": 24,
+ "size": 1
+ },
+ "BK2P": {
+ "description": "Break 2 polarity",
+ "offset": 25,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DCR": {
+ "description": "DMA control register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBL": {
+ "description": "DMA burst length",
+ "offset": 8,
+ "size": 5
+ },
+ "DBA": {
+ "description": "DMA base address",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "DMAR": {
+ "description": "DMA address for full transfer",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAB": {
+ "description": "DMA register for burst\n accesses",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCMR3_Output": {
+ "description": "capture/compare mode register 3 (output\n mode)",
+ "offset": 84,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OC5FE": {
+ "description": "Output compare 5 fast\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "OC5PE": {
+ "description": "Output compare 5 preload\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "OC5M": {
+ "description": "Output compare 5 mode",
+ "offset": 4,
+ "size": 3
+ },
+ "OC5CE": {
+ "description": "Output compare 5 clear\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "OC6FE": {
+ "description": "Output compare 6 fast\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "OC6PE": {
+ "description": "Output compare 6 preload\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "OC6M": {
+ "description": "Output compare 6 mode",
+ "offset": 12,
+ "size": 3
+ },
+ "OC6CE": {
+ "description": "Output compare 6 clear\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "OC5M_3": {
+ "description": "Outout Compare 5 mode bit\n 3",
+ "offset": 16,
+ "size": 1
+ },
+ "OC6M_3": {
+ "description": "Outout Compare 6 mode bit\n 3",
+ "offset": 24,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCR5": {
+ "description": "capture/compare register 5",
+ "offset": 88,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR5": {
+ "description": "Capture/Compare 5 value",
+ "offset": 0,
+ "size": 16
+ },
+ "GC5C1": {
+ "description": "Group Channel 5 and Channel\n 1",
+ "offset": 29,
+ "size": 1
+ },
+ "GC5C2": {
+ "description": "Group Channel 5 and Channel\n 2",
+ "offset": 30,
+ "size": 1
+ },
+ "GC5C3": {
+ "description": "Group Channel 5 and Channel\n 3",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCR6": {
+ "description": "capture/compare register 6",
+ "offset": 92,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR6": {
+ "description": "Capture/Compare 6 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OR": {
+ "description": "option registers",
+ "offset": 96,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIM1_ETR_ADC1_RMP": {
+ "description": "TIM1_ETR_ADC1 remapping\n capability",
+ "offset": 0,
+ "size": 2
+ },
+ "TIM1_ETR_ADC4_RMP": {
+ "description": "TIM1_ETR_ADC4 remapping\n capability",
+ "offset": 2,
+ "size": 2
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "DBGMCU": {
+ "description": "Debug support",
+ "children": {
+ "registers": {
+ "IDCODE": {
+ "description": "MCU Device ID Code Register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DEV_ID": {
+ "description": "Device Identifier",
+ "offset": 0,
+ "size": 12
+ },
+ "REV_ID": {
+ "description": "Revision Identifier",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CR": {
+ "description": "Debug MCU Configuration\n Register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBG_SLEEP": {
+ "description": "Debug Sleep mode",
+ "offset": 0,
+ "size": 1
+ },
+ "DBG_STOP": {
+ "description": "Debug Stop Mode",
+ "offset": 1,
+ "size": 1
+ },
+ "DBG_STANDBY": {
+ "description": "Debug Standby Mode",
+ "offset": 2,
+ "size": 1
+ },
+ "TRACE_IOEN": {
+ "description": "Trace pin assignment\n control",
+ "offset": 5,
+ "size": 1
+ },
+ "TRACE_MODE": {
+ "description": "Trace pin assignment\n control",
+ "offset": 6,
+ "size": 2
+ }
+ }
+ }
+ },
+ "APB1FZ": {
+ "description": "APB Low Freeze Register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBG_TIM2_STOP": {
+ "description": "Debug Timer 2 stopped when Core is\n halted",
+ "offset": 0,
+ "size": 1
+ },
+ "DBG_TIM3_STOP": {
+ "description": "Debug Timer 3 stopped when Core is\n halted",
+ "offset": 1,
+ "size": 1
+ },
+ "DBG_TIM4_STOP": {
+ "description": "Debug Timer 4 stopped when Core is\n halted",
+ "offset": 2,
+ "size": 1
+ },
+ "DBG_TIM5_STOP": {
+ "description": "Debug Timer 5 stopped when Core is\n halted",
+ "offset": 3,
+ "size": 1
+ },
+ "DBG_TIM6_STOP": {
+ "description": "Debug Timer 6 stopped when Core is\n halted",
+ "offset": 4,
+ "size": 1
+ },
+ "DBG_TIM7_STOP": {
+ "description": "Debug Timer 7 stopped when Core is\n halted",
+ "offset": 5,
+ "size": 1
+ },
+ "DBG_TIM12_STOP": {
+ "description": "Debug Timer 12 stopped when Core is\n halted",
+ "offset": 6,
+ "size": 1
+ },
+ "DBG_TIM13_STOP": {
+ "description": "Debug Timer 13 stopped when Core is\n halted",
+ "offset": 7,
+ "size": 1
+ },
+ "DBG_TIMER14_STOP": {
+ "description": "Debug Timer 14 stopped when Core is\n halted",
+ "offset": 8,
+ "size": 1
+ },
+ "DBG_TIM18_STOP": {
+ "description": "Debug Timer 18 stopped when Core is\n halted",
+ "offset": 9,
+ "size": 1
+ },
+ "DBG_RTC_STOP": {
+ "description": "Debug RTC stopped when Core is\n halted",
+ "offset": 10,
+ "size": 1
+ },
+ "DBG_WWDG_STOP": {
+ "description": "Debug Window Wachdog stopped when Core\n is halted",
+ "offset": 11,
+ "size": 1
+ },
+ "DBG_IWDG_STOP": {
+ "description": "Debug Independent Wachdog stopped when\n Core is halted",
+ "offset": 12,
+ "size": 1
+ },
+ "I2C1_SMBUS_TIMEOUT": {
+ "description": "SMBUS timeout mode stopped when Core is\n halted",
+ "offset": 21,
+ "size": 1
+ },
+ "I2C2_SMBUS_TIMEOUT": {
+ "description": "SMBUS timeout mode stopped when Core is\n halted",
+ "offset": 22,
+ "size": 1
+ },
+ "DBG_CAN_STOP": {
+ "description": "Debug CAN stopped when core is\n halted",
+ "offset": 25,
+ "size": 1
+ }
+ }
+ }
+ },
+ "APB2FZ": {
+ "description": "APB High Freeze Register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBG_TIM15_STOP": {
+ "description": "Debug Timer 15 stopped when Core is\n halted",
+ "offset": 2,
+ "size": 1
+ },
+ "DBG_TIM16_STOP": {
+ "description": "Debug Timer 16 stopped when Core is\n halted",
+ "offset": 3,
+ "size": 1
+ },
+ "DBG_TIM17_STO": {
+ "description": "Debug Timer 17 stopped when Core is\n halted",
+ "offset": 4,
+ "size": 1
+ },
+ "DBG_TIM19_STOP": {
+ "description": "Debug Timer 19 stopped when Core is\n halted",
+ "offset": 5,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "devices": {
+ "STM32F303": {
+ "arch": "cortex_m4",
+ "description": "STM32F303",
+ "properties": {
+ "cpu.nvic_prio_bits": "3",
+ "cpu.mpu": "false",
+ "cpu.fpu": "false",
+ "cpu.revision": "r1p0",
+ "cpu.vendor_systick_config": "false",
+ "cpu.endian": "little",
+ "cpu.name": "CM4"
+ },
+ "children": {
+ "interrupts": {
+ "MemManageFault": {
+ "index": -12
+ },
+ "BusFault": {
+ "index": -11
+ },
+ "UsageFault": {
+ "index": -10
+ },
+ "DebugMonitor": {
+ "index": -4
+ },
+ "NMI": {
+ "index": -14
+ },
+ "HardFault": {
+ "index": -13
+ },
+ "SVCall": {
+ "index": -5
+ },
+ "PendSV": {
+ "index": -2
+ },
+ "SysTick": {
+ "index": -1
+ },
+ "EXTI2_TSC": {
+ "index": 8,
+ "description": "EXTI Line2 and Touch sensing\n interrupts"
+ },
+ "FLASH": {
+ "index": 4,
+ "description": "Flash global interrupt"
+ },
+ "RCC": {
+ "index": 5,
+ "description": "RCC global interrupt"
+ },
+ "DMA1_CH1": {
+ "index": 11,
+ "description": "DMA1 channel 1 interrupt"
+ },
+ "DMA2_CH1": {
+ "index": 56,
+ "description": "DMA2 channel1 global interrupt"
+ },
+ "TIM2": {
+ "index": 28,
+ "description": "TIM2 global interrupt"
+ },
+ "TIM3": {
+ "index": 29,
+ "description": "TIM3 global interrupt"
+ },
+ "TIM4": {
+ "index": 30,
+ "description": "TIM4 global interrupt"
+ },
+ "TIM1_BRK_TIM15": {
+ "index": 24,
+ "description": "TIM1 Break/TIM15 global\n interruts"
+ },
+ "TIM1_UP_TIM16": {
+ "index": 25,
+ "description": "TIM1 Update/TIM16 global\n interrupts"
+ },
+ "TIM1_TRG_COM_TIM17": {
+ "index": 26,
+ "description": "TIM1 trigger and commutation/TIM17\n interrupts"
+ },
+ "USART1_EXTI25": {
+ "index": 37,
+ "description": "USART1 global interrupt and EXTI Line 25\n interrupt"
+ },
+ "USART2_EXTI26": {
+ "index": 38,
+ "description": "USART2 global interrupt and EXTI Line 26\n interrupt"
+ },
+ "USART3_EXTI28": {
+ "index": 39,
+ "description": "USART3 global interrupt and EXTI Line 28\n interrupt"
+ },
+ "UART4_EXTI34": {
+ "index": 52,
+ "description": "UART4 global and EXTI Line 34\n interrupts"
+ },
+ "UART5_EXTI35": {
+ "index": 53,
+ "description": "UART5 global and EXTI Line 35\n interrupts"
+ },
+ "SPI1": {
+ "index": 35,
+ "description": "SPI1 global interrupt"
+ },
+ "SPI2": {
+ "index": 36,
+ "description": "SPI2 global interrupt"
+ },
+ "SPI3": {
+ "index": 51,
+ "description": "SPI3 global interrupt"
+ },
+ "TAMP_STAMP": {
+ "index": 2,
+ "description": "Tamper and TimeStamp interrupts"
+ },
+ "PVD": {
+ "index": 1,
+ "description": "PVD through EXTI line detection\n interrupt"
+ },
+ "USB_HP_CAN_TX": {
+ "index": 19,
+ "description": "USB High Priority/CAN_TX\n interrupts"
+ },
+ "USB_WKUP": {
+ "index": 42,
+ "description": "USB wakeup from Suspend"
+ },
+ "I2C1_EV_EXTI23": {
+ "index": 31,
+ "description": "I2C1 event interrupt and EXTI Line23\n interrupt"
+ },
+ "I2C2_EV_EXTI24": {
+ "index": 33,
+ "description": "I2C2 event interrupt & EXTI Line24\n interrupt"
+ },
+ "WWDG": {
+ "index": 0,
+ "description": "Window Watchdog interrupt"
+ },
+ "RTC_WKUP": {
+ "index": 3,
+ "description": "RTC Wakeup interrupt through the EXTI\n line"
+ },
+ "TIM6_DACUNDER": {
+ "index": 54,
+ "description": "TIM6 global and DAC12 underrun\n interrupts"
+ },
+ "TIM7": {
+ "index": 55,
+ "description": "TIM7 global interrupt"
+ },
+ "TIM1_CC": {
+ "index": 27,
+ "description": "TIM1 capture compare interrupt"
+ },
+ "TIM8_BRK": {
+ "index": 43,
+ "description": "TIM8 break interrupt"
+ },
+ "ADC1_2": {
+ "index": 18,
+ "description": "ADC1 and ADC2 global interrupt"
+ },
+ "ADC3": {
+ "index": 47,
+ "description": "ADC3 global interrupt"
+ },
+ "ADC4": {
+ "index": 61,
+ "description": "ADC4 global interrupt"
+ },
+ "COMP123": {
+ "index": 64,
+ "description": "COMP1 & COMP2 & COMP3 interrupts\n combined with EXTI Lines 21, 22 and 29\n interrupts"
+ },
+ "FMC": {
+ "index": 48,
+ "description": "FSMC global interrupt"
+ },
+ "FPU": {
+ "index": 81,
+ "description": "Floating point unit interrupt"
+ }
+ },
+ "peripheral_instances": {
+ "GPIOA": {
+ "description": "General-purpose I/Os",
+ "offset": 1207959552,
+ "type": "types.peripherals.GPIOA"
+ },
+ "GPIOB": {
+ "description": "General-purpose I/Os",
+ "offset": 1207960576,
+ "type": "types.peripherals.GPIOB"
+ },
+ "GPIOC": {
+ "offset": 1207961600,
+ "type": "types.peripherals.GPIOB"
+ },
+ "GPIOD": {
+ "offset": 1207962624,
+ "type": "types.peripherals.GPIOB"
+ },
+ "GPIOE": {
+ "offset": 1207963648,
+ "type": "types.peripherals.GPIOB"
+ },
+ "GPIOF": {
+ "offset": 1207964672,
+ "type": "types.peripherals.GPIOB"
+ },
+ "GPIOG": {
+ "offset": 1207965696,
+ "type": "types.peripherals.GPIOB"
+ },
+ "GPIOH": {
+ "offset": 1207966720,
+ "type": "types.peripherals.GPIOB"
+ },
+ "TSC": {
+ "description": "Touch sensing controller",
+ "offset": 1073889280,
+ "type": "types.peripherals.TSC"
+ },
+ "CRC": {
+ "description": "cyclic redundancy check calculation\n unit",
+ "offset": 1073885184,
+ "type": "types.peripherals.CRC"
+ },
+ "Flash": {
+ "description": "Flash",
+ "offset": 1073881088,
+ "type": "types.peripherals.Flash"
+ },
+ "RCC": {
+ "description": "Reset and clock control",
+ "offset": 1073876992,
+ "type": "types.peripherals.RCC"
+ },
+ "DMA1": {
+ "description": "DMA controller 1",
+ "offset": 1073872896,
+ "type": "types.peripherals.DMA1"
+ },
+ "DMA2": {
+ "offset": 1073873920,
+ "type": "types.peripherals.DMA1"
+ },
+ "TIM2": {
+ "description": "General purpose timer",
+ "offset": 1073741824,
+ "type": "types.peripherals.TIM2"
+ },
+ "TIM3": {
+ "offset": 1073742848,
+ "type": "types.peripherals.TIM2"
+ },
+ "TIM4": {
+ "offset": 1073743872,
+ "type": "types.peripherals.TIM2"
+ },
+ "TIM15": {
+ "description": "General purpose timers",
+ "offset": 1073823744,
+ "type": "types.peripherals.TIM15"
+ },
+ "TIM16": {
+ "description": "General-purpose-timers",
+ "offset": 1073824768,
+ "type": "types.peripherals.TIM16"
+ },
+ "TIM17": {
+ "description": "General purpose timer",
+ "offset": 1073825792,
+ "type": "types.peripherals.TIM17"
+ },
+ "USART1": {
+ "description": "Universal synchronous asynchronous receiver\n transmitter",
+ "offset": 1073821696,
+ "type": "types.peripherals.USART1"
+ },
+ "USART2": {
+ "offset": 1073759232,
+ "type": "types.peripherals.USART1"
+ },
+ "USART3": {
+ "offset": 1073760256,
+ "type": "types.peripherals.USART1"
+ },
+ "UART4": {
+ "offset": 1073761280,
+ "type": "types.peripherals.USART1"
+ },
+ "UART5": {
+ "offset": 1073762304,
+ "type": "types.peripherals.USART1"
+ },
+ "SPI1": {
+ "description": "Serial peripheral interface/Inter-IC\n sound",
+ "offset": 1073819648,
+ "type": "types.peripherals.SPI1"
+ },
+ "SPI2": {
+ "offset": 1073756160,
+ "type": "types.peripherals.SPI1"
+ },
+ "SPI3": {
+ "offset": 1073757184,
+ "type": "types.peripherals.SPI1"
+ },
+ "I2S2ext": {
+ "offset": 1073755136,
+ "type": "types.peripherals.SPI1"
+ },
+ "I2S3ext": {
+ "offset": 1073758208,
+ "type": "types.peripherals.SPI1"
+ },
+ "SPI4": {
+ "offset": 1073822720,
+ "type": "types.peripherals.SPI1"
+ },
+ "EXTI": {
+ "description": "External interrupt/event\n controller",
+ "offset": 1073808384,
+ "type": "types.peripherals.EXTI"
+ },
+ "PWR": {
+ "description": "Power control",
+ "offset": 1073770496,
+ "type": "types.peripherals.PWR"
+ },
+ "CAN": {
+ "description": "Controller area network",
+ "offset": 1073767424,
+ "type": "types.peripherals.CAN"
+ },
+ "USB_FS": {
+ "description": "Universal serial bus full-speed device\n interface",
+ "offset": 1073765376,
+ "type": "types.peripherals.USB_FS"
+ },
+ "I2C1": {
+ "description": "Inter-integrated circuit",
+ "offset": 1073763328,
+ "type": "types.peripherals.I2C1"
+ },
+ "I2C2": {
+ "offset": 1073764352,
+ "type": "types.peripherals.I2C1"
+ },
+ "I2C3": {
+ "offset": 1073772544,
+ "type": "types.peripherals.I2C1"
+ },
+ "IWDG": {
+ "description": "Independent watchdog",
+ "offset": 1073754112,
+ "type": "types.peripherals.IWDG"
+ },
+ "WWDG": {
+ "description": "Window watchdog",
+ "offset": 1073753088,
+ "type": "types.peripherals.WWDG"
+ },
+ "RTC": {
+ "description": "Real-time clock",
+ "offset": 1073752064,
+ "type": "types.peripherals.RTC"
+ },
+ "TIM6": {
+ "description": "Basic timers",
+ "offset": 1073745920,
+ "type": "types.peripherals.TIM6"
+ },
+ "TIM7": {
+ "offset": 1073746944,
+ "type": "types.peripherals.TIM6"
+ },
+ "DAC": {
+ "description": "Digital-to-analog converter",
+ "offset": 1073771520,
+ "type": "types.peripherals.DAC"
+ },
+ "DBGMCU": {
+ "description": "Debug support",
+ "offset": 3758366720,
+ "type": "types.peripherals.DBGMCU"
+ },
+ "TIM1": {
+ "description": "Advanced timer",
+ "offset": 1073818624,
+ "type": "types.peripherals.TIM1"
+ },
+ "TIM20": {
+ "offset": 1073827840,
+ "type": "types.peripherals.TIM1"
+ },
+ "TIM8": {
+ "description": "Advanced-timers",
+ "offset": 1073820672,
+ "type": "types.peripherals.TIM8"
+ },
+ "ADC1": {
+ "description": "Analog-to-Digital Converter",
+ "offset": 1342177280,
+ "type": "types.peripherals.ADC1"
+ },
+ "ADC2": {
+ "offset": 1342177536,
+ "type": "types.peripherals.ADC1"
+ },
+ "ADC3": {
+ "offset": 1342178304,
+ "type": "types.peripherals.ADC1"
+ },
+ "ADC4": {
+ "offset": 1342178560,
+ "type": "types.peripherals.ADC1"
+ },
+ "ADC1_2": {
+ "description": "Analog-to-Digital Converter",
+ "offset": 1342178048,
+ "type": "types.peripherals.ADC1_2"
+ },
+ "ADC3_4": {
+ "offset": 1342179072,
+ "type": "types.peripherals.ADC1_2"
+ },
+ "SYSCFG_COMP_OPAMP": {
+ "description": "System configuration controller _Comparator and\n Operational amplifier",
+ "offset": 1073807360,
+ "type": "types.peripherals.SYSCFG_COMP_OPAMP"
+ },
+ "FMC": {
+ "description": "Flexible memory controller",
+ "offset": 2684355584,
+ "type": "types.peripherals.FMC"
+ },
+ "NVIC": {
+ "description": "Nested Vectored Interrupt\n Controller",
+ "offset": 3758153984,
+ "type": "types.peripherals.NVIC"
+ },
+ "FPU": {
+ "description": "Floting point unit",
+ "offset": 3758157620,
+ "type": "types.peripherals.FPU"
+ },
+ "MPU": {
+ "description": "Memory protection unit",
+ "offset": 3758157200,
+ "type": "types.peripherals.MPU"
+ },
+ "STK": {
+ "description": "SysTick timer",
+ "offset": 3758153744,
+ "type": "types.peripherals.STK"
+ },
+ "SCB": {
+ "description": "System control block",
+ "offset": 3758157056,
+ "type": "types.peripherals.SCB"
+ },
+ "NVIC_STIR": {
+ "description": "Nested vectored interrupt\n controller",
+ "offset": 3758157568,
+ "type": "types.peripherals.NVIC_STIR"
+ },
+ "FPU_CPACR": {
+ "description": "Floating point unit CPACR",
+ "offset": 3758157192,
+ "type": "types.peripherals.FPU_CPACR"
+ },
+ "SCB_ACTRL": {
+ "description": "System control block ACTLR",
+ "offset": 3758153736,
+ "type": "types.peripherals.SCB_ACTRL"
+ }
+ }
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/board-support/stmicro-stm32/src/chips/STM32F407.json b/board-support/stmicro-stm32/src/chips/STM32F407.json
new file mode 100644
index 0000000..7f592e5
--- /dev/null
+++ b/board-support/stmicro-stm32/src/chips/STM32F407.json
@@ -0,0 +1,50953 @@
+{
+ "version": "0.1.0",
+ "types": {
+ "peripherals": {
+ "RNG": {
+ "description": "Random number generator",
+ "children": {
+ "registers": {
+ "CR": {
+ "description": "control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IE": {
+ "description": "Interrupt enable",
+ "offset": 3,
+ "size": 1
+ },
+ "RNGEN": {
+ "description": "Random number generator\n enable",
+ "offset": 2,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SEIS": {
+ "description": "Seed error interrupt\n status",
+ "offset": 6,
+ "size": 1
+ },
+ "CEIS": {
+ "description": "Clock error interrupt\n status",
+ "offset": 5,
+ "size": 1
+ },
+ "SECS": {
+ "description": "Seed error current status",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "CECS": {
+ "description": "Clock error current status",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "DRDY": {
+ "description": "Data ready",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "DR": {
+ "description": "data register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "RNDATA": {
+ "description": "Random data",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "DCMI": {
+ "description": "Digital camera interface",
+ "children": {
+ "registers": {
+ "CR": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ENABLE": {
+ "description": "DCMI enable",
+ "offset": 14,
+ "size": 1
+ },
+ "EDM": {
+ "description": "Extended data mode",
+ "offset": 10,
+ "size": 2
+ },
+ "FCRC": {
+ "description": "Frame capture rate control",
+ "offset": 8,
+ "size": 2
+ },
+ "VSPOL": {
+ "description": "Vertical synchronization\n polarity",
+ "offset": 7,
+ "size": 1
+ },
+ "HSPOL": {
+ "description": "Horizontal synchronization\n polarity",
+ "offset": 6,
+ "size": 1
+ },
+ "PCKPOL": {
+ "description": "Pixel clock polarity",
+ "offset": 5,
+ "size": 1
+ },
+ "ESS": {
+ "description": "Embedded synchronization\n select",
+ "offset": 4,
+ "size": 1
+ },
+ "JPEG": {
+ "description": "JPEG format",
+ "offset": 3,
+ "size": 1
+ },
+ "CROP": {
+ "description": "Crop feature",
+ "offset": 2,
+ "size": 1
+ },
+ "CM": {
+ "description": "Capture mode",
+ "offset": 1,
+ "size": 1
+ },
+ "CAPTURE": {
+ "description": "Capture enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "FNE": {
+ "description": "FIFO not empty",
+ "offset": 2,
+ "size": 1
+ },
+ "VSYNC": {
+ "description": "VSYNC",
+ "offset": 1,
+ "size": 1
+ },
+ "HSYNC": {
+ "description": "HSYNC",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "RIS": {
+ "description": "raw interrupt status register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "LINE_RIS": {
+ "description": "Line raw interrupt status",
+ "offset": 4,
+ "size": 1
+ },
+ "VSYNC_RIS": {
+ "description": "VSYNC raw interrupt status",
+ "offset": 3,
+ "size": 1
+ },
+ "ERR_RIS": {
+ "description": "Synchronization error raw interrupt\n status",
+ "offset": 2,
+ "size": 1
+ },
+ "OVR_RIS": {
+ "description": "Overrun raw interrupt\n status",
+ "offset": 1,
+ "size": 1
+ },
+ "FRAME_RIS": {
+ "description": "Capture complete raw interrupt\n status",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "IER": {
+ "description": "interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LINE_IE": {
+ "description": "Line interrupt enable",
+ "offset": 4,
+ "size": 1
+ },
+ "VSYNC_IE": {
+ "description": "VSYNC interrupt enable",
+ "offset": 3,
+ "size": 1
+ },
+ "ERR_IE": {
+ "description": "Synchronization error interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "OVR_IE": {
+ "description": "Overrun interrupt enable",
+ "offset": 1,
+ "size": 1
+ },
+ "FRAME_IE": {
+ "description": "Capture complete interrupt\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MIS": {
+ "description": "masked interrupt status\n register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "LINE_MIS": {
+ "description": "Line masked interrupt\n status",
+ "offset": 4,
+ "size": 1
+ },
+ "VSYNC_MIS": {
+ "description": "VSYNC masked interrupt\n status",
+ "offset": 3,
+ "size": 1
+ },
+ "ERR_MIS": {
+ "description": "Synchronization error masked interrupt\n status",
+ "offset": 2,
+ "size": 1
+ },
+ "OVR_MIS": {
+ "description": "Overrun masked interrupt\n status",
+ "offset": 1,
+ "size": 1
+ },
+ "FRAME_MIS": {
+ "description": "Capture complete masked interrupt\n status",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ICR": {
+ "description": "interrupt clear register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "LINE_ISC": {
+ "description": "line interrupt status\n clear",
+ "offset": 4,
+ "size": 1
+ },
+ "VSYNC_ISC": {
+ "description": "Vertical synch interrupt status\n clear",
+ "offset": 3,
+ "size": 1
+ },
+ "ERR_ISC": {
+ "description": "Synchronization error interrupt status\n clear",
+ "offset": 2,
+ "size": 1
+ },
+ "OVR_ISC": {
+ "description": "Overrun interrupt status\n clear",
+ "offset": 1,
+ "size": 1
+ },
+ "FRAME_ISC": {
+ "description": "Capture complete interrupt status\n clear",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ESCR": {
+ "description": "embedded synchronization code\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEC": {
+ "description": "Frame end delimiter code",
+ "offset": 24,
+ "size": 8
+ },
+ "LEC": {
+ "description": "Line end delimiter code",
+ "offset": 16,
+ "size": 8
+ },
+ "LSC": {
+ "description": "Line start delimiter code",
+ "offset": 8,
+ "size": 8
+ },
+ "FSC": {
+ "description": "Frame start delimiter code",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "ESUR": {
+ "description": "embedded synchronization unmask\n register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEU": {
+ "description": "Frame end delimiter unmask",
+ "offset": 24,
+ "size": 8
+ },
+ "LEU": {
+ "description": "Line end delimiter unmask",
+ "offset": 16,
+ "size": 8
+ },
+ "LSU": {
+ "description": "Line start delimiter\n unmask",
+ "offset": 8,
+ "size": 8
+ },
+ "FSU": {
+ "description": "Frame start delimiter\n unmask",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "CWSTRT": {
+ "description": "crop window start",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "VST": {
+ "description": "Vertical start line count",
+ "offset": 16,
+ "size": 13
+ },
+ "HOFFCNT": {
+ "description": "Horizontal offset count",
+ "offset": 0,
+ "size": 14
+ }
+ }
+ }
+ },
+ "CWSIZE": {
+ "description": "crop window size",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "VLINE": {
+ "description": "Vertical line count",
+ "offset": 16,
+ "size": 14
+ },
+ "CAPCNT": {
+ "description": "Capture count",
+ "offset": 0,
+ "size": 14
+ }
+ }
+ }
+ },
+ "DR": {
+ "description": "data register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "Byte3": {
+ "description": "Data byte 3",
+ "offset": 24,
+ "size": 8
+ },
+ "Byte2": {
+ "description": "Data byte 2",
+ "offset": 16,
+ "size": 8
+ },
+ "Byte1": {
+ "description": "Data byte 1",
+ "offset": 8,
+ "size": 8
+ },
+ "Byte0": {
+ "description": "Data byte 0",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "FSMC": {
+ "description": "Flexible static memory controller",
+ "children": {
+ "registers": {
+ "BCR1": {
+ "description": "SRAM/NOR-Flash chip-select control register\n 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 12496,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CBURSTRW": {
+ "description": "CBURSTRW",
+ "offset": 19,
+ "size": 1
+ },
+ "ASYNCWAIT": {
+ "description": "ASYNCWAIT",
+ "offset": 15,
+ "size": 1
+ },
+ "EXTMOD": {
+ "description": "EXTMOD",
+ "offset": 14,
+ "size": 1
+ },
+ "WAITEN": {
+ "description": "WAITEN",
+ "offset": 13,
+ "size": 1
+ },
+ "WREN": {
+ "description": "WREN",
+ "offset": 12,
+ "size": 1
+ },
+ "WAITCFG": {
+ "description": "WAITCFG",
+ "offset": 11,
+ "size": 1
+ },
+ "WAITPOL": {
+ "description": "WAITPOL",
+ "offset": 9,
+ "size": 1
+ },
+ "BURSTEN": {
+ "description": "BURSTEN",
+ "offset": 8,
+ "size": 1
+ },
+ "FACCEN": {
+ "description": "FACCEN",
+ "offset": 6,
+ "size": 1
+ },
+ "MWID": {
+ "description": "MWID",
+ "offset": 4,
+ "size": 2
+ },
+ "MTYP": {
+ "description": "MTYP",
+ "offset": 2,
+ "size": 2
+ },
+ "MUXEN": {
+ "description": "MUXEN",
+ "offset": 1,
+ "size": 1
+ },
+ "MBKEN": {
+ "description": "MBKEN",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BTR1": {
+ "description": "SRAM/NOR-Flash chip-select timing register\n 1",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "BUSTURN": {
+ "description": "BUSTURN",
+ "offset": 16,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "BCR2": {
+ "description": "SRAM/NOR-Flash chip-select control register\n 2",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 12496,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CBURSTRW": {
+ "description": "CBURSTRW",
+ "offset": 19,
+ "size": 1
+ },
+ "ASYNCWAIT": {
+ "description": "ASYNCWAIT",
+ "offset": 15,
+ "size": 1
+ },
+ "EXTMOD": {
+ "description": "EXTMOD",
+ "offset": 14,
+ "size": 1
+ },
+ "WAITEN": {
+ "description": "WAITEN",
+ "offset": 13,
+ "size": 1
+ },
+ "WREN": {
+ "description": "WREN",
+ "offset": 12,
+ "size": 1
+ },
+ "WAITCFG": {
+ "description": "WAITCFG",
+ "offset": 11,
+ "size": 1
+ },
+ "WRAPMOD": {
+ "description": "WRAPMOD",
+ "offset": 10,
+ "size": 1
+ },
+ "WAITPOL": {
+ "description": "WAITPOL",
+ "offset": 9,
+ "size": 1
+ },
+ "BURSTEN": {
+ "description": "BURSTEN",
+ "offset": 8,
+ "size": 1
+ },
+ "FACCEN": {
+ "description": "FACCEN",
+ "offset": 6,
+ "size": 1
+ },
+ "MWID": {
+ "description": "MWID",
+ "offset": 4,
+ "size": 2
+ },
+ "MTYP": {
+ "description": "MTYP",
+ "offset": 2,
+ "size": 2
+ },
+ "MUXEN": {
+ "description": "MUXEN",
+ "offset": 1,
+ "size": 1
+ },
+ "MBKEN": {
+ "description": "MBKEN",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BTR2": {
+ "description": "SRAM/NOR-Flash chip-select timing register\n 2",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "BUSTURN": {
+ "description": "BUSTURN",
+ "offset": 16,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "BCR3": {
+ "description": "SRAM/NOR-Flash chip-select control register\n 3",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 12496,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CBURSTRW": {
+ "description": "CBURSTRW",
+ "offset": 19,
+ "size": 1
+ },
+ "ASYNCWAIT": {
+ "description": "ASYNCWAIT",
+ "offset": 15,
+ "size": 1
+ },
+ "EXTMOD": {
+ "description": "EXTMOD",
+ "offset": 14,
+ "size": 1
+ },
+ "WAITEN": {
+ "description": "WAITEN",
+ "offset": 13,
+ "size": 1
+ },
+ "WREN": {
+ "description": "WREN",
+ "offset": 12,
+ "size": 1
+ },
+ "WAITCFG": {
+ "description": "WAITCFG",
+ "offset": 11,
+ "size": 1
+ },
+ "WRAPMOD": {
+ "description": "WRAPMOD",
+ "offset": 10,
+ "size": 1
+ },
+ "WAITPOL": {
+ "description": "WAITPOL",
+ "offset": 9,
+ "size": 1
+ },
+ "BURSTEN": {
+ "description": "BURSTEN",
+ "offset": 8,
+ "size": 1
+ },
+ "FACCEN": {
+ "description": "FACCEN",
+ "offset": 6,
+ "size": 1
+ },
+ "MWID": {
+ "description": "MWID",
+ "offset": 4,
+ "size": 2
+ },
+ "MTYP": {
+ "description": "MTYP",
+ "offset": 2,
+ "size": 2
+ },
+ "MUXEN": {
+ "description": "MUXEN",
+ "offset": 1,
+ "size": 1
+ },
+ "MBKEN": {
+ "description": "MBKEN",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BTR3": {
+ "description": "SRAM/NOR-Flash chip-select timing register\n 3",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "BUSTURN": {
+ "description": "BUSTURN",
+ "offset": 16,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "BCR4": {
+ "description": "SRAM/NOR-Flash chip-select control register\n 4",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 12496,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CBURSTRW": {
+ "description": "CBURSTRW",
+ "offset": 19,
+ "size": 1
+ },
+ "ASYNCWAIT": {
+ "description": "ASYNCWAIT",
+ "offset": 15,
+ "size": 1
+ },
+ "EXTMOD": {
+ "description": "EXTMOD",
+ "offset": 14,
+ "size": 1
+ },
+ "WAITEN": {
+ "description": "WAITEN",
+ "offset": 13,
+ "size": 1
+ },
+ "WREN": {
+ "description": "WREN",
+ "offset": 12,
+ "size": 1
+ },
+ "WAITCFG": {
+ "description": "WAITCFG",
+ "offset": 11,
+ "size": 1
+ },
+ "WRAPMOD": {
+ "description": "WRAPMOD",
+ "offset": 10,
+ "size": 1
+ },
+ "WAITPOL": {
+ "description": "WAITPOL",
+ "offset": 9,
+ "size": 1
+ },
+ "BURSTEN": {
+ "description": "BURSTEN",
+ "offset": 8,
+ "size": 1
+ },
+ "FACCEN": {
+ "description": "FACCEN",
+ "offset": 6,
+ "size": 1
+ },
+ "MWID": {
+ "description": "MWID",
+ "offset": 4,
+ "size": 2
+ },
+ "MTYP": {
+ "description": "MTYP",
+ "offset": 2,
+ "size": 2
+ },
+ "MUXEN": {
+ "description": "MUXEN",
+ "offset": 1,
+ "size": 1
+ },
+ "MBKEN": {
+ "description": "MBKEN",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BTR4": {
+ "description": "SRAM/NOR-Flash chip-select timing register\n 4",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "BUSTURN": {
+ "description": "BUSTURN",
+ "offset": 16,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "PCR2": {
+ "description": "PC Card/NAND Flash control register\n 2",
+ "offset": 96,
+ "size": 32,
+ "reset_value": 24,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ECCPS": {
+ "description": "ECCPS",
+ "offset": 17,
+ "size": 3
+ },
+ "TAR": {
+ "description": "TAR",
+ "offset": 13,
+ "size": 4
+ },
+ "TCLR": {
+ "description": "TCLR",
+ "offset": 9,
+ "size": 4
+ },
+ "ECCEN": {
+ "description": "ECCEN",
+ "offset": 6,
+ "size": 1
+ },
+ "PWID": {
+ "description": "PWID",
+ "offset": 4,
+ "size": 2
+ },
+ "PTYP": {
+ "description": "PTYP",
+ "offset": 3,
+ "size": 1
+ },
+ "PBKEN": {
+ "description": "PBKEN",
+ "offset": 2,
+ "size": 1
+ },
+ "PWAITEN": {
+ "description": "PWAITEN",
+ "offset": 1,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR2": {
+ "description": "FIFO status and interrupt register\n 2",
+ "offset": 100,
+ "size": 32,
+ "reset_value": 64,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEMPT": {
+ "description": "FEMPT",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "IFEN": {
+ "description": "IFEN",
+ "offset": 5,
+ "size": 1
+ },
+ "ILEN": {
+ "description": "ILEN",
+ "offset": 4,
+ "size": 1
+ },
+ "IREN": {
+ "description": "IREN",
+ "offset": 3,
+ "size": 1
+ },
+ "IFS": {
+ "description": "IFS",
+ "offset": 2,
+ "size": 1
+ },
+ "ILS": {
+ "description": "ILS",
+ "offset": 1,
+ "size": 1
+ },
+ "IRS": {
+ "description": "IRS",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PMEM2": {
+ "description": "Common memory space timing register\n 2",
+ "offset": 104,
+ "size": 32,
+ "reset_value": 4244438268,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MEMHIZx": {
+ "description": "MEMHIZx",
+ "offset": 24,
+ "size": 8
+ },
+ "MEMHOLDx": {
+ "description": "MEMHOLDx",
+ "offset": 16,
+ "size": 8
+ },
+ "MEMWAITx": {
+ "description": "MEMWAITx",
+ "offset": 8,
+ "size": 8
+ },
+ "MEMSETx": {
+ "description": "MEMSETx",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "PATT2": {
+ "description": "Attribute memory space timing register\n 2",
+ "offset": 108,
+ "size": 32,
+ "reset_value": 4244438268,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ATTHIZx": {
+ "description": "ATTHIZx",
+ "offset": 24,
+ "size": 8
+ },
+ "ATTHOLDx": {
+ "description": "ATTHOLDx",
+ "offset": 16,
+ "size": 8
+ },
+ "ATTWAITx": {
+ "description": "ATTWAITx",
+ "offset": 8,
+ "size": 8
+ },
+ "ATTSETx": {
+ "description": "ATTSETx",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "ECCR2": {
+ "description": "ECC result register 2",
+ "offset": 116,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "ECCx": {
+ "description": "ECCx",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "PCR3": {
+ "description": "PC Card/NAND Flash control register\n 3",
+ "offset": 128,
+ "size": 32,
+ "reset_value": 24,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ECCPS": {
+ "description": "ECCPS",
+ "offset": 17,
+ "size": 3
+ },
+ "TAR": {
+ "description": "TAR",
+ "offset": 13,
+ "size": 4
+ },
+ "TCLR": {
+ "description": "TCLR",
+ "offset": 9,
+ "size": 4
+ },
+ "ECCEN": {
+ "description": "ECCEN",
+ "offset": 6,
+ "size": 1
+ },
+ "PWID": {
+ "description": "PWID",
+ "offset": 4,
+ "size": 2
+ },
+ "PTYP": {
+ "description": "PTYP",
+ "offset": 3,
+ "size": 1
+ },
+ "PBKEN": {
+ "description": "PBKEN",
+ "offset": 2,
+ "size": 1
+ },
+ "PWAITEN": {
+ "description": "PWAITEN",
+ "offset": 1,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR3": {
+ "description": "FIFO status and interrupt register\n 3",
+ "offset": 132,
+ "size": 32,
+ "reset_value": 64,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEMPT": {
+ "description": "FEMPT",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "IFEN": {
+ "description": "IFEN",
+ "offset": 5,
+ "size": 1
+ },
+ "ILEN": {
+ "description": "ILEN",
+ "offset": 4,
+ "size": 1
+ },
+ "IREN": {
+ "description": "IREN",
+ "offset": 3,
+ "size": 1
+ },
+ "IFS": {
+ "description": "IFS",
+ "offset": 2,
+ "size": 1
+ },
+ "ILS": {
+ "description": "ILS",
+ "offset": 1,
+ "size": 1
+ },
+ "IRS": {
+ "description": "IRS",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PMEM3": {
+ "description": "Common memory space timing register\n 3",
+ "offset": 136,
+ "size": 32,
+ "reset_value": 4244438268,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MEMHIZx": {
+ "description": "MEMHIZx",
+ "offset": 24,
+ "size": 8
+ },
+ "MEMHOLDx": {
+ "description": "MEMHOLDx",
+ "offset": 16,
+ "size": 8
+ },
+ "MEMWAITx": {
+ "description": "MEMWAITx",
+ "offset": 8,
+ "size": 8
+ },
+ "MEMSETx": {
+ "description": "MEMSETx",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "PATT3": {
+ "description": "Attribute memory space timing register\n 3",
+ "offset": 140,
+ "size": 32,
+ "reset_value": 4244438268,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ATTHIZx": {
+ "description": "ATTHIZx",
+ "offset": 24,
+ "size": 8
+ },
+ "ATTHOLDx": {
+ "description": "ATTHOLDx",
+ "offset": 16,
+ "size": 8
+ },
+ "ATTWAITx": {
+ "description": "ATTWAITx",
+ "offset": 8,
+ "size": 8
+ },
+ "ATTSETx": {
+ "description": "ATTSETx",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "ECCR3": {
+ "description": "ECC result register 3",
+ "offset": 148,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "ECCx": {
+ "description": "ECCx",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "PCR4": {
+ "description": "PC Card/NAND Flash control register\n 4",
+ "offset": 160,
+ "size": 32,
+ "reset_value": 24,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ECCPS": {
+ "description": "ECCPS",
+ "offset": 17,
+ "size": 3
+ },
+ "TAR": {
+ "description": "TAR",
+ "offset": 13,
+ "size": 4
+ },
+ "TCLR": {
+ "description": "TCLR",
+ "offset": 9,
+ "size": 4
+ },
+ "ECCEN": {
+ "description": "ECCEN",
+ "offset": 6,
+ "size": 1
+ },
+ "PWID": {
+ "description": "PWID",
+ "offset": 4,
+ "size": 2
+ },
+ "PTYP": {
+ "description": "PTYP",
+ "offset": 3,
+ "size": 1
+ },
+ "PBKEN": {
+ "description": "PBKEN",
+ "offset": 2,
+ "size": 1
+ },
+ "PWAITEN": {
+ "description": "PWAITEN",
+ "offset": 1,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR4": {
+ "description": "FIFO status and interrupt register\n 4",
+ "offset": 164,
+ "size": 32,
+ "reset_value": 64,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEMPT": {
+ "description": "FEMPT",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "IFEN": {
+ "description": "IFEN",
+ "offset": 5,
+ "size": 1
+ },
+ "ILEN": {
+ "description": "ILEN",
+ "offset": 4,
+ "size": 1
+ },
+ "IREN": {
+ "description": "IREN",
+ "offset": 3,
+ "size": 1
+ },
+ "IFS": {
+ "description": "IFS",
+ "offset": 2,
+ "size": 1
+ },
+ "ILS": {
+ "description": "ILS",
+ "offset": 1,
+ "size": 1
+ },
+ "IRS": {
+ "description": "IRS",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PMEM4": {
+ "description": "Common memory space timing register\n 4",
+ "offset": 168,
+ "size": 32,
+ "reset_value": 4244438268,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MEMHIZx": {
+ "description": "MEMHIZx",
+ "offset": 24,
+ "size": 8
+ },
+ "MEMHOLDx": {
+ "description": "MEMHOLDx",
+ "offset": 16,
+ "size": 8
+ },
+ "MEMWAITx": {
+ "description": "MEMWAITx",
+ "offset": 8,
+ "size": 8
+ },
+ "MEMSETx": {
+ "description": "MEMSETx",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "PATT4": {
+ "description": "Attribute memory space timing register\n 4",
+ "offset": 172,
+ "size": 32,
+ "reset_value": 4244438268,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ATTHIZx": {
+ "description": "ATTHIZx",
+ "offset": 24,
+ "size": 8
+ },
+ "ATTHOLDx": {
+ "description": "ATTHOLDx",
+ "offset": 16,
+ "size": 8
+ },
+ "ATTWAITx": {
+ "description": "ATTWAITx",
+ "offset": 8,
+ "size": 8
+ },
+ "ATTSETx": {
+ "description": "ATTSETx",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "PIO4": {
+ "description": "I/O space timing register 4",
+ "offset": 176,
+ "size": 32,
+ "reset_value": 4244438268,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IOHIZx": {
+ "description": "IOHIZx",
+ "offset": 24,
+ "size": 8
+ },
+ "IOHOLDx": {
+ "description": "IOHOLDx",
+ "offset": 16,
+ "size": 8
+ },
+ "IOWAITx": {
+ "description": "IOWAITx",
+ "offset": 8,
+ "size": 8
+ },
+ "IOSETx": {
+ "description": "IOSETx",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "BWTR1": {
+ "description": "SRAM/NOR-Flash write timing registers\n 1",
+ "offset": 260,
+ "size": 32,
+ "reset_value": 268435455,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "BWTR2": {
+ "description": "SRAM/NOR-Flash write timing registers\n 2",
+ "offset": 268,
+ "size": 32,
+ "reset_value": 268435455,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "BWTR3": {
+ "description": "SRAM/NOR-Flash write timing registers\n 3",
+ "offset": 276,
+ "size": 32,
+ "reset_value": 268435455,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "BWTR4": {
+ "description": "SRAM/NOR-Flash write timing registers\n 4",
+ "offset": 284,
+ "size": 32,
+ "reset_value": 268435455,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "DBG": {
+ "description": "Debug support",
+ "children": {
+ "registers": {
+ "DBGMCU_IDCODE": {
+ "description": "IDCODE",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 268461073,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DEV_ID": {
+ "description": "DEV_ID",
+ "offset": 0,
+ "size": 12
+ },
+ "REV_ID": {
+ "description": "REV_ID",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DBGMCU_CR": {
+ "description": "Control Register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBG_SLEEP": {
+ "description": "DBG_SLEEP",
+ "offset": 0,
+ "size": 1
+ },
+ "DBG_STOP": {
+ "description": "DBG_STOP",
+ "offset": 1,
+ "size": 1
+ },
+ "DBG_STANDBY": {
+ "description": "DBG_STANDBY",
+ "offset": 2,
+ "size": 1
+ },
+ "TRACE_IOEN": {
+ "description": "TRACE_IOEN",
+ "offset": 5,
+ "size": 1
+ },
+ "TRACE_MODE": {
+ "description": "TRACE_MODE",
+ "offset": 6,
+ "size": 2
+ },
+ "DBG_I2C2_SMBUS_TIMEOUT": {
+ "description": "DBG_I2C2_SMBUS_TIMEOUT",
+ "offset": 16,
+ "size": 1
+ },
+ "DBG_TIM8_STOP": {
+ "description": "DBG_TIM8_STOP",
+ "offset": 17,
+ "size": 1
+ },
+ "DBG_TIM5_STOP": {
+ "description": "DBG_TIM5_STOP",
+ "offset": 18,
+ "size": 1
+ },
+ "DBG_TIM6_STOP": {
+ "description": "DBG_TIM6_STOP",
+ "offset": 19,
+ "size": 1
+ },
+ "DBG_TIM7_STOP": {
+ "description": "DBG_TIM7_STOP",
+ "offset": 20,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DBGMCU_APB1_FZ": {
+ "description": "Debug MCU APB1 Freeze registe",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBG_TIM2_STOP": {
+ "description": "DBG_TIM2_STOP",
+ "offset": 0,
+ "size": 1
+ },
+ "DBG_TIM3_STOP": {
+ "description": "DBG_TIM3 _STOP",
+ "offset": 1,
+ "size": 1
+ },
+ "DBG_TIM4_STOP": {
+ "description": "DBG_TIM4_STOP",
+ "offset": 2,
+ "size": 1
+ },
+ "DBG_TIM5_STOP": {
+ "description": "DBG_TIM5_STOP",
+ "offset": 3,
+ "size": 1
+ },
+ "DBG_TIM6_STOP": {
+ "description": "DBG_TIM6_STOP",
+ "offset": 4,
+ "size": 1
+ },
+ "DBG_TIM7_STOP": {
+ "description": "DBG_TIM7_STOP",
+ "offset": 5,
+ "size": 1
+ },
+ "DBG_TIM12_STOP": {
+ "description": "DBG_TIM12_STOP",
+ "offset": 6,
+ "size": 1
+ },
+ "DBG_TIM13_STOP": {
+ "description": "DBG_TIM13_STOP",
+ "offset": 7,
+ "size": 1
+ },
+ "DBG_TIM14_STOP": {
+ "description": "DBG_TIM14_STOP",
+ "offset": 8,
+ "size": 1
+ },
+ "DBG_WWDG_STOP": {
+ "description": "DBG_WWDG_STOP",
+ "offset": 11,
+ "size": 1
+ },
+ "DBG_IWDEG_STOP": {
+ "description": "DBG_IWDEG_STOP",
+ "offset": 12,
+ "size": 1
+ },
+ "DBG_J2C1_SMBUS_TIMEOUT": {
+ "description": "DBG_J2C1_SMBUS_TIMEOUT",
+ "offset": 21,
+ "size": 1
+ },
+ "DBG_J2C2_SMBUS_TIMEOUT": {
+ "description": "DBG_J2C2_SMBUS_TIMEOUT",
+ "offset": 22,
+ "size": 1
+ },
+ "DBG_J2C3SMBUS_TIMEOUT": {
+ "description": "DBG_J2C3SMBUS_TIMEOUT",
+ "offset": 23,
+ "size": 1
+ },
+ "DBG_CAN1_STOP": {
+ "description": "DBG_CAN1_STOP",
+ "offset": 25,
+ "size": 1
+ },
+ "DBG_CAN2_STOP": {
+ "description": "DBG_CAN2_STOP",
+ "offset": 26,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DBGMCU_APB2_FZ": {
+ "description": "Debug MCU APB2 Freeze registe",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBG_TIM1_STOP": {
+ "description": "TIM1 counter stopped when core is\n halted",
+ "offset": 0,
+ "size": 1
+ },
+ "DBG_TIM8_STOP": {
+ "description": "TIM8 counter stopped when core is\n halted",
+ "offset": 1,
+ "size": 1
+ },
+ "DBG_TIM9_STOP": {
+ "description": "TIM9 counter stopped when core is\n halted",
+ "offset": 16,
+ "size": 1
+ },
+ "DBG_TIM10_STOP": {
+ "description": "TIM10 counter stopped when core is\n halted",
+ "offset": 17,
+ "size": 1
+ },
+ "DBG_TIM11_STOP": {
+ "description": "TIM11 counter stopped when core is\n halted",
+ "offset": 18,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "DMA2": {
+ "description": "DMA controller",
+ "children": {
+ "registers": {
+ "LISR": {
+ "description": "low interrupt status register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "TCIF3": {
+ "description": "Stream x transfer complete interrupt\n flag (x = 3..0)",
+ "offset": 27,
+ "size": 1
+ },
+ "HTIF3": {
+ "description": "Stream x half transfer interrupt flag\n (x=3..0)",
+ "offset": 26,
+ "size": 1
+ },
+ "TEIF3": {
+ "description": "Stream x transfer error interrupt flag\n (x=3..0)",
+ "offset": 25,
+ "size": 1
+ },
+ "DMEIF3": {
+ "description": "Stream x direct mode error interrupt\n flag (x=3..0)",
+ "offset": 24,
+ "size": 1
+ },
+ "FEIF3": {
+ "description": "Stream x FIFO error interrupt flag\n (x=3..0)",
+ "offset": 22,
+ "size": 1
+ },
+ "TCIF2": {
+ "description": "Stream x transfer complete interrupt\n flag (x = 3..0)",
+ "offset": 21,
+ "size": 1
+ },
+ "HTIF2": {
+ "description": "Stream x half transfer interrupt flag\n (x=3..0)",
+ "offset": 20,
+ "size": 1
+ },
+ "TEIF2": {
+ "description": "Stream x transfer error interrupt flag\n (x=3..0)",
+ "offset": 19,
+ "size": 1
+ },
+ "DMEIF2": {
+ "description": "Stream x direct mode error interrupt\n flag (x=3..0)",
+ "offset": 18,
+ "size": 1
+ },
+ "FEIF2": {
+ "description": "Stream x FIFO error interrupt flag\n (x=3..0)",
+ "offset": 16,
+ "size": 1
+ },
+ "TCIF1": {
+ "description": "Stream x transfer complete interrupt\n flag (x = 3..0)",
+ "offset": 11,
+ "size": 1
+ },
+ "HTIF1": {
+ "description": "Stream x half transfer interrupt flag\n (x=3..0)",
+ "offset": 10,
+ "size": 1
+ },
+ "TEIF1": {
+ "description": "Stream x transfer error interrupt flag\n (x=3..0)",
+ "offset": 9,
+ "size": 1
+ },
+ "DMEIF1": {
+ "description": "Stream x direct mode error interrupt\n flag (x=3..0)",
+ "offset": 8,
+ "size": 1
+ },
+ "FEIF1": {
+ "description": "Stream x FIFO error interrupt flag\n (x=3..0)",
+ "offset": 6,
+ "size": 1
+ },
+ "TCIF0": {
+ "description": "Stream x transfer complete interrupt\n flag (x = 3..0)",
+ "offset": 5,
+ "size": 1
+ },
+ "HTIF0": {
+ "description": "Stream x half transfer interrupt flag\n (x=3..0)",
+ "offset": 4,
+ "size": 1
+ },
+ "TEIF0": {
+ "description": "Stream x transfer error interrupt flag\n (x=3..0)",
+ "offset": 3,
+ "size": 1
+ },
+ "DMEIF0": {
+ "description": "Stream x direct mode error interrupt\n flag (x=3..0)",
+ "offset": 2,
+ "size": 1
+ },
+ "FEIF0": {
+ "description": "Stream x FIFO error interrupt flag\n (x=3..0)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "HISR": {
+ "description": "high interrupt status register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "TCIF7": {
+ "description": "Stream x transfer complete interrupt\n flag (x=7..4)",
+ "offset": 27,
+ "size": 1
+ },
+ "HTIF7": {
+ "description": "Stream x half transfer interrupt flag\n (x=7..4)",
+ "offset": 26,
+ "size": 1
+ },
+ "TEIF7": {
+ "description": "Stream x transfer error interrupt flag\n (x=7..4)",
+ "offset": 25,
+ "size": 1
+ },
+ "DMEIF7": {
+ "description": "Stream x direct mode error interrupt\n flag (x=7..4)",
+ "offset": 24,
+ "size": 1
+ },
+ "FEIF7": {
+ "description": "Stream x FIFO error interrupt flag\n (x=7..4)",
+ "offset": 22,
+ "size": 1
+ },
+ "TCIF6": {
+ "description": "Stream x transfer complete interrupt\n flag (x=7..4)",
+ "offset": 21,
+ "size": 1
+ },
+ "HTIF6": {
+ "description": "Stream x half transfer interrupt flag\n (x=7..4)",
+ "offset": 20,
+ "size": 1
+ },
+ "TEIF6": {
+ "description": "Stream x transfer error interrupt flag\n (x=7..4)",
+ "offset": 19,
+ "size": 1
+ },
+ "DMEIF6": {
+ "description": "Stream x direct mode error interrupt\n flag (x=7..4)",
+ "offset": 18,
+ "size": 1
+ },
+ "FEIF6": {
+ "description": "Stream x FIFO error interrupt flag\n (x=7..4)",
+ "offset": 16,
+ "size": 1
+ },
+ "TCIF5": {
+ "description": "Stream x transfer complete interrupt\n flag (x=7..4)",
+ "offset": 11,
+ "size": 1
+ },
+ "HTIF5": {
+ "description": "Stream x half transfer interrupt flag\n (x=7..4)",
+ "offset": 10,
+ "size": 1
+ },
+ "TEIF5": {
+ "description": "Stream x transfer error interrupt flag\n (x=7..4)",
+ "offset": 9,
+ "size": 1
+ },
+ "DMEIF5": {
+ "description": "Stream x direct mode error interrupt\n flag (x=7..4)",
+ "offset": 8,
+ "size": 1
+ },
+ "FEIF5": {
+ "description": "Stream x FIFO error interrupt flag\n (x=7..4)",
+ "offset": 6,
+ "size": 1
+ },
+ "TCIF4": {
+ "description": "Stream x transfer complete interrupt\n flag (x=7..4)",
+ "offset": 5,
+ "size": 1
+ },
+ "HTIF4": {
+ "description": "Stream x half transfer interrupt flag\n (x=7..4)",
+ "offset": 4,
+ "size": 1
+ },
+ "TEIF4": {
+ "description": "Stream x transfer error interrupt flag\n (x=7..4)",
+ "offset": 3,
+ "size": 1
+ },
+ "DMEIF4": {
+ "description": "Stream x direct mode error interrupt\n flag (x=7..4)",
+ "offset": 2,
+ "size": 1
+ },
+ "FEIF4": {
+ "description": "Stream x FIFO error interrupt flag\n (x=7..4)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "LIFCR": {
+ "description": "low interrupt flag clear\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CTCIF3": {
+ "description": "Stream x clear transfer complete\n interrupt flag (x = 3..0)",
+ "offset": 27,
+ "size": 1
+ },
+ "CHTIF3": {
+ "description": "Stream x clear half transfer interrupt\n flag (x = 3..0)",
+ "offset": 26,
+ "size": 1
+ },
+ "CTEIF3": {
+ "description": "Stream x clear transfer error interrupt\n flag (x = 3..0)",
+ "offset": 25,
+ "size": 1
+ },
+ "CDMEIF3": {
+ "description": "Stream x clear direct mode error\n interrupt flag (x = 3..0)",
+ "offset": 24,
+ "size": 1
+ },
+ "CFEIF3": {
+ "description": "Stream x clear FIFO error interrupt flag\n (x = 3..0)",
+ "offset": 22,
+ "size": 1
+ },
+ "CTCIF2": {
+ "description": "Stream x clear transfer complete\n interrupt flag (x = 3..0)",
+ "offset": 21,
+ "size": 1
+ },
+ "CHTIF2": {
+ "description": "Stream x clear half transfer interrupt\n flag (x = 3..0)",
+ "offset": 20,
+ "size": 1
+ },
+ "CTEIF2": {
+ "description": "Stream x clear transfer error interrupt\n flag (x = 3..0)",
+ "offset": 19,
+ "size": 1
+ },
+ "CDMEIF2": {
+ "description": "Stream x clear direct mode error\n interrupt flag (x = 3..0)",
+ "offset": 18,
+ "size": 1
+ },
+ "CFEIF2": {
+ "description": "Stream x clear FIFO error interrupt flag\n (x = 3..0)",
+ "offset": 16,
+ "size": 1
+ },
+ "CTCIF1": {
+ "description": "Stream x clear transfer complete\n interrupt flag (x = 3..0)",
+ "offset": 11,
+ "size": 1
+ },
+ "CHTIF1": {
+ "description": "Stream x clear half transfer interrupt\n flag (x = 3..0)",
+ "offset": 10,
+ "size": 1
+ },
+ "CTEIF1": {
+ "description": "Stream x clear transfer error interrupt\n flag (x = 3..0)",
+ "offset": 9,
+ "size": 1
+ },
+ "CDMEIF1": {
+ "description": "Stream x clear direct mode error\n interrupt flag (x = 3..0)",
+ "offset": 8,
+ "size": 1
+ },
+ "CFEIF1": {
+ "description": "Stream x clear FIFO error interrupt flag\n (x = 3..0)",
+ "offset": 6,
+ "size": 1
+ },
+ "CTCIF0": {
+ "description": "Stream x clear transfer complete\n interrupt flag (x = 3..0)",
+ "offset": 5,
+ "size": 1
+ },
+ "CHTIF0": {
+ "description": "Stream x clear half transfer interrupt\n flag (x = 3..0)",
+ "offset": 4,
+ "size": 1
+ },
+ "CTEIF0": {
+ "description": "Stream x clear transfer error interrupt\n flag (x = 3..0)",
+ "offset": 3,
+ "size": 1
+ },
+ "CDMEIF0": {
+ "description": "Stream x clear direct mode error\n interrupt flag (x = 3..0)",
+ "offset": 2,
+ "size": 1
+ },
+ "CFEIF0": {
+ "description": "Stream x clear FIFO error interrupt flag\n (x = 3..0)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "HIFCR": {
+ "description": "high interrupt flag clear\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CTCIF7": {
+ "description": "Stream x clear transfer complete\n interrupt flag (x = 7..4)",
+ "offset": 27,
+ "size": 1
+ },
+ "CHTIF7": {
+ "description": "Stream x clear half transfer interrupt\n flag (x = 7..4)",
+ "offset": 26,
+ "size": 1
+ },
+ "CTEIF7": {
+ "description": "Stream x clear transfer error interrupt\n flag (x = 7..4)",
+ "offset": 25,
+ "size": 1
+ },
+ "CDMEIF7": {
+ "description": "Stream x clear direct mode error\n interrupt flag (x = 7..4)",
+ "offset": 24,
+ "size": 1
+ },
+ "CFEIF7": {
+ "description": "Stream x clear FIFO error interrupt flag\n (x = 7..4)",
+ "offset": 22,
+ "size": 1
+ },
+ "CTCIF6": {
+ "description": "Stream x clear transfer complete\n interrupt flag (x = 7..4)",
+ "offset": 21,
+ "size": 1
+ },
+ "CHTIF6": {
+ "description": "Stream x clear half transfer interrupt\n flag (x = 7..4)",
+ "offset": 20,
+ "size": 1
+ },
+ "CTEIF6": {
+ "description": "Stream x clear transfer error interrupt\n flag (x = 7..4)",
+ "offset": 19,
+ "size": 1
+ },
+ "CDMEIF6": {
+ "description": "Stream x clear direct mode error\n interrupt flag (x = 7..4)",
+ "offset": 18,
+ "size": 1
+ },
+ "CFEIF6": {
+ "description": "Stream x clear FIFO error interrupt flag\n (x = 7..4)",
+ "offset": 16,
+ "size": 1
+ },
+ "CTCIF5": {
+ "description": "Stream x clear transfer complete\n interrupt flag (x = 7..4)",
+ "offset": 11,
+ "size": 1
+ },
+ "CHTIF5": {
+ "description": "Stream x clear half transfer interrupt\n flag (x = 7..4)",
+ "offset": 10,
+ "size": 1
+ },
+ "CTEIF5": {
+ "description": "Stream x clear transfer error interrupt\n flag (x = 7..4)",
+ "offset": 9,
+ "size": 1
+ },
+ "CDMEIF5": {
+ "description": "Stream x clear direct mode error\n interrupt flag (x = 7..4)",
+ "offset": 8,
+ "size": 1
+ },
+ "CFEIF5": {
+ "description": "Stream x clear FIFO error interrupt flag\n (x = 7..4)",
+ "offset": 6,
+ "size": 1
+ },
+ "CTCIF4": {
+ "description": "Stream x clear transfer complete\n interrupt flag (x = 7..4)",
+ "offset": 5,
+ "size": 1
+ },
+ "CHTIF4": {
+ "description": "Stream x clear half transfer interrupt\n flag (x = 7..4)",
+ "offset": 4,
+ "size": 1
+ },
+ "CTEIF4": {
+ "description": "Stream x clear transfer error interrupt\n flag (x = 7..4)",
+ "offset": 3,
+ "size": 1
+ },
+ "CDMEIF4": {
+ "description": "Stream x clear direct mode error\n interrupt flag (x = 7..4)",
+ "offset": 2,
+ "size": 1
+ },
+ "CFEIF4": {
+ "description": "Stream x clear FIFO error interrupt flag\n (x = 7..4)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "S0CR": {
+ "description": "stream x configuration\n register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CHSEL": {
+ "description": "Channel selection",
+ "offset": 25,
+ "size": 3
+ },
+ "MBURST": {
+ "description": "Memory burst transfer\n configuration",
+ "offset": 23,
+ "size": 2
+ },
+ "PBURST": {
+ "description": "Peripheral burst transfer\n configuration",
+ "offset": 21,
+ "size": 2
+ },
+ "CT": {
+ "description": "Current target (only in double buffer\n mode)",
+ "offset": 19,
+ "size": 1
+ },
+ "DBM": {
+ "description": "Double buffer mode",
+ "offset": 18,
+ "size": 1
+ },
+ "PL": {
+ "description": "Priority level",
+ "offset": 16,
+ "size": 2
+ },
+ "PINCOS": {
+ "description": "Peripheral increment offset\n size",
+ "offset": 15,
+ "size": 1
+ },
+ "MSIZE": {
+ "description": "Memory data size",
+ "offset": 13,
+ "size": 2
+ },
+ "PSIZE": {
+ "description": "Peripheral data size",
+ "offset": 11,
+ "size": 2
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 10,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 9,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 8,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 6,
+ "size": 2
+ },
+ "PFCTRL": {
+ "description": "Peripheral flow controller",
+ "offset": 5,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half transfer interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "DMEIE": {
+ "description": "Direct mode error interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "EN": {
+ "description": "Stream enable / flag stream ready when\n read low",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "S0NDTR": {
+ "description": "stream x number of data\n register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data items to\n transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "S0PAR": {
+ "description": "stream x peripheral address\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S0M0AR": {
+ "description": "stream x memory 0 address\n register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M0A": {
+ "description": "Memory 0 address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S0M1AR": {
+ "description": "stream x memory 1 address\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M1A": {
+ "description": "Memory 1 address (used in case of Double\n buffer mode)",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S0FCR": {
+ "description": "stream x FIFO control register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 33,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEIE": {
+ "description": "FIFO error interrupt\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "FS": {
+ "description": "FIFO status",
+ "offset": 3,
+ "size": 3,
+ "access": "read-only"
+ },
+ "DMDIS": {
+ "description": "Direct mode disable",
+ "offset": 2,
+ "size": 1
+ },
+ "FTH": {
+ "description": "FIFO threshold selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "S1CR": {
+ "description": "stream x configuration\n register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CHSEL": {
+ "description": "Channel selection",
+ "offset": 25,
+ "size": 3
+ },
+ "MBURST": {
+ "description": "Memory burst transfer\n configuration",
+ "offset": 23,
+ "size": 2
+ },
+ "PBURST": {
+ "description": "Peripheral burst transfer\n configuration",
+ "offset": 21,
+ "size": 2
+ },
+ "ACK": {
+ "description": "ACK",
+ "offset": 20,
+ "size": 1
+ },
+ "CT": {
+ "description": "Current target (only in double buffer\n mode)",
+ "offset": 19,
+ "size": 1
+ },
+ "DBM": {
+ "description": "Double buffer mode",
+ "offset": 18,
+ "size": 1
+ },
+ "PL": {
+ "description": "Priority level",
+ "offset": 16,
+ "size": 2
+ },
+ "PINCOS": {
+ "description": "Peripheral increment offset\n size",
+ "offset": 15,
+ "size": 1
+ },
+ "MSIZE": {
+ "description": "Memory data size",
+ "offset": 13,
+ "size": 2
+ },
+ "PSIZE": {
+ "description": "Peripheral data size",
+ "offset": 11,
+ "size": 2
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 10,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 9,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 8,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 6,
+ "size": 2
+ },
+ "PFCTRL": {
+ "description": "Peripheral flow controller",
+ "offset": 5,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half transfer interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "DMEIE": {
+ "description": "Direct mode error interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "EN": {
+ "description": "Stream enable / flag stream ready when\n read low",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "S1NDTR": {
+ "description": "stream x number of data\n register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data items to\n transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "S1PAR": {
+ "description": "stream x peripheral address\n register",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S1M0AR": {
+ "description": "stream x memory 0 address\n register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M0A": {
+ "description": "Memory 0 address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S1M1AR": {
+ "description": "stream x memory 1 address\n register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M1A": {
+ "description": "Memory 1 address (used in case of Double\n buffer mode)",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S1FCR": {
+ "description": "stream x FIFO control register",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 33,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEIE": {
+ "description": "FIFO error interrupt\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "FS": {
+ "description": "FIFO status",
+ "offset": 3,
+ "size": 3,
+ "access": "read-only"
+ },
+ "DMDIS": {
+ "description": "Direct mode disable",
+ "offset": 2,
+ "size": 1
+ },
+ "FTH": {
+ "description": "FIFO threshold selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "S2CR": {
+ "description": "stream x configuration\n register",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CHSEL": {
+ "description": "Channel selection",
+ "offset": 25,
+ "size": 3
+ },
+ "MBURST": {
+ "description": "Memory burst transfer\n configuration",
+ "offset": 23,
+ "size": 2
+ },
+ "PBURST": {
+ "description": "Peripheral burst transfer\n configuration",
+ "offset": 21,
+ "size": 2
+ },
+ "ACK": {
+ "description": "ACK",
+ "offset": 20,
+ "size": 1
+ },
+ "CT": {
+ "description": "Current target (only in double buffer\n mode)",
+ "offset": 19,
+ "size": 1
+ },
+ "DBM": {
+ "description": "Double buffer mode",
+ "offset": 18,
+ "size": 1
+ },
+ "PL": {
+ "description": "Priority level",
+ "offset": 16,
+ "size": 2
+ },
+ "PINCOS": {
+ "description": "Peripheral increment offset\n size",
+ "offset": 15,
+ "size": 1
+ },
+ "MSIZE": {
+ "description": "Memory data size",
+ "offset": 13,
+ "size": 2
+ },
+ "PSIZE": {
+ "description": "Peripheral data size",
+ "offset": 11,
+ "size": 2
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 10,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 9,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 8,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 6,
+ "size": 2
+ },
+ "PFCTRL": {
+ "description": "Peripheral flow controller",
+ "offset": 5,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half transfer interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "DMEIE": {
+ "description": "Direct mode error interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "EN": {
+ "description": "Stream enable / flag stream ready when\n read low",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "S2NDTR": {
+ "description": "stream x number of data\n register",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data items to\n transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "S2PAR": {
+ "description": "stream x peripheral address\n register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S2M0AR": {
+ "description": "stream x memory 0 address\n register",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M0A": {
+ "description": "Memory 0 address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S2M1AR": {
+ "description": "stream x memory 1 address\n register",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M1A": {
+ "description": "Memory 1 address (used in case of Double\n buffer mode)",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S2FCR": {
+ "description": "stream x FIFO control register",
+ "offset": 84,
+ "size": 32,
+ "reset_value": 33,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEIE": {
+ "description": "FIFO error interrupt\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "FS": {
+ "description": "FIFO status",
+ "offset": 3,
+ "size": 3,
+ "access": "read-only"
+ },
+ "DMDIS": {
+ "description": "Direct mode disable",
+ "offset": 2,
+ "size": 1
+ },
+ "FTH": {
+ "description": "FIFO threshold selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "S3CR": {
+ "description": "stream x configuration\n register",
+ "offset": 88,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CHSEL": {
+ "description": "Channel selection",
+ "offset": 25,
+ "size": 3
+ },
+ "MBURST": {
+ "description": "Memory burst transfer\n configuration",
+ "offset": 23,
+ "size": 2
+ },
+ "PBURST": {
+ "description": "Peripheral burst transfer\n configuration",
+ "offset": 21,
+ "size": 2
+ },
+ "ACK": {
+ "description": "ACK",
+ "offset": 20,
+ "size": 1
+ },
+ "CT": {
+ "description": "Current target (only in double buffer\n mode)",
+ "offset": 19,
+ "size": 1
+ },
+ "DBM": {
+ "description": "Double buffer mode",
+ "offset": 18,
+ "size": 1
+ },
+ "PL": {
+ "description": "Priority level",
+ "offset": 16,
+ "size": 2
+ },
+ "PINCOS": {
+ "description": "Peripheral increment offset\n size",
+ "offset": 15,
+ "size": 1
+ },
+ "MSIZE": {
+ "description": "Memory data size",
+ "offset": 13,
+ "size": 2
+ },
+ "PSIZE": {
+ "description": "Peripheral data size",
+ "offset": 11,
+ "size": 2
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 10,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 9,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 8,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 6,
+ "size": 2
+ },
+ "PFCTRL": {
+ "description": "Peripheral flow controller",
+ "offset": 5,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half transfer interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "DMEIE": {
+ "description": "Direct mode error interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "EN": {
+ "description": "Stream enable / flag stream ready when\n read low",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "S3NDTR": {
+ "description": "stream x number of data\n register",
+ "offset": 92,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data items to\n transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "S3PAR": {
+ "description": "stream x peripheral address\n register",
+ "offset": 96,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S3M0AR": {
+ "description": "stream x memory 0 address\n register",
+ "offset": 100,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M0A": {
+ "description": "Memory 0 address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S3M1AR": {
+ "description": "stream x memory 1 address\n register",
+ "offset": 104,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M1A": {
+ "description": "Memory 1 address (used in case of Double\n buffer mode)",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S3FCR": {
+ "description": "stream x FIFO control register",
+ "offset": 108,
+ "size": 32,
+ "reset_value": 33,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEIE": {
+ "description": "FIFO error interrupt\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "FS": {
+ "description": "FIFO status",
+ "offset": 3,
+ "size": 3,
+ "access": "read-only"
+ },
+ "DMDIS": {
+ "description": "Direct mode disable",
+ "offset": 2,
+ "size": 1
+ },
+ "FTH": {
+ "description": "FIFO threshold selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "S4CR": {
+ "description": "stream x configuration\n register",
+ "offset": 112,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CHSEL": {
+ "description": "Channel selection",
+ "offset": 25,
+ "size": 3
+ },
+ "MBURST": {
+ "description": "Memory burst transfer\n configuration",
+ "offset": 23,
+ "size": 2
+ },
+ "PBURST": {
+ "description": "Peripheral burst transfer\n configuration",
+ "offset": 21,
+ "size": 2
+ },
+ "ACK": {
+ "description": "ACK",
+ "offset": 20,
+ "size": 1
+ },
+ "CT": {
+ "description": "Current target (only in double buffer\n mode)",
+ "offset": 19,
+ "size": 1
+ },
+ "DBM": {
+ "description": "Double buffer mode",
+ "offset": 18,
+ "size": 1
+ },
+ "PL": {
+ "description": "Priority level",
+ "offset": 16,
+ "size": 2
+ },
+ "PINCOS": {
+ "description": "Peripheral increment offset\n size",
+ "offset": 15,
+ "size": 1
+ },
+ "MSIZE": {
+ "description": "Memory data size",
+ "offset": 13,
+ "size": 2
+ },
+ "PSIZE": {
+ "description": "Peripheral data size",
+ "offset": 11,
+ "size": 2
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 10,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 9,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 8,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 6,
+ "size": 2
+ },
+ "PFCTRL": {
+ "description": "Peripheral flow controller",
+ "offset": 5,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half transfer interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "DMEIE": {
+ "description": "Direct mode error interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "EN": {
+ "description": "Stream enable / flag stream ready when\n read low",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "S4NDTR": {
+ "description": "stream x number of data\n register",
+ "offset": 116,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data items to\n transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "S4PAR": {
+ "description": "stream x peripheral address\n register",
+ "offset": 120,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S4M0AR": {
+ "description": "stream x memory 0 address\n register",
+ "offset": 124,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M0A": {
+ "description": "Memory 0 address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S4M1AR": {
+ "description": "stream x memory 1 address\n register",
+ "offset": 128,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M1A": {
+ "description": "Memory 1 address (used in case of Double\n buffer mode)",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S4FCR": {
+ "description": "stream x FIFO control register",
+ "offset": 132,
+ "size": 32,
+ "reset_value": 33,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEIE": {
+ "description": "FIFO error interrupt\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "FS": {
+ "description": "FIFO status",
+ "offset": 3,
+ "size": 3,
+ "access": "read-only"
+ },
+ "DMDIS": {
+ "description": "Direct mode disable",
+ "offset": 2,
+ "size": 1
+ },
+ "FTH": {
+ "description": "FIFO threshold selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "S5CR": {
+ "description": "stream x configuration\n register",
+ "offset": 136,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CHSEL": {
+ "description": "Channel selection",
+ "offset": 25,
+ "size": 3
+ },
+ "MBURST": {
+ "description": "Memory burst transfer\n configuration",
+ "offset": 23,
+ "size": 2
+ },
+ "PBURST": {
+ "description": "Peripheral burst transfer\n configuration",
+ "offset": 21,
+ "size": 2
+ },
+ "ACK": {
+ "description": "ACK",
+ "offset": 20,
+ "size": 1
+ },
+ "CT": {
+ "description": "Current target (only in double buffer\n mode)",
+ "offset": 19,
+ "size": 1
+ },
+ "DBM": {
+ "description": "Double buffer mode",
+ "offset": 18,
+ "size": 1
+ },
+ "PL": {
+ "description": "Priority level",
+ "offset": 16,
+ "size": 2
+ },
+ "PINCOS": {
+ "description": "Peripheral increment offset\n size",
+ "offset": 15,
+ "size": 1
+ },
+ "MSIZE": {
+ "description": "Memory data size",
+ "offset": 13,
+ "size": 2
+ },
+ "PSIZE": {
+ "description": "Peripheral data size",
+ "offset": 11,
+ "size": 2
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 10,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 9,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 8,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 6,
+ "size": 2
+ },
+ "PFCTRL": {
+ "description": "Peripheral flow controller",
+ "offset": 5,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half transfer interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "DMEIE": {
+ "description": "Direct mode error interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "EN": {
+ "description": "Stream enable / flag stream ready when\n read low",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "S5NDTR": {
+ "description": "stream x number of data\n register",
+ "offset": 140,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data items to\n transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "S5PAR": {
+ "description": "stream x peripheral address\n register",
+ "offset": 144,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S5M0AR": {
+ "description": "stream x memory 0 address\n register",
+ "offset": 148,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M0A": {
+ "description": "Memory 0 address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S5M1AR": {
+ "description": "stream x memory 1 address\n register",
+ "offset": 152,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M1A": {
+ "description": "Memory 1 address (used in case of Double\n buffer mode)",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S5FCR": {
+ "description": "stream x FIFO control register",
+ "offset": 156,
+ "size": 32,
+ "reset_value": 33,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEIE": {
+ "description": "FIFO error interrupt\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "FS": {
+ "description": "FIFO status",
+ "offset": 3,
+ "size": 3,
+ "access": "read-only"
+ },
+ "DMDIS": {
+ "description": "Direct mode disable",
+ "offset": 2,
+ "size": 1
+ },
+ "FTH": {
+ "description": "FIFO threshold selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "S6CR": {
+ "description": "stream x configuration\n register",
+ "offset": 160,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CHSEL": {
+ "description": "Channel selection",
+ "offset": 25,
+ "size": 3
+ },
+ "MBURST": {
+ "description": "Memory burst transfer\n configuration",
+ "offset": 23,
+ "size": 2
+ },
+ "PBURST": {
+ "description": "Peripheral burst transfer\n configuration",
+ "offset": 21,
+ "size": 2
+ },
+ "ACK": {
+ "description": "ACK",
+ "offset": 20,
+ "size": 1
+ },
+ "CT": {
+ "description": "Current target (only in double buffer\n mode)",
+ "offset": 19,
+ "size": 1
+ },
+ "DBM": {
+ "description": "Double buffer mode",
+ "offset": 18,
+ "size": 1
+ },
+ "PL": {
+ "description": "Priority level",
+ "offset": 16,
+ "size": 2
+ },
+ "PINCOS": {
+ "description": "Peripheral increment offset\n size",
+ "offset": 15,
+ "size": 1
+ },
+ "MSIZE": {
+ "description": "Memory data size",
+ "offset": 13,
+ "size": 2
+ },
+ "PSIZE": {
+ "description": "Peripheral data size",
+ "offset": 11,
+ "size": 2
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 10,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 9,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 8,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 6,
+ "size": 2
+ },
+ "PFCTRL": {
+ "description": "Peripheral flow controller",
+ "offset": 5,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half transfer interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "DMEIE": {
+ "description": "Direct mode error interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "EN": {
+ "description": "Stream enable / flag stream ready when\n read low",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "S6NDTR": {
+ "description": "stream x number of data\n register",
+ "offset": 164,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data items to\n transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "S6PAR": {
+ "description": "stream x peripheral address\n register",
+ "offset": 168,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S6M0AR": {
+ "description": "stream x memory 0 address\n register",
+ "offset": 172,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M0A": {
+ "description": "Memory 0 address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S6M1AR": {
+ "description": "stream x memory 1 address\n register",
+ "offset": 176,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M1A": {
+ "description": "Memory 1 address (used in case of Double\n buffer mode)",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S6FCR": {
+ "description": "stream x FIFO control register",
+ "offset": 180,
+ "size": 32,
+ "reset_value": 33,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEIE": {
+ "description": "FIFO error interrupt\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "FS": {
+ "description": "FIFO status",
+ "offset": 3,
+ "size": 3,
+ "access": "read-only"
+ },
+ "DMDIS": {
+ "description": "Direct mode disable",
+ "offset": 2,
+ "size": 1
+ },
+ "FTH": {
+ "description": "FIFO threshold selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "S7CR": {
+ "description": "stream x configuration\n register",
+ "offset": 184,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CHSEL": {
+ "description": "Channel selection",
+ "offset": 25,
+ "size": 3
+ },
+ "MBURST": {
+ "description": "Memory burst transfer\n configuration",
+ "offset": 23,
+ "size": 2
+ },
+ "PBURST": {
+ "description": "Peripheral burst transfer\n configuration",
+ "offset": 21,
+ "size": 2
+ },
+ "ACK": {
+ "description": "ACK",
+ "offset": 20,
+ "size": 1
+ },
+ "CT": {
+ "description": "Current target (only in double buffer\n mode)",
+ "offset": 19,
+ "size": 1
+ },
+ "DBM": {
+ "description": "Double buffer mode",
+ "offset": 18,
+ "size": 1
+ },
+ "PL": {
+ "description": "Priority level",
+ "offset": 16,
+ "size": 2
+ },
+ "PINCOS": {
+ "description": "Peripheral increment offset\n size",
+ "offset": 15,
+ "size": 1
+ },
+ "MSIZE": {
+ "description": "Memory data size",
+ "offset": 13,
+ "size": 2
+ },
+ "PSIZE": {
+ "description": "Peripheral data size",
+ "offset": 11,
+ "size": 2
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 10,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 9,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 8,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 6,
+ "size": 2
+ },
+ "PFCTRL": {
+ "description": "Peripheral flow controller",
+ "offset": 5,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half transfer interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "DMEIE": {
+ "description": "Direct mode error interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "EN": {
+ "description": "Stream enable / flag stream ready when\n read low",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "S7NDTR": {
+ "description": "stream x number of data\n register",
+ "offset": 188,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data items to\n transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "S7PAR": {
+ "description": "stream x peripheral address\n register",
+ "offset": 192,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S7M0AR": {
+ "description": "stream x memory 0 address\n register",
+ "offset": 196,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M0A": {
+ "description": "Memory 0 address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S7M1AR": {
+ "description": "stream x memory 1 address\n register",
+ "offset": 200,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M1A": {
+ "description": "Memory 1 address (used in case of Double\n buffer mode)",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S7FCR": {
+ "description": "stream x FIFO control register",
+ "offset": 204,
+ "size": 32,
+ "reset_value": 33,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEIE": {
+ "description": "FIFO error interrupt\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "FS": {
+ "description": "FIFO status",
+ "offset": 3,
+ "size": 3,
+ "access": "read-only"
+ },
+ "DMDIS": {
+ "description": "Direct mode disable",
+ "offset": 2,
+ "size": 1
+ },
+ "FTH": {
+ "description": "FIFO threshold selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "SCB_ACTRL": {
+ "description": "System control block ACTLR",
+ "children": {
+ "registers": {
+ "ACTRL": {
+ "description": "Auxiliary control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DISMCYCINT": {
+ "description": "DISMCYCINT",
+ "offset": 0,
+ "size": 1
+ },
+ "DISDEFWBUF": {
+ "description": "DISDEFWBUF",
+ "offset": 1,
+ "size": 1
+ },
+ "DISFOLD": {
+ "description": "DISFOLD",
+ "offset": 2,
+ "size": 1
+ },
+ "DISFPCA": {
+ "description": "DISFPCA",
+ "offset": 8,
+ "size": 1
+ },
+ "DISOOFP": {
+ "description": "DISOOFP",
+ "offset": 9,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "RCC": {
+ "description": "Reset and clock control",
+ "children": {
+ "registers": {
+ "CR": {
+ "description": "clock control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 131,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PLLI2SRDY": {
+ "description": "PLLI2S clock ready flag",
+ "offset": 27,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PLLI2SON": {
+ "description": "PLLI2S enable",
+ "offset": 26,
+ "size": 1
+ },
+ "PLLRDY": {
+ "description": "Main PLL (PLL) clock ready\n flag",
+ "offset": 25,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PLLON": {
+ "description": "Main PLL (PLL) enable",
+ "offset": 24,
+ "size": 1
+ },
+ "CSSON": {
+ "description": "Clock security system\n enable",
+ "offset": 19,
+ "size": 1
+ },
+ "HSEBYP": {
+ "description": "HSE clock bypass",
+ "offset": 18,
+ "size": 1
+ },
+ "HSERDY": {
+ "description": "HSE clock ready flag",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HSEON": {
+ "description": "HSE clock enable",
+ "offset": 16,
+ "size": 1
+ },
+ "HSICAL": {
+ "description": "Internal high-speed clock\n calibration",
+ "offset": 8,
+ "size": 8,
+ "access": "read-only"
+ },
+ "HSITRIM": {
+ "description": "Internal high-speed clock\n trimming",
+ "offset": 3,
+ "size": 5
+ },
+ "HSIRDY": {
+ "description": "Internal high-speed clock ready\n flag",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HSION": {
+ "description": "Internal high-speed clock\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PLLCFGR": {
+ "description": "PLL configuration register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 603992080,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PLLQ3": {
+ "description": "Main PLL (PLL) division factor for USB\n OTG FS, SDIO and random number generator\n clocks",
+ "offset": 27,
+ "size": 1
+ },
+ "PLLQ2": {
+ "description": "Main PLL (PLL) division factor for USB\n OTG FS, SDIO and random number generator\n clocks",
+ "offset": 26,
+ "size": 1
+ },
+ "PLLQ1": {
+ "description": "Main PLL (PLL) division factor for USB\n OTG FS, SDIO and random number generator\n clocks",
+ "offset": 25,
+ "size": 1
+ },
+ "PLLQ0": {
+ "description": "Main PLL (PLL) division factor for USB\n OTG FS, SDIO and random number generator\n clocks",
+ "offset": 24,
+ "size": 1
+ },
+ "PLLSRC": {
+ "description": "Main PLL(PLL) and audio PLL (PLLI2S)\n entry clock source",
+ "offset": 22,
+ "size": 1
+ },
+ "PLLP1": {
+ "description": "Main PLL (PLL) division factor for main\n system clock",
+ "offset": 17,
+ "size": 1
+ },
+ "PLLP0": {
+ "description": "Main PLL (PLL) division factor for main\n system clock",
+ "offset": 16,
+ "size": 1
+ },
+ "PLLN8": {
+ "description": "Main PLL (PLL) multiplication factor for\n VCO",
+ "offset": 14,
+ "size": 1
+ },
+ "PLLN7": {
+ "description": "Main PLL (PLL) multiplication factor for\n VCO",
+ "offset": 13,
+ "size": 1
+ },
+ "PLLN6": {
+ "description": "Main PLL (PLL) multiplication factor for\n VCO",
+ "offset": 12,
+ "size": 1
+ },
+ "PLLN5": {
+ "description": "Main PLL (PLL) multiplication factor for\n VCO",
+ "offset": 11,
+ "size": 1
+ },
+ "PLLN4": {
+ "description": "Main PLL (PLL) multiplication factor for\n VCO",
+ "offset": 10,
+ "size": 1
+ },
+ "PLLN3": {
+ "description": "Main PLL (PLL) multiplication factor for\n VCO",
+ "offset": 9,
+ "size": 1
+ },
+ "PLLN2": {
+ "description": "Main PLL (PLL) multiplication factor for\n VCO",
+ "offset": 8,
+ "size": 1
+ },
+ "PLLN1": {
+ "description": "Main PLL (PLL) multiplication factor for\n VCO",
+ "offset": 7,
+ "size": 1
+ },
+ "PLLN0": {
+ "description": "Main PLL (PLL) multiplication factor for\n VCO",
+ "offset": 6,
+ "size": 1
+ },
+ "PLLM5": {
+ "description": "Division factor for the main PLL (PLL)\n and audio PLL (PLLI2S) input clock",
+ "offset": 5,
+ "size": 1
+ },
+ "PLLM4": {
+ "description": "Division factor for the main PLL (PLL)\n and audio PLL (PLLI2S) input clock",
+ "offset": 4,
+ "size": 1
+ },
+ "PLLM3": {
+ "description": "Division factor for the main PLL (PLL)\n and audio PLL (PLLI2S) input clock",
+ "offset": 3,
+ "size": 1
+ },
+ "PLLM2": {
+ "description": "Division factor for the main PLL (PLL)\n and audio PLL (PLLI2S) input clock",
+ "offset": 2,
+ "size": 1
+ },
+ "PLLM1": {
+ "description": "Division factor for the main PLL (PLL)\n and audio PLL (PLLI2S) input clock",
+ "offset": 1,
+ "size": 1
+ },
+ "PLLM0": {
+ "description": "Division factor for the main PLL (PLL)\n and audio PLL (PLLI2S) input clock",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CFGR": {
+ "description": "clock configuration register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MCO2": {
+ "description": "Microcontroller clock output\n 2",
+ "offset": 30,
+ "size": 2
+ },
+ "MCO2PRE": {
+ "description": "MCO2 prescaler",
+ "offset": 27,
+ "size": 3
+ },
+ "MCO1PRE": {
+ "description": "MCO1 prescaler",
+ "offset": 24,
+ "size": 3
+ },
+ "I2SSRC": {
+ "description": "I2S clock selection",
+ "offset": 23,
+ "size": 1
+ },
+ "MCO1": {
+ "description": "Microcontroller clock output\n 1",
+ "offset": 21,
+ "size": 2
+ },
+ "RTCPRE": {
+ "description": "HSE division factor for RTC\n clock",
+ "offset": 16,
+ "size": 5
+ },
+ "PPRE2": {
+ "description": "APB high-speed prescaler\n (APB2)",
+ "offset": 13,
+ "size": 3
+ },
+ "PPRE1": {
+ "description": "APB Low speed prescaler\n (APB1)",
+ "offset": 10,
+ "size": 3
+ },
+ "HPRE": {
+ "description": "AHB prescaler",
+ "offset": 4,
+ "size": 4
+ },
+ "SWS1": {
+ "description": "System clock switch status",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SWS0": {
+ "description": "System clock switch status",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SW1": {
+ "description": "System clock switch",
+ "offset": 1,
+ "size": 1
+ },
+ "SW0": {
+ "description": "System clock switch",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CIR": {
+ "description": "clock interrupt register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSSC": {
+ "description": "Clock security system interrupt\n clear",
+ "offset": 23,
+ "size": 1,
+ "access": "write-only"
+ },
+ "PLLI2SRDYC": {
+ "description": "PLLI2S ready interrupt\n clear",
+ "offset": 21,
+ "size": 1,
+ "access": "write-only"
+ },
+ "PLLRDYC": {
+ "description": "Main PLL(PLL) ready interrupt\n clear",
+ "offset": 20,
+ "size": 1,
+ "access": "write-only"
+ },
+ "HSERDYC": {
+ "description": "HSE ready interrupt clear",
+ "offset": 19,
+ "size": 1,
+ "access": "write-only"
+ },
+ "HSIRDYC": {
+ "description": "HSI ready interrupt clear",
+ "offset": 18,
+ "size": 1,
+ "access": "write-only"
+ },
+ "LSERDYC": {
+ "description": "LSE ready interrupt clear",
+ "offset": 17,
+ "size": 1,
+ "access": "write-only"
+ },
+ "LSIRDYC": {
+ "description": "LSI ready interrupt clear",
+ "offset": 16,
+ "size": 1,
+ "access": "write-only"
+ },
+ "PLLI2SRDYIE": {
+ "description": "PLLI2S ready interrupt\n enable",
+ "offset": 13,
+ "size": 1
+ },
+ "PLLRDYIE": {
+ "description": "Main PLL (PLL) ready interrupt\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "HSERDYIE": {
+ "description": "HSE ready interrupt enable",
+ "offset": 11,
+ "size": 1
+ },
+ "HSIRDYIE": {
+ "description": "HSI ready interrupt enable",
+ "offset": 10,
+ "size": 1
+ },
+ "LSERDYIE": {
+ "description": "LSE ready interrupt enable",
+ "offset": 9,
+ "size": 1
+ },
+ "LSIRDYIE": {
+ "description": "LSI ready interrupt enable",
+ "offset": 8,
+ "size": 1
+ },
+ "CSSF": {
+ "description": "Clock security system interrupt\n flag",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PLLI2SRDYF": {
+ "description": "PLLI2S ready interrupt\n flag",
+ "offset": 5,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PLLRDYF": {
+ "description": "Main PLL (PLL) ready interrupt\n flag",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HSERDYF": {
+ "description": "HSE ready interrupt flag",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HSIRDYF": {
+ "description": "HSI ready interrupt flag",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "LSERDYF": {
+ "description": "LSE ready interrupt flag",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "LSIRDYF": {
+ "description": "LSI ready interrupt flag",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "AHB1RSTR": {
+ "description": "AHB1 peripheral reset register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OTGHSRST": {
+ "description": "USB OTG HS module reset",
+ "offset": 29,
+ "size": 1
+ },
+ "ETHMACRST": {
+ "description": "Ethernet MAC reset",
+ "offset": 25,
+ "size": 1
+ },
+ "DMA2RST": {
+ "description": "DMA2 reset",
+ "offset": 22,
+ "size": 1
+ },
+ "DMA1RST": {
+ "description": "DMA2 reset",
+ "offset": 21,
+ "size": 1
+ },
+ "CRCRST": {
+ "description": "CRC reset",
+ "offset": 12,
+ "size": 1
+ },
+ "GPIOIRST": {
+ "description": "IO port I reset",
+ "offset": 8,
+ "size": 1
+ },
+ "GPIOHRST": {
+ "description": "IO port H reset",
+ "offset": 7,
+ "size": 1
+ },
+ "GPIOGRST": {
+ "description": "IO port G reset",
+ "offset": 6,
+ "size": 1
+ },
+ "GPIOFRST": {
+ "description": "IO port F reset",
+ "offset": 5,
+ "size": 1
+ },
+ "GPIOERST": {
+ "description": "IO port E reset",
+ "offset": 4,
+ "size": 1
+ },
+ "GPIODRST": {
+ "description": "IO port D reset",
+ "offset": 3,
+ "size": 1
+ },
+ "GPIOCRST": {
+ "description": "IO port C reset",
+ "offset": 2,
+ "size": 1
+ },
+ "GPIOBRST": {
+ "description": "IO port B reset",
+ "offset": 1,
+ "size": 1
+ },
+ "GPIOARST": {
+ "description": "IO port A reset",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "AHB2RSTR": {
+ "description": "AHB2 peripheral reset register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OTGFSRST": {
+ "description": "USB OTG FS module reset",
+ "offset": 7,
+ "size": 1
+ },
+ "RNGRST": {
+ "description": "Random number generator module\n reset",
+ "offset": 6,
+ "size": 1
+ },
+ "DCMIRST": {
+ "description": "Camera interface reset",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "AHB3RSTR": {
+ "description": "AHB3 peripheral reset register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FSMCRST": {
+ "description": "Flexible static memory controller module\n reset",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "APB1RSTR": {
+ "description": "APB1 peripheral reset register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACRST": {
+ "description": "DAC reset",
+ "offset": 29,
+ "size": 1
+ },
+ "PWRRST": {
+ "description": "Power interface reset",
+ "offset": 28,
+ "size": 1
+ },
+ "CAN2RST": {
+ "description": "CAN2 reset",
+ "offset": 26,
+ "size": 1
+ },
+ "CAN1RST": {
+ "description": "CAN1 reset",
+ "offset": 25,
+ "size": 1
+ },
+ "I2C3RST": {
+ "description": "I2C3 reset",
+ "offset": 23,
+ "size": 1
+ },
+ "I2C2RST": {
+ "description": "I2C 2 reset",
+ "offset": 22,
+ "size": 1
+ },
+ "I2C1RST": {
+ "description": "I2C 1 reset",
+ "offset": 21,
+ "size": 1
+ },
+ "UART5RST": {
+ "description": "USART 5 reset",
+ "offset": 20,
+ "size": 1
+ },
+ "UART4RST": {
+ "description": "USART 4 reset",
+ "offset": 19,
+ "size": 1
+ },
+ "UART3RST": {
+ "description": "USART 3 reset",
+ "offset": 18,
+ "size": 1
+ },
+ "UART2RST": {
+ "description": "USART 2 reset",
+ "offset": 17,
+ "size": 1
+ },
+ "SPI3RST": {
+ "description": "SPI 3 reset",
+ "offset": 15,
+ "size": 1
+ },
+ "SPI2RST": {
+ "description": "SPI 2 reset",
+ "offset": 14,
+ "size": 1
+ },
+ "WWDGRST": {
+ "description": "Window watchdog reset",
+ "offset": 11,
+ "size": 1
+ },
+ "TIM14RST": {
+ "description": "TIM14 reset",
+ "offset": 8,
+ "size": 1
+ },
+ "TIM13RST": {
+ "description": "TIM13 reset",
+ "offset": 7,
+ "size": 1
+ },
+ "TIM12RST": {
+ "description": "TIM12 reset",
+ "offset": 6,
+ "size": 1
+ },
+ "TIM7RST": {
+ "description": "TIM7 reset",
+ "offset": 5,
+ "size": 1
+ },
+ "TIM6RST": {
+ "description": "TIM6 reset",
+ "offset": 4,
+ "size": 1
+ },
+ "TIM5RST": {
+ "description": "TIM5 reset",
+ "offset": 3,
+ "size": 1
+ },
+ "TIM4RST": {
+ "description": "TIM4 reset",
+ "offset": 2,
+ "size": 1
+ },
+ "TIM3RST": {
+ "description": "TIM3 reset",
+ "offset": 1,
+ "size": 1
+ },
+ "TIM2RST": {
+ "description": "TIM2 reset",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "APB2RSTR": {
+ "description": "APB2 peripheral reset register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIM11RST": {
+ "description": "TIM11 reset",
+ "offset": 18,
+ "size": 1
+ },
+ "TIM10RST": {
+ "description": "TIM10 reset",
+ "offset": 17,
+ "size": 1
+ },
+ "TIM9RST": {
+ "description": "TIM9 reset",
+ "offset": 16,
+ "size": 1
+ },
+ "SYSCFGRST": {
+ "description": "System configuration controller\n reset",
+ "offset": 14,
+ "size": 1
+ },
+ "SPI1RST": {
+ "description": "SPI 1 reset",
+ "offset": 12,
+ "size": 1
+ },
+ "SDIORST": {
+ "description": "SDIO reset",
+ "offset": 11,
+ "size": 1
+ },
+ "ADCRST": {
+ "description": "ADC interface reset (common to all\n ADCs)",
+ "offset": 8,
+ "size": 1
+ },
+ "USART6RST": {
+ "description": "USART6 reset",
+ "offset": 5,
+ "size": 1
+ },
+ "USART1RST": {
+ "description": "USART1 reset",
+ "offset": 4,
+ "size": 1
+ },
+ "TIM8RST": {
+ "description": "TIM8 reset",
+ "offset": 1,
+ "size": 1
+ },
+ "TIM1RST": {
+ "description": "TIM1 reset",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "AHB1ENR": {
+ "description": "AHB1 peripheral clock register",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 1048576,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OTGHSULPIEN": {
+ "description": "USB OTG HSULPI clock\n enable",
+ "offset": 30,
+ "size": 1
+ },
+ "OTGHSEN": {
+ "description": "USB OTG HS clock enable",
+ "offset": 29,
+ "size": 1
+ },
+ "ETHMACPTPEN": {
+ "description": "Ethernet PTP clock enable",
+ "offset": 28,
+ "size": 1
+ },
+ "ETHMACRXEN": {
+ "description": "Ethernet Reception clock\n enable",
+ "offset": 27,
+ "size": 1
+ },
+ "ETHMACTXEN": {
+ "description": "Ethernet Transmission clock\n enable",
+ "offset": 26,
+ "size": 1
+ },
+ "ETHMACEN": {
+ "description": "Ethernet MAC clock enable",
+ "offset": 25,
+ "size": 1
+ },
+ "DMA2EN": {
+ "description": "DMA2 clock enable",
+ "offset": 22,
+ "size": 1
+ },
+ "DMA1EN": {
+ "description": "DMA1 clock enable",
+ "offset": 21,
+ "size": 1
+ },
+ "BKPSRAMEN": {
+ "description": "Backup SRAM interface clock\n enable",
+ "offset": 18,
+ "size": 1
+ },
+ "CRCEN": {
+ "description": "CRC clock enable",
+ "offset": 12,
+ "size": 1
+ },
+ "GPIOIEN": {
+ "description": "IO port I clock enable",
+ "offset": 8,
+ "size": 1
+ },
+ "GPIOHEN": {
+ "description": "IO port H clock enable",
+ "offset": 7,
+ "size": 1
+ },
+ "GPIOGEN": {
+ "description": "IO port G clock enable",
+ "offset": 6,
+ "size": 1
+ },
+ "GPIOFEN": {
+ "description": "IO port F clock enable",
+ "offset": 5,
+ "size": 1
+ },
+ "GPIOEEN": {
+ "description": "IO port E clock enable",
+ "offset": 4,
+ "size": 1
+ },
+ "GPIODEN": {
+ "description": "IO port D clock enable",
+ "offset": 3,
+ "size": 1
+ },
+ "GPIOCEN": {
+ "description": "IO port C clock enable",
+ "offset": 2,
+ "size": 1
+ },
+ "GPIOBEN": {
+ "description": "IO port B clock enable",
+ "offset": 1,
+ "size": 1
+ },
+ "GPIOAEN": {
+ "description": "IO port A clock enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "AHB2ENR": {
+ "description": "AHB2 peripheral clock enable\n register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OTGFSEN": {
+ "description": "USB OTG FS clock enable",
+ "offset": 7,
+ "size": 1
+ },
+ "RNGEN": {
+ "description": "Random number generator clock\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "DCMIEN": {
+ "description": "Camera interface enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "AHB3ENR": {
+ "description": "AHB3 peripheral clock enable\n register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FSMCEN": {
+ "description": "Flexible static memory controller module\n clock enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "APB1ENR": {
+ "description": "APB1 peripheral clock enable\n register",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACEN": {
+ "description": "DAC interface clock enable",
+ "offset": 29,
+ "size": 1
+ },
+ "PWREN": {
+ "description": "Power interface clock\n enable",
+ "offset": 28,
+ "size": 1
+ },
+ "CAN2EN": {
+ "description": "CAN 2 clock enable",
+ "offset": 26,
+ "size": 1
+ },
+ "CAN1EN": {
+ "description": "CAN 1 clock enable",
+ "offset": 25,
+ "size": 1
+ },
+ "I2C3EN": {
+ "description": "I2C3 clock enable",
+ "offset": 23,
+ "size": 1
+ },
+ "I2C2EN": {
+ "description": "I2C2 clock enable",
+ "offset": 22,
+ "size": 1
+ },
+ "I2C1EN": {
+ "description": "I2C1 clock enable",
+ "offset": 21,
+ "size": 1
+ },
+ "UART5EN": {
+ "description": "UART5 clock enable",
+ "offset": 20,
+ "size": 1
+ },
+ "UART4EN": {
+ "description": "UART4 clock enable",
+ "offset": 19,
+ "size": 1
+ },
+ "USART3EN": {
+ "description": "USART3 clock enable",
+ "offset": 18,
+ "size": 1
+ },
+ "USART2EN": {
+ "description": "USART 2 clock enable",
+ "offset": 17,
+ "size": 1
+ },
+ "SPI3EN": {
+ "description": "SPI3 clock enable",
+ "offset": 15,
+ "size": 1
+ },
+ "SPI2EN": {
+ "description": "SPI2 clock enable",
+ "offset": 14,
+ "size": 1
+ },
+ "WWDGEN": {
+ "description": "Window watchdog clock\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "TIM14EN": {
+ "description": "TIM14 clock enable",
+ "offset": 8,
+ "size": 1
+ },
+ "TIM13EN": {
+ "description": "TIM13 clock enable",
+ "offset": 7,
+ "size": 1
+ },
+ "TIM12EN": {
+ "description": "TIM12 clock enable",
+ "offset": 6,
+ "size": 1
+ },
+ "TIM7EN": {
+ "description": "TIM7 clock enable",
+ "offset": 5,
+ "size": 1
+ },
+ "TIM6EN": {
+ "description": "TIM6 clock enable",
+ "offset": 4,
+ "size": 1
+ },
+ "TIM5EN": {
+ "description": "TIM5 clock enable",
+ "offset": 3,
+ "size": 1
+ },
+ "TIM4EN": {
+ "description": "TIM4 clock enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TIM3EN": {
+ "description": "TIM3 clock enable",
+ "offset": 1,
+ "size": 1
+ },
+ "TIM2EN": {
+ "description": "TIM2 clock enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "APB2ENR": {
+ "description": "APB2 peripheral clock enable\n register",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIM11EN": {
+ "description": "TIM11 clock enable",
+ "offset": 18,
+ "size": 1
+ },
+ "TIM10EN": {
+ "description": "TIM10 clock enable",
+ "offset": 17,
+ "size": 1
+ },
+ "TIM9EN": {
+ "description": "TIM9 clock enable",
+ "offset": 16,
+ "size": 1
+ },
+ "SYSCFGEN": {
+ "description": "System configuration controller clock\n enable",
+ "offset": 14,
+ "size": 1
+ },
+ "SPI1EN": {
+ "description": "SPI1 clock enable",
+ "offset": 12,
+ "size": 1
+ },
+ "SDIOEN": {
+ "description": "SDIO clock enable",
+ "offset": 11,
+ "size": 1
+ },
+ "ADC3EN": {
+ "description": "ADC3 clock enable",
+ "offset": 10,
+ "size": 1
+ },
+ "ADC2EN": {
+ "description": "ADC2 clock enable",
+ "offset": 9,
+ "size": 1
+ },
+ "ADC1EN": {
+ "description": "ADC1 clock enable",
+ "offset": 8,
+ "size": 1
+ },
+ "USART6EN": {
+ "description": "USART6 clock enable",
+ "offset": 5,
+ "size": 1
+ },
+ "USART1EN": {
+ "description": "USART1 clock enable",
+ "offset": 4,
+ "size": 1
+ },
+ "TIM8EN": {
+ "description": "TIM8 clock enable",
+ "offset": 1,
+ "size": 1
+ },
+ "TIM1EN": {
+ "description": "TIM1 clock enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "AHB1LPENR": {
+ "description": "AHB1 peripheral clock enable in low power\n mode register",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 2120716799,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OTGHSULPILPEN": {
+ "description": "USB OTG HS ULPI clock enable during\n Sleep mode",
+ "offset": 30,
+ "size": 1
+ },
+ "OTGHSLPEN": {
+ "description": "USB OTG HS clock enable during Sleep\n mode",
+ "offset": 29,
+ "size": 1
+ },
+ "ETHMACPTPLPEN": {
+ "description": "Ethernet PTP clock enable during Sleep\n mode",
+ "offset": 28,
+ "size": 1
+ },
+ "ETHMACRXLPEN": {
+ "description": "Ethernet reception clock enable during\n Sleep mode",
+ "offset": 27,
+ "size": 1
+ },
+ "ETHMACTXLPEN": {
+ "description": "Ethernet transmission clock enable\n during Sleep mode",
+ "offset": 26,
+ "size": 1
+ },
+ "ETHMACLPEN": {
+ "description": "Ethernet MAC clock enable during Sleep\n mode",
+ "offset": 25,
+ "size": 1
+ },
+ "DMA2LPEN": {
+ "description": "DMA2 clock enable during Sleep\n mode",
+ "offset": 22,
+ "size": 1
+ },
+ "DMA1LPEN": {
+ "description": "DMA1 clock enable during Sleep\n mode",
+ "offset": 21,
+ "size": 1
+ },
+ "BKPSRAMLPEN": {
+ "description": "Backup SRAM interface clock enable\n during Sleep mode",
+ "offset": 18,
+ "size": 1
+ },
+ "SRAM2LPEN": {
+ "description": "SRAM 2 interface clock enable during\n Sleep mode",
+ "offset": 17,
+ "size": 1
+ },
+ "SRAM1LPEN": {
+ "description": "SRAM 1interface clock enable during\n Sleep mode",
+ "offset": 16,
+ "size": 1
+ },
+ "FLITFLPEN": {
+ "description": "Flash interface clock enable during\n Sleep mode",
+ "offset": 15,
+ "size": 1
+ },
+ "CRCLPEN": {
+ "description": "CRC clock enable during Sleep\n mode",
+ "offset": 12,
+ "size": 1
+ },
+ "GPIOILPEN": {
+ "description": "IO port I clock enable during Sleep\n mode",
+ "offset": 8,
+ "size": 1
+ },
+ "GPIOHLPEN": {
+ "description": "IO port H clock enable during Sleep\n mode",
+ "offset": 7,
+ "size": 1
+ },
+ "GPIOGLPEN": {
+ "description": "IO port G clock enable during Sleep\n mode",
+ "offset": 6,
+ "size": 1
+ },
+ "GPIOFLPEN": {
+ "description": "IO port F clock enable during Sleep\n mode",
+ "offset": 5,
+ "size": 1
+ },
+ "GPIOELPEN": {
+ "description": "IO port E clock enable during Sleep\n mode",
+ "offset": 4,
+ "size": 1
+ },
+ "GPIODLPEN": {
+ "description": "IO port D clock enable during Sleep\n mode",
+ "offset": 3,
+ "size": 1
+ },
+ "GPIOCLPEN": {
+ "description": "IO port C clock enable during Sleep\n mode",
+ "offset": 2,
+ "size": 1
+ },
+ "GPIOBLPEN": {
+ "description": "IO port B clock enable during Sleep\n mode",
+ "offset": 1,
+ "size": 1
+ },
+ "GPIOALPEN": {
+ "description": "IO port A clock enable during sleep\n mode",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "AHB2LPENR": {
+ "description": "AHB2 peripheral clock enable in low power\n mode register",
+ "offset": 84,
+ "size": 32,
+ "reset_value": 241,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OTGFSLPEN": {
+ "description": "USB OTG FS clock enable during Sleep\n mode",
+ "offset": 7,
+ "size": 1
+ },
+ "RNGLPEN": {
+ "description": "Random number generator clock enable\n during Sleep mode",
+ "offset": 6,
+ "size": 1
+ },
+ "DCMILPEN": {
+ "description": "Camera interface enable during Sleep\n mode",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "AHB3LPENR": {
+ "description": "AHB3 peripheral clock enable in low power\n mode register",
+ "offset": 88,
+ "size": 32,
+ "reset_value": 1,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FSMCLPEN": {
+ "description": "Flexible static memory controller module\n clock enable during Sleep mode",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "APB1LPENR": {
+ "description": "APB1 peripheral clock enable in low power\n mode register",
+ "offset": 96,
+ "size": 32,
+ "reset_value": 922667519,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACLPEN": {
+ "description": "DAC interface clock enable during Sleep\n mode",
+ "offset": 29,
+ "size": 1
+ },
+ "PWRLPEN": {
+ "description": "Power interface clock enable during\n Sleep mode",
+ "offset": 28,
+ "size": 1
+ },
+ "CAN2LPEN": {
+ "description": "CAN 2 clock enable during Sleep\n mode",
+ "offset": 26,
+ "size": 1
+ },
+ "CAN1LPEN": {
+ "description": "CAN 1 clock enable during Sleep\n mode",
+ "offset": 25,
+ "size": 1
+ },
+ "I2C3LPEN": {
+ "description": "I2C3 clock enable during Sleep\n mode",
+ "offset": 23,
+ "size": 1
+ },
+ "I2C2LPEN": {
+ "description": "I2C2 clock enable during Sleep\n mode",
+ "offset": 22,
+ "size": 1
+ },
+ "I2C1LPEN": {
+ "description": "I2C1 clock enable during Sleep\n mode",
+ "offset": 21,
+ "size": 1
+ },
+ "UART5LPEN": {
+ "description": "UART5 clock enable during Sleep\n mode",
+ "offset": 20,
+ "size": 1
+ },
+ "UART4LPEN": {
+ "description": "UART4 clock enable during Sleep\n mode",
+ "offset": 19,
+ "size": 1
+ },
+ "USART3LPEN": {
+ "description": "USART3 clock enable during Sleep\n mode",
+ "offset": 18,
+ "size": 1
+ },
+ "USART2LPEN": {
+ "description": "USART2 clock enable during Sleep\n mode",
+ "offset": 17,
+ "size": 1
+ },
+ "SPI3LPEN": {
+ "description": "SPI3 clock enable during Sleep\n mode",
+ "offset": 15,
+ "size": 1
+ },
+ "SPI2LPEN": {
+ "description": "SPI2 clock enable during Sleep\n mode",
+ "offset": 14,
+ "size": 1
+ },
+ "WWDGLPEN": {
+ "description": "Window watchdog clock enable during\n Sleep mode",
+ "offset": 11,
+ "size": 1
+ },
+ "TIM14LPEN": {
+ "description": "TIM14 clock enable during Sleep\n mode",
+ "offset": 8,
+ "size": 1
+ },
+ "TIM13LPEN": {
+ "description": "TIM13 clock enable during Sleep\n mode",
+ "offset": 7,
+ "size": 1
+ },
+ "TIM12LPEN": {
+ "description": "TIM12 clock enable during Sleep\n mode",
+ "offset": 6,
+ "size": 1
+ },
+ "TIM7LPEN": {
+ "description": "TIM7 clock enable during Sleep\n mode",
+ "offset": 5,
+ "size": 1
+ },
+ "TIM6LPEN": {
+ "description": "TIM6 clock enable during Sleep\n mode",
+ "offset": 4,
+ "size": 1
+ },
+ "TIM5LPEN": {
+ "description": "TIM5 clock enable during Sleep\n mode",
+ "offset": 3,
+ "size": 1
+ },
+ "TIM4LPEN": {
+ "description": "TIM4 clock enable during Sleep\n mode",
+ "offset": 2,
+ "size": 1
+ },
+ "TIM3LPEN": {
+ "description": "TIM3 clock enable during Sleep\n mode",
+ "offset": 1,
+ "size": 1
+ },
+ "TIM2LPEN": {
+ "description": "TIM2 clock enable during Sleep\n mode",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "APB2LPENR": {
+ "description": "APB2 peripheral clock enabled in low power\n mode register",
+ "offset": 100,
+ "size": 32,
+ "reset_value": 483123,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIM11LPEN": {
+ "description": "TIM11 clock enable during Sleep\n mode",
+ "offset": 18,
+ "size": 1
+ },
+ "TIM10LPEN": {
+ "description": "TIM10 clock enable during Sleep\n mode",
+ "offset": 17,
+ "size": 1
+ },
+ "TIM9LPEN": {
+ "description": "TIM9 clock enable during sleep\n mode",
+ "offset": 16,
+ "size": 1
+ },
+ "SYSCFGLPEN": {
+ "description": "System configuration controller clock\n enable during Sleep mode",
+ "offset": 14,
+ "size": 1
+ },
+ "SPI1LPEN": {
+ "description": "SPI 1 clock enable during Sleep\n mode",
+ "offset": 12,
+ "size": 1
+ },
+ "SDIOLPEN": {
+ "description": "SDIO clock enable during Sleep\n mode",
+ "offset": 11,
+ "size": 1
+ },
+ "ADC3LPEN": {
+ "description": "ADC 3 clock enable during Sleep\n mode",
+ "offset": 10,
+ "size": 1
+ },
+ "ADC2LPEN": {
+ "description": "ADC2 clock enable during Sleep\n mode",
+ "offset": 9,
+ "size": 1
+ },
+ "ADC1LPEN": {
+ "description": "ADC1 clock enable during Sleep\n mode",
+ "offset": 8,
+ "size": 1
+ },
+ "USART6LPEN": {
+ "description": "USART6 clock enable during Sleep\n mode",
+ "offset": 5,
+ "size": 1
+ },
+ "USART1LPEN": {
+ "description": "USART1 clock enable during Sleep\n mode",
+ "offset": 4,
+ "size": 1
+ },
+ "TIM8LPEN": {
+ "description": "TIM8 clock enable during Sleep\n mode",
+ "offset": 1,
+ "size": 1
+ },
+ "TIM1LPEN": {
+ "description": "TIM1 clock enable during Sleep\n mode",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BDCR": {
+ "description": "Backup domain control register",
+ "offset": 112,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BDRST": {
+ "description": "Backup domain software\n reset",
+ "offset": 16,
+ "size": 1
+ },
+ "RTCEN": {
+ "description": "RTC clock enable",
+ "offset": 15,
+ "size": 1
+ },
+ "RTCSEL1": {
+ "description": "RTC clock source selection",
+ "offset": 9,
+ "size": 1
+ },
+ "RTCSEL0": {
+ "description": "RTC clock source selection",
+ "offset": 8,
+ "size": 1
+ },
+ "LSEBYP": {
+ "description": "External low-speed oscillator\n bypass",
+ "offset": 2,
+ "size": 1
+ },
+ "LSERDY": {
+ "description": "External low-speed oscillator\n ready",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "LSEON": {
+ "description": "External low-speed oscillator\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CSR": {
+ "description": "clock control & status\n register",
+ "offset": 116,
+ "size": 32,
+ "reset_value": 234881024,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LPWRRSTF": {
+ "description": "Low-power reset flag",
+ "offset": 31,
+ "size": 1
+ },
+ "WWDGRSTF": {
+ "description": "Window watchdog reset flag",
+ "offset": 30,
+ "size": 1
+ },
+ "WDGRSTF": {
+ "description": "Independent watchdog reset\n flag",
+ "offset": 29,
+ "size": 1
+ },
+ "SFTRSTF": {
+ "description": "Software reset flag",
+ "offset": 28,
+ "size": 1
+ },
+ "PORRSTF": {
+ "description": "POR/PDR reset flag",
+ "offset": 27,
+ "size": 1
+ },
+ "PADRSTF": {
+ "description": "PIN reset flag",
+ "offset": 26,
+ "size": 1
+ },
+ "BORRSTF": {
+ "description": "BOR reset flag",
+ "offset": 25,
+ "size": 1
+ },
+ "RMVF": {
+ "description": "Remove reset flag",
+ "offset": 24,
+ "size": 1
+ },
+ "LSIRDY": {
+ "description": "Internal low-speed oscillator\n ready",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "LSION": {
+ "description": "Internal low-speed oscillator\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SSCGR": {
+ "description": "spread spectrum clock generation\n register",
+ "offset": 128,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SSCGEN": {
+ "description": "Spread spectrum modulation\n enable",
+ "offset": 31,
+ "size": 1
+ },
+ "SPREADSEL": {
+ "description": "Spread Select",
+ "offset": 30,
+ "size": 1
+ },
+ "INCSTEP": {
+ "description": "Incrementation step",
+ "offset": 13,
+ "size": 15
+ },
+ "MODPER": {
+ "description": "Modulation period",
+ "offset": 0,
+ "size": 13
+ }
+ }
+ }
+ },
+ "PLLI2SCFGR": {
+ "description": "PLLI2S configuration register",
+ "offset": 132,
+ "size": 32,
+ "reset_value": 536883200,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PLLI2SRx": {
+ "description": "PLLI2S division factor for I2S\n clocks",
+ "offset": 28,
+ "size": 3
+ },
+ "PLLI2SNx": {
+ "description": "PLLI2S multiplication factor for\n VCO",
+ "offset": 6,
+ "size": 9
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "GPIOI": {
+ "description": "General-purpose I/Os",
+ "children": {
+ "registers": {
+ "MODER": {
+ "description": "GPIO port mode register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MODER15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 30,
+ "size": 2
+ },
+ "MODER14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 28,
+ "size": 2
+ },
+ "MODER13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 26,
+ "size": 2
+ },
+ "MODER12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 24,
+ "size": 2
+ },
+ "MODER11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 22,
+ "size": 2
+ },
+ "MODER10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 20,
+ "size": 2
+ },
+ "MODER9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 18,
+ "size": 2
+ },
+ "MODER8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 16,
+ "size": 2
+ },
+ "MODER7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 2
+ },
+ "MODER6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 2
+ },
+ "MODER5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 2
+ },
+ "MODER4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 2
+ },
+ "MODER3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 2
+ },
+ "MODER2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 2
+ },
+ "MODER1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 2
+ },
+ "MODER0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTYPER": {
+ "description": "GPIO port output type register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OT15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "OT14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "OT13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "OT12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "OT11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "OT10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "OT9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "OT8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "OT7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "OT6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "OT5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "OT4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "OT3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "OT2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "OT1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "OT0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OSPEEDR": {
+ "description": "GPIO port output speed\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OSPEEDR15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 30,
+ "size": 2
+ },
+ "OSPEEDR14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 28,
+ "size": 2
+ },
+ "OSPEEDR13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 26,
+ "size": 2
+ },
+ "OSPEEDR12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 24,
+ "size": 2
+ },
+ "OSPEEDR11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 22,
+ "size": 2
+ },
+ "OSPEEDR10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 20,
+ "size": 2
+ },
+ "OSPEEDR9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 18,
+ "size": 2
+ },
+ "OSPEEDR8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 16,
+ "size": 2
+ },
+ "OSPEEDR7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 2
+ },
+ "OSPEEDR6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 2
+ },
+ "OSPEEDR5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 2
+ },
+ "OSPEEDR4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 2
+ },
+ "OSPEEDR3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 2
+ },
+ "OSPEEDR2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 2
+ },
+ "OSPEEDR1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 2
+ },
+ "OSPEEDR0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "PUPDR": {
+ "description": "GPIO port pull-up/pull-down\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PUPDR15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 30,
+ "size": 2
+ },
+ "PUPDR14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 28,
+ "size": 2
+ },
+ "PUPDR13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 26,
+ "size": 2
+ },
+ "PUPDR12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 24,
+ "size": 2
+ },
+ "PUPDR11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 22,
+ "size": 2
+ },
+ "PUPDR10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 20,
+ "size": 2
+ },
+ "PUPDR9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 18,
+ "size": 2
+ },
+ "PUPDR8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 16,
+ "size": 2
+ },
+ "PUPDR7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 2
+ },
+ "PUPDR6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 2
+ },
+ "PUPDR5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 2
+ },
+ "PUPDR4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 2
+ },
+ "PUPDR3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 2
+ },
+ "PUPDR2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 2
+ },
+ "PUPDR1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 2
+ },
+ "PUPDR0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "IDR": {
+ "description": "GPIO port input data register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "IDR15": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "IDR14": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "IDR13": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "IDR12": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "IDR11": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "IDR10": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "IDR9": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "IDR8": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "IDR7": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "IDR6": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "IDR5": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "IDR4": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "IDR3": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "IDR2": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "IDR1": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "IDR0": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ODR": {
+ "description": "GPIO port output data register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ODR15": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "ODR14": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "ODR13": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "ODR12": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "ODR11": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "ODR10": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "ODR9": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "ODR8": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "ODR7": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "ODR6": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "ODR5": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "ODR4": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "ODR3": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "ODR2": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "ODR1": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "ODR0": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BSRR": {
+ "description": "GPIO port bit set/reset\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "BR15": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 31,
+ "size": 1
+ },
+ "BR14": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 30,
+ "size": 1
+ },
+ "BR13": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 29,
+ "size": 1
+ },
+ "BR12": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 28,
+ "size": 1
+ },
+ "BR11": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 27,
+ "size": 1
+ },
+ "BR10": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 26,
+ "size": 1
+ },
+ "BR9": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 25,
+ "size": 1
+ },
+ "BR8": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 24,
+ "size": 1
+ },
+ "BR7": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 23,
+ "size": 1
+ },
+ "BR6": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 22,
+ "size": 1
+ },
+ "BR5": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 21,
+ "size": 1
+ },
+ "BR4": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 20,
+ "size": 1
+ },
+ "BR3": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 19,
+ "size": 1
+ },
+ "BR2": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 18,
+ "size": 1
+ },
+ "BR1": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 17,
+ "size": 1
+ },
+ "BR0": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 16,
+ "size": 1
+ },
+ "BS15": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "BS14": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "BS13": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "BS12": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "BS11": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "BS10": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "BS9": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "BS8": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "BS7": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "BS6": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "BS5": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "BS4": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "BS3": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "BS2": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "BS1": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "BS0": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "LCKR": {
+ "description": "GPIO port configuration lock\n register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LCKK": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 16,
+ "size": 1
+ },
+ "LCK15": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "LCK14": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "LCK13": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "LCK12": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "LCK11": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "LCK10": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "LCK9": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "LCK8": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "LCK7": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "LCK6": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "LCK5": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "LCK4": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "LCK3": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "LCK2": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "LCK1": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "LCK0": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "AFRL": {
+ "description": "GPIO alternate function low\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "AFRL7": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 28,
+ "size": 4
+ },
+ "AFRL6": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 24,
+ "size": 4
+ },
+ "AFRL5": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 20,
+ "size": 4
+ },
+ "AFRL4": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 16,
+ "size": 4
+ },
+ "AFRL3": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 12,
+ "size": 4
+ },
+ "AFRL2": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 8,
+ "size": 4
+ },
+ "AFRL1": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 4,
+ "size": 4
+ },
+ "AFRL0": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "AFRH": {
+ "description": "GPIO alternate function high\n register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "AFRH15": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 28,
+ "size": 4
+ },
+ "AFRH14": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 24,
+ "size": 4
+ },
+ "AFRH13": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 20,
+ "size": 4
+ },
+ "AFRH12": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 16,
+ "size": 4
+ },
+ "AFRH11": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 12,
+ "size": 4
+ },
+ "AFRH10": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 8,
+ "size": 4
+ },
+ "AFRH9": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 4,
+ "size": 4
+ },
+ "AFRH8": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "FPU_CPACR": {
+ "description": "Floating point unit CPACR",
+ "children": {
+ "registers": {
+ "CPACR": {
+ "description": "Coprocessor access control\n register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CP": {
+ "description": "CP",
+ "offset": 20,
+ "size": 4
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "NVIC_STIR": {
+ "description": "Nested vectored interrupt\n controller",
+ "children": {
+ "registers": {
+ "STIR": {
+ "description": "Software trigger interrupt\n register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INTID": {
+ "description": "Software generated interrupt\n ID",
+ "offset": 0,
+ "size": 9
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "SCB": {
+ "description": "System control block",
+ "children": {
+ "registers": {
+ "CPUID": {
+ "description": "CPUID base register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 1091551809,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "Revision": {
+ "description": "Revision number",
+ "offset": 0,
+ "size": 4
+ },
+ "PartNo": {
+ "description": "Part number of the\n processor",
+ "offset": 4,
+ "size": 12
+ },
+ "Constant": {
+ "description": "Reads as 0xF",
+ "offset": 16,
+ "size": 4
+ },
+ "Variant": {
+ "description": "Variant number",
+ "offset": 20,
+ "size": 4
+ },
+ "Implementer": {
+ "description": "Implementer code",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "ICSR": {
+ "description": "Interrupt control and state\n register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "VECTACTIVE": {
+ "description": "Active vector",
+ "offset": 0,
+ "size": 9
+ },
+ "RETTOBASE": {
+ "description": "Return to base level",
+ "offset": 11,
+ "size": 1
+ },
+ "VECTPENDING": {
+ "description": "Pending vector",
+ "offset": 12,
+ "size": 7
+ },
+ "ISRPENDING": {
+ "description": "Interrupt pending flag",
+ "offset": 22,
+ "size": 1
+ },
+ "PENDSTCLR": {
+ "description": "SysTick exception clear-pending\n bit",
+ "offset": 25,
+ "size": 1
+ },
+ "PENDSTSET": {
+ "description": "SysTick exception set-pending\n bit",
+ "offset": 26,
+ "size": 1
+ },
+ "PENDSVCLR": {
+ "description": "PendSV clear-pending bit",
+ "offset": 27,
+ "size": 1
+ },
+ "PENDSVSET": {
+ "description": "PendSV set-pending bit",
+ "offset": 28,
+ "size": 1
+ },
+ "NMIPENDSET": {
+ "description": "NMI set-pending bit.",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "VTOR": {
+ "description": "Vector table offset register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TBLOFF": {
+ "description": "Vector table base offset\n field",
+ "offset": 9,
+ "size": 21
+ }
+ }
+ }
+ },
+ "AIRCR": {
+ "description": "Application interrupt and reset control\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "VECTRESET": {
+ "description": "VECTRESET",
+ "offset": 0,
+ "size": 1
+ },
+ "VECTCLRACTIVE": {
+ "description": "VECTCLRACTIVE",
+ "offset": 1,
+ "size": 1
+ },
+ "SYSRESETREQ": {
+ "description": "SYSRESETREQ",
+ "offset": 2,
+ "size": 1
+ },
+ "PRIGROUP": {
+ "description": "PRIGROUP",
+ "offset": 8,
+ "size": 3
+ },
+ "ENDIANESS": {
+ "description": "ENDIANESS",
+ "offset": 15,
+ "size": 1
+ },
+ "VECTKEYSTAT": {
+ "description": "Register key",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "SCR": {
+ "description": "System control register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SLEEPONEXIT": {
+ "description": "SLEEPONEXIT",
+ "offset": 1,
+ "size": 1
+ },
+ "SLEEPDEEP": {
+ "description": "SLEEPDEEP",
+ "offset": 2,
+ "size": 1
+ },
+ "SEVEONPEND": {
+ "description": "Send Event on Pending bit",
+ "offset": 4,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCR": {
+ "description": "Configuration and control\n register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NONBASETHRDENA": {
+ "description": "Configures how the processor enters\n Thread mode",
+ "offset": 0,
+ "size": 1
+ },
+ "USERSETMPEND": {
+ "description": "USERSETMPEND",
+ "offset": 1,
+ "size": 1
+ },
+ "UNALIGN__TRP": {
+ "description": "UNALIGN_ TRP",
+ "offset": 3,
+ "size": 1
+ },
+ "DIV_0_TRP": {
+ "description": "DIV_0_TRP",
+ "offset": 4,
+ "size": 1
+ },
+ "BFHFNMIGN": {
+ "description": "BFHFNMIGN",
+ "offset": 8,
+ "size": 1
+ },
+ "STKALIGN": {
+ "description": "STKALIGN",
+ "offset": 9,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SHPR1": {
+ "description": "System handler priority\n registers",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRI_4": {
+ "description": "Priority of system handler\n 4",
+ "offset": 0,
+ "size": 8
+ },
+ "PRI_5": {
+ "description": "Priority of system handler\n 5",
+ "offset": 8,
+ "size": 8
+ },
+ "PRI_6": {
+ "description": "Priority of system handler\n 6",
+ "offset": 16,
+ "size": 8
+ }
+ }
+ }
+ },
+ "SHPR2": {
+ "description": "System handler priority\n registers",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRI_11": {
+ "description": "Priority of system handler\n 11",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "SHPR3": {
+ "description": "System handler priority\n registers",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRI_14": {
+ "description": "Priority of system handler\n 14",
+ "offset": 16,
+ "size": 8
+ },
+ "PRI_15": {
+ "description": "Priority of system handler\n 15",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "SHCRS": {
+ "description": "System handler control and state\n register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MEMFAULTACT": {
+ "description": "Memory management fault exception active\n bit",
+ "offset": 0,
+ "size": 1
+ },
+ "BUSFAULTACT": {
+ "description": "Bus fault exception active\n bit",
+ "offset": 1,
+ "size": 1
+ },
+ "USGFAULTACT": {
+ "description": "Usage fault exception active\n bit",
+ "offset": 3,
+ "size": 1
+ },
+ "SVCALLACT": {
+ "description": "SVC call active bit",
+ "offset": 7,
+ "size": 1
+ },
+ "MONITORACT": {
+ "description": "Debug monitor active bit",
+ "offset": 8,
+ "size": 1
+ },
+ "PENDSVACT": {
+ "description": "PendSV exception active\n bit",
+ "offset": 10,
+ "size": 1
+ },
+ "SYSTICKACT": {
+ "description": "SysTick exception active\n bit",
+ "offset": 11,
+ "size": 1
+ },
+ "USGFAULTPENDED": {
+ "description": "Usage fault exception pending\n bit",
+ "offset": 12,
+ "size": 1
+ },
+ "MEMFAULTPENDED": {
+ "description": "Memory management fault exception\n pending bit",
+ "offset": 13,
+ "size": 1
+ },
+ "BUSFAULTPENDED": {
+ "description": "Bus fault exception pending\n bit",
+ "offset": 14,
+ "size": 1
+ },
+ "SVCALLPENDED": {
+ "description": "SVC call pending bit",
+ "offset": 15,
+ "size": 1
+ },
+ "MEMFAULTENA": {
+ "description": "Memory management fault enable\n bit",
+ "offset": 16,
+ "size": 1
+ },
+ "BUSFAULTENA": {
+ "description": "Bus fault enable bit",
+ "offset": 17,
+ "size": 1
+ },
+ "USGFAULTENA": {
+ "description": "Usage fault enable bit",
+ "offset": 18,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CFSR_UFSR_BFSR_MMFSR": {
+ "description": "Configurable fault status\n register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IACCVIOL": {
+ "description": "Instruction access violation\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "MUNSTKERR": {
+ "description": "Memory manager fault on unstacking for a\n return from exception",
+ "offset": 3,
+ "size": 1
+ },
+ "MSTKERR": {
+ "description": "Memory manager fault on stacking for\n exception entry.",
+ "offset": 4,
+ "size": 1
+ },
+ "MLSPERR": {
+ "description": "MLSPERR",
+ "offset": 5,
+ "size": 1
+ },
+ "MMARVALID": {
+ "description": "Memory Management Fault Address Register\n (MMAR) valid flag",
+ "offset": 7,
+ "size": 1
+ },
+ "IBUSERR": {
+ "description": "Instruction bus error",
+ "offset": 8,
+ "size": 1
+ },
+ "PRECISERR": {
+ "description": "Precise data bus error",
+ "offset": 9,
+ "size": 1
+ },
+ "IMPRECISERR": {
+ "description": "Imprecise data bus error",
+ "offset": 10,
+ "size": 1
+ },
+ "UNSTKERR": {
+ "description": "Bus fault on unstacking for a return\n from exception",
+ "offset": 11,
+ "size": 1
+ },
+ "STKERR": {
+ "description": "Bus fault on stacking for exception\n entry",
+ "offset": 12,
+ "size": 1
+ },
+ "LSPERR": {
+ "description": "Bus fault on floating-point lazy state\n preservation",
+ "offset": 13,
+ "size": 1
+ },
+ "BFARVALID": {
+ "description": "Bus Fault Address Register (BFAR) valid\n flag",
+ "offset": 15,
+ "size": 1
+ },
+ "UNDEFINSTR": {
+ "description": "Undefined instruction usage\n fault",
+ "offset": 16,
+ "size": 1
+ },
+ "INVSTATE": {
+ "description": "Invalid state usage fault",
+ "offset": 17,
+ "size": 1
+ },
+ "INVPC": {
+ "description": "Invalid PC load usage\n fault",
+ "offset": 18,
+ "size": 1
+ },
+ "NOCP": {
+ "description": "No coprocessor usage\n fault.",
+ "offset": 19,
+ "size": 1
+ },
+ "UNALIGNED": {
+ "description": "Unaligned access usage\n fault",
+ "offset": 24,
+ "size": 1
+ },
+ "DIVBYZERO": {
+ "description": "Divide by zero usage fault",
+ "offset": 25,
+ "size": 1
+ }
+ }
+ }
+ },
+ "HFSR": {
+ "description": "Hard fault status register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "VECTTBL": {
+ "description": "Vector table hard fault",
+ "offset": 1,
+ "size": 1
+ },
+ "FORCED": {
+ "description": "Forced hard fault",
+ "offset": 30,
+ "size": 1
+ },
+ "DEBUG_VT": {
+ "description": "Reserved for Debug use",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MMFAR": {
+ "description": "Memory management fault address\n register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MMFAR": {
+ "description": "Memory management fault\n address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BFAR": {
+ "description": "Bus fault address register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BFAR": {
+ "description": "Bus fault address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "AFSR": {
+ "description": "Auxiliary fault status\n register",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IMPDEF": {
+ "description": "Implementation defined",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "STK": {
+ "description": "SysTick timer",
+ "children": {
+ "registers": {
+ "CTRL": {
+ "description": "SysTick control and status\n register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ENABLE": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ },
+ "TICKINT": {
+ "description": "SysTick exception request\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "CLKSOURCE": {
+ "description": "Clock source selection",
+ "offset": 2,
+ "size": 1
+ },
+ "COUNTFLAG": {
+ "description": "COUNTFLAG",
+ "offset": 16,
+ "size": 1
+ }
+ }
+ }
+ },
+ "LOAD": {
+ "description": "SysTick reload value register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RELOAD": {
+ "description": "RELOAD value",
+ "offset": 0,
+ "size": 24
+ }
+ }
+ }
+ },
+ "VAL": {
+ "description": "SysTick current value register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CURRENT": {
+ "description": "Current counter value",
+ "offset": 0,
+ "size": 24
+ }
+ }
+ }
+ },
+ "CALIB": {
+ "description": "SysTick calibration value\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TENMS": {
+ "description": "Calibration value",
+ "offset": 0,
+ "size": 24
+ },
+ "SKEW": {
+ "description": "SKEW flag: Indicates whether the TENMS\n value is exact",
+ "offset": 30,
+ "size": 1
+ },
+ "NOREF": {
+ "description": "NOREF flag. Reads as zero",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "MPU": {
+ "description": "Memory protection unit",
+ "children": {
+ "registers": {
+ "MPU_TYPER": {
+ "description": "MPU type register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 2048,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "SEPARATE": {
+ "description": "Separate flag",
+ "offset": 0,
+ "size": 1
+ },
+ "DREGION": {
+ "description": "Number of MPU data regions",
+ "offset": 8,
+ "size": 8
+ },
+ "IREGION": {
+ "description": "Number of MPU instruction\n regions",
+ "offset": 16,
+ "size": 8
+ }
+ }
+ }
+ },
+ "MPU_CTRL": {
+ "description": "MPU control register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "ENABLE": {
+ "description": "Enables the MPU",
+ "offset": 0,
+ "size": 1
+ },
+ "HFNMIENA": {
+ "description": "Enables the operation of MPU during hard\n fault",
+ "offset": 1,
+ "size": 1
+ },
+ "PRIVDEFENA": {
+ "description": "Enable priviliged software access to\n default memory map",
+ "offset": 2,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MPU_RNR": {
+ "description": "MPU region number register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "REGION": {
+ "description": "MPU region",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "MPU_RBAR": {
+ "description": "MPU region base address\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "REGION": {
+ "description": "MPU region field",
+ "offset": 0,
+ "size": 4
+ },
+ "VALID": {
+ "description": "MPU region number valid",
+ "offset": 4,
+ "size": 1
+ },
+ "ADDR": {
+ "description": "Region base address field",
+ "offset": 5,
+ "size": 27
+ }
+ }
+ }
+ },
+ "MPU_RASR": {
+ "description": "MPU region attribute and size\n register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ENABLE": {
+ "description": "Region enable bit.",
+ "offset": 0,
+ "size": 1
+ },
+ "SIZE": {
+ "description": "Size of the MPU protection\n region",
+ "offset": 1,
+ "size": 5
+ },
+ "SRD": {
+ "description": "Subregion disable bits",
+ "offset": 8,
+ "size": 8
+ },
+ "B": {
+ "description": "memory attribute",
+ "offset": 16,
+ "size": 1
+ },
+ "C": {
+ "description": "memory attribute",
+ "offset": 17,
+ "size": 1
+ },
+ "S": {
+ "description": "Shareable memory attribute",
+ "offset": 18,
+ "size": 1
+ },
+ "TEX": {
+ "description": "memory attribute",
+ "offset": 19,
+ "size": 3
+ },
+ "AP": {
+ "description": "Access permission",
+ "offset": 24,
+ "size": 3
+ },
+ "XN": {
+ "description": "Instruction access disable\n bit",
+ "offset": 28,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "FPU": {
+ "description": "Floting point unit",
+ "children": {
+ "registers": {
+ "FPCCR": {
+ "description": "Floating-point context control\n register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LSPACT": {
+ "description": "LSPACT",
+ "offset": 0,
+ "size": 1
+ },
+ "USER": {
+ "description": "USER",
+ "offset": 1,
+ "size": 1
+ },
+ "THREAD": {
+ "description": "THREAD",
+ "offset": 3,
+ "size": 1
+ },
+ "HFRDY": {
+ "description": "HFRDY",
+ "offset": 4,
+ "size": 1
+ },
+ "MMRDY": {
+ "description": "MMRDY",
+ "offset": 5,
+ "size": 1
+ },
+ "BFRDY": {
+ "description": "BFRDY",
+ "offset": 6,
+ "size": 1
+ },
+ "MONRDY": {
+ "description": "MONRDY",
+ "offset": 8,
+ "size": 1
+ },
+ "LSPEN": {
+ "description": "LSPEN",
+ "offset": 30,
+ "size": 1
+ },
+ "ASPEN": {
+ "description": "ASPEN",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FPCAR": {
+ "description": "Floating-point context address\n register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ADDRESS": {
+ "description": "Location of unpopulated\n floating-point",
+ "offset": 3,
+ "size": 29
+ }
+ }
+ }
+ },
+ "FPSCR": {
+ "description": "Floating-point status control\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IOC": {
+ "description": "Invalid operation cumulative exception\n bit",
+ "offset": 0,
+ "size": 1
+ },
+ "DZC": {
+ "description": "Division by zero cumulative exception\n bit.",
+ "offset": 1,
+ "size": 1
+ },
+ "OFC": {
+ "description": "Overflow cumulative exception\n bit",
+ "offset": 2,
+ "size": 1
+ },
+ "UFC": {
+ "description": "Underflow cumulative exception\n bit",
+ "offset": 3,
+ "size": 1
+ },
+ "IXC": {
+ "description": "Inexact cumulative exception\n bit",
+ "offset": 4,
+ "size": 1
+ },
+ "IDC": {
+ "description": "Input denormal cumulative exception\n bit.",
+ "offset": 7,
+ "size": 1
+ },
+ "RMode": {
+ "description": "Rounding Mode control\n field",
+ "offset": 22,
+ "size": 2
+ },
+ "FZ": {
+ "description": "Flush-to-zero mode control\n bit:",
+ "offset": 24,
+ "size": 1
+ },
+ "DN": {
+ "description": "Default NaN mode control\n bit",
+ "offset": 25,
+ "size": 1
+ },
+ "AHP": {
+ "description": "Alternative half-precision control\n bit",
+ "offset": 26,
+ "size": 1
+ },
+ "V": {
+ "description": "Overflow condition code\n flag",
+ "offset": 28,
+ "size": 1
+ },
+ "C": {
+ "description": "Carry condition code flag",
+ "offset": 29,
+ "size": 1
+ },
+ "Z": {
+ "description": "Zero condition code flag",
+ "offset": 30,
+ "size": 1
+ },
+ "N": {
+ "description": "Negative condition code\n flag",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "CRYP": {
+ "description": "Cryptographic processor",
+ "children": {
+ "registers": {
+ "CR": {
+ "description": "control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ALGODIR": {
+ "description": "Algorithm direction",
+ "offset": 2,
+ "size": 1
+ },
+ "ALGOMODE0": {
+ "description": "Algorithm mode",
+ "offset": 3,
+ "size": 3
+ },
+ "DATATYPE": {
+ "description": "Data type selection",
+ "offset": 6,
+ "size": 2
+ },
+ "KEYSIZE": {
+ "description": "Key size selection (AES mode\n only)",
+ "offset": 8,
+ "size": 2
+ },
+ "FFLUSH": {
+ "description": "FIFO flush",
+ "offset": 14,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CRYPEN": {
+ "description": "Cryptographic processor\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "GCM_CCMPH": {
+ "description": "GCM_CCMPH",
+ "offset": 16,
+ "size": 2
+ },
+ "ALGOMODE3": {
+ "description": "ALGOMODE",
+ "offset": 19,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 3,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "BUSY": {
+ "description": "Busy bit",
+ "offset": 4,
+ "size": 1
+ },
+ "OFFU": {
+ "description": "Output FIFO full",
+ "offset": 3,
+ "size": 1
+ },
+ "OFNE": {
+ "description": "Output FIFO not empty",
+ "offset": 2,
+ "size": 1
+ },
+ "IFNF": {
+ "description": "Input FIFO not full",
+ "offset": 1,
+ "size": 1
+ },
+ "IFEM": {
+ "description": "Input FIFO empty",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DIN": {
+ "description": "data input register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATAIN": {
+ "description": "Data input",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DOUT": {
+ "description": "data output register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DATAOUT": {
+ "description": "Data output",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DMACR": {
+ "description": "DMA control register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DOEN": {
+ "description": "DMA output enable",
+ "offset": 1,
+ "size": 1
+ },
+ "DIEN": {
+ "description": "DMA input enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "IMSCR": {
+ "description": "interrupt mask set/clear\n register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OUTIM": {
+ "description": "Output FIFO service interrupt\n mask",
+ "offset": 1,
+ "size": 1
+ },
+ "INIM": {
+ "description": "Input FIFO service interrupt\n mask",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "RISR": {
+ "description": "raw interrupt status register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 1,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "OUTRIS": {
+ "description": "Output FIFO service raw interrupt\n status",
+ "offset": 1,
+ "size": 1
+ },
+ "INRIS": {
+ "description": "Input FIFO service raw interrupt\n status",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MISR": {
+ "description": "masked interrupt status\n register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "OUTMIS": {
+ "description": "Output FIFO service masked interrupt\n status",
+ "offset": 1,
+ "size": 1
+ },
+ "INMIS": {
+ "description": "Input FIFO service masked interrupt\n status",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "K0LR": {
+ "description": "key registers",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "b224": {
+ "description": "b224",
+ "offset": 0,
+ "size": 1
+ },
+ "b225": {
+ "description": "b225",
+ "offset": 1,
+ "size": 1
+ },
+ "b226": {
+ "description": "b226",
+ "offset": 2,
+ "size": 1
+ },
+ "b227": {
+ "description": "b227",
+ "offset": 3,
+ "size": 1
+ },
+ "b228": {
+ "description": "b228",
+ "offset": 4,
+ "size": 1
+ },
+ "b229": {
+ "description": "b229",
+ "offset": 5,
+ "size": 1
+ },
+ "b230": {
+ "description": "b230",
+ "offset": 6,
+ "size": 1
+ },
+ "b231": {
+ "description": "b231",
+ "offset": 7,
+ "size": 1
+ },
+ "b232": {
+ "description": "b232",
+ "offset": 8,
+ "size": 1
+ },
+ "b233": {
+ "description": "b233",
+ "offset": 9,
+ "size": 1
+ },
+ "b234": {
+ "description": "b234",
+ "offset": 10,
+ "size": 1
+ },
+ "b235": {
+ "description": "b235",
+ "offset": 11,
+ "size": 1
+ },
+ "b236": {
+ "description": "b236",
+ "offset": 12,
+ "size": 1
+ },
+ "b237": {
+ "description": "b237",
+ "offset": 13,
+ "size": 1
+ },
+ "b238": {
+ "description": "b238",
+ "offset": 14,
+ "size": 1
+ },
+ "b239": {
+ "description": "b239",
+ "offset": 15,
+ "size": 1
+ },
+ "b240": {
+ "description": "b240",
+ "offset": 16,
+ "size": 1
+ },
+ "b241": {
+ "description": "b241",
+ "offset": 17,
+ "size": 1
+ },
+ "b242": {
+ "description": "b242",
+ "offset": 18,
+ "size": 1
+ },
+ "b243": {
+ "description": "b243",
+ "offset": 19,
+ "size": 1
+ },
+ "b244": {
+ "description": "b244",
+ "offset": 20,
+ "size": 1
+ },
+ "b245": {
+ "description": "b245",
+ "offset": 21,
+ "size": 1
+ },
+ "b246": {
+ "description": "b246",
+ "offset": 22,
+ "size": 1
+ },
+ "b247": {
+ "description": "b247",
+ "offset": 23,
+ "size": 1
+ },
+ "b248": {
+ "description": "b248",
+ "offset": 24,
+ "size": 1
+ },
+ "b249": {
+ "description": "b249",
+ "offset": 25,
+ "size": 1
+ },
+ "b250": {
+ "description": "b250",
+ "offset": 26,
+ "size": 1
+ },
+ "b251": {
+ "description": "b251",
+ "offset": 27,
+ "size": 1
+ },
+ "b252": {
+ "description": "b252",
+ "offset": 28,
+ "size": 1
+ },
+ "b253": {
+ "description": "b253",
+ "offset": 29,
+ "size": 1
+ },
+ "b254": {
+ "description": "b254",
+ "offset": 30,
+ "size": 1
+ },
+ "b255": {
+ "description": "b255",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "K0RR": {
+ "description": "key registers",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "b192": {
+ "description": "b192",
+ "offset": 0,
+ "size": 1
+ },
+ "b193": {
+ "description": "b193",
+ "offset": 1,
+ "size": 1
+ },
+ "b194": {
+ "description": "b194",
+ "offset": 2,
+ "size": 1
+ },
+ "b195": {
+ "description": "b195",
+ "offset": 3,
+ "size": 1
+ },
+ "b196": {
+ "description": "b196",
+ "offset": 4,
+ "size": 1
+ },
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+ },
+ "b19": {
+ "description": "b19",
+ "offset": 19,
+ "size": 1
+ },
+ "b20": {
+ "description": "b20",
+ "offset": 20,
+ "size": 1
+ },
+ "b21": {
+ "description": "b21",
+ "offset": 21,
+ "size": 1
+ },
+ "b22": {
+ "description": "b22",
+ "offset": 22,
+ "size": 1
+ },
+ "b23": {
+ "description": "b23",
+ "offset": 23,
+ "size": 1
+ },
+ "b24": {
+ "description": "b24",
+ "offset": 24,
+ "size": 1
+ },
+ "b25": {
+ "description": "b25",
+ "offset": 25,
+ "size": 1
+ },
+ "b26": {
+ "description": "b26",
+ "offset": 26,
+ "size": 1
+ },
+ "b27": {
+ "description": "b27",
+ "offset": 27,
+ "size": 1
+ },
+ "b28": {
+ "description": "b28",
+ "offset": 28,
+ "size": 1
+ },
+ "b29": {
+ "description": "b29",
+ "offset": 29,
+ "size": 1
+ },
+ "b30": {
+ "description": "b30",
+ "offset": 30,
+ "size": 1
+ },
+ "b31": {
+ "description": "b31",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "IV0LR": {
+ "description": "initialization vector\n registers",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IV31": {
+ "description": "IV31",
+ "offset": 0,
+ "size": 1
+ },
+ "IV30": {
+ "description": "IV30",
+ "offset": 1,
+ "size": 1
+ },
+ "IV29": {
+ "description": "IV29",
+ "offset": 2,
+ "size": 1
+ },
+ "IV28": {
+ "description": "IV28",
+ "offset": 3,
+ "size": 1
+ },
+ "IV27": {
+ "description": "IV27",
+ "offset": 4,
+ "size": 1
+ },
+ "IV26": {
+ "description": "IV26",
+ "offset": 5,
+ "size": 1
+ },
+ "IV25": {
+ "description": "IV25",
+ "offset": 6,
+ "size": 1
+ },
+ "IV24": {
+ "description": "IV24",
+ "offset": 7,
+ "size": 1
+ },
+ "IV23": {
+ "description": "IV23",
+ "offset": 8,
+ "size": 1
+ },
+ "IV22": {
+ "description": "IV22",
+ "offset": 9,
+ "size": 1
+ },
+ "IV21": {
+ "description": "IV21",
+ "offset": 10,
+ "size": 1
+ },
+ "IV20": {
+ "description": "IV20",
+ "offset": 11,
+ "size": 1
+ },
+ "IV19": {
+ "description": "IV19",
+ "offset": 12,
+ "size": 1
+ },
+ "IV18": {
+ "description": "IV18",
+ "offset": 13,
+ "size": 1
+ },
+ "IV17": {
+ "description": "IV17",
+ "offset": 14,
+ "size": 1
+ },
+ "IV16": {
+ "description": "IV16",
+ "offset": 15,
+ "size": 1
+ },
+ "IV15": {
+ "description": "IV15",
+ "offset": 16,
+ "size": 1
+ },
+ "IV14": {
+ "description": "IV14",
+ "offset": 17,
+ "size": 1
+ },
+ "IV13": {
+ "description": "IV13",
+ "offset": 18,
+ "size": 1
+ },
+ "IV12": {
+ "description": "IV12",
+ "offset": 19,
+ "size": 1
+ },
+ "IV11": {
+ "description": "IV11",
+ "offset": 20,
+ "size": 1
+ },
+ "IV10": {
+ "description": "IV10",
+ "offset": 21,
+ "size": 1
+ },
+ "IV9": {
+ "description": "IV9",
+ "offset": 22,
+ "size": 1
+ },
+ "IV8": {
+ "description": "IV8",
+ "offset": 23,
+ "size": 1
+ },
+ "IV7": {
+ "description": "IV7",
+ "offset": 24,
+ "size": 1
+ },
+ "IV6": {
+ "description": "IV6",
+ "offset": 25,
+ "size": 1
+ },
+ "IV5": {
+ "description": "IV5",
+ "offset": 26,
+ "size": 1
+ },
+ "IV4": {
+ "description": "IV4",
+ "offset": 27,
+ "size": 1
+ },
+ "IV3": {
+ "description": "IV3",
+ "offset": 28,
+ "size": 1
+ },
+ "IV2": {
+ "description": "IV2",
+ "offset": 29,
+ "size": 1
+ },
+ "IV1": {
+ "description": "IV1",
+ "offset": 30,
+ "size": 1
+ },
+ "IV0": {
+ "description": "IV0",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "IV0RR": {
+ "description": "initialization vector\n registers",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IV63": {
+ "description": "IV63",
+ "offset": 0,
+ "size": 1
+ },
+ "IV62": {
+ "description": "IV62",
+ "offset": 1,
+ "size": 1
+ },
+ "IV61": {
+ "description": "IV61",
+ "offset": 2,
+ "size": 1
+ },
+ "IV60": {
+ "description": "IV60",
+ "offset": 3,
+ "size": 1
+ },
+ "IV59": {
+ "description": "IV59",
+ "offset": 4,
+ "size": 1
+ },
+ "IV58": {
+ "description": "IV58",
+ "offset": 5,
+ "size": 1
+ },
+ "IV57": {
+ "description": "IV57",
+ "offset": 6,
+ "size": 1
+ },
+ "IV56": {
+ "description": "IV56",
+ "offset": 7,
+ "size": 1
+ },
+ "IV55": {
+ "description": "IV55",
+ "offset": 8,
+ "size": 1
+ },
+ "IV54": {
+ "description": "IV54",
+ "offset": 9,
+ "size": 1
+ },
+ "IV53": {
+ "description": "IV53",
+ "offset": 10,
+ "size": 1
+ },
+ "IV52": {
+ "description": "IV52",
+ "offset": 11,
+ "size": 1
+ },
+ "IV51": {
+ "description": "IV51",
+ "offset": 12,
+ "size": 1
+ },
+ "IV50": {
+ "description": "IV50",
+ "offset": 13,
+ "size": 1
+ },
+ "IV49": {
+ "description": "IV49",
+ "offset": 14,
+ "size": 1
+ },
+ "IV48": {
+ "description": "IV48",
+ "offset": 15,
+ "size": 1
+ },
+ "IV47": {
+ "description": "IV47",
+ "offset": 16,
+ "size": 1
+ },
+ "IV46": {
+ "description": "IV46",
+ "offset": 17,
+ "size": 1
+ },
+ "IV45": {
+ "description": "IV45",
+ "offset": 18,
+ "size": 1
+ },
+ "IV44": {
+ "description": "IV44",
+ "offset": 19,
+ "size": 1
+ },
+ "IV43": {
+ "description": "IV43",
+ "offset": 20,
+ "size": 1
+ },
+ "IV42": {
+ "description": "IV42",
+ "offset": 21,
+ "size": 1
+ },
+ "IV41": {
+ "description": "IV41",
+ "offset": 22,
+ "size": 1
+ },
+ "IV40": {
+ "description": "IV40",
+ "offset": 23,
+ "size": 1
+ },
+ "IV39": {
+ "description": "IV39",
+ "offset": 24,
+ "size": 1
+ },
+ "IV38": {
+ "description": "IV38",
+ "offset": 25,
+ "size": 1
+ },
+ "IV37": {
+ "description": "IV37",
+ "offset": 26,
+ "size": 1
+ },
+ "IV36": {
+ "description": "IV36",
+ "offset": 27,
+ "size": 1
+ },
+ "IV35": {
+ "description": "IV35",
+ "offset": 28,
+ "size": 1
+ },
+ "IV34": {
+ "description": "IV34",
+ "offset": 29,
+ "size": 1
+ },
+ "IV33": {
+ "description": "IV33",
+ "offset": 30,
+ "size": 1
+ },
+ "IV32": {
+ "description": "IV32",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "IV1LR": {
+ "description": "initialization vector\n registers",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IV95": {
+ "description": "IV95",
+ "offset": 0,
+ "size": 1
+ },
+ "IV94": {
+ "description": "IV94",
+ "offset": 1,
+ "size": 1
+ },
+ "IV93": {
+ "description": "IV93",
+ "offset": 2,
+ "size": 1
+ },
+ "IV92": {
+ "description": "IV92",
+ "offset": 3,
+ "size": 1
+ },
+ "IV91": {
+ "description": "IV91",
+ "offset": 4,
+ "size": 1
+ },
+ "IV90": {
+ "description": "IV90",
+ "offset": 5,
+ "size": 1
+ },
+ "IV89": {
+ "description": "IV89",
+ "offset": 6,
+ "size": 1
+ },
+ "IV88": {
+ "description": "IV88",
+ "offset": 7,
+ "size": 1
+ },
+ "IV87": {
+ "description": "IV87",
+ "offset": 8,
+ "size": 1
+ },
+ "IV86": {
+ "description": "IV86",
+ "offset": 9,
+ "size": 1
+ },
+ "IV85": {
+ "description": "IV85",
+ "offset": 10,
+ "size": 1
+ },
+ "IV84": {
+ "description": "IV84",
+ "offset": 11,
+ "size": 1
+ },
+ "IV83": {
+ "description": "IV83",
+ "offset": 12,
+ "size": 1
+ },
+ "IV82": {
+ "description": "IV82",
+ "offset": 13,
+ "size": 1
+ },
+ "IV81": {
+ "description": "IV81",
+ "offset": 14,
+ "size": 1
+ },
+ "IV80": {
+ "description": "IV80",
+ "offset": 15,
+ "size": 1
+ },
+ "IV79": {
+ "description": "IV79",
+ "offset": 16,
+ "size": 1
+ },
+ "IV78": {
+ "description": "IV78",
+ "offset": 17,
+ "size": 1
+ },
+ "IV77": {
+ "description": "IV77",
+ "offset": 18,
+ "size": 1
+ },
+ "IV76": {
+ "description": "IV76",
+ "offset": 19,
+ "size": 1
+ },
+ "IV75": {
+ "description": "IV75",
+ "offset": 20,
+ "size": 1
+ },
+ "IV74": {
+ "description": "IV74",
+ "offset": 21,
+ "size": 1
+ },
+ "IV73": {
+ "description": "IV73",
+ "offset": 22,
+ "size": 1
+ },
+ "IV72": {
+ "description": "IV72",
+ "offset": 23,
+ "size": 1
+ },
+ "IV71": {
+ "description": "IV71",
+ "offset": 24,
+ "size": 1
+ },
+ "IV70": {
+ "description": "IV70",
+ "offset": 25,
+ "size": 1
+ },
+ "IV69": {
+ "description": "IV69",
+ "offset": 26,
+ "size": 1
+ },
+ "IV68": {
+ "description": "IV68",
+ "offset": 27,
+ "size": 1
+ },
+ "IV67": {
+ "description": "IV67",
+ "offset": 28,
+ "size": 1
+ },
+ "IV66": {
+ "description": "IV66",
+ "offset": 29,
+ "size": 1
+ },
+ "IV65": {
+ "description": "IV65",
+ "offset": 30,
+ "size": 1
+ },
+ "IV64": {
+ "description": "IV64",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "IV1RR": {
+ "description": "initialization vector\n registers",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IV127": {
+ "description": "IV127",
+ "offset": 0,
+ "size": 1
+ },
+ "IV126": {
+ "description": "IV126",
+ "offset": 1,
+ "size": 1
+ },
+ "IV125": {
+ "description": "IV125",
+ "offset": 2,
+ "size": 1
+ },
+ "IV124": {
+ "description": "IV124",
+ "offset": 3,
+ "size": 1
+ },
+ "IV123": {
+ "description": "IV123",
+ "offset": 4,
+ "size": 1
+ },
+ "IV122": {
+ "description": "IV122",
+ "offset": 5,
+ "size": 1
+ },
+ "IV121": {
+ "description": "IV121",
+ "offset": 6,
+ "size": 1
+ },
+ "IV120": {
+ "description": "IV120",
+ "offset": 7,
+ "size": 1
+ },
+ "IV119": {
+ "description": "IV119",
+ "offset": 8,
+ "size": 1
+ },
+ "IV118": {
+ "description": "IV118",
+ "offset": 9,
+ "size": 1
+ },
+ "IV117": {
+ "description": "IV117",
+ "offset": 10,
+ "size": 1
+ },
+ "IV116": {
+ "description": "IV116",
+ "offset": 11,
+ "size": 1
+ },
+ "IV115": {
+ "description": "IV115",
+ "offset": 12,
+ "size": 1
+ },
+ "IV114": {
+ "description": "IV114",
+ "offset": 13,
+ "size": 1
+ },
+ "IV113": {
+ "description": "IV113",
+ "offset": 14,
+ "size": 1
+ },
+ "IV112": {
+ "description": "IV112",
+ "offset": 15,
+ "size": 1
+ },
+ "IV111": {
+ "description": "IV111",
+ "offset": 16,
+ "size": 1
+ },
+ "IV110": {
+ "description": "IV110",
+ "offset": 17,
+ "size": 1
+ },
+ "IV109": {
+ "description": "IV109",
+ "offset": 18,
+ "size": 1
+ },
+ "IV108": {
+ "description": "IV108",
+ "offset": 19,
+ "size": 1
+ },
+ "IV107": {
+ "description": "IV107",
+ "offset": 20,
+ "size": 1
+ },
+ "IV106": {
+ "description": "IV106",
+ "offset": 21,
+ "size": 1
+ },
+ "IV105": {
+ "description": "IV105",
+ "offset": 22,
+ "size": 1
+ },
+ "IV104": {
+ "description": "IV104",
+ "offset": 23,
+ "size": 1
+ },
+ "IV103": {
+ "description": "IV103",
+ "offset": 24,
+ "size": 1
+ },
+ "IV102": {
+ "description": "IV102",
+ "offset": 25,
+ "size": 1
+ },
+ "IV101": {
+ "description": "IV101",
+ "offset": 26,
+ "size": 1
+ },
+ "IV100": {
+ "description": "IV100",
+ "offset": 27,
+ "size": 1
+ },
+ "IV99": {
+ "description": "IV99",
+ "offset": 28,
+ "size": 1
+ },
+ "IV98": {
+ "description": "IV98",
+ "offset": 29,
+ "size": 1
+ },
+ "IV97": {
+ "description": "IV97",
+ "offset": 30,
+ "size": 1
+ },
+ "IV96": {
+ "description": "IV96",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CSGCMCCM0R": {
+ "description": "context swap register",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSGCMCCM0R": {
+ "description": "CSGCMCCM0R",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCMCCM1R": {
+ "description": "context swap register",
+ "offset": 84,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSGCMCCM1R": {
+ "description": "CSGCMCCM1R",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCMCCM2R": {
+ "description": "context swap register",
+ "offset": 88,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSGCMCCM2R": {
+ "description": "CSGCMCCM2R",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCMCCM3R": {
+ "description": "context swap register",
+ "offset": 92,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSGCMCCM3R": {
+ "description": "CSGCMCCM3R",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCMCCM4R": {
+ "description": "context swap register",
+ "offset": 96,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSGCMCCM4R": {
+ "description": "CSGCMCCM4R",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCMCCM5R": {
+ "description": "context swap register",
+ "offset": 100,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSGCMCCM5R": {
+ "description": "CSGCMCCM5R",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCMCCM6R": {
+ "description": "context swap register",
+ "offset": 104,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSGCMCCM6R": {
+ "description": "CSGCMCCM6R",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCMCCM7R": {
+ "description": "context swap register",
+ "offset": 108,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSGCMCCM7R": {
+ "description": "CSGCMCCM7R",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCM0R": {
+ "description": "context swap register",
+ "offset": 112,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSGCM0R": {
+ "description": "CSGCM0R",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCM1R": {
+ "description": "context swap register",
+ "offset": 116,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSGCM1R": {
+ "description": "CSGCM1R",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCM2R": {
+ "description": "context swap register",
+ "offset": 120,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSGCM2R": {
+ "description": "CSGCM2R",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCM3R": {
+ "description": "context swap register",
+ "offset": 124,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSGCM3R": {
+ "description": "CSGCM3R",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCM4R": {
+ "description": "context swap register",
+ "offset": 128,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSGCM4R": {
+ "description": "CSGCM4R",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCM5R": {
+ "description": "context swap register",
+ "offset": 132,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSGCM5R": {
+ "description": "CSGCM5R",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCM6R": {
+ "description": "context swap register",
+ "offset": 136,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSGCM6R": {
+ "description": "CSGCM6R",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCM7R": {
+ "description": "context swap register",
+ "offset": 140,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSGCM7R": {
+ "description": "CSGCM7R",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "HASH": {
+ "description": "Hash processor",
+ "children": {
+ "registers": {
+ "CR": {
+ "description": "control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INIT": {
+ "description": "Initialize message digest\n calculation",
+ "offset": 2,
+ "size": 1,
+ "access": "write-only"
+ },
+ "DMAE": {
+ "description": "DMA enable",
+ "offset": 3,
+ "size": 1
+ },
+ "DATATYPE": {
+ "description": "Data type selection",
+ "offset": 4,
+ "size": 2
+ },
+ "MODE": {
+ "description": "Mode selection",
+ "offset": 6,
+ "size": 1
+ },
+ "ALGO0": {
+ "description": "Algorithm selection",
+ "offset": 7,
+ "size": 1
+ },
+ "NBW": {
+ "description": "Number of words already\n pushed",
+ "offset": 8,
+ "size": 4,
+ "access": "read-only"
+ },
+ "DINNE": {
+ "description": "DIN not empty",
+ "offset": 12,
+ "size": 1,
+ "access": "read-only"
+ },
+ "MDMAT": {
+ "description": "Multiple DMA Transfers",
+ "offset": 13,
+ "size": 1
+ },
+ "LKEY": {
+ "description": "Long key selection",
+ "offset": 16,
+ "size": 1
+ },
+ "ALGO1": {
+ "description": "ALGO",
+ "offset": 18,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DIN": {
+ "description": "data input register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATAIN": {
+ "description": "Data input",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "STR": {
+ "description": "start register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DCAL": {
+ "description": "Digest calculation",
+ "offset": 8,
+ "size": 1,
+ "access": "write-only"
+ },
+ "NBLW": {
+ "description": "Number of valid bits in the last word of\n the message",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "HR0": {
+ "description": "digest registers",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "H0": {
+ "description": "H0",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "HR1": {
+ "description": "digest registers",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "H1": {
+ "description": "H1",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "HR2": {
+ "description": "digest registers",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "H2": {
+ "description": "H2",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "HR3": {
+ "description": "digest registers",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "H3": {
+ "description": "H3",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "HR4": {
+ "description": "digest registers",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "H4": {
+ "description": "H4",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "IMR": {
+ "description": "interrupt enable register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DCIE": {
+ "description": "Digest calculation completion interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "DINIE": {
+ "description": "Data input interrupt\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 1,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BUSY": {
+ "description": "Busy bit",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "DMAS": {
+ "description": "DMA Status",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "DCIS": {
+ "description": "Digest calculation completion interrupt\n status",
+ "offset": 1,
+ "size": 1
+ },
+ "DINIS": {
+ "description": "Data input interrupt\n status",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CSR0": {
+ "description": "context swap registers",
+ "offset": 248,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR0": {
+ "description": "CSR0",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR1": {
+ "description": "context swap registers",
+ "offset": 252,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR1": {
+ "description": "CSR1",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR2": {
+ "description": "context swap registers",
+ "offset": 256,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR2": {
+ "description": "CSR2",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR3": {
+ "description": "context swap registers",
+ "offset": 260,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR3": {
+ "description": "CSR3",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR4": {
+ "description": "context swap registers",
+ "offset": 264,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR4": {
+ "description": "CSR4",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR5": {
+ "description": "context swap registers",
+ "offset": 268,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR5": {
+ "description": "CSR5",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR6": {
+ "description": "context swap registers",
+ "offset": 272,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR6": {
+ "description": "CSR6",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR7": {
+ "description": "context swap registers",
+ "offset": 276,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR7": {
+ "description": "CSR7",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR8": {
+ "description": "context swap registers",
+ "offset": 280,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR8": {
+ "description": "CSR8",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR9": {
+ "description": "context swap registers",
+ "offset": 284,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR9": {
+ "description": "CSR9",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR10": {
+ "description": "context swap registers",
+ "offset": 288,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR10": {
+ "description": "CSR10",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR11": {
+ "description": "context swap registers",
+ "offset": 292,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR11": {
+ "description": "CSR11",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR12": {
+ "description": "context swap registers",
+ "offset": 296,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR12": {
+ "description": "CSR12",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR13": {
+ "description": "context swap registers",
+ "offset": 300,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR13": {
+ "description": "CSR13",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR14": {
+ "description": "context swap registers",
+ "offset": 304,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR14": {
+ "description": "CSR14",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR15": {
+ "description": "context swap registers",
+ "offset": 308,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR15": {
+ "description": "CSR15",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR16": {
+ "description": "context swap registers",
+ "offset": 312,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR16": {
+ "description": "CSR16",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR17": {
+ "description": "context swap registers",
+ "offset": 316,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR17": {
+ "description": "CSR17",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR18": {
+ "description": "context swap registers",
+ "offset": 320,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR18": {
+ "description": "CSR18",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR19": {
+ "description": "context swap registers",
+ "offset": 324,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR19": {
+ "description": "CSR19",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR20": {
+ "description": "context swap registers",
+ "offset": 328,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR20": {
+ "description": "CSR20",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR21": {
+ "description": "context swap registers",
+ "offset": 332,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR21": {
+ "description": "CSR21",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR22": {
+ "description": "context swap registers",
+ "offset": 336,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR22": {
+ "description": "CSR22",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR23": {
+ "description": "context swap registers",
+ "offset": 340,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR23": {
+ "description": "CSR23",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR24": {
+ "description": "context swap registers",
+ "offset": 344,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR24": {
+ "description": "CSR24",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR25": {
+ "description": "context swap registers",
+ "offset": 348,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR25": {
+ "description": "CSR25",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR26": {
+ "description": "context swap registers",
+ "offset": 352,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR26": {
+ "description": "CSR26",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR27": {
+ "description": "context swap registers",
+ "offset": 356,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR27": {
+ "description": "CSR27",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR28": {
+ "description": "context swap registers",
+ "offset": 360,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR28": {
+ "description": "CSR28",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR29": {
+ "description": "context swap registers",
+ "offset": 364,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR29": {
+ "description": "CSR29",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR30": {
+ "description": "context swap registers",
+ "offset": 368,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR30": {
+ "description": "CSR30",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR31": {
+ "description": "context swap registers",
+ "offset": 372,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR31": {
+ "description": "CSR31",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR32": {
+ "description": "context swap registers",
+ "offset": 376,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR32": {
+ "description": "CSR32",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR33": {
+ "description": "context swap registers",
+ "offset": 380,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR33": {
+ "description": "CSR33",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR34": {
+ "description": "context swap registers",
+ "offset": 384,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR34": {
+ "description": "CSR34",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR35": {
+ "description": "context swap registers",
+ "offset": 388,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR35": {
+ "description": "CSR35",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR36": {
+ "description": "context swap registers",
+ "offset": 392,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR36": {
+ "description": "CSR36",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR37": {
+ "description": "context swap registers",
+ "offset": 396,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR37": {
+ "description": "CSR37",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR38": {
+ "description": "context swap registers",
+ "offset": 400,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR38": {
+ "description": "CSR38",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR39": {
+ "description": "context swap registers",
+ "offset": 404,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR39": {
+ "description": "CSR39",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR40": {
+ "description": "context swap registers",
+ "offset": 408,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR40": {
+ "description": "CSR40",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR41": {
+ "description": "context swap registers",
+ "offset": 412,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR41": {
+ "description": "CSR41",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR42": {
+ "description": "context swap registers",
+ "offset": 416,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR42": {
+ "description": "CSR42",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR43": {
+ "description": "context swap registers",
+ "offset": 420,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR43": {
+ "description": "CSR43",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR44": {
+ "description": "context swap registers",
+ "offset": 424,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR44": {
+ "description": "CSR44",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR45": {
+ "description": "context swap registers",
+ "offset": 428,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR45": {
+ "description": "CSR45",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR46": {
+ "description": "context swap registers",
+ "offset": 432,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR46": {
+ "description": "CSR46",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR47": {
+ "description": "context swap registers",
+ "offset": 436,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR47": {
+ "description": "CSR47",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR48": {
+ "description": "context swap registers",
+ "offset": 440,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR48": {
+ "description": "CSR48",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR49": {
+ "description": "context swap registers",
+ "offset": 444,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR49": {
+ "description": "CSR49",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR50": {
+ "description": "context swap registers",
+ "offset": 448,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR50": {
+ "description": "CSR50",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR51": {
+ "description": "context swap registers",
+ "offset": 452,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR51": {
+ "description": "CSR51",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR52": {
+ "description": "context swap registers",
+ "offset": 456,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR52": {
+ "description": "CSR52",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR53": {
+ "description": "context swap registers",
+ "offset": 460,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR53": {
+ "description": "CSR53",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "HASH_HR0": {
+ "description": "HASH digest register",
+ "offset": 784,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "H0": {
+ "description": "H0",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "HASH_HR1": {
+ "description": "read-only",
+ "offset": 788,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "H1": {
+ "description": "H1",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "HASH_HR2": {
+ "description": "read-only",
+ "offset": 792,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "H2": {
+ "description": "H2",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "HASH_HR3": {
+ "description": "read-only",
+ "offset": 796,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "H3": {
+ "description": "H3",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "HASH_HR4": {
+ "description": "read-only",
+ "offset": 800,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "H4": {
+ "description": "H4",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "HASH_HR5": {
+ "description": "read-only",
+ "offset": 804,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "H5": {
+ "description": "H5",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "HASH_HR6": {
+ "description": "read-only",
+ "offset": 808,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "H6": {
+ "description": "H6",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "HASH_HR7": {
+ "description": "read-only",
+ "offset": 812,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "H7": {
+ "description": "H7",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "GPIOB": {
+ "description": "General-purpose I/Os",
+ "children": {
+ "registers": {
+ "MODER": {
+ "description": "GPIO port mode register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 640,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MODER15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 30,
+ "size": 2
+ },
+ "MODER14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 28,
+ "size": 2
+ },
+ "MODER13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 26,
+ "size": 2
+ },
+ "MODER12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 24,
+ "size": 2
+ },
+ "MODER11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 22,
+ "size": 2
+ },
+ "MODER10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 20,
+ "size": 2
+ },
+ "MODER9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 18,
+ "size": 2
+ },
+ "MODER8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 16,
+ "size": 2
+ },
+ "MODER7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 2
+ },
+ "MODER6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 2
+ },
+ "MODER5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 2
+ },
+ "MODER4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 2
+ },
+ "MODER3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 2
+ },
+ "MODER2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 2
+ },
+ "MODER1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 2
+ },
+ "MODER0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTYPER": {
+ "description": "GPIO port output type register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OT15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "OT14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "OT13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "OT12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "OT11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "OT10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "OT9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "OT8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "OT7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "OT6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "OT5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "OT4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "OT3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "OT2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "OT1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "OT0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OSPEEDR": {
+ "description": "GPIO port output speed\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 192,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OSPEEDR15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 30,
+ "size": 2
+ },
+ "OSPEEDR14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 28,
+ "size": 2
+ },
+ "OSPEEDR13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 26,
+ "size": 2
+ },
+ "OSPEEDR12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 24,
+ "size": 2
+ },
+ "OSPEEDR11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 22,
+ "size": 2
+ },
+ "OSPEEDR10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 20,
+ "size": 2
+ },
+ "OSPEEDR9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 18,
+ "size": 2
+ },
+ "OSPEEDR8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 16,
+ "size": 2
+ },
+ "OSPEEDR7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 2
+ },
+ "OSPEEDR6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 2
+ },
+ "OSPEEDR5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 2
+ },
+ "OSPEEDR4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 2
+ },
+ "OSPEEDR3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 2
+ },
+ "OSPEEDR2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 2
+ },
+ "OSPEEDR1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 2
+ },
+ "OSPEEDR0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "PUPDR": {
+ "description": "GPIO port pull-up/pull-down\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 256,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PUPDR15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 30,
+ "size": 2
+ },
+ "PUPDR14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 28,
+ "size": 2
+ },
+ "PUPDR13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 26,
+ "size": 2
+ },
+ "PUPDR12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 24,
+ "size": 2
+ },
+ "PUPDR11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 22,
+ "size": 2
+ },
+ "PUPDR10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 20,
+ "size": 2
+ },
+ "PUPDR9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 18,
+ "size": 2
+ },
+ "PUPDR8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 16,
+ "size": 2
+ },
+ "PUPDR7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 2
+ },
+ "PUPDR6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 2
+ },
+ "PUPDR5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 2
+ },
+ "PUPDR4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 2
+ },
+ "PUPDR3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 2
+ },
+ "PUPDR2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 2
+ },
+ "PUPDR1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 2
+ },
+ "PUPDR0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "IDR": {
+ "description": "GPIO port input data register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "IDR15": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "IDR14": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "IDR13": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "IDR12": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "IDR11": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "IDR10": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "IDR9": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "IDR8": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "IDR7": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "IDR6": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "IDR5": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "IDR4": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "IDR3": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "IDR2": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "IDR1": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "IDR0": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ODR": {
+ "description": "GPIO port output data register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ODR15": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "ODR14": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "ODR13": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "ODR12": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "ODR11": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "ODR10": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "ODR9": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "ODR8": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "ODR7": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "ODR6": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "ODR5": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "ODR4": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "ODR3": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "ODR2": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "ODR1": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "ODR0": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BSRR": {
+ "description": "GPIO port bit set/reset\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "BR15": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 31,
+ "size": 1
+ },
+ "BR14": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 30,
+ "size": 1
+ },
+ "BR13": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 29,
+ "size": 1
+ },
+ "BR12": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 28,
+ "size": 1
+ },
+ "BR11": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 27,
+ "size": 1
+ },
+ "BR10": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 26,
+ "size": 1
+ },
+ "BR9": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 25,
+ "size": 1
+ },
+ "BR8": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 24,
+ "size": 1
+ },
+ "BR7": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 23,
+ "size": 1
+ },
+ "BR6": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 22,
+ "size": 1
+ },
+ "BR5": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 21,
+ "size": 1
+ },
+ "BR4": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 20,
+ "size": 1
+ },
+ "BR3": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 19,
+ "size": 1
+ },
+ "BR2": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 18,
+ "size": 1
+ },
+ "BR1": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 17,
+ "size": 1
+ },
+ "BR0": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 16,
+ "size": 1
+ },
+ "BS15": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "BS14": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "BS13": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "BS12": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "BS11": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "BS10": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "BS9": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "BS8": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "BS7": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "BS6": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "BS5": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "BS4": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "BS3": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "BS2": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "BS1": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "BS0": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "LCKR": {
+ "description": "GPIO port configuration lock\n register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LCKK": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 16,
+ "size": 1
+ },
+ "LCK15": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "LCK14": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "LCK13": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "LCK12": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "LCK11": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "LCK10": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "LCK9": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "LCK8": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "LCK7": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "LCK6": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "LCK5": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "LCK4": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "LCK3": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "LCK2": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "LCK1": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "LCK0": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "AFRL": {
+ "description": "GPIO alternate function low\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "AFRL7": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 28,
+ "size": 4
+ },
+ "AFRL6": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 24,
+ "size": 4
+ },
+ "AFRL5": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 20,
+ "size": 4
+ },
+ "AFRL4": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 16,
+ "size": 4
+ },
+ "AFRL3": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 12,
+ "size": 4
+ },
+ "AFRL2": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 8,
+ "size": 4
+ },
+ "AFRL1": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 4,
+ "size": 4
+ },
+ "AFRL0": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "AFRH": {
+ "description": "GPIO alternate function high\n register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "AFRH15": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 28,
+ "size": 4
+ },
+ "AFRH14": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 24,
+ "size": 4
+ },
+ "AFRH13": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 20,
+ "size": 4
+ },
+ "AFRH12": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 16,
+ "size": 4
+ },
+ "AFRH11": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 12,
+ "size": 4
+ },
+ "AFRH10": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 8,
+ "size": 4
+ },
+ "AFRH9": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 4,
+ "size": 4
+ },
+ "AFRH8": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "GPIOA": {
+ "description": "General-purpose I/Os",
+ "children": {
+ "registers": {
+ "MODER": {
+ "description": "GPIO port mode register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 2818572288,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MODER15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 30,
+ "size": 2
+ },
+ "MODER14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 28,
+ "size": 2
+ },
+ "MODER13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 26,
+ "size": 2
+ },
+ "MODER12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 24,
+ "size": 2
+ },
+ "MODER11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 22,
+ "size": 2
+ },
+ "MODER10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 20,
+ "size": 2
+ },
+ "MODER9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 18,
+ "size": 2
+ },
+ "MODER8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 16,
+ "size": 2
+ },
+ "MODER7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 2
+ },
+ "MODER6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 2
+ },
+ "MODER5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 2
+ },
+ "MODER4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 2
+ },
+ "MODER3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 2
+ },
+ "MODER2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 2
+ },
+ "MODER1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 2
+ },
+ "MODER0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTYPER": {
+ "description": "GPIO port output type register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OT15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "OT14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "OT13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "OT12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "OT11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "OT10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "OT9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "OT8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "OT7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "OT6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "OT5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "OT4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "OT3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "OT2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "OT1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "OT0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OSPEEDR": {
+ "description": "GPIO port output speed\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OSPEEDR15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 30,
+ "size": 2
+ },
+ "OSPEEDR14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 28,
+ "size": 2
+ },
+ "OSPEEDR13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 26,
+ "size": 2
+ },
+ "OSPEEDR12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 24,
+ "size": 2
+ },
+ "OSPEEDR11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 22,
+ "size": 2
+ },
+ "OSPEEDR10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 20,
+ "size": 2
+ },
+ "OSPEEDR9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 18,
+ "size": 2
+ },
+ "OSPEEDR8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 16,
+ "size": 2
+ },
+ "OSPEEDR7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 2
+ },
+ "OSPEEDR6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 2
+ },
+ "OSPEEDR5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 2
+ },
+ "OSPEEDR4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 2
+ },
+ "OSPEEDR3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 2
+ },
+ "OSPEEDR2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 2
+ },
+ "OSPEEDR1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 2
+ },
+ "OSPEEDR0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "PUPDR": {
+ "description": "GPIO port pull-up/pull-down\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 1677721600,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PUPDR15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 30,
+ "size": 2
+ },
+ "PUPDR14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 28,
+ "size": 2
+ },
+ "PUPDR13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 26,
+ "size": 2
+ },
+ "PUPDR12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 24,
+ "size": 2
+ },
+ "PUPDR11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 22,
+ "size": 2
+ },
+ "PUPDR10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 20,
+ "size": 2
+ },
+ "PUPDR9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 18,
+ "size": 2
+ },
+ "PUPDR8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 16,
+ "size": 2
+ },
+ "PUPDR7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 2
+ },
+ "PUPDR6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 2
+ },
+ "PUPDR5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 2
+ },
+ "PUPDR4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 2
+ },
+ "PUPDR3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 2
+ },
+ "PUPDR2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 2
+ },
+ "PUPDR1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 2
+ },
+ "PUPDR0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "IDR": {
+ "description": "GPIO port input data register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "IDR15": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "IDR14": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "IDR13": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "IDR12": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "IDR11": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "IDR10": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "IDR9": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "IDR8": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "IDR7": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "IDR6": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "IDR5": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "IDR4": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "IDR3": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "IDR2": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "IDR1": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "IDR0": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ODR": {
+ "description": "GPIO port output data register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ODR15": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "ODR14": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "ODR13": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "ODR12": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "ODR11": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "ODR10": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "ODR9": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "ODR8": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "ODR7": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "ODR6": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "ODR5": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "ODR4": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "ODR3": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "ODR2": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "ODR1": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "ODR0": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BSRR": {
+ "description": "GPIO port bit set/reset\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "BR15": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 31,
+ "size": 1
+ },
+ "BR14": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 30,
+ "size": 1
+ },
+ "BR13": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 29,
+ "size": 1
+ },
+ "BR12": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 28,
+ "size": 1
+ },
+ "BR11": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 27,
+ "size": 1
+ },
+ "BR10": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 26,
+ "size": 1
+ },
+ "BR9": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 25,
+ "size": 1
+ },
+ "BR8": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 24,
+ "size": 1
+ },
+ "BR7": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 23,
+ "size": 1
+ },
+ "BR6": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 22,
+ "size": 1
+ },
+ "BR5": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 21,
+ "size": 1
+ },
+ "BR4": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 20,
+ "size": 1
+ },
+ "BR3": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 19,
+ "size": 1
+ },
+ "BR2": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 18,
+ "size": 1
+ },
+ "BR1": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 17,
+ "size": 1
+ },
+ "BR0": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 16,
+ "size": 1
+ },
+ "BS15": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "BS14": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "BS13": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "BS12": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "BS11": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "BS10": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "BS9": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "BS8": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "BS7": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "BS6": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "BS5": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "BS4": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "BS3": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "BS2": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "BS1": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "BS0": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "LCKR": {
+ "description": "GPIO port configuration lock\n register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LCKK": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 16,
+ "size": 1
+ },
+ "LCK15": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "LCK14": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "LCK13": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "LCK12": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "LCK11": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "LCK10": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "LCK9": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "LCK8": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "LCK7": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "LCK6": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "LCK5": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "LCK4": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "LCK3": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "LCK2": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "LCK1": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "LCK0": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "AFRL": {
+ "description": "GPIO alternate function low\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "AFRL7": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 28,
+ "size": 4
+ },
+ "AFRL6": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 24,
+ "size": 4
+ },
+ "AFRL5": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 20,
+ "size": 4
+ },
+ "AFRL4": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 16,
+ "size": 4
+ },
+ "AFRL3": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 12,
+ "size": 4
+ },
+ "AFRL2": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 8,
+ "size": 4
+ },
+ "AFRL1": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 4,
+ "size": 4
+ },
+ "AFRL0": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "AFRH": {
+ "description": "GPIO alternate function high\n register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "AFRH15": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 28,
+ "size": 4
+ },
+ "AFRH14": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 24,
+ "size": 4
+ },
+ "AFRH13": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 20,
+ "size": 4
+ },
+ "AFRH12": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 16,
+ "size": 4
+ },
+ "AFRH11": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 12,
+ "size": 4
+ },
+ "AFRH10": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 8,
+ "size": 4
+ },
+ "AFRH9": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 4,
+ "size": 4
+ },
+ "AFRH8": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "SYSCFG": {
+ "description": "System configuration controller",
+ "children": {
+ "registers": {
+ "MEMRM": {
+ "description": "memory remap register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MEM_MODE": {
+ "description": "MEM_MODE",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "PMC": {
+ "description": "peripheral mode configuration\n register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MII_RMII_SEL": {
+ "description": "Ethernet PHY interface\n selection",
+ "offset": 23,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EXTICR1": {
+ "description": "external interrupt configuration register\n 1",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EXTI3": {
+ "description": "EXTI x configuration (x = 0 to\n 3)",
+ "offset": 12,
+ "size": 4
+ },
+ "EXTI2": {
+ "description": "EXTI x configuration (x = 0 to\n 3)",
+ "offset": 8,
+ "size": 4
+ },
+ "EXTI1": {
+ "description": "EXTI x configuration (x = 0 to\n 3)",
+ "offset": 4,
+ "size": 4
+ },
+ "EXTI0": {
+ "description": "EXTI x configuration (x = 0 to\n 3)",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "EXTICR2": {
+ "description": "external interrupt configuration register\n 2",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EXTI7": {
+ "description": "EXTI x configuration (x = 4 to\n 7)",
+ "offset": 12,
+ "size": 4
+ },
+ "EXTI6": {
+ "description": "EXTI x configuration (x = 4 to\n 7)",
+ "offset": 8,
+ "size": 4
+ },
+ "EXTI5": {
+ "description": "EXTI x configuration (x = 4 to\n 7)",
+ "offset": 4,
+ "size": 4
+ },
+ "EXTI4": {
+ "description": "EXTI x configuration (x = 4 to\n 7)",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "EXTICR3": {
+ "description": "external interrupt configuration register\n 3",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EXTI11": {
+ "description": "EXTI x configuration (x = 8 to\n 11)",
+ "offset": 12,
+ "size": 4
+ },
+ "EXTI10": {
+ "description": "EXTI10",
+ "offset": 8,
+ "size": 4
+ },
+ "EXTI9": {
+ "description": "EXTI x configuration (x = 8 to\n 11)",
+ "offset": 4,
+ "size": 4
+ },
+ "EXTI8": {
+ "description": "EXTI x configuration (x = 8 to\n 11)",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "EXTICR4": {
+ "description": "external interrupt configuration register\n 4",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EXTI15": {
+ "description": "EXTI x configuration (x = 12 to\n 15)",
+ "offset": 12,
+ "size": 4
+ },
+ "EXTI14": {
+ "description": "EXTI x configuration (x = 12 to\n 15)",
+ "offset": 8,
+ "size": 4
+ },
+ "EXTI13": {
+ "description": "EXTI x configuration (x = 12 to\n 15)",
+ "offset": 4,
+ "size": 4
+ },
+ "EXTI12": {
+ "description": "EXTI x configuration (x = 12 to\n 15)",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "CMPCR": {
+ "description": "Compensation cell control\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "READY": {
+ "description": "READY",
+ "offset": 8,
+ "size": 1
+ },
+ "CMP_PD": {
+ "description": "Compensation cell\n power-down",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "SPI1": {
+ "description": "Serial peripheral interface",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BIDIMODE": {
+ "description": "Bidirectional data mode\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "BIDIOE": {
+ "description": "Output enable in bidirectional\n mode",
+ "offset": 14,
+ "size": 1
+ },
+ "CRCEN": {
+ "description": "Hardware CRC calculation\n enable",
+ "offset": 13,
+ "size": 1
+ },
+ "CRCNEXT": {
+ "description": "CRC transfer next",
+ "offset": 12,
+ "size": 1
+ },
+ "DFF": {
+ "description": "Data frame format",
+ "offset": 11,
+ "size": 1
+ },
+ "RXONLY": {
+ "description": "Receive only",
+ "offset": 10,
+ "size": 1
+ },
+ "SSM": {
+ "description": "Software slave management",
+ "offset": 9,
+ "size": 1
+ },
+ "SSI": {
+ "description": "Internal slave select",
+ "offset": 8,
+ "size": 1
+ },
+ "LSBFIRST": {
+ "description": "Frame format",
+ "offset": 7,
+ "size": 1
+ },
+ "SPE": {
+ "description": "SPI enable",
+ "offset": 6,
+ "size": 1
+ },
+ "BR": {
+ "description": "Baud rate control",
+ "offset": 3,
+ "size": 3
+ },
+ "MSTR": {
+ "description": "Master selection",
+ "offset": 2,
+ "size": 1
+ },
+ "CPOL": {
+ "description": "Clock polarity",
+ "offset": 1,
+ "size": 1
+ },
+ "CPHA": {
+ "description": "Clock phase",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TXEIE": {
+ "description": "Tx buffer empty interrupt\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "RXNEIE": {
+ "description": "RX buffer not empty interrupt\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "ERRIE": {
+ "description": "Error interrupt enable",
+ "offset": 5,
+ "size": 1
+ },
+ "FRF": {
+ "description": "Frame format",
+ "offset": 4,
+ "size": 1
+ },
+ "SSOE": {
+ "description": "SS output enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TXDMAEN": {
+ "description": "Tx buffer DMA enable",
+ "offset": 1,
+ "size": 1
+ },
+ "RXDMAEN": {
+ "description": "Rx buffer DMA enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 2,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIFRFE": {
+ "description": "TI frame format error",
+ "offset": 8,
+ "size": 1,
+ "access": "read-only"
+ },
+ "BSY": {
+ "description": "Busy flag",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "OVR": {
+ "description": "Overrun flag",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "MODF": {
+ "description": "Mode fault",
+ "offset": 5,
+ "size": 1,
+ "access": "read-only"
+ },
+ "CRCERR": {
+ "description": "CRC error flag",
+ "offset": 4,
+ "size": 1
+ },
+ "UDR": {
+ "description": "Underrun flag",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "CHSIDE": {
+ "description": "Channel side",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TXE": {
+ "description": "Transmit buffer empty",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "RXNE": {
+ "description": "Receive buffer not empty",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "DR": {
+ "description": "data register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DR": {
+ "description": "Data register",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CRCPR": {
+ "description": "CRC polynomial register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 7,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CRCPOLY": {
+ "description": "CRC polynomial register",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "RXCRCR": {
+ "description": "RX CRC register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "RxCRC": {
+ "description": "Rx CRC register",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "TXCRCR": {
+ "description": "TX CRC register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "TxCRC": {
+ "description": "Tx CRC register",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "I2SCFGR": {
+ "description": "I2S configuration register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "I2SMOD": {
+ "description": "I2S mode selection",
+ "offset": 11,
+ "size": 1
+ },
+ "I2SE": {
+ "description": "I2S Enable",
+ "offset": 10,
+ "size": 1
+ },
+ "I2SCFG": {
+ "description": "I2S configuration mode",
+ "offset": 8,
+ "size": 2
+ },
+ "PCMSYNC": {
+ "description": "PCM frame synchronization",
+ "offset": 7,
+ "size": 1
+ },
+ "I2SSTD": {
+ "description": "I2S standard selection",
+ "offset": 4,
+ "size": 2
+ },
+ "CKPOL": {
+ "description": "Steady state clock\n polarity",
+ "offset": 3,
+ "size": 1
+ },
+ "DATLEN": {
+ "description": "Data length to be\n transferred",
+ "offset": 1,
+ "size": 2
+ },
+ "CHLEN": {
+ "description": "Channel length (number of bits per audio\n channel)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "I2SPR": {
+ "description": "I2S prescaler register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 10,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MCKOE": {
+ "description": "Master clock output enable",
+ "offset": 9,
+ "size": 1
+ },
+ "ODD": {
+ "description": "Odd factor for the\n prescaler",
+ "offset": 8,
+ "size": 1
+ },
+ "I2SDIV": {
+ "description": "I2S Linear prescaler",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "LTDC": {
+ "description": "LCD-TFT Controller",
+ "children": {
+ "registers": {
+ "SSCR": {
+ "description": "Synchronization Size Configuration\n Register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "HSW": {
+ "description": "Horizontal Synchronization Width (in\n units of pixel clock period)",
+ "offset": 16,
+ "size": 10
+ },
+ "VSH": {
+ "description": "Vertical Synchronization Height (in\n units of horizontal scan line)",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "BPCR": {
+ "description": "Back Porch Configuration\n Register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "AHBP": {
+ "description": "Accumulated Horizontal back porch (in\n units of pixel clock period)",
+ "offset": 16,
+ "size": 10
+ },
+ "AVBP": {
+ "description": "Accumulated Vertical back porch (in\n units of horizontal scan line)",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "AWCR": {
+ "description": "Active Width Configuration\n Register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "AAV": {
+ "description": "AAV",
+ "offset": 16,
+ "size": 10
+ },
+ "AAH": {
+ "description": "Accumulated Active Height (in units of\n horizontal scan line)",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "TWCR": {
+ "description": "Total Width Configuration\n Register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TOTALW": {
+ "description": "Total Width (in units of pixel clock\n period)",
+ "offset": 16,
+ "size": 10
+ },
+ "TOTALH": {
+ "description": "Total Height (in units of horizontal\n scan line)",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "GCR": {
+ "description": "Global Control Register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 8736,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "HSPOL": {
+ "description": "Horizontal Synchronization\n Polarity",
+ "offset": 31,
+ "size": 1
+ },
+ "VSPOL": {
+ "description": "Vertical Synchronization\n Polarity",
+ "offset": 30,
+ "size": 1
+ },
+ "DEPOL": {
+ "description": "Data Enable Polarity",
+ "offset": 29,
+ "size": 1
+ },
+ "PCPOL": {
+ "description": "Pixel Clock Polarity",
+ "offset": 28,
+ "size": 1
+ },
+ "DEN": {
+ "description": "Dither Enable",
+ "offset": 16,
+ "size": 1
+ },
+ "DRW": {
+ "description": "Dither Red Width",
+ "offset": 12,
+ "size": 3,
+ "access": "read-only"
+ },
+ "DGW": {
+ "description": "Dither Green Width",
+ "offset": 8,
+ "size": 3,
+ "access": "read-only"
+ },
+ "DBW": {
+ "description": "Dither Blue Width",
+ "offset": 4,
+ "size": 3,
+ "access": "read-only"
+ },
+ "LTDCEN": {
+ "description": "LCD-TFT controller enable\n bit",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SRCR": {
+ "description": "Shadow Reload Configuration\n Register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "VBR": {
+ "description": "Vertical Blanking Reload",
+ "offset": 1,
+ "size": 1
+ },
+ "IMR": {
+ "description": "Immediate Reload",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BCCR": {
+ "description": "Background Color Configuration\n Register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BC": {
+ "description": "Background Color Red value",
+ "offset": 0,
+ "size": 24
+ }
+ }
+ }
+ },
+ "IER": {
+ "description": "Interrupt Enable Register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RRIE": {
+ "description": "Register Reload interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "TERRIE": {
+ "description": "Transfer Error Interrupt\n Enable",
+ "offset": 2,
+ "size": 1
+ },
+ "FUIE": {
+ "description": "FIFO Underrun Interrupt\n Enable",
+ "offset": 1,
+ "size": 1
+ },
+ "LIE": {
+ "description": "Line Interrupt Enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ISR": {
+ "description": "Interrupt Status Register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "RRIF": {
+ "description": "Register Reload Interrupt\n Flag",
+ "offset": 3,
+ "size": 1
+ },
+ "TERRIF": {
+ "description": "Transfer Error interrupt\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "FUIF": {
+ "description": "FIFO Underrun Interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "LIF": {
+ "description": "Line Interrupt flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ICR": {
+ "description": "Interrupt Clear Register",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "CRRIF": {
+ "description": "Clears Register Reload Interrupt\n Flag",
+ "offset": 3,
+ "size": 1
+ },
+ "CTERRIF": {
+ "description": "Clears the Transfer Error Interrupt\n Flag",
+ "offset": 2,
+ "size": 1
+ },
+ "CFUIF": {
+ "description": "Clears the FIFO Underrun Interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "CLIF": {
+ "description": "Clears the Line Interrupt\n Flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "LIPCR": {
+ "description": "Line Interrupt Position Configuration\n Register",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LIPOS": {
+ "description": "Line Interrupt Position",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "CPSR": {
+ "description": "Current Position Status\n Register",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CXPOS": {
+ "description": "Current X Position",
+ "offset": 16,
+ "size": 16
+ },
+ "CYPOS": {
+ "description": "Current Y Position",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CDSR": {
+ "description": "Current Display Status\n Register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 15,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "HSYNCS": {
+ "description": "Horizontal Synchronization display\n Status",
+ "offset": 3,
+ "size": 1
+ },
+ "VSYNCS": {
+ "description": "Vertical Synchronization display\n Status",
+ "offset": 2,
+ "size": 1
+ },
+ "HDES": {
+ "description": "Horizontal Data Enable display\n Status",
+ "offset": 1,
+ "size": 1
+ },
+ "VDES": {
+ "description": "Vertical Data Enable display\n Status",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "L1CR": {
+ "description": "Layerx Control Register",
+ "offset": 132,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CLUTEN": {
+ "description": "Color Look-Up Table Enable",
+ "offset": 4,
+ "size": 1
+ },
+ "COLKEN": {
+ "description": "Color Keying Enable",
+ "offset": 1,
+ "size": 1
+ },
+ "LEN": {
+ "description": "Layer Enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "L1WHPCR": {
+ "description": "Layerx Window Horizontal Position\n Configuration Register",
+ "offset": 136,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "WHSPPOS": {
+ "description": "Window Horizontal Stop\n Position",
+ "offset": 16,
+ "size": 12
+ },
+ "WHSTPOS": {
+ "description": "Window Horizontal Start\n Position",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "L1WVPCR": {
+ "description": "Layerx Window Vertical Position\n Configuration Register",
+ "offset": 140,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "WVSPPOS": {
+ "description": "Window Vertical Stop\n Position",
+ "offset": 16,
+ "size": 11
+ },
+ "WVSTPOS": {
+ "description": "Window Vertical Start\n Position",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "L1CKCR": {
+ "description": "Layerx Color Keying Configuration\n Register",
+ "offset": 144,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CKRED": {
+ "description": "Color Key Red value",
+ "offset": 16,
+ "size": 8
+ },
+ "CKGREEN": {
+ "description": "Color Key Green value",
+ "offset": 8,
+ "size": 8
+ },
+ "CKBLUE": {
+ "description": "Color Key Blue value",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "L1PFCR": {
+ "description": "Layerx Pixel Format Configuration\n Register",
+ "offset": 148,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PF": {
+ "description": "Pixel Format",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "L1CACR": {
+ "description": "Layerx Constant Alpha Configuration\n Register",
+ "offset": 152,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CONSTA": {
+ "description": "Constant Alpha",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "L1DCCR": {
+ "description": "Layerx Default Color Configuration\n Register",
+ "offset": 156,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DCALPHA": {
+ "description": "Default Color Alpha",
+ "offset": 24,
+ "size": 8
+ },
+ "DCRED": {
+ "description": "Default Color Red",
+ "offset": 16,
+ "size": 8
+ },
+ "DCGREEN": {
+ "description": "Default Color Green",
+ "offset": 8,
+ "size": 8
+ },
+ "DCBLUE": {
+ "description": "Default Color Blue",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "L1BFCR": {
+ "description": "Layerx Blending Factors Configuration\n Register",
+ "offset": 160,
+ "size": 32,
+ "reset_value": 1543,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BF1": {
+ "description": "Blending Factor 1",
+ "offset": 8,
+ "size": 3
+ },
+ "BF2": {
+ "description": "Blending Factor 2",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "L1CFBAR": {
+ "description": "Layerx Color Frame Buffer Address\n Register",
+ "offset": 172,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CFBADD": {
+ "description": "Color Frame Buffer Start\n Address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "L1CFBLR": {
+ "description": "Layerx Color Frame Buffer Length\n Register",
+ "offset": 176,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CFBP": {
+ "description": "Color Frame Buffer Pitch in\n bytes",
+ "offset": 16,
+ "size": 13
+ },
+ "CFBLL": {
+ "description": "Color Frame Buffer Line\n Length",
+ "offset": 0,
+ "size": 13
+ }
+ }
+ }
+ },
+ "L1CFBLNR": {
+ "description": "Layerx ColorFrame Buffer Line Number\n Register",
+ "offset": 180,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CFBLNBR": {
+ "description": "Frame Buffer Line Number",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "L1CLUTWR": {
+ "description": "Layerx CLUT Write Register",
+ "offset": 196,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "CLUTADD": {
+ "description": "CLUT Address",
+ "offset": 24,
+ "size": 8
+ },
+ "RED": {
+ "description": "Red value",
+ "offset": 16,
+ "size": 8
+ },
+ "GREEN": {
+ "description": "Green value",
+ "offset": 8,
+ "size": 8
+ },
+ "BLUE": {
+ "description": "Blue value",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "L2CR": {
+ "description": "Layerx Control Register",
+ "offset": 260,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CLUTEN": {
+ "description": "Color Look-Up Table Enable",
+ "offset": 4,
+ "size": 1
+ },
+ "COLKEN": {
+ "description": "Color Keying Enable",
+ "offset": 1,
+ "size": 1
+ },
+ "LEN": {
+ "description": "Layer Enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "L2WHPCR": {
+ "description": "Layerx Window Horizontal Position\n Configuration Register",
+ "offset": 264,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "WHSPPOS": {
+ "description": "Window Horizontal Stop\n Position",
+ "offset": 16,
+ "size": 12
+ },
+ "WHSTPOS": {
+ "description": "Window Horizontal Start\n Position",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "L2WVPCR": {
+ "description": "Layerx Window Vertical Position\n Configuration Register",
+ "offset": 268,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "WVSPPOS": {
+ "description": "Window Vertical Stop\n Position",
+ "offset": 16,
+ "size": 11
+ },
+ "WVSTPOS": {
+ "description": "Window Vertical Start\n Position",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "L2CKCR": {
+ "description": "Layerx Color Keying Configuration\n Register",
+ "offset": 272,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CKRED": {
+ "description": "Color Key Red value",
+ "offset": 15,
+ "size": 9
+ },
+ "CKGREEN": {
+ "description": "Color Key Green value",
+ "offset": 8,
+ "size": 7
+ },
+ "CKBLUE": {
+ "description": "Color Key Blue value",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "L2PFCR": {
+ "description": "Layerx Pixel Format Configuration\n Register",
+ "offset": 276,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PF": {
+ "description": "Pixel Format",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "L2CACR": {
+ "description": "Layerx Constant Alpha Configuration\n Register",
+ "offset": 280,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CONSTA": {
+ "description": "Constant Alpha",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "L2DCCR": {
+ "description": "Layerx Default Color Configuration\n Register",
+ "offset": 284,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DCALPHA": {
+ "description": "Default Color Alpha",
+ "offset": 24,
+ "size": 8
+ },
+ "DCRED": {
+ "description": "Default Color Red",
+ "offset": 16,
+ "size": 8
+ },
+ "DCGREEN": {
+ "description": "Default Color Green",
+ "offset": 8,
+ "size": 8
+ },
+ "DCBLUE": {
+ "description": "Default Color Blue",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "L2BFCR": {
+ "description": "Layerx Blending Factors Configuration\n Register",
+ "offset": 288,
+ "size": 32,
+ "reset_value": 1543,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BF1": {
+ "description": "Blending Factor 1",
+ "offset": 8,
+ "size": 3
+ },
+ "BF2": {
+ "description": "Blending Factor 2",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "L2CFBAR": {
+ "description": "Layerx Color Frame Buffer Address\n Register",
+ "offset": 300,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CFBADD": {
+ "description": "Color Frame Buffer Start\n Address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "L2CFBLR": {
+ "description": "Layerx Color Frame Buffer Length\n Register",
+ "offset": 304,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CFBP": {
+ "description": "Color Frame Buffer Pitch in\n bytes",
+ "offset": 16,
+ "size": 13
+ },
+ "CFBLL": {
+ "description": "Color Frame Buffer Line\n Length",
+ "offset": 0,
+ "size": 13
+ }
+ }
+ }
+ },
+ "L2CFBLNR": {
+ "description": "Layerx ColorFrame Buffer Line Number\n Register",
+ "offset": 308,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CFBLNBR": {
+ "description": "Frame Buffer Line Number",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "L2CLUTWR": {
+ "description": "Layerx CLUT Write Register",
+ "offset": 324,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "CLUTADD": {
+ "description": "CLUT Address",
+ "offset": 24,
+ "size": 8
+ },
+ "RED": {
+ "description": "Red value",
+ "offset": 16,
+ "size": 8
+ },
+ "GREEN": {
+ "description": "Green value",
+ "offset": 8,
+ "size": 8
+ },
+ "BLUE": {
+ "description": "Blue value",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "SAI1": {
+ "description": "Serial audio interface",
+ "children": {
+ "registers": {
+ "SAI_ACR1": {
+ "description": "SAI AConfiguration register 1",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 64,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MCKDIV": {
+ "description": "Master clock divider",
+ "offset": 20,
+ "size": 4
+ },
+ "MODE": {
+ "description": "Audio block mode",
+ "offset": 0,
+ "size": 2
+ },
+ "PRTCFG": {
+ "description": "Protocol configuration",
+ "offset": 2,
+ "size": 2
+ },
+ "DS": {
+ "description": "Data size",
+ "offset": 5,
+ "size": 3
+ },
+ "LSBFIRST": {
+ "description": "Least significant bit\n first",
+ "offset": 8,
+ "size": 1
+ },
+ "CKSTR": {
+ "description": "Clock strobing edge",
+ "offset": 9,
+ "size": 1
+ },
+ "SYNCEN": {
+ "description": "Synchronization enable",
+ "offset": 10,
+ "size": 2
+ },
+ "MONO": {
+ "description": "Mono mode",
+ "offset": 12,
+ "size": 1
+ },
+ "OUTDRIV": {
+ "description": "Output drive",
+ "offset": 13,
+ "size": 1
+ },
+ "SAIAEN": {
+ "description": "Audio block enable",
+ "offset": 16,
+ "size": 1
+ },
+ "DMAEN": {
+ "description": "DMA enable",
+ "offset": 17,
+ "size": 1
+ },
+ "NODIV": {
+ "description": "No divider",
+ "offset": 19,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SAI_BCR1": {
+ "description": "SAI BConfiguration register 1",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 64,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MODE": {
+ "description": "Audio block mode",
+ "offset": 0,
+ "size": 2
+ },
+ "PRTCFG": {
+ "description": "Protocol configuration",
+ "offset": 2,
+ "size": 2
+ },
+ "DS": {
+ "description": "Data size",
+ "offset": 5,
+ "size": 3
+ },
+ "LSBFIRST": {
+ "description": "Least significant bit\n first",
+ "offset": 8,
+ "size": 1
+ },
+ "CKSTR": {
+ "description": "Clock strobing edge",
+ "offset": 9,
+ "size": 1
+ },
+ "SYNCEN": {
+ "description": "Synchronization enable",
+ "offset": 10,
+ "size": 2
+ },
+ "MONO": {
+ "description": "Mono mode",
+ "offset": 12,
+ "size": 1
+ },
+ "OUTDRIV": {
+ "description": "Output drive",
+ "offset": 13,
+ "size": 1
+ },
+ "SAIBEN": {
+ "description": "Audio block enable",
+ "offset": 16,
+ "size": 1
+ },
+ "DMAEN": {
+ "description": "DMA enable",
+ "offset": 17,
+ "size": 1
+ },
+ "NODIV": {
+ "description": "No divider",
+ "offset": 19,
+ "size": 1
+ },
+ "MCKDIV": {
+ "description": "Master clock divider",
+ "offset": 20,
+ "size": 4
+ }
+ }
+ }
+ },
+ "SAI_ACR2": {
+ "description": "SAI AConfiguration register 2",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 64,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FTH": {
+ "description": "FIFO threshold",
+ "offset": 0,
+ "size": 3
+ },
+ "FFLUSH": {
+ "description": "FIFO flush",
+ "offset": 3,
+ "size": 1
+ },
+ "TRIS": {
+ "description": "Tristate management on data\n line",
+ "offset": 4,
+ "size": 1
+ },
+ "MUTE": {
+ "description": "Mute",
+ "offset": 5,
+ "size": 1
+ },
+ "MUTEVAL": {
+ "description": "Mute value",
+ "offset": 6,
+ "size": 1
+ },
+ "MUTECNT": {
+ "description": "Mute counter",
+ "offset": 7,
+ "size": 6
+ },
+ "CPL": {
+ "description": "Complement bit",
+ "offset": 13,
+ "size": 1
+ },
+ "COMP": {
+ "description": "Companding mode",
+ "offset": 14,
+ "size": 2
+ }
+ }
+ }
+ },
+ "SAI_BCR2": {
+ "description": "SAI BConfiguration register 2",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 64,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FTH": {
+ "description": "FIFO threshold",
+ "offset": 0,
+ "size": 3
+ },
+ "FFLUSH": {
+ "description": "FIFO flush",
+ "offset": 3,
+ "size": 1
+ },
+ "TRIS": {
+ "description": "Tristate management on data\n line",
+ "offset": 4,
+ "size": 1
+ },
+ "MUTE": {
+ "description": "Mute",
+ "offset": 5,
+ "size": 1
+ },
+ "MUTEVAL": {
+ "description": "Mute value",
+ "offset": 6,
+ "size": 1
+ },
+ "MUTECNT": {
+ "description": "Mute counter",
+ "offset": 7,
+ "size": 6
+ },
+ "CPL": {
+ "description": "Complement bit",
+ "offset": 13,
+ "size": 1
+ },
+ "COMP": {
+ "description": "Companding mode",
+ "offset": 14,
+ "size": 2
+ }
+ }
+ }
+ },
+ "SAI_AFRCR": {
+ "description": "SAI AFrame configuration\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 7,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FRL": {
+ "description": "Frame length",
+ "offset": 0,
+ "size": 8
+ },
+ "FSALL": {
+ "description": "Frame synchronization active level\n length",
+ "offset": 8,
+ "size": 7
+ },
+ "FSDEF": {
+ "description": "Frame synchronization\n definition",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "FSPOL": {
+ "description": "Frame synchronization\n polarity",
+ "offset": 17,
+ "size": 1
+ },
+ "FSOFF": {
+ "description": "Frame synchronization\n offset",
+ "offset": 18,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SAI_BFRCR": {
+ "description": "SAI BFrame configuration\n register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 7,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FRL": {
+ "description": "Frame length",
+ "offset": 0,
+ "size": 8
+ },
+ "FSALL": {
+ "description": "Frame synchronization active level\n length",
+ "offset": 8,
+ "size": 7
+ },
+ "FSDEF": {
+ "description": "Frame synchronization\n definition",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "FSPOL": {
+ "description": "Frame synchronization\n polarity",
+ "offset": 17,
+ "size": 1
+ },
+ "FSOFF": {
+ "description": "Frame synchronization\n offset",
+ "offset": 18,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SAI_ASLOTR": {
+ "description": "SAI ASlot register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FBOFF": {
+ "description": "First bit offset",
+ "offset": 0,
+ "size": 5
+ },
+ "SLOTSZ": {
+ "description": "Slot size",
+ "offset": 6,
+ "size": 2
+ },
+ "NBSLOT": {
+ "description": "Number of slots in an audio\n frame",
+ "offset": 8,
+ "size": 4
+ },
+ "SLOTEN": {
+ "description": "Slot enable",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "SAI_BSLOTR": {
+ "description": "SAI BSlot register",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FBOFF": {
+ "description": "First bit offset",
+ "offset": 0,
+ "size": 5
+ },
+ "SLOTSZ": {
+ "description": "Slot size",
+ "offset": 6,
+ "size": 2
+ },
+ "NBSLOT": {
+ "description": "Number of slots in an audio\n frame",
+ "offset": 8,
+ "size": 4
+ },
+ "SLOTEN": {
+ "description": "Slot enable",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "SAI_AIM": {
+ "description": "SAI AInterrupt mask register2",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OVRUDRIE": {
+ "description": "Overrun/underrun interrupt\n enable",
+ "offset": 0,
+ "size": 1
+ },
+ "MUTEDETIE": {
+ "description": "Mute detection interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "WCKCFGIE": {
+ "description": "Wrong clock configuration interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "FREQIE": {
+ "description": "FIFO request interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "CNRDYIE": {
+ "description": "Codec not ready interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "AFSDETIE": {
+ "description": "Anticipated frame synchronization\n detection interrupt enable",
+ "offset": 5,
+ "size": 1
+ },
+ "LFSDETIE": {
+ "description": "Late frame synchronization detection\n interrupt enable",
+ "offset": 6,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SAI_BIM": {
+ "description": "SAI BInterrupt mask register2",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OVRUDRIE": {
+ "description": "Overrun/underrun interrupt\n enable",
+ "offset": 0,
+ "size": 1
+ },
+ "MUTEDETIE": {
+ "description": "Mute detection interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "WCKCFGIE": {
+ "description": "Wrong clock configuration interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "FREQIE": {
+ "description": "FIFO request interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "CNRDYIE": {
+ "description": "Codec not ready interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "AFSDETIE": {
+ "description": "Anticipated frame synchronization\n detection interrupt enable",
+ "offset": 5,
+ "size": 1
+ },
+ "LFSDETIE": {
+ "description": "Late frame synchronization detection\n interrupt enable",
+ "offset": 6,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SAI_ASR": {
+ "description": "SAI AStatus register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 8,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "OVRUDR": {
+ "description": "Overrun / underrun",
+ "offset": 0,
+ "size": 1
+ },
+ "MUTEDET": {
+ "description": "Mute detection",
+ "offset": 1,
+ "size": 1
+ },
+ "WCKCFG": {
+ "description": "Wrong clock configuration\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "FREQ": {
+ "description": "FIFO request",
+ "offset": 3,
+ "size": 1
+ },
+ "CNRDY": {
+ "description": "Codec not ready",
+ "offset": 4,
+ "size": 1
+ },
+ "AFSDET": {
+ "description": "Anticipated frame synchronization\n detection",
+ "offset": 5,
+ "size": 1
+ },
+ "LFSDET": {
+ "description": "Late frame synchronization\n detection",
+ "offset": 6,
+ "size": 1
+ },
+ "FLTH": {
+ "description": "FIFO level threshold",
+ "offset": 16,
+ "size": 3
+ }
+ }
+ }
+ },
+ "SAI_BSR": {
+ "description": "SAI BStatus register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 8,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "OVRUDR": {
+ "description": "Overrun / underrun",
+ "offset": 0,
+ "size": 1
+ },
+ "MUTEDET": {
+ "description": "Mute detection",
+ "offset": 1,
+ "size": 1
+ },
+ "WCKCFG": {
+ "description": "Wrong clock configuration\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "FREQ": {
+ "description": "FIFO request",
+ "offset": 3,
+ "size": 1
+ },
+ "CNRDY": {
+ "description": "Codec not ready",
+ "offset": 4,
+ "size": 1
+ },
+ "AFSDET": {
+ "description": "Anticipated frame synchronization\n detection",
+ "offset": 5,
+ "size": 1
+ },
+ "LFSDET": {
+ "description": "Late frame synchronization\n detection",
+ "offset": 6,
+ "size": 1
+ },
+ "FLTH": {
+ "description": "FIFO level threshold",
+ "offset": 16,
+ "size": 3
+ }
+ }
+ }
+ },
+ "SAI_ACLRFR": {
+ "description": "SAI AClear flag register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "COVRUDR": {
+ "description": "Clear overrun / underrun",
+ "offset": 0,
+ "size": 1
+ },
+ "CMUTEDET": {
+ "description": "Mute detection flag",
+ "offset": 1,
+ "size": 1
+ },
+ "CWCKCFG": {
+ "description": "Clear wrong clock configuration\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "CCNRDY": {
+ "description": "Clear codec not ready flag",
+ "offset": 4,
+ "size": 1
+ },
+ "CAFSDET": {
+ "description": "Clear anticipated frame synchronization\n detection flag",
+ "offset": 5,
+ "size": 1
+ },
+ "CLFSDET": {
+ "description": "Clear late frame synchronization\n detection flag",
+ "offset": 6,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SAI_BCLRFR": {
+ "description": "SAI BClear flag register",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "COVRUDR": {
+ "description": "Clear overrun / underrun",
+ "offset": 0,
+ "size": 1
+ },
+ "CMUTEDET": {
+ "description": "Mute detection flag",
+ "offset": 1,
+ "size": 1
+ },
+ "CWCKCFG": {
+ "description": "Clear wrong clock configuration\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "CCNRDY": {
+ "description": "Clear codec not ready flag",
+ "offset": 4,
+ "size": 1
+ },
+ "CAFSDET": {
+ "description": "Clear anticipated frame synchronization\n detection flag",
+ "offset": 5,
+ "size": 1
+ },
+ "CLFSDET": {
+ "description": "Clear late frame synchronization\n detection flag",
+ "offset": 6,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SAI_ADR": {
+ "description": "SAI AData register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATA": {
+ "description": "Data",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "SAI_BDR": {
+ "description": "SAI BData register",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATA": {
+ "description": "Data",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "NVIC": {
+ "description": "Nested Vectored Interrupt\n Controller",
+ "children": {
+ "registers": {
+ "ISER0": {
+ "description": "Interrupt Set-Enable Register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SETENA": {
+ "description": "SETENA",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ISER1": {
+ "description": "Interrupt Set-Enable Register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SETENA": {
+ "description": "SETENA",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ISER2": {
+ "description": "Interrupt Set-Enable Register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SETENA": {
+ "description": "SETENA",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ICER0": {
+ "description": "Interrupt Clear-Enable\n Register",
+ "offset": 128,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CLRENA": {
+ "description": "CLRENA",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ICER1": {
+ "description": "Interrupt Clear-Enable\n Register",
+ "offset": 132,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CLRENA": {
+ "description": "CLRENA",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ICER2": {
+ "description": "Interrupt Clear-Enable\n Register",
+ "offset": 136,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CLRENA": {
+ "description": "CLRENA",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ISPR0": {
+ "description": "Interrupt Set-Pending Register",
+ "offset": 256,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SETPEND": {
+ "description": "SETPEND",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ISPR1": {
+ "description": "Interrupt Set-Pending Register",
+ "offset": 260,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SETPEND": {
+ "description": "SETPEND",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ISPR2": {
+ "description": "Interrupt Set-Pending Register",
+ "offset": 264,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SETPEND": {
+ "description": "SETPEND",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ICPR0": {
+ "description": "Interrupt Clear-Pending\n Register",
+ "offset": 384,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CLRPEND": {
+ "description": "CLRPEND",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ICPR1": {
+ "description": "Interrupt Clear-Pending\n Register",
+ "offset": 388,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CLRPEND": {
+ "description": "CLRPEND",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ICPR2": {
+ "description": "Interrupt Clear-Pending\n Register",
+ "offset": 392,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CLRPEND": {
+ "description": "CLRPEND",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "IABR0": {
+ "description": "Interrupt Active Bit Register",
+ "offset": 512,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "ACTIVE": {
+ "description": "ACTIVE",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "IABR1": {
+ "description": "Interrupt Active Bit Register",
+ "offset": 516,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "ACTIVE": {
+ "description": "ACTIVE",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "IABR2": {
+ "description": "Interrupt Active Bit Register",
+ "offset": 520,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "ACTIVE": {
+ "description": "ACTIVE",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "IPR0": {
+ "description": "Interrupt Priority Register",
+ "offset": 768,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR1": {
+ "description": "Interrupt Priority Register",
+ "offset": 772,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR2": {
+ "description": "Interrupt Priority Register",
+ "offset": 776,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR3": {
+ "description": "Interrupt Priority Register",
+ "offset": 780,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR4": {
+ "description": "Interrupt Priority Register",
+ "offset": 784,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR5": {
+ "description": "Interrupt Priority Register",
+ "offset": 788,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR6": {
+ "description": "Interrupt Priority Register",
+ "offset": 792,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR7": {
+ "description": "Interrupt Priority Register",
+ "offset": 796,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR8": {
+ "description": "Interrupt Priority Register",
+ "offset": 800,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR9": {
+ "description": "Interrupt Priority Register",
+ "offset": 804,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR10": {
+ "description": "Interrupt Priority Register",
+ "offset": 808,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR11": {
+ "description": "Interrupt Priority Register",
+ "offset": 812,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR12": {
+ "description": "Interrupt Priority Register",
+ "offset": 816,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR13": {
+ "description": "Interrupt Priority Register",
+ "offset": 820,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR14": {
+ "description": "Interrupt Priority Register",
+ "offset": 824,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR15": {
+ "description": "Interrupt Priority Register",
+ "offset": 828,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR16": {
+ "description": "Interrupt Priority Register",
+ "offset": 832,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR17": {
+ "description": "Interrupt Priority Register",
+ "offset": 836,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR18": {
+ "description": "Interrupt Priority Register",
+ "offset": 840,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR19": {
+ "description": "Interrupt Priority Register",
+ "offset": 844,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "OTG_HS_PWRCLK": {
+ "description": "USB on the go high speed",
+ "children": {
+ "registers": {
+ "OTG_HS_PCGCR": {
+ "description": "Power and clock gating control\n register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "STPPCLK": {
+ "description": "Stop PHY clock",
+ "offset": 0,
+ "size": 1
+ },
+ "GATEHCLK": {
+ "description": "Gate HCLK",
+ "offset": 1,
+ "size": 1
+ },
+ "PHYSUSP": {
+ "description": "PHY suspended",
+ "offset": 4,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "OTG_HS_DEVICE": {
+ "description": "USB on the go high speed",
+ "children": {
+ "registers": {
+ "OTG_HS_DCFG": {
+ "description": "OTG_HS device configuration\n register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 35651584,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DSPD": {
+ "description": "Device speed",
+ "offset": 0,
+ "size": 2
+ },
+ "NZLSOHSK": {
+ "description": "Nonzero-length status OUT\n handshake",
+ "offset": 2,
+ "size": 1
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 4,
+ "size": 7
+ },
+ "PFIVL": {
+ "description": "Periodic (micro)frame\n interval",
+ "offset": 11,
+ "size": 2
+ },
+ "PERSCHIVL": {
+ "description": "Periodic scheduling\n interval",
+ "offset": 24,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_DCTL": {
+ "description": "OTG_HS device control register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RWUSIG": {
+ "description": "Remote wakeup signaling",
+ "offset": 0,
+ "size": 1
+ },
+ "SDIS": {
+ "description": "Soft disconnect",
+ "offset": 1,
+ "size": 1
+ },
+ "GINSTS": {
+ "description": "Global IN NAK status",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "GONSTS": {
+ "description": "Global OUT NAK status",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TCTL": {
+ "description": "Test control",
+ "offset": 4,
+ "size": 3
+ },
+ "SGINAK": {
+ "description": "Set global IN NAK",
+ "offset": 7,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CGINAK": {
+ "description": "Clear global IN NAK",
+ "offset": 8,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SGONAK": {
+ "description": "Set global OUT NAK",
+ "offset": 9,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CGONAK": {
+ "description": "Clear global OUT NAK",
+ "offset": 10,
+ "size": 1,
+ "access": "write-only"
+ },
+ "POPRGDNE": {
+ "description": "Power-on programming done",
+ "offset": 11,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DSTS": {
+ "description": "OTG_HS device status register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 16,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "SUSPSTS": {
+ "description": "Suspend status",
+ "offset": 0,
+ "size": 1
+ },
+ "ENUMSPD": {
+ "description": "Enumerated speed",
+ "offset": 1,
+ "size": 2
+ },
+ "EERR": {
+ "description": "Erratic error",
+ "offset": 3,
+ "size": 1
+ },
+ "FNSOF": {
+ "description": "Frame number of the received\n SOF",
+ "offset": 8,
+ "size": 14
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPMSK": {
+ "description": "OTG_HS device IN endpoint common interrupt\n mask register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed interrupt\n mask",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDM": {
+ "description": "Endpoint disabled interrupt\n mask",
+ "offset": 1,
+ "size": 1
+ },
+ "TOM": {
+ "description": "Timeout condition mask (nonisochronous\n endpoints)",
+ "offset": 3,
+ "size": 1
+ },
+ "ITTXFEMSK": {
+ "description": "IN token received when TxFIFO empty\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "INEPNMM": {
+ "description": "IN token received with EP mismatch\n mask",
+ "offset": 5,
+ "size": 1
+ },
+ "INEPNEM": {
+ "description": "IN endpoint NAK effective\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXFURM": {
+ "description": "FIFO underrun mask",
+ "offset": 8,
+ "size": 1
+ },
+ "BIM": {
+ "description": "BNA interrupt mask",
+ "offset": 9,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPMSK": {
+ "description": "OTG_HS device OUT endpoint common interrupt\n mask register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed interrupt\n mask",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDM": {
+ "description": "Endpoint disabled interrupt\n mask",
+ "offset": 1,
+ "size": 1
+ },
+ "STUPM": {
+ "description": "SETUP phase done mask",
+ "offset": 3,
+ "size": 1
+ },
+ "OTEPDM": {
+ "description": "OUT token received when endpoint\n disabled mask",
+ "offset": 4,
+ "size": 1
+ },
+ "B2BSTUP": {
+ "description": "Back-to-back SETUP packets received\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "OPEM": {
+ "description": "OUT packet error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "BOIM": {
+ "description": "BNA interrupt mask",
+ "offset": 9,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DAINT": {
+ "description": "OTG_HS device all endpoints interrupt\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "IEPINT": {
+ "description": "IN endpoint interrupt bits",
+ "offset": 0,
+ "size": 16
+ },
+ "OEPINT": {
+ "description": "OUT endpoint interrupt\n bits",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DAINTMSK": {
+ "description": "OTG_HS all endpoints interrupt mask\n register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IEPM": {
+ "description": "IN EP interrupt mask bits",
+ "offset": 0,
+ "size": 16
+ },
+ "OEPM": {
+ "description": "OUT EP interrupt mask bits",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DVBUSDIS": {
+ "description": "OTG_HS device VBUS discharge time\n register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 6103,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "VBUSDT": {
+ "description": "Device VBUS discharge time",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DVBUSPULSE": {
+ "description": "OTG_HS device VBUS pulsing time\n register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 1464,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DVBUSP": {
+ "description": "Device VBUS pulsing time",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "OTG_HS_DTHRCTL": {
+ "description": "OTG_HS Device threshold control\n register",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NONISOTHREN": {
+ "description": "Nonisochronous IN endpoints threshold\n enable",
+ "offset": 0,
+ "size": 1
+ },
+ "ISOTHREN": {
+ "description": "ISO IN endpoint threshold\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "TXTHRLEN": {
+ "description": "Transmit threshold length",
+ "offset": 2,
+ "size": 9
+ },
+ "RXTHREN": {
+ "description": "Receive threshold enable",
+ "offset": 16,
+ "size": 1
+ },
+ "RXTHRLEN": {
+ "description": "Receive threshold length",
+ "offset": 17,
+ "size": 9
+ },
+ "ARPEN": {
+ "description": "Arbiter parking enable",
+ "offset": 27,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPEMPMSK": {
+ "description": "OTG_HS device IN endpoint FIFO empty\n interrupt mask register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INEPTXFEM": {
+ "description": "IN EP Tx FIFO empty interrupt mask\n bits",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DEACHINT": {
+ "description": "OTG_HS device each endpoint interrupt\n register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IEP1INT": {
+ "description": "IN endpoint 1interrupt bit",
+ "offset": 1,
+ "size": 1
+ },
+ "OEP1INT": {
+ "description": "OUT endpoint 1 interrupt\n bit",
+ "offset": 17,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DEACHINTMSK": {
+ "description": "OTG_HS device each endpoint interrupt\n register mask",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IEP1INTM": {
+ "description": "IN Endpoint 1 interrupt mask\n bit",
+ "offset": 1,
+ "size": 1
+ },
+ "OEP1INTM": {
+ "description": "OUT Endpoint 1 interrupt mask\n bit",
+ "offset": 17,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPEACHMSK1": {
+ "description": "OTG_HS device each in endpoint-1 interrupt\n register",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed interrupt\n mask",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDM": {
+ "description": "Endpoint disabled interrupt\n mask",
+ "offset": 1,
+ "size": 1
+ },
+ "TOM": {
+ "description": "Timeout condition mask (nonisochronous\n endpoints)",
+ "offset": 3,
+ "size": 1
+ },
+ "ITTXFEMSK": {
+ "description": "IN token received when TxFIFO empty\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "INEPNMM": {
+ "description": "IN token received with EP mismatch\n mask",
+ "offset": 5,
+ "size": 1
+ },
+ "INEPNEM": {
+ "description": "IN endpoint NAK effective\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXFURM": {
+ "description": "FIFO underrun mask",
+ "offset": 8,
+ "size": 1
+ },
+ "BIM": {
+ "description": "BNA interrupt mask",
+ "offset": 9,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK interrupt mask",
+ "offset": 13,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPEACHMSK1": {
+ "description": "OTG_HS device each OUT endpoint-1 interrupt\n register",
+ "offset": 128,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed interrupt\n mask",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDM": {
+ "description": "Endpoint disabled interrupt\n mask",
+ "offset": 1,
+ "size": 1
+ },
+ "TOM": {
+ "description": "Timeout condition mask",
+ "offset": 3,
+ "size": 1
+ },
+ "ITTXFEMSK": {
+ "description": "IN token received when TxFIFO empty\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "INEPNMM": {
+ "description": "IN token received with EP mismatch\n mask",
+ "offset": 5,
+ "size": 1
+ },
+ "INEPNEM": {
+ "description": "IN endpoint NAK effective\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXFURM": {
+ "description": "OUT packet error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "BIM": {
+ "description": "BNA interrupt mask",
+ "offset": 9,
+ "size": 1
+ },
+ "BERRM": {
+ "description": "Bubble error interrupt\n mask",
+ "offset": 12,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK interrupt mask",
+ "offset": 13,
+ "size": 1
+ },
+ "NYETM": {
+ "description": "NYET interrupt mask",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPCTL0": {
+ "description": "OTG device endpoint-0 control\n register",
+ "offset": 256,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "USBAEP": {
+ "description": "USB active endpoint",
+ "offset": 15,
+ "size": 1
+ },
+ "EONUM_DPID": {
+ "description": "Even/odd frame",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAK status",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "Stall": {
+ "description": "STALL handshake",
+ "offset": 21,
+ "size": 1
+ },
+ "TXFNUM": {
+ "description": "TxFIFO number",
+ "offset": 22,
+ "size": 4
+ },
+ "CNAK": {
+ "description": "Clear NAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "Set NAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "Set DATA0 PID",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SODDFRM": {
+ "description": "Set odd frame",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "Endpoint disable",
+ "offset": 30,
+ "size": 1
+ },
+ "EPENA": {
+ "description": "Endpoint enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPCTL1": {
+ "description": "OTG device endpoint-1 control\n register",
+ "offset": 288,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "USBAEP": {
+ "description": "USB active endpoint",
+ "offset": 15,
+ "size": 1
+ },
+ "EONUM_DPID": {
+ "description": "Even/odd frame",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAK status",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "Stall": {
+ "description": "STALL handshake",
+ "offset": 21,
+ "size": 1
+ },
+ "TXFNUM": {
+ "description": "TxFIFO number",
+ "offset": 22,
+ "size": 4
+ },
+ "CNAK": {
+ "description": "Clear NAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "Set NAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "Set DATA0 PID",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SODDFRM": {
+ "description": "Set odd frame",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "Endpoint disable",
+ "offset": 30,
+ "size": 1
+ },
+ "EPENA": {
+ "description": "Endpoint enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPCTL2": {
+ "description": "OTG device endpoint-2 control\n register",
+ "offset": 320,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "USBAEP": {
+ "description": "USB active endpoint",
+ "offset": 15,
+ "size": 1
+ },
+ "EONUM_DPID": {
+ "description": "Even/odd frame",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAK status",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "Stall": {
+ "description": "STALL handshake",
+ "offset": 21,
+ "size": 1
+ },
+ "TXFNUM": {
+ "description": "TxFIFO number",
+ "offset": 22,
+ "size": 4
+ },
+ "CNAK": {
+ "description": "Clear NAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "Set NAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "Set DATA0 PID",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SODDFRM": {
+ "description": "Set odd frame",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "Endpoint disable",
+ "offset": 30,
+ "size": 1
+ },
+ "EPENA": {
+ "description": "Endpoint enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPCTL3": {
+ "description": "OTG device endpoint-3 control\n register",
+ "offset": 352,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "USBAEP": {
+ "description": "USB active endpoint",
+ "offset": 15,
+ "size": 1
+ },
+ "EONUM_DPID": {
+ "description": "Even/odd frame",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAK status",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "Stall": {
+ "description": "STALL handshake",
+ "offset": 21,
+ "size": 1
+ },
+ "TXFNUM": {
+ "description": "TxFIFO number",
+ "offset": 22,
+ "size": 4
+ },
+ "CNAK": {
+ "description": "Clear NAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "Set NAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "Set DATA0 PID",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SODDFRM": {
+ "description": "Set odd frame",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "Endpoint disable",
+ "offset": 30,
+ "size": 1
+ },
+ "EPENA": {
+ "description": "Endpoint enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPCTL4": {
+ "description": "OTG device endpoint-4 control\n register",
+ "offset": 384,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "USBAEP": {
+ "description": "USB active endpoint",
+ "offset": 15,
+ "size": 1
+ },
+ "EONUM_DPID": {
+ "description": "Even/odd frame",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAK status",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "Stall": {
+ "description": "STALL handshake",
+ "offset": 21,
+ "size": 1
+ },
+ "TXFNUM": {
+ "description": "TxFIFO number",
+ "offset": 22,
+ "size": 4
+ },
+ "CNAK": {
+ "description": "Clear NAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "Set NAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "Set DATA0 PID",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SODDFRM": {
+ "description": "Set odd frame",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "Endpoint disable",
+ "offset": 30,
+ "size": 1
+ },
+ "EPENA": {
+ "description": "Endpoint enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPCTL5": {
+ "description": "OTG device endpoint-5 control\n register",
+ "offset": 416,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "USBAEP": {
+ "description": "USB active endpoint",
+ "offset": 15,
+ "size": 1
+ },
+ "EONUM_DPID": {
+ "description": "Even/odd frame",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAK status",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "Stall": {
+ "description": "STALL handshake",
+ "offset": 21,
+ "size": 1
+ },
+ "TXFNUM": {
+ "description": "TxFIFO number",
+ "offset": 22,
+ "size": 4
+ },
+ "CNAK": {
+ "description": "Clear NAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "Set NAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "Set DATA0 PID",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SODDFRM": {
+ "description": "Set odd frame",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "Endpoint disable",
+ "offset": 30,
+ "size": 1
+ },
+ "EPENA": {
+ "description": "Endpoint enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPCTL6": {
+ "description": "OTG device endpoint-6 control\n register",
+ "offset": 448,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "USBAEP": {
+ "description": "USB active endpoint",
+ "offset": 15,
+ "size": 1
+ },
+ "EONUM_DPID": {
+ "description": "Even/odd frame",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAK status",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "Stall": {
+ "description": "STALL handshake",
+ "offset": 21,
+ "size": 1
+ },
+ "TXFNUM": {
+ "description": "TxFIFO number",
+ "offset": 22,
+ "size": 4
+ },
+ "CNAK": {
+ "description": "Clear NAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "Set NAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "Set DATA0 PID",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SODDFRM": {
+ "description": "Set odd frame",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "Endpoint disable",
+ "offset": 30,
+ "size": 1
+ },
+ "EPENA": {
+ "description": "Endpoint enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPCTL7": {
+ "description": "OTG device endpoint-7 control\n register",
+ "offset": 480,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "USBAEP": {
+ "description": "USB active endpoint",
+ "offset": 15,
+ "size": 1
+ },
+ "EONUM_DPID": {
+ "description": "Even/odd frame",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAK status",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "Stall": {
+ "description": "STALL handshake",
+ "offset": 21,
+ "size": 1
+ },
+ "TXFNUM": {
+ "description": "TxFIFO number",
+ "offset": 22,
+ "size": 4
+ },
+ "CNAK": {
+ "description": "Clear NAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "Set NAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "Set DATA0 PID",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SODDFRM": {
+ "description": "Set odd frame",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "Endpoint disable",
+ "offset": 30,
+ "size": 1
+ },
+ "EPENA": {
+ "description": "Endpoint enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPINT0": {
+ "description": "OTG device endpoint-0 interrupt\n register",
+ "offset": 264,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "TOC": {
+ "description": "Timeout condition",
+ "offset": 3,
+ "size": 1
+ },
+ "ITTXFE": {
+ "description": "IN token received when TxFIFO is\n empty",
+ "offset": 4,
+ "size": 1
+ },
+ "INEPNE": {
+ "description": "IN endpoint NAK effective",
+ "offset": 6,
+ "size": 1
+ },
+ "TXFE": {
+ "description": "Transmit FIFO empty",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TXFIFOUDRN": {
+ "description": "Transmit Fifo Underrun",
+ "offset": 8,
+ "size": 1
+ },
+ "BNA": {
+ "description": "Buffer not available\n interrupt",
+ "offset": 9,
+ "size": 1
+ },
+ "PKTDRPSTS": {
+ "description": "Packet dropped status",
+ "offset": 11,
+ "size": 1
+ },
+ "BERR": {
+ "description": "Babble error interrupt",
+ "offset": 12,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK interrupt",
+ "offset": 13,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPINT1": {
+ "description": "OTG device endpoint-1 interrupt\n register",
+ "offset": 296,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "TOC": {
+ "description": "Timeout condition",
+ "offset": 3,
+ "size": 1
+ },
+ "ITTXFE": {
+ "description": "IN token received when TxFIFO is\n empty",
+ "offset": 4,
+ "size": 1
+ },
+ "INEPNE": {
+ "description": "IN endpoint NAK effective",
+ "offset": 6,
+ "size": 1
+ },
+ "TXFE": {
+ "description": "Transmit FIFO empty",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TXFIFOUDRN": {
+ "description": "Transmit Fifo Underrun",
+ "offset": 8,
+ "size": 1
+ },
+ "BNA": {
+ "description": "Buffer not available\n interrupt",
+ "offset": 9,
+ "size": 1
+ },
+ "PKTDRPSTS": {
+ "description": "Packet dropped status",
+ "offset": 11,
+ "size": 1
+ },
+ "BERR": {
+ "description": "Babble error interrupt",
+ "offset": 12,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK interrupt",
+ "offset": 13,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPINT2": {
+ "description": "OTG device endpoint-2 interrupt\n register",
+ "offset": 328,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "TOC": {
+ "description": "Timeout condition",
+ "offset": 3,
+ "size": 1
+ },
+ "ITTXFE": {
+ "description": "IN token received when TxFIFO is\n empty",
+ "offset": 4,
+ "size": 1
+ },
+ "INEPNE": {
+ "description": "IN endpoint NAK effective",
+ "offset": 6,
+ "size": 1
+ },
+ "TXFE": {
+ "description": "Transmit FIFO empty",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TXFIFOUDRN": {
+ "description": "Transmit Fifo Underrun",
+ "offset": 8,
+ "size": 1
+ },
+ "BNA": {
+ "description": "Buffer not available\n interrupt",
+ "offset": 9,
+ "size": 1
+ },
+ "PKTDRPSTS": {
+ "description": "Packet dropped status",
+ "offset": 11,
+ "size": 1
+ },
+ "BERR": {
+ "description": "Babble error interrupt",
+ "offset": 12,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK interrupt",
+ "offset": 13,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPINT3": {
+ "description": "OTG device endpoint-3 interrupt\n register",
+ "offset": 360,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "TOC": {
+ "description": "Timeout condition",
+ "offset": 3,
+ "size": 1
+ },
+ "ITTXFE": {
+ "description": "IN token received when TxFIFO is\n empty",
+ "offset": 4,
+ "size": 1
+ },
+ "INEPNE": {
+ "description": "IN endpoint NAK effective",
+ "offset": 6,
+ "size": 1
+ },
+ "TXFE": {
+ "description": "Transmit FIFO empty",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TXFIFOUDRN": {
+ "description": "Transmit Fifo Underrun",
+ "offset": 8,
+ "size": 1
+ },
+ "BNA": {
+ "description": "Buffer not available\n interrupt",
+ "offset": 9,
+ "size": 1
+ },
+ "PKTDRPSTS": {
+ "description": "Packet dropped status",
+ "offset": 11,
+ "size": 1
+ },
+ "BERR": {
+ "description": "Babble error interrupt",
+ "offset": 12,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK interrupt",
+ "offset": 13,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPINT4": {
+ "description": "OTG device endpoint-4 interrupt\n register",
+ "offset": 392,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "TOC": {
+ "description": "Timeout condition",
+ "offset": 3,
+ "size": 1
+ },
+ "ITTXFE": {
+ "description": "IN token received when TxFIFO is\n empty",
+ "offset": 4,
+ "size": 1
+ },
+ "INEPNE": {
+ "description": "IN endpoint NAK effective",
+ "offset": 6,
+ "size": 1
+ },
+ "TXFE": {
+ "description": "Transmit FIFO empty",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TXFIFOUDRN": {
+ "description": "Transmit Fifo Underrun",
+ "offset": 8,
+ "size": 1
+ },
+ "BNA": {
+ "description": "Buffer not available\n interrupt",
+ "offset": 9,
+ "size": 1
+ },
+ "PKTDRPSTS": {
+ "description": "Packet dropped status",
+ "offset": 11,
+ "size": 1
+ },
+ "BERR": {
+ "description": "Babble error interrupt",
+ "offset": 12,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK interrupt",
+ "offset": 13,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPINT5": {
+ "description": "OTG device endpoint-5 interrupt\n register",
+ "offset": 424,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "TOC": {
+ "description": "Timeout condition",
+ "offset": 3,
+ "size": 1
+ },
+ "ITTXFE": {
+ "description": "IN token received when TxFIFO is\n empty",
+ "offset": 4,
+ "size": 1
+ },
+ "INEPNE": {
+ "description": "IN endpoint NAK effective",
+ "offset": 6,
+ "size": 1
+ },
+ "TXFE": {
+ "description": "Transmit FIFO empty",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TXFIFOUDRN": {
+ "description": "Transmit Fifo Underrun",
+ "offset": 8,
+ "size": 1
+ },
+ "BNA": {
+ "description": "Buffer not available\n interrupt",
+ "offset": 9,
+ "size": 1
+ },
+ "PKTDRPSTS": {
+ "description": "Packet dropped status",
+ "offset": 11,
+ "size": 1
+ },
+ "BERR": {
+ "description": "Babble error interrupt",
+ "offset": 12,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK interrupt",
+ "offset": 13,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPINT6": {
+ "description": "OTG device endpoint-6 interrupt\n register",
+ "offset": 456,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "TOC": {
+ "description": "Timeout condition",
+ "offset": 3,
+ "size": 1
+ },
+ "ITTXFE": {
+ "description": "IN token received when TxFIFO is\n empty",
+ "offset": 4,
+ "size": 1
+ },
+ "INEPNE": {
+ "description": "IN endpoint NAK effective",
+ "offset": 6,
+ "size": 1
+ },
+ "TXFE": {
+ "description": "Transmit FIFO empty",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TXFIFOUDRN": {
+ "description": "Transmit Fifo Underrun",
+ "offset": 8,
+ "size": 1
+ },
+ "BNA": {
+ "description": "Buffer not available\n interrupt",
+ "offset": 9,
+ "size": 1
+ },
+ "PKTDRPSTS": {
+ "description": "Packet dropped status",
+ "offset": 11,
+ "size": 1
+ },
+ "BERR": {
+ "description": "Babble error interrupt",
+ "offset": 12,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK interrupt",
+ "offset": 13,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPINT7": {
+ "description": "OTG device endpoint-7 interrupt\n register",
+ "offset": 488,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "TOC": {
+ "description": "Timeout condition",
+ "offset": 3,
+ "size": 1
+ },
+ "ITTXFE": {
+ "description": "IN token received when TxFIFO is\n empty",
+ "offset": 4,
+ "size": 1
+ },
+ "INEPNE": {
+ "description": "IN endpoint NAK effective",
+ "offset": 6,
+ "size": 1
+ },
+ "TXFE": {
+ "description": "Transmit FIFO empty",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TXFIFOUDRN": {
+ "description": "Transmit Fifo Underrun",
+ "offset": 8,
+ "size": 1
+ },
+ "BNA": {
+ "description": "Buffer not available\n interrupt",
+ "offset": 9,
+ "size": 1
+ },
+ "PKTDRPSTS": {
+ "description": "Packet dropped status",
+ "offset": 11,
+ "size": 1
+ },
+ "BERR": {
+ "description": "Babble error interrupt",
+ "offset": 12,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK interrupt",
+ "offset": 13,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPTSIZ0": {
+ "description": "OTG_HS device IN endpoint 0 transfer size\n register",
+ "offset": 272,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 7
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPDMA1": {
+ "description": "OTG_HS device endpoint-1 DMA address\n register",
+ "offset": 276,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPDMA2": {
+ "description": "OTG_HS device endpoint-2 DMA address\n register",
+ "offset": 308,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPDMA3": {
+ "description": "OTG_HS device endpoint-3 DMA address\n register",
+ "offset": 340,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPDMA4": {
+ "description": "OTG_HS device endpoint-4 DMA address\n register",
+ "offset": 372,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPDMA5": {
+ "description": "OTG_HS device endpoint-5 DMA address\n register",
+ "offset": 404,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_DTXFSTS0": {
+ "description": "OTG_HS device IN endpoint transmit FIFO\n status register",
+ "offset": 280,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "INEPTFSAV": {
+ "description": "IN endpoint TxFIFO space\n avail",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DTXFSTS1": {
+ "description": "OTG_HS device IN endpoint transmit FIFO\n status register",
+ "offset": 312,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "INEPTFSAV": {
+ "description": "IN endpoint TxFIFO space\n avail",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DTXFSTS2": {
+ "description": "OTG_HS device IN endpoint transmit FIFO\n status register",
+ "offset": 344,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "INEPTFSAV": {
+ "description": "IN endpoint TxFIFO space\n avail",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DTXFSTS3": {
+ "description": "OTG_HS device IN endpoint transmit FIFO\n status register",
+ "offset": 376,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "INEPTFSAV": {
+ "description": "IN endpoint TxFIFO space\n avail",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DTXFSTS4": {
+ "description": "OTG_HS device IN endpoint transmit FIFO\n status register",
+ "offset": 408,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "INEPTFSAV": {
+ "description": "IN endpoint TxFIFO space\n avail",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DTXFSTS5": {
+ "description": "OTG_HS device IN endpoint transmit FIFO\n status register",
+ "offset": 440,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "INEPTFSAV": {
+ "description": "IN endpoint TxFIFO space\n avail",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPTSIZ1": {
+ "description": "OTG_HS device endpoint transfer size\n register",
+ "offset": 304,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "MCNT": {
+ "description": "Multi count",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPTSIZ2": {
+ "description": "OTG_HS device endpoint transfer size\n register",
+ "offset": 336,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "MCNT": {
+ "description": "Multi count",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPTSIZ3": {
+ "description": "OTG_HS device endpoint transfer size\n register",
+ "offset": 368,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "MCNT": {
+ "description": "Multi count",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPTSIZ4": {
+ "description": "OTG_HS device endpoint transfer size\n register",
+ "offset": 400,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "MCNT": {
+ "description": "Multi count",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPTSIZ5": {
+ "description": "OTG_HS device endpoint transfer size\n register",
+ "offset": 432,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "MCNT": {
+ "description": "Multi count",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPCTL0": {
+ "description": "OTG_HS device control OUT endpoint 0 control\n register",
+ "offset": 768,
+ "size": 32,
+ "reset_value": 32768,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 2,
+ "access": "read-only"
+ },
+ "USBAEP": {
+ "description": "USB active endpoint",
+ "offset": 15,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAK status",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2,
+ "access": "read-only"
+ },
+ "SNPM": {
+ "description": "Snoop mode",
+ "offset": 20,
+ "size": 1
+ },
+ "Stall": {
+ "description": "STALL handshake",
+ "offset": 21,
+ "size": 1
+ },
+ "CNAK": {
+ "description": "Clear NAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "Set NAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "Endpoint disable",
+ "offset": 30,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPENA": {
+ "description": "Endpoint enable",
+ "offset": 31,
+ "size": 1,
+ "access": "write-only"
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPCTL1": {
+ "description": "OTG device endpoint-1 control\n register",
+ "offset": 800,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "USBAEP": {
+ "description": "USB active endpoint",
+ "offset": 15,
+ "size": 1
+ },
+ "EONUM_DPID": {
+ "description": "Even odd frame/Endpoint data\n PID",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAK status",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "SNPM": {
+ "description": "Snoop mode",
+ "offset": 20,
+ "size": 1
+ },
+ "Stall": {
+ "description": "STALL handshake",
+ "offset": 21,
+ "size": 1
+ },
+ "CNAK": {
+ "description": "Clear NAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "Set NAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "Set DATA0 PID/Set even\n frame",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SODDFRM": {
+ "description": "Set odd frame",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "Endpoint disable",
+ "offset": 30,
+ "size": 1
+ },
+ "EPENA": {
+ "description": "Endpoint enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPCTL2": {
+ "description": "OTG device endpoint-2 control\n register",
+ "offset": 832,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "USBAEP": {
+ "description": "USB active endpoint",
+ "offset": 15,
+ "size": 1
+ },
+ "EONUM_DPID": {
+ "description": "Even odd frame/Endpoint data\n PID",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAK status",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "SNPM": {
+ "description": "Snoop mode",
+ "offset": 20,
+ "size": 1
+ },
+ "Stall": {
+ "description": "STALL handshake",
+ "offset": 21,
+ "size": 1
+ },
+ "CNAK": {
+ "description": "Clear NAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "Set NAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "Set DATA0 PID/Set even\n frame",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SODDFRM": {
+ "description": "Set odd frame",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "Endpoint disable",
+ "offset": 30,
+ "size": 1
+ },
+ "EPENA": {
+ "description": "Endpoint enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPCTL3": {
+ "description": "OTG device endpoint-3 control\n register",
+ "offset": 864,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "USBAEP": {
+ "description": "USB active endpoint",
+ "offset": 15,
+ "size": 1
+ },
+ "EONUM_DPID": {
+ "description": "Even odd frame/Endpoint data\n PID",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAK status",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "SNPM": {
+ "description": "Snoop mode",
+ "offset": 20,
+ "size": 1
+ },
+ "Stall": {
+ "description": "STALL handshake",
+ "offset": 21,
+ "size": 1
+ },
+ "CNAK": {
+ "description": "Clear NAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "Set NAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "Set DATA0 PID/Set even\n frame",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SODDFRM": {
+ "description": "Set odd frame",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "Endpoint disable",
+ "offset": 30,
+ "size": 1
+ },
+ "EPENA": {
+ "description": "Endpoint enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPINT0": {
+ "description": "OTG_HS device endpoint-0 interrupt\n register",
+ "offset": 776,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "STUP": {
+ "description": "SETUP phase done",
+ "offset": 3,
+ "size": 1
+ },
+ "OTEPDIS": {
+ "description": "OUT token received when endpoint\n disabled",
+ "offset": 4,
+ "size": 1
+ },
+ "B2BSTUP": {
+ "description": "Back-to-back SETUP packets\n received",
+ "offset": 6,
+ "size": 1
+ },
+ "NYET": {
+ "description": "NYET interrupt",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPINT1": {
+ "description": "OTG_HS device endpoint-1 interrupt\n register",
+ "offset": 808,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "STUP": {
+ "description": "SETUP phase done",
+ "offset": 3,
+ "size": 1
+ },
+ "OTEPDIS": {
+ "description": "OUT token received when endpoint\n disabled",
+ "offset": 4,
+ "size": 1
+ },
+ "B2BSTUP": {
+ "description": "Back-to-back SETUP packets\n received",
+ "offset": 6,
+ "size": 1
+ },
+ "NYET": {
+ "description": "NYET interrupt",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPINT2": {
+ "description": "OTG_HS device endpoint-2 interrupt\n register",
+ "offset": 840,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "STUP": {
+ "description": "SETUP phase done",
+ "offset": 3,
+ "size": 1
+ },
+ "OTEPDIS": {
+ "description": "OUT token received when endpoint\n disabled",
+ "offset": 4,
+ "size": 1
+ },
+ "B2BSTUP": {
+ "description": "Back-to-back SETUP packets\n received",
+ "offset": 6,
+ "size": 1
+ },
+ "NYET": {
+ "description": "NYET interrupt",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPINT3": {
+ "description": "OTG_HS device endpoint-3 interrupt\n register",
+ "offset": 872,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "STUP": {
+ "description": "SETUP phase done",
+ "offset": 3,
+ "size": 1
+ },
+ "OTEPDIS": {
+ "description": "OUT token received when endpoint\n disabled",
+ "offset": 4,
+ "size": 1
+ },
+ "B2BSTUP": {
+ "description": "Back-to-back SETUP packets\n received",
+ "offset": 6,
+ "size": 1
+ },
+ "NYET": {
+ "description": "NYET interrupt",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPINT4": {
+ "description": "OTG_HS device endpoint-4 interrupt\n register",
+ "offset": 904,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "STUP": {
+ "description": "SETUP phase done",
+ "offset": 3,
+ "size": 1
+ },
+ "OTEPDIS": {
+ "description": "OUT token received when endpoint\n disabled",
+ "offset": 4,
+ "size": 1
+ },
+ "B2BSTUP": {
+ "description": "Back-to-back SETUP packets\n received",
+ "offset": 6,
+ "size": 1
+ },
+ "NYET": {
+ "description": "NYET interrupt",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPINT5": {
+ "description": "OTG_HS device endpoint-5 interrupt\n register",
+ "offset": 936,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "STUP": {
+ "description": "SETUP phase done",
+ "offset": 3,
+ "size": 1
+ },
+ "OTEPDIS": {
+ "description": "OUT token received when endpoint\n disabled",
+ "offset": 4,
+ "size": 1
+ },
+ "B2BSTUP": {
+ "description": "Back-to-back SETUP packets\n received",
+ "offset": 6,
+ "size": 1
+ },
+ "NYET": {
+ "description": "NYET interrupt",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPINT6": {
+ "description": "OTG_HS device endpoint-6 interrupt\n register",
+ "offset": 968,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "STUP": {
+ "description": "SETUP phase done",
+ "offset": 3,
+ "size": 1
+ },
+ "OTEPDIS": {
+ "description": "OUT token received when endpoint\n disabled",
+ "offset": 4,
+ "size": 1
+ },
+ "B2BSTUP": {
+ "description": "Back-to-back SETUP packets\n received",
+ "offset": 6,
+ "size": 1
+ },
+ "NYET": {
+ "description": "NYET interrupt",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPINT7": {
+ "description": "OTG_HS device endpoint-7 interrupt\n register",
+ "offset": 1000,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "STUP": {
+ "description": "SETUP phase done",
+ "offset": 3,
+ "size": 1
+ },
+ "OTEPDIS": {
+ "description": "OUT token received when endpoint\n disabled",
+ "offset": 4,
+ "size": 1
+ },
+ "B2BSTUP": {
+ "description": "Back-to-back SETUP packets\n received",
+ "offset": 6,
+ "size": 1
+ },
+ "NYET": {
+ "description": "NYET interrupt",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPTSIZ0": {
+ "description": "OTG_HS device endpoint-1 transfer size\n register",
+ "offset": 784,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 7
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 1
+ },
+ "STUPCNT": {
+ "description": "SETUP packet count",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPTSIZ1": {
+ "description": "OTG_HS device endpoint-2 transfer size\n register",
+ "offset": 816,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "RXDPID_STUPCNT": {
+ "description": "Received data PID/SETUP packet\n count",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPTSIZ2": {
+ "description": "OTG_HS device endpoint-3 transfer size\n register",
+ "offset": 848,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "RXDPID_STUPCNT": {
+ "description": "Received data PID/SETUP packet\n count",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPTSIZ3": {
+ "description": "OTG_HS device endpoint-4 transfer size\n register",
+ "offset": 880,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "RXDPID_STUPCNT": {
+ "description": "Received data PID/SETUP packet\n count",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPTSIZ4": {
+ "description": "OTG_HS device endpoint-5 transfer size\n register",
+ "offset": 912,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "RXDPID_STUPCNT": {
+ "description": "Received data PID/SETUP packet\n count",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "OTG_HS_HOST": {
+ "description": "USB on the go high speed",
+ "children": {
+ "registers": {
+ "OTG_HS_HCFG": {
+ "description": "OTG_HS host configuration\n register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FSLSPCS": {
+ "description": "FS/LS PHY clock select",
+ "offset": 0,
+ "size": 2
+ },
+ "FSLSS": {
+ "description": "FS- and LS-only support",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "OTG_HS_HFIR": {
+ "description": "OTG_HS Host frame interval\n register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 60000,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FRIVL": {
+ "description": "Frame interval",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_HFNUM": {
+ "description": "OTG_HS host frame number/frame time\n remaining register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 16383,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "FRNUM": {
+ "description": "Frame number",
+ "offset": 0,
+ "size": 16
+ },
+ "FTREM": {
+ "description": "Frame time remaining",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_HPTXSTS": {
+ "description": "OTG_HS_Host periodic transmit FIFO/queue\n status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 524544,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PTXFSAVL": {
+ "description": "Periodic transmit data FIFO space\n available",
+ "offset": 0,
+ "size": 16
+ },
+ "PTXQSAV": {
+ "description": "Periodic transmit request queue space\n available",
+ "offset": 16,
+ "size": 8,
+ "access": "read-only"
+ },
+ "PTXQTOP": {
+ "description": "Top of the periodic transmit request\n queue",
+ "offset": 24,
+ "size": 8,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "OTG_HS_HAINT": {
+ "description": "OTG_HS Host all channels interrupt\n register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "HAINT": {
+ "description": "Channel interrupts",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_HAINTMSK": {
+ "description": "OTG_HS host all channels interrupt mask\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "HAINTM": {
+ "description": "Channel interrupt mask",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_HPRT": {
+ "description": "OTG_HS host port control and status\n register",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PCSTS": {
+ "description": "Port connect status",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PCDET": {
+ "description": "Port connect detected",
+ "offset": 1,
+ "size": 1
+ },
+ "PENA": {
+ "description": "Port enable",
+ "offset": 2,
+ "size": 1
+ },
+ "PENCHNG": {
+ "description": "Port enable/disable change",
+ "offset": 3,
+ "size": 1
+ },
+ "POCA": {
+ "description": "Port overcurrent active",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "POCCHNG": {
+ "description": "Port overcurrent change",
+ "offset": 5,
+ "size": 1
+ },
+ "PRES": {
+ "description": "Port resume",
+ "offset": 6,
+ "size": 1
+ },
+ "PSUSP": {
+ "description": "Port suspend",
+ "offset": 7,
+ "size": 1
+ },
+ "PRST": {
+ "description": "Port reset",
+ "offset": 8,
+ "size": 1
+ },
+ "PLSTS": {
+ "description": "Port line status",
+ "offset": 10,
+ "size": 2,
+ "access": "read-only"
+ },
+ "PPWR": {
+ "description": "Port power",
+ "offset": 12,
+ "size": 1
+ },
+ "PTCTL": {
+ "description": "Port test control",
+ "offset": 13,
+ "size": 4
+ },
+ "PSPD": {
+ "description": "Port speed",
+ "offset": 17,
+ "size": 2,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "OTG_HS_HCCHAR0": {
+ "description": "OTG_HS host channel-0 characteristics\n register",
+ "offset": 256,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MC": {
+ "description": "Multi Count (MC) / Error Count\n (EC)",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCCHAR1": {
+ "description": "OTG_HS host channel-1 characteristics\n register",
+ "offset": 288,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MC": {
+ "description": "Multi Count (MC) / Error Count\n (EC)",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCCHAR2": {
+ "description": "OTG_HS host channel-2 characteristics\n register",
+ "offset": 320,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MC": {
+ "description": "Multi Count (MC) / Error Count\n (EC)",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCCHAR3": {
+ "description": "OTG_HS host channel-3 characteristics\n register",
+ "offset": 352,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MC": {
+ "description": "Multi Count (MC) / Error Count\n (EC)",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCCHAR4": {
+ "description": "OTG_HS host channel-4 characteristics\n register",
+ "offset": 384,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MC": {
+ "description": "Multi Count (MC) / Error Count\n (EC)",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCCHAR5": {
+ "description": "OTG_HS host channel-5 characteristics\n register",
+ "offset": 416,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MC": {
+ "description": "Multi Count (MC) / Error Count\n (EC)",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCCHAR6": {
+ "description": "OTG_HS host channel-6 characteristics\n register",
+ "offset": 448,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MC": {
+ "description": "Multi Count (MC) / Error Count\n (EC)",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCCHAR7": {
+ "description": "OTG_HS host channel-7 characteristics\n register",
+ "offset": 480,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MC": {
+ "description": "Multi Count (MC) / Error Count\n (EC)",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCCHAR8": {
+ "description": "OTG_HS host channel-8 characteristics\n register",
+ "offset": 512,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MC": {
+ "description": "Multi Count (MC) / Error Count\n (EC)",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCCHAR9": {
+ "description": "OTG_HS host channel-9 characteristics\n register",
+ "offset": 544,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MC": {
+ "description": "Multi Count (MC) / Error Count\n (EC)",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCCHAR10": {
+ "description": "OTG_HS host channel-10 characteristics\n register",
+ "offset": 576,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MC": {
+ "description": "Multi Count (MC) / Error Count\n (EC)",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCCHAR11": {
+ "description": "OTG_HS host channel-11 characteristics\n register",
+ "offset": 608,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MC": {
+ "description": "Multi Count (MC) / Error Count\n (EC)",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCSPLT0": {
+ "description": "OTG_HS host channel-0 split control\n register",
+ "offset": 260,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRTADDR": {
+ "description": "Port address",
+ "offset": 0,
+ "size": 7
+ },
+ "HUBADDR": {
+ "description": "Hub address",
+ "offset": 7,
+ "size": 7
+ },
+ "XACTPOS": {
+ "description": "XACTPOS",
+ "offset": 14,
+ "size": 2
+ },
+ "COMPLSPLT": {
+ "description": "Do complete split",
+ "offset": 16,
+ "size": 1
+ },
+ "SPLITEN": {
+ "description": "Split enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCSPLT1": {
+ "description": "OTG_HS host channel-1 split control\n register",
+ "offset": 292,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRTADDR": {
+ "description": "Port address",
+ "offset": 0,
+ "size": 7
+ },
+ "HUBADDR": {
+ "description": "Hub address",
+ "offset": 7,
+ "size": 7
+ },
+ "XACTPOS": {
+ "description": "XACTPOS",
+ "offset": 14,
+ "size": 2
+ },
+ "COMPLSPLT": {
+ "description": "Do complete split",
+ "offset": 16,
+ "size": 1
+ },
+ "SPLITEN": {
+ "description": "Split enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCSPLT2": {
+ "description": "OTG_HS host channel-2 split control\n register",
+ "offset": 324,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRTADDR": {
+ "description": "Port address",
+ "offset": 0,
+ "size": 7
+ },
+ "HUBADDR": {
+ "description": "Hub address",
+ "offset": 7,
+ "size": 7
+ },
+ "XACTPOS": {
+ "description": "XACTPOS",
+ "offset": 14,
+ "size": 2
+ },
+ "COMPLSPLT": {
+ "description": "Do complete split",
+ "offset": 16,
+ "size": 1
+ },
+ "SPLITEN": {
+ "description": "Split enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCSPLT3": {
+ "description": "OTG_HS host channel-3 split control\n register",
+ "offset": 356,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRTADDR": {
+ "description": "Port address",
+ "offset": 0,
+ "size": 7
+ },
+ "HUBADDR": {
+ "description": "Hub address",
+ "offset": 7,
+ "size": 7
+ },
+ "XACTPOS": {
+ "description": "XACTPOS",
+ "offset": 14,
+ "size": 2
+ },
+ "COMPLSPLT": {
+ "description": "Do complete split",
+ "offset": 16,
+ "size": 1
+ },
+ "SPLITEN": {
+ "description": "Split enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCSPLT4": {
+ "description": "OTG_HS host channel-4 split control\n register",
+ "offset": 388,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRTADDR": {
+ "description": "Port address",
+ "offset": 0,
+ "size": 7
+ },
+ "HUBADDR": {
+ "description": "Hub address",
+ "offset": 7,
+ "size": 7
+ },
+ "XACTPOS": {
+ "description": "XACTPOS",
+ "offset": 14,
+ "size": 2
+ },
+ "COMPLSPLT": {
+ "description": "Do complete split",
+ "offset": 16,
+ "size": 1
+ },
+ "SPLITEN": {
+ "description": "Split enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCSPLT5": {
+ "description": "OTG_HS host channel-5 split control\n register",
+ "offset": 420,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRTADDR": {
+ "description": "Port address",
+ "offset": 0,
+ "size": 7
+ },
+ "HUBADDR": {
+ "description": "Hub address",
+ "offset": 7,
+ "size": 7
+ },
+ "XACTPOS": {
+ "description": "XACTPOS",
+ "offset": 14,
+ "size": 2
+ },
+ "COMPLSPLT": {
+ "description": "Do complete split",
+ "offset": 16,
+ "size": 1
+ },
+ "SPLITEN": {
+ "description": "Split enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCSPLT6": {
+ "description": "OTG_HS host channel-6 split control\n register",
+ "offset": 452,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRTADDR": {
+ "description": "Port address",
+ "offset": 0,
+ "size": 7
+ },
+ "HUBADDR": {
+ "description": "Hub address",
+ "offset": 7,
+ "size": 7
+ },
+ "XACTPOS": {
+ "description": "XACTPOS",
+ "offset": 14,
+ "size": 2
+ },
+ "COMPLSPLT": {
+ "description": "Do complete split",
+ "offset": 16,
+ "size": 1
+ },
+ "SPLITEN": {
+ "description": "Split enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCSPLT7": {
+ "description": "OTG_HS host channel-7 split control\n register",
+ "offset": 484,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRTADDR": {
+ "description": "Port address",
+ "offset": 0,
+ "size": 7
+ },
+ "HUBADDR": {
+ "description": "Hub address",
+ "offset": 7,
+ "size": 7
+ },
+ "XACTPOS": {
+ "description": "XACTPOS",
+ "offset": 14,
+ "size": 2
+ },
+ "COMPLSPLT": {
+ "description": "Do complete split",
+ "offset": 16,
+ "size": 1
+ },
+ "SPLITEN": {
+ "description": "Split enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCSPLT8": {
+ "description": "OTG_HS host channel-8 split control\n register",
+ "offset": 516,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRTADDR": {
+ "description": "Port address",
+ "offset": 0,
+ "size": 7
+ },
+ "HUBADDR": {
+ "description": "Hub address",
+ "offset": 7,
+ "size": 7
+ },
+ "XACTPOS": {
+ "description": "XACTPOS",
+ "offset": 14,
+ "size": 2
+ },
+ "COMPLSPLT": {
+ "description": "Do complete split",
+ "offset": 16,
+ "size": 1
+ },
+ "SPLITEN": {
+ "description": "Split enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCSPLT9": {
+ "description": "OTG_HS host channel-9 split control\n register",
+ "offset": 548,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRTADDR": {
+ "description": "Port address",
+ "offset": 0,
+ "size": 7
+ },
+ "HUBADDR": {
+ "description": "Hub address",
+ "offset": 7,
+ "size": 7
+ },
+ "XACTPOS": {
+ "description": "XACTPOS",
+ "offset": 14,
+ "size": 2
+ },
+ "COMPLSPLT": {
+ "description": "Do complete split",
+ "offset": 16,
+ "size": 1
+ },
+ "SPLITEN": {
+ "description": "Split enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCSPLT10": {
+ "description": "OTG_HS host channel-10 split control\n register",
+ "offset": 580,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRTADDR": {
+ "description": "Port address",
+ "offset": 0,
+ "size": 7
+ },
+ "HUBADDR": {
+ "description": "Hub address",
+ "offset": 7,
+ "size": 7
+ },
+ "XACTPOS": {
+ "description": "XACTPOS",
+ "offset": 14,
+ "size": 2
+ },
+ "COMPLSPLT": {
+ "description": "Do complete split",
+ "offset": 16,
+ "size": 1
+ },
+ "SPLITEN": {
+ "description": "Split enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCSPLT11": {
+ "description": "OTG_HS host channel-11 split control\n register",
+ "offset": 612,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRTADDR": {
+ "description": "Port address",
+ "offset": 0,
+ "size": 7
+ },
+ "HUBADDR": {
+ "description": "Hub address",
+ "offset": 7,
+ "size": 7
+ },
+ "XACTPOS": {
+ "description": "XACTPOS",
+ "offset": 14,
+ "size": 2
+ },
+ "COMPLSPLT": {
+ "description": "Do complete split",
+ "offset": 16,
+ "size": 1
+ },
+ "SPLITEN": {
+ "description": "Split enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINT0": {
+ "description": "OTG_HS host channel-11 interrupt\n register",
+ "offset": 264,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "Response received\n interrupt",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINT1": {
+ "description": "OTG_HS host channel-1 interrupt\n register",
+ "offset": 296,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "Response received\n interrupt",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINT2": {
+ "description": "OTG_HS host channel-2 interrupt\n register",
+ "offset": 328,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "Response received\n interrupt",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINT3": {
+ "description": "OTG_HS host channel-3 interrupt\n register",
+ "offset": 360,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "Response received\n interrupt",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINT4": {
+ "description": "OTG_HS host channel-4 interrupt\n register",
+ "offset": 392,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "Response received\n interrupt",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINT5": {
+ "description": "OTG_HS host channel-5 interrupt\n register",
+ "offset": 424,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "Response received\n interrupt",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINT6": {
+ "description": "OTG_HS host channel-6 interrupt\n register",
+ "offset": 456,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "Response received\n interrupt",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINT7": {
+ "description": "OTG_HS host channel-7 interrupt\n register",
+ "offset": 488,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "Response received\n interrupt",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINT8": {
+ "description": "OTG_HS host channel-8 interrupt\n register",
+ "offset": 520,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "Response received\n interrupt",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINT9": {
+ "description": "OTG_HS host channel-9 interrupt\n register",
+ "offset": 552,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "Response received\n interrupt",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINT10": {
+ "description": "OTG_HS host channel-10 interrupt\n register",
+ "offset": 584,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "Response received\n interrupt",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINT11": {
+ "description": "OTG_HS host channel-11 interrupt\n register",
+ "offset": 616,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "Response received\n interrupt",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINTMSK0": {
+ "description": "OTG_HS host channel-11 interrupt mask\n register",
+ "offset": 268,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINTMSK1": {
+ "description": "OTG_HS host channel-1 interrupt mask\n register",
+ "offset": 300,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINTMSK2": {
+ "description": "OTG_HS host channel-2 interrupt mask\n register",
+ "offset": 332,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINTMSK3": {
+ "description": "OTG_HS host channel-3 interrupt mask\n register",
+ "offset": 364,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINTMSK4": {
+ "description": "OTG_HS host channel-4 interrupt mask\n register",
+ "offset": 396,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINTMSK5": {
+ "description": "OTG_HS host channel-5 interrupt mask\n register",
+ "offset": 428,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINTMSK6": {
+ "description": "OTG_HS host channel-6 interrupt mask\n register",
+ "offset": 460,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINTMSK7": {
+ "description": "OTG_HS host channel-7 interrupt mask\n register",
+ "offset": 492,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINTMSK8": {
+ "description": "OTG_HS host channel-8 interrupt mask\n register",
+ "offset": 524,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINTMSK9": {
+ "description": "OTG_HS host channel-9 interrupt mask\n register",
+ "offset": 556,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINTMSK10": {
+ "description": "OTG_HS host channel-10 interrupt mask\n register",
+ "offset": 588,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINTMSK11": {
+ "description": "OTG_HS host channel-11 interrupt mask\n register",
+ "offset": 620,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCTSIZ0": {
+ "description": "OTG_HS host channel-11 transfer size\n register",
+ "offset": 272,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_HCTSIZ1": {
+ "description": "OTG_HS host channel-1 transfer size\n register",
+ "offset": 304,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_HCTSIZ2": {
+ "description": "OTG_HS host channel-2 transfer size\n register",
+ "offset": 336,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_HCTSIZ3": {
+ "description": "OTG_HS host channel-3 transfer size\n register",
+ "offset": 368,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_HCTSIZ4": {
+ "description": "OTG_HS host channel-4 transfer size\n register",
+ "offset": 400,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_HCTSIZ5": {
+ "description": "OTG_HS host channel-5 transfer size\n register",
+ "offset": 432,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_HCTSIZ6": {
+ "description": "OTG_HS host channel-6 transfer size\n register",
+ "offset": 464,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_HCTSIZ7": {
+ "description": "OTG_HS host channel-7 transfer size\n register",
+ "offset": 496,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_HCTSIZ8": {
+ "description": "OTG_HS host channel-8 transfer size\n register",
+ "offset": 528,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_HCTSIZ9": {
+ "description": "OTG_HS host channel-9 transfer size\n register",
+ "offset": 560,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_HCTSIZ10": {
+ "description": "OTG_HS host channel-10 transfer size\n register",
+ "offset": 592,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_HCTSIZ11": {
+ "description": "OTG_HS host channel-11 transfer size\n register",
+ "offset": 624,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_HCDMA0": {
+ "description": "OTG_HS host channel-0 DMA address\n register",
+ "offset": 276,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_HCDMA1": {
+ "description": "OTG_HS host channel-1 DMA address\n register",
+ "offset": 308,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_HCDMA2": {
+ "description": "OTG_HS host channel-2 DMA address\n register",
+ "offset": 340,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_HCDMA3": {
+ "description": "OTG_HS host channel-3 DMA address\n register",
+ "offset": 372,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_HCDMA4": {
+ "description": "OTG_HS host channel-4 DMA address\n register",
+ "offset": 404,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_HCDMA5": {
+ "description": "OTG_HS host channel-5 DMA address\n register",
+ "offset": 436,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_HCDMA6": {
+ "description": "OTG_HS host channel-6 DMA address\n register",
+ "offset": 468,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_HCDMA7": {
+ "description": "OTG_HS host channel-7 DMA address\n register",
+ "offset": 500,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_HCDMA8": {
+ "description": "OTG_HS host channel-8 DMA address\n register",
+ "offset": 532,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_HCDMA9": {
+ "description": "OTG_HS host channel-9 DMA address\n register",
+ "offset": 564,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_HCDMA10": {
+ "description": "OTG_HS host channel-10 DMA address\n register",
+ "offset": 596,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_HCDMA11": {
+ "description": "OTG_HS host channel-11 DMA address\n register",
+ "offset": 628,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "OTG_HS_GLOBAL": {
+ "description": "USB on the go high speed",
+ "children": {
+ "registers": {
+ "OTG_HS_GOTGCTL": {
+ "description": "OTG_HS control and status\n register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 2048,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SRQSCS": {
+ "description": "Session request success",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SRQ": {
+ "description": "Session request",
+ "offset": 1,
+ "size": 1
+ },
+ "HNGSCS": {
+ "description": "Host negotiation success",
+ "offset": 8,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HNPRQ": {
+ "description": "HNP request",
+ "offset": 9,
+ "size": 1
+ },
+ "HSHNPEN": {
+ "description": "Host set HNP enable",
+ "offset": 10,
+ "size": 1
+ },
+ "DHNPEN": {
+ "description": "Device HNP enabled",
+ "offset": 11,
+ "size": 1
+ },
+ "CIDSTS": {
+ "description": "Connector ID status",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "DBCT": {
+ "description": "Long/short debounce time",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ASVLD": {
+ "description": "A-session valid",
+ "offset": 18,
+ "size": 1,
+ "access": "read-only"
+ },
+ "BSVLD": {
+ "description": "B-session valid",
+ "offset": 19,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "OTG_HS_GOTGINT": {
+ "description": "OTG_HS interrupt register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SEDET": {
+ "description": "Session end detected",
+ "offset": 2,
+ "size": 1
+ },
+ "SRSSCHG": {
+ "description": "Session request success status\n change",
+ "offset": 8,
+ "size": 1
+ },
+ "HNSSCHG": {
+ "description": "Host negotiation success status\n change",
+ "offset": 9,
+ "size": 1
+ },
+ "HNGDET": {
+ "description": "Host negotiation detected",
+ "offset": 17,
+ "size": 1
+ },
+ "ADTOCHG": {
+ "description": "A-device timeout change",
+ "offset": 18,
+ "size": 1
+ },
+ "DBCDNE": {
+ "description": "Debounce done",
+ "offset": 19,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_GAHBCFG": {
+ "description": "OTG_HS AHB configuration\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "GINT": {
+ "description": "Global interrupt mask",
+ "offset": 0,
+ "size": 1
+ },
+ "HBSTLEN": {
+ "description": "Burst length/type",
+ "offset": 1,
+ "size": 4
+ },
+ "DMAEN": {
+ "description": "DMA enable",
+ "offset": 5,
+ "size": 1
+ },
+ "TXFELVL": {
+ "description": "TxFIFO empty level",
+ "offset": 7,
+ "size": 1
+ },
+ "PTXFELVL": {
+ "description": "Periodic TxFIFO empty\n level",
+ "offset": 8,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_GUSBCFG": {
+ "description": "OTG_HS USB configuration\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 2560,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TOCAL": {
+ "description": "FS timeout calibration",
+ "offset": 0,
+ "size": 3
+ },
+ "PHYSEL": {
+ "description": "USB 2.0 high-speed ULPI PHY or USB 1.1\n full-speed serial transceiver select",
+ "offset": 6,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SRPCAP": {
+ "description": "SRP-capable",
+ "offset": 8,
+ "size": 1
+ },
+ "HNPCAP": {
+ "description": "HNP-capable",
+ "offset": 9,
+ "size": 1
+ },
+ "TRDT": {
+ "description": "USB turnaround time",
+ "offset": 10,
+ "size": 4
+ },
+ "PHYLPCS": {
+ "description": "PHY Low-power clock select",
+ "offset": 15,
+ "size": 1
+ },
+ "ULPIFSLS": {
+ "description": "ULPI FS/LS select",
+ "offset": 17,
+ "size": 1
+ },
+ "ULPIAR": {
+ "description": "ULPI Auto-resume",
+ "offset": 18,
+ "size": 1
+ },
+ "ULPICSM": {
+ "description": "ULPI Clock SuspendM",
+ "offset": 19,
+ "size": 1
+ },
+ "ULPIEVBUSD": {
+ "description": "ULPI External VBUS Drive",
+ "offset": 20,
+ "size": 1
+ },
+ "ULPIEVBUSI": {
+ "description": "ULPI external VBUS\n indicator",
+ "offset": 21,
+ "size": 1
+ },
+ "TSDPS": {
+ "description": "TermSel DLine pulsing\n selection",
+ "offset": 22,
+ "size": 1
+ },
+ "PCCI": {
+ "description": "Indicator complement",
+ "offset": 23,
+ "size": 1
+ },
+ "PTCI": {
+ "description": "Indicator pass through",
+ "offset": 24,
+ "size": 1
+ },
+ "ULPIIPD": {
+ "description": "ULPI interface protect\n disable",
+ "offset": 25,
+ "size": 1
+ },
+ "FHMOD": {
+ "description": "Forced host mode",
+ "offset": 29,
+ "size": 1
+ },
+ "FDMOD": {
+ "description": "Forced peripheral mode",
+ "offset": 30,
+ "size": 1
+ },
+ "CTXPKT": {
+ "description": "Corrupt Tx packet",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_GRSTCTL": {
+ "description": "OTG_HS reset register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 536870912,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSRST": {
+ "description": "Core soft reset",
+ "offset": 0,
+ "size": 1
+ },
+ "HSRST": {
+ "description": "HCLK soft reset",
+ "offset": 1,
+ "size": 1
+ },
+ "FCRST": {
+ "description": "Host frame counter reset",
+ "offset": 2,
+ "size": 1
+ },
+ "RXFFLSH": {
+ "description": "RxFIFO flush",
+ "offset": 4,
+ "size": 1
+ },
+ "TXFFLSH": {
+ "description": "TxFIFO flush",
+ "offset": 5,
+ "size": 1
+ },
+ "TXFNUM": {
+ "description": "TxFIFO number",
+ "offset": 6,
+ "size": 5
+ },
+ "DMAREQ": {
+ "description": "DMA request signal",
+ "offset": 30,
+ "size": 1,
+ "access": "read-only"
+ },
+ "AHBIDL": {
+ "description": "AHB master idle",
+ "offset": 31,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "OTG_HS_GINTSTS": {
+ "description": "OTG_HS core interrupt register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 67108896,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CMOD": {
+ "description": "Current mode of operation",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ },
+ "MMIS": {
+ "description": "Mode mismatch interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "OTGINT": {
+ "description": "OTG interrupt",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SOF": {
+ "description": "Start of frame",
+ "offset": 3,
+ "size": 1
+ },
+ "RXFLVL": {
+ "description": "RxFIFO nonempty",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NPTXFE": {
+ "description": "Nonperiodic TxFIFO empty",
+ "offset": 5,
+ "size": 1,
+ "access": "read-only"
+ },
+ "GINAKEFF": {
+ "description": "Global IN nonperiodic NAK\n effective",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "BOUTNAKEFF": {
+ "description": "Global OUT NAK effective",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ESUSP": {
+ "description": "Early suspend",
+ "offset": 10,
+ "size": 1
+ },
+ "USBSUSP": {
+ "description": "USB suspend",
+ "offset": 11,
+ "size": 1
+ },
+ "USBRST": {
+ "description": "USB reset",
+ "offset": 12,
+ "size": 1
+ },
+ "ENUMDNE": {
+ "description": "Enumeration done",
+ "offset": 13,
+ "size": 1
+ },
+ "ISOODRP": {
+ "description": "Isochronous OUT packet dropped\n interrupt",
+ "offset": 14,
+ "size": 1
+ },
+ "EOPF": {
+ "description": "End of periodic frame\n interrupt",
+ "offset": 15,
+ "size": 1
+ },
+ "IEPINT": {
+ "description": "IN endpoint interrupt",
+ "offset": 18,
+ "size": 1,
+ "access": "read-only"
+ },
+ "OEPINT": {
+ "description": "OUT endpoint interrupt",
+ "offset": 19,
+ "size": 1,
+ "access": "read-only"
+ },
+ "IISOIXFR": {
+ "description": "Incomplete isochronous IN\n transfer",
+ "offset": 20,
+ "size": 1
+ },
+ "PXFR_INCOMPISOOUT": {
+ "description": "Incomplete periodic\n transfer",
+ "offset": 21,
+ "size": 1
+ },
+ "DATAFSUSP": {
+ "description": "Data fetch suspended",
+ "offset": 22,
+ "size": 1
+ },
+ "HPRTINT": {
+ "description": "Host port interrupt",
+ "offset": 24,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HCINT": {
+ "description": "Host channels interrupt",
+ "offset": 25,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PTXFE": {
+ "description": "Periodic TxFIFO empty",
+ "offset": 26,
+ "size": 1,
+ "access": "read-only"
+ },
+ "CIDSCHG": {
+ "description": "Connector ID status change",
+ "offset": 28,
+ "size": 1
+ },
+ "DISCINT": {
+ "description": "Disconnect detected\n interrupt",
+ "offset": 29,
+ "size": 1
+ },
+ "SRQINT": {
+ "description": "Session request/new session detected\n interrupt",
+ "offset": 30,
+ "size": 1
+ },
+ "WKUINT": {
+ "description": "Resume/remote wakeup detected\n interrupt",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_GINTMSK": {
+ "description": "OTG_HS interrupt mask register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MMISM": {
+ "description": "Mode mismatch interrupt\n mask",
+ "offset": 1,
+ "size": 1
+ },
+ "OTGINT": {
+ "description": "OTG interrupt mask",
+ "offset": 2,
+ "size": 1
+ },
+ "SOFM": {
+ "description": "Start of frame mask",
+ "offset": 3,
+ "size": 1
+ },
+ "RXFLVLM": {
+ "description": "Receive FIFO nonempty mask",
+ "offset": 4,
+ "size": 1
+ },
+ "NPTXFEM": {
+ "description": "Nonperiodic TxFIFO empty\n mask",
+ "offset": 5,
+ "size": 1
+ },
+ "GINAKEFFM": {
+ "description": "Global nonperiodic IN NAK effective\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "GONAKEFFM": {
+ "description": "Global OUT NAK effective\n mask",
+ "offset": 7,
+ "size": 1
+ },
+ "ESUSPM": {
+ "description": "Early suspend mask",
+ "offset": 10,
+ "size": 1
+ },
+ "USBSUSPM": {
+ "description": "USB suspend mask",
+ "offset": 11,
+ "size": 1
+ },
+ "USBRST": {
+ "description": "USB reset mask",
+ "offset": 12,
+ "size": 1
+ },
+ "ENUMDNEM": {
+ "description": "Enumeration done mask",
+ "offset": 13,
+ "size": 1
+ },
+ "ISOODRPM": {
+ "description": "Isochronous OUT packet dropped interrupt\n mask",
+ "offset": 14,
+ "size": 1
+ },
+ "EOPFM": {
+ "description": "End of periodic frame interrupt\n mask",
+ "offset": 15,
+ "size": 1
+ },
+ "EPMISM": {
+ "description": "Endpoint mismatch interrupt\n mask",
+ "offset": 17,
+ "size": 1
+ },
+ "IEPINT": {
+ "description": "IN endpoints interrupt\n mask",
+ "offset": 18,
+ "size": 1
+ },
+ "OEPINT": {
+ "description": "OUT endpoints interrupt\n mask",
+ "offset": 19,
+ "size": 1
+ },
+ "IISOIXFRM": {
+ "description": "Incomplete isochronous IN transfer\n mask",
+ "offset": 20,
+ "size": 1
+ },
+ "PXFRM_IISOOXFRM": {
+ "description": "Incomplete periodic transfer\n mask",
+ "offset": 21,
+ "size": 1
+ },
+ "FSUSPM": {
+ "description": "Data fetch suspended mask",
+ "offset": 22,
+ "size": 1
+ },
+ "PRTIM": {
+ "description": "Host port interrupt mask",
+ "offset": 24,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HCIM": {
+ "description": "Host channels interrupt\n mask",
+ "offset": 25,
+ "size": 1
+ },
+ "PTXFEM": {
+ "description": "Periodic TxFIFO empty mask",
+ "offset": 26,
+ "size": 1
+ },
+ "CIDSCHGM": {
+ "description": "Connector ID status change\n mask",
+ "offset": 28,
+ "size": 1
+ },
+ "DISCINT": {
+ "description": "Disconnect detected interrupt\n mask",
+ "offset": 29,
+ "size": 1
+ },
+ "SRQIM": {
+ "description": "Session request/new session detected\n interrupt mask",
+ "offset": 30,
+ "size": 1
+ },
+ "WUIM": {
+ "description": "Resume/remote wakeup detected interrupt\n mask",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_GRXSTSR_Host": {
+ "description": "OTG_HS Receive status debug read register\n (host mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CHNUM": {
+ "description": "Channel number",
+ "offset": 0,
+ "size": 4
+ },
+ "BCNT": {
+ "description": "Byte count",
+ "offset": 4,
+ "size": 11
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 15,
+ "size": 2
+ },
+ "PKTSTS": {
+ "description": "Packet status",
+ "offset": 17,
+ "size": 4
+ }
+ }
+ }
+ },
+ "OTG_HS_GRXSTSP_Host": {
+ "description": "OTG_HS status read and pop register (host\n mode)",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CHNUM": {
+ "description": "Channel number",
+ "offset": 0,
+ "size": 4
+ },
+ "BCNT": {
+ "description": "Byte count",
+ "offset": 4,
+ "size": 11
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 15,
+ "size": 2
+ },
+ "PKTSTS": {
+ "description": "Packet status",
+ "offset": 17,
+ "size": 4
+ }
+ }
+ }
+ },
+ "OTG_HS_GRXFSIZ": {
+ "description": "OTG_HS Receive FIFO size\n register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 512,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RXFD": {
+ "description": "RxFIFO depth",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_GNPTXFSIZ_Host": {
+ "description": "OTG_HS nonperiodic transmit FIFO size\n register (host mode)",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 512,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NPTXFSA": {
+ "description": "Nonperiodic transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "NPTXFD": {
+ "description": "Nonperiodic TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_TX0FSIZ_Peripheral": {
+ "description": "Endpoint 0 transmit FIFO size (peripheral\n mode)",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 512,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TX0FSA": {
+ "description": "Endpoint 0 transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "TX0FD": {
+ "description": "Endpoint 0 TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_GNPTXSTS": {
+ "description": "OTG_HS nonperiodic transmit FIFO/queue\n status register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 524800,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "NPTXFSAV": {
+ "description": "Nonperiodic TxFIFO space\n available",
+ "offset": 0,
+ "size": 16
+ },
+ "NPTQXSAV": {
+ "description": "Nonperiodic transmit request queue space\n available",
+ "offset": 16,
+ "size": 8
+ },
+ "NPTXQTOP": {
+ "description": "Top of the nonperiodic transmit request\n queue",
+ "offset": 24,
+ "size": 7
+ }
+ }
+ }
+ },
+ "OTG_HS_GCCFG": {
+ "description": "OTG_HS general core configuration\n register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PWRDWN": {
+ "description": "Power down",
+ "offset": 16,
+ "size": 1
+ },
+ "I2CPADEN": {
+ "description": "Enable I2C bus connection for the\n external I2C PHY interface",
+ "offset": 17,
+ "size": 1
+ },
+ "VBUSASEN": {
+ "description": "Enable the VBUS sensing\n device",
+ "offset": 18,
+ "size": 1
+ },
+ "VBUSBSEN": {
+ "description": "Enable the VBUS sensing\n device",
+ "offset": 19,
+ "size": 1
+ },
+ "SOFOUTEN": {
+ "description": "SOF output enable",
+ "offset": 20,
+ "size": 1
+ },
+ "NOVBUSSENS": {
+ "description": "VBUS sensing disable\n option",
+ "offset": 21,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_CID": {
+ "description": "OTG_HS core ID register",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 4608,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRODUCT_ID": {
+ "description": "Product ID field",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_HPTXFSIZ": {
+ "description": "OTG_HS Host periodic transmit FIFO size\n register",
+ "offset": 256,
+ "size": 32,
+ "reset_value": 33555968,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PTXSA": {
+ "description": "Host periodic TxFIFO start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "PTXFD": {
+ "description": "Host periodic TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPTXF1": {
+ "description": "OTG_HS device IN endpoint transmit FIFO size\n register",
+ "offset": 260,
+ "size": 32,
+ "reset_value": 33555456,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INEPTXSA": {
+ "description": "IN endpoint FIFOx transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "INEPTXFD": {
+ "description": "IN endpoint TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPTXF2": {
+ "description": "OTG_HS device IN endpoint transmit FIFO size\n register",
+ "offset": 264,
+ "size": 32,
+ "reset_value": 33555456,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INEPTXSA": {
+ "description": "IN endpoint FIFOx transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "INEPTXFD": {
+ "description": "IN endpoint TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPTXF3": {
+ "description": "OTG_HS device IN endpoint transmit FIFO size\n register",
+ "offset": 284,
+ "size": 32,
+ "reset_value": 33555456,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INEPTXSA": {
+ "description": "IN endpoint FIFOx transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "INEPTXFD": {
+ "description": "IN endpoint TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPTXF4": {
+ "description": "OTG_HS device IN endpoint transmit FIFO size\n register",
+ "offset": 288,
+ "size": 32,
+ "reset_value": 33555456,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INEPTXSA": {
+ "description": "IN endpoint FIFOx transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "INEPTXFD": {
+ "description": "IN endpoint TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPTXF5": {
+ "description": "OTG_HS device IN endpoint transmit FIFO size\n register",
+ "offset": 292,
+ "size": 32,
+ "reset_value": 33555456,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INEPTXSA": {
+ "description": "IN endpoint FIFOx transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "INEPTXFD": {
+ "description": "IN endpoint TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPTXF6": {
+ "description": "OTG_HS device IN endpoint transmit FIFO size\n register",
+ "offset": 296,
+ "size": 32,
+ "reset_value": 33555456,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INEPTXSA": {
+ "description": "IN endpoint FIFOx transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "INEPTXFD": {
+ "description": "IN endpoint TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPTXF7": {
+ "description": "OTG_HS device IN endpoint transmit FIFO size\n register",
+ "offset": 300,
+ "size": 32,
+ "reset_value": 33555456,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INEPTXSA": {
+ "description": "IN endpoint FIFOx transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "INEPTXFD": {
+ "description": "IN endpoint TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_GRXSTSR_Peripheral": {
+ "description": "OTG_HS Receive status debug read register\n (peripheral mode mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 0,
+ "size": 4
+ },
+ "BCNT": {
+ "description": "Byte count",
+ "offset": 4,
+ "size": 11
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 15,
+ "size": 2
+ },
+ "PKTSTS": {
+ "description": "Packet status",
+ "offset": 17,
+ "size": 4
+ },
+ "FRMNUM": {
+ "description": "Frame number",
+ "offset": 21,
+ "size": 4
+ }
+ }
+ }
+ },
+ "OTG_HS_GRXSTSP_Peripheral": {
+ "description": "OTG_HS status read and pop register\n (peripheral mode)",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 0,
+ "size": 4
+ },
+ "BCNT": {
+ "description": "Byte count",
+ "offset": 4,
+ "size": 11
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 15,
+ "size": 2
+ },
+ "PKTSTS": {
+ "description": "Packet status",
+ "offset": 17,
+ "size": 4
+ },
+ "FRMNUM": {
+ "description": "Frame number",
+ "offset": 21,
+ "size": 4
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "SDIO": {
+ "description": "Secure digital input/output\n interface",
+ "children": {
+ "registers": {
+ "POWER": {
+ "description": "power control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PWRCTRL": {
+ "description": "PWRCTRL",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CLKCR": {
+ "description": "SDI clock control register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "HWFC_EN": {
+ "description": "HW Flow Control enable",
+ "offset": 14,
+ "size": 1
+ },
+ "NEGEDGE": {
+ "description": "SDIO_CK dephasing selection\n bit",
+ "offset": 13,
+ "size": 1
+ },
+ "WIDBUS": {
+ "description": "Wide bus mode enable bit",
+ "offset": 11,
+ "size": 2
+ },
+ "BYPASS": {
+ "description": "Clock divider bypass enable\n bit",
+ "offset": 10,
+ "size": 1
+ },
+ "PWRSAV": {
+ "description": "Power saving configuration\n bit",
+ "offset": 9,
+ "size": 1
+ },
+ "CLKEN": {
+ "description": "Clock enable bit",
+ "offset": 8,
+ "size": 1
+ },
+ "CLKDIV": {
+ "description": "Clock divide factor",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "ARG": {
+ "description": "argument register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CMDARG": {
+ "description": "Command argument",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CMD": {
+ "description": "command register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CE_ATACMD": {
+ "description": "CE-ATA command",
+ "offset": 14,
+ "size": 1
+ },
+ "nIEN": {
+ "description": "not Interrupt Enable",
+ "offset": 13,
+ "size": 1
+ },
+ "ENCMDcompl": {
+ "description": "Enable CMD completion",
+ "offset": 12,
+ "size": 1
+ },
+ "SDIOSuspend": {
+ "description": "SD I/O suspend command",
+ "offset": 11,
+ "size": 1
+ },
+ "CPSMEN": {
+ "description": "Command path state machine (CPSM) Enable\n bit",
+ "offset": 10,
+ "size": 1
+ },
+ "WAITPEND": {
+ "description": "CPSM Waits for ends of data transfer\n (CmdPend internal signal).",
+ "offset": 9,
+ "size": 1
+ },
+ "WAITINT": {
+ "description": "CPSM waits for interrupt\n request",
+ "offset": 8,
+ "size": 1
+ },
+ "WAITRESP": {
+ "description": "Wait for response bits",
+ "offset": 6,
+ "size": 2
+ },
+ "CMDINDEX": {
+ "description": "Command index",
+ "offset": 0,
+ "size": 6
+ }
+ }
+ }
+ },
+ "RESPCMD": {
+ "description": "command response register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "RESPCMD": {
+ "description": "Response command index",
+ "offset": 0,
+ "size": 6
+ }
+ }
+ }
+ },
+ "RESP1": {
+ "description": "response 1..4 register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CARDSTATUS1": {
+ "description": "see Table 132.",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "RESP2": {
+ "description": "response 1..4 register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CARDSTATUS2": {
+ "description": "see Table 132.",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "RESP3": {
+ "description": "response 1..4 register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CARDSTATUS3": {
+ "description": "see Table 132.",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "RESP4": {
+ "description": "response 1..4 register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CARDSTATUS4": {
+ "description": "see Table 132.",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DTIMER": {
+ "description": "data timer register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATATIME": {
+ "description": "Data timeout period",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DLEN": {
+ "description": "data length register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATALENGTH": {
+ "description": "Data length value",
+ "offset": 0,
+ "size": 25
+ }
+ }
+ }
+ },
+ "DCTRL": {
+ "description": "data control register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SDIOEN": {
+ "description": "SD I/O enable functions",
+ "offset": 11,
+ "size": 1
+ },
+ "RWMOD": {
+ "description": "Read wait mode",
+ "offset": 10,
+ "size": 1
+ },
+ "RWSTOP": {
+ "description": "Read wait stop",
+ "offset": 9,
+ "size": 1
+ },
+ "RWSTART": {
+ "description": "Read wait start",
+ "offset": 8,
+ "size": 1
+ },
+ "DBLOCKSIZE": {
+ "description": "Data block size",
+ "offset": 4,
+ "size": 4
+ },
+ "DMAEN": {
+ "description": "DMA enable bit",
+ "offset": 3,
+ "size": 1
+ },
+ "DTMODE": {
+ "description": "Data transfer mode selection 1: Stream\n or SDIO multibyte data transfer.",
+ "offset": 2,
+ "size": 1
+ },
+ "DTDIR": {
+ "description": "Data transfer direction\n selection",
+ "offset": 1,
+ "size": 1
+ },
+ "DTEN": {
+ "description": "DTEN",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DCOUNT": {
+ "description": "data counter register",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DATACOUNT": {
+ "description": "Data count value",
+ "offset": 0,
+ "size": 25
+ }
+ }
+ }
+ },
+ "STA": {
+ "description": "status register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CEATAEND": {
+ "description": "CE-ATA command completion signal\n received for CMD61",
+ "offset": 23,
+ "size": 1
+ },
+ "SDIOIT": {
+ "description": "SDIO interrupt received",
+ "offset": 22,
+ "size": 1
+ },
+ "RXDAVL": {
+ "description": "Data available in receive\n FIFO",
+ "offset": 21,
+ "size": 1
+ },
+ "TXDAVL": {
+ "description": "Data available in transmit\n FIFO",
+ "offset": 20,
+ "size": 1
+ },
+ "RXFIFOE": {
+ "description": "Receive FIFO empty",
+ "offset": 19,
+ "size": 1
+ },
+ "TXFIFOE": {
+ "description": "Transmit FIFO empty",
+ "offset": 18,
+ "size": 1
+ },
+ "RXFIFOF": {
+ "description": "Receive FIFO full",
+ "offset": 17,
+ "size": 1
+ },
+ "TXFIFOF": {
+ "description": "Transmit FIFO full",
+ "offset": 16,
+ "size": 1
+ },
+ "RXFIFOHF": {
+ "description": "Receive FIFO half full: there are at\n least 8 words in the FIFO",
+ "offset": 15,
+ "size": 1
+ },
+ "TXFIFOHE": {
+ "description": "Transmit FIFO half empty: at least 8\n words can be written into the FIFO",
+ "offset": 14,
+ "size": 1
+ },
+ "RXACT": {
+ "description": "Data receive in progress",
+ "offset": 13,
+ "size": 1
+ },
+ "TXACT": {
+ "description": "Data transmit in progress",
+ "offset": 12,
+ "size": 1
+ },
+ "CMDACT": {
+ "description": "Command transfer in\n progress",
+ "offset": 11,
+ "size": 1
+ },
+ "DBCKEND": {
+ "description": "Data block sent/received (CRC check\n passed)",
+ "offset": 10,
+ "size": 1
+ },
+ "STBITERR": {
+ "description": "Start bit not detected on all data\n signals in wide bus mode",
+ "offset": 9,
+ "size": 1
+ },
+ "DATAEND": {
+ "description": "Data end (data counter, SDIDCOUNT, is\n zero)",
+ "offset": 8,
+ "size": 1
+ },
+ "CMDSENT": {
+ "description": "Command sent (no response\n required)",
+ "offset": 7,
+ "size": 1
+ },
+ "CMDREND": {
+ "description": "Command response received (CRC check\n passed)",
+ "offset": 6,
+ "size": 1
+ },
+ "RXOVERR": {
+ "description": "Received FIFO overrun\n error",
+ "offset": 5,
+ "size": 1
+ },
+ "TXUNDERR": {
+ "description": "Transmit FIFO underrun\n error",
+ "offset": 4,
+ "size": 1
+ },
+ "DTIMEOUT": {
+ "description": "Data timeout",
+ "offset": 3,
+ "size": 1
+ },
+ "CTIMEOUT": {
+ "description": "Command response timeout",
+ "offset": 2,
+ "size": 1
+ },
+ "DCRCFAIL": {
+ "description": "Data block sent/received (CRC check\n failed)",
+ "offset": 1,
+ "size": 1
+ },
+ "CCRCFAIL": {
+ "description": "Command response received (CRC check\n failed)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ICR": {
+ "description": "interrupt clear register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CEATAENDC": {
+ "description": "CEATAEND flag clear bit",
+ "offset": 23,
+ "size": 1
+ },
+ "SDIOITC": {
+ "description": "SDIOIT flag clear bit",
+ "offset": 22,
+ "size": 1
+ },
+ "DBCKENDC": {
+ "description": "DBCKEND flag clear bit",
+ "offset": 10,
+ "size": 1
+ },
+ "STBITERRC": {
+ "description": "STBITERR flag clear bit",
+ "offset": 9,
+ "size": 1
+ },
+ "DATAENDC": {
+ "description": "DATAEND flag clear bit",
+ "offset": 8,
+ "size": 1
+ },
+ "CMDSENTC": {
+ "description": "CMDSENT flag clear bit",
+ "offset": 7,
+ "size": 1
+ },
+ "CMDRENDC": {
+ "description": "CMDREND flag clear bit",
+ "offset": 6,
+ "size": 1
+ },
+ "RXOVERRC": {
+ "description": "RXOVERR flag clear bit",
+ "offset": 5,
+ "size": 1
+ },
+ "TXUNDERRC": {
+ "description": "TXUNDERR flag clear bit",
+ "offset": 4,
+ "size": 1
+ },
+ "DTIMEOUTC": {
+ "description": "DTIMEOUT flag clear bit",
+ "offset": 3,
+ "size": 1
+ },
+ "CTIMEOUTC": {
+ "description": "CTIMEOUT flag clear bit",
+ "offset": 2,
+ "size": 1
+ },
+ "DCRCFAILC": {
+ "description": "DCRCFAIL flag clear bit",
+ "offset": 1,
+ "size": 1
+ },
+ "CCRCFAILC": {
+ "description": "CCRCFAIL flag clear bit",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MASK": {
+ "description": "mask register",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CEATAENDIE": {
+ "description": "CE-ATA command completion signal\n received interrupt enable",
+ "offset": 23,
+ "size": 1
+ },
+ "SDIOITIE": {
+ "description": "SDIO mode interrupt received interrupt\n enable",
+ "offset": 22,
+ "size": 1
+ },
+ "RXDAVLIE": {
+ "description": "Data available in Rx FIFO interrupt\n enable",
+ "offset": 21,
+ "size": 1
+ },
+ "TXDAVLIE": {
+ "description": "Data available in Tx FIFO interrupt\n enable",
+ "offset": 20,
+ "size": 1
+ },
+ "RXFIFOEIE": {
+ "description": "Rx FIFO empty interrupt\n enable",
+ "offset": 19,
+ "size": 1
+ },
+ "TXFIFOEIE": {
+ "description": "Tx FIFO empty interrupt\n enable",
+ "offset": 18,
+ "size": 1
+ },
+ "RXFIFOFIE": {
+ "description": "Rx FIFO full interrupt\n enable",
+ "offset": 17,
+ "size": 1
+ },
+ "TXFIFOFIE": {
+ "description": "Tx FIFO full interrupt\n enable",
+ "offset": 16,
+ "size": 1
+ },
+ "RXFIFOHFIE": {
+ "description": "Rx FIFO half full interrupt\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "TXFIFOHEIE": {
+ "description": "Tx FIFO half empty interrupt\n enable",
+ "offset": 14,
+ "size": 1
+ },
+ "RXACTIE": {
+ "description": "Data receive acting interrupt\n enable",
+ "offset": 13,
+ "size": 1
+ },
+ "TXACTIE": {
+ "description": "Data transmit acting interrupt\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "CMDACTIE": {
+ "description": "Command acting interrupt\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "DBCKENDIE": {
+ "description": "Data block end interrupt\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "STBITERRIE": {
+ "description": "Start bit error interrupt\n enable",
+ "offset": 9,
+ "size": 1
+ },
+ "DATAENDIE": {
+ "description": "Data end interrupt enable",
+ "offset": 8,
+ "size": 1
+ },
+ "CMDSENTIE": {
+ "description": "Command sent interrupt\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "CMDRENDIE": {
+ "description": "Command response received interrupt\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "RXOVERRIE": {
+ "description": "Rx FIFO overrun error interrupt\n enable",
+ "offset": 5,
+ "size": 1
+ },
+ "TXUNDERRIE": {
+ "description": "Tx FIFO underrun error interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "DTIMEOUTIE": {
+ "description": "Data timeout interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "CTIMEOUTIE": {
+ "description": "Command timeout interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "DCRCFAILIE": {
+ "description": "Data CRC fail interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "CCRCFAILIE": {
+ "description": "Command CRC fail interrupt\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FIFOCNT": {
+ "description": "FIFO counter register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "FIFOCOUNT": {
+ "description": "Remaining number of words to be written\n to or read from the FIFO.",
+ "offset": 0,
+ "size": 24
+ }
+ }
+ }
+ },
+ "FIFO": {
+ "description": "data FIFO register",
+ "offset": 128,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FIFOData": {
+ "description": "Receive and transmit FIFO\n data",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "ADC1": {
+ "description": "Analog-to-digital converter",
+ "children": {
+ "registers": {
+ "SR": {
+ "description": "status register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OVR": {
+ "description": "Overrun",
+ "offset": 5,
+ "size": 1
+ },
+ "STRT": {
+ "description": "Regular channel start flag",
+ "offset": 4,
+ "size": 1
+ },
+ "JSTRT": {
+ "description": "Injected channel start\n flag",
+ "offset": 3,
+ "size": 1
+ },
+ "JEOC": {
+ "description": "Injected channel end of\n conversion",
+ "offset": 2,
+ "size": 1
+ },
+ "EOC": {
+ "description": "Regular channel end of\n conversion",
+ "offset": 1,
+ "size": 1
+ },
+ "AWD": {
+ "description": "Analog watchdog flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR1": {
+ "description": "control register 1",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OVRIE": {
+ "description": "Overrun interrupt enable",
+ "offset": 26,
+ "size": 1
+ },
+ "RES": {
+ "description": "Resolution",
+ "offset": 24,
+ "size": 2
+ },
+ "AWDEN": {
+ "description": "Analog watchdog enable on regular\n channels",
+ "offset": 23,
+ "size": 1
+ },
+ "JAWDEN": {
+ "description": "Analog watchdog enable on injected\n channels",
+ "offset": 22,
+ "size": 1
+ },
+ "DISCNUM": {
+ "description": "Discontinuous mode channel\n count",
+ "offset": 13,
+ "size": 3
+ },
+ "JDISCEN": {
+ "description": "Discontinuous mode on injected\n channels",
+ "offset": 12,
+ "size": 1
+ },
+ "DISCEN": {
+ "description": "Discontinuous mode on regular\n channels",
+ "offset": 11,
+ "size": 1
+ },
+ "JAUTO": {
+ "description": "Automatic injected group\n conversion",
+ "offset": 10,
+ "size": 1
+ },
+ "AWDSGL": {
+ "description": "Enable the watchdog on a single channel\n in scan mode",
+ "offset": 9,
+ "size": 1
+ },
+ "SCAN": {
+ "description": "Scan mode",
+ "offset": 8,
+ "size": 1
+ },
+ "JEOCIE": {
+ "description": "Interrupt enable for injected\n channels",
+ "offset": 7,
+ "size": 1
+ },
+ "AWDIE": {
+ "description": "Analog watchdog interrupt\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "EOCIE": {
+ "description": "Interrupt enable for EOC",
+ "offset": 5,
+ "size": 1
+ },
+ "AWDCH": {
+ "description": "Analog watchdog channel select\n bits",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SWSTART": {
+ "description": "Start conversion of regular\n channels",
+ "offset": 30,
+ "size": 1
+ },
+ "EXTEN": {
+ "description": "External trigger enable for regular\n channels",
+ "offset": 28,
+ "size": 2
+ },
+ "EXTSEL": {
+ "description": "External event select for regular\n group",
+ "offset": 24,
+ "size": 4
+ },
+ "JSWSTART": {
+ "description": "Start conversion of injected\n channels",
+ "offset": 22,
+ "size": 1
+ },
+ "JEXTEN": {
+ "description": "External trigger enable for injected\n channels",
+ "offset": 20,
+ "size": 2
+ },
+ "JEXTSEL": {
+ "description": "External event select for injected\n group",
+ "offset": 16,
+ "size": 4
+ },
+ "ALIGN": {
+ "description": "Data alignment",
+ "offset": 11,
+ "size": 1
+ },
+ "EOCS": {
+ "description": "End of conversion\n selection",
+ "offset": 10,
+ "size": 1
+ },
+ "DDS": {
+ "description": "DMA disable selection (for single ADC\n mode)",
+ "offset": 9,
+ "size": 1
+ },
+ "DMA": {
+ "description": "Direct memory access mode (for single\n ADC mode)",
+ "offset": 8,
+ "size": 1
+ },
+ "CONT": {
+ "description": "Continuous conversion",
+ "offset": 1,
+ "size": 1
+ },
+ "ADON": {
+ "description": "A/D Converter ON / OFF",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SMPR1": {
+ "description": "sample time register 1",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SMPx_x": {
+ "description": "Sample time bits",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "SMPR2": {
+ "description": "sample time register 2",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SMPx_x": {
+ "description": "Sample time bits",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "JOFR1": {
+ "description": "injected channel data offset register\n x",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "JOFFSET1": {
+ "description": "Data offset for injected channel\n x",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "JOFR2": {
+ "description": "injected channel data offset register\n x",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "JOFFSET2": {
+ "description": "Data offset for injected channel\n x",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "JOFR3": {
+ "description": "injected channel data offset register\n x",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "JOFFSET3": {
+ "description": "Data offset for injected channel\n x",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "JOFR4": {
+ "description": "injected channel data offset register\n x",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "JOFFSET4": {
+ "description": "Data offset for injected channel\n x",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "HTR": {
+ "description": "watchdog higher threshold\n register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 4095,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "HT": {
+ "description": "Analog watchdog higher\n threshold",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "LTR": {
+ "description": "watchdog lower threshold\n register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LT": {
+ "description": "Analog watchdog lower\n threshold",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "SQR1": {
+ "description": "regular sequence register 1",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "L": {
+ "description": "Regular channel sequence\n length",
+ "offset": 20,
+ "size": 4
+ },
+ "SQ16": {
+ "description": "16th conversion in regular\n sequence",
+ "offset": 15,
+ "size": 5
+ },
+ "SQ15": {
+ "description": "15th conversion in regular\n sequence",
+ "offset": 10,
+ "size": 5
+ },
+ "SQ14": {
+ "description": "14th conversion in regular\n sequence",
+ "offset": 5,
+ "size": 5
+ },
+ "SQ13": {
+ "description": "13th conversion in regular\n sequence",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "SQR2": {
+ "description": "regular sequence register 2",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SQ12": {
+ "description": "12th conversion in regular\n sequence",
+ "offset": 25,
+ "size": 5
+ },
+ "SQ11": {
+ "description": "11th conversion in regular\n sequence",
+ "offset": 20,
+ "size": 5
+ },
+ "SQ10": {
+ "description": "10th conversion in regular\n sequence",
+ "offset": 15,
+ "size": 5
+ },
+ "SQ9": {
+ "description": "9th conversion in regular\n sequence",
+ "offset": 10,
+ "size": 5
+ },
+ "SQ8": {
+ "description": "8th conversion in regular\n sequence",
+ "offset": 5,
+ "size": 5
+ },
+ "SQ7": {
+ "description": "7th conversion in regular\n sequence",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "SQR3": {
+ "description": "regular sequence register 3",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SQ6": {
+ "description": "6th conversion in regular\n sequence",
+ "offset": 25,
+ "size": 5
+ },
+ "SQ5": {
+ "description": "5th conversion in regular\n sequence",
+ "offset": 20,
+ "size": 5
+ },
+ "SQ4": {
+ "description": "4th conversion in regular\n sequence",
+ "offset": 15,
+ "size": 5
+ },
+ "SQ3": {
+ "description": "3rd conversion in regular\n sequence",
+ "offset": 10,
+ "size": 5
+ },
+ "SQ2": {
+ "description": "2nd conversion in regular\n sequence",
+ "offset": 5,
+ "size": 5
+ },
+ "SQ1": {
+ "description": "1st conversion in regular\n sequence",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "JSQR": {
+ "description": "injected sequence register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "JL": {
+ "description": "Injected sequence length",
+ "offset": 20,
+ "size": 2
+ },
+ "JSQ4": {
+ "description": "4th conversion in injected\n sequence",
+ "offset": 15,
+ "size": 5
+ },
+ "JSQ3": {
+ "description": "3rd conversion in injected\n sequence",
+ "offset": 10,
+ "size": 5
+ },
+ "JSQ2": {
+ "description": "2nd conversion in injected\n sequence",
+ "offset": 5,
+ "size": 5
+ },
+ "JSQ1": {
+ "description": "1st conversion in injected\n sequence",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "JDR1": {
+ "description": "injected data register x",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "JDATA": {
+ "description": "Injected data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "JDR2": {
+ "description": "injected data register x",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "JDATA": {
+ "description": "Injected data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "JDR3": {
+ "description": "injected data register x",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "JDATA": {
+ "description": "Injected data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "JDR4": {
+ "description": "injected data register x",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "JDATA": {
+ "description": "Injected data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR": {
+ "description": "regular data register",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DATA": {
+ "description": "Regular data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "EXTI": {
+ "description": "External interrupt/event\n controller",
+ "children": {
+ "registers": {
+ "IMR": {
+ "description": "Interrupt mask register\n (EXTI_IMR)",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MR0": {
+ "description": "Interrupt Mask on line 0",
+ "offset": 0,
+ "size": 1
+ },
+ "MR1": {
+ "description": "Interrupt Mask on line 1",
+ "offset": 1,
+ "size": 1
+ },
+ "MR2": {
+ "description": "Interrupt Mask on line 2",
+ "offset": 2,
+ "size": 1
+ },
+ "MR3": {
+ "description": "Interrupt Mask on line 3",
+ "offset": 3,
+ "size": 1
+ },
+ "MR4": {
+ "description": "Interrupt Mask on line 4",
+ "offset": 4,
+ "size": 1
+ },
+ "MR5": {
+ "description": "Interrupt Mask on line 5",
+ "offset": 5,
+ "size": 1
+ },
+ "MR6": {
+ "description": "Interrupt Mask on line 6",
+ "offset": 6,
+ "size": 1
+ },
+ "MR7": {
+ "description": "Interrupt Mask on line 7",
+ "offset": 7,
+ "size": 1
+ },
+ "MR8": {
+ "description": "Interrupt Mask on line 8",
+ "offset": 8,
+ "size": 1
+ },
+ "MR9": {
+ "description": "Interrupt Mask on line 9",
+ "offset": 9,
+ "size": 1
+ },
+ "MR10": {
+ "description": "Interrupt Mask on line 10",
+ "offset": 10,
+ "size": 1
+ },
+ "MR11": {
+ "description": "Interrupt Mask on line 11",
+ "offset": 11,
+ "size": 1
+ },
+ "MR12": {
+ "description": "Interrupt Mask on line 12",
+ "offset": 12,
+ "size": 1
+ },
+ "MR13": {
+ "description": "Interrupt Mask on line 13",
+ "offset": 13,
+ "size": 1
+ },
+ "MR14": {
+ "description": "Interrupt Mask on line 14",
+ "offset": 14,
+ "size": 1
+ },
+ "MR15": {
+ "description": "Interrupt Mask on line 15",
+ "offset": 15,
+ "size": 1
+ },
+ "MR16": {
+ "description": "Interrupt Mask on line 16",
+ "offset": 16,
+ "size": 1
+ },
+ "MR17": {
+ "description": "Interrupt Mask on line 17",
+ "offset": 17,
+ "size": 1
+ },
+ "MR18": {
+ "description": "Interrupt Mask on line 18",
+ "offset": 18,
+ "size": 1
+ },
+ "MR19": {
+ "description": "Interrupt Mask on line 19",
+ "offset": 19,
+ "size": 1
+ },
+ "MR20": {
+ "description": "Interrupt Mask on line 20",
+ "offset": 20,
+ "size": 1
+ },
+ "MR21": {
+ "description": "Interrupt Mask on line 21",
+ "offset": 21,
+ "size": 1
+ },
+ "MR22": {
+ "description": "Interrupt Mask on line 22",
+ "offset": 22,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EMR": {
+ "description": "Event mask register (EXTI_EMR)",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MR0": {
+ "description": "Event Mask on line 0",
+ "offset": 0,
+ "size": 1
+ },
+ "MR1": {
+ "description": "Event Mask on line 1",
+ "offset": 1,
+ "size": 1
+ },
+ "MR2": {
+ "description": "Event Mask on line 2",
+ "offset": 2,
+ "size": 1
+ },
+ "MR3": {
+ "description": "Event Mask on line 3",
+ "offset": 3,
+ "size": 1
+ },
+ "MR4": {
+ "description": "Event Mask on line 4",
+ "offset": 4,
+ "size": 1
+ },
+ "MR5": {
+ "description": "Event Mask on line 5",
+ "offset": 5,
+ "size": 1
+ },
+ "MR6": {
+ "description": "Event Mask on line 6",
+ "offset": 6,
+ "size": 1
+ },
+ "MR7": {
+ "description": "Event Mask on line 7",
+ "offset": 7,
+ "size": 1
+ },
+ "MR8": {
+ "description": "Event Mask on line 8",
+ "offset": 8,
+ "size": 1
+ },
+ "MR9": {
+ "description": "Event Mask on line 9",
+ "offset": 9,
+ "size": 1
+ },
+ "MR10": {
+ "description": "Event Mask on line 10",
+ "offset": 10,
+ "size": 1
+ },
+ "MR11": {
+ "description": "Event Mask on line 11",
+ "offset": 11,
+ "size": 1
+ },
+ "MR12": {
+ "description": "Event Mask on line 12",
+ "offset": 12,
+ "size": 1
+ },
+ "MR13": {
+ "description": "Event Mask on line 13",
+ "offset": 13,
+ "size": 1
+ },
+ "MR14": {
+ "description": "Event Mask on line 14",
+ "offset": 14,
+ "size": 1
+ },
+ "MR15": {
+ "description": "Event Mask on line 15",
+ "offset": 15,
+ "size": 1
+ },
+ "MR16": {
+ "description": "Event Mask on line 16",
+ "offset": 16,
+ "size": 1
+ },
+ "MR17": {
+ "description": "Event Mask on line 17",
+ "offset": 17,
+ "size": 1
+ },
+ "MR18": {
+ "description": "Event Mask on line 18",
+ "offset": 18,
+ "size": 1
+ },
+ "MR19": {
+ "description": "Event Mask on line 19",
+ "offset": 19,
+ "size": 1
+ },
+ "MR20": {
+ "description": "Event Mask on line 20",
+ "offset": 20,
+ "size": 1
+ },
+ "MR21": {
+ "description": "Event Mask on line 21",
+ "offset": 21,
+ "size": 1
+ },
+ "MR22": {
+ "description": "Event Mask on line 22",
+ "offset": 22,
+ "size": 1
+ }
+ }
+ }
+ },
+ "RTSR": {
+ "description": "Rising Trigger selection register\n (EXTI_RTSR)",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TR0": {
+ "description": "Rising trigger event configuration of\n line 0",
+ "offset": 0,
+ "size": 1
+ },
+ "TR1": {
+ "description": "Rising trigger event configuration of\n line 1",
+ "offset": 1,
+ "size": 1
+ },
+ "TR2": {
+ "description": "Rising trigger event configuration of\n line 2",
+ "offset": 2,
+ "size": 1
+ },
+ "TR3": {
+ "description": "Rising trigger event configuration of\n line 3",
+ "offset": 3,
+ "size": 1
+ },
+ "TR4": {
+ "description": "Rising trigger event configuration of\n line 4",
+ "offset": 4,
+ "size": 1
+ },
+ "TR5": {
+ "description": "Rising trigger event configuration of\n line 5",
+ "offset": 5,
+ "size": 1
+ },
+ "TR6": {
+ "description": "Rising trigger event configuration of\n line 6",
+ "offset": 6,
+ "size": 1
+ },
+ "TR7": {
+ "description": "Rising trigger event configuration of\n line 7",
+ "offset": 7,
+ "size": 1
+ },
+ "TR8": {
+ "description": "Rising trigger event configuration of\n line 8",
+ "offset": 8,
+ "size": 1
+ },
+ "TR9": {
+ "description": "Rising trigger event configuration of\n line 9",
+ "offset": 9,
+ "size": 1
+ },
+ "TR10": {
+ "description": "Rising trigger event configuration of\n line 10",
+ "offset": 10,
+ "size": 1
+ },
+ "TR11": {
+ "description": "Rising trigger event configuration of\n line 11",
+ "offset": 11,
+ "size": 1
+ },
+ "TR12": {
+ "description": "Rising trigger event configuration of\n line 12",
+ "offset": 12,
+ "size": 1
+ },
+ "TR13": {
+ "description": "Rising trigger event configuration of\n line 13",
+ "offset": 13,
+ "size": 1
+ },
+ "TR14": {
+ "description": "Rising trigger event configuration of\n line 14",
+ "offset": 14,
+ "size": 1
+ },
+ "TR15": {
+ "description": "Rising trigger event configuration of\n line 15",
+ "offset": 15,
+ "size": 1
+ },
+ "TR16": {
+ "description": "Rising trigger event configuration of\n line 16",
+ "offset": 16,
+ "size": 1
+ },
+ "TR17": {
+ "description": "Rising trigger event configuration of\n line 17",
+ "offset": 17,
+ "size": 1
+ },
+ "TR18": {
+ "description": "Rising trigger event configuration of\n line 18",
+ "offset": 18,
+ "size": 1
+ },
+ "TR19": {
+ "description": "Rising trigger event configuration of\n line 19",
+ "offset": 19,
+ "size": 1
+ },
+ "TR20": {
+ "description": "Rising trigger event configuration of\n line 20",
+ "offset": 20,
+ "size": 1
+ },
+ "TR21": {
+ "description": "Rising trigger event configuration of\n line 21",
+ "offset": 21,
+ "size": 1
+ },
+ "TR22": {
+ "description": "Rising trigger event configuration of\n line 22",
+ "offset": 22,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FTSR": {
+ "description": "Falling Trigger selection register\n (EXTI_FTSR)",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TR0": {
+ "description": "Falling trigger event configuration of\n line 0",
+ "offset": 0,
+ "size": 1
+ },
+ "TR1": {
+ "description": "Falling trigger event configuration of\n line 1",
+ "offset": 1,
+ "size": 1
+ },
+ "TR2": {
+ "description": "Falling trigger event configuration of\n line 2",
+ "offset": 2,
+ "size": 1
+ },
+ "TR3": {
+ "description": "Falling trigger event configuration of\n line 3",
+ "offset": 3,
+ "size": 1
+ },
+ "TR4": {
+ "description": "Falling trigger event configuration of\n line 4",
+ "offset": 4,
+ "size": 1
+ },
+ "TR5": {
+ "description": "Falling trigger event configuration of\n line 5",
+ "offset": 5,
+ "size": 1
+ },
+ "TR6": {
+ "description": "Falling trigger event configuration of\n line 6",
+ "offset": 6,
+ "size": 1
+ },
+ "TR7": {
+ "description": "Falling trigger event configuration of\n line 7",
+ "offset": 7,
+ "size": 1
+ },
+ "TR8": {
+ "description": "Falling trigger event configuration of\n line 8",
+ "offset": 8,
+ "size": 1
+ },
+ "TR9": {
+ "description": "Falling trigger event configuration of\n line 9",
+ "offset": 9,
+ "size": 1
+ },
+ "TR10": {
+ "description": "Falling trigger event configuration of\n line 10",
+ "offset": 10,
+ "size": 1
+ },
+ "TR11": {
+ "description": "Falling trigger event configuration of\n line 11",
+ "offset": 11,
+ "size": 1
+ },
+ "TR12": {
+ "description": "Falling trigger event configuration of\n line 12",
+ "offset": 12,
+ "size": 1
+ },
+ "TR13": {
+ "description": "Falling trigger event configuration of\n line 13",
+ "offset": 13,
+ "size": 1
+ },
+ "TR14": {
+ "description": "Falling trigger event configuration of\n line 14",
+ "offset": 14,
+ "size": 1
+ },
+ "TR15": {
+ "description": "Falling trigger event configuration of\n line 15",
+ "offset": 15,
+ "size": 1
+ },
+ "TR16": {
+ "description": "Falling trigger event configuration of\n line 16",
+ "offset": 16,
+ "size": 1
+ },
+ "TR17": {
+ "description": "Falling trigger event configuration of\n line 17",
+ "offset": 17,
+ "size": 1
+ },
+ "TR18": {
+ "description": "Falling trigger event configuration of\n line 18",
+ "offset": 18,
+ "size": 1
+ },
+ "TR19": {
+ "description": "Falling trigger event configuration of\n line 19",
+ "offset": 19,
+ "size": 1
+ },
+ "TR20": {
+ "description": "Falling trigger event configuration of\n line 20",
+ "offset": 20,
+ "size": 1
+ },
+ "TR21": {
+ "description": "Falling trigger event configuration of\n line 21",
+ "offset": 21,
+ "size": 1
+ },
+ "TR22": {
+ "description": "Falling trigger event configuration of\n line 22",
+ "offset": 22,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SWIER": {
+ "description": "Software interrupt event register\n (EXTI_SWIER)",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SWIER0": {
+ "description": "Software Interrupt on line\n 0",
+ "offset": 0,
+ "size": 1
+ },
+ "SWIER1": {
+ "description": "Software Interrupt on line\n 1",
+ "offset": 1,
+ "size": 1
+ },
+ "SWIER2": {
+ "description": "Software Interrupt on line\n 2",
+ "offset": 2,
+ "size": 1
+ },
+ "SWIER3": {
+ "description": "Software Interrupt on line\n 3",
+ "offset": 3,
+ "size": 1
+ },
+ "SWIER4": {
+ "description": "Software Interrupt on line\n 4",
+ "offset": 4,
+ "size": 1
+ },
+ "SWIER5": {
+ "description": "Software Interrupt on line\n 5",
+ "offset": 5,
+ "size": 1
+ },
+ "SWIER6": {
+ "description": "Software Interrupt on line\n 6",
+ "offset": 6,
+ "size": 1
+ },
+ "SWIER7": {
+ "description": "Software Interrupt on line\n 7",
+ "offset": 7,
+ "size": 1
+ },
+ "SWIER8": {
+ "description": "Software Interrupt on line\n 8",
+ "offset": 8,
+ "size": 1
+ },
+ "SWIER9": {
+ "description": "Software Interrupt on line\n 9",
+ "offset": 9,
+ "size": 1
+ },
+ "SWIER10": {
+ "description": "Software Interrupt on line\n 10",
+ "offset": 10,
+ "size": 1
+ },
+ "SWIER11": {
+ "description": "Software Interrupt on line\n 11",
+ "offset": 11,
+ "size": 1
+ },
+ "SWIER12": {
+ "description": "Software Interrupt on line\n 12",
+ "offset": 12,
+ "size": 1
+ },
+ "SWIER13": {
+ "description": "Software Interrupt on line\n 13",
+ "offset": 13,
+ "size": 1
+ },
+ "SWIER14": {
+ "description": "Software Interrupt on line\n 14",
+ "offset": 14,
+ "size": 1
+ },
+ "SWIER15": {
+ "description": "Software Interrupt on line\n 15",
+ "offset": 15,
+ "size": 1
+ },
+ "SWIER16": {
+ "description": "Software Interrupt on line\n 16",
+ "offset": 16,
+ "size": 1
+ },
+ "SWIER17": {
+ "description": "Software Interrupt on line\n 17",
+ "offset": 17,
+ "size": 1
+ },
+ "SWIER18": {
+ "description": "Software Interrupt on line\n 18",
+ "offset": 18,
+ "size": 1
+ },
+ "SWIER19": {
+ "description": "Software Interrupt on line\n 19",
+ "offset": 19,
+ "size": 1
+ },
+ "SWIER20": {
+ "description": "Software Interrupt on line\n 20",
+ "offset": 20,
+ "size": 1
+ },
+ "SWIER21": {
+ "description": "Software Interrupt on line\n 21",
+ "offset": 21,
+ "size": 1
+ },
+ "SWIER22": {
+ "description": "Software Interrupt on line\n 22",
+ "offset": 22,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PR": {
+ "description": "Pending register (EXTI_PR)",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PR0": {
+ "description": "Pending bit 0",
+ "offset": 0,
+ "size": 1
+ },
+ "PR1": {
+ "description": "Pending bit 1",
+ "offset": 1,
+ "size": 1
+ },
+ "PR2": {
+ "description": "Pending bit 2",
+ "offset": 2,
+ "size": 1
+ },
+ "PR3": {
+ "description": "Pending bit 3",
+ "offset": 3,
+ "size": 1
+ },
+ "PR4": {
+ "description": "Pending bit 4",
+ "offset": 4,
+ "size": 1
+ },
+ "PR5": {
+ "description": "Pending bit 5",
+ "offset": 5,
+ "size": 1
+ },
+ "PR6": {
+ "description": "Pending bit 6",
+ "offset": 6,
+ "size": 1
+ },
+ "PR7": {
+ "description": "Pending bit 7",
+ "offset": 7,
+ "size": 1
+ },
+ "PR8": {
+ "description": "Pending bit 8",
+ "offset": 8,
+ "size": 1
+ },
+ "PR9": {
+ "description": "Pending bit 9",
+ "offset": 9,
+ "size": 1
+ },
+ "PR10": {
+ "description": "Pending bit 10",
+ "offset": 10,
+ "size": 1
+ },
+ "PR11": {
+ "description": "Pending bit 11",
+ "offset": 11,
+ "size": 1
+ },
+ "PR12": {
+ "description": "Pending bit 12",
+ "offset": 12,
+ "size": 1
+ },
+ "PR13": {
+ "description": "Pending bit 13",
+ "offset": 13,
+ "size": 1
+ },
+ "PR14": {
+ "description": "Pending bit 14",
+ "offset": 14,
+ "size": 1
+ },
+ "PR15": {
+ "description": "Pending bit 15",
+ "offset": 15,
+ "size": 1
+ },
+ "PR16": {
+ "description": "Pending bit 16",
+ "offset": 16,
+ "size": 1
+ },
+ "PR17": {
+ "description": "Pending bit 17",
+ "offset": 17,
+ "size": 1
+ },
+ "PR18": {
+ "description": "Pending bit 18",
+ "offset": 18,
+ "size": 1
+ },
+ "PR19": {
+ "description": "Pending bit 19",
+ "offset": 19,
+ "size": 1
+ },
+ "PR20": {
+ "description": "Pending bit 20",
+ "offset": 20,
+ "size": 1
+ },
+ "PR21": {
+ "description": "Pending bit 21",
+ "offset": 21,
+ "size": 1
+ },
+ "PR22": {
+ "description": "Pending bit 22",
+ "offset": 22,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "FLASH": {
+ "description": "FLASH",
+ "children": {
+ "registers": {
+ "ACR": {
+ "description": "Flash access control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LATENCY": {
+ "description": "Latency",
+ "offset": 0,
+ "size": 3
+ },
+ "PRFTEN": {
+ "description": "Prefetch enable",
+ "offset": 8,
+ "size": 1
+ },
+ "ICEN": {
+ "description": "Instruction cache enable",
+ "offset": 9,
+ "size": 1
+ },
+ "DCEN": {
+ "description": "Data cache enable",
+ "offset": 10,
+ "size": 1
+ },
+ "ICRST": {
+ "description": "Instruction cache reset",
+ "offset": 11,
+ "size": 1,
+ "access": "write-only"
+ },
+ "DCRST": {
+ "description": "Data cache reset",
+ "offset": 12,
+ "size": 1
+ }
+ }
+ }
+ },
+ "KEYR": {
+ "description": "Flash key register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "KEY": {
+ "description": "FPEC key",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OPTKEYR": {
+ "description": "Flash option key register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "OPTKEY": {
+ "description": "Option byte key",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "Status register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EOP": {
+ "description": "End of operation",
+ "offset": 0,
+ "size": 1
+ },
+ "OPERR": {
+ "description": "Operation error",
+ "offset": 1,
+ "size": 1
+ },
+ "WRPERR": {
+ "description": "Write protection error",
+ "offset": 4,
+ "size": 1
+ },
+ "PGAERR": {
+ "description": "Programming alignment\n error",
+ "offset": 5,
+ "size": 1
+ },
+ "PGPERR": {
+ "description": "Programming parallelism\n error",
+ "offset": 6,
+ "size": 1
+ },
+ "PGSERR": {
+ "description": "Programming sequence error",
+ "offset": 7,
+ "size": 1
+ },
+ "BSY": {
+ "description": "Busy",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "CR": {
+ "description": "Control register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 2147483648,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PG": {
+ "description": "Programming",
+ "offset": 0,
+ "size": 1
+ },
+ "SER": {
+ "description": "Sector Erase",
+ "offset": 1,
+ "size": 1
+ },
+ "MER": {
+ "description": "Mass Erase",
+ "offset": 2,
+ "size": 1
+ },
+ "SNB": {
+ "description": "Sector number",
+ "offset": 3,
+ "size": 4
+ },
+ "PSIZE": {
+ "description": "Program size",
+ "offset": 8,
+ "size": 2
+ },
+ "STRT": {
+ "description": "Start",
+ "offset": 16,
+ "size": 1
+ },
+ "EOPIE": {
+ "description": "End of operation interrupt\n enable",
+ "offset": 24,
+ "size": 1
+ },
+ "ERRIE": {
+ "description": "Error interrupt enable",
+ "offset": 25,
+ "size": 1
+ },
+ "LOCK": {
+ "description": "Lock",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OPTCR": {
+ "description": "Flash option control register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 20,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OPTLOCK": {
+ "description": "Option lock",
+ "offset": 0,
+ "size": 1
+ },
+ "OPTSTRT": {
+ "description": "Option start",
+ "offset": 1,
+ "size": 1
+ },
+ "BOR_LEV": {
+ "description": "BOR reset Level",
+ "offset": 2,
+ "size": 2
+ },
+ "WDG_SW": {
+ "description": "WDG_SW User option bytes",
+ "offset": 5,
+ "size": 1
+ },
+ "nRST_STOP": {
+ "description": "nRST_STOP User option\n bytes",
+ "offset": 6,
+ "size": 1
+ },
+ "nRST_STDBY": {
+ "description": "nRST_STDBY User option\n bytes",
+ "offset": 7,
+ "size": 1
+ },
+ "RDP": {
+ "description": "Read protect",
+ "offset": 8,
+ "size": 8
+ },
+ "nWRP": {
+ "description": "Not write protect",
+ "offset": 16,
+ "size": 12
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "USART6": {
+ "description": "Universal synchronous asynchronous receiver\n transmitter",
+ "children": {
+ "registers": {
+ "SR": {
+ "description": "Status register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 12582912,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CTS": {
+ "description": "CTS flag",
+ "offset": 9,
+ "size": 1
+ },
+ "LBD": {
+ "description": "LIN break detection flag",
+ "offset": 8,
+ "size": 1
+ },
+ "TXE": {
+ "description": "Transmit data register\n empty",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TC": {
+ "description": "Transmission complete",
+ "offset": 6,
+ "size": 1
+ },
+ "RXNE": {
+ "description": "Read data register not\n empty",
+ "offset": 5,
+ "size": 1
+ },
+ "IDLE": {
+ "description": "IDLE line detected",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ORE": {
+ "description": "Overrun error",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NF": {
+ "description": "Noise detected flag",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "FE": {
+ "description": "Framing error",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PE": {
+ "description": "Parity error",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "DR": {
+ "description": "Data register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DR": {
+ "description": "Data value",
+ "offset": 0,
+ "size": 9
+ }
+ }
+ }
+ },
+ "BRR": {
+ "description": "Baud rate register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DIV_Mantissa": {
+ "description": "mantissa of USARTDIV",
+ "offset": 4,
+ "size": 12
+ },
+ "DIV_Fraction": {
+ "description": "fraction of USARTDIV",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "CR1": {
+ "description": "Control register 1",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OVER8": {
+ "description": "Oversampling mode",
+ "offset": 15,
+ "size": 1
+ },
+ "UE": {
+ "description": "USART enable",
+ "offset": 13,
+ "size": 1
+ },
+ "M": {
+ "description": "Word length",
+ "offset": 12,
+ "size": 1
+ },
+ "WAKE": {
+ "description": "Wakeup method",
+ "offset": 11,
+ "size": 1
+ },
+ "PCE": {
+ "description": "Parity control enable",
+ "offset": 10,
+ "size": 1
+ },
+ "PS": {
+ "description": "Parity selection",
+ "offset": 9,
+ "size": 1
+ },
+ "PEIE": {
+ "description": "PE interrupt enable",
+ "offset": 8,
+ "size": 1
+ },
+ "TXEIE": {
+ "description": "TXE interrupt enable",
+ "offset": 7,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transmission complete interrupt\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "RXNEIE": {
+ "description": "RXNE interrupt enable",
+ "offset": 5,
+ "size": 1
+ },
+ "IDLEIE": {
+ "description": "IDLE interrupt enable",
+ "offset": 4,
+ "size": 1
+ },
+ "TE": {
+ "description": "Transmitter enable",
+ "offset": 3,
+ "size": 1
+ },
+ "RE": {
+ "description": "Receiver enable",
+ "offset": 2,
+ "size": 1
+ },
+ "RWU": {
+ "description": "Receiver wakeup",
+ "offset": 1,
+ "size": 1
+ },
+ "SBK": {
+ "description": "Send break",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "Control register 2",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LINEN": {
+ "description": "LIN mode enable",
+ "offset": 14,
+ "size": 1
+ },
+ "STOP": {
+ "description": "STOP bits",
+ "offset": 12,
+ "size": 2
+ },
+ "CLKEN": {
+ "description": "Clock enable",
+ "offset": 11,
+ "size": 1
+ },
+ "CPOL": {
+ "description": "Clock polarity",
+ "offset": 10,
+ "size": 1
+ },
+ "CPHA": {
+ "description": "Clock phase",
+ "offset": 9,
+ "size": 1
+ },
+ "LBCL": {
+ "description": "Last bit clock pulse",
+ "offset": 8,
+ "size": 1
+ },
+ "LBDIE": {
+ "description": "LIN break detection interrupt\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "LBDL": {
+ "description": "lin break detection length",
+ "offset": 5,
+ "size": 1
+ },
+ "ADD": {
+ "description": "Address of the USART node",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "CR3": {
+ "description": "Control register 3",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ONEBIT": {
+ "description": "One sample bit method\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "CTSIE": {
+ "description": "CTS interrupt enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CTSE": {
+ "description": "CTS enable",
+ "offset": 9,
+ "size": 1
+ },
+ "RTSE": {
+ "description": "RTS enable",
+ "offset": 8,
+ "size": 1
+ },
+ "DMAT": {
+ "description": "DMA enable transmitter",
+ "offset": 7,
+ "size": 1
+ },
+ "DMAR": {
+ "description": "DMA enable receiver",
+ "offset": 6,
+ "size": 1
+ },
+ "SCEN": {
+ "description": "Smartcard mode enable",
+ "offset": 5,
+ "size": 1
+ },
+ "NACK": {
+ "description": "Smartcard NACK enable",
+ "offset": 4,
+ "size": 1
+ },
+ "HDSEL": {
+ "description": "Half-duplex selection",
+ "offset": 3,
+ "size": 1
+ },
+ "IRLP": {
+ "description": "IrDA low-power",
+ "offset": 2,
+ "size": 1
+ },
+ "IREN": {
+ "description": "IrDA mode enable",
+ "offset": 1,
+ "size": 1
+ },
+ "EIE": {
+ "description": "Error interrupt enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "GTPR": {
+ "description": "Guard time and prescaler\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "GT": {
+ "description": "Guard time value",
+ "offset": 8,
+ "size": 8
+ },
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "TIM6": {
+ "description": "Basic timers",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARPE": {
+ "description": "Auto-reload preload enable",
+ "offset": 7,
+ "size": 1
+ },
+ "OPM": {
+ "description": "One-pulse mode",
+ "offset": 3,
+ "size": 1
+ },
+ "URS": {
+ "description": "Update request source",
+ "offset": 2,
+ "size": 1
+ },
+ "UDIS": {
+ "description": "Update disable",
+ "offset": 1,
+ "size": 1
+ },
+ "CEN": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MMS": {
+ "description": "Master mode selection",
+ "offset": 4,
+ "size": 3
+ }
+ }
+ }
+ },
+ "DIER": {
+ "description": "DMA/Interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "UDE": {
+ "description": "Update DMA request enable",
+ "offset": 8,
+ "size": 1
+ },
+ "UIE": {
+ "description": "Update interrupt enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "UIF": {
+ "description": "Update interrupt flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EGR": {
+ "description": "event generation register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "UG": {
+ "description": "Update generation",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNT": {
+ "description": "counter",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNT": {
+ "description": "Low counter value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "PSC": {
+ "description": "prescaler",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ARR": {
+ "description": "auto-reload register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARR": {
+ "description": "Low Auto-reload value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "CAN1": {
+ "description": "Controller area network",
+ "children": {
+ "registers": {
+ "MCR": {
+ "description": "master control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 65538,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBF": {
+ "description": "DBF",
+ "offset": 16,
+ "size": 1
+ },
+ "RESET": {
+ "description": "RESET",
+ "offset": 15,
+ "size": 1
+ },
+ "TTCM": {
+ "description": "TTCM",
+ "offset": 7,
+ "size": 1
+ },
+ "ABOM": {
+ "description": "ABOM",
+ "offset": 6,
+ "size": 1
+ },
+ "AWUM": {
+ "description": "AWUM",
+ "offset": 5,
+ "size": 1
+ },
+ "NART": {
+ "description": "NART",
+ "offset": 4,
+ "size": 1
+ },
+ "RFLM": {
+ "description": "RFLM",
+ "offset": 3,
+ "size": 1
+ },
+ "TXFP": {
+ "description": "TXFP",
+ "offset": 2,
+ "size": 1
+ },
+ "SLEEP": {
+ "description": "SLEEP",
+ "offset": 1,
+ "size": 1
+ },
+ "INRQ": {
+ "description": "INRQ",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MSR": {
+ "description": "master status register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 3074,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RX": {
+ "description": "RX",
+ "offset": 11,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SAMP": {
+ "description": "SAMP",
+ "offset": 10,
+ "size": 1,
+ "access": "read-only"
+ },
+ "RXM": {
+ "description": "RXM",
+ "offset": 9,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TXM": {
+ "description": "TXM",
+ "offset": 8,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SLAKI": {
+ "description": "SLAKI",
+ "offset": 4,
+ "size": 1
+ },
+ "WKUI": {
+ "description": "WKUI",
+ "offset": 3,
+ "size": 1
+ },
+ "ERRI": {
+ "description": "ERRI",
+ "offset": 2,
+ "size": 1
+ },
+ "SLAK": {
+ "description": "SLAK",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "INAK": {
+ "description": "INAK",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "TSR": {
+ "description": "transmit status register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 469762048,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LOW2": {
+ "description": "Lowest priority flag for mailbox\n 2",
+ "offset": 31,
+ "size": 1,
+ "access": "read-only"
+ },
+ "LOW1": {
+ "description": "Lowest priority flag for mailbox\n 1",
+ "offset": 30,
+ "size": 1,
+ "access": "read-only"
+ },
+ "LOW0": {
+ "description": "Lowest priority flag for mailbox\n 0",
+ "offset": 29,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TME2": {
+ "description": "Lowest priority flag for mailbox\n 2",
+ "offset": 28,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TME1": {
+ "description": "Lowest priority flag for mailbox\n 1",
+ "offset": 27,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TME0": {
+ "description": "Lowest priority flag for mailbox\n 0",
+ "offset": 26,
+ "size": 1,
+ "access": "read-only"
+ },
+ "CODE": {
+ "description": "CODE",
+ "offset": 24,
+ "size": 2,
+ "access": "read-only"
+ },
+ "ABRQ2": {
+ "description": "ABRQ2",
+ "offset": 23,
+ "size": 1
+ },
+ "TERR2": {
+ "description": "TERR2",
+ "offset": 19,
+ "size": 1
+ },
+ "ALST2": {
+ "description": "ALST2",
+ "offset": 18,
+ "size": 1
+ },
+ "TXOK2": {
+ "description": "TXOK2",
+ "offset": 17,
+ "size": 1
+ },
+ "RQCP2": {
+ "description": "RQCP2",
+ "offset": 16,
+ "size": 1
+ },
+ "ABRQ1": {
+ "description": "ABRQ1",
+ "offset": 15,
+ "size": 1
+ },
+ "TERR1": {
+ "description": "TERR1",
+ "offset": 11,
+ "size": 1
+ },
+ "ALST1": {
+ "description": "ALST1",
+ "offset": 10,
+ "size": 1
+ },
+ "TXOK1": {
+ "description": "TXOK1",
+ "offset": 9,
+ "size": 1
+ },
+ "RQCP1": {
+ "description": "RQCP1",
+ "offset": 8,
+ "size": 1
+ },
+ "ABRQ0": {
+ "description": "ABRQ0",
+ "offset": 7,
+ "size": 1
+ },
+ "TERR0": {
+ "description": "TERR0",
+ "offset": 3,
+ "size": 1
+ },
+ "ALST0": {
+ "description": "ALST0",
+ "offset": 2,
+ "size": 1
+ },
+ "TXOK0": {
+ "description": "TXOK0",
+ "offset": 1,
+ "size": 1
+ },
+ "RQCP0": {
+ "description": "RQCP0",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "RF0R": {
+ "description": "receive FIFO 0 register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RFOM0": {
+ "description": "RFOM0",
+ "offset": 5,
+ "size": 1
+ },
+ "FOVR0": {
+ "description": "FOVR0",
+ "offset": 4,
+ "size": 1
+ },
+ "FULL0": {
+ "description": "FULL0",
+ "offset": 3,
+ "size": 1
+ },
+ "FMP0": {
+ "description": "FMP0",
+ "offset": 0,
+ "size": 2,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "RF1R": {
+ "description": "receive FIFO 1 register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RFOM1": {
+ "description": "RFOM1",
+ "offset": 5,
+ "size": 1
+ },
+ "FOVR1": {
+ "description": "FOVR1",
+ "offset": 4,
+ "size": 1
+ },
+ "FULL1": {
+ "description": "FULL1",
+ "offset": 3,
+ "size": 1
+ },
+ "FMP1": {
+ "description": "FMP1",
+ "offset": 0,
+ "size": 2,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "IER": {
+ "description": "interrupt enable register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SLKIE": {
+ "description": "SLKIE",
+ "offset": 17,
+ "size": 1
+ },
+ "WKUIE": {
+ "description": "WKUIE",
+ "offset": 16,
+ "size": 1
+ },
+ "ERRIE": {
+ "description": "ERRIE",
+ "offset": 15,
+ "size": 1
+ },
+ "LECIE": {
+ "description": "LECIE",
+ "offset": 11,
+ "size": 1
+ },
+ "BOFIE": {
+ "description": "BOFIE",
+ "offset": 10,
+ "size": 1
+ },
+ "EPVIE": {
+ "description": "EPVIE",
+ "offset": 9,
+ "size": 1
+ },
+ "EWGIE": {
+ "description": "EWGIE",
+ "offset": 8,
+ "size": 1
+ },
+ "FOVIE1": {
+ "description": "FOVIE1",
+ "offset": 6,
+ "size": 1
+ },
+ "FFIE1": {
+ "description": "FFIE1",
+ "offset": 5,
+ "size": 1
+ },
+ "FMPIE1": {
+ "description": "FMPIE1",
+ "offset": 4,
+ "size": 1
+ },
+ "FOVIE0": {
+ "description": "FOVIE0",
+ "offset": 3,
+ "size": 1
+ },
+ "FFIE0": {
+ "description": "FFIE0",
+ "offset": 2,
+ "size": 1
+ },
+ "FMPIE0": {
+ "description": "FMPIE0",
+ "offset": 1,
+ "size": 1
+ },
+ "TMEIE": {
+ "description": "TMEIE",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ESR": {
+ "description": "interrupt enable register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "REC": {
+ "description": "REC",
+ "offset": 24,
+ "size": 8,
+ "access": "read-only"
+ },
+ "TEC": {
+ "description": "TEC",
+ "offset": 16,
+ "size": 8,
+ "access": "read-only"
+ },
+ "LEC": {
+ "description": "LEC",
+ "offset": 4,
+ "size": 3
+ },
+ "BOFF": {
+ "description": "BOFF",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPVF": {
+ "description": "EPVF",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EWGF": {
+ "description": "EWGF",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "BTR": {
+ "description": "bit timing register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SILM": {
+ "description": "SILM",
+ "offset": 31,
+ "size": 1
+ },
+ "LBKM": {
+ "description": "LBKM",
+ "offset": 30,
+ "size": 1
+ },
+ "SJW": {
+ "description": "SJW",
+ "offset": 24,
+ "size": 2
+ },
+ "TS2": {
+ "description": "TS2",
+ "offset": 20,
+ "size": 3
+ },
+ "TS1": {
+ "description": "TS1",
+ "offset": 16,
+ "size": 4
+ },
+ "BRP": {
+ "description": "BRP",
+ "offset": 0,
+ "size": 10
+ }
+ }
+ }
+ },
+ "TI0R": {
+ "description": "TX mailbox identifier register",
+ "offset": 384,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "STID": {
+ "description": "STID",
+ "offset": 21,
+ "size": 11
+ },
+ "EXID": {
+ "description": "EXID",
+ "offset": 3,
+ "size": 18
+ },
+ "IDE": {
+ "description": "IDE",
+ "offset": 2,
+ "size": 1
+ },
+ "RTR": {
+ "description": "RTR",
+ "offset": 1,
+ "size": 1
+ },
+ "TXRQ": {
+ "description": "TXRQ",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "TDT0R": {
+ "description": "mailbox data length control and time stamp\n register",
+ "offset": 388,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIME": {
+ "description": "TIME",
+ "offset": 16,
+ "size": 16
+ },
+ "TGT": {
+ "description": "TGT",
+ "offset": 8,
+ "size": 1
+ },
+ "DLC": {
+ "description": "DLC",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "TDL0R": {
+ "description": "mailbox data low register",
+ "offset": 392,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATA3": {
+ "description": "DATA3",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA2": {
+ "description": "DATA2",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA1": {
+ "description": "DATA1",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA0": {
+ "description": "DATA0",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "TDH0R": {
+ "description": "mailbox data high register",
+ "offset": 396,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATA7": {
+ "description": "DATA7",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA6": {
+ "description": "DATA6",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA5": {
+ "description": "DATA5",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA4": {
+ "description": "DATA4",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "TI1R": {
+ "description": "mailbox identifier register",
+ "offset": 400,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "STID": {
+ "description": "STID",
+ "offset": 21,
+ "size": 11
+ },
+ "EXID": {
+ "description": "EXID",
+ "offset": 3,
+ "size": 18
+ },
+ "IDE": {
+ "description": "IDE",
+ "offset": 2,
+ "size": 1
+ },
+ "RTR": {
+ "description": "RTR",
+ "offset": 1,
+ "size": 1
+ },
+ "TXRQ": {
+ "description": "TXRQ",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "TDT1R": {
+ "description": "mailbox data length control and time stamp\n register",
+ "offset": 404,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIME": {
+ "description": "TIME",
+ "offset": 16,
+ "size": 16
+ },
+ "TGT": {
+ "description": "TGT",
+ "offset": 8,
+ "size": 1
+ },
+ "DLC": {
+ "description": "DLC",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "TDL1R": {
+ "description": "mailbox data low register",
+ "offset": 408,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATA3": {
+ "description": "DATA3",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA2": {
+ "description": "DATA2",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA1": {
+ "description": "DATA1",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA0": {
+ "description": "DATA0",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "TDH1R": {
+ "description": "mailbox data high register",
+ "offset": 412,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATA7": {
+ "description": "DATA7",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA6": {
+ "description": "DATA6",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA5": {
+ "description": "DATA5",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA4": {
+ "description": "DATA4",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "TI2R": {
+ "description": "mailbox identifier register",
+ "offset": 416,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "STID": {
+ "description": "STID",
+ "offset": 21,
+ "size": 11
+ },
+ "EXID": {
+ "description": "EXID",
+ "offset": 3,
+ "size": 18
+ },
+ "IDE": {
+ "description": "IDE",
+ "offset": 2,
+ "size": 1
+ },
+ "RTR": {
+ "description": "RTR",
+ "offset": 1,
+ "size": 1
+ },
+ "TXRQ": {
+ "description": "TXRQ",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "TDT2R": {
+ "description": "mailbox data length control and time stamp\n register",
+ "offset": 420,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIME": {
+ "description": "TIME",
+ "offset": 16,
+ "size": 16
+ },
+ "TGT": {
+ "description": "TGT",
+ "offset": 8,
+ "size": 1
+ },
+ "DLC": {
+ "description": "DLC",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "TDL2R": {
+ "description": "mailbox data low register",
+ "offset": 424,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATA3": {
+ "description": "DATA3",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA2": {
+ "description": "DATA2",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA1": {
+ "description": "DATA1",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA0": {
+ "description": "DATA0",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "TDH2R": {
+ "description": "mailbox data high register",
+ "offset": 428,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATA7": {
+ "description": "DATA7",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA6": {
+ "description": "DATA6",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA5": {
+ "description": "DATA5",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA4": {
+ "description": "DATA4",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "RI0R": {
+ "description": "receive FIFO mailbox identifier\n register",
+ "offset": 432,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "STID": {
+ "description": "STID",
+ "offset": 21,
+ "size": 11
+ },
+ "EXID": {
+ "description": "EXID",
+ "offset": 3,
+ "size": 18
+ },
+ "IDE": {
+ "description": "IDE",
+ "offset": 2,
+ "size": 1
+ },
+ "RTR": {
+ "description": "RTR",
+ "offset": 1,
+ "size": 1
+ }
+ }
+ }
+ },
+ "RDT0R": {
+ "description": "mailbox data high register",
+ "offset": 436,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "TIME": {
+ "description": "TIME",
+ "offset": 16,
+ "size": 16
+ },
+ "FMI": {
+ "description": "FMI",
+ "offset": 8,
+ "size": 8
+ },
+ "DLC": {
+ "description": "DLC",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "RDL0R": {
+ "description": "mailbox data high register",
+ "offset": 440,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DATA3": {
+ "description": "DATA3",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA2": {
+ "description": "DATA2",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA1": {
+ "description": "DATA1",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA0": {
+ "description": "DATA0",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "RDH0R": {
+ "description": "receive FIFO mailbox data high\n register",
+ "offset": 444,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DATA7": {
+ "description": "DATA7",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA6": {
+ "description": "DATA6",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA5": {
+ "description": "DATA5",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA4": {
+ "description": "DATA4",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "RI1R": {
+ "description": "mailbox data high register",
+ "offset": 448,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "STID": {
+ "description": "STID",
+ "offset": 21,
+ "size": 11
+ },
+ "EXID": {
+ "description": "EXID",
+ "offset": 3,
+ "size": 18
+ },
+ "IDE": {
+ "description": "IDE",
+ "offset": 2,
+ "size": 1
+ },
+ "RTR": {
+ "description": "RTR",
+ "offset": 1,
+ "size": 1
+ }
+ }
+ }
+ },
+ "RDT1R": {
+ "description": "mailbox data high register",
+ "offset": 452,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "TIME": {
+ "description": "TIME",
+ "offset": 16,
+ "size": 16
+ },
+ "FMI": {
+ "description": "FMI",
+ "offset": 8,
+ "size": 8
+ },
+ "DLC": {
+ "description": "DLC",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "RDL1R": {
+ "description": "mailbox data high register",
+ "offset": 456,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DATA3": {
+ "description": "DATA3",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA2": {
+ "description": "DATA2",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA1": {
+ "description": "DATA1",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA0": {
+ "description": "DATA0",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "RDH1R": {
+ "description": "mailbox data high register",
+ "offset": 460,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DATA7": {
+ "description": "DATA7",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA6": {
+ "description": "DATA6",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA5": {
+ "description": "DATA5",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA4": {
+ "description": "DATA4",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "FMR": {
+ "description": "filter master register",
+ "offset": 512,
+ "size": 32,
+ "reset_value": 706481665,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CAN2SB": {
+ "description": "CAN2SB",
+ "offset": 8,
+ "size": 6
+ },
+ "FINIT": {
+ "description": "FINIT",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FM1R": {
+ "description": "filter mode register",
+ "offset": 516,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FBM0": {
+ "description": "Filter mode",
+ "offset": 0,
+ "size": 1
+ },
+ "FBM1": {
+ "description": "Filter mode",
+ "offset": 1,
+ "size": 1
+ },
+ "FBM2": {
+ "description": "Filter mode",
+ "offset": 2,
+ "size": 1
+ },
+ "FBM3": {
+ "description": "Filter mode",
+ "offset": 3,
+ "size": 1
+ },
+ "FBM4": {
+ "description": "Filter mode",
+ "offset": 4,
+ "size": 1
+ },
+ "FBM5": {
+ "description": "Filter mode",
+ "offset": 5,
+ "size": 1
+ },
+ "FBM6": {
+ "description": "Filter mode",
+ "offset": 6,
+ "size": 1
+ },
+ "FBM7": {
+ "description": "Filter mode",
+ "offset": 7,
+ "size": 1
+ },
+ "FBM8": {
+ "description": "Filter mode",
+ "offset": 8,
+ "size": 1
+ },
+ "FBM9": {
+ "description": "Filter mode",
+ "offset": 9,
+ "size": 1
+ },
+ "FBM10": {
+ "description": "Filter mode",
+ "offset": 10,
+ "size": 1
+ },
+ "FBM11": {
+ "description": "Filter mode",
+ "offset": 11,
+ "size": 1
+ },
+ "FBM12": {
+ "description": "Filter mode",
+ "offset": 12,
+ "size": 1
+ },
+ "FBM13": {
+ "description": "Filter mode",
+ "offset": 13,
+ "size": 1
+ },
+ "FBM14": {
+ "description": "Filter mode",
+ "offset": 14,
+ "size": 1
+ },
+ "FBM15": {
+ "description": "Filter mode",
+ "offset": 15,
+ "size": 1
+ },
+ "FBM16": {
+ "description": "Filter mode",
+ "offset": 16,
+ "size": 1
+ },
+ "FBM17": {
+ "description": "Filter mode",
+ "offset": 17,
+ "size": 1
+ },
+ "FBM18": {
+ "description": "Filter mode",
+ "offset": 18,
+ "size": 1
+ },
+ "FBM19": {
+ "description": "Filter mode",
+ "offset": 19,
+ "size": 1
+ },
+ "FBM20": {
+ "description": "Filter mode",
+ "offset": 20,
+ "size": 1
+ },
+ "FBM21": {
+ "description": "Filter mode",
+ "offset": 21,
+ "size": 1
+ },
+ "FBM22": {
+ "description": "Filter mode",
+ "offset": 22,
+ "size": 1
+ },
+ "FBM23": {
+ "description": "Filter mode",
+ "offset": 23,
+ "size": 1
+ },
+ "FBM24": {
+ "description": "Filter mode",
+ "offset": 24,
+ "size": 1
+ },
+ "FBM25": {
+ "description": "Filter mode",
+ "offset": 25,
+ "size": 1
+ },
+ "FBM26": {
+ "description": "Filter mode",
+ "offset": 26,
+ "size": 1
+ },
+ "FBM27": {
+ "description": "Filter mode",
+ "offset": 27,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS1R": {
+ "description": "filter scale register",
+ "offset": 524,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FSC0": {
+ "description": "Filter scale configuration",
+ "offset": 0,
+ "size": 1
+ },
+ "FSC1": {
+ "description": "Filter scale configuration",
+ "offset": 1,
+ "size": 1
+ },
+ "FSC2": {
+ "description": "Filter scale configuration",
+ "offset": 2,
+ "size": 1
+ },
+ "FSC3": {
+ "description": "Filter scale configuration",
+ "offset": 3,
+ "size": 1
+ },
+ "FSC4": {
+ "description": "Filter scale configuration",
+ "offset": 4,
+ "size": 1
+ },
+ "FSC5": {
+ "description": "Filter scale configuration",
+ "offset": 5,
+ "size": 1
+ },
+ "FSC6": {
+ "description": "Filter scale configuration",
+ "offset": 6,
+ "size": 1
+ },
+ "FSC7": {
+ "description": "Filter scale configuration",
+ "offset": 7,
+ "size": 1
+ },
+ "FSC8": {
+ "description": "Filter scale configuration",
+ "offset": 8,
+ "size": 1
+ },
+ "FSC9": {
+ "description": "Filter scale configuration",
+ "offset": 9,
+ "size": 1
+ },
+ "FSC10": {
+ "description": "Filter scale configuration",
+ "offset": 10,
+ "size": 1
+ },
+ "FSC11": {
+ "description": "Filter scale configuration",
+ "offset": 11,
+ "size": 1
+ },
+ "FSC12": {
+ "description": "Filter scale configuration",
+ "offset": 12,
+ "size": 1
+ },
+ "FSC13": {
+ "description": "Filter scale configuration",
+ "offset": 13,
+ "size": 1
+ },
+ "FSC14": {
+ "description": "Filter scale configuration",
+ "offset": 14,
+ "size": 1
+ },
+ "FSC15": {
+ "description": "Filter scale configuration",
+ "offset": 15,
+ "size": 1
+ },
+ "FSC16": {
+ "description": "Filter scale configuration",
+ "offset": 16,
+ "size": 1
+ },
+ "FSC17": {
+ "description": "Filter scale configuration",
+ "offset": 17,
+ "size": 1
+ },
+ "FSC18": {
+ "description": "Filter scale configuration",
+ "offset": 18,
+ "size": 1
+ },
+ "FSC19": {
+ "description": "Filter scale configuration",
+ "offset": 19,
+ "size": 1
+ },
+ "FSC20": {
+ "description": "Filter scale configuration",
+ "offset": 20,
+ "size": 1
+ },
+ "FSC21": {
+ "description": "Filter scale configuration",
+ "offset": 21,
+ "size": 1
+ },
+ "FSC22": {
+ "description": "Filter scale configuration",
+ "offset": 22,
+ "size": 1
+ },
+ "FSC23": {
+ "description": "Filter scale configuration",
+ "offset": 23,
+ "size": 1
+ },
+ "FSC24": {
+ "description": "Filter scale configuration",
+ "offset": 24,
+ "size": 1
+ },
+ "FSC25": {
+ "description": "Filter scale configuration",
+ "offset": 25,
+ "size": 1
+ },
+ "FSC26": {
+ "description": "Filter scale configuration",
+ "offset": 26,
+ "size": 1
+ },
+ "FSC27": {
+ "description": "Filter scale configuration",
+ "offset": 27,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FFA1R": {
+ "description": "filter FIFO assignment\n register",
+ "offset": 532,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FFA0": {
+ "description": "Filter FIFO assignment for filter\n 0",
+ "offset": 0,
+ "size": 1
+ },
+ "FFA1": {
+ "description": "Filter FIFO assignment for filter\n 1",
+ "offset": 1,
+ "size": 1
+ },
+ "FFA2": {
+ "description": "Filter FIFO assignment for filter\n 2",
+ "offset": 2,
+ "size": 1
+ },
+ "FFA3": {
+ "description": "Filter FIFO assignment for filter\n 3",
+ "offset": 3,
+ "size": 1
+ },
+ "FFA4": {
+ "description": "Filter FIFO assignment for filter\n 4",
+ "offset": 4,
+ "size": 1
+ },
+ "FFA5": {
+ "description": "Filter FIFO assignment for filter\n 5",
+ "offset": 5,
+ "size": 1
+ },
+ "FFA6": {
+ "description": "Filter FIFO assignment for filter\n 6",
+ "offset": 6,
+ "size": 1
+ },
+ "FFA7": {
+ "description": "Filter FIFO assignment for filter\n 7",
+ "offset": 7,
+ "size": 1
+ },
+ "FFA8": {
+ "description": "Filter FIFO assignment for filter\n 8",
+ "offset": 8,
+ "size": 1
+ },
+ "FFA9": {
+ "description": "Filter FIFO assignment for filter\n 9",
+ "offset": 9,
+ "size": 1
+ },
+ "FFA10": {
+ "description": "Filter FIFO assignment for filter\n 10",
+ "offset": 10,
+ "size": 1
+ },
+ "FFA11": {
+ "description": "Filter FIFO assignment for filter\n 11",
+ "offset": 11,
+ "size": 1
+ },
+ "FFA12": {
+ "description": "Filter FIFO assignment for filter\n 12",
+ "offset": 12,
+ "size": 1
+ },
+ "FFA13": {
+ "description": "Filter FIFO assignment for filter\n 13",
+ "offset": 13,
+ "size": 1
+ },
+ "FFA14": {
+ "description": "Filter FIFO assignment for filter\n 14",
+ "offset": 14,
+ "size": 1
+ },
+ "FFA15": {
+ "description": "Filter FIFO assignment for filter\n 15",
+ "offset": 15,
+ "size": 1
+ },
+ "FFA16": {
+ "description": "Filter FIFO assignment for filter\n 16",
+ "offset": 16,
+ "size": 1
+ },
+ "FFA17": {
+ "description": "Filter FIFO assignment for filter\n 17",
+ "offset": 17,
+ "size": 1
+ },
+ "FFA18": {
+ "description": "Filter FIFO assignment for filter\n 18",
+ "offset": 18,
+ "size": 1
+ },
+ "FFA19": {
+ "description": "Filter FIFO assignment for filter\n 19",
+ "offset": 19,
+ "size": 1
+ },
+ "FFA20": {
+ "description": "Filter FIFO assignment for filter\n 20",
+ "offset": 20,
+ "size": 1
+ },
+ "FFA21": {
+ "description": "Filter FIFO assignment for filter\n 21",
+ "offset": 21,
+ "size": 1
+ },
+ "FFA22": {
+ "description": "Filter FIFO assignment for filter\n 22",
+ "offset": 22,
+ "size": 1
+ },
+ "FFA23": {
+ "description": "Filter FIFO assignment for filter\n 23",
+ "offset": 23,
+ "size": 1
+ },
+ "FFA24": {
+ "description": "Filter FIFO assignment for filter\n 24",
+ "offset": 24,
+ "size": 1
+ },
+ "FFA25": {
+ "description": "Filter FIFO assignment for filter\n 25",
+ "offset": 25,
+ "size": 1
+ },
+ "FFA26": {
+ "description": "Filter FIFO assignment for filter\n 26",
+ "offset": 26,
+ "size": 1
+ },
+ "FFA27": {
+ "description": "Filter FIFO assignment for filter\n 27",
+ "offset": 27,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FA1R": {
+ "description": "filter activation register",
+ "offset": 540,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FACT0": {
+ "description": "Filter active",
+ "offset": 0,
+ "size": 1
+ },
+ "FACT1": {
+ "description": "Filter active",
+ "offset": 1,
+ "size": 1
+ },
+ "FACT2": {
+ "description": "Filter active",
+ "offset": 2,
+ "size": 1
+ },
+ "FACT3": {
+ "description": "Filter active",
+ "offset": 3,
+ "size": 1
+ },
+ "FACT4": {
+ "description": "Filter active",
+ "offset": 4,
+ "size": 1
+ },
+ "FACT5": {
+ "description": "Filter active",
+ "offset": 5,
+ "size": 1
+ },
+ "FACT6": {
+ "description": "Filter active",
+ "offset": 6,
+ "size": 1
+ },
+ "FACT7": {
+ "description": "Filter active",
+ "offset": 7,
+ "size": 1
+ },
+ "FACT8": {
+ "description": "Filter active",
+ "offset": 8,
+ "size": 1
+ },
+ "FACT9": {
+ "description": "Filter active",
+ "offset": 9,
+ "size": 1
+ },
+ "FACT10": {
+ "description": "Filter active",
+ "offset": 10,
+ "size": 1
+ },
+ "FACT11": {
+ "description": "Filter active",
+ "offset": 11,
+ "size": 1
+ },
+ "FACT12": {
+ "description": "Filter active",
+ "offset": 12,
+ "size": 1
+ },
+ "FACT13": {
+ "description": "Filter active",
+ "offset": 13,
+ "size": 1
+ },
+ "FACT14": {
+ "description": "Filter active",
+ "offset": 14,
+ "size": 1
+ },
+ "FACT15": {
+ "description": "Filter active",
+ "offset": 15,
+ "size": 1
+ },
+ "FACT16": {
+ "description": "Filter active",
+ "offset": 16,
+ "size": 1
+ },
+ "FACT17": {
+ "description": "Filter active",
+ "offset": 17,
+ "size": 1
+ },
+ "FACT18": {
+ "description": "Filter active",
+ "offset": 18,
+ "size": 1
+ },
+ "FACT19": {
+ "description": "Filter active",
+ "offset": 19,
+ "size": 1
+ },
+ "FACT20": {
+ "description": "Filter active",
+ "offset": 20,
+ "size": 1
+ },
+ "FACT21": {
+ "description": "Filter active",
+ "offset": 21,
+ "size": 1
+ },
+ "FACT22": {
+ "description": "Filter active",
+ "offset": 22,
+ "size": 1
+ },
+ "FACT23": {
+ "description": "Filter active",
+ "offset": 23,
+ "size": 1
+ },
+ "FACT24": {
+ "description": "Filter active",
+ "offset": 24,
+ "size": 1
+ },
+ "FACT25": {
+ "description": "Filter active",
+ "offset": 25,
+ "size": 1
+ },
+ "FACT26": {
+ "description": "Filter active",
+ "offset": 26,
+ "size": 1
+ },
+ "FACT27": {
+ "description": "Filter active",
+ "offset": 27,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F0R1": {
+ "description": "Filter bank 0 register 1",
+ "offset": 576,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F0R2": {
+ "description": "Filter bank 0 register 2",
+ "offset": 580,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F1R1": {
+ "description": "Filter bank 1 register 1",
+ "offset": 584,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F1R2": {
+ "description": "Filter bank 1 register 2",
+ "offset": 588,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F2R1": {
+ "description": "Filter bank 2 register 1",
+ "offset": 592,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F2R2": {
+ "description": "Filter bank 2 register 2",
+ "offset": 596,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F3R1": {
+ "description": "Filter bank 3 register 1",
+ "offset": 600,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F3R2": {
+ "description": "Filter bank 3 register 2",
+ "offset": 604,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F4R1": {
+ "description": "Filter bank 4 register 1",
+ "offset": 608,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F4R2": {
+ "description": "Filter bank 4 register 2",
+ "offset": 612,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F5R1": {
+ "description": "Filter bank 5 register 1",
+ "offset": 616,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F5R2": {
+ "description": "Filter bank 5 register 2",
+ "offset": 620,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F6R1": {
+ "description": "Filter bank 6 register 1",
+ "offset": 624,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F6R2": {
+ "description": "Filter bank 6 register 2",
+ "offset": 628,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F7R1": {
+ "description": "Filter bank 7 register 1",
+ "offset": 632,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F7R2": {
+ "description": "Filter bank 7 register 2",
+ "offset": 636,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F8R1": {
+ "description": "Filter bank 8 register 1",
+ "offset": 640,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F8R2": {
+ "description": "Filter bank 8 register 2",
+ "offset": 644,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F9R1": {
+ "description": "Filter bank 9 register 1",
+ "offset": 648,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F9R2": {
+ "description": "Filter bank 9 register 2",
+ "offset": 652,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F10R1": {
+ "description": "Filter bank 10 register 1",
+ "offset": 656,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F10R2": {
+ "description": "Filter bank 10 register 2",
+ "offset": 660,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F11R1": {
+ "description": "Filter bank 11 register 1",
+ "offset": 664,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F11R2": {
+ "description": "Filter bank 11 register 2",
+ "offset": 668,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F12R1": {
+ "description": "Filter bank 4 register 1",
+ "offset": 672,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F12R2": {
+ "description": "Filter bank 12 register 2",
+ "offset": 676,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F13R1": {
+ "description": "Filter bank 13 register 1",
+ "offset": 680,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F13R2": {
+ "description": "Filter bank 13 register 2",
+ "offset": 684,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F14R1": {
+ "description": "Filter bank 14 register 1",
+ "offset": 688,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F14R2": {
+ "description": "Filter bank 14 register 2",
+ "offset": 692,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F15R1": {
+ "description": "Filter bank 15 register 1",
+ "offset": 696,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F15R2": {
+ "description": "Filter bank 15 register 2",
+ "offset": 700,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F16R1": {
+ "description": "Filter bank 16 register 1",
+ "offset": 704,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F16R2": {
+ "description": "Filter bank 16 register 2",
+ "offset": 708,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F17R1": {
+ "description": "Filter bank 17 register 1",
+ "offset": 712,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F17R2": {
+ "description": "Filter bank 17 register 2",
+ "offset": 716,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F18R1": {
+ "description": "Filter bank 18 register 1",
+ "offset": 720,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F18R2": {
+ "description": "Filter bank 18 register 2",
+ "offset": 724,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F19R1": {
+ "description": "Filter bank 19 register 1",
+ "offset": 728,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F19R2": {
+ "description": "Filter bank 19 register 2",
+ "offset": 732,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F20R1": {
+ "description": "Filter bank 20 register 1",
+ "offset": 736,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F20R2": {
+ "description": "Filter bank 20 register 2",
+ "offset": 740,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F21R1": {
+ "description": "Filter bank 21 register 1",
+ "offset": 744,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F21R2": {
+ "description": "Filter bank 21 register 2",
+ "offset": 748,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F22R1": {
+ "description": "Filter bank 22 register 1",
+ "offset": 752,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F22R2": {
+ "description": "Filter bank 22 register 2",
+ "offset": 756,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F23R1": {
+ "description": "Filter bank 23 register 1",
+ "offset": 760,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F23R2": {
+ "description": "Filter bank 23 register 2",
+ "offset": 764,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F24R1": {
+ "description": "Filter bank 24 register 1",
+ "offset": 768,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F24R2": {
+ "description": "Filter bank 24 register 2",
+ "offset": 772,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F25R1": {
+ "description": "Filter bank 25 register 1",
+ "offset": 776,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F25R2": {
+ "description": "Filter bank 25 register 2",
+ "offset": 780,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F26R1": {
+ "description": "Filter bank 26 register 1",
+ "offset": 784,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F26R2": {
+ "description": "Filter bank 26 register 2",
+ "offset": 788,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F27R1": {
+ "description": "Filter bank 27 register 1",
+ "offset": 792,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F27R2": {
+ "description": "Filter bank 27 register 2",
+ "offset": 796,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "OTG_FS_PWRCLK": {
+ "description": "USB on the go full speed",
+ "children": {
+ "registers": {
+ "FS_PCGCCTL": {
+ "description": "OTG_FS power and clock gating control\n register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "STPPCLK": {
+ "description": "Stop PHY clock",
+ "offset": 0,
+ "size": 1
+ },
+ "GATEHCLK": {
+ "description": "Gate HCLK",
+ "offset": 1,
+ "size": 1
+ },
+ "PHYSUSP": {
+ "description": "PHY Suspended",
+ "offset": 4,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "DAC": {
+ "description": "Digital-to-analog converter",
+ "children": {
+ "registers": {
+ "CR": {
+ "description": "control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAUDRIE2": {
+ "description": "DAC channel2 DMA underrun interrupt\n enable",
+ "offset": 29,
+ "size": 1
+ },
+ "DMAEN2": {
+ "description": "DAC channel2 DMA enable",
+ "offset": 28,
+ "size": 1
+ },
+ "MAMP2": {
+ "description": "DAC channel2 mask/amplitude\n selector",
+ "offset": 24,
+ "size": 4
+ },
+ "WAVE2": {
+ "description": "DAC channel2 noise/triangle wave\n generation enable",
+ "offset": 22,
+ "size": 2
+ },
+ "TSEL2": {
+ "description": "DAC channel2 trigger\n selection",
+ "offset": 19,
+ "size": 3
+ },
+ "TEN2": {
+ "description": "DAC channel2 trigger\n enable",
+ "offset": 18,
+ "size": 1
+ },
+ "BOFF2": {
+ "description": "DAC channel2 output buffer\n disable",
+ "offset": 17,
+ "size": 1
+ },
+ "EN2": {
+ "description": "DAC channel2 enable",
+ "offset": 16,
+ "size": 1
+ },
+ "DMAUDRIE1": {
+ "description": "DAC channel1 DMA Underrun Interrupt\n enable",
+ "offset": 13,
+ "size": 1
+ },
+ "DMAEN1": {
+ "description": "DAC channel1 DMA enable",
+ "offset": 12,
+ "size": 1
+ },
+ "MAMP1": {
+ "description": "DAC channel1 mask/amplitude\n selector",
+ "offset": 8,
+ "size": 4
+ },
+ "WAVE1": {
+ "description": "DAC channel1 noise/triangle wave\n generation enable",
+ "offset": 6,
+ "size": 2
+ },
+ "TSEL1": {
+ "description": "DAC channel1 trigger\n selection",
+ "offset": 3,
+ "size": 3
+ },
+ "TEN1": {
+ "description": "DAC channel1 trigger\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "BOFF1": {
+ "description": "DAC channel1 output buffer\n disable",
+ "offset": 1,
+ "size": 1
+ },
+ "EN1": {
+ "description": "DAC channel1 enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SWTRIGR": {
+ "description": "software trigger register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "SWTRIG2": {
+ "description": "DAC channel2 software\n trigger",
+ "offset": 1,
+ "size": 1
+ },
+ "SWTRIG1": {
+ "description": "DAC channel1 software\n trigger",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DHR12R1": {
+ "description": "channel1 12-bit right-aligned data holding\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC1DHR": {
+ "description": "DAC channel1 12-bit right-aligned\n data",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DHR12L1": {
+ "description": "channel1 12-bit left aligned data holding\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC1DHR": {
+ "description": "DAC channel1 12-bit left-aligned\n data",
+ "offset": 4,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DHR8R1": {
+ "description": "channel1 8-bit right aligned data holding\n register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC1DHR": {
+ "description": "DAC channel1 8-bit right-aligned\n data",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "DHR12R2": {
+ "description": "channel2 12-bit right aligned data holding\n register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC2DHR": {
+ "description": "DAC channel2 12-bit right-aligned\n data",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DHR12L2": {
+ "description": "channel2 12-bit left aligned data holding\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC2DHR": {
+ "description": "DAC channel2 12-bit left-aligned\n data",
+ "offset": 4,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DHR8R2": {
+ "description": "channel2 8-bit right-aligned data holding\n register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC2DHR": {
+ "description": "DAC channel2 8-bit right-aligned\n data",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "DHR12RD": {
+ "description": "Dual DAC 12-bit right-aligned data holding\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC2DHR": {
+ "description": "DAC channel2 12-bit right-aligned\n data",
+ "offset": 16,
+ "size": 12
+ },
+ "DACC1DHR": {
+ "description": "DAC channel1 12-bit right-aligned\n data",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DHR12LD": {
+ "description": "DUAL DAC 12-bit left aligned data holding\n register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC2DHR": {
+ "description": "DAC channel2 12-bit left-aligned\n data",
+ "offset": 20,
+ "size": 12
+ },
+ "DACC1DHR": {
+ "description": "DAC channel1 12-bit left-aligned\n data",
+ "offset": 4,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DHR8RD": {
+ "description": "DUAL DAC 8-bit right aligned data holding\n register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC2DHR": {
+ "description": "DAC channel2 8-bit right-aligned\n data",
+ "offset": 8,
+ "size": 8
+ },
+ "DACC1DHR": {
+ "description": "DAC channel1 8-bit right-aligned\n data",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "DOR1": {
+ "description": "channel1 data output register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DACC1DOR": {
+ "description": "DAC channel1 data output",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DOR2": {
+ "description": "channel2 data output register",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DACC2DOR": {
+ "description": "DAC channel2 data output",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAUDR2": {
+ "description": "DAC channel2 DMA underrun\n flag",
+ "offset": 29,
+ "size": 1
+ },
+ "DMAUDR1": {
+ "description": "DAC channel1 DMA underrun\n flag",
+ "offset": 13,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "PWR": {
+ "description": "Power control",
+ "children": {
+ "registers": {
+ "CR": {
+ "description": "power control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FPDS": {
+ "description": "Flash power down in Stop\n mode",
+ "offset": 9,
+ "size": 1
+ },
+ "DBP": {
+ "description": "Disable backup domain write\n protection",
+ "offset": 8,
+ "size": 1
+ },
+ "PLS": {
+ "description": "PVD level selection",
+ "offset": 5,
+ "size": 3
+ },
+ "PVDE": {
+ "description": "Power voltage detector\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CSBF": {
+ "description": "Clear standby flag",
+ "offset": 3,
+ "size": 1
+ },
+ "CWUF": {
+ "description": "Clear wakeup flag",
+ "offset": 2,
+ "size": 1
+ },
+ "PDDS": {
+ "description": "Power down deepsleep",
+ "offset": 1,
+ "size": 1
+ },
+ "LPDS": {
+ "description": "Low-power deep sleep",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CSR": {
+ "description": "power control/status register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "WUF": {
+ "description": "Wakeup flag",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SBF": {
+ "description": "Standby flag",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PVDO": {
+ "description": "PVD output",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "BRR": {
+ "description": "Backup regulator ready",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EWUP": {
+ "description": "Enable WKUP pin",
+ "offset": 8,
+ "size": 1
+ },
+ "BRE": {
+ "description": "Backup regulator enable",
+ "offset": 9,
+ "size": 1
+ },
+ "VOSRDY": {
+ "description": "Regulator voltage scaling output\n selection ready bit",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "I2C3": {
+ "description": "Inter-integrated circuit",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "Control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SWRST": {
+ "description": "Software reset",
+ "offset": 15,
+ "size": 1
+ },
+ "ALERT": {
+ "description": "SMBus alert",
+ "offset": 13,
+ "size": 1
+ },
+ "PEC": {
+ "description": "Packet error checking",
+ "offset": 12,
+ "size": 1
+ },
+ "POS": {
+ "description": "Acknowledge/PEC Position (for data\n reception)",
+ "offset": 11,
+ "size": 1
+ },
+ "ACK": {
+ "description": "Acknowledge enable",
+ "offset": 10,
+ "size": 1
+ },
+ "STOP": {
+ "description": "Stop generation",
+ "offset": 9,
+ "size": 1
+ },
+ "START": {
+ "description": "Start generation",
+ "offset": 8,
+ "size": 1
+ },
+ "NOSTRETCH": {
+ "description": "Clock stretching disable (Slave\n mode)",
+ "offset": 7,
+ "size": 1
+ },
+ "ENGC": {
+ "description": "General call enable",
+ "offset": 6,
+ "size": 1
+ },
+ "ENPEC": {
+ "description": "PEC enable",
+ "offset": 5,
+ "size": 1
+ },
+ "ENARP": {
+ "description": "ARP enable",
+ "offset": 4,
+ "size": 1
+ },
+ "SMBTYPE": {
+ "description": "SMBus type",
+ "offset": 3,
+ "size": 1
+ },
+ "SMBUS": {
+ "description": "SMBus mode",
+ "offset": 1,
+ "size": 1
+ },
+ "PE": {
+ "description": "Peripheral enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "Control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LAST": {
+ "description": "DMA last transfer",
+ "offset": 12,
+ "size": 1
+ },
+ "DMAEN": {
+ "description": "DMA requests enable",
+ "offset": 11,
+ "size": 1
+ },
+ "ITBUFEN": {
+ "description": "Buffer interrupt enable",
+ "offset": 10,
+ "size": 1
+ },
+ "ITEVTEN": {
+ "description": "Event interrupt enable",
+ "offset": 9,
+ "size": 1
+ },
+ "ITERREN": {
+ "description": "Error interrupt enable",
+ "offset": 8,
+ "size": 1
+ },
+ "FREQ": {
+ "description": "Peripheral clock frequency",
+ "offset": 0,
+ "size": 6
+ }
+ }
+ }
+ },
+ "OAR1": {
+ "description": "Own address register 1",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ADDMODE": {
+ "description": "Addressing mode (slave\n mode)",
+ "offset": 15,
+ "size": 1
+ },
+ "ADD10": {
+ "description": "Interface address",
+ "offset": 8,
+ "size": 2
+ },
+ "ADD7": {
+ "description": "Interface address",
+ "offset": 1,
+ "size": 7
+ },
+ "ADD0": {
+ "description": "Interface address",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OAR2": {
+ "description": "Own address register 2",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ADD2": {
+ "description": "Interface address",
+ "offset": 1,
+ "size": 7
+ },
+ "ENDUAL": {
+ "description": "Dual addressing mode\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DR": {
+ "description": "Data register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DR": {
+ "description": "8-bit data register",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "SR1": {
+ "description": "Status register 1",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SMBALERT": {
+ "description": "SMBus alert",
+ "offset": 15,
+ "size": 1
+ },
+ "TIMEOUT": {
+ "description": "Timeout or Tlow error",
+ "offset": 14,
+ "size": 1
+ },
+ "PECERR": {
+ "description": "PEC Error in reception",
+ "offset": 12,
+ "size": 1
+ },
+ "OVR": {
+ "description": "Overrun/Underrun",
+ "offset": 11,
+ "size": 1
+ },
+ "AF": {
+ "description": "Acknowledge failure",
+ "offset": 10,
+ "size": 1
+ },
+ "ARLO": {
+ "description": "Arbitration lost (master\n mode)",
+ "offset": 9,
+ "size": 1
+ },
+ "BERR": {
+ "description": "Bus error",
+ "offset": 8,
+ "size": 1
+ },
+ "TxE": {
+ "description": "Data register empty\n (transmitters)",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "RxNE": {
+ "description": "Data register not empty\n (receivers)",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "STOPF": {
+ "description": "Stop detection (slave\n mode)",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ADD10": {
+ "description": "10-bit header sent (Master\n mode)",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "BTF": {
+ "description": "Byte transfer finished",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ADDR": {
+ "description": "Address sent (master mode)/matched\n (slave mode)",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SB": {
+ "description": "Start bit (Master mode)",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "SR2": {
+ "description": "Status register 2",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "PEC": {
+ "description": "acket error checking\n register",
+ "offset": 8,
+ "size": 8
+ },
+ "DUALF": {
+ "description": "Dual flag (Slave mode)",
+ "offset": 7,
+ "size": 1
+ },
+ "SMBHOST": {
+ "description": "SMBus host header (Slave\n mode)",
+ "offset": 6,
+ "size": 1
+ },
+ "SMBDEFAULT": {
+ "description": "SMBus device default address (Slave\n mode)",
+ "offset": 5,
+ "size": 1
+ },
+ "GENCALL": {
+ "description": "General call address (Slave\n mode)",
+ "offset": 4,
+ "size": 1
+ },
+ "TRA": {
+ "description": "Transmitter/receiver",
+ "offset": 2,
+ "size": 1
+ },
+ "BUSY": {
+ "description": "Bus busy",
+ "offset": 1,
+ "size": 1
+ },
+ "MSL": {
+ "description": "Master/slave",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCR": {
+ "description": "Clock control register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "F_S": {
+ "description": "I2C master mode selection",
+ "offset": 15,
+ "size": 1
+ },
+ "DUTY": {
+ "description": "Fast mode duty cycle",
+ "offset": 14,
+ "size": 1
+ },
+ "CCR": {
+ "description": "Clock control register in Fast/Standard\n mode (Master mode)",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "TRISE": {
+ "description": "TRISE register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 2,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TRISE": {
+ "description": "Maximum rise time in Fast/Standard mode\n (Master mode)",
+ "offset": 0,
+ "size": 6
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "OTG_FS_DEVICE": {
+ "description": "USB on the go full speed",
+ "children": {
+ "registers": {
+ "FS_DCFG": {
+ "description": "OTG_FS device configuration register\n (OTG_FS_DCFG)",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 35651584,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DSPD": {
+ "description": "Device speed",
+ "offset": 0,
+ "size": 2
+ },
+ "NZLSOHSK": {
+ "description": "Non-zero-length status OUT\n handshake",
+ "offset": 2,
+ "size": 1
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 4,
+ "size": 7
+ },
+ "PFIVL": {
+ "description": "Periodic frame interval",
+ "offset": 11,
+ "size": 2
+ }
+ }
+ }
+ },
+ "FS_DCTL": {
+ "description": "OTG_FS device control register\n (OTG_FS_DCTL)",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RWUSIG": {
+ "description": "Remote wakeup signaling",
+ "offset": 0,
+ "size": 1
+ },
+ "SDIS": {
+ "description": "Soft disconnect",
+ "offset": 1,
+ "size": 1
+ },
+ "GINSTS": {
+ "description": "Global IN NAK status",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "GONSTS": {
+ "description": "Global OUT NAK status",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TCTL": {
+ "description": "Test control",
+ "offset": 4,
+ "size": 3
+ },
+ "SGINAK": {
+ "description": "Set global IN NAK",
+ "offset": 7,
+ "size": 1
+ },
+ "CGINAK": {
+ "description": "Clear global IN NAK",
+ "offset": 8,
+ "size": 1
+ },
+ "SGONAK": {
+ "description": "Set global OUT NAK",
+ "offset": 9,
+ "size": 1
+ },
+ "CGONAK": {
+ "description": "Clear global OUT NAK",
+ "offset": 10,
+ "size": 1
+ },
+ "POPRGDNE": {
+ "description": "Power-on programming done",
+ "offset": 11,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_DSTS": {
+ "description": "OTG_FS device status register\n (OTG_FS_DSTS)",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 16,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "SUSPSTS": {
+ "description": "Suspend status",
+ "offset": 0,
+ "size": 1
+ },
+ "ENUMSPD": {
+ "description": "Enumerated speed",
+ "offset": 1,
+ "size": 2
+ },
+ "EERR": {
+ "description": "Erratic error",
+ "offset": 3,
+ "size": 1
+ },
+ "FNSOF": {
+ "description": "Frame number of the received\n SOF",
+ "offset": 8,
+ "size": 14
+ }
+ }
+ }
+ },
+ "FS_DIEPMSK": {
+ "description": "OTG_FS device IN endpoint common interrupt\n mask register (OTG_FS_DIEPMSK)",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed interrupt\n mask",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDM": {
+ "description": "Endpoint disabled interrupt\n mask",
+ "offset": 1,
+ "size": 1
+ },
+ "TOM": {
+ "description": "Timeout condition mask (Non-isochronous\n endpoints)",
+ "offset": 3,
+ "size": 1
+ },
+ "ITTXFEMSK": {
+ "description": "IN token received when TxFIFO empty\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "INEPNMM": {
+ "description": "IN token received with EP mismatch\n mask",
+ "offset": 5,
+ "size": 1
+ },
+ "INEPNEM": {
+ "description": "IN endpoint NAK effective\n mask",
+ "offset": 6,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_DOEPMSK": {
+ "description": "OTG_FS device OUT endpoint common interrupt\n mask register (OTG_FS_DOEPMSK)",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed interrupt\n mask",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDM": {
+ "description": "Endpoint disabled interrupt\n mask",
+ "offset": 1,
+ "size": 1
+ },
+ "STUPM": {
+ "description": "SETUP phase done mask",
+ "offset": 3,
+ "size": 1
+ },
+ "OTEPDM": {
+ "description": "OUT token received when endpoint\n disabled mask",
+ "offset": 4,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_DAINT": {
+ "description": "OTG_FS device all endpoints interrupt\n register (OTG_FS_DAINT)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "IEPINT": {
+ "description": "IN endpoint interrupt bits",
+ "offset": 0,
+ "size": 16
+ },
+ "OEPINT": {
+ "description": "OUT endpoint interrupt\n bits",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_DAINTMSK": {
+ "description": "OTG_FS all endpoints interrupt mask register\n (OTG_FS_DAINTMSK)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IEPM": {
+ "description": "IN EP interrupt mask bits",
+ "offset": 0,
+ "size": 16
+ },
+ "OEPINT": {
+ "description": "OUT endpoint interrupt\n bits",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DVBUSDIS": {
+ "description": "OTG_FS device VBUS discharge time\n register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 6103,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "VBUSDT": {
+ "description": "Device VBUS discharge time",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DVBUSPULSE": {
+ "description": "OTG_FS device VBUS pulsing time\n register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 1464,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DVBUSP": {
+ "description": "Device VBUS pulsing time",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DIEPEMPMSK": {
+ "description": "OTG_FS device IN endpoint FIFO empty\n interrupt mask register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INEPTXFEM": {
+ "description": "IN EP Tx FIFO empty interrupt mask\n bits",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_DIEPCTL0": {
+ "description": "OTG_FS device control IN endpoint 0 control\n register (OTG_FS_DIEPCTL0)",
+ "offset": 256,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 2
+ },
+ "USBAEP": {
+ "description": "USB active endpoint",
+ "offset": 15,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAK status",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2,
+ "access": "read-only"
+ },
+ "STALL": {
+ "description": "STALL handshake",
+ "offset": 21,
+ "size": 1
+ },
+ "TXFNUM": {
+ "description": "TxFIFO number",
+ "offset": 22,
+ "size": 4
+ },
+ "CNAK": {
+ "description": "Clear NAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "Set NAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "Endpoint disable",
+ "offset": 30,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPENA": {
+ "description": "Endpoint enable",
+ "offset": 31,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "DIEPCTL1": {
+ "description": "OTG device endpoint-1 control\n register",
+ "offset": 288,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EPENA": {
+ "description": "EPENA",
+ "offset": 31,
+ "size": 1
+ },
+ "EPDIS": {
+ "description": "EPDIS",
+ "offset": 30,
+ "size": 1
+ },
+ "SODDFRM_SD1PID": {
+ "description": "SODDFRM/SD1PID",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "SD0PID/SEVNFRM",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "SNAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CNAK": {
+ "description": "CNAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "TXFNUM": {
+ "description": "TXFNUM",
+ "offset": 22,
+ "size": 4
+ },
+ "Stall": {
+ "description": "Stall",
+ "offset": 21,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "EPTYP",
+ "offset": 18,
+ "size": 2
+ },
+ "NAKSTS": {
+ "description": "NAKSTS",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EONUM_DPID": {
+ "description": "EONUM/DPID",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "USBAEP": {
+ "description": "USBAEP",
+ "offset": 15,
+ "size": 1
+ },
+ "MPSIZ": {
+ "description": "MPSIZ",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "DIEPCTL2": {
+ "description": "OTG device endpoint-2 control\n register",
+ "offset": 320,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EPENA": {
+ "description": "EPENA",
+ "offset": 31,
+ "size": 1
+ },
+ "EPDIS": {
+ "description": "EPDIS",
+ "offset": 30,
+ "size": 1
+ },
+ "SODDFRM": {
+ "description": "SODDFRM",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "SD0PID/SEVNFRM",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "SNAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CNAK": {
+ "description": "CNAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "TXFNUM": {
+ "description": "TXFNUM",
+ "offset": 22,
+ "size": 4
+ },
+ "Stall": {
+ "description": "Stall",
+ "offset": 21,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "EPTYP",
+ "offset": 18,
+ "size": 2
+ },
+ "NAKSTS": {
+ "description": "NAKSTS",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EONUM_DPID": {
+ "description": "EONUM/DPID",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "USBAEP": {
+ "description": "USBAEP",
+ "offset": 15,
+ "size": 1
+ },
+ "MPSIZ": {
+ "description": "MPSIZ",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "DIEPCTL3": {
+ "description": "OTG device endpoint-3 control\n register",
+ "offset": 352,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EPENA": {
+ "description": "EPENA",
+ "offset": 31,
+ "size": 1
+ },
+ "EPDIS": {
+ "description": "EPDIS",
+ "offset": 30,
+ "size": 1
+ },
+ "SODDFRM": {
+ "description": "SODDFRM",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "SD0PID/SEVNFRM",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "SNAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CNAK": {
+ "description": "CNAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "TXFNUM": {
+ "description": "TXFNUM",
+ "offset": 22,
+ "size": 4
+ },
+ "Stall": {
+ "description": "Stall",
+ "offset": 21,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "EPTYP",
+ "offset": 18,
+ "size": 2
+ },
+ "NAKSTS": {
+ "description": "NAKSTS",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EONUM_DPID": {
+ "description": "EONUM/DPID",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "USBAEP": {
+ "description": "USBAEP",
+ "offset": 15,
+ "size": 1
+ },
+ "MPSIZ": {
+ "description": "MPSIZ",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "DOEPCTL0": {
+ "description": "device endpoint-0 control\n register",
+ "offset": 768,
+ "size": 32,
+ "reset_value": 32768,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EPENA": {
+ "description": "EPENA",
+ "offset": 31,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "EPDIS",
+ "offset": 30,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SNAK": {
+ "description": "SNAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CNAK": {
+ "description": "CNAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "Stall": {
+ "description": "Stall",
+ "offset": 21,
+ "size": 1
+ },
+ "SNPM": {
+ "description": "SNPM",
+ "offset": 20,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "EPTYP",
+ "offset": 18,
+ "size": 2,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAKSTS",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "USBAEP": {
+ "description": "USBAEP",
+ "offset": 15,
+ "size": 1,
+ "access": "read-only"
+ },
+ "MPSIZ": {
+ "description": "MPSIZ",
+ "offset": 0,
+ "size": 2,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "DOEPCTL1": {
+ "description": "device endpoint-1 control\n register",
+ "offset": 800,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EPENA": {
+ "description": "EPENA",
+ "offset": 31,
+ "size": 1
+ },
+ "EPDIS": {
+ "description": "EPDIS",
+ "offset": 30,
+ "size": 1
+ },
+ "SODDFRM": {
+ "description": "SODDFRM",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "SD0PID/SEVNFRM",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "SNAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CNAK": {
+ "description": "CNAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "Stall": {
+ "description": "Stall",
+ "offset": 21,
+ "size": 1
+ },
+ "SNPM": {
+ "description": "SNPM",
+ "offset": 20,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "EPTYP",
+ "offset": 18,
+ "size": 2
+ },
+ "NAKSTS": {
+ "description": "NAKSTS",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EONUM_DPID": {
+ "description": "EONUM/DPID",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "USBAEP": {
+ "description": "USBAEP",
+ "offset": 15,
+ "size": 1
+ },
+ "MPSIZ": {
+ "description": "MPSIZ",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "DOEPCTL2": {
+ "description": "device endpoint-2 control\n register",
+ "offset": 832,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EPENA": {
+ "description": "EPENA",
+ "offset": 31,
+ "size": 1
+ },
+ "EPDIS": {
+ "description": "EPDIS",
+ "offset": 30,
+ "size": 1
+ },
+ "SODDFRM": {
+ "description": "SODDFRM",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "SD0PID/SEVNFRM",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "SNAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CNAK": {
+ "description": "CNAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "Stall": {
+ "description": "Stall",
+ "offset": 21,
+ "size": 1
+ },
+ "SNPM": {
+ "description": "SNPM",
+ "offset": 20,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "EPTYP",
+ "offset": 18,
+ "size": 2
+ },
+ "NAKSTS": {
+ "description": "NAKSTS",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EONUM_DPID": {
+ "description": "EONUM/DPID",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "USBAEP": {
+ "description": "USBAEP",
+ "offset": 15,
+ "size": 1
+ },
+ "MPSIZ": {
+ "description": "MPSIZ",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "DOEPCTL3": {
+ "description": "device endpoint-3 control\n register",
+ "offset": 864,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EPENA": {
+ "description": "EPENA",
+ "offset": 31,
+ "size": 1
+ },
+ "EPDIS": {
+ "description": "EPDIS",
+ "offset": 30,
+ "size": 1
+ },
+ "SODDFRM": {
+ "description": "SODDFRM",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "SD0PID/SEVNFRM",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "SNAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CNAK": {
+ "description": "CNAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "Stall": {
+ "description": "Stall",
+ "offset": 21,
+ "size": 1
+ },
+ "SNPM": {
+ "description": "SNPM",
+ "offset": 20,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "EPTYP",
+ "offset": 18,
+ "size": 2
+ },
+ "NAKSTS": {
+ "description": "NAKSTS",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EONUM_DPID": {
+ "description": "EONUM/DPID",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "USBAEP": {
+ "description": "USBAEP",
+ "offset": 15,
+ "size": 1
+ },
+ "MPSIZ": {
+ "description": "MPSIZ",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "DIEPINT0": {
+ "description": "device endpoint-x interrupt\n register",
+ "offset": 264,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TXFE": {
+ "description": "TXFE",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "INEPNE": {
+ "description": "INEPNE",
+ "offset": 6,
+ "size": 1
+ },
+ "ITTXFE": {
+ "description": "ITTXFE",
+ "offset": 4,
+ "size": 1
+ },
+ "TOC": {
+ "description": "TOC",
+ "offset": 3,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "EPDISD",
+ "offset": 1,
+ "size": 1
+ },
+ "XFRC": {
+ "description": "XFRC",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DIEPINT1": {
+ "description": "device endpoint-1 interrupt\n register",
+ "offset": 296,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TXFE": {
+ "description": "TXFE",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "INEPNE": {
+ "description": "INEPNE",
+ "offset": 6,
+ "size": 1
+ },
+ "ITTXFE": {
+ "description": "ITTXFE",
+ "offset": 4,
+ "size": 1
+ },
+ "TOC": {
+ "description": "TOC",
+ "offset": 3,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "EPDISD",
+ "offset": 1,
+ "size": 1
+ },
+ "XFRC": {
+ "description": "XFRC",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DIEPINT2": {
+ "description": "device endpoint-2 interrupt\n register",
+ "offset": 328,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TXFE": {
+ "description": "TXFE",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "INEPNE": {
+ "description": "INEPNE",
+ "offset": 6,
+ "size": 1
+ },
+ "ITTXFE": {
+ "description": "ITTXFE",
+ "offset": 4,
+ "size": 1
+ },
+ "TOC": {
+ "description": "TOC",
+ "offset": 3,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "EPDISD",
+ "offset": 1,
+ "size": 1
+ },
+ "XFRC": {
+ "description": "XFRC",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DIEPINT3": {
+ "description": "device endpoint-3 interrupt\n register",
+ "offset": 360,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TXFE": {
+ "description": "TXFE",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "INEPNE": {
+ "description": "INEPNE",
+ "offset": 6,
+ "size": 1
+ },
+ "ITTXFE": {
+ "description": "ITTXFE",
+ "offset": 4,
+ "size": 1
+ },
+ "TOC": {
+ "description": "TOC",
+ "offset": 3,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "EPDISD",
+ "offset": 1,
+ "size": 1
+ },
+ "XFRC": {
+ "description": "XFRC",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DOEPINT0": {
+ "description": "device endpoint-0 interrupt\n register",
+ "offset": 776,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "B2BSTUP": {
+ "description": "B2BSTUP",
+ "offset": 6,
+ "size": 1
+ },
+ "OTEPDIS": {
+ "description": "OTEPDIS",
+ "offset": 4,
+ "size": 1
+ },
+ "STUP": {
+ "description": "STUP",
+ "offset": 3,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "EPDISD",
+ "offset": 1,
+ "size": 1
+ },
+ "XFRC": {
+ "description": "XFRC",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DOEPINT1": {
+ "description": "device endpoint-1 interrupt\n register",
+ "offset": 808,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "B2BSTUP": {
+ "description": "B2BSTUP",
+ "offset": 6,
+ "size": 1
+ },
+ "OTEPDIS": {
+ "description": "OTEPDIS",
+ "offset": 4,
+ "size": 1
+ },
+ "STUP": {
+ "description": "STUP",
+ "offset": 3,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "EPDISD",
+ "offset": 1,
+ "size": 1
+ },
+ "XFRC": {
+ "description": "XFRC",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DOEPINT2": {
+ "description": "device endpoint-2 interrupt\n register",
+ "offset": 840,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "B2BSTUP": {
+ "description": "B2BSTUP",
+ "offset": 6,
+ "size": 1
+ },
+ "OTEPDIS": {
+ "description": "OTEPDIS",
+ "offset": 4,
+ "size": 1
+ },
+ "STUP": {
+ "description": "STUP",
+ "offset": 3,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "EPDISD",
+ "offset": 1,
+ "size": 1
+ },
+ "XFRC": {
+ "description": "XFRC",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DOEPINT3": {
+ "description": "device endpoint-3 interrupt\n register",
+ "offset": 872,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "B2BSTUP": {
+ "description": "B2BSTUP",
+ "offset": 6,
+ "size": 1
+ },
+ "OTEPDIS": {
+ "description": "OTEPDIS",
+ "offset": 4,
+ "size": 1
+ },
+ "STUP": {
+ "description": "STUP",
+ "offset": 3,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "EPDISD",
+ "offset": 1,
+ "size": 1
+ },
+ "XFRC": {
+ "description": "XFRC",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DIEPTSIZ0": {
+ "description": "device endpoint-0 transfer size\n register",
+ "offset": 272,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 2
+ },
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 7
+ }
+ }
+ }
+ },
+ "DOEPTSIZ0": {
+ "description": "device OUT endpoint-0 transfer size\n register",
+ "offset": 784,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "STUPCNT": {
+ "description": "SETUP packet count",
+ "offset": 29,
+ "size": 2
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 1
+ },
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 7
+ }
+ }
+ }
+ },
+ "DIEPTSIZ1": {
+ "description": "device endpoint-1 transfer size\n register",
+ "offset": 304,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MCNT": {
+ "description": "Multi count",
+ "offset": 29,
+ "size": 2
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ }
+ }
+ }
+ },
+ "DIEPTSIZ2": {
+ "description": "device endpoint-2 transfer size\n register",
+ "offset": 336,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MCNT": {
+ "description": "Multi count",
+ "offset": 29,
+ "size": 2
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ }
+ }
+ }
+ },
+ "DIEPTSIZ3": {
+ "description": "device endpoint-3 transfer size\n register",
+ "offset": 368,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MCNT": {
+ "description": "Multi count",
+ "offset": 29,
+ "size": 2
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ }
+ }
+ }
+ },
+ "DTXFSTS0": {
+ "description": "OTG_FS device IN endpoint transmit FIFO\n status register",
+ "offset": 280,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "INEPTFSAV": {
+ "description": "IN endpoint TxFIFO space\n available",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DTXFSTS1": {
+ "description": "OTG_FS device IN endpoint transmit FIFO\n status register",
+ "offset": 312,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "INEPTFSAV": {
+ "description": "IN endpoint TxFIFO space\n available",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DTXFSTS2": {
+ "description": "OTG_FS device IN endpoint transmit FIFO\n status register",
+ "offset": 344,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "INEPTFSAV": {
+ "description": "IN endpoint TxFIFO space\n available",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DTXFSTS3": {
+ "description": "OTG_FS device IN endpoint transmit FIFO\n status register",
+ "offset": 376,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "INEPTFSAV": {
+ "description": "IN endpoint TxFIFO space\n available",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DOEPTSIZ1": {
+ "description": "device OUT endpoint-1 transfer size\n register",
+ "offset": 816,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RXDPID_STUPCNT": {
+ "description": "Received data PID/SETUP packet\n count",
+ "offset": 29,
+ "size": 2
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ }
+ }
+ }
+ },
+ "DOEPTSIZ2": {
+ "description": "device OUT endpoint-2 transfer size\n register",
+ "offset": 848,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RXDPID_STUPCNT": {
+ "description": "Received data PID/SETUP packet\n count",
+ "offset": 29,
+ "size": 2
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ }
+ }
+ }
+ },
+ "DOEPTSIZ3": {
+ "description": "device OUT endpoint-3 transfer size\n register",
+ "offset": 880,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RXDPID_STUPCNT": {
+ "description": "Received data PID/SETUP packet\n count",
+ "offset": 29,
+ "size": 2
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "OTG_FS_HOST": {
+ "description": "USB on the go full speed",
+ "children": {
+ "registers": {
+ "FS_HCFG": {
+ "description": "OTG_FS host configuration register\n (OTG_FS_HCFG)",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FSLSPCS": {
+ "description": "FS/LS PHY clock select",
+ "offset": 0,
+ "size": 2
+ },
+ "FSLSS": {
+ "description": "FS- and LS-only support",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "HFIR": {
+ "description": "OTG_FS Host frame interval\n register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 60000,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FRIVL": {
+ "description": "Frame interval",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_HFNUM": {
+ "description": "OTG_FS host frame number/frame time\n remaining register (OTG_FS_HFNUM)",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 16383,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "FRNUM": {
+ "description": "Frame number",
+ "offset": 0,
+ "size": 16
+ },
+ "FTREM": {
+ "description": "Frame time remaining",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_HPTXSTS": {
+ "description": "OTG_FS_Host periodic transmit FIFO/queue\n status register (OTG_FS_HPTXSTS)",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 524544,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PTXFSAVL": {
+ "description": "Periodic transmit data FIFO space\n available",
+ "offset": 0,
+ "size": 16
+ },
+ "PTXQSAV": {
+ "description": "Periodic transmit request queue space\n available",
+ "offset": 16,
+ "size": 8,
+ "access": "read-only"
+ },
+ "PTXQTOP": {
+ "description": "Top of the periodic transmit request\n queue",
+ "offset": 24,
+ "size": 8,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "HAINT": {
+ "description": "OTG_FS Host all channels interrupt\n register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "HAINT": {
+ "description": "Channel interrupts",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "HAINTMSK": {
+ "description": "OTG_FS host all channels interrupt mask\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "HAINTM": {
+ "description": "Channel interrupt mask",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_HPRT": {
+ "description": "OTG_FS host port control and status register\n (OTG_FS_HPRT)",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PCSTS": {
+ "description": "Port connect status",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PCDET": {
+ "description": "Port connect detected",
+ "offset": 1,
+ "size": 1
+ },
+ "PENA": {
+ "description": "Port enable",
+ "offset": 2,
+ "size": 1
+ },
+ "PENCHNG": {
+ "description": "Port enable/disable change",
+ "offset": 3,
+ "size": 1
+ },
+ "POCA": {
+ "description": "Port overcurrent active",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "POCCHNG": {
+ "description": "Port overcurrent change",
+ "offset": 5,
+ "size": 1
+ },
+ "PRES": {
+ "description": "Port resume",
+ "offset": 6,
+ "size": 1
+ },
+ "PSUSP": {
+ "description": "Port suspend",
+ "offset": 7,
+ "size": 1
+ },
+ "PRST": {
+ "description": "Port reset",
+ "offset": 8,
+ "size": 1
+ },
+ "PLSTS": {
+ "description": "Port line status",
+ "offset": 10,
+ "size": 2,
+ "access": "read-only"
+ },
+ "PPWR": {
+ "description": "Port power",
+ "offset": 12,
+ "size": 1
+ },
+ "PTCTL": {
+ "description": "Port test control",
+ "offset": 13,
+ "size": 4
+ },
+ "PSPD": {
+ "description": "Port speed",
+ "offset": 17,
+ "size": 2,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "FS_HCCHAR0": {
+ "description": "OTG_FS host channel-0 characteristics\n register (OTG_FS_HCCHAR0)",
+ "offset": 256,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MCNT": {
+ "description": "Multicount",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCCHAR1": {
+ "description": "OTG_FS host channel-1 characteristics\n register (OTG_FS_HCCHAR1)",
+ "offset": 288,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MCNT": {
+ "description": "Multicount",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCCHAR2": {
+ "description": "OTG_FS host channel-2 characteristics\n register (OTG_FS_HCCHAR2)",
+ "offset": 320,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MCNT": {
+ "description": "Multicount",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCCHAR3": {
+ "description": "OTG_FS host channel-3 characteristics\n register (OTG_FS_HCCHAR3)",
+ "offset": 352,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MCNT": {
+ "description": "Multicount",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCCHAR4": {
+ "description": "OTG_FS host channel-4 characteristics\n register (OTG_FS_HCCHAR4)",
+ "offset": 384,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MCNT": {
+ "description": "Multicount",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCCHAR5": {
+ "description": "OTG_FS host channel-5 characteristics\n register (OTG_FS_HCCHAR5)",
+ "offset": 416,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MCNT": {
+ "description": "Multicount",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCCHAR6": {
+ "description": "OTG_FS host channel-6 characteristics\n register (OTG_FS_HCCHAR6)",
+ "offset": 448,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MCNT": {
+ "description": "Multicount",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCCHAR7": {
+ "description": "OTG_FS host channel-7 characteristics\n register (OTG_FS_HCCHAR7)",
+ "offset": 480,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MCNT": {
+ "description": "Multicount",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINT0": {
+ "description": "OTG_FS host channel-0 interrupt register\n (OTG_FS_HCINT0)",
+ "offset": 264,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINT1": {
+ "description": "OTG_FS host channel-1 interrupt register\n (OTG_FS_HCINT1)",
+ "offset": 296,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINT2": {
+ "description": "OTG_FS host channel-2 interrupt register\n (OTG_FS_HCINT2)",
+ "offset": 328,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINT3": {
+ "description": "OTG_FS host channel-3 interrupt register\n (OTG_FS_HCINT3)",
+ "offset": 360,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINT4": {
+ "description": "OTG_FS host channel-4 interrupt register\n (OTG_FS_HCINT4)",
+ "offset": 392,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINT5": {
+ "description": "OTG_FS host channel-5 interrupt register\n (OTG_FS_HCINT5)",
+ "offset": 424,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINT6": {
+ "description": "OTG_FS host channel-6 interrupt register\n (OTG_FS_HCINT6)",
+ "offset": 456,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINT7": {
+ "description": "OTG_FS host channel-7 interrupt register\n (OTG_FS_HCINT7)",
+ "offset": 488,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINTMSK0": {
+ "description": "OTG_FS host channel-0 mask register\n (OTG_FS_HCINTMSK0)",
+ "offset": 268,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINTMSK1": {
+ "description": "OTG_FS host channel-1 mask register\n (OTG_FS_HCINTMSK1)",
+ "offset": 300,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINTMSK2": {
+ "description": "OTG_FS host channel-2 mask register\n (OTG_FS_HCINTMSK2)",
+ "offset": 332,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINTMSK3": {
+ "description": "OTG_FS host channel-3 mask register\n (OTG_FS_HCINTMSK3)",
+ "offset": 364,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINTMSK4": {
+ "description": "OTG_FS host channel-4 mask register\n (OTG_FS_HCINTMSK4)",
+ "offset": 396,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINTMSK5": {
+ "description": "OTG_FS host channel-5 mask register\n (OTG_FS_HCINTMSK5)",
+ "offset": 428,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINTMSK6": {
+ "description": "OTG_FS host channel-6 mask register\n (OTG_FS_HCINTMSK6)",
+ "offset": 460,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINTMSK7": {
+ "description": "OTG_FS host channel-7 mask register\n (OTG_FS_HCINTMSK7)",
+ "offset": 492,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCTSIZ0": {
+ "description": "OTG_FS host channel-0 transfer size\n register",
+ "offset": 272,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "FS_HCTSIZ1": {
+ "description": "OTG_FS host channel-1 transfer size\n register",
+ "offset": 304,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "FS_HCTSIZ2": {
+ "description": "OTG_FS host channel-2 transfer size\n register",
+ "offset": 336,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "FS_HCTSIZ3": {
+ "description": "OTG_FS host channel-3 transfer size\n register",
+ "offset": 368,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "FS_HCTSIZ4": {
+ "description": "OTG_FS host channel-x transfer size\n register",
+ "offset": 400,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "FS_HCTSIZ5": {
+ "description": "OTG_FS host channel-5 transfer size\n register",
+ "offset": 432,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "FS_HCTSIZ6": {
+ "description": "OTG_FS host channel-6 transfer size\n register",
+ "offset": 464,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "FS_HCTSIZ7": {
+ "description": "OTG_FS host channel-7 transfer size\n register",
+ "offset": 496,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "IWDG": {
+ "description": "Independent watchdog",
+ "children": {
+ "registers": {
+ "KR": {
+ "description": "Key register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "KEY": {
+ "description": "Key value (write only, read\n 0000h)",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "PR": {
+ "description": "Prescaler register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PR": {
+ "description": "Prescaler divider",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "RLR": {
+ "description": "Reload register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 4095,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RL": {
+ "description": "Watchdog counter reload\n value",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "Status register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "RVU": {
+ "description": "Watchdog counter reload value\n update",
+ "offset": 1,
+ "size": 1
+ },
+ "PVU": {
+ "description": "Watchdog prescaler value\n update",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "WWDG": {
+ "description": "Window watchdog",
+ "children": {
+ "registers": {
+ "CR": {
+ "description": "Control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 127,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "WDGA": {
+ "description": "Activation bit",
+ "offset": 7,
+ "size": 1
+ },
+ "T": {
+ "description": "7-bit counter (MSB to LSB)",
+ "offset": 0,
+ "size": 7
+ }
+ }
+ }
+ },
+ "CFR": {
+ "description": "Configuration register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 127,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EWI": {
+ "description": "Early wakeup interrupt",
+ "offset": 9,
+ "size": 1
+ },
+ "WDGTB1": {
+ "description": "Timer base",
+ "offset": 8,
+ "size": 1
+ },
+ "WDGTB0": {
+ "description": "Timer base",
+ "offset": 7,
+ "size": 1
+ },
+ "W": {
+ "description": "7-bit window value",
+ "offset": 0,
+ "size": 7
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "Status register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EWIF": {
+ "description": "Early wakeup interrupt\n flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "RTC": {
+ "description": "Real-time clock",
+ "children": {
+ "registers": {
+ "TR": {
+ "description": "time register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PM": {
+ "description": "AM/PM notation",
+ "offset": 22,
+ "size": 1
+ },
+ "HT": {
+ "description": "Hour tens in BCD format",
+ "offset": 20,
+ "size": 2
+ },
+ "HU": {
+ "description": "Hour units in BCD format",
+ "offset": 16,
+ "size": 4
+ },
+ "MNT": {
+ "description": "Minute tens in BCD format",
+ "offset": 12,
+ "size": 3
+ },
+ "MNU": {
+ "description": "Minute units in BCD format",
+ "offset": 8,
+ "size": 4
+ },
+ "ST": {
+ "description": "Second tens in BCD format",
+ "offset": 4,
+ "size": 3
+ },
+ "SU": {
+ "description": "Second units in BCD format",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "DR": {
+ "description": "date register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 8449,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "YT": {
+ "description": "Year tens in BCD format",
+ "offset": 20,
+ "size": 4
+ },
+ "YU": {
+ "description": "Year units in BCD format",
+ "offset": 16,
+ "size": 4
+ },
+ "WDU": {
+ "description": "Week day units",
+ "offset": 13,
+ "size": 3
+ },
+ "MT": {
+ "description": "Month tens in BCD format",
+ "offset": 12,
+ "size": 1
+ },
+ "MU": {
+ "description": "Month units in BCD format",
+ "offset": 8,
+ "size": 4
+ },
+ "DT": {
+ "description": "Date tens in BCD format",
+ "offset": 4,
+ "size": 2
+ },
+ "DU": {
+ "description": "Date units in BCD format",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "CR": {
+ "description": "control register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "COE": {
+ "description": "Calibration output enable",
+ "offset": 23,
+ "size": 1
+ },
+ "OSEL": {
+ "description": "Output selection",
+ "offset": 21,
+ "size": 2
+ },
+ "POL": {
+ "description": "Output polarity",
+ "offset": 20,
+ "size": 1
+ },
+ "BKP": {
+ "description": "Backup",
+ "offset": 18,
+ "size": 1
+ },
+ "SUB1H": {
+ "description": "Subtract 1 hour (winter time\n change)",
+ "offset": 17,
+ "size": 1
+ },
+ "ADD1H": {
+ "description": "Add 1 hour (summer time\n change)",
+ "offset": 16,
+ "size": 1
+ },
+ "TSIE": {
+ "description": "Time-stamp interrupt\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "WUTIE": {
+ "description": "Wakeup timer interrupt\n enable",
+ "offset": 14,
+ "size": 1
+ },
+ "ALRBIE": {
+ "description": "Alarm B interrupt enable",
+ "offset": 13,
+ "size": 1
+ },
+ "ALRAIE": {
+ "description": "Alarm A interrupt enable",
+ "offset": 12,
+ "size": 1
+ },
+ "TSE": {
+ "description": "Time stamp enable",
+ "offset": 11,
+ "size": 1
+ },
+ "WUTE": {
+ "description": "Wakeup timer enable",
+ "offset": 10,
+ "size": 1
+ },
+ "ALRBE": {
+ "description": "Alarm B enable",
+ "offset": 9,
+ "size": 1
+ },
+ "ALRAE": {
+ "description": "Alarm A enable",
+ "offset": 8,
+ "size": 1
+ },
+ "DCE": {
+ "description": "Coarse digital calibration\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "FMT": {
+ "description": "Hour format",
+ "offset": 6,
+ "size": 1
+ },
+ "REFCKON": {
+ "description": "Reference clock detection enable (50 or\n 60 Hz)",
+ "offset": 4,
+ "size": 1
+ },
+ "TSEDGE": {
+ "description": "Time-stamp event active\n edge",
+ "offset": 3,
+ "size": 1
+ },
+ "WCKSEL": {
+ "description": "Wakeup clock selection",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "ISR": {
+ "description": "initialization and status\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 7,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ALRAWF": {
+ "description": "Alarm A write flag",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ALRBWF": {
+ "description": "Alarm B write flag",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "WUTWF": {
+ "description": "Wakeup timer write flag",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SHPF": {
+ "description": "Shift operation pending",
+ "offset": 3,
+ "size": 1
+ },
+ "INITS": {
+ "description": "Initialization status flag",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "RSF": {
+ "description": "Registers synchronization\n flag",
+ "offset": 5,
+ "size": 1
+ },
+ "INITF": {
+ "description": "Initialization flag",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "INIT": {
+ "description": "Initialization mode",
+ "offset": 7,
+ "size": 1
+ },
+ "ALRAF": {
+ "description": "Alarm A flag",
+ "offset": 8,
+ "size": 1
+ },
+ "ALRBF": {
+ "description": "Alarm B flag",
+ "offset": 9,
+ "size": 1
+ },
+ "WUTF": {
+ "description": "Wakeup timer flag",
+ "offset": 10,
+ "size": 1
+ },
+ "TSF": {
+ "description": "Time-stamp flag",
+ "offset": 11,
+ "size": 1
+ },
+ "TSOVF": {
+ "description": "Time-stamp overflow flag",
+ "offset": 12,
+ "size": 1
+ },
+ "TAMP1F": {
+ "description": "Tamper detection flag",
+ "offset": 13,
+ "size": 1
+ },
+ "TAMP2F": {
+ "description": "TAMPER2 detection flag",
+ "offset": 14,
+ "size": 1
+ },
+ "RECALPF": {
+ "description": "Recalibration pending Flag",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "PRER": {
+ "description": "prescaler register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 8323327,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PREDIV_A": {
+ "description": "Asynchronous prescaler\n factor",
+ "offset": 16,
+ "size": 7
+ },
+ "PREDIV_S": {
+ "description": "Synchronous prescaler\n factor",
+ "offset": 0,
+ "size": 15
+ }
+ }
+ }
+ },
+ "WUTR": {
+ "description": "wakeup timer register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 65535,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "WUT": {
+ "description": "Wakeup auto-reload value\n bits",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CALIBR": {
+ "description": "calibration register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DCS": {
+ "description": "Digital calibration sign",
+ "offset": 7,
+ "size": 1
+ },
+ "DC": {
+ "description": "Digital calibration",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "ALRMAR": {
+ "description": "alarm A register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MSK4": {
+ "description": "Alarm A date mask",
+ "offset": 31,
+ "size": 1
+ },
+ "WDSEL": {
+ "description": "Week day selection",
+ "offset": 30,
+ "size": 1
+ },
+ "DT": {
+ "description": "Date tens in BCD format",
+ "offset": 28,
+ "size": 2
+ },
+ "DU": {
+ "description": "Date units or day in BCD\n format",
+ "offset": 24,
+ "size": 4
+ },
+ "MSK3": {
+ "description": "Alarm A hours mask",
+ "offset": 23,
+ "size": 1
+ },
+ "PM": {
+ "description": "AM/PM notation",
+ "offset": 22,
+ "size": 1
+ },
+ "HT": {
+ "description": "Hour tens in BCD format",
+ "offset": 20,
+ "size": 2
+ },
+ "HU": {
+ "description": "Hour units in BCD format",
+ "offset": 16,
+ "size": 4
+ },
+ "MSK2": {
+ "description": "Alarm A minutes mask",
+ "offset": 15,
+ "size": 1
+ },
+ "MNT": {
+ "description": "Minute tens in BCD format",
+ "offset": 12,
+ "size": 3
+ },
+ "MNU": {
+ "description": "Minute units in BCD format",
+ "offset": 8,
+ "size": 4
+ },
+ "MSK1": {
+ "description": "Alarm A seconds mask",
+ "offset": 7,
+ "size": 1
+ },
+ "ST": {
+ "description": "Second tens in BCD format",
+ "offset": 4,
+ "size": 3
+ },
+ "SU": {
+ "description": "Second units in BCD format",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "ALRMBR": {
+ "description": "alarm B register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MSK4": {
+ "description": "Alarm B date mask",
+ "offset": 31,
+ "size": 1
+ },
+ "WDSEL": {
+ "description": "Week day selection",
+ "offset": 30,
+ "size": 1
+ },
+ "DT": {
+ "description": "Date tens in BCD format",
+ "offset": 28,
+ "size": 2
+ },
+ "DU": {
+ "description": "Date units or day in BCD\n format",
+ "offset": 24,
+ "size": 4
+ },
+ "MSK3": {
+ "description": "Alarm B hours mask",
+ "offset": 23,
+ "size": 1
+ },
+ "PM": {
+ "description": "AM/PM notation",
+ "offset": 22,
+ "size": 1
+ },
+ "HT": {
+ "description": "Hour tens in BCD format",
+ "offset": 20,
+ "size": 2
+ },
+ "HU": {
+ "description": "Hour units in BCD format",
+ "offset": 16,
+ "size": 4
+ },
+ "MSK2": {
+ "description": "Alarm B minutes mask",
+ "offset": 15,
+ "size": 1
+ },
+ "MNT": {
+ "description": "Minute tens in BCD format",
+ "offset": 12,
+ "size": 3
+ },
+ "MNU": {
+ "description": "Minute units in BCD format",
+ "offset": 8,
+ "size": 4
+ },
+ "MSK1": {
+ "description": "Alarm B seconds mask",
+ "offset": 7,
+ "size": 1
+ },
+ "ST": {
+ "description": "Second tens in BCD format",
+ "offset": 4,
+ "size": 3
+ },
+ "SU": {
+ "description": "Second units in BCD format",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "WPR": {
+ "description": "write protection register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "KEY": {
+ "description": "Write protection key",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "SSR": {
+ "description": "sub second register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "SS": {
+ "description": "Sub second value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "SHIFTR": {
+ "description": "shift control register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "ADD1S": {
+ "description": "Add one second",
+ "offset": 31,
+ "size": 1
+ },
+ "SUBFS": {
+ "description": "Subtract a fraction of a\n second",
+ "offset": 0,
+ "size": 15
+ }
+ }
+ }
+ },
+ "TSTR": {
+ "description": "time stamp time register",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "ALARMOUTTYPE": {
+ "description": "AFO_ALARM output type",
+ "offset": 18,
+ "size": 1
+ },
+ "TSINSEL": {
+ "description": "TIMESTAMP mapping",
+ "offset": 17,
+ "size": 1
+ },
+ "TAMP1INSEL": {
+ "description": "TAMPER1 mapping",
+ "offset": 16,
+ "size": 1
+ },
+ "TAMPIE": {
+ "description": "Tamper interrupt enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TAMP1TRG": {
+ "description": "Active level for tamper 1",
+ "offset": 1,
+ "size": 1
+ },
+ "TAMP1E": {
+ "description": "Tamper 1 detection enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "TSDR": {
+ "description": "time stamp date register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "WDU": {
+ "description": "Week day units",
+ "offset": 13,
+ "size": 3
+ },
+ "MT": {
+ "description": "Month tens in BCD format",
+ "offset": 12,
+ "size": 1
+ },
+ "MU": {
+ "description": "Month units in BCD format",
+ "offset": 8,
+ "size": 4
+ },
+ "DT": {
+ "description": "Date tens in BCD format",
+ "offset": 4,
+ "size": 2
+ },
+ "DU": {
+ "description": "Date units in BCD format",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "TSSSR": {
+ "description": "timestamp sub second register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "SS": {
+ "description": "Sub second value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CALR": {
+ "description": "calibration register",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CALP": {
+ "description": "Increase frequency of RTC by 488.5\n ppm",
+ "offset": 15,
+ "size": 1
+ },
+ "CALW8": {
+ "description": "Use an 8-second calibration cycle\n period",
+ "offset": 14,
+ "size": 1
+ },
+ "CALW16": {
+ "description": "Use a 16-second calibration cycle\n period",
+ "offset": 13,
+ "size": 1
+ },
+ "CALM": {
+ "description": "Calibration minus",
+ "offset": 0,
+ "size": 9
+ }
+ }
+ }
+ },
+ "TAFCR": {
+ "description": "tamper and alternate function configuration\n register",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ALARMOUTTYPE": {
+ "description": "AFO_ALARM output type",
+ "offset": 18,
+ "size": 1
+ },
+ "TSINSEL": {
+ "description": "TIMESTAMP mapping",
+ "offset": 17,
+ "size": 1
+ },
+ "TAMP1INSEL": {
+ "description": "TAMPER1 mapping",
+ "offset": 16,
+ "size": 1
+ },
+ "TAMPPUDIS": {
+ "description": "TAMPER pull-up disable",
+ "offset": 15,
+ "size": 1
+ },
+ "TAMPPRCH": {
+ "description": "Tamper precharge duration",
+ "offset": 13,
+ "size": 2
+ },
+ "TAMPFLT": {
+ "description": "Tamper filter count",
+ "offset": 11,
+ "size": 2
+ },
+ "TAMPFREQ": {
+ "description": "Tamper sampling frequency",
+ "offset": 8,
+ "size": 3
+ },
+ "TAMPTS": {
+ "description": "Activate timestamp on tamper detection\n event",
+ "offset": 7,
+ "size": 1
+ },
+ "TAMP2TRG": {
+ "description": "Active level for tamper 2",
+ "offset": 4,
+ "size": 1
+ },
+ "TAMP2E": {
+ "description": "Tamper 2 detection enable",
+ "offset": 3,
+ "size": 1
+ },
+ "TAMPIE": {
+ "description": "Tamper interrupt enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TAMP1TRG": {
+ "description": "Active level for tamper 1",
+ "offset": 1,
+ "size": 1
+ },
+ "TAMP1E": {
+ "description": "Tamper 1 detection enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ALRMASSR": {
+ "description": "alarm A sub second register",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MASKSS": {
+ "description": "Mask the most-significant bits starting\n at this bit",
+ "offset": 24,
+ "size": 4
+ },
+ "SS": {
+ "description": "Sub seconds value",
+ "offset": 0,
+ "size": 15
+ }
+ }
+ }
+ },
+ "ALRMBSSR": {
+ "description": "alarm B sub second register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MASKSS": {
+ "description": "Mask the most-significant bits starting\n at this bit",
+ "offset": 24,
+ "size": 4
+ },
+ "SS": {
+ "description": "Sub seconds value",
+ "offset": 0,
+ "size": 15
+ }
+ }
+ }
+ },
+ "BKP0R": {
+ "description": "backup register",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP1R": {
+ "description": "backup register",
+ "offset": 84,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP2R": {
+ "description": "backup register",
+ "offset": 88,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP3R": {
+ "description": "backup register",
+ "offset": 92,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP4R": {
+ "description": "backup register",
+ "offset": 96,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP5R": {
+ "description": "backup register",
+ "offset": 100,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP6R": {
+ "description": "backup register",
+ "offset": 104,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP7R": {
+ "description": "backup register",
+ "offset": 108,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP8R": {
+ "description": "backup register",
+ "offset": 112,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP9R": {
+ "description": "backup register",
+ "offset": 116,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP10R": {
+ "description": "backup register",
+ "offset": 120,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP11R": {
+ "description": "backup register",
+ "offset": 124,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP12R": {
+ "description": "backup register",
+ "offset": 128,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP13R": {
+ "description": "backup register",
+ "offset": 132,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP14R": {
+ "description": "backup register",
+ "offset": 136,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP15R": {
+ "description": "backup register",
+ "offset": 140,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP16R": {
+ "description": "backup register",
+ "offset": 144,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP17R": {
+ "description": "backup register",
+ "offset": 148,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP18R": {
+ "description": "backup register",
+ "offset": 152,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP19R": {
+ "description": "backup register",
+ "offset": 156,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "UART4": {
+ "description": "Universal synchronous asynchronous receiver\n transmitter",
+ "children": {
+ "registers": {
+ "SR": {
+ "description": "Status register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 12582912,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LBD": {
+ "description": "LIN break detection flag",
+ "offset": 8,
+ "size": 1
+ },
+ "TXE": {
+ "description": "Transmit data register\n empty",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TC": {
+ "description": "Transmission complete",
+ "offset": 6,
+ "size": 1
+ },
+ "RXNE": {
+ "description": "Read data register not\n empty",
+ "offset": 5,
+ "size": 1
+ },
+ "IDLE": {
+ "description": "IDLE line detected",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ORE": {
+ "description": "Overrun error",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NF": {
+ "description": "Noise detected flag",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "FE": {
+ "description": "Framing error",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PE": {
+ "description": "Parity error",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "DR": {
+ "description": "Data register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DR": {
+ "description": "Data value",
+ "offset": 0,
+ "size": 9
+ }
+ }
+ }
+ },
+ "BRR": {
+ "description": "Baud rate register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DIV_Mantissa": {
+ "description": "mantissa of USARTDIV",
+ "offset": 4,
+ "size": 12
+ },
+ "DIV_Fraction": {
+ "description": "fraction of USARTDIV",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "CR1": {
+ "description": "Control register 1",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OVER8": {
+ "description": "Oversampling mode",
+ "offset": 15,
+ "size": 1
+ },
+ "UE": {
+ "description": "USART enable",
+ "offset": 13,
+ "size": 1
+ },
+ "M": {
+ "description": "Word length",
+ "offset": 12,
+ "size": 1
+ },
+ "WAKE": {
+ "description": "Wakeup method",
+ "offset": 11,
+ "size": 1
+ },
+ "PCE": {
+ "description": "Parity control enable",
+ "offset": 10,
+ "size": 1
+ },
+ "PS": {
+ "description": "Parity selection",
+ "offset": 9,
+ "size": 1
+ },
+ "PEIE": {
+ "description": "PE interrupt enable",
+ "offset": 8,
+ "size": 1
+ },
+ "TXEIE": {
+ "description": "TXE interrupt enable",
+ "offset": 7,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transmission complete interrupt\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "RXNEIE": {
+ "description": "RXNE interrupt enable",
+ "offset": 5,
+ "size": 1
+ },
+ "IDLEIE": {
+ "description": "IDLE interrupt enable",
+ "offset": 4,
+ "size": 1
+ },
+ "TE": {
+ "description": "Transmitter enable",
+ "offset": 3,
+ "size": 1
+ },
+ "RE": {
+ "description": "Receiver enable",
+ "offset": 2,
+ "size": 1
+ },
+ "RWU": {
+ "description": "Receiver wakeup",
+ "offset": 1,
+ "size": 1
+ },
+ "SBK": {
+ "description": "Send break",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "Control register 2",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LINEN": {
+ "description": "LIN mode enable",
+ "offset": 14,
+ "size": 1
+ },
+ "STOP": {
+ "description": "STOP bits",
+ "offset": 12,
+ "size": 2
+ },
+ "LBDIE": {
+ "description": "LIN break detection interrupt\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "LBDL": {
+ "description": "lin break detection length",
+ "offset": 5,
+ "size": 1
+ },
+ "ADD": {
+ "description": "Address of the USART node",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "CR3": {
+ "description": "Control register 3",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ONEBIT": {
+ "description": "One sample bit method\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "DMAT": {
+ "description": "DMA enable transmitter",
+ "offset": 7,
+ "size": 1
+ },
+ "DMAR": {
+ "description": "DMA enable receiver",
+ "offset": 6,
+ "size": 1
+ },
+ "HDSEL": {
+ "description": "Half-duplex selection",
+ "offset": 3,
+ "size": 1
+ },
+ "IRLP": {
+ "description": "IrDA low-power",
+ "offset": 2,
+ "size": 1
+ },
+ "IREN": {
+ "description": "IrDA mode enable",
+ "offset": 1,
+ "size": 1
+ },
+ "EIE": {
+ "description": "Error interrupt enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "OTG_FS_GLOBAL": {
+ "description": "USB on the go full speed",
+ "children": {
+ "registers": {
+ "FS_GOTGCTL": {
+ "description": "OTG_FS control and status register\n (OTG_FS_GOTGCTL)",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 2048,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SRQSCS": {
+ "description": "Session request success",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SRQ": {
+ "description": "Session request",
+ "offset": 1,
+ "size": 1
+ },
+ "HNGSCS": {
+ "description": "Host negotiation success",
+ "offset": 8,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HNPRQ": {
+ "description": "HNP request",
+ "offset": 9,
+ "size": 1
+ },
+ "HSHNPEN": {
+ "description": "Host set HNP enable",
+ "offset": 10,
+ "size": 1
+ },
+ "DHNPEN": {
+ "description": "Device HNP enabled",
+ "offset": 11,
+ "size": 1
+ },
+ "CIDSTS": {
+ "description": "Connector ID status",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "DBCT": {
+ "description": "Long/short debounce time",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ASVLD": {
+ "description": "A-session valid",
+ "offset": 18,
+ "size": 1,
+ "access": "read-only"
+ },
+ "BSVLD": {
+ "description": "B-session valid",
+ "offset": 19,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "FS_GOTGINT": {
+ "description": "OTG_FS interrupt register\n (OTG_FS_GOTGINT)",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SEDET": {
+ "description": "Session end detected",
+ "offset": 2,
+ "size": 1
+ },
+ "SRSSCHG": {
+ "description": "Session request success status\n change",
+ "offset": 8,
+ "size": 1
+ },
+ "HNSSCHG": {
+ "description": "Host negotiation success status\n change",
+ "offset": 9,
+ "size": 1
+ },
+ "HNGDET": {
+ "description": "Host negotiation detected",
+ "offset": 17,
+ "size": 1
+ },
+ "ADTOCHG": {
+ "description": "A-device timeout change",
+ "offset": 18,
+ "size": 1
+ },
+ "DBCDNE": {
+ "description": "Debounce done",
+ "offset": 19,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_GAHBCFG": {
+ "description": "OTG_FS AHB configuration register\n (OTG_FS_GAHBCFG)",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "GINT": {
+ "description": "Global interrupt mask",
+ "offset": 0,
+ "size": 1
+ },
+ "TXFELVL": {
+ "description": "TxFIFO empty level",
+ "offset": 7,
+ "size": 1
+ },
+ "PTXFELVL": {
+ "description": "Periodic TxFIFO empty\n level",
+ "offset": 8,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_GUSBCFG": {
+ "description": "OTG_FS USB configuration register\n (OTG_FS_GUSBCFG)",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 2560,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TOCAL": {
+ "description": "FS timeout calibration",
+ "offset": 0,
+ "size": 3
+ },
+ "PHYSEL": {
+ "description": "Full Speed serial transceiver\n select",
+ "offset": 6,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SRPCAP": {
+ "description": "SRP-capable",
+ "offset": 8,
+ "size": 1
+ },
+ "HNPCAP": {
+ "description": "HNP-capable",
+ "offset": 9,
+ "size": 1
+ },
+ "TRDT": {
+ "description": "USB turnaround time",
+ "offset": 10,
+ "size": 4
+ },
+ "FHMOD": {
+ "description": "Force host mode",
+ "offset": 29,
+ "size": 1
+ },
+ "FDMOD": {
+ "description": "Force device mode",
+ "offset": 30,
+ "size": 1
+ },
+ "CTXPKT": {
+ "description": "Corrupt Tx packet",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_GRSTCTL": {
+ "description": "OTG_FS reset register\n (OTG_FS_GRSTCTL)",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 536870912,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSRST": {
+ "description": "Core soft reset",
+ "offset": 0,
+ "size": 1
+ },
+ "HSRST": {
+ "description": "HCLK soft reset",
+ "offset": 1,
+ "size": 1
+ },
+ "FCRST": {
+ "description": "Host frame counter reset",
+ "offset": 2,
+ "size": 1
+ },
+ "RXFFLSH": {
+ "description": "RxFIFO flush",
+ "offset": 4,
+ "size": 1
+ },
+ "TXFFLSH": {
+ "description": "TxFIFO flush",
+ "offset": 5,
+ "size": 1
+ },
+ "TXFNUM": {
+ "description": "TxFIFO number",
+ "offset": 6,
+ "size": 5
+ },
+ "AHBIDL": {
+ "description": "AHB master idle",
+ "offset": 31,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "FS_GINTSTS": {
+ "description": "OTG_FS core interrupt register\n (OTG_FS_GINTSTS)",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 67108896,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CMOD": {
+ "description": "Current mode of operation",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ },
+ "MMIS": {
+ "description": "Mode mismatch interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "OTGINT": {
+ "description": "OTG interrupt",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SOF": {
+ "description": "Start of frame",
+ "offset": 3,
+ "size": 1
+ },
+ "RXFLVL": {
+ "description": "RxFIFO non-empty",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NPTXFE": {
+ "description": "Non-periodic TxFIFO empty",
+ "offset": 5,
+ "size": 1,
+ "access": "read-only"
+ },
+ "GINAKEFF": {
+ "description": "Global IN non-periodic NAK\n effective",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "GOUTNAKEFF": {
+ "description": "Global OUT NAK effective",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ESUSP": {
+ "description": "Early suspend",
+ "offset": 10,
+ "size": 1
+ },
+ "USBSUSP": {
+ "description": "USB suspend",
+ "offset": 11,
+ "size": 1
+ },
+ "USBRST": {
+ "description": "USB reset",
+ "offset": 12,
+ "size": 1
+ },
+ "ENUMDNE": {
+ "description": "Enumeration done",
+ "offset": 13,
+ "size": 1
+ },
+ "ISOODRP": {
+ "description": "Isochronous OUT packet dropped\n interrupt",
+ "offset": 14,
+ "size": 1
+ },
+ "EOPF": {
+ "description": "End of periodic frame\n interrupt",
+ "offset": 15,
+ "size": 1
+ },
+ "IEPINT": {
+ "description": "IN endpoint interrupt",
+ "offset": 18,
+ "size": 1,
+ "access": "read-only"
+ },
+ "OEPINT": {
+ "description": "OUT endpoint interrupt",
+ "offset": 19,
+ "size": 1,
+ "access": "read-only"
+ },
+ "IISOIXFR": {
+ "description": "Incomplete isochronous IN\n transfer",
+ "offset": 20,
+ "size": 1
+ },
+ "IPXFR_INCOMPISOOUT": {
+ "description": "Incomplete periodic transfer(Host\n mode)/Incomplete isochronous OUT transfer(Device\n mode)",
+ "offset": 21,
+ "size": 1
+ },
+ "HPRTINT": {
+ "description": "Host port interrupt",
+ "offset": 24,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HCINT": {
+ "description": "Host channels interrupt",
+ "offset": 25,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PTXFE": {
+ "description": "Periodic TxFIFO empty",
+ "offset": 26,
+ "size": 1,
+ "access": "read-only"
+ },
+ "CIDSCHG": {
+ "description": "Connector ID status change",
+ "offset": 28,
+ "size": 1
+ },
+ "DISCINT": {
+ "description": "Disconnect detected\n interrupt",
+ "offset": 29,
+ "size": 1
+ },
+ "SRQINT": {
+ "description": "Session request/new session detected\n interrupt",
+ "offset": 30,
+ "size": 1
+ },
+ "WKUPINT": {
+ "description": "Resume/remote wakeup detected\n interrupt",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_GINTMSK": {
+ "description": "OTG_FS interrupt mask register\n (OTG_FS_GINTMSK)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MMISM": {
+ "description": "Mode mismatch interrupt\n mask",
+ "offset": 1,
+ "size": 1
+ },
+ "OTGINT": {
+ "description": "OTG interrupt mask",
+ "offset": 2,
+ "size": 1
+ },
+ "SOFM": {
+ "description": "Start of frame mask",
+ "offset": 3,
+ "size": 1
+ },
+ "RXFLVLM": {
+ "description": "Receive FIFO non-empty\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "NPTXFEM": {
+ "description": "Non-periodic TxFIFO empty\n mask",
+ "offset": 5,
+ "size": 1
+ },
+ "GINAKEFFM": {
+ "description": "Global non-periodic IN NAK effective\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "GONAKEFFM": {
+ "description": "Global OUT NAK effective\n mask",
+ "offset": 7,
+ "size": 1
+ },
+ "ESUSPM": {
+ "description": "Early suspend mask",
+ "offset": 10,
+ "size": 1
+ },
+ "USBSUSPM": {
+ "description": "USB suspend mask",
+ "offset": 11,
+ "size": 1
+ },
+ "USBRST": {
+ "description": "USB reset mask",
+ "offset": 12,
+ "size": 1
+ },
+ "ENUMDNEM": {
+ "description": "Enumeration done mask",
+ "offset": 13,
+ "size": 1
+ },
+ "ISOODRPM": {
+ "description": "Isochronous OUT packet dropped interrupt\n mask",
+ "offset": 14,
+ "size": 1
+ },
+ "EOPFM": {
+ "description": "End of periodic frame interrupt\n mask",
+ "offset": 15,
+ "size": 1
+ },
+ "EPMISM": {
+ "description": "Endpoint mismatch interrupt\n mask",
+ "offset": 17,
+ "size": 1
+ },
+ "IEPINT": {
+ "description": "IN endpoints interrupt\n mask",
+ "offset": 18,
+ "size": 1
+ },
+ "OEPINT": {
+ "description": "OUT endpoints interrupt\n mask",
+ "offset": 19,
+ "size": 1
+ },
+ "IISOIXFRM": {
+ "description": "Incomplete isochronous IN transfer\n mask",
+ "offset": 20,
+ "size": 1
+ },
+ "IPXFRM_IISOOXFRM": {
+ "description": "Incomplete periodic transfer mask(Host\n mode)/Incomplete isochronous OUT transfer mask(Device\n mode)",
+ "offset": 21,
+ "size": 1
+ },
+ "PRTIM": {
+ "description": "Host port interrupt mask",
+ "offset": 24,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HCIM": {
+ "description": "Host channels interrupt\n mask",
+ "offset": 25,
+ "size": 1
+ },
+ "PTXFEM": {
+ "description": "Periodic TxFIFO empty mask",
+ "offset": 26,
+ "size": 1
+ },
+ "CIDSCHGM": {
+ "description": "Connector ID status change\n mask",
+ "offset": 28,
+ "size": 1
+ },
+ "DISCINT": {
+ "description": "Disconnect detected interrupt\n mask",
+ "offset": 29,
+ "size": 1
+ },
+ "SRQIM": {
+ "description": "Session request/new session detected\n interrupt mask",
+ "offset": 30,
+ "size": 1
+ },
+ "WUIM": {
+ "description": "Resume/remote wakeup detected interrupt\n mask",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_GRXSTSR_Device": {
+ "description": "OTG_FS Receive status debug read(Device\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 0,
+ "size": 4
+ },
+ "BCNT": {
+ "description": "Byte count",
+ "offset": 4,
+ "size": 11
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 15,
+ "size": 2
+ },
+ "PKTSTS": {
+ "description": "Packet status",
+ "offset": 17,
+ "size": 4
+ },
+ "FRMNUM": {
+ "description": "Frame number",
+ "offset": 21,
+ "size": 4
+ }
+ }
+ }
+ },
+ "FS_GRXSTSR_Host": {
+ "description": "OTG_FS Receive status debug read(Host\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 0,
+ "size": 4
+ },
+ "BCNT": {
+ "description": "Byte count",
+ "offset": 4,
+ "size": 11
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 15,
+ "size": 2
+ },
+ "PKTSTS": {
+ "description": "Packet status",
+ "offset": 17,
+ "size": 4
+ },
+ "FRMNUM": {
+ "description": "Frame number",
+ "offset": 21,
+ "size": 4
+ }
+ }
+ }
+ },
+ "FS_GRXFSIZ": {
+ "description": "OTG_FS Receive FIFO size register\n (OTG_FS_GRXFSIZ)",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 512,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RXFD": {
+ "description": "RxFIFO depth",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_GNPTXFSIZ_Device": {
+ "description": "OTG_FS non-periodic transmit FIFO size\n register (Device mode)",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 512,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TX0FSA": {
+ "description": "Endpoint 0 transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "TX0FD": {
+ "description": "Endpoint 0 TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_GNPTXFSIZ_Host": {
+ "description": "OTG_FS non-periodic transmit FIFO size\n register (Host mode)",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 512,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NPTXFSA": {
+ "description": "Non-periodic transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "NPTXFD": {
+ "description": "Non-periodic TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_GNPTXSTS": {
+ "description": "OTG_FS non-periodic transmit FIFO/queue\n status register (OTG_FS_GNPTXSTS)",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 524800,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "NPTXFSAV": {
+ "description": "Non-periodic TxFIFO space\n available",
+ "offset": 0,
+ "size": 16
+ },
+ "NPTQXSAV": {
+ "description": "Non-periodic transmit request queue\n space available",
+ "offset": 16,
+ "size": 8
+ },
+ "NPTXQTOP": {
+ "description": "Top of the non-periodic transmit request\n queue",
+ "offset": 24,
+ "size": 7
+ }
+ }
+ }
+ },
+ "FS_GCCFG": {
+ "description": "OTG_FS general core configuration register\n (OTG_FS_GCCFG)",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PWRDWN": {
+ "description": "Power down",
+ "offset": 16,
+ "size": 1
+ },
+ "VBUSASEN": {
+ "description": "Enable the VBUS sensing\n device",
+ "offset": 18,
+ "size": 1
+ },
+ "VBUSBSEN": {
+ "description": "Enable the VBUS sensing\n device",
+ "offset": 19,
+ "size": 1
+ },
+ "SOFOUTEN": {
+ "description": "SOF output enable",
+ "offset": 20,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_CID": {
+ "description": "core ID register",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 4096,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRODUCT_ID": {
+ "description": "Product ID field",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "FS_HPTXFSIZ": {
+ "description": "OTG_FS Host periodic transmit FIFO size\n register (OTG_FS_HPTXFSIZ)",
+ "offset": 256,
+ "size": 32,
+ "reset_value": 33555968,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PTXSA": {
+ "description": "Host periodic TxFIFO start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "PTXFSIZ": {
+ "description": "Host periodic TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_DIEPTXF1": {
+ "description": "OTG_FS device IN endpoint transmit FIFO size\n register (OTG_FS_DIEPTXF2)",
+ "offset": 260,
+ "size": 32,
+ "reset_value": 33555456,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INEPTXSA": {
+ "description": "IN endpoint FIFO2 transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "INEPTXFD": {
+ "description": "IN endpoint TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_DIEPTXF2": {
+ "description": "OTG_FS device IN endpoint transmit FIFO size\n register (OTG_FS_DIEPTXF3)",
+ "offset": 264,
+ "size": 32,
+ "reset_value": 33555456,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INEPTXSA": {
+ "description": "IN endpoint FIFO3 transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "INEPTXFD": {
+ "description": "IN endpoint TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_DIEPTXF3": {
+ "description": "OTG_FS device IN endpoint transmit FIFO size\n register (OTG_FS_DIEPTXF4)",
+ "offset": 268,
+ "size": 32,
+ "reset_value": 33555456,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INEPTXSA": {
+ "description": "IN endpoint FIFO4 transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "INEPTXFD": {
+ "description": "IN endpoint TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "CRC": {
+ "description": "Cryptographic processor",
+ "children": {
+ "registers": {
+ "DR": {
+ "description": "Data register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DR": {
+ "description": "Data Register",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "IDR": {
+ "description": "Independent Data register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IDR": {
+ "description": "Independent Data register",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "CR": {
+ "description": "Control register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "CR": {
+ "description": "Control regidter",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "Ethernet_DMA": {
+ "description": "Ethernet: DMA controller operation",
+ "children": {
+ "registers": {
+ "DMABMR": {
+ "description": "Ethernet DMA bus mode register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 8449,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SR": {
+ "description": "SR",
+ "offset": 0,
+ "size": 1
+ },
+ "DA": {
+ "description": "DA",
+ "offset": 1,
+ "size": 1
+ },
+ "DSL": {
+ "description": "DSL",
+ "offset": 2,
+ "size": 5
+ },
+ "EDFE": {
+ "description": "EDFE",
+ "offset": 7,
+ "size": 1
+ },
+ "PBL": {
+ "description": "PBL",
+ "offset": 8,
+ "size": 6
+ },
+ "RTPR": {
+ "description": "RTPR",
+ "offset": 14,
+ "size": 2
+ },
+ "FB": {
+ "description": "FB",
+ "offset": 16,
+ "size": 1
+ },
+ "RDP": {
+ "description": "RDP",
+ "offset": 17,
+ "size": 6
+ },
+ "USP": {
+ "description": "USP",
+ "offset": 23,
+ "size": 1
+ },
+ "FPM": {
+ "description": "FPM",
+ "offset": 24,
+ "size": 1
+ },
+ "AAB": {
+ "description": "AAB",
+ "offset": 25,
+ "size": 1
+ },
+ "MB": {
+ "description": "MB",
+ "offset": 26,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DMATPDR": {
+ "description": "Ethernet DMA transmit poll demand\n register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TPD": {
+ "description": "TPD",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DMARPDR": {
+ "description": "EHERNET DMA receive poll demand\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RPD": {
+ "description": "RPD",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DMARDLAR": {
+ "description": "Ethernet DMA receive descriptor list address\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SRL": {
+ "description": "SRL",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DMATDLAR": {
+ "description": "Ethernet DMA transmit descriptor list\n address register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "STL": {
+ "description": "STL",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DMASR": {
+ "description": "Ethernet DMA status register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TS": {
+ "description": "TS",
+ "offset": 0,
+ "size": 1
+ },
+ "TPSS": {
+ "description": "TPSS",
+ "offset": 1,
+ "size": 1
+ },
+ "TBUS": {
+ "description": "TBUS",
+ "offset": 2,
+ "size": 1
+ },
+ "TJTS": {
+ "description": "TJTS",
+ "offset": 3,
+ "size": 1
+ },
+ "ROS": {
+ "description": "ROS",
+ "offset": 4,
+ "size": 1
+ },
+ "TUS": {
+ "description": "TUS",
+ "offset": 5,
+ "size": 1
+ },
+ "RS": {
+ "description": "RS",
+ "offset": 6,
+ "size": 1
+ },
+ "RBUS": {
+ "description": "RBUS",
+ "offset": 7,
+ "size": 1
+ },
+ "RPSS": {
+ "description": "RPSS",
+ "offset": 8,
+ "size": 1
+ },
+ "PWTS": {
+ "description": "PWTS",
+ "offset": 9,
+ "size": 1
+ },
+ "ETS": {
+ "description": "ETS",
+ "offset": 10,
+ "size": 1
+ },
+ "FBES": {
+ "description": "FBES",
+ "offset": 13,
+ "size": 1
+ },
+ "ERS": {
+ "description": "ERS",
+ "offset": 14,
+ "size": 1
+ },
+ "AIS": {
+ "description": "AIS",
+ "offset": 15,
+ "size": 1
+ },
+ "NIS": {
+ "description": "NIS",
+ "offset": 16,
+ "size": 1
+ },
+ "RPS": {
+ "description": "RPS",
+ "offset": 17,
+ "size": 3,
+ "access": "read-only"
+ },
+ "TPS": {
+ "description": "TPS",
+ "offset": 20,
+ "size": 3,
+ "access": "read-only"
+ },
+ "EBS": {
+ "description": "EBS",
+ "offset": 23,
+ "size": 3,
+ "access": "read-only"
+ },
+ "MMCS": {
+ "description": "MMCS",
+ "offset": 27,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PMTS": {
+ "description": "PMTS",
+ "offset": 28,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TSTS": {
+ "description": "TSTS",
+ "offset": 29,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "DMAOMR": {
+ "description": "Ethernet DMA operation mode\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SR": {
+ "description": "SR",
+ "offset": 1,
+ "size": 1
+ },
+ "OSF": {
+ "description": "OSF",
+ "offset": 2,
+ "size": 1
+ },
+ "RTC": {
+ "description": "RTC",
+ "offset": 3,
+ "size": 2
+ },
+ "FUGF": {
+ "description": "FUGF",
+ "offset": 6,
+ "size": 1
+ },
+ "FEF": {
+ "description": "FEF",
+ "offset": 7,
+ "size": 1
+ },
+ "ST": {
+ "description": "ST",
+ "offset": 13,
+ "size": 1
+ },
+ "TTC": {
+ "description": "TTC",
+ "offset": 14,
+ "size": 3
+ },
+ "FTF": {
+ "description": "FTF",
+ "offset": 20,
+ "size": 1
+ },
+ "TSF": {
+ "description": "TSF",
+ "offset": 21,
+ "size": 1
+ },
+ "DFRF": {
+ "description": "DFRF",
+ "offset": 24,
+ "size": 1
+ },
+ "RSF": {
+ "description": "RSF",
+ "offset": 25,
+ "size": 1
+ },
+ "DTCEFD": {
+ "description": "DTCEFD",
+ "offset": 26,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DMAIER": {
+ "description": "Ethernet DMA interrupt enable\n register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIE": {
+ "description": "TIE",
+ "offset": 0,
+ "size": 1
+ },
+ "TPSIE": {
+ "description": "TPSIE",
+ "offset": 1,
+ "size": 1
+ },
+ "TBUIE": {
+ "description": "TBUIE",
+ "offset": 2,
+ "size": 1
+ },
+ "TJTIE": {
+ "description": "TJTIE",
+ "offset": 3,
+ "size": 1
+ },
+ "ROIE": {
+ "description": "ROIE",
+ "offset": 4,
+ "size": 1
+ },
+ "TUIE": {
+ "description": "TUIE",
+ "offset": 5,
+ "size": 1
+ },
+ "RIE": {
+ "description": "RIE",
+ "offset": 6,
+ "size": 1
+ },
+ "RBUIE": {
+ "description": "RBUIE",
+ "offset": 7,
+ "size": 1
+ },
+ "RPSIE": {
+ "description": "RPSIE",
+ "offset": 8,
+ "size": 1
+ },
+ "RWTIE": {
+ "description": "RWTIE",
+ "offset": 9,
+ "size": 1
+ },
+ "ETIE": {
+ "description": "ETIE",
+ "offset": 10,
+ "size": 1
+ },
+ "FBEIE": {
+ "description": "FBEIE",
+ "offset": 13,
+ "size": 1
+ },
+ "ERIE": {
+ "description": "ERIE",
+ "offset": 14,
+ "size": 1
+ },
+ "AISE": {
+ "description": "AISE",
+ "offset": 15,
+ "size": 1
+ },
+ "NISE": {
+ "description": "NISE",
+ "offset": 16,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DMAMFBOCR": {
+ "description": "Ethernet DMA missed frame and buffer\n overflow counter register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MFC": {
+ "description": "MFC",
+ "offset": 0,
+ "size": 16
+ },
+ "OMFC": {
+ "description": "OMFC",
+ "offset": 16,
+ "size": 1
+ },
+ "MFA": {
+ "description": "MFA",
+ "offset": 17,
+ "size": 11
+ },
+ "OFOC": {
+ "description": "OFOC",
+ "offset": 28,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DMARSWTR": {
+ "description": "Ethernet DMA receive status watchdog timer\n register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RSWTC": {
+ "description": "RSWTC",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "DMACHTDR": {
+ "description": "Ethernet DMA current host transmit\n descriptor register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "HTDAP": {
+ "description": "HTDAP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DMACHRDR": {
+ "description": "Ethernet DMA current host receive descriptor\n register",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "HRDAP": {
+ "description": "HRDAP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DMACHTBAR": {
+ "description": "Ethernet DMA current host transmit buffer\n address register",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "HTBAP": {
+ "description": "HTBAP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DMACHRBAR": {
+ "description": "Ethernet DMA current host receive buffer\n address register",
+ "offset": 84,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "HRBAP": {
+ "description": "HRBAP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "C_ADC": {
+ "description": "Common ADC registers",
+ "children": {
+ "registers": {
+ "CSR": {
+ "description": "ADC Common status register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "OVR3": {
+ "description": "Overrun flag of ADC3",
+ "offset": 21,
+ "size": 1
+ },
+ "STRT3": {
+ "description": "Regular channel Start flag of ADC\n 3",
+ "offset": 20,
+ "size": 1
+ },
+ "JSTRT3": {
+ "description": "Injected channel Start flag of ADC\n 3",
+ "offset": 19,
+ "size": 1
+ },
+ "JEOC3": {
+ "description": "Injected channel end of conversion of\n ADC 3",
+ "offset": 18,
+ "size": 1
+ },
+ "EOC3": {
+ "description": "End of conversion of ADC 3",
+ "offset": 17,
+ "size": 1
+ },
+ "AWD3": {
+ "description": "Analog watchdog flag of ADC\n 3",
+ "offset": 16,
+ "size": 1
+ },
+ "OVR2": {
+ "description": "Overrun flag of ADC 2",
+ "offset": 13,
+ "size": 1
+ },
+ "STRT2": {
+ "description": "Regular channel Start flag of ADC\n 2",
+ "offset": 12,
+ "size": 1
+ },
+ "JSTRT2": {
+ "description": "Injected channel Start flag of ADC\n 2",
+ "offset": 11,
+ "size": 1
+ },
+ "JEOC2": {
+ "description": "Injected channel end of conversion of\n ADC 2",
+ "offset": 10,
+ "size": 1
+ },
+ "EOC2": {
+ "description": "End of conversion of ADC 2",
+ "offset": 9,
+ "size": 1
+ },
+ "AWD2": {
+ "description": "Analog watchdog flag of ADC\n 2",
+ "offset": 8,
+ "size": 1
+ },
+ "OVR1": {
+ "description": "Overrun flag of ADC 1",
+ "offset": 5,
+ "size": 1
+ },
+ "STRT1": {
+ "description": "Regular channel Start flag of ADC\n 1",
+ "offset": 4,
+ "size": 1
+ },
+ "JSTRT1": {
+ "description": "Injected channel Start flag of ADC\n 1",
+ "offset": 3,
+ "size": 1
+ },
+ "JEOC1": {
+ "description": "Injected channel end of conversion of\n ADC 1",
+ "offset": 2,
+ "size": 1
+ },
+ "EOC1": {
+ "description": "End of conversion of ADC 1",
+ "offset": 1,
+ "size": 1
+ },
+ "AWD1": {
+ "description": "Analog watchdog flag of ADC\n 1",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCR": {
+ "description": "ADC common control register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TSVREFE": {
+ "description": "Temperature sensor and VREFINT\n enable",
+ "offset": 23,
+ "size": 1
+ },
+ "VBATE": {
+ "description": "VBAT enable",
+ "offset": 22,
+ "size": 1
+ },
+ "ADCPRE": {
+ "description": "ADC prescaler",
+ "offset": 16,
+ "size": 2
+ },
+ "DMA": {
+ "description": "Direct memory access mode for multi ADC\n mode",
+ "offset": 14,
+ "size": 2
+ },
+ "DDS": {
+ "description": "DMA disable selection for multi-ADC\n mode",
+ "offset": 13,
+ "size": 1
+ },
+ "DELAY": {
+ "description": "Delay between 2 sampling\n phases",
+ "offset": 8,
+ "size": 4
+ },
+ "MULT": {
+ "description": "Multi ADC mode selection",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "CDR": {
+ "description": "ADC common regular data register for dual\n and triple modes",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DATA2": {
+ "description": "2nd data item of a pair of regular\n conversions",
+ "offset": 16,
+ "size": 16
+ },
+ "DATA1": {
+ "description": "1st data item of a pair of regular\n conversions",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "TIM1": {
+ "description": "Advanced-timers",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CKD": {
+ "description": "Clock division",
+ "offset": 8,
+ "size": 2
+ },
+ "ARPE": {
+ "description": "Auto-reload preload enable",
+ "offset": 7,
+ "size": 1
+ },
+ "CMS": {
+ "description": "Center-aligned mode\n selection",
+ "offset": 5,
+ "size": 2
+ },
+ "DIR": {
+ "description": "Direction",
+ "offset": 4,
+ "size": 1
+ },
+ "OPM": {
+ "description": "One-pulse mode",
+ "offset": 3,
+ "size": 1
+ },
+ "URS": {
+ "description": "Update request source",
+ "offset": 2,
+ "size": 1
+ },
+ "UDIS": {
+ "description": "Update disable",
+ "offset": 1,
+ "size": 1
+ },
+ "CEN": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OIS4": {
+ "description": "Output Idle state 4",
+ "offset": 14,
+ "size": 1
+ },
+ "OIS3N": {
+ "description": "Output Idle state 3",
+ "offset": 13,
+ "size": 1
+ },
+ "OIS3": {
+ "description": "Output Idle state 3",
+ "offset": 12,
+ "size": 1
+ },
+ "OIS2N": {
+ "description": "Output Idle state 2",
+ "offset": 11,
+ "size": 1
+ },
+ "OIS2": {
+ "description": "Output Idle state 2",
+ "offset": 10,
+ "size": 1
+ },
+ "OIS1N": {
+ "description": "Output Idle state 1",
+ "offset": 9,
+ "size": 1
+ },
+ "OIS1": {
+ "description": "Output Idle state 1",
+ "offset": 8,
+ "size": 1
+ },
+ "TI1S": {
+ "description": "TI1 selection",
+ "offset": 7,
+ "size": 1
+ },
+ "MMS": {
+ "description": "Master mode selection",
+ "offset": 4,
+ "size": 3
+ },
+ "CCDS": {
+ "description": "Capture/compare DMA\n selection",
+ "offset": 3,
+ "size": 1
+ },
+ "CCUS": {
+ "description": "Capture/compare control update\n selection",
+ "offset": 2,
+ "size": 1
+ },
+ "CCPC": {
+ "description": "Capture/compare preloaded\n control",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SMCR": {
+ "description": "slave mode control register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ETP": {
+ "description": "External trigger polarity",
+ "offset": 15,
+ "size": 1
+ },
+ "ECE": {
+ "description": "External clock enable",
+ "offset": 14,
+ "size": 1
+ },
+ "ETPS": {
+ "description": "External trigger prescaler",
+ "offset": 12,
+ "size": 2
+ },
+ "ETF": {
+ "description": "External trigger filter",
+ "offset": 8,
+ "size": 4
+ },
+ "MSM": {
+ "description": "Master/Slave mode",
+ "offset": 7,
+ "size": 1
+ },
+ "TS": {
+ "description": "Trigger selection",
+ "offset": 4,
+ "size": 3
+ },
+ "SMS": {
+ "description": "Slave mode selection",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "DIER": {
+ "description": "DMA/Interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TDE": {
+ "description": "Trigger DMA request enable",
+ "offset": 14,
+ "size": 1
+ },
+ "COMDE": {
+ "description": "COM DMA request enable",
+ "offset": 13,
+ "size": 1
+ },
+ "CC4DE": {
+ "description": "Capture/Compare 4 DMA request\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3DE": {
+ "description": "Capture/Compare 3 DMA request\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "CC2DE": {
+ "description": "Capture/Compare 2 DMA request\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC1DE": {
+ "description": "Capture/Compare 1 DMA request\n enable",
+ "offset": 9,
+ "size": 1
+ },
+ "UDE": {
+ "description": "Update DMA request enable",
+ "offset": 8,
+ "size": 1
+ },
+ "TIE": {
+ "description": "Trigger interrupt enable",
+ "offset": 6,
+ "size": 1
+ },
+ "CC4IE": {
+ "description": "Capture/Compare 4 interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3IE": {
+ "description": "Capture/Compare 3 interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2IE": {
+ "description": "Capture/Compare 2 interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IE": {
+ "description": "Capture/Compare 1 interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "UIE": {
+ "description": "Update interrupt enable",
+ "offset": 0,
+ "size": 1
+ },
+ "BIE": {
+ "description": "Break interrupt enable",
+ "offset": 7,
+ "size": 1
+ },
+ "COMIE": {
+ "description": "COM interrupt enable",
+ "offset": 5,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC4OF": {
+ "description": "Capture/Compare 4 overcapture\n flag",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3OF": {
+ "description": "Capture/Compare 3 overcapture\n flag",
+ "offset": 11,
+ "size": 1
+ },
+ "CC2OF": {
+ "description": "Capture/compare 2 overcapture\n flag",
+ "offset": 10,
+ "size": 1
+ },
+ "CC1OF": {
+ "description": "Capture/Compare 1 overcapture\n flag",
+ "offset": 9,
+ "size": 1
+ },
+ "BIF": {
+ "description": "Break interrupt flag",
+ "offset": 7,
+ "size": 1
+ },
+ "TIF": {
+ "description": "Trigger interrupt flag",
+ "offset": 6,
+ "size": 1
+ },
+ "COMIF": {
+ "description": "COM interrupt flag",
+ "offset": 5,
+ "size": 1
+ },
+ "CC4IF": {
+ "description": "Capture/Compare 4 interrupt\n flag",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3IF": {
+ "description": "Capture/Compare 3 interrupt\n flag",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2IF": {
+ "description": "Capture/Compare 2 interrupt\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IF": {
+ "description": "Capture/compare 1 interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "UIF": {
+ "description": "Update interrupt flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EGR": {
+ "description": "event generation register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "BG": {
+ "description": "Break generation",
+ "offset": 7,
+ "size": 1
+ },
+ "TG": {
+ "description": "Trigger generation",
+ "offset": 6,
+ "size": 1
+ },
+ "COMG": {
+ "description": "Capture/Compare control update\n generation",
+ "offset": 5,
+ "size": 1
+ },
+ "CC4G": {
+ "description": "Capture/compare 4\n generation",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3G": {
+ "description": "Capture/compare 3\n generation",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2G": {
+ "description": "Capture/compare 2\n generation",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1G": {
+ "description": "Capture/compare 1\n generation",
+ "offset": 1,
+ "size": 1
+ },
+ "UG": {
+ "description": "Update generation",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Output": {
+ "description": "capture/compare mode register 1 (output\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OC2CE": {
+ "description": "Output Compare 2 clear\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "OC2M": {
+ "description": "Output Compare 2 mode",
+ "offset": 12,
+ "size": 3
+ },
+ "OC2PE": {
+ "description": "Output Compare 2 preload\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "OC2FE": {
+ "description": "Output Compare 2 fast\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC2S": {
+ "description": "Capture/Compare 2\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "OC1CE": {
+ "description": "Output Compare 1 clear\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "OC1M": {
+ "description": "Output Compare 1 mode",
+ "offset": 4,
+ "size": 3
+ },
+ "OC1PE": {
+ "description": "Output Compare 1 preload\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "OC1FE": {
+ "description": "Output Compare 1 fast\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR1_Input": {
+ "description": "capture/compare mode register 1 (input\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC2F": {
+ "description": "Input capture 2 filter",
+ "offset": 12,
+ "size": 4
+ },
+ "IC2PCS": {
+ "description": "Input capture 2 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC2S": {
+ "description": "Capture/Compare 2\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC1F": {
+ "description": "Input capture 1 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "ICPCS": {
+ "description": "Input capture 1 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR2_Output": {
+ "description": "capture/compare mode register 2 (output\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OC4CE": {
+ "description": "Output compare 4 clear\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "OC4M": {
+ "description": "Output compare 4 mode",
+ "offset": 12,
+ "size": 3
+ },
+ "OC4PE": {
+ "description": "Output compare 4 preload\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "OC4FE": {
+ "description": "Output compare 4 fast\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC4S": {
+ "description": "Capture/Compare 4\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "OC3CE": {
+ "description": "Output compare 3 clear\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "OC3M": {
+ "description": "Output compare 3 mode",
+ "offset": 4,
+ "size": 3
+ },
+ "OC3PE": {
+ "description": "Output compare 3 preload\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "OC3FE": {
+ "description": "Output compare 3 fast\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC3S": {
+ "description": "Capture/Compare 3\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR2_Input": {
+ "description": "capture/compare mode register 2 (input\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC4F": {
+ "description": "Input capture 4 filter",
+ "offset": 12,
+ "size": 4
+ },
+ "IC4PSC": {
+ "description": "Input capture 4 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC4S": {
+ "description": "Capture/Compare 4\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC3F": {
+ "description": "Input capture 3 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "IC3PSC": {
+ "description": "Input capture 3 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC3S": {
+ "description": "Capture/compare 3\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCER": {
+ "description": "capture/compare enable\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC4P": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 13,
+ "size": 1
+ },
+ "CC4E": {
+ "description": "Capture/Compare 4 output\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3NP": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 11,
+ "size": 1
+ },
+ "CC3NE": {
+ "description": "Capture/Compare 3 complementary output\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC3P": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 9,
+ "size": 1
+ },
+ "CC3E": {
+ "description": "Capture/Compare 3 output\n enable",
+ "offset": 8,
+ "size": 1
+ },
+ "CC2NP": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 7,
+ "size": 1
+ },
+ "CC2NE": {
+ "description": "Capture/Compare 2 complementary output\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "CC2P": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 5,
+ "size": 1
+ },
+ "CC2E": {
+ "description": "Capture/Compare 2 output\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC1NP": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 3,
+ "size": 1
+ },
+ "CC1NE": {
+ "description": "Capture/Compare 1 complementary output\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1P": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 1,
+ "size": 1
+ },
+ "CC1E": {
+ "description": "Capture/Compare 1 output\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNT": {
+ "description": "counter",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNT": {
+ "description": "counter value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "PSC": {
+ "description": "prescaler",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ARR": {
+ "description": "auto-reload register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARR": {
+ "description": "Auto-reload value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR1": {
+ "description": "capture/compare register 1",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR1": {
+ "description": "Capture/Compare 1 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR2": {
+ "description": "capture/compare register 2",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR2": {
+ "description": "Capture/Compare 2 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR3": {
+ "description": "capture/compare register 3",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR3": {
+ "description": "Capture/Compare value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR4": {
+ "description": "capture/compare register 4",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR4": {
+ "description": "Capture/Compare value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DCR": {
+ "description": "DMA control register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBL": {
+ "description": "DMA burst length",
+ "offset": 8,
+ "size": 5
+ },
+ "DBA": {
+ "description": "DMA base address",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "DMAR": {
+ "description": "DMA address for full transfer",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAB": {
+ "description": "DMA register for burst\n accesses",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "RCR": {
+ "description": "repetition counter register",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "REP": {
+ "description": "Repetition counter value",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "BDTR": {
+ "description": "break and dead-time register",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MOE": {
+ "description": "Main output enable",
+ "offset": 15,
+ "size": 1
+ },
+ "AOE": {
+ "description": "Automatic output enable",
+ "offset": 14,
+ "size": 1
+ },
+ "BKP": {
+ "description": "Break polarity",
+ "offset": 13,
+ "size": 1
+ },
+ "BKE": {
+ "description": "Break enable",
+ "offset": 12,
+ "size": 1
+ },
+ "OSSR": {
+ "description": "Off-state selection for Run\n mode",
+ "offset": 11,
+ "size": 1
+ },
+ "OSSI": {
+ "description": "Off-state selection for Idle\n mode",
+ "offset": 10,
+ "size": 1
+ },
+ "LOCK": {
+ "description": "Lock configuration",
+ "offset": 8,
+ "size": 2
+ },
+ "DTG": {
+ "description": "Dead-time generator setup",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "Ethernet_PTP": {
+ "description": "Ethernet: Precision time protocol",
+ "children": {
+ "registers": {
+ "PTPTSCR": {
+ "description": "Ethernet PTP time stamp control\n register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 8192,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TSE": {
+ "description": "TSE",
+ "offset": 0,
+ "size": 1
+ },
+ "TSFCU": {
+ "description": "TSFCU",
+ "offset": 1,
+ "size": 1
+ },
+ "TSPTPPSV2E": {
+ "description": "TSPTPPSV2E",
+ "offset": 10,
+ "size": 1
+ },
+ "TSSPTPOEFE": {
+ "description": "TSSPTPOEFE",
+ "offset": 11,
+ "size": 1
+ },
+ "TSSIPV6FE": {
+ "description": "TSSIPV6FE",
+ "offset": 12,
+ "size": 1
+ },
+ "TSSIPV4FE": {
+ "description": "TSSIPV4FE",
+ "offset": 13,
+ "size": 1
+ },
+ "TSSEME": {
+ "description": "TSSEME",
+ "offset": 14,
+ "size": 1
+ },
+ "TSSMRME": {
+ "description": "TSSMRME",
+ "offset": 15,
+ "size": 1
+ },
+ "TSCNT": {
+ "description": "TSCNT",
+ "offset": 16,
+ "size": 2
+ },
+ "TSPFFMAE": {
+ "description": "TSPFFMAE",
+ "offset": 18,
+ "size": 1
+ },
+ "TSSTI": {
+ "description": "TSSTI",
+ "offset": 2,
+ "size": 1
+ },
+ "TSSTU": {
+ "description": "TSSTU",
+ "offset": 3,
+ "size": 1
+ },
+ "TSITE": {
+ "description": "TSITE",
+ "offset": 4,
+ "size": 1
+ },
+ "TTSARU": {
+ "description": "TTSARU",
+ "offset": 5,
+ "size": 1
+ },
+ "TSSARFE": {
+ "description": "TSSARFE",
+ "offset": 8,
+ "size": 1
+ },
+ "TSSSR": {
+ "description": "TSSSR",
+ "offset": 9,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PTPSSIR": {
+ "description": "Ethernet PTP subsecond increment\n register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "STSSI": {
+ "description": "STSSI",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "PTPTSHR": {
+ "description": "Ethernet PTP time stamp high\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "STS": {
+ "description": "STS",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "PTPTSLR": {
+ "description": "Ethernet PTP time stamp low\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "STSS": {
+ "description": "STSS",
+ "offset": 0,
+ "size": 31
+ },
+ "STPNS": {
+ "description": "STPNS",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PTPTSHUR": {
+ "description": "Ethernet PTP time stamp high update\n register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TSUS": {
+ "description": "TSUS",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "PTPTSLUR": {
+ "description": "Ethernet PTP time stamp low update\n register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TSUSS": {
+ "description": "TSUSS",
+ "offset": 0,
+ "size": 31
+ },
+ "TSUPNS": {
+ "description": "TSUPNS",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PTPTSAR": {
+ "description": "Ethernet PTP time stamp addend\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TSA": {
+ "description": "TSA",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "PTPTTHR": {
+ "description": "Ethernet PTP target time high\n register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TTSH": {
+ "description": "0",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "PTPTTLR": {
+ "description": "Ethernet PTP target time low\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TTSL": {
+ "description": "TTSL",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "PTPTSSR": {
+ "description": "Ethernet PTP time stamp status\n register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "TSSO": {
+ "description": "TSSO",
+ "offset": 0,
+ "size": 1
+ },
+ "TSTTR": {
+ "description": "TSTTR",
+ "offset": 1,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PTPPPSCR": {
+ "description": "Ethernet PTP PPS control\n register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "TSSO": {
+ "description": "TSSO",
+ "offset": 0,
+ "size": 1
+ },
+ "TSTTR": {
+ "description": "TSTTR",
+ "offset": 1,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "TIM2": {
+ "description": "General purpose timers",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CKD": {
+ "description": "Clock division",
+ "offset": 8,
+ "size": 2
+ },
+ "ARPE": {
+ "description": "Auto-reload preload enable",
+ "offset": 7,
+ "size": 1
+ },
+ "CMS": {
+ "description": "Center-aligned mode\n selection",
+ "offset": 5,
+ "size": 2
+ },
+ "DIR": {
+ "description": "Direction",
+ "offset": 4,
+ "size": 1
+ },
+ "OPM": {
+ "description": "One-pulse mode",
+ "offset": 3,
+ "size": 1
+ },
+ "URS": {
+ "description": "Update request source",
+ "offset": 2,
+ "size": 1
+ },
+ "UDIS": {
+ "description": "Update disable",
+ "offset": 1,
+ "size": 1
+ },
+ "CEN": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TI1S": {
+ "description": "TI1 selection",
+ "offset": 7,
+ "size": 1
+ },
+ "MMS": {
+ "description": "Master mode selection",
+ "offset": 4,
+ "size": 3
+ },
+ "CCDS": {
+ "description": "Capture/compare DMA\n selection",
+ "offset": 3,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SMCR": {
+ "description": "slave mode control register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ETP": {
+ "description": "External trigger polarity",
+ "offset": 15,
+ "size": 1
+ },
+ "ECE": {
+ "description": "External clock enable",
+ "offset": 14,
+ "size": 1
+ },
+ "ETPS": {
+ "description": "External trigger prescaler",
+ "offset": 12,
+ "size": 2
+ },
+ "ETF": {
+ "description": "External trigger filter",
+ "offset": 8,
+ "size": 4
+ },
+ "MSM": {
+ "description": "Master/Slave mode",
+ "offset": 7,
+ "size": 1
+ },
+ "TS": {
+ "description": "Trigger selection",
+ "offset": 4,
+ "size": 3
+ },
+ "SMS": {
+ "description": "Slave mode selection",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "DIER": {
+ "description": "DMA/Interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TDE": {
+ "description": "Trigger DMA request enable",
+ "offset": 14,
+ "size": 1
+ },
+ "CC4DE": {
+ "description": "Capture/Compare 4 DMA request\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3DE": {
+ "description": "Capture/Compare 3 DMA request\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "CC2DE": {
+ "description": "Capture/Compare 2 DMA request\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC1DE": {
+ "description": "Capture/Compare 1 DMA request\n enable",
+ "offset": 9,
+ "size": 1
+ },
+ "UDE": {
+ "description": "Update DMA request enable",
+ "offset": 8,
+ "size": 1
+ },
+ "TIE": {
+ "description": "Trigger interrupt enable",
+ "offset": 6,
+ "size": 1
+ },
+ "CC4IE": {
+ "description": "Capture/Compare 4 interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3IE": {
+ "description": "Capture/Compare 3 interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2IE": {
+ "description": "Capture/Compare 2 interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IE": {
+ "description": "Capture/Compare 1 interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "UIE": {
+ "description": "Update interrupt enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC4OF": {
+ "description": "Capture/Compare 4 overcapture\n flag",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3OF": {
+ "description": "Capture/Compare 3 overcapture\n flag",
+ "offset": 11,
+ "size": 1
+ },
+ "CC2OF": {
+ "description": "Capture/compare 2 overcapture\n flag",
+ "offset": 10,
+ "size": 1
+ },
+ "CC1OF": {
+ "description": "Capture/Compare 1 overcapture\n flag",
+ "offset": 9,
+ "size": 1
+ },
+ "TIF": {
+ "description": "Trigger interrupt flag",
+ "offset": 6,
+ "size": 1
+ },
+ "CC4IF": {
+ "description": "Capture/Compare 4 interrupt\n flag",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3IF": {
+ "description": "Capture/Compare 3 interrupt\n flag",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2IF": {
+ "description": "Capture/Compare 2 interrupt\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IF": {
+ "description": "Capture/compare 1 interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "UIF": {
+ "description": "Update interrupt flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EGR": {
+ "description": "event generation register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "TG": {
+ "description": "Trigger generation",
+ "offset": 6,
+ "size": 1
+ },
+ "CC4G": {
+ "description": "Capture/compare 4\n generation",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3G": {
+ "description": "Capture/compare 3\n generation",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2G": {
+ "description": "Capture/compare 2\n generation",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1G": {
+ "description": "Capture/compare 1\n generation",
+ "offset": 1,
+ "size": 1
+ },
+ "UG": {
+ "description": "Update generation",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Output": {
+ "description": "capture/compare mode register 1 (output\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OC2CE": {
+ "description": "OC2CE",
+ "offset": 15,
+ "size": 1
+ },
+ "OC2M": {
+ "description": "OC2M",
+ "offset": 12,
+ "size": 3
+ },
+ "OC2PE": {
+ "description": "OC2PE",
+ "offset": 11,
+ "size": 1
+ },
+ "OC2FE": {
+ "description": "OC2FE",
+ "offset": 10,
+ "size": 1
+ },
+ "CC2S": {
+ "description": "CC2S",
+ "offset": 8,
+ "size": 2
+ },
+ "OC1CE": {
+ "description": "OC1CE",
+ "offset": 7,
+ "size": 1
+ },
+ "OC1M": {
+ "description": "OC1M",
+ "offset": 4,
+ "size": 3
+ },
+ "OC1PE": {
+ "description": "OC1PE",
+ "offset": 3,
+ "size": 1
+ },
+ "OC1FE": {
+ "description": "OC1FE",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1S": {
+ "description": "CC1S",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR1_Input": {
+ "description": "capture/compare mode register 1 (input\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC2F": {
+ "description": "Input capture 2 filter",
+ "offset": 12,
+ "size": 4
+ },
+ "IC2PCS": {
+ "description": "Input capture 2 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC2S": {
+ "description": "Capture/Compare 2\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC1F": {
+ "description": "Input capture 1 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "ICPCS": {
+ "description": "Input capture 1 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR2_Output": {
+ "description": "capture/compare mode register 2 (output\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "O24CE": {
+ "description": "O24CE",
+ "offset": 15,
+ "size": 1
+ },
+ "OC4M": {
+ "description": "OC4M",
+ "offset": 12,
+ "size": 3
+ },
+ "OC4PE": {
+ "description": "OC4PE",
+ "offset": 11,
+ "size": 1
+ },
+ "OC4FE": {
+ "description": "OC4FE",
+ "offset": 10,
+ "size": 1
+ },
+ "CC4S": {
+ "description": "CC4S",
+ "offset": 8,
+ "size": 2
+ },
+ "OC3CE": {
+ "description": "OC3CE",
+ "offset": 7,
+ "size": 1
+ },
+ "OC3M": {
+ "description": "OC3M",
+ "offset": 4,
+ "size": 3
+ },
+ "OC3PE": {
+ "description": "OC3PE",
+ "offset": 3,
+ "size": 1
+ },
+ "OC3FE": {
+ "description": "OC3FE",
+ "offset": 2,
+ "size": 1
+ },
+ "CC3S": {
+ "description": "CC3S",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR2_Input": {
+ "description": "capture/compare mode register 2 (input\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC4F": {
+ "description": "Input capture 4 filter",
+ "offset": 12,
+ "size": 4
+ },
+ "IC4PSC": {
+ "description": "Input capture 4 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC4S": {
+ "description": "Capture/Compare 4\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC3F": {
+ "description": "Input capture 3 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "IC3PSC": {
+ "description": "Input capture 3 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC3S": {
+ "description": "Capture/compare 3\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCER": {
+ "description": "capture/compare enable\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC4NP": {
+ "description": "Capture/Compare 4 output\n Polarity",
+ "offset": 15,
+ "size": 1
+ },
+ "CC4P": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 13,
+ "size": 1
+ },
+ "CC4E": {
+ "description": "Capture/Compare 4 output\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3NP": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 11,
+ "size": 1
+ },
+ "CC3P": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 9,
+ "size": 1
+ },
+ "CC3E": {
+ "description": "Capture/Compare 3 output\n enable",
+ "offset": 8,
+ "size": 1
+ },
+ "CC2NP": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 7,
+ "size": 1
+ },
+ "CC2P": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 5,
+ "size": 1
+ },
+ "CC2E": {
+ "description": "Capture/Compare 2 output\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC1NP": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 3,
+ "size": 1
+ },
+ "CC1P": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 1,
+ "size": 1
+ },
+ "CC1E": {
+ "description": "Capture/Compare 1 output\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNT": {
+ "description": "counter",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNT_H": {
+ "description": "High counter value",
+ "offset": 16,
+ "size": 16
+ },
+ "CNT_L": {
+ "description": "Low counter value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "PSC": {
+ "description": "prescaler",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ARR": {
+ "description": "auto-reload register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARR_H": {
+ "description": "High Auto-reload value",
+ "offset": 16,
+ "size": 16
+ },
+ "ARR_L": {
+ "description": "Low Auto-reload value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR1": {
+ "description": "capture/compare register 1",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR1_H": {
+ "description": "High Capture/Compare 1\n value",
+ "offset": 16,
+ "size": 16
+ },
+ "CCR1_L": {
+ "description": "Low Capture/Compare 1\n value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR2": {
+ "description": "capture/compare register 2",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR2_H": {
+ "description": "High Capture/Compare 2\n value",
+ "offset": 16,
+ "size": 16
+ },
+ "CCR2_L": {
+ "description": "Low Capture/Compare 2\n value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR3": {
+ "description": "capture/compare register 3",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR3_H": {
+ "description": "High Capture/Compare value",
+ "offset": 16,
+ "size": 16
+ },
+ "CCR3_L": {
+ "description": "Low Capture/Compare value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR4": {
+ "description": "capture/compare register 4",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR4_H": {
+ "description": "High Capture/Compare value",
+ "offset": 16,
+ "size": 16
+ },
+ "CCR4_L": {
+ "description": "Low Capture/Compare value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DCR": {
+ "description": "DMA control register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBL": {
+ "description": "DMA burst length",
+ "offset": 8,
+ "size": 5
+ },
+ "DBA": {
+ "description": "DMA base address",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "DMAR": {
+ "description": "DMA address for full transfer",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAB": {
+ "description": "DMA register for burst\n accesses",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OR": {
+ "description": "TIM5 option register",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ITR1_RMP": {
+ "description": "Timer Input 4 remap",
+ "offset": 10,
+ "size": 2
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "TIM3": {
+ "description": "General purpose timers",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CKD": {
+ "description": "Clock division",
+ "offset": 8,
+ "size": 2
+ },
+ "ARPE": {
+ "description": "Auto-reload preload enable",
+ "offset": 7,
+ "size": 1
+ },
+ "CMS": {
+ "description": "Center-aligned mode\n selection",
+ "offset": 5,
+ "size": 2
+ },
+ "DIR": {
+ "description": "Direction",
+ "offset": 4,
+ "size": 1
+ },
+ "OPM": {
+ "description": "One-pulse mode",
+ "offset": 3,
+ "size": 1
+ },
+ "URS": {
+ "description": "Update request source",
+ "offset": 2,
+ "size": 1
+ },
+ "UDIS": {
+ "description": "Update disable",
+ "offset": 1,
+ "size": 1
+ },
+ "CEN": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TI1S": {
+ "description": "TI1 selection",
+ "offset": 7,
+ "size": 1
+ },
+ "MMS": {
+ "description": "Master mode selection",
+ "offset": 4,
+ "size": 3
+ },
+ "CCDS": {
+ "description": "Capture/compare DMA\n selection",
+ "offset": 3,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SMCR": {
+ "description": "slave mode control register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ETP": {
+ "description": "External trigger polarity",
+ "offset": 15,
+ "size": 1
+ },
+ "ECE": {
+ "description": "External clock enable",
+ "offset": 14,
+ "size": 1
+ },
+ "ETPS": {
+ "description": "External trigger prescaler",
+ "offset": 12,
+ "size": 2
+ },
+ "ETF": {
+ "description": "External trigger filter",
+ "offset": 8,
+ "size": 4
+ },
+ "MSM": {
+ "description": "Master/Slave mode",
+ "offset": 7,
+ "size": 1
+ },
+ "TS": {
+ "description": "Trigger selection",
+ "offset": 4,
+ "size": 3
+ },
+ "SMS": {
+ "description": "Slave mode selection",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "DIER": {
+ "description": "DMA/Interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TDE": {
+ "description": "Trigger DMA request enable",
+ "offset": 14,
+ "size": 1
+ },
+ "CC4DE": {
+ "description": "Capture/Compare 4 DMA request\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3DE": {
+ "description": "Capture/Compare 3 DMA request\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "CC2DE": {
+ "description": "Capture/Compare 2 DMA request\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC1DE": {
+ "description": "Capture/Compare 1 DMA request\n enable",
+ "offset": 9,
+ "size": 1
+ },
+ "UDE": {
+ "description": "Update DMA request enable",
+ "offset": 8,
+ "size": 1
+ },
+ "TIE": {
+ "description": "Trigger interrupt enable",
+ "offset": 6,
+ "size": 1
+ },
+ "CC4IE": {
+ "description": "Capture/Compare 4 interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3IE": {
+ "description": "Capture/Compare 3 interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2IE": {
+ "description": "Capture/Compare 2 interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IE": {
+ "description": "Capture/Compare 1 interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "UIE": {
+ "description": "Update interrupt enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC4OF": {
+ "description": "Capture/Compare 4 overcapture\n flag",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3OF": {
+ "description": "Capture/Compare 3 overcapture\n flag",
+ "offset": 11,
+ "size": 1
+ },
+ "CC2OF": {
+ "description": "Capture/compare 2 overcapture\n flag",
+ "offset": 10,
+ "size": 1
+ },
+ "CC1OF": {
+ "description": "Capture/Compare 1 overcapture\n flag",
+ "offset": 9,
+ "size": 1
+ },
+ "TIF": {
+ "description": "Trigger interrupt flag",
+ "offset": 6,
+ "size": 1
+ },
+ "CC4IF": {
+ "description": "Capture/Compare 4 interrupt\n flag",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3IF": {
+ "description": "Capture/Compare 3 interrupt\n flag",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2IF": {
+ "description": "Capture/Compare 2 interrupt\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IF": {
+ "description": "Capture/compare 1 interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "UIF": {
+ "description": "Update interrupt flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EGR": {
+ "description": "event generation register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "TG": {
+ "description": "Trigger generation",
+ "offset": 6,
+ "size": 1
+ },
+ "CC4G": {
+ "description": "Capture/compare 4\n generation",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3G": {
+ "description": "Capture/compare 3\n generation",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2G": {
+ "description": "Capture/compare 2\n generation",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1G": {
+ "description": "Capture/compare 1\n generation",
+ "offset": 1,
+ "size": 1
+ },
+ "UG": {
+ "description": "Update generation",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Output": {
+ "description": "capture/compare mode register 1 (output\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OC2CE": {
+ "description": "OC2CE",
+ "offset": 15,
+ "size": 1
+ },
+ "OC2M": {
+ "description": "OC2M",
+ "offset": 12,
+ "size": 3
+ },
+ "OC2PE": {
+ "description": "OC2PE",
+ "offset": 11,
+ "size": 1
+ },
+ "OC2FE": {
+ "description": "OC2FE",
+ "offset": 10,
+ "size": 1
+ },
+ "CC2S": {
+ "description": "CC2S",
+ "offset": 8,
+ "size": 2
+ },
+ "OC1CE": {
+ "description": "OC1CE",
+ "offset": 7,
+ "size": 1
+ },
+ "OC1M": {
+ "description": "OC1M",
+ "offset": 4,
+ "size": 3
+ },
+ "OC1PE": {
+ "description": "OC1PE",
+ "offset": 3,
+ "size": 1
+ },
+ "OC1FE": {
+ "description": "OC1FE",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1S": {
+ "description": "CC1S",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR1_Input": {
+ "description": "capture/compare mode register 1 (input\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC2F": {
+ "description": "Input capture 2 filter",
+ "offset": 12,
+ "size": 4
+ },
+ "IC2PCS": {
+ "description": "Input capture 2 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC2S": {
+ "description": "Capture/Compare 2\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC1F": {
+ "description": "Input capture 1 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "ICPCS": {
+ "description": "Input capture 1 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR2_Output": {
+ "description": "capture/compare mode register 2 (output\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "O24CE": {
+ "description": "O24CE",
+ "offset": 15,
+ "size": 1
+ },
+ "OC4M": {
+ "description": "OC4M",
+ "offset": 12,
+ "size": 3
+ },
+ "OC4PE": {
+ "description": "OC4PE",
+ "offset": 11,
+ "size": 1
+ },
+ "OC4FE": {
+ "description": "OC4FE",
+ "offset": 10,
+ "size": 1
+ },
+ "CC4S": {
+ "description": "CC4S",
+ "offset": 8,
+ "size": 2
+ },
+ "OC3CE": {
+ "description": "OC3CE",
+ "offset": 7,
+ "size": 1
+ },
+ "OC3M": {
+ "description": "OC3M",
+ "offset": 4,
+ "size": 3
+ },
+ "OC3PE": {
+ "description": "OC3PE",
+ "offset": 3,
+ "size": 1
+ },
+ "OC3FE": {
+ "description": "OC3FE",
+ "offset": 2,
+ "size": 1
+ },
+ "CC3S": {
+ "description": "CC3S",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR2_Input": {
+ "description": "capture/compare mode register 2 (input\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC4F": {
+ "description": "Input capture 4 filter",
+ "offset": 12,
+ "size": 4
+ },
+ "IC4PSC": {
+ "description": "Input capture 4 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC4S": {
+ "description": "Capture/Compare 4\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC3F": {
+ "description": "Input capture 3 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "IC3PSC": {
+ "description": "Input capture 3 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC3S": {
+ "description": "Capture/compare 3\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCER": {
+ "description": "capture/compare enable\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC4NP": {
+ "description": "Capture/Compare 4 output\n Polarity",
+ "offset": 15,
+ "size": 1
+ },
+ "CC4P": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 13,
+ "size": 1
+ },
+ "CC4E": {
+ "description": "Capture/Compare 4 output\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3NP": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 11,
+ "size": 1
+ },
+ "CC3P": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 9,
+ "size": 1
+ },
+ "CC3E": {
+ "description": "Capture/Compare 3 output\n enable",
+ "offset": 8,
+ "size": 1
+ },
+ "CC2NP": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 7,
+ "size": 1
+ },
+ "CC2P": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 5,
+ "size": 1
+ },
+ "CC2E": {
+ "description": "Capture/Compare 2 output\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC1NP": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 3,
+ "size": 1
+ },
+ "CC1P": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 1,
+ "size": 1
+ },
+ "CC1E": {
+ "description": "Capture/Compare 1 output\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNT": {
+ "description": "counter",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNT_H": {
+ "description": "High counter value",
+ "offset": 16,
+ "size": 16
+ },
+ "CNT_L": {
+ "description": "Low counter value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "PSC": {
+ "description": "prescaler",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ARR": {
+ "description": "auto-reload register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARR_H": {
+ "description": "High Auto-reload value",
+ "offset": 16,
+ "size": 16
+ },
+ "ARR_L": {
+ "description": "Low Auto-reload value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR1": {
+ "description": "capture/compare register 1",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR1_H": {
+ "description": "High Capture/Compare 1\n value",
+ "offset": 16,
+ "size": 16
+ },
+ "CCR1_L": {
+ "description": "Low Capture/Compare 1\n value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR2": {
+ "description": "capture/compare register 2",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR2_H": {
+ "description": "High Capture/Compare 2\n value",
+ "offset": 16,
+ "size": 16
+ },
+ "CCR2_L": {
+ "description": "Low Capture/Compare 2\n value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR3": {
+ "description": "capture/compare register 3",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR3_H": {
+ "description": "High Capture/Compare value",
+ "offset": 16,
+ "size": 16
+ },
+ "CCR3_L": {
+ "description": "Low Capture/Compare value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR4": {
+ "description": "capture/compare register 4",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR4_H": {
+ "description": "High Capture/Compare value",
+ "offset": 16,
+ "size": 16
+ },
+ "CCR4_L": {
+ "description": "Low Capture/Compare value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DCR": {
+ "description": "DMA control register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBL": {
+ "description": "DMA burst length",
+ "offset": 8,
+ "size": 5
+ },
+ "DBA": {
+ "description": "DMA base address",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "DMAR": {
+ "description": "DMA address for full transfer",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAB": {
+ "description": "DMA register for burst\n accesses",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "Ethernet_MMC": {
+ "description": "Ethernet: MAC management counters",
+ "children": {
+ "registers": {
+ "MMCCR": {
+ "description": "Ethernet MMC control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CR": {
+ "description": "CR",
+ "offset": 0,
+ "size": 1
+ },
+ "CSR": {
+ "description": "CSR",
+ "offset": 1,
+ "size": 1
+ },
+ "ROR": {
+ "description": "ROR",
+ "offset": 2,
+ "size": 1
+ },
+ "MCF": {
+ "description": "MCF",
+ "offset": 3,
+ "size": 1
+ },
+ "MCP": {
+ "description": "MCP",
+ "offset": 4,
+ "size": 1
+ },
+ "MCFHP": {
+ "description": "MCFHP",
+ "offset": 5,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MMCRIR": {
+ "description": "Ethernet MMC receive interrupt\n register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RFCES": {
+ "description": "RFCES",
+ "offset": 5,
+ "size": 1
+ },
+ "RFAES": {
+ "description": "RFAES",
+ "offset": 6,
+ "size": 1
+ },
+ "RGUFS": {
+ "description": "RGUFS",
+ "offset": 17,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MMCTIR": {
+ "description": "Ethernet MMC transmit interrupt\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "TGFSCS": {
+ "description": "TGFSCS",
+ "offset": 14,
+ "size": 1
+ },
+ "TGFMSCS": {
+ "description": "TGFMSCS",
+ "offset": 15,
+ "size": 1
+ },
+ "TGFS": {
+ "description": "TGFS",
+ "offset": 21,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MMCRIMR": {
+ "description": "Ethernet MMC receive interrupt mask\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RFCEM": {
+ "description": "RFCEM",
+ "offset": 5,
+ "size": 1
+ },
+ "RFAEM": {
+ "description": "RFAEM",
+ "offset": 6,
+ "size": 1
+ },
+ "RGUFM": {
+ "description": "RGUFM",
+ "offset": 17,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MMCTIMR": {
+ "description": "Ethernet MMC transmit interrupt mask\n register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TGFSCM": {
+ "description": "TGFSCM",
+ "offset": 14,
+ "size": 1
+ },
+ "TGFMSCM": {
+ "description": "TGFMSCM",
+ "offset": 15,
+ "size": 1
+ },
+ "TGFM": {
+ "description": "TGFM",
+ "offset": 16,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MMCTGFSCCR": {
+ "description": "Ethernet MMC transmitted good frames after a\n single collision counter",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "TGFSCC": {
+ "description": "TGFSCC",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "MMCTGFMSCCR": {
+ "description": "Ethernet MMC transmitted good frames after\n more than a single collision",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "TGFMSCC": {
+ "description": "TGFMSCC",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "MMCTGFCR": {
+ "description": "Ethernet MMC transmitted good frames counter\n register",
+ "offset": 104,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "TGFC": {
+ "description": "HTL",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "MMCRFCECR": {
+ "description": "Ethernet MMC received frames with CRC error\n counter register",
+ "offset": 148,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "RFCFC": {
+ "description": "RFCFC",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "MMCRFAECR": {
+ "description": "Ethernet MMC received frames with alignment\n error counter register",
+ "offset": 152,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "RFAEC": {
+ "description": "RFAEC",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "MMCRGUFCR": {
+ "description": "MMC received good unicast frames counter\n register",
+ "offset": 196,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "RGUFC": {
+ "description": "RGUFC",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "TIM5": {
+ "description": "General-purpose-timers",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CKD": {
+ "description": "Clock division",
+ "offset": 8,
+ "size": 2
+ },
+ "ARPE": {
+ "description": "Auto-reload preload enable",
+ "offset": 7,
+ "size": 1
+ },
+ "CMS": {
+ "description": "Center-aligned mode\n selection",
+ "offset": 5,
+ "size": 2
+ },
+ "DIR": {
+ "description": "Direction",
+ "offset": 4,
+ "size": 1
+ },
+ "OPM": {
+ "description": "One-pulse mode",
+ "offset": 3,
+ "size": 1
+ },
+ "URS": {
+ "description": "Update request source",
+ "offset": 2,
+ "size": 1
+ },
+ "UDIS": {
+ "description": "Update disable",
+ "offset": 1,
+ "size": 1
+ },
+ "CEN": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TI1S": {
+ "description": "TI1 selection",
+ "offset": 7,
+ "size": 1
+ },
+ "MMS": {
+ "description": "Master mode selection",
+ "offset": 4,
+ "size": 3
+ },
+ "CCDS": {
+ "description": "Capture/compare DMA\n selection",
+ "offset": 3,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SMCR": {
+ "description": "slave mode control register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ETP": {
+ "description": "External trigger polarity",
+ "offset": 15,
+ "size": 1
+ },
+ "ECE": {
+ "description": "External clock enable",
+ "offset": 14,
+ "size": 1
+ },
+ "ETPS": {
+ "description": "External trigger prescaler",
+ "offset": 12,
+ "size": 2
+ },
+ "ETF": {
+ "description": "External trigger filter",
+ "offset": 8,
+ "size": 4
+ },
+ "MSM": {
+ "description": "Master/Slave mode",
+ "offset": 7,
+ "size": 1
+ },
+ "TS": {
+ "description": "Trigger selection",
+ "offset": 4,
+ "size": 3
+ },
+ "SMS": {
+ "description": "Slave mode selection",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "DIER": {
+ "description": "DMA/Interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TDE": {
+ "description": "Trigger DMA request enable",
+ "offset": 14,
+ "size": 1
+ },
+ "CC4DE": {
+ "description": "Capture/Compare 4 DMA request\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3DE": {
+ "description": "Capture/Compare 3 DMA request\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "CC2DE": {
+ "description": "Capture/Compare 2 DMA request\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC1DE": {
+ "description": "Capture/Compare 1 DMA request\n enable",
+ "offset": 9,
+ "size": 1
+ },
+ "UDE": {
+ "description": "Update DMA request enable",
+ "offset": 8,
+ "size": 1
+ },
+ "TIE": {
+ "description": "Trigger interrupt enable",
+ "offset": 6,
+ "size": 1
+ },
+ "CC4IE": {
+ "description": "Capture/Compare 4 interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3IE": {
+ "description": "Capture/Compare 3 interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2IE": {
+ "description": "Capture/Compare 2 interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IE": {
+ "description": "Capture/Compare 1 interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "UIE": {
+ "description": "Update interrupt enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC4OF": {
+ "description": "Capture/Compare 4 overcapture\n flag",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3OF": {
+ "description": "Capture/Compare 3 overcapture\n flag",
+ "offset": 11,
+ "size": 1
+ },
+ "CC2OF": {
+ "description": "Capture/compare 2 overcapture\n flag",
+ "offset": 10,
+ "size": 1
+ },
+ "CC1OF": {
+ "description": "Capture/Compare 1 overcapture\n flag",
+ "offset": 9,
+ "size": 1
+ },
+ "TIF": {
+ "description": "Trigger interrupt flag",
+ "offset": 6,
+ "size": 1
+ },
+ "CC4IF": {
+ "description": "Capture/Compare 4 interrupt\n flag",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3IF": {
+ "description": "Capture/Compare 3 interrupt\n flag",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2IF": {
+ "description": "Capture/Compare 2 interrupt\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IF": {
+ "description": "Capture/compare 1 interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "UIF": {
+ "description": "Update interrupt flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EGR": {
+ "description": "event generation register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "TG": {
+ "description": "Trigger generation",
+ "offset": 6,
+ "size": 1
+ },
+ "CC4G": {
+ "description": "Capture/compare 4\n generation",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3G": {
+ "description": "Capture/compare 3\n generation",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2G": {
+ "description": "Capture/compare 2\n generation",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1G": {
+ "description": "Capture/compare 1\n generation",
+ "offset": 1,
+ "size": 1
+ },
+ "UG": {
+ "description": "Update generation",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Output": {
+ "description": "capture/compare mode register 1 (output\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OC2CE": {
+ "description": "OC2CE",
+ "offset": 15,
+ "size": 1
+ },
+ "OC2M": {
+ "description": "OC2M",
+ "offset": 12,
+ "size": 3
+ },
+ "OC2PE": {
+ "description": "OC2PE",
+ "offset": 11,
+ "size": 1
+ },
+ "OC2FE": {
+ "description": "OC2FE",
+ "offset": 10,
+ "size": 1
+ },
+ "CC2S": {
+ "description": "CC2S",
+ "offset": 8,
+ "size": 2
+ },
+ "OC1CE": {
+ "description": "OC1CE",
+ "offset": 7,
+ "size": 1
+ },
+ "OC1M": {
+ "description": "OC1M",
+ "offset": 4,
+ "size": 3
+ },
+ "OC1PE": {
+ "description": "OC1PE",
+ "offset": 3,
+ "size": 1
+ },
+ "OC1FE": {
+ "description": "OC1FE",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1S": {
+ "description": "CC1S",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR1_Input": {
+ "description": "capture/compare mode register 1 (input\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC2F": {
+ "description": "Input capture 2 filter",
+ "offset": 12,
+ "size": 4
+ },
+ "IC2PCS": {
+ "description": "Input capture 2 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC2S": {
+ "description": "Capture/Compare 2\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC1F": {
+ "description": "Input capture 1 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "ICPCS": {
+ "description": "Input capture 1 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR2_Output": {
+ "description": "capture/compare mode register 2 (output\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "O24CE": {
+ "description": "O24CE",
+ "offset": 15,
+ "size": 1
+ },
+ "OC4M": {
+ "description": "OC4M",
+ "offset": 12,
+ "size": 3
+ },
+ "OC4PE": {
+ "description": "OC4PE",
+ "offset": 11,
+ "size": 1
+ },
+ "OC4FE": {
+ "description": "OC4FE",
+ "offset": 10,
+ "size": 1
+ },
+ "CC4S": {
+ "description": "CC4S",
+ "offset": 8,
+ "size": 2
+ },
+ "OC3CE": {
+ "description": "OC3CE",
+ "offset": 7,
+ "size": 1
+ },
+ "OC3M": {
+ "description": "OC3M",
+ "offset": 4,
+ "size": 3
+ },
+ "OC3PE": {
+ "description": "OC3PE",
+ "offset": 3,
+ "size": 1
+ },
+ "OC3FE": {
+ "description": "OC3FE",
+ "offset": 2,
+ "size": 1
+ },
+ "CC3S": {
+ "description": "CC3S",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR2_Input": {
+ "description": "capture/compare mode register 2 (input\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC4F": {
+ "description": "Input capture 4 filter",
+ "offset": 12,
+ "size": 4
+ },
+ "IC4PSC": {
+ "description": "Input capture 4 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC4S": {
+ "description": "Capture/Compare 4\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC3F": {
+ "description": "Input capture 3 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "IC3PSC": {
+ "description": "Input capture 3 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC3S": {
+ "description": "Capture/compare 3\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCER": {
+ "description": "capture/compare enable\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC4NP": {
+ "description": "Capture/Compare 4 output\n Polarity",
+ "offset": 15,
+ "size": 1
+ },
+ "CC4P": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 13,
+ "size": 1
+ },
+ "CC4E": {
+ "description": "Capture/Compare 4 output\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3NP": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 11,
+ "size": 1
+ },
+ "CC3P": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 9,
+ "size": 1
+ },
+ "CC3E": {
+ "description": "Capture/Compare 3 output\n enable",
+ "offset": 8,
+ "size": 1
+ },
+ "CC2NP": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 7,
+ "size": 1
+ },
+ "CC2P": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 5,
+ "size": 1
+ },
+ "CC2E": {
+ "description": "Capture/Compare 2 output\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC1NP": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 3,
+ "size": 1
+ },
+ "CC1P": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 1,
+ "size": 1
+ },
+ "CC1E": {
+ "description": "Capture/Compare 1 output\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNT": {
+ "description": "counter",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNT_H": {
+ "description": "High counter value",
+ "offset": 16,
+ "size": 16
+ },
+ "CNT_L": {
+ "description": "Low counter value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "PSC": {
+ "description": "prescaler",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ARR": {
+ "description": "auto-reload register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARR_H": {
+ "description": "High Auto-reload value",
+ "offset": 16,
+ "size": 16
+ },
+ "ARR_L": {
+ "description": "Low Auto-reload value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR1": {
+ "description": "capture/compare register 1",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR1_H": {
+ "description": "High Capture/Compare 1\n value",
+ "offset": 16,
+ "size": 16
+ },
+ "CCR1_L": {
+ "description": "Low Capture/Compare 1\n value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR2": {
+ "description": "capture/compare register 2",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR2_H": {
+ "description": "High Capture/Compare 2\n value",
+ "offset": 16,
+ "size": 16
+ },
+ "CCR2_L": {
+ "description": "Low Capture/Compare 2\n value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR3": {
+ "description": "capture/compare register 3",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR3_H": {
+ "description": "High Capture/Compare value",
+ "offset": 16,
+ "size": 16
+ },
+ "CCR3_L": {
+ "description": "Low Capture/Compare value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR4": {
+ "description": "capture/compare register 4",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR4_H": {
+ "description": "High Capture/Compare value",
+ "offset": 16,
+ "size": 16
+ },
+ "CCR4_L": {
+ "description": "Low Capture/Compare value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DCR": {
+ "description": "DMA control register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBL": {
+ "description": "DMA burst length",
+ "offset": 8,
+ "size": 5
+ },
+ "DBA": {
+ "description": "DMA base address",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "DMAR": {
+ "description": "DMA address for full transfer",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAB": {
+ "description": "DMA register for burst\n accesses",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OR": {
+ "description": "TIM5 option register",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IT4_RMP": {
+ "description": "Timer Input 4 remap",
+ "offset": 6,
+ "size": 2
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "TIM9": {
+ "description": "General purpose timers",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CKD": {
+ "description": "Clock division",
+ "offset": 8,
+ "size": 2
+ },
+ "ARPE": {
+ "description": "Auto-reload preload enable",
+ "offset": 7,
+ "size": 1
+ },
+ "OPM": {
+ "description": "One-pulse mode",
+ "offset": 3,
+ "size": 1
+ },
+ "URS": {
+ "description": "Update request source",
+ "offset": 2,
+ "size": 1
+ },
+ "UDIS": {
+ "description": "Update disable",
+ "offset": 1,
+ "size": 1
+ },
+ "CEN": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MMS": {
+ "description": "Master mode selection",
+ "offset": 4,
+ "size": 3
+ }
+ }
+ }
+ },
+ "SMCR": {
+ "description": "slave mode control register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MSM": {
+ "description": "Master/Slave mode",
+ "offset": 7,
+ "size": 1
+ },
+ "TS": {
+ "description": "Trigger selection",
+ "offset": 4,
+ "size": 3
+ },
+ "SMS": {
+ "description": "Slave mode selection",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "DIER": {
+ "description": "DMA/Interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIE": {
+ "description": "Trigger interrupt enable",
+ "offset": 6,
+ "size": 1
+ },
+ "CC2IE": {
+ "description": "Capture/Compare 2 interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IE": {
+ "description": "Capture/Compare 1 interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "UIE": {
+ "description": "Update interrupt enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC2OF": {
+ "description": "Capture/compare 2 overcapture\n flag",
+ "offset": 10,
+ "size": 1
+ },
+ "CC1OF": {
+ "description": "Capture/Compare 1 overcapture\n flag",
+ "offset": 9,
+ "size": 1
+ },
+ "TIF": {
+ "description": "Trigger interrupt flag",
+ "offset": 6,
+ "size": 1
+ },
+ "CC2IF": {
+ "description": "Capture/Compare 2 interrupt\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IF": {
+ "description": "Capture/compare 1 interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "UIF": {
+ "description": "Update interrupt flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EGR": {
+ "description": "event generation register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "TG": {
+ "description": "Trigger generation",
+ "offset": 6,
+ "size": 1
+ },
+ "CC2G": {
+ "description": "Capture/compare 2\n generation",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1G": {
+ "description": "Capture/compare 1\n generation",
+ "offset": 1,
+ "size": 1
+ },
+ "UG": {
+ "description": "Update generation",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Output": {
+ "description": "capture/compare mode register 1 (output\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OC2M": {
+ "description": "Output Compare 2 mode",
+ "offset": 12,
+ "size": 3
+ },
+ "OC2PE": {
+ "description": "Output Compare 2 preload\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "OC2FE": {
+ "description": "Output Compare 2 fast\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC2S": {
+ "description": "Capture/Compare 2\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "OC1M": {
+ "description": "Output Compare 1 mode",
+ "offset": 4,
+ "size": 3
+ },
+ "OC1PE": {
+ "description": "Output Compare 1 preload\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "OC1FE": {
+ "description": "Output Compare 1 fast\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR1_Input": {
+ "description": "capture/compare mode register 1 (input\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC2F": {
+ "description": "Input capture 2 filter",
+ "offset": 12,
+ "size": 3
+ },
+ "IC2PCS": {
+ "description": "Input capture 2 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC2S": {
+ "description": "Capture/Compare 2\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC1F": {
+ "description": "Input capture 1 filter",
+ "offset": 4,
+ "size": 3
+ },
+ "ICPCS": {
+ "description": "Input capture 1 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCER": {
+ "description": "capture/compare enable\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC2NP": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 7,
+ "size": 1
+ },
+ "CC2P": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 5,
+ "size": 1
+ },
+ "CC2E": {
+ "description": "Capture/Compare 2 output\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC1NP": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 3,
+ "size": 1
+ },
+ "CC1P": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 1,
+ "size": 1
+ },
+ "CC1E": {
+ "description": "Capture/Compare 1 output\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNT": {
+ "description": "counter",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNT": {
+ "description": "counter value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "PSC": {
+ "description": "prescaler",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ARR": {
+ "description": "auto-reload register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARR": {
+ "description": "Auto-reload value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR1": {
+ "description": "capture/compare register 1",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR1": {
+ "description": "Capture/Compare 1 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR2": {
+ "description": "capture/compare register 2",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR2": {
+ "description": "Capture/Compare 2 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "Ethernet_MAC": {
+ "description": "Ethernet: media access control\n (MAC)",
+ "children": {
+ "registers": {
+ "MACCR": {
+ "description": "Ethernet MAC configuration\n register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 32768,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RE": {
+ "description": "RE",
+ "offset": 2,
+ "size": 1
+ },
+ "TE": {
+ "description": "TE",
+ "offset": 3,
+ "size": 1
+ },
+ "DC": {
+ "description": "DC",
+ "offset": 4,
+ "size": 1
+ },
+ "BL": {
+ "description": "BL",
+ "offset": 5,
+ "size": 2
+ },
+ "APCS": {
+ "description": "APCS",
+ "offset": 7,
+ "size": 1
+ },
+ "RD": {
+ "description": "RD",
+ "offset": 9,
+ "size": 1
+ },
+ "IPCO": {
+ "description": "IPCO",
+ "offset": 10,
+ "size": 1
+ },
+ "DM": {
+ "description": "DM",
+ "offset": 11,
+ "size": 1
+ },
+ "LM": {
+ "description": "LM",
+ "offset": 12,
+ "size": 1
+ },
+ "ROD": {
+ "description": "ROD",
+ "offset": 13,
+ "size": 1
+ },
+ "FES": {
+ "description": "FES",
+ "offset": 14,
+ "size": 1
+ },
+ "CSD": {
+ "description": "CSD",
+ "offset": 16,
+ "size": 1
+ },
+ "IFG": {
+ "description": "IFG",
+ "offset": 17,
+ "size": 3
+ },
+ "JD": {
+ "description": "JD",
+ "offset": 22,
+ "size": 1
+ },
+ "WD": {
+ "description": "WD",
+ "offset": 23,
+ "size": 1
+ },
+ "CSTF": {
+ "description": "CSTF",
+ "offset": 25,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MACFFR": {
+ "description": "Ethernet MAC frame filter\n register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PM": {
+ "description": "PM",
+ "offset": 0,
+ "size": 1
+ },
+ "HU": {
+ "description": "HU",
+ "offset": 1,
+ "size": 1
+ },
+ "HM": {
+ "description": "HM",
+ "offset": 2,
+ "size": 1
+ },
+ "DAIF": {
+ "description": "DAIF",
+ "offset": 3,
+ "size": 1
+ },
+ "RAM": {
+ "description": "RAM",
+ "offset": 4,
+ "size": 1
+ },
+ "BFD": {
+ "description": "BFD",
+ "offset": 5,
+ "size": 1
+ },
+ "PCF": {
+ "description": "PCF",
+ "offset": 6,
+ "size": 1
+ },
+ "SAIF": {
+ "description": "SAIF",
+ "offset": 7,
+ "size": 1
+ },
+ "SAF": {
+ "description": "SAF",
+ "offset": 8,
+ "size": 1
+ },
+ "HPF": {
+ "description": "HPF",
+ "offset": 9,
+ "size": 1
+ },
+ "RA": {
+ "description": "RA",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MACHTHR": {
+ "description": "Ethernet MAC hash table high\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "HTH": {
+ "description": "HTH",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "MACHTLR": {
+ "description": "Ethernet MAC hash table low\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "HTL": {
+ "description": "HTL",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "MACMIIAR": {
+ "description": "Ethernet MAC MII address\n register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MB": {
+ "description": "MB",
+ "offset": 0,
+ "size": 1
+ },
+ "MW": {
+ "description": "MW",
+ "offset": 1,
+ "size": 1
+ },
+ "CR": {
+ "description": "CR",
+ "offset": 2,
+ "size": 3
+ },
+ "MR": {
+ "description": "MR",
+ "offset": 6,
+ "size": 5
+ },
+ "PA": {
+ "description": "PA",
+ "offset": 11,
+ "size": 5
+ }
+ }
+ }
+ },
+ "MACMIIDR": {
+ "description": "Ethernet MAC MII data register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TD": {
+ "description": "TD",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "MACFCR": {
+ "description": "Ethernet MAC flow control\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FCB": {
+ "description": "FCB",
+ "offset": 0,
+ "size": 1
+ },
+ "TFCE": {
+ "description": "TFCE",
+ "offset": 1,
+ "size": 1
+ },
+ "RFCE": {
+ "description": "RFCE",
+ "offset": 2,
+ "size": 1
+ },
+ "UPFD": {
+ "description": "UPFD",
+ "offset": 3,
+ "size": 1
+ },
+ "PLT": {
+ "description": "PLT",
+ "offset": 4,
+ "size": 2
+ },
+ "ZQPD": {
+ "description": "ZQPD",
+ "offset": 7,
+ "size": 1
+ },
+ "PT": {
+ "description": "PT",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "MACVLANTR": {
+ "description": "Ethernet MAC VLAN tag register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "VLANTI": {
+ "description": "VLANTI",
+ "offset": 0,
+ "size": 16
+ },
+ "VLANTC": {
+ "description": "VLANTC",
+ "offset": 16,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MACPMTCSR": {
+ "description": "Ethernet MAC PMT control and status\n register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PD": {
+ "description": "PD",
+ "offset": 0,
+ "size": 1
+ },
+ "MPE": {
+ "description": "MPE",
+ "offset": 1,
+ "size": 1
+ },
+ "WFE": {
+ "description": "WFE",
+ "offset": 2,
+ "size": 1
+ },
+ "MPR": {
+ "description": "MPR",
+ "offset": 5,
+ "size": 1
+ },
+ "WFR": {
+ "description": "WFR",
+ "offset": 6,
+ "size": 1
+ },
+ "GU": {
+ "description": "GU",
+ "offset": 9,
+ "size": 1
+ },
+ "WFFRPR": {
+ "description": "WFFRPR",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MACDBGR": {
+ "description": "Ethernet MAC debug register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CR": {
+ "description": "CR",
+ "offset": 0,
+ "size": 1
+ },
+ "CSR": {
+ "description": "CSR",
+ "offset": 1,
+ "size": 1
+ },
+ "ROR": {
+ "description": "ROR",
+ "offset": 2,
+ "size": 1
+ },
+ "MCF": {
+ "description": "MCF",
+ "offset": 3,
+ "size": 1
+ },
+ "MCP": {
+ "description": "MCP",
+ "offset": 4,
+ "size": 1
+ },
+ "MCFHP": {
+ "description": "MCFHP",
+ "offset": 5,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MACSR": {
+ "description": "Ethernet MAC interrupt status\n register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PMTS": {
+ "description": "PMTS",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "MMCS": {
+ "description": "MMCS",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "MMCRS": {
+ "description": "MMCRS",
+ "offset": 5,
+ "size": 1,
+ "access": "read-only"
+ },
+ "MMCTS": {
+ "description": "MMCTS",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TSTS": {
+ "description": "TSTS",
+ "offset": 9,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MACIMR": {
+ "description": "Ethernet MAC interrupt mask\n register",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PMTIM": {
+ "description": "PMTIM",
+ "offset": 3,
+ "size": 1
+ },
+ "TSTIM": {
+ "description": "TSTIM",
+ "offset": 9,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MACA0HR": {
+ "description": "Ethernet MAC address 0 high\n register",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 1114111,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MACA0H": {
+ "description": "MAC address0 high",
+ "offset": 0,
+ "size": 16
+ },
+ "MO": {
+ "description": "Always 1",
+ "offset": 31,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "MACA0LR": {
+ "description": "Ethernet MAC address 0 low\n register",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MACA0L": {
+ "description": "0",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "MACA1HR": {
+ "description": "Ethernet MAC address 1 high\n register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 65535,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MACA1H": {
+ "description": "MACA1H",
+ "offset": 0,
+ "size": 16
+ },
+ "MBC": {
+ "description": "MBC",
+ "offset": 24,
+ "size": 6
+ },
+ "SA": {
+ "description": "SA",
+ "offset": 30,
+ "size": 1
+ },
+ "AE": {
+ "description": "AE",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MACA1LR": {
+ "description": "Ethernet MAC address1 low\n register",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MACA1LR": {
+ "description": "MACA1LR",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "MACA2HR": {
+ "description": "Ethernet MAC address 2 high\n register",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 65535,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MAC2AH": {
+ "description": "MAC2AH",
+ "offset": 0,
+ "size": 16
+ },
+ "MBC": {
+ "description": "MBC",
+ "offset": 24,
+ "size": 6
+ },
+ "SA": {
+ "description": "SA",
+ "offset": 30,
+ "size": 1
+ },
+ "AE": {
+ "description": "AE",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MACA2LR": {
+ "description": "Ethernet MAC address 2 low\n register",
+ "offset": 84,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MACA2L": {
+ "description": "MACA2L",
+ "offset": 0,
+ "size": 31
+ }
+ }
+ }
+ },
+ "MACA3HR": {
+ "description": "Ethernet MAC address 3 high\n register",
+ "offset": 88,
+ "size": 32,
+ "reset_value": 65535,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MACA3H": {
+ "description": "MACA3H",
+ "offset": 0,
+ "size": 16
+ },
+ "MBC": {
+ "description": "MBC",
+ "offset": 24,
+ "size": 6
+ },
+ "SA": {
+ "description": "SA",
+ "offset": 30,
+ "size": 1
+ },
+ "AE": {
+ "description": "AE",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MACA3LR": {
+ "description": "Ethernet MAC address 3 low\n register",
+ "offset": 92,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MBCA3L": {
+ "description": "MBCA3L",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "TIM10": {
+ "description": "General-purpose-timers",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CKD": {
+ "description": "Clock division",
+ "offset": 8,
+ "size": 2
+ },
+ "ARPE": {
+ "description": "Auto-reload preload enable",
+ "offset": 7,
+ "size": 1
+ },
+ "URS": {
+ "description": "Update request source",
+ "offset": 2,
+ "size": 1
+ },
+ "UDIS": {
+ "description": "Update disable",
+ "offset": 1,
+ "size": 1
+ },
+ "CEN": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DIER": {
+ "description": "DMA/Interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC1IE": {
+ "description": "Capture/Compare 1 interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "UIE": {
+ "description": "Update interrupt enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC1OF": {
+ "description": "Capture/Compare 1 overcapture\n flag",
+ "offset": 9,
+ "size": 1
+ },
+ "CC1IF": {
+ "description": "Capture/compare 1 interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "UIF": {
+ "description": "Update interrupt flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EGR": {
+ "description": "event generation register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "CC1G": {
+ "description": "Capture/compare 1\n generation",
+ "offset": 1,
+ "size": 1
+ },
+ "UG": {
+ "description": "Update generation",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Output": {
+ "description": "capture/compare mode register 1 (output\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OC1M": {
+ "description": "Output Compare 1 mode",
+ "offset": 4,
+ "size": 3
+ },
+ "OC1PE": {
+ "description": "Output Compare 1 preload\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "OC1FE": {
+ "description": "Output Compare 1 fast\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR1_Input": {
+ "description": "capture/compare mode register 1 (input\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC1F": {
+ "description": "Input capture 1 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "ICPCS": {
+ "description": "Input capture 1 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCER": {
+ "description": "capture/compare enable\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC1NP": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 3,
+ "size": 1
+ },
+ "CC1P": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 1,
+ "size": 1
+ },
+ "CC1E": {
+ "description": "Capture/Compare 1 output\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNT": {
+ "description": "counter",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNT": {
+ "description": "counter value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "PSC": {
+ "description": "prescaler",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ARR": {
+ "description": "auto-reload register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARR": {
+ "description": "Auto-reload value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR1": {
+ "description": "capture/compare register 1",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR1": {
+ "description": "Capture/Compare 1 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "TIM11": {
+ "description": "General-purpose-timers",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CKD": {
+ "description": "Clock division",
+ "offset": 8,
+ "size": 2
+ },
+ "ARPE": {
+ "description": "Auto-reload preload enable",
+ "offset": 7,
+ "size": 1
+ },
+ "URS": {
+ "description": "Update request source",
+ "offset": 2,
+ "size": 1
+ },
+ "UDIS": {
+ "description": "Update disable",
+ "offset": 1,
+ "size": 1
+ },
+ "CEN": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DIER": {
+ "description": "DMA/Interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC1IE": {
+ "description": "Capture/Compare 1 interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "UIE": {
+ "description": "Update interrupt enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC1OF": {
+ "description": "Capture/Compare 1 overcapture\n flag",
+ "offset": 9,
+ "size": 1
+ },
+ "CC1IF": {
+ "description": "Capture/compare 1 interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "UIF": {
+ "description": "Update interrupt flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EGR": {
+ "description": "event generation register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "CC1G": {
+ "description": "Capture/compare 1\n generation",
+ "offset": 1,
+ "size": 1
+ },
+ "UG": {
+ "description": "Update generation",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Output": {
+ "description": "capture/compare mode register 1 (output\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OC1M": {
+ "description": "Output Compare 1 mode",
+ "offset": 4,
+ "size": 3
+ },
+ "OC1PE": {
+ "description": "Output Compare 1 preload\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "OC1FE": {
+ "description": "Output Compare 1 fast\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR1_Input": {
+ "description": "capture/compare mode register 1 (input\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC1F": {
+ "description": "Input capture 1 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "ICPCS": {
+ "description": "Input capture 1 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCER": {
+ "description": "capture/compare enable\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC1NP": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 3,
+ "size": 1
+ },
+ "CC1P": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 1,
+ "size": 1
+ },
+ "CC1E": {
+ "description": "Capture/Compare 1 output\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNT": {
+ "description": "counter",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNT": {
+ "description": "counter value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "PSC": {
+ "description": "prescaler",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ARR": {
+ "description": "auto-reload register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARR": {
+ "description": "Auto-reload value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR1": {
+ "description": "capture/compare register 1",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR1": {
+ "description": "Capture/Compare 1 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OR": {
+ "description": "option register",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RMP": {
+ "description": "Input 1 remapping\n capability",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "devices": {
+ "STM32F407": {
+ "arch": "cortex_m4",
+ "description": "STM32F407",
+ "properties": {
+ "cpu.nvic_prio_bits": "3",
+ "cpu.mpu": "false",
+ "cpu.fpu": "false",
+ "cpu.revision": "r1p0",
+ "cpu.vendor_systick_config": "false",
+ "cpu.endian": "little",
+ "cpu.name": "CM4"
+ },
+ "children": {
+ "interrupts": {
+ "MemManageFault": {
+ "index": -12
+ },
+ "BusFault": {
+ "index": -11
+ },
+ "UsageFault": {
+ "index": -10
+ },
+ "DebugMonitor": {
+ "index": -4
+ },
+ "NMI": {
+ "index": -14
+ },
+ "HardFault": {
+ "index": -13
+ },
+ "SVCall": {
+ "index": -5
+ },
+ "PendSV": {
+ "index": -2
+ },
+ "SysTick": {
+ "index": -1
+ },
+ "FPU": {
+ "index": 81,
+ "description": "Floating point unit interrupt"
+ },
+ "DCMI": {
+ "index": 78,
+ "description": "DCMI global interrupt"
+ },
+ "FSMC": {
+ "index": 48,
+ "description": "FSMC global interrupt"
+ },
+ "DMA2_Stream0": {
+ "index": 56,
+ "description": "DMA2 Stream0 global interrupt"
+ },
+ "DMA1_Stream0": {
+ "index": 11,
+ "description": "DMA1 Stream0 global interrupt"
+ },
+ "RCC": {
+ "index": 5,
+ "description": "RCC global interrupt"
+ },
+ "SPI1": {
+ "index": 35,
+ "description": "SPI1 global interrupt"
+ },
+ "SPI2": {
+ "index": 36,
+ "description": "SPI2 global interrupt"
+ },
+ "SPI3": {
+ "index": 51,
+ "description": "SPI3 global interrupt"
+ },
+ "SDIO": {
+ "index": 49,
+ "description": "SDIO global interrupt"
+ },
+ "ADC": {
+ "index": 18,
+ "description": "ADC3 global interrupts"
+ },
+ "USART6": {
+ "index": 71,
+ "description": "USART6 global interrupt"
+ },
+ "USART1": {
+ "index": 37,
+ "description": "USART1 global interrupt"
+ },
+ "USART2": {
+ "index": 38,
+ "description": "USART2 global interrupt"
+ },
+ "USART3": {
+ "index": 39,
+ "description": "USART3 global interrupt"
+ },
+ "TIM6_DAC": {
+ "index": 54,
+ "description": "TIM6 global interrupt, DAC1 and DAC2 underrun\n error interrupt"
+ },
+ "PVD": {
+ "index": 1,
+ "description": "PVD through EXTI line detection\n interrupt"
+ },
+ "I2C3_EV": {
+ "index": 72,
+ "description": "I2C3 event interrupt"
+ },
+ "I2C2_EV": {
+ "index": 33,
+ "description": "I2C2 event interrupt"
+ },
+ "I2C1_EV": {
+ "index": 31,
+ "description": "I2C1 event interrupt"
+ },
+ "WWDG": {
+ "index": 0,
+ "description": "Window Watchdog interrupt"
+ },
+ "RTC_WKUP": {
+ "index": 3,
+ "description": "RTC Wakeup interrupt through the EXTI\n line"
+ },
+ "UART4": {
+ "index": 52,
+ "description": "UART4 global interrupt"
+ },
+ "UART5": {
+ "index": 53,
+ "description": "UART5 global interrupt"
+ },
+ "TIM1_BRK_TIM9": {
+ "index": 24,
+ "description": "TIM1 Break interrupt and TIM9 global\n interrupt"
+ },
+ "TIM8_BRK_TIM12": {
+ "index": 43,
+ "description": "TIM8 Break interrupt and TIM12 global\n interrupt"
+ },
+ "TIM2": {
+ "index": 28,
+ "description": "TIM2 global interrupt"
+ },
+ "TIM3": {
+ "index": 29,
+ "description": "TIM3 global interrupt"
+ },
+ "TIM4": {
+ "index": 30,
+ "description": "TIM4 global interrupt"
+ },
+ "TIM5": {
+ "index": 50,
+ "description": "TIM5 global interrupt"
+ },
+ "TIM1_UP_TIM10": {
+ "index": 25,
+ "description": "TIM1 Update interrupt and TIM10 global\n interrupt"
+ },
+ "TIM8_UP_TIM13": {
+ "index": 44,
+ "description": "TIM8 Update interrupt and TIM13 global\n interrupt"
+ },
+ "TIM8_TRG_COM_TIM14": {
+ "index": 45,
+ "description": "TIM8 Trigger and Commutation interrupts and\n TIM14 global interrupt"
+ },
+ "TIM1_TRG_COM_TIM11": {
+ "index": 26,
+ "description": "TIM1 Trigger and Commutation interrupts and\n TIM11 global interrupt"
+ },
+ "TIM7": {
+ "index": 55,
+ "description": "TIM7 global interrupt"
+ },
+ "ETH": {
+ "index": 61,
+ "description": "Ethernet global interrupt"
+ },
+ "OTG_FS_WKUP": {
+ "index": 42,
+ "description": "USB On-The-Go FS Wakeup through EXTI line\n interrupt"
+ },
+ "CAN1_TX": {
+ "index": 19,
+ "description": "CAN1 TX interrupts"
+ },
+ "CAN2_TX": {
+ "index": 63,
+ "description": "CAN2 TX interrupts"
+ },
+ "TAMP_STAMP": {
+ "index": 2,
+ "description": "Tamper and TimeStamp interrupts through the\n EXTI line"
+ },
+ "OTG_HS_EP1_OUT": {
+ "index": 74,
+ "description": "USB On The Go HS End Point 1 Out global\n interrupt"
+ },
+ "LCD_TFT": {
+ "index": 88,
+ "description": "LTDC global interrupt"
+ },
+ "HASH_RNG": {
+ "index": 80,
+ "description": "Hash and Rng global interrupt"
+ },
+ "CRYP": {
+ "index": 79,
+ "description": "CRYP crypto global interrupt"
+ }
+ },
+ "peripheral_instances": {
+ "RNG": {
+ "description": "Random number generator",
+ "offset": 1342572544,
+ "type": "types.peripherals.RNG"
+ },
+ "DCMI": {
+ "description": "Digital camera interface",
+ "offset": 1342504960,
+ "type": "types.peripherals.DCMI"
+ },
+ "FSMC": {
+ "description": "Flexible static memory controller",
+ "offset": 2684354560,
+ "type": "types.peripherals.FSMC"
+ },
+ "DBG": {
+ "description": "Debug support",
+ "offset": 3758366720,
+ "type": "types.peripherals.DBG"
+ },
+ "DMA2": {
+ "description": "DMA controller",
+ "offset": 1073898496,
+ "type": "types.peripherals.DMA2"
+ },
+ "DMA1": {
+ "offset": 1073897472,
+ "type": "types.peripherals.DMA2"
+ },
+ "RCC": {
+ "description": "Reset and clock control",
+ "offset": 1073887232,
+ "type": "types.peripherals.RCC"
+ },
+ "GPIOI": {
+ "description": "General-purpose I/Os",
+ "offset": 1073881088,
+ "type": "types.peripherals.GPIOI"
+ },
+ "GPIOH": {
+ "offset": 1073880064,
+ "type": "types.peripherals.GPIOI"
+ },
+ "GPIOG": {
+ "offset": 1073879040,
+ "type": "types.peripherals.GPIOI"
+ },
+ "GPIOF": {
+ "offset": 1073878016,
+ "type": "types.peripherals.GPIOI"
+ },
+ "GPIOE": {
+ "offset": 1073876992,
+ "type": "types.peripherals.GPIOI"
+ },
+ "GPIOD": {
+ "offset": 1073875968,
+ "type": "types.peripherals.GPIOI"
+ },
+ "GPIOC": {
+ "offset": 1073874944,
+ "type": "types.peripherals.GPIOI"
+ },
+ "GPIOJ": {
+ "offset": 1073882112,
+ "type": "types.peripherals.GPIOI"
+ },
+ "GPIOK": {
+ "offset": 1073883136,
+ "type": "types.peripherals.GPIOI"
+ },
+ "GPIOB": {
+ "description": "General-purpose I/Os",
+ "offset": 1073873920,
+ "type": "types.peripherals.GPIOB"
+ },
+ "GPIOA": {
+ "description": "General-purpose I/Os",
+ "offset": 1073872896,
+ "type": "types.peripherals.GPIOA"
+ },
+ "SYSCFG": {
+ "description": "System configuration controller",
+ "offset": 1073821696,
+ "type": "types.peripherals.SYSCFG"
+ },
+ "SPI1": {
+ "description": "Serial peripheral interface",
+ "offset": 1073819648,
+ "type": "types.peripherals.SPI1"
+ },
+ "SPI2": {
+ "offset": 1073756160,
+ "type": "types.peripherals.SPI1"
+ },
+ "SPI3": {
+ "offset": 1073757184,
+ "type": "types.peripherals.SPI1"
+ },
+ "I2S2ext": {
+ "offset": 1073755136,
+ "type": "types.peripherals.SPI1"
+ },
+ "I2S3ext": {
+ "offset": 1073758208,
+ "type": "types.peripherals.SPI1"
+ },
+ "SPI4": {
+ "offset": 1073820672,
+ "type": "types.peripherals.SPI1"
+ },
+ "SPI5": {
+ "offset": 1073827840,
+ "type": "types.peripherals.SPI1"
+ },
+ "SPI6": {
+ "offset": 1073828864,
+ "type": "types.peripherals.SPI1"
+ },
+ "SDIO": {
+ "description": "Secure digital input/output\n interface",
+ "offset": 1073818624,
+ "type": "types.peripherals.SDIO"
+ },
+ "ADC1": {
+ "description": "Analog-to-digital converter",
+ "offset": 1073815552,
+ "type": "types.peripherals.ADC1"
+ },
+ "ADC2": {
+ "offset": 1073815808,
+ "type": "types.peripherals.ADC1"
+ },
+ "ADC3": {
+ "offset": 1073816064,
+ "type": "types.peripherals.ADC1"
+ },
+ "USART6": {
+ "description": "Universal synchronous asynchronous receiver\n transmitter",
+ "offset": 1073812480,
+ "type": "types.peripherals.USART6"
+ },
+ "USART1": {
+ "offset": 1073811456,
+ "type": "types.peripherals.USART6"
+ },
+ "USART2": {
+ "offset": 1073759232,
+ "type": "types.peripherals.USART6"
+ },
+ "USART3": {
+ "offset": 1073760256,
+ "type": "types.peripherals.USART6"
+ },
+ "DAC": {
+ "description": "Digital-to-analog converter",
+ "offset": 1073771520,
+ "type": "types.peripherals.DAC"
+ },
+ "PWR": {
+ "description": "Power control",
+ "offset": 1073770496,
+ "type": "types.peripherals.PWR"
+ },
+ "I2C3": {
+ "description": "Inter-integrated circuit",
+ "offset": 1073765376,
+ "type": "types.peripherals.I2C3"
+ },
+ "I2C2": {
+ "offset": 1073764352,
+ "type": "types.peripherals.I2C3"
+ },
+ "I2C1": {
+ "offset": 1073763328,
+ "type": "types.peripherals.I2C3"
+ },
+ "IWDG": {
+ "description": "Independent watchdog",
+ "offset": 1073754112,
+ "type": "types.peripherals.IWDG"
+ },
+ "WWDG": {
+ "description": "Window watchdog",
+ "offset": 1073753088,
+ "type": "types.peripherals.WWDG"
+ },
+ "RTC": {
+ "description": "Real-time clock",
+ "offset": 1073752064,
+ "type": "types.peripherals.RTC"
+ },
+ "UART4": {
+ "description": "Universal synchronous asynchronous receiver\n transmitter",
+ "offset": 1073761280,
+ "type": "types.peripherals.UART4"
+ },
+ "UART5": {
+ "offset": 1073762304,
+ "type": "types.peripherals.UART4"
+ },
+ "UART7": {
+ "offset": 1073772544,
+ "type": "types.peripherals.UART4"
+ },
+ "UART8": {
+ "offset": 1073773568,
+ "type": "types.peripherals.UART4"
+ },
+ "C_ADC": {
+ "description": "Common ADC registers",
+ "offset": 1073816320,
+ "type": "types.peripherals.C_ADC"
+ },
+ "TIM1": {
+ "description": "Advanced-timers",
+ "offset": 1073807360,
+ "type": "types.peripherals.TIM1"
+ },
+ "TIM8": {
+ "offset": 1073808384,
+ "type": "types.peripherals.TIM1"
+ },
+ "TIM2": {
+ "description": "General purpose timers",
+ "offset": 1073741824,
+ "type": "types.peripherals.TIM2"
+ },
+ "TIM3": {
+ "description": "General purpose timers",
+ "offset": 1073742848,
+ "type": "types.peripherals.TIM3"
+ },
+ "TIM4": {
+ "offset": 1073743872,
+ "type": "types.peripherals.TIM3"
+ },
+ "TIM5": {
+ "description": "General-purpose-timers",
+ "offset": 1073744896,
+ "type": "types.peripherals.TIM5"
+ },
+ "TIM9": {
+ "description": "General purpose timers",
+ "offset": 1073823744,
+ "type": "types.peripherals.TIM9"
+ },
+ "TIM12": {
+ "offset": 1073747968,
+ "type": "types.peripherals.TIM9"
+ },
+ "TIM10": {
+ "description": "General-purpose-timers",
+ "offset": 1073824768,
+ "type": "types.peripherals.TIM10"
+ },
+ "TIM13": {
+ "offset": 1073748992,
+ "type": "types.peripherals.TIM10"
+ },
+ "TIM14": {
+ "offset": 1073750016,
+ "type": "types.peripherals.TIM10"
+ },
+ "TIM11": {
+ "description": "General-purpose-timers",
+ "offset": 1073825792,
+ "type": "types.peripherals.TIM11"
+ },
+ "TIM6": {
+ "description": "Basic timers",
+ "offset": 1073745920,
+ "type": "types.peripherals.TIM6"
+ },
+ "TIM7": {
+ "offset": 1073746944,
+ "type": "types.peripherals.TIM6"
+ },
+ "Ethernet_MAC": {
+ "description": "Ethernet: media access control\n (MAC)",
+ "offset": 1073905664,
+ "type": "types.peripherals.Ethernet_MAC"
+ },
+ "Ethernet_MMC": {
+ "description": "Ethernet: MAC management counters",
+ "offset": 1073905920,
+ "type": "types.peripherals.Ethernet_MMC"
+ },
+ "Ethernet_PTP": {
+ "description": "Ethernet: Precision time protocol",
+ "offset": 1073907456,
+ "type": "types.peripherals.Ethernet_PTP"
+ },
+ "Ethernet_DMA": {
+ "description": "Ethernet: DMA controller operation",
+ "offset": 1073909760,
+ "type": "types.peripherals.Ethernet_DMA"
+ },
+ "CRC": {
+ "description": "Cryptographic processor",
+ "offset": 1073885184,
+ "type": "types.peripherals.CRC"
+ },
+ "OTG_FS_GLOBAL": {
+ "description": "USB on the go full speed",
+ "offset": 1342177280,
+ "type": "types.peripherals.OTG_FS_GLOBAL"
+ },
+ "OTG_FS_HOST": {
+ "description": "USB on the go full speed",
+ "offset": 1342178304,
+ "type": "types.peripherals.OTG_FS_HOST"
+ },
+ "OTG_FS_DEVICE": {
+ "description": "USB on the go full speed",
+ "offset": 1342179328,
+ "type": "types.peripherals.OTG_FS_DEVICE"
+ },
+ "OTG_FS_PWRCLK": {
+ "description": "USB on the go full speed",
+ "offset": 1342180864,
+ "type": "types.peripherals.OTG_FS_PWRCLK"
+ },
+ "CAN1": {
+ "description": "Controller area network",
+ "offset": 1073767424,
+ "type": "types.peripherals.CAN1"
+ },
+ "CAN2": {
+ "offset": 1073768448,
+ "type": "types.peripherals.CAN1"
+ },
+ "FLASH": {
+ "description": "FLASH",
+ "offset": 1073888256,
+ "type": "types.peripherals.FLASH"
+ },
+ "EXTI": {
+ "description": "External interrupt/event\n controller",
+ "offset": 1073822720,
+ "type": "types.peripherals.EXTI"
+ },
+ "OTG_HS_GLOBAL": {
+ "description": "USB on the go high speed",
+ "offset": 1074003968,
+ "type": "types.peripherals.OTG_HS_GLOBAL"
+ },
+ "OTG_HS_HOST": {
+ "description": "USB on the go high speed",
+ "offset": 1074004992,
+ "type": "types.peripherals.OTG_HS_HOST"
+ },
+ "OTG_HS_DEVICE": {
+ "description": "USB on the go high speed",
+ "offset": 1074006016,
+ "type": "types.peripherals.OTG_HS_DEVICE"
+ },
+ "OTG_HS_PWRCLK": {
+ "description": "USB on the go high speed",
+ "offset": 1074007552,
+ "type": "types.peripherals.OTG_HS_PWRCLK"
+ },
+ "NVIC": {
+ "description": "Nested Vectored Interrupt\n Controller",
+ "offset": 3758153984,
+ "type": "types.peripherals.NVIC"
+ },
+ "SAI1": {
+ "description": "Serial audio interface",
+ "offset": 1073829888,
+ "type": "types.peripherals.SAI1"
+ },
+ "LTDC": {
+ "description": "LCD-TFT Controller",
+ "offset": 1073833984,
+ "type": "types.peripherals.LTDC"
+ },
+ "HASH": {
+ "description": "Hash processor",
+ "offset": 1342571520,
+ "type": "types.peripherals.HASH"
+ },
+ "CRYP": {
+ "description": "Cryptographic processor",
+ "offset": 1342570496,
+ "type": "types.peripherals.CRYP"
+ },
+ "FPU": {
+ "description": "Floting point unit",
+ "offset": 3758157620,
+ "type": "types.peripherals.FPU"
+ },
+ "MPU": {
+ "description": "Memory protection unit",
+ "offset": 3758157200,
+ "type": "types.peripherals.MPU"
+ },
+ "STK": {
+ "description": "SysTick timer",
+ "offset": 3758153744,
+ "type": "types.peripherals.STK"
+ },
+ "SCB": {
+ "description": "System control block",
+ "offset": 3758157056,
+ "type": "types.peripherals.SCB"
+ },
+ "NVIC_STIR": {
+ "description": "Nested vectored interrupt\n controller",
+ "offset": 3758157568,
+ "type": "types.peripherals.NVIC_STIR"
+ },
+ "FPU_CPACR": {
+ "description": "Floating point unit CPACR",
+ "offset": 3758157192,
+ "type": "types.peripherals.FPU_CPACR"
+ },
+ "SCB_ACTRL": {
+ "description": "System control block ACTLR",
+ "offset": 3758153736,
+ "type": "types.peripherals.SCB_ACTRL"
+ }
+ }
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/board-support/stmicro-stm32/src/chips/STM32F429.json b/board-support/stmicro-stm32/src/chips/STM32F429.json
new file mode 100644
index 0000000..efbd775
--- /dev/null
+++ b/board-support/stmicro-stm32/src/chips/STM32F429.json
@@ -0,0 +1,52094 @@
+{
+ "version": "0.1.0",
+ "types": {
+ "peripherals": {
+ "RNG": {
+ "description": "Random number generator",
+ "children": {
+ "registers": {
+ "CR": {
+ "description": "control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IE": {
+ "description": "Interrupt enable",
+ "offset": 3,
+ "size": 1
+ },
+ "RNGEN": {
+ "description": "Random number generator\n enable",
+ "offset": 2,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SEIS": {
+ "description": "Seed error interrupt\n status",
+ "offset": 6,
+ "size": 1
+ },
+ "CEIS": {
+ "description": "Clock error interrupt\n status",
+ "offset": 5,
+ "size": 1
+ },
+ "SECS": {
+ "description": "Seed error current status",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "CECS": {
+ "description": "Clock error current status",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "DRDY": {
+ "description": "Data ready",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "DR": {
+ "description": "data register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "RNDATA": {
+ "description": "Random data",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "HASH": {
+ "description": "Hash processor",
+ "children": {
+ "registers": {
+ "CR": {
+ "description": "control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INIT": {
+ "description": "Initialize message digest\n calculation",
+ "offset": 2,
+ "size": 1,
+ "access": "write-only"
+ },
+ "DMAE": {
+ "description": "DMA enable",
+ "offset": 3,
+ "size": 1
+ },
+ "DATATYPE": {
+ "description": "Data type selection",
+ "offset": 4,
+ "size": 2
+ },
+ "MODE": {
+ "description": "Mode selection",
+ "offset": 6,
+ "size": 1
+ },
+ "ALGO0": {
+ "description": "Algorithm selection",
+ "offset": 7,
+ "size": 1
+ },
+ "NBW": {
+ "description": "Number of words already\n pushed",
+ "offset": 8,
+ "size": 4,
+ "access": "read-only"
+ },
+ "DINNE": {
+ "description": "DIN not empty",
+ "offset": 12,
+ "size": 1,
+ "access": "read-only"
+ },
+ "MDMAT": {
+ "description": "Multiple DMA Transfers",
+ "offset": 13,
+ "size": 1
+ },
+ "LKEY": {
+ "description": "Long key selection",
+ "offset": 16,
+ "size": 1
+ },
+ "ALGO1": {
+ "description": "ALGO",
+ "offset": 18,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DIN": {
+ "description": "data input register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATAIN": {
+ "description": "Data input",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "STR": {
+ "description": "start register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DCAL": {
+ "description": "Digest calculation",
+ "offset": 8,
+ "size": 1,
+ "access": "write-only"
+ },
+ "NBLW": {
+ "description": "Number of valid bits in the last word of\n the message",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "HR0": {
+ "description": "digest registers",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "H0": {
+ "description": "H0",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "HR1": {
+ "description": "digest registers",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "H1": {
+ "description": "H1",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "HR2": {
+ "description": "digest registers",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "H2": {
+ "description": "H2",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "HR3": {
+ "description": "digest registers",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "H3": {
+ "description": "H3",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "HR4": {
+ "description": "digest registers",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "H4": {
+ "description": "H4",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "IMR": {
+ "description": "interrupt enable register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DCIE": {
+ "description": "Digest calculation completion interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "DINIE": {
+ "description": "Data input interrupt\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 1,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BUSY": {
+ "description": "Busy bit",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "DMAS": {
+ "description": "DMA Status",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "DCIS": {
+ "description": "Digest calculation completion interrupt\n status",
+ "offset": 1,
+ "size": 1
+ },
+ "DINIS": {
+ "description": "Data input interrupt\n status",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CSR0": {
+ "description": "context swap registers",
+ "offset": 248,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR0": {
+ "description": "CSR0",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR1": {
+ "description": "context swap registers",
+ "offset": 252,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR1": {
+ "description": "CSR1",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR2": {
+ "description": "context swap registers",
+ "offset": 256,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR2": {
+ "description": "CSR2",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR3": {
+ "description": "context swap registers",
+ "offset": 260,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR3": {
+ "description": "CSR3",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR4": {
+ "description": "context swap registers",
+ "offset": 264,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR4": {
+ "description": "CSR4",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR5": {
+ "description": "context swap registers",
+ "offset": 268,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR5": {
+ "description": "CSR5",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR6": {
+ "description": "context swap registers",
+ "offset": 272,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR6": {
+ "description": "CSR6",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR7": {
+ "description": "context swap registers",
+ "offset": 276,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR7": {
+ "description": "CSR7",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR8": {
+ "description": "context swap registers",
+ "offset": 280,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR8": {
+ "description": "CSR8",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR9": {
+ "description": "context swap registers",
+ "offset": 284,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR9": {
+ "description": "CSR9",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR10": {
+ "description": "context swap registers",
+ "offset": 288,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR10": {
+ "description": "CSR10",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR11": {
+ "description": "context swap registers",
+ "offset": 292,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR11": {
+ "description": "CSR11",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR12": {
+ "description": "context swap registers",
+ "offset": 296,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR12": {
+ "description": "CSR12",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR13": {
+ "description": "context swap registers",
+ "offset": 300,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR13": {
+ "description": "CSR13",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR14": {
+ "description": "context swap registers",
+ "offset": 304,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR14": {
+ "description": "CSR14",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR15": {
+ "description": "context swap registers",
+ "offset": 308,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR15": {
+ "description": "CSR15",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR16": {
+ "description": "context swap registers",
+ "offset": 312,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR16": {
+ "description": "CSR16",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR17": {
+ "description": "context swap registers",
+ "offset": 316,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR17": {
+ "description": "CSR17",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR18": {
+ "description": "context swap registers",
+ "offset": 320,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR18": {
+ "description": "CSR18",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR19": {
+ "description": "context swap registers",
+ "offset": 324,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR19": {
+ "description": "CSR19",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR20": {
+ "description": "context swap registers",
+ "offset": 328,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR20": {
+ "description": "CSR20",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR21": {
+ "description": "context swap registers",
+ "offset": 332,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR21": {
+ "description": "CSR21",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR22": {
+ "description": "context swap registers",
+ "offset": 336,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR22": {
+ "description": "CSR22",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR23": {
+ "description": "context swap registers",
+ "offset": 340,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR23": {
+ "description": "CSR23",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR24": {
+ "description": "context swap registers",
+ "offset": 344,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR24": {
+ "description": "CSR24",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR25": {
+ "description": "context swap registers",
+ "offset": 348,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR25": {
+ "description": "CSR25",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR26": {
+ "description": "context swap registers",
+ "offset": 352,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR26": {
+ "description": "CSR26",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR27": {
+ "description": "context swap registers",
+ "offset": 356,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR27": {
+ "description": "CSR27",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR28": {
+ "description": "context swap registers",
+ "offset": 360,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR28": {
+ "description": "CSR28",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR29": {
+ "description": "context swap registers",
+ "offset": 364,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR29": {
+ "description": "CSR29",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR30": {
+ "description": "context swap registers",
+ "offset": 368,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR30": {
+ "description": "CSR30",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR31": {
+ "description": "context swap registers",
+ "offset": 372,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR31": {
+ "description": "CSR31",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR32": {
+ "description": "context swap registers",
+ "offset": 376,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR32": {
+ "description": "CSR32",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR33": {
+ "description": "context swap registers",
+ "offset": 380,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR33": {
+ "description": "CSR33",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR34": {
+ "description": "context swap registers",
+ "offset": 384,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR34": {
+ "description": "CSR34",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR35": {
+ "description": "context swap registers",
+ "offset": 388,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR35": {
+ "description": "CSR35",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR36": {
+ "description": "context swap registers",
+ "offset": 392,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR36": {
+ "description": "CSR36",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR37": {
+ "description": "context swap registers",
+ "offset": 396,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR37": {
+ "description": "CSR37",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR38": {
+ "description": "context swap registers",
+ "offset": 400,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR38": {
+ "description": "CSR38",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR39": {
+ "description": "context swap registers",
+ "offset": 404,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR39": {
+ "description": "CSR39",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR40": {
+ "description": "context swap registers",
+ "offset": 408,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR40": {
+ "description": "CSR40",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR41": {
+ "description": "context swap registers",
+ "offset": 412,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR41": {
+ "description": "CSR41",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR42": {
+ "description": "context swap registers",
+ "offset": 416,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR42": {
+ "description": "CSR42",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR43": {
+ "description": "context swap registers",
+ "offset": 420,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR43": {
+ "description": "CSR43",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR44": {
+ "description": "context swap registers",
+ "offset": 424,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR44": {
+ "description": "CSR44",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR45": {
+ "description": "context swap registers",
+ "offset": 428,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR45": {
+ "description": "CSR45",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR46": {
+ "description": "context swap registers",
+ "offset": 432,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR46": {
+ "description": "CSR46",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR47": {
+ "description": "context swap registers",
+ "offset": 436,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR47": {
+ "description": "CSR47",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR48": {
+ "description": "context swap registers",
+ "offset": 440,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR48": {
+ "description": "CSR48",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR49": {
+ "description": "context swap registers",
+ "offset": 444,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR49": {
+ "description": "CSR49",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR50": {
+ "description": "context swap registers",
+ "offset": 448,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR50": {
+ "description": "CSR50",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR51": {
+ "description": "context swap registers",
+ "offset": 452,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR51": {
+ "description": "CSR51",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR52": {
+ "description": "context swap registers",
+ "offset": 456,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR52": {
+ "description": "CSR52",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSR53": {
+ "description": "context swap registers",
+ "offset": 460,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSR53": {
+ "description": "CSR53",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "HASH_HR0": {
+ "description": "HASH digest register",
+ "offset": 784,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "H0": {
+ "description": "H0",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "HASH_HR1": {
+ "description": "read-only",
+ "offset": 788,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "H1": {
+ "description": "H1",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "HASH_HR2": {
+ "description": "read-only",
+ "offset": 792,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "H2": {
+ "description": "H2",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "HASH_HR3": {
+ "description": "read-only",
+ "offset": 796,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "H3": {
+ "description": "H3",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "HASH_HR4": {
+ "description": "read-only",
+ "offset": 800,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "H4": {
+ "description": "H4",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "HASH_HR5": {
+ "description": "read-only",
+ "offset": 804,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "H5": {
+ "description": "H5",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "HASH_HR6": {
+ "description": "read-only",
+ "offset": 808,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "H6": {
+ "description": "H6",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "HASH_HR7": {
+ "description": "read-only",
+ "offset": 812,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "H7": {
+ "description": "H7",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "CRYP": {
+ "description": "Cryptographic processor",
+ "children": {
+ "registers": {
+ "CR": {
+ "description": "control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ALGODIR": {
+ "description": "Algorithm direction",
+ "offset": 2,
+ "size": 1
+ },
+ "ALGOMODE0": {
+ "description": "Algorithm mode",
+ "offset": 3,
+ "size": 3
+ },
+ "DATATYPE": {
+ "description": "Data type selection",
+ "offset": 6,
+ "size": 2
+ },
+ "KEYSIZE": {
+ "description": "Key size selection (AES mode\n only)",
+ "offset": 8,
+ "size": 2
+ },
+ "FFLUSH": {
+ "description": "FIFO flush",
+ "offset": 14,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CRYPEN": {
+ "description": "Cryptographic processor\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "GCM_CCMPH": {
+ "description": "GCM_CCMPH",
+ "offset": 16,
+ "size": 2
+ },
+ "ALGOMODE3": {
+ "description": "ALGOMODE",
+ "offset": 19,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 3,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "BUSY": {
+ "description": "Busy bit",
+ "offset": 4,
+ "size": 1
+ },
+ "OFFU": {
+ "description": "Output FIFO full",
+ "offset": 3,
+ "size": 1
+ },
+ "OFNE": {
+ "description": "Output FIFO not empty",
+ "offset": 2,
+ "size": 1
+ },
+ "IFNF": {
+ "description": "Input FIFO not full",
+ "offset": 1,
+ "size": 1
+ },
+ "IFEM": {
+ "description": "Input FIFO empty",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DIN": {
+ "description": "data input register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATAIN": {
+ "description": "Data input",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DOUT": {
+ "description": "data output register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DATAOUT": {
+ "description": "Data output",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DMACR": {
+ "description": "DMA control register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DOEN": {
+ "description": "DMA output enable",
+ "offset": 1,
+ "size": 1
+ },
+ "DIEN": {
+ "description": "DMA input enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "IMSCR": {
+ "description": "interrupt mask set/clear\n register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OUTIM": {
+ "description": "Output FIFO service interrupt\n mask",
+ "offset": 1,
+ "size": 1
+ },
+ "INIM": {
+ "description": "Input FIFO service interrupt\n mask",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "RISR": {
+ "description": "raw interrupt status register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 1,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "OUTRIS": {
+ "description": "Output FIFO service raw interrupt\n status",
+ "offset": 1,
+ "size": 1
+ },
+ "INRIS": {
+ "description": "Input FIFO service raw interrupt\n status",
+ "offset": 0,
+ "size": 1
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+ "IV113": {
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+ "IV112": {
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+ "IV111": {
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+ "IV102": {
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+ "IV101": {
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+ "IV100": {
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+ "IV99": {
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+ "IV98": {
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+ "IV97": {
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+ "IV96": {
+ "description": "IV96",
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+ "size": 1
+ }
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+ },
+ "CSGCMCCM0R": {
+ "description": "context swap register",
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+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
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+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCMCCM1R": {
+ "description": "context swap register",
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+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
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+ "description": "CSGCMCCM1R",
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+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCMCCM2R": {
+ "description": "context swap register",
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+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSGCMCCM2R": {
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+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCMCCM3R": {
+ "description": "context swap register",
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+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
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+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCMCCM4R": {
+ "description": "context swap register",
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+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSGCMCCM4R": {
+ "description": "CSGCMCCM4R",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCMCCM5R": {
+ "description": "context swap register",
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+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSGCMCCM5R": {
+ "description": "CSGCMCCM5R",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCMCCM6R": {
+ "description": "context swap register",
+ "offset": 104,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSGCMCCM6R": {
+ "description": "CSGCMCCM6R",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCMCCM7R": {
+ "description": "context swap register",
+ "offset": 108,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSGCMCCM7R": {
+ "description": "CSGCMCCM7R",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCM0R": {
+ "description": "context swap register",
+ "offset": 112,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSGCM0R": {
+ "description": "CSGCM0R",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCM1R": {
+ "description": "context swap register",
+ "offset": 116,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSGCM1R": {
+ "description": "CSGCM1R",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCM2R": {
+ "description": "context swap register",
+ "offset": 120,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSGCM2R": {
+ "description": "CSGCM2R",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCM3R": {
+ "description": "context swap register",
+ "offset": 124,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSGCM3R": {
+ "description": "CSGCM3R",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCM4R": {
+ "description": "context swap register",
+ "offset": 128,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSGCM4R": {
+ "description": "CSGCM4R",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCM5R": {
+ "description": "context swap register",
+ "offset": 132,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSGCM5R": {
+ "description": "CSGCM5R",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCM6R": {
+ "description": "context swap register",
+ "offset": 136,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSGCM6R": {
+ "description": "CSGCM6R",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CSGCM7R": {
+ "description": "context swap register",
+ "offset": 140,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSGCM7R": {
+ "description": "CSGCM7R",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "DCMI": {
+ "description": "Digital camera interface",
+ "children": {
+ "registers": {
+ "CR": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ENABLE": {
+ "description": "DCMI enable",
+ "offset": 14,
+ "size": 1
+ },
+ "EDM": {
+ "description": "Extended data mode",
+ "offset": 10,
+ "size": 2
+ },
+ "FCRC": {
+ "description": "Frame capture rate control",
+ "offset": 8,
+ "size": 2
+ },
+ "VSPOL": {
+ "description": "Vertical synchronization\n polarity",
+ "offset": 7,
+ "size": 1
+ },
+ "HSPOL": {
+ "description": "Horizontal synchronization\n polarity",
+ "offset": 6,
+ "size": 1
+ },
+ "PCKPOL": {
+ "description": "Pixel clock polarity",
+ "offset": 5,
+ "size": 1
+ },
+ "ESS": {
+ "description": "Embedded synchronization\n select",
+ "offset": 4,
+ "size": 1
+ },
+ "JPEG": {
+ "description": "JPEG format",
+ "offset": 3,
+ "size": 1
+ },
+ "CROP": {
+ "description": "Crop feature",
+ "offset": 2,
+ "size": 1
+ },
+ "CM": {
+ "description": "Capture mode",
+ "offset": 1,
+ "size": 1
+ },
+ "CAPTURE": {
+ "description": "Capture enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "FNE": {
+ "description": "FIFO not empty",
+ "offset": 2,
+ "size": 1
+ },
+ "VSYNC": {
+ "description": "VSYNC",
+ "offset": 1,
+ "size": 1
+ },
+ "HSYNC": {
+ "description": "HSYNC",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "RIS": {
+ "description": "raw interrupt status register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "LINE_RIS": {
+ "description": "Line raw interrupt status",
+ "offset": 4,
+ "size": 1
+ },
+ "VSYNC_RIS": {
+ "description": "VSYNC raw interrupt status",
+ "offset": 3,
+ "size": 1
+ },
+ "ERR_RIS": {
+ "description": "Synchronization error raw interrupt\n status",
+ "offset": 2,
+ "size": 1
+ },
+ "OVR_RIS": {
+ "description": "Overrun raw interrupt\n status",
+ "offset": 1,
+ "size": 1
+ },
+ "FRAME_RIS": {
+ "description": "Capture complete raw interrupt\n status",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "IER": {
+ "description": "interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LINE_IE": {
+ "description": "Line interrupt enable",
+ "offset": 4,
+ "size": 1
+ },
+ "VSYNC_IE": {
+ "description": "VSYNC interrupt enable",
+ "offset": 3,
+ "size": 1
+ },
+ "ERR_IE": {
+ "description": "Synchronization error interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "OVR_IE": {
+ "description": "Overrun interrupt enable",
+ "offset": 1,
+ "size": 1
+ },
+ "FRAME_IE": {
+ "description": "Capture complete interrupt\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MIS": {
+ "description": "masked interrupt status\n register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "LINE_MIS": {
+ "description": "Line masked interrupt\n status",
+ "offset": 4,
+ "size": 1
+ },
+ "VSYNC_MIS": {
+ "description": "VSYNC masked interrupt\n status",
+ "offset": 3,
+ "size": 1
+ },
+ "ERR_MIS": {
+ "description": "Synchronization error masked interrupt\n status",
+ "offset": 2,
+ "size": 1
+ },
+ "OVR_MIS": {
+ "description": "Overrun masked interrupt\n status",
+ "offset": 1,
+ "size": 1
+ },
+ "FRAME_MIS": {
+ "description": "Capture complete masked interrupt\n status",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ICR": {
+ "description": "interrupt clear register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "LINE_ISC": {
+ "description": "line interrupt status\n clear",
+ "offset": 4,
+ "size": 1
+ },
+ "VSYNC_ISC": {
+ "description": "Vertical synch interrupt status\n clear",
+ "offset": 3,
+ "size": 1
+ },
+ "ERR_ISC": {
+ "description": "Synchronization error interrupt status\n clear",
+ "offset": 2,
+ "size": 1
+ },
+ "OVR_ISC": {
+ "description": "Overrun interrupt status\n clear",
+ "offset": 1,
+ "size": 1
+ },
+ "FRAME_ISC": {
+ "description": "Capture complete interrupt status\n clear",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ESCR": {
+ "description": "embedded synchronization code\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEC": {
+ "description": "Frame end delimiter code",
+ "offset": 24,
+ "size": 8
+ },
+ "LEC": {
+ "description": "Line end delimiter code",
+ "offset": 16,
+ "size": 8
+ },
+ "LSC": {
+ "description": "Line start delimiter code",
+ "offset": 8,
+ "size": 8
+ },
+ "FSC": {
+ "description": "Frame start delimiter code",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "ESUR": {
+ "description": "embedded synchronization unmask\n register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEU": {
+ "description": "Frame end delimiter unmask",
+ "offset": 24,
+ "size": 8
+ },
+ "LEU": {
+ "description": "Line end delimiter unmask",
+ "offset": 16,
+ "size": 8
+ },
+ "LSU": {
+ "description": "Line start delimiter\n unmask",
+ "offset": 8,
+ "size": 8
+ },
+ "FSU": {
+ "description": "Frame start delimiter\n unmask",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "CWSTRT": {
+ "description": "crop window start",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "VST": {
+ "description": "Vertical start line count",
+ "offset": 16,
+ "size": 13
+ },
+ "HOFFCNT": {
+ "description": "Horizontal offset count",
+ "offset": 0,
+ "size": 14
+ }
+ }
+ }
+ },
+ "CWSIZE": {
+ "description": "crop window size",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "VLINE": {
+ "description": "Vertical line count",
+ "offset": 16,
+ "size": 14
+ },
+ "CAPCNT": {
+ "description": "Capture count",
+ "offset": 0,
+ "size": 14
+ }
+ }
+ }
+ },
+ "DR": {
+ "description": "data register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "Byte3": {
+ "description": "Data byte 3",
+ "offset": 24,
+ "size": 8
+ },
+ "Byte2": {
+ "description": "Data byte 2",
+ "offset": 16,
+ "size": 8
+ },
+ "Byte1": {
+ "description": "Data byte 1",
+ "offset": 8,
+ "size": 8
+ },
+ "Byte0": {
+ "description": "Data byte 0",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "FMC": {
+ "description": "Flexible memory controller",
+ "children": {
+ "registers": {
+ "BCR1": {
+ "description": "SRAM/NOR-Flash chip-select control register\n 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 12496,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCLKEN": {
+ "description": "CCLKEN",
+ "offset": 20,
+ "size": 1
+ },
+ "CBURSTRW": {
+ "description": "CBURSTRW",
+ "offset": 19,
+ "size": 1
+ },
+ "ASYNCWAIT": {
+ "description": "ASYNCWAIT",
+ "offset": 15,
+ "size": 1
+ },
+ "EXTMOD": {
+ "description": "EXTMOD",
+ "offset": 14,
+ "size": 1
+ },
+ "WAITEN": {
+ "description": "WAITEN",
+ "offset": 13,
+ "size": 1
+ },
+ "WREN": {
+ "description": "WREN",
+ "offset": 12,
+ "size": 1
+ },
+ "WAITCFG": {
+ "description": "WAITCFG",
+ "offset": 11,
+ "size": 1
+ },
+ "WAITPOL": {
+ "description": "WAITPOL",
+ "offset": 9,
+ "size": 1
+ },
+ "BURSTEN": {
+ "description": "BURSTEN",
+ "offset": 8,
+ "size": 1
+ },
+ "FACCEN": {
+ "description": "FACCEN",
+ "offset": 6,
+ "size": 1
+ },
+ "MWID": {
+ "description": "MWID",
+ "offset": 4,
+ "size": 2
+ },
+ "MTYP": {
+ "description": "MTYP",
+ "offset": 2,
+ "size": 2
+ },
+ "MUXEN": {
+ "description": "MUXEN",
+ "offset": 1,
+ "size": 1
+ },
+ "MBKEN": {
+ "description": "MBKEN",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BTR1": {
+ "description": "SRAM/NOR-Flash chip-select timing register\n 1",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "BUSTURN": {
+ "description": "BUSTURN",
+ "offset": 16,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "BCR2": {
+ "description": "SRAM/NOR-Flash chip-select control register\n 2",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 12496,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CBURSTRW": {
+ "description": "CBURSTRW",
+ "offset": 19,
+ "size": 1
+ },
+ "ASYNCWAIT": {
+ "description": "ASYNCWAIT",
+ "offset": 15,
+ "size": 1
+ },
+ "EXTMOD": {
+ "description": "EXTMOD",
+ "offset": 14,
+ "size": 1
+ },
+ "WAITEN": {
+ "description": "WAITEN",
+ "offset": 13,
+ "size": 1
+ },
+ "WREN": {
+ "description": "WREN",
+ "offset": 12,
+ "size": 1
+ },
+ "WAITCFG": {
+ "description": "WAITCFG",
+ "offset": 11,
+ "size": 1
+ },
+ "WRAPMOD": {
+ "description": "WRAPMOD",
+ "offset": 10,
+ "size": 1
+ },
+ "WAITPOL": {
+ "description": "WAITPOL",
+ "offset": 9,
+ "size": 1
+ },
+ "BURSTEN": {
+ "description": "BURSTEN",
+ "offset": 8,
+ "size": 1
+ },
+ "FACCEN": {
+ "description": "FACCEN",
+ "offset": 6,
+ "size": 1
+ },
+ "MWID": {
+ "description": "MWID",
+ "offset": 4,
+ "size": 2
+ },
+ "MTYP": {
+ "description": "MTYP",
+ "offset": 2,
+ "size": 2
+ },
+ "MUXEN": {
+ "description": "MUXEN",
+ "offset": 1,
+ "size": 1
+ },
+ "MBKEN": {
+ "description": "MBKEN",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BTR2": {
+ "description": "SRAM/NOR-Flash chip-select timing register\n 2",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "BUSTURN": {
+ "description": "BUSTURN",
+ "offset": 16,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "BCR3": {
+ "description": "SRAM/NOR-Flash chip-select control register\n 3",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 12496,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CBURSTRW": {
+ "description": "CBURSTRW",
+ "offset": 19,
+ "size": 1
+ },
+ "ASYNCWAIT": {
+ "description": "ASYNCWAIT",
+ "offset": 15,
+ "size": 1
+ },
+ "EXTMOD": {
+ "description": "EXTMOD",
+ "offset": 14,
+ "size": 1
+ },
+ "WAITEN": {
+ "description": "WAITEN",
+ "offset": 13,
+ "size": 1
+ },
+ "WREN": {
+ "description": "WREN",
+ "offset": 12,
+ "size": 1
+ },
+ "WAITCFG": {
+ "description": "WAITCFG",
+ "offset": 11,
+ "size": 1
+ },
+ "WRAPMOD": {
+ "description": "WRAPMOD",
+ "offset": 10,
+ "size": 1
+ },
+ "WAITPOL": {
+ "description": "WAITPOL",
+ "offset": 9,
+ "size": 1
+ },
+ "BURSTEN": {
+ "description": "BURSTEN",
+ "offset": 8,
+ "size": 1
+ },
+ "FACCEN": {
+ "description": "FACCEN",
+ "offset": 6,
+ "size": 1
+ },
+ "MWID": {
+ "description": "MWID",
+ "offset": 4,
+ "size": 2
+ },
+ "MTYP": {
+ "description": "MTYP",
+ "offset": 2,
+ "size": 2
+ },
+ "MUXEN": {
+ "description": "MUXEN",
+ "offset": 1,
+ "size": 1
+ },
+ "MBKEN": {
+ "description": "MBKEN",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BTR3": {
+ "description": "SRAM/NOR-Flash chip-select timing register\n 3",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "BUSTURN": {
+ "description": "BUSTURN",
+ "offset": 16,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "BCR4": {
+ "description": "SRAM/NOR-Flash chip-select control register\n 4",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 12496,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CBURSTRW": {
+ "description": "CBURSTRW",
+ "offset": 19,
+ "size": 1
+ },
+ "ASYNCWAIT": {
+ "description": "ASYNCWAIT",
+ "offset": 15,
+ "size": 1
+ },
+ "EXTMOD": {
+ "description": "EXTMOD",
+ "offset": 14,
+ "size": 1
+ },
+ "WAITEN": {
+ "description": "WAITEN",
+ "offset": 13,
+ "size": 1
+ },
+ "WREN": {
+ "description": "WREN",
+ "offset": 12,
+ "size": 1
+ },
+ "WAITCFG": {
+ "description": "WAITCFG",
+ "offset": 11,
+ "size": 1
+ },
+ "WRAPMOD": {
+ "description": "WRAPMOD",
+ "offset": 10,
+ "size": 1
+ },
+ "WAITPOL": {
+ "description": "WAITPOL",
+ "offset": 9,
+ "size": 1
+ },
+ "BURSTEN": {
+ "description": "BURSTEN",
+ "offset": 8,
+ "size": 1
+ },
+ "FACCEN": {
+ "description": "FACCEN",
+ "offset": 6,
+ "size": 1
+ },
+ "MWID": {
+ "description": "MWID",
+ "offset": 4,
+ "size": 2
+ },
+ "MTYP": {
+ "description": "MTYP",
+ "offset": 2,
+ "size": 2
+ },
+ "MUXEN": {
+ "description": "MUXEN",
+ "offset": 1,
+ "size": 1
+ },
+ "MBKEN": {
+ "description": "MBKEN",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BTR4": {
+ "description": "SRAM/NOR-Flash chip-select timing register\n 4",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "BUSTURN": {
+ "description": "BUSTURN",
+ "offset": 16,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "PCR2": {
+ "description": "PC Card/NAND Flash control register\n 2",
+ "offset": 96,
+ "size": 32,
+ "reset_value": 24,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ECCPS": {
+ "description": "ECCPS",
+ "offset": 17,
+ "size": 3
+ },
+ "TAR": {
+ "description": "TAR",
+ "offset": 13,
+ "size": 4
+ },
+ "TCLR": {
+ "description": "TCLR",
+ "offset": 9,
+ "size": 4
+ },
+ "ECCEN": {
+ "description": "ECCEN",
+ "offset": 6,
+ "size": 1
+ },
+ "PWID": {
+ "description": "PWID",
+ "offset": 4,
+ "size": 2
+ },
+ "PTYP": {
+ "description": "PTYP",
+ "offset": 3,
+ "size": 1
+ },
+ "PBKEN": {
+ "description": "PBKEN",
+ "offset": 2,
+ "size": 1
+ },
+ "PWAITEN": {
+ "description": "PWAITEN",
+ "offset": 1,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR2": {
+ "description": "FIFO status and interrupt register\n 2",
+ "offset": 100,
+ "size": 32,
+ "reset_value": 64,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEMPT": {
+ "description": "FEMPT",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "IFEN": {
+ "description": "IFEN",
+ "offset": 5,
+ "size": 1
+ },
+ "ILEN": {
+ "description": "ILEN",
+ "offset": 4,
+ "size": 1
+ },
+ "IREN": {
+ "description": "IREN",
+ "offset": 3,
+ "size": 1
+ },
+ "IFS": {
+ "description": "IFS",
+ "offset": 2,
+ "size": 1
+ },
+ "ILS": {
+ "description": "ILS",
+ "offset": 1,
+ "size": 1
+ },
+ "IRS": {
+ "description": "IRS",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PMEM2": {
+ "description": "Common memory space timing register\n 2",
+ "offset": 104,
+ "size": 32,
+ "reset_value": 4244438268,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MEMHIZx": {
+ "description": "MEMHIZx",
+ "offset": 24,
+ "size": 8
+ },
+ "MEMHOLDx": {
+ "description": "MEMHOLDx",
+ "offset": 16,
+ "size": 8
+ },
+ "MEMWAITx": {
+ "description": "MEMWAITx",
+ "offset": 8,
+ "size": 8
+ },
+ "MEMSETx": {
+ "description": "MEMSETx",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "PATT2": {
+ "description": "Attribute memory space timing register\n 2",
+ "offset": 108,
+ "size": 32,
+ "reset_value": 4244438268,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ATTHIZx": {
+ "description": "ATTHIZx",
+ "offset": 24,
+ "size": 8
+ },
+ "ATTHOLDx": {
+ "description": "ATTHOLDx",
+ "offset": 16,
+ "size": 8
+ },
+ "ATTWAITx": {
+ "description": "ATTWAITx",
+ "offset": 8,
+ "size": 8
+ },
+ "ATTSETx": {
+ "description": "ATTSETx",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "ECCR2": {
+ "description": "ECC result register 2",
+ "offset": 116,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "ECCx": {
+ "description": "ECCx",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "PCR3": {
+ "description": "PC Card/NAND Flash control register\n 3",
+ "offset": 128,
+ "size": 32,
+ "reset_value": 24,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ECCPS": {
+ "description": "ECCPS",
+ "offset": 17,
+ "size": 3
+ },
+ "TAR": {
+ "description": "TAR",
+ "offset": 13,
+ "size": 4
+ },
+ "TCLR": {
+ "description": "TCLR",
+ "offset": 9,
+ "size": 4
+ },
+ "ECCEN": {
+ "description": "ECCEN",
+ "offset": 6,
+ "size": 1
+ },
+ "PWID": {
+ "description": "PWID",
+ "offset": 4,
+ "size": 2
+ },
+ "PTYP": {
+ "description": "PTYP",
+ "offset": 3,
+ "size": 1
+ },
+ "PBKEN": {
+ "description": "PBKEN",
+ "offset": 2,
+ "size": 1
+ },
+ "PWAITEN": {
+ "description": "PWAITEN",
+ "offset": 1,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR3": {
+ "description": "FIFO status and interrupt register\n 3",
+ "offset": 132,
+ "size": 32,
+ "reset_value": 64,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEMPT": {
+ "description": "FEMPT",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "IFEN": {
+ "description": "IFEN",
+ "offset": 5,
+ "size": 1
+ },
+ "ILEN": {
+ "description": "ILEN",
+ "offset": 4,
+ "size": 1
+ },
+ "IREN": {
+ "description": "IREN",
+ "offset": 3,
+ "size": 1
+ },
+ "IFS": {
+ "description": "IFS",
+ "offset": 2,
+ "size": 1
+ },
+ "ILS": {
+ "description": "ILS",
+ "offset": 1,
+ "size": 1
+ },
+ "IRS": {
+ "description": "IRS",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PMEM3": {
+ "description": "Common memory space timing register\n 3",
+ "offset": 136,
+ "size": 32,
+ "reset_value": 4244438268,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MEMHIZx": {
+ "description": "MEMHIZx",
+ "offset": 24,
+ "size": 8
+ },
+ "MEMHOLDx": {
+ "description": "MEMHOLDx",
+ "offset": 16,
+ "size": 8
+ },
+ "MEMWAITx": {
+ "description": "MEMWAITx",
+ "offset": 8,
+ "size": 8
+ },
+ "MEMSETx": {
+ "description": "MEMSETx",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "PATT3": {
+ "description": "Attribute memory space timing register\n 3",
+ "offset": 140,
+ "size": 32,
+ "reset_value": 4244438268,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ATTHIZx": {
+ "description": "ATTHIZx",
+ "offset": 24,
+ "size": 8
+ },
+ "ATTHOLDx": {
+ "description": "ATTHOLDx",
+ "offset": 16,
+ "size": 8
+ },
+ "ATTWAITx": {
+ "description": "ATTWAITx",
+ "offset": 8,
+ "size": 8
+ },
+ "ATTSETx": {
+ "description": "ATTSETx",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "ECCR3": {
+ "description": "ECC result register 3",
+ "offset": 148,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "ECCx": {
+ "description": "ECCx",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "PCR4": {
+ "description": "PC Card/NAND Flash control register\n 4",
+ "offset": 160,
+ "size": 32,
+ "reset_value": 24,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ECCPS": {
+ "description": "ECCPS",
+ "offset": 17,
+ "size": 3
+ },
+ "TAR": {
+ "description": "TAR",
+ "offset": 13,
+ "size": 4
+ },
+ "TCLR": {
+ "description": "TCLR",
+ "offset": 9,
+ "size": 4
+ },
+ "ECCEN": {
+ "description": "ECCEN",
+ "offset": 6,
+ "size": 1
+ },
+ "PWID": {
+ "description": "PWID",
+ "offset": 4,
+ "size": 2
+ },
+ "PTYP": {
+ "description": "PTYP",
+ "offset": 3,
+ "size": 1
+ },
+ "PBKEN": {
+ "description": "PBKEN",
+ "offset": 2,
+ "size": 1
+ },
+ "PWAITEN": {
+ "description": "PWAITEN",
+ "offset": 1,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR4": {
+ "description": "FIFO status and interrupt register\n 4",
+ "offset": 164,
+ "size": 32,
+ "reset_value": 64,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEMPT": {
+ "description": "FEMPT",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "IFEN": {
+ "description": "IFEN",
+ "offset": 5,
+ "size": 1
+ },
+ "ILEN": {
+ "description": "ILEN",
+ "offset": 4,
+ "size": 1
+ },
+ "IREN": {
+ "description": "IREN",
+ "offset": 3,
+ "size": 1
+ },
+ "IFS": {
+ "description": "IFS",
+ "offset": 2,
+ "size": 1
+ },
+ "ILS": {
+ "description": "ILS",
+ "offset": 1,
+ "size": 1
+ },
+ "IRS": {
+ "description": "IRS",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PMEM4": {
+ "description": "Common memory space timing register\n 4",
+ "offset": 168,
+ "size": 32,
+ "reset_value": 4244438268,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MEMHIZx": {
+ "description": "MEMHIZx",
+ "offset": 24,
+ "size": 8
+ },
+ "MEMHOLDx": {
+ "description": "MEMHOLDx",
+ "offset": 16,
+ "size": 8
+ },
+ "MEMWAITx": {
+ "description": "MEMWAITx",
+ "offset": 8,
+ "size": 8
+ },
+ "MEMSETx": {
+ "description": "MEMSETx",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "PATT4": {
+ "description": "Attribute memory space timing register\n 4",
+ "offset": 172,
+ "size": 32,
+ "reset_value": 4244438268,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ATTHIZx": {
+ "description": "ATTHIZx",
+ "offset": 24,
+ "size": 8
+ },
+ "ATTHOLDx": {
+ "description": "ATTHOLDx",
+ "offset": 16,
+ "size": 8
+ },
+ "ATTWAITx": {
+ "description": "ATTWAITx",
+ "offset": 8,
+ "size": 8
+ },
+ "ATTSETx": {
+ "description": "ATTSETx",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "PIO4": {
+ "description": "I/O space timing register 4",
+ "offset": 176,
+ "size": 32,
+ "reset_value": 4244438268,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IOHIZx": {
+ "description": "IOHIZx",
+ "offset": 24,
+ "size": 8
+ },
+ "IOHOLDx": {
+ "description": "IOHOLDx",
+ "offset": 16,
+ "size": 8
+ },
+ "IOWAITx": {
+ "description": "IOWAITx",
+ "offset": 8,
+ "size": 8
+ },
+ "IOSETx": {
+ "description": "IOSETx",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "BWTR1": {
+ "description": "SRAM/NOR-Flash write timing registers\n 1",
+ "offset": 260,
+ "size": 32,
+ "reset_value": 268435455,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "BWTR2": {
+ "description": "SRAM/NOR-Flash write timing registers\n 2",
+ "offset": 268,
+ "size": 32,
+ "reset_value": 268435455,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "BWTR3": {
+ "description": "SRAM/NOR-Flash write timing registers\n 3",
+ "offset": 260,
+ "size": 32,
+ "reset_value": 268435455,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "BWTR4": {
+ "description": "SRAM/NOR-Flash write timing registers\n 4",
+ "offset": 268,
+ "size": 32,
+ "reset_value": 268435455,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ACCMOD": {
+ "description": "ACCMOD",
+ "offset": 28,
+ "size": 2
+ },
+ "DATLAT": {
+ "description": "DATLAT",
+ "offset": 24,
+ "size": 4
+ },
+ "CLKDIV": {
+ "description": "CLKDIV",
+ "offset": 20,
+ "size": 4
+ },
+ "DATAST": {
+ "description": "DATAST",
+ "offset": 8,
+ "size": 8
+ },
+ "ADDHLD": {
+ "description": "ADDHLD",
+ "offset": 4,
+ "size": 4
+ },
+ "ADDSET": {
+ "description": "ADDSET",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "SDCR1": {
+ "description": "SDRAM Control Register 1",
+ "offset": 320,
+ "size": 32,
+ "reset_value": 720,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NC": {
+ "description": "Number of column address\n bits",
+ "offset": 0,
+ "size": 2
+ },
+ "NR": {
+ "description": "Number of row address bits",
+ "offset": 2,
+ "size": 2
+ },
+ "MWID": {
+ "description": "Memory data bus width",
+ "offset": 4,
+ "size": 2
+ },
+ "NB": {
+ "description": "Number of internal banks",
+ "offset": 6,
+ "size": 1
+ },
+ "CAS": {
+ "description": "CAS latency",
+ "offset": 7,
+ "size": 2
+ },
+ "WP": {
+ "description": "Write protection",
+ "offset": 9,
+ "size": 1
+ },
+ "SDCLK": {
+ "description": "SDRAM clock configuration",
+ "offset": 10,
+ "size": 2
+ },
+ "RBURST": {
+ "description": "Burst read",
+ "offset": 12,
+ "size": 1
+ },
+ "RPIPE": {
+ "description": "Read pipe",
+ "offset": 13,
+ "size": 2
+ }
+ }
+ }
+ },
+ "SDCR2": {
+ "description": "SDRAM Control Register 2",
+ "offset": 324,
+ "size": 32,
+ "reset_value": 720,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NC": {
+ "description": "Number of column address\n bits",
+ "offset": 0,
+ "size": 2
+ },
+ "NR": {
+ "description": "Number of row address bits",
+ "offset": 2,
+ "size": 2
+ },
+ "MWID": {
+ "description": "Memory data bus width",
+ "offset": 4,
+ "size": 2
+ },
+ "NB": {
+ "description": "Number of internal banks",
+ "offset": 6,
+ "size": 1
+ },
+ "CAS": {
+ "description": "CAS latency",
+ "offset": 7,
+ "size": 2
+ },
+ "WP": {
+ "description": "Write protection",
+ "offset": 9,
+ "size": 1
+ },
+ "SDCLK": {
+ "description": "SDRAM clock configuration",
+ "offset": 10,
+ "size": 2
+ },
+ "RBURST": {
+ "description": "Burst read",
+ "offset": 12,
+ "size": 1
+ },
+ "RPIPE": {
+ "description": "Read pipe",
+ "offset": 13,
+ "size": 2
+ }
+ }
+ }
+ },
+ "SDTR1": {
+ "description": "SDRAM Timing register 1",
+ "offset": 328,
+ "size": 32,
+ "reset_value": 268435455,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TMRD": {
+ "description": "Load Mode Register to\n Active",
+ "offset": 0,
+ "size": 4
+ },
+ "TXSR": {
+ "description": "Exit self-refresh delay",
+ "offset": 4,
+ "size": 4
+ },
+ "TRAS": {
+ "description": "Self refresh time",
+ "offset": 8,
+ "size": 4
+ },
+ "TRC": {
+ "description": "Row cycle delay",
+ "offset": 12,
+ "size": 4
+ },
+ "TWR": {
+ "description": "Recovery delay",
+ "offset": 16,
+ "size": 4
+ },
+ "TRP": {
+ "description": "Row precharge delay",
+ "offset": 20,
+ "size": 4
+ },
+ "TRCD": {
+ "description": "Row to column delay",
+ "offset": 24,
+ "size": 4
+ }
+ }
+ }
+ },
+ "SDTR2": {
+ "description": "SDRAM Timing register 2",
+ "offset": 332,
+ "size": 32,
+ "reset_value": 268435455,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TMRD": {
+ "description": "Load Mode Register to\n Active",
+ "offset": 0,
+ "size": 4
+ },
+ "TXSR": {
+ "description": "Exit self-refresh delay",
+ "offset": 4,
+ "size": 4
+ },
+ "TRAS": {
+ "description": "Self refresh time",
+ "offset": 8,
+ "size": 4
+ },
+ "TRC": {
+ "description": "Row cycle delay",
+ "offset": 12,
+ "size": 4
+ },
+ "TWR": {
+ "description": "Recovery delay",
+ "offset": 16,
+ "size": 4
+ },
+ "TRP": {
+ "description": "Row precharge delay",
+ "offset": 20,
+ "size": 4
+ },
+ "TRCD": {
+ "description": "Row to column delay",
+ "offset": 24,
+ "size": 4
+ }
+ }
+ }
+ },
+ "SDCMR": {
+ "description": "SDRAM Command Mode register",
+ "offset": 336,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MODE": {
+ "description": "Command mode",
+ "offset": 0,
+ "size": 3,
+ "access": "write-only"
+ },
+ "CTB2": {
+ "description": "Command target bank 2",
+ "offset": 3,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CTB1": {
+ "description": "Command target bank 1",
+ "offset": 4,
+ "size": 1,
+ "access": "write-only"
+ },
+ "NRFS": {
+ "description": "Number of Auto-refresh",
+ "offset": 5,
+ "size": 4
+ },
+ "MRD": {
+ "description": "Mode Register definition",
+ "offset": 9,
+ "size": 13
+ }
+ }
+ }
+ },
+ "SDRTR": {
+ "description": "SDRAM Refresh Timer register",
+ "offset": 340,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CRE": {
+ "description": "Clear Refresh error flag",
+ "offset": 0,
+ "size": 1,
+ "access": "write-only"
+ },
+ "COUNT": {
+ "description": "Refresh Timer Count",
+ "offset": 1,
+ "size": 13
+ },
+ "REIE": {
+ "description": "RES Interrupt Enable",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SDSR": {
+ "description": "SDRAM Status register",
+ "offset": 344,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "RE": {
+ "description": "Refresh error flag",
+ "offset": 0,
+ "size": 1
+ },
+ "MODES1": {
+ "description": "Status Mode for Bank 1",
+ "offset": 1,
+ "size": 2
+ },
+ "MODES2": {
+ "description": "Status Mode for Bank 2",
+ "offset": 3,
+ "size": 2
+ },
+ "BUSY": {
+ "description": "Busy status",
+ "offset": 5,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "DBG": {
+ "description": "Debug support",
+ "children": {
+ "registers": {
+ "DBGMCU_IDCODE": {
+ "description": "IDCODE",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 268461073,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DEV_ID": {
+ "description": "DEV_ID",
+ "offset": 0,
+ "size": 12
+ },
+ "REV_ID": {
+ "description": "REV_ID",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DBGMCU_CR": {
+ "description": "Control Register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBG_SLEEP": {
+ "description": "DBG_SLEEP",
+ "offset": 0,
+ "size": 1
+ },
+ "DBG_STOP": {
+ "description": "DBG_STOP",
+ "offset": 1,
+ "size": 1
+ },
+ "DBG_STANDBY": {
+ "description": "DBG_STANDBY",
+ "offset": 2,
+ "size": 1
+ },
+ "TRACE_IOEN": {
+ "description": "TRACE_IOEN",
+ "offset": 5,
+ "size": 1
+ },
+ "TRACE_MODE": {
+ "description": "TRACE_MODE",
+ "offset": 6,
+ "size": 2
+ }
+ }
+ }
+ },
+ "DBGMCU_APB1_FZ": {
+ "description": "Debug MCU APB1 Freeze registe",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBG_TIM2_STOP": {
+ "description": "DBG_TIM2_STOP",
+ "offset": 0,
+ "size": 1
+ },
+ "DBG_TIM3_STOP": {
+ "description": "DBG_TIM3 _STOP",
+ "offset": 1,
+ "size": 1
+ },
+ "DBG_TIM4_STOP": {
+ "description": "DBG_TIM4_STOP",
+ "offset": 2,
+ "size": 1
+ },
+ "DBG_TIM5_STOP": {
+ "description": "DBG_TIM5_STOP",
+ "offset": 3,
+ "size": 1
+ },
+ "DBG_TIM6_STOP": {
+ "description": "DBG_TIM6_STOP",
+ "offset": 4,
+ "size": 1
+ },
+ "DBG_TIM7_STOP": {
+ "description": "DBG_TIM7_STOP",
+ "offset": 5,
+ "size": 1
+ },
+ "DBG_TIM12_STOP": {
+ "description": "DBG_TIM12_STOP",
+ "offset": 6,
+ "size": 1
+ },
+ "DBG_TIM13_STOP": {
+ "description": "DBG_TIM13_STOP",
+ "offset": 7,
+ "size": 1
+ },
+ "DBG_TIM14_STOP": {
+ "description": "DBG_TIM14_STOP",
+ "offset": 8,
+ "size": 1
+ },
+ "DBG_WWDG_STOP": {
+ "description": "DBG_WWDG_STOP",
+ "offset": 11,
+ "size": 1
+ },
+ "DBG_IWDEG_STOP": {
+ "description": "DBG_IWDEG_STOP",
+ "offset": 12,
+ "size": 1
+ },
+ "DBG_J2C1_SMBUS_TIMEOUT": {
+ "description": "DBG_J2C1_SMBUS_TIMEOUT",
+ "offset": 21,
+ "size": 1
+ },
+ "DBG_J2C2_SMBUS_TIMEOUT": {
+ "description": "DBG_J2C2_SMBUS_TIMEOUT",
+ "offset": 22,
+ "size": 1
+ },
+ "DBG_J2C3SMBUS_TIMEOUT": {
+ "description": "DBG_J2C3SMBUS_TIMEOUT",
+ "offset": 23,
+ "size": 1
+ },
+ "DBG_CAN1_STOP": {
+ "description": "DBG_CAN1_STOP",
+ "offset": 25,
+ "size": 1
+ },
+ "DBG_CAN2_STOP": {
+ "description": "DBG_CAN2_STOP",
+ "offset": 26,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DBGMCU_APB2_FZ": {
+ "description": "Debug MCU APB2 Freeze registe",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBG_TIM1_STOP": {
+ "description": "TIM1 counter stopped when core is\n halted",
+ "offset": 0,
+ "size": 1
+ },
+ "DBG_TIM8_STOP": {
+ "description": "TIM8 counter stopped when core is\n halted",
+ "offset": 1,
+ "size": 1
+ },
+ "DBG_TIM9_STOP": {
+ "description": "TIM9 counter stopped when core is\n halted",
+ "offset": 16,
+ "size": 1
+ },
+ "DBG_TIM10_STOP": {
+ "description": "TIM10 counter stopped when core is\n halted",
+ "offset": 17,
+ "size": 1
+ },
+ "DBG_TIM11_STOP": {
+ "description": "TIM11 counter stopped when core is\n halted",
+ "offset": 18,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "DMA2": {
+ "description": "DMA controller",
+ "children": {
+ "registers": {
+ "LISR": {
+ "description": "low interrupt status register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "TCIF3": {
+ "description": "Stream x transfer complete interrupt\n flag (x = 3..0)",
+ "offset": 27,
+ "size": 1
+ },
+ "HTIF3": {
+ "description": "Stream x half transfer interrupt flag\n (x=3..0)",
+ "offset": 26,
+ "size": 1
+ },
+ "TEIF3": {
+ "description": "Stream x transfer error interrupt flag\n (x=3..0)",
+ "offset": 25,
+ "size": 1
+ },
+ "DMEIF3": {
+ "description": "Stream x direct mode error interrupt\n flag (x=3..0)",
+ "offset": 24,
+ "size": 1
+ },
+ "FEIF3": {
+ "description": "Stream x FIFO error interrupt flag\n (x=3..0)",
+ "offset": 22,
+ "size": 1
+ },
+ "TCIF2": {
+ "description": "Stream x transfer complete interrupt\n flag (x = 3..0)",
+ "offset": 21,
+ "size": 1
+ },
+ "HTIF2": {
+ "description": "Stream x half transfer interrupt flag\n (x=3..0)",
+ "offset": 20,
+ "size": 1
+ },
+ "TEIF2": {
+ "description": "Stream x transfer error interrupt flag\n (x=3..0)",
+ "offset": 19,
+ "size": 1
+ },
+ "DMEIF2": {
+ "description": "Stream x direct mode error interrupt\n flag (x=3..0)",
+ "offset": 18,
+ "size": 1
+ },
+ "FEIF2": {
+ "description": "Stream x FIFO error interrupt flag\n (x=3..0)",
+ "offset": 16,
+ "size": 1
+ },
+ "TCIF1": {
+ "description": "Stream x transfer complete interrupt\n flag (x = 3..0)",
+ "offset": 11,
+ "size": 1
+ },
+ "HTIF1": {
+ "description": "Stream x half transfer interrupt flag\n (x=3..0)",
+ "offset": 10,
+ "size": 1
+ },
+ "TEIF1": {
+ "description": "Stream x transfer error interrupt flag\n (x=3..0)",
+ "offset": 9,
+ "size": 1
+ },
+ "DMEIF1": {
+ "description": "Stream x direct mode error interrupt\n flag (x=3..0)",
+ "offset": 8,
+ "size": 1
+ },
+ "FEIF1": {
+ "description": "Stream x FIFO error interrupt flag\n (x=3..0)",
+ "offset": 6,
+ "size": 1
+ },
+ "TCIF0": {
+ "description": "Stream x transfer complete interrupt\n flag (x = 3..0)",
+ "offset": 5,
+ "size": 1
+ },
+ "HTIF0": {
+ "description": "Stream x half transfer interrupt flag\n (x=3..0)",
+ "offset": 4,
+ "size": 1
+ },
+ "TEIF0": {
+ "description": "Stream x transfer error interrupt flag\n (x=3..0)",
+ "offset": 3,
+ "size": 1
+ },
+ "DMEIF0": {
+ "description": "Stream x direct mode error interrupt\n flag (x=3..0)",
+ "offset": 2,
+ "size": 1
+ },
+ "FEIF0": {
+ "description": "Stream x FIFO error interrupt flag\n (x=3..0)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "HISR": {
+ "description": "high interrupt status register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "TCIF7": {
+ "description": "Stream x transfer complete interrupt\n flag (x=7..4)",
+ "offset": 27,
+ "size": 1
+ },
+ "HTIF7": {
+ "description": "Stream x half transfer interrupt flag\n (x=7..4)",
+ "offset": 26,
+ "size": 1
+ },
+ "TEIF7": {
+ "description": "Stream x transfer error interrupt flag\n (x=7..4)",
+ "offset": 25,
+ "size": 1
+ },
+ "DMEIF7": {
+ "description": "Stream x direct mode error interrupt\n flag (x=7..4)",
+ "offset": 24,
+ "size": 1
+ },
+ "FEIF7": {
+ "description": "Stream x FIFO error interrupt flag\n (x=7..4)",
+ "offset": 22,
+ "size": 1
+ },
+ "TCIF6": {
+ "description": "Stream x transfer complete interrupt\n flag (x=7..4)",
+ "offset": 21,
+ "size": 1
+ },
+ "HTIF6": {
+ "description": "Stream x half transfer interrupt flag\n (x=7..4)",
+ "offset": 20,
+ "size": 1
+ },
+ "TEIF6": {
+ "description": "Stream x transfer error interrupt flag\n (x=7..4)",
+ "offset": 19,
+ "size": 1
+ },
+ "DMEIF6": {
+ "description": "Stream x direct mode error interrupt\n flag (x=7..4)",
+ "offset": 18,
+ "size": 1
+ },
+ "FEIF6": {
+ "description": "Stream x FIFO error interrupt flag\n (x=7..4)",
+ "offset": 16,
+ "size": 1
+ },
+ "TCIF5": {
+ "description": "Stream x transfer complete interrupt\n flag (x=7..4)",
+ "offset": 11,
+ "size": 1
+ },
+ "HTIF5": {
+ "description": "Stream x half transfer interrupt flag\n (x=7..4)",
+ "offset": 10,
+ "size": 1
+ },
+ "TEIF5": {
+ "description": "Stream x transfer error interrupt flag\n (x=7..4)",
+ "offset": 9,
+ "size": 1
+ },
+ "DMEIF5": {
+ "description": "Stream x direct mode error interrupt\n flag (x=7..4)",
+ "offset": 8,
+ "size": 1
+ },
+ "FEIF5": {
+ "description": "Stream x FIFO error interrupt flag\n (x=7..4)",
+ "offset": 6,
+ "size": 1
+ },
+ "TCIF4": {
+ "description": "Stream x transfer complete interrupt\n flag (x=7..4)",
+ "offset": 5,
+ "size": 1
+ },
+ "HTIF4": {
+ "description": "Stream x half transfer interrupt flag\n (x=7..4)",
+ "offset": 4,
+ "size": 1
+ },
+ "TEIF4": {
+ "description": "Stream x transfer error interrupt flag\n (x=7..4)",
+ "offset": 3,
+ "size": 1
+ },
+ "DMEIF4": {
+ "description": "Stream x direct mode error interrupt\n flag (x=7..4)",
+ "offset": 2,
+ "size": 1
+ },
+ "FEIF4": {
+ "description": "Stream x FIFO error interrupt flag\n (x=7..4)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "LIFCR": {
+ "description": "low interrupt flag clear\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CTCIF3": {
+ "description": "Stream x clear transfer complete\n interrupt flag (x = 3..0)",
+ "offset": 27,
+ "size": 1
+ },
+ "CHTIF3": {
+ "description": "Stream x clear half transfer interrupt\n flag (x = 3..0)",
+ "offset": 26,
+ "size": 1
+ },
+ "CTEIF3": {
+ "description": "Stream x clear transfer error interrupt\n flag (x = 3..0)",
+ "offset": 25,
+ "size": 1
+ },
+ "CDMEIF3": {
+ "description": "Stream x clear direct mode error\n interrupt flag (x = 3..0)",
+ "offset": 24,
+ "size": 1
+ },
+ "CFEIF3": {
+ "description": "Stream x clear FIFO error interrupt flag\n (x = 3..0)",
+ "offset": 22,
+ "size": 1
+ },
+ "CTCIF2": {
+ "description": "Stream x clear transfer complete\n interrupt flag (x = 3..0)",
+ "offset": 21,
+ "size": 1
+ },
+ "CHTIF2": {
+ "description": "Stream x clear half transfer interrupt\n flag (x = 3..0)",
+ "offset": 20,
+ "size": 1
+ },
+ "CTEIF2": {
+ "description": "Stream x clear transfer error interrupt\n flag (x = 3..0)",
+ "offset": 19,
+ "size": 1
+ },
+ "CDMEIF2": {
+ "description": "Stream x clear direct mode error\n interrupt flag (x = 3..0)",
+ "offset": 18,
+ "size": 1
+ },
+ "CFEIF2": {
+ "description": "Stream x clear FIFO error interrupt flag\n (x = 3..0)",
+ "offset": 16,
+ "size": 1
+ },
+ "CTCIF1": {
+ "description": "Stream x clear transfer complete\n interrupt flag (x = 3..0)",
+ "offset": 11,
+ "size": 1
+ },
+ "CHTIF1": {
+ "description": "Stream x clear half transfer interrupt\n flag (x = 3..0)",
+ "offset": 10,
+ "size": 1
+ },
+ "CTEIF1": {
+ "description": "Stream x clear transfer error interrupt\n flag (x = 3..0)",
+ "offset": 9,
+ "size": 1
+ },
+ "CDMEIF1": {
+ "description": "Stream x clear direct mode error\n interrupt flag (x = 3..0)",
+ "offset": 8,
+ "size": 1
+ },
+ "CFEIF1": {
+ "description": "Stream x clear FIFO error interrupt flag\n (x = 3..0)",
+ "offset": 6,
+ "size": 1
+ },
+ "CTCIF0": {
+ "description": "Stream x clear transfer complete\n interrupt flag (x = 3..0)",
+ "offset": 5,
+ "size": 1
+ },
+ "CHTIF0": {
+ "description": "Stream x clear half transfer interrupt\n flag (x = 3..0)",
+ "offset": 4,
+ "size": 1
+ },
+ "CTEIF0": {
+ "description": "Stream x clear transfer error interrupt\n flag (x = 3..0)",
+ "offset": 3,
+ "size": 1
+ },
+ "CDMEIF0": {
+ "description": "Stream x clear direct mode error\n interrupt flag (x = 3..0)",
+ "offset": 2,
+ "size": 1
+ },
+ "CFEIF0": {
+ "description": "Stream x clear FIFO error interrupt flag\n (x = 3..0)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "HIFCR": {
+ "description": "high interrupt flag clear\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CTCIF7": {
+ "description": "Stream x clear transfer complete\n interrupt flag (x = 7..4)",
+ "offset": 27,
+ "size": 1
+ },
+ "CHTIF7": {
+ "description": "Stream x clear half transfer interrupt\n flag (x = 7..4)",
+ "offset": 26,
+ "size": 1
+ },
+ "CTEIF7": {
+ "description": "Stream x clear transfer error interrupt\n flag (x = 7..4)",
+ "offset": 25,
+ "size": 1
+ },
+ "CDMEIF7": {
+ "description": "Stream x clear direct mode error\n interrupt flag (x = 7..4)",
+ "offset": 24,
+ "size": 1
+ },
+ "CFEIF7": {
+ "description": "Stream x clear FIFO error interrupt flag\n (x = 7..4)",
+ "offset": 22,
+ "size": 1
+ },
+ "CTCIF6": {
+ "description": "Stream x clear transfer complete\n interrupt flag (x = 7..4)",
+ "offset": 21,
+ "size": 1
+ },
+ "CHTIF6": {
+ "description": "Stream x clear half transfer interrupt\n flag (x = 7..4)",
+ "offset": 20,
+ "size": 1
+ },
+ "CTEIF6": {
+ "description": "Stream x clear transfer error interrupt\n flag (x = 7..4)",
+ "offset": 19,
+ "size": 1
+ },
+ "CDMEIF6": {
+ "description": "Stream x clear direct mode error\n interrupt flag (x = 7..4)",
+ "offset": 18,
+ "size": 1
+ },
+ "CFEIF6": {
+ "description": "Stream x clear FIFO error interrupt flag\n (x = 7..4)",
+ "offset": 16,
+ "size": 1
+ },
+ "CTCIF5": {
+ "description": "Stream x clear transfer complete\n interrupt flag (x = 7..4)",
+ "offset": 11,
+ "size": 1
+ },
+ "CHTIF5": {
+ "description": "Stream x clear half transfer interrupt\n flag (x = 7..4)",
+ "offset": 10,
+ "size": 1
+ },
+ "CTEIF5": {
+ "description": "Stream x clear transfer error interrupt\n flag (x = 7..4)",
+ "offset": 9,
+ "size": 1
+ },
+ "CDMEIF5": {
+ "description": "Stream x clear direct mode error\n interrupt flag (x = 7..4)",
+ "offset": 8,
+ "size": 1
+ },
+ "CFEIF5": {
+ "description": "Stream x clear FIFO error interrupt flag\n (x = 7..4)",
+ "offset": 6,
+ "size": 1
+ },
+ "CTCIF4": {
+ "description": "Stream x clear transfer complete\n interrupt flag (x = 7..4)",
+ "offset": 5,
+ "size": 1
+ },
+ "CHTIF4": {
+ "description": "Stream x clear half transfer interrupt\n flag (x = 7..4)",
+ "offset": 4,
+ "size": 1
+ },
+ "CTEIF4": {
+ "description": "Stream x clear transfer error interrupt\n flag (x = 7..4)",
+ "offset": 3,
+ "size": 1
+ },
+ "CDMEIF4": {
+ "description": "Stream x clear direct mode error\n interrupt flag (x = 7..4)",
+ "offset": 2,
+ "size": 1
+ },
+ "CFEIF4": {
+ "description": "Stream x clear FIFO error interrupt flag\n (x = 7..4)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "S0CR": {
+ "description": "stream x configuration\n register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CHSEL": {
+ "description": "Channel selection",
+ "offset": 25,
+ "size": 3
+ },
+ "MBURST": {
+ "description": "Memory burst transfer\n configuration",
+ "offset": 23,
+ "size": 2
+ },
+ "PBURST": {
+ "description": "Peripheral burst transfer\n configuration",
+ "offset": 21,
+ "size": 2
+ },
+ "CT": {
+ "description": "Current target (only in double buffer\n mode)",
+ "offset": 19,
+ "size": 1
+ },
+ "DBM": {
+ "description": "Double buffer mode",
+ "offset": 18,
+ "size": 1
+ },
+ "PL": {
+ "description": "Priority level",
+ "offset": 16,
+ "size": 2
+ },
+ "PINCOS": {
+ "description": "Peripheral increment offset\n size",
+ "offset": 15,
+ "size": 1
+ },
+ "MSIZE": {
+ "description": "Memory data size",
+ "offset": 13,
+ "size": 2
+ },
+ "PSIZE": {
+ "description": "Peripheral data size",
+ "offset": 11,
+ "size": 2
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 10,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 9,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 8,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 6,
+ "size": 2
+ },
+ "PFCTRL": {
+ "description": "Peripheral flow controller",
+ "offset": 5,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half transfer interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "DMEIE": {
+ "description": "Direct mode error interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "EN": {
+ "description": "Stream enable / flag stream ready when\n read low",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "S0NDTR": {
+ "description": "stream x number of data\n register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data items to\n transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "S0PAR": {
+ "description": "stream x peripheral address\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S0M0AR": {
+ "description": "stream x memory 0 address\n register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M0A": {
+ "description": "Memory 0 address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S0M1AR": {
+ "description": "stream x memory 1 address\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M1A": {
+ "description": "Memory 1 address (used in case of Double\n buffer mode)",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S0FCR": {
+ "description": "stream x FIFO control register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 33,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEIE": {
+ "description": "FIFO error interrupt\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "FS": {
+ "description": "FIFO status",
+ "offset": 3,
+ "size": 3,
+ "access": "read-only"
+ },
+ "DMDIS": {
+ "description": "Direct mode disable",
+ "offset": 2,
+ "size": 1
+ },
+ "FTH": {
+ "description": "FIFO threshold selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "S1CR": {
+ "description": "stream x configuration\n register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CHSEL": {
+ "description": "Channel selection",
+ "offset": 25,
+ "size": 3
+ },
+ "MBURST": {
+ "description": "Memory burst transfer\n configuration",
+ "offset": 23,
+ "size": 2
+ },
+ "PBURST": {
+ "description": "Peripheral burst transfer\n configuration",
+ "offset": 21,
+ "size": 2
+ },
+ "ACK": {
+ "description": "ACK",
+ "offset": 20,
+ "size": 1
+ },
+ "CT": {
+ "description": "Current target (only in double buffer\n mode)",
+ "offset": 19,
+ "size": 1
+ },
+ "DBM": {
+ "description": "Double buffer mode",
+ "offset": 18,
+ "size": 1
+ },
+ "PL": {
+ "description": "Priority level",
+ "offset": 16,
+ "size": 2
+ },
+ "PINCOS": {
+ "description": "Peripheral increment offset\n size",
+ "offset": 15,
+ "size": 1
+ },
+ "MSIZE": {
+ "description": "Memory data size",
+ "offset": 13,
+ "size": 2
+ },
+ "PSIZE": {
+ "description": "Peripheral data size",
+ "offset": 11,
+ "size": 2
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 10,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 9,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 8,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 6,
+ "size": 2
+ },
+ "PFCTRL": {
+ "description": "Peripheral flow controller",
+ "offset": 5,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half transfer interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "DMEIE": {
+ "description": "Direct mode error interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "EN": {
+ "description": "Stream enable / flag stream ready when\n read low",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "S1NDTR": {
+ "description": "stream x number of data\n register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data items to\n transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "S1PAR": {
+ "description": "stream x peripheral address\n register",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S1M0AR": {
+ "description": "stream x memory 0 address\n register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M0A": {
+ "description": "Memory 0 address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S1M1AR": {
+ "description": "stream x memory 1 address\n register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M1A": {
+ "description": "Memory 1 address (used in case of Double\n buffer mode)",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S1FCR": {
+ "description": "stream x FIFO control register",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 33,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEIE": {
+ "description": "FIFO error interrupt\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "FS": {
+ "description": "FIFO status",
+ "offset": 3,
+ "size": 3,
+ "access": "read-only"
+ },
+ "DMDIS": {
+ "description": "Direct mode disable",
+ "offset": 2,
+ "size": 1
+ },
+ "FTH": {
+ "description": "FIFO threshold selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "S2CR": {
+ "description": "stream x configuration\n register",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CHSEL": {
+ "description": "Channel selection",
+ "offset": 25,
+ "size": 3
+ },
+ "MBURST": {
+ "description": "Memory burst transfer\n configuration",
+ "offset": 23,
+ "size": 2
+ },
+ "PBURST": {
+ "description": "Peripheral burst transfer\n configuration",
+ "offset": 21,
+ "size": 2
+ },
+ "ACK": {
+ "description": "ACK",
+ "offset": 20,
+ "size": 1
+ },
+ "CT": {
+ "description": "Current target (only in double buffer\n mode)",
+ "offset": 19,
+ "size": 1
+ },
+ "DBM": {
+ "description": "Double buffer mode",
+ "offset": 18,
+ "size": 1
+ },
+ "PL": {
+ "description": "Priority level",
+ "offset": 16,
+ "size": 2
+ },
+ "PINCOS": {
+ "description": "Peripheral increment offset\n size",
+ "offset": 15,
+ "size": 1
+ },
+ "MSIZE": {
+ "description": "Memory data size",
+ "offset": 13,
+ "size": 2
+ },
+ "PSIZE": {
+ "description": "Peripheral data size",
+ "offset": 11,
+ "size": 2
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 10,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 9,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 8,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 6,
+ "size": 2
+ },
+ "PFCTRL": {
+ "description": "Peripheral flow controller",
+ "offset": 5,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half transfer interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "DMEIE": {
+ "description": "Direct mode error interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "EN": {
+ "description": "Stream enable / flag stream ready when\n read low",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "S2NDTR": {
+ "description": "stream x number of data\n register",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data items to\n transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "S2PAR": {
+ "description": "stream x peripheral address\n register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S2M0AR": {
+ "description": "stream x memory 0 address\n register",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M0A": {
+ "description": "Memory 0 address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S2M1AR": {
+ "description": "stream x memory 1 address\n register",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M1A": {
+ "description": "Memory 1 address (used in case of Double\n buffer mode)",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S2FCR": {
+ "description": "stream x FIFO control register",
+ "offset": 84,
+ "size": 32,
+ "reset_value": 33,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEIE": {
+ "description": "FIFO error interrupt\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "FS": {
+ "description": "FIFO status",
+ "offset": 3,
+ "size": 3,
+ "access": "read-only"
+ },
+ "DMDIS": {
+ "description": "Direct mode disable",
+ "offset": 2,
+ "size": 1
+ },
+ "FTH": {
+ "description": "FIFO threshold selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "S3CR": {
+ "description": "stream x configuration\n register",
+ "offset": 88,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CHSEL": {
+ "description": "Channel selection",
+ "offset": 25,
+ "size": 3
+ },
+ "MBURST": {
+ "description": "Memory burst transfer\n configuration",
+ "offset": 23,
+ "size": 2
+ },
+ "PBURST": {
+ "description": "Peripheral burst transfer\n configuration",
+ "offset": 21,
+ "size": 2
+ },
+ "ACK": {
+ "description": "ACK",
+ "offset": 20,
+ "size": 1
+ },
+ "CT": {
+ "description": "Current target (only in double buffer\n mode)",
+ "offset": 19,
+ "size": 1
+ },
+ "DBM": {
+ "description": "Double buffer mode",
+ "offset": 18,
+ "size": 1
+ },
+ "PL": {
+ "description": "Priority level",
+ "offset": 16,
+ "size": 2
+ },
+ "PINCOS": {
+ "description": "Peripheral increment offset\n size",
+ "offset": 15,
+ "size": 1
+ },
+ "MSIZE": {
+ "description": "Memory data size",
+ "offset": 13,
+ "size": 2
+ },
+ "PSIZE": {
+ "description": "Peripheral data size",
+ "offset": 11,
+ "size": 2
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 10,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 9,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 8,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 6,
+ "size": 2
+ },
+ "PFCTRL": {
+ "description": "Peripheral flow controller",
+ "offset": 5,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half transfer interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "DMEIE": {
+ "description": "Direct mode error interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "EN": {
+ "description": "Stream enable / flag stream ready when\n read low",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "S3NDTR": {
+ "description": "stream x number of data\n register",
+ "offset": 92,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data items to\n transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "S3PAR": {
+ "description": "stream x peripheral address\n register",
+ "offset": 96,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S3M0AR": {
+ "description": "stream x memory 0 address\n register",
+ "offset": 100,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M0A": {
+ "description": "Memory 0 address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S3M1AR": {
+ "description": "stream x memory 1 address\n register",
+ "offset": 104,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M1A": {
+ "description": "Memory 1 address (used in case of Double\n buffer mode)",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S3FCR": {
+ "description": "stream x FIFO control register",
+ "offset": 108,
+ "size": 32,
+ "reset_value": 33,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEIE": {
+ "description": "FIFO error interrupt\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "FS": {
+ "description": "FIFO status",
+ "offset": 3,
+ "size": 3,
+ "access": "read-only"
+ },
+ "DMDIS": {
+ "description": "Direct mode disable",
+ "offset": 2,
+ "size": 1
+ },
+ "FTH": {
+ "description": "FIFO threshold selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "S4CR": {
+ "description": "stream x configuration\n register",
+ "offset": 112,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CHSEL": {
+ "description": "Channel selection",
+ "offset": 25,
+ "size": 3
+ },
+ "MBURST": {
+ "description": "Memory burst transfer\n configuration",
+ "offset": 23,
+ "size": 2
+ },
+ "PBURST": {
+ "description": "Peripheral burst transfer\n configuration",
+ "offset": 21,
+ "size": 2
+ },
+ "ACK": {
+ "description": "ACK",
+ "offset": 20,
+ "size": 1
+ },
+ "CT": {
+ "description": "Current target (only in double buffer\n mode)",
+ "offset": 19,
+ "size": 1
+ },
+ "DBM": {
+ "description": "Double buffer mode",
+ "offset": 18,
+ "size": 1
+ },
+ "PL": {
+ "description": "Priority level",
+ "offset": 16,
+ "size": 2
+ },
+ "PINCOS": {
+ "description": "Peripheral increment offset\n size",
+ "offset": 15,
+ "size": 1
+ },
+ "MSIZE": {
+ "description": "Memory data size",
+ "offset": 13,
+ "size": 2
+ },
+ "PSIZE": {
+ "description": "Peripheral data size",
+ "offset": 11,
+ "size": 2
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 10,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 9,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 8,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 6,
+ "size": 2
+ },
+ "PFCTRL": {
+ "description": "Peripheral flow controller",
+ "offset": 5,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half transfer interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "DMEIE": {
+ "description": "Direct mode error interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "EN": {
+ "description": "Stream enable / flag stream ready when\n read low",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "S4NDTR": {
+ "description": "stream x number of data\n register",
+ "offset": 116,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data items to\n transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "S4PAR": {
+ "description": "stream x peripheral address\n register",
+ "offset": 120,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S4M0AR": {
+ "description": "stream x memory 0 address\n register",
+ "offset": 124,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M0A": {
+ "description": "Memory 0 address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S4M1AR": {
+ "description": "stream x memory 1 address\n register",
+ "offset": 128,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M1A": {
+ "description": "Memory 1 address (used in case of Double\n buffer mode)",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S4FCR": {
+ "description": "stream x FIFO control register",
+ "offset": 132,
+ "size": 32,
+ "reset_value": 33,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEIE": {
+ "description": "FIFO error interrupt\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "FS": {
+ "description": "FIFO status",
+ "offset": 3,
+ "size": 3,
+ "access": "read-only"
+ },
+ "DMDIS": {
+ "description": "Direct mode disable",
+ "offset": 2,
+ "size": 1
+ },
+ "FTH": {
+ "description": "FIFO threshold selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "S5CR": {
+ "description": "stream x configuration\n register",
+ "offset": 136,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CHSEL": {
+ "description": "Channel selection",
+ "offset": 25,
+ "size": 3
+ },
+ "MBURST": {
+ "description": "Memory burst transfer\n configuration",
+ "offset": 23,
+ "size": 2
+ },
+ "PBURST": {
+ "description": "Peripheral burst transfer\n configuration",
+ "offset": 21,
+ "size": 2
+ },
+ "ACK": {
+ "description": "ACK",
+ "offset": 20,
+ "size": 1
+ },
+ "CT": {
+ "description": "Current target (only in double buffer\n mode)",
+ "offset": 19,
+ "size": 1
+ },
+ "DBM": {
+ "description": "Double buffer mode",
+ "offset": 18,
+ "size": 1
+ },
+ "PL": {
+ "description": "Priority level",
+ "offset": 16,
+ "size": 2
+ },
+ "PINCOS": {
+ "description": "Peripheral increment offset\n size",
+ "offset": 15,
+ "size": 1
+ },
+ "MSIZE": {
+ "description": "Memory data size",
+ "offset": 13,
+ "size": 2
+ },
+ "PSIZE": {
+ "description": "Peripheral data size",
+ "offset": 11,
+ "size": 2
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 10,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 9,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 8,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 6,
+ "size": 2
+ },
+ "PFCTRL": {
+ "description": "Peripheral flow controller",
+ "offset": 5,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half transfer interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "DMEIE": {
+ "description": "Direct mode error interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "EN": {
+ "description": "Stream enable / flag stream ready when\n read low",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "S5NDTR": {
+ "description": "stream x number of data\n register",
+ "offset": 140,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data items to\n transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "S5PAR": {
+ "description": "stream x peripheral address\n register",
+ "offset": 144,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S5M0AR": {
+ "description": "stream x memory 0 address\n register",
+ "offset": 148,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M0A": {
+ "description": "Memory 0 address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S5M1AR": {
+ "description": "stream x memory 1 address\n register",
+ "offset": 152,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M1A": {
+ "description": "Memory 1 address (used in case of Double\n buffer mode)",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S5FCR": {
+ "description": "stream x FIFO control register",
+ "offset": 156,
+ "size": 32,
+ "reset_value": 33,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEIE": {
+ "description": "FIFO error interrupt\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "FS": {
+ "description": "FIFO status",
+ "offset": 3,
+ "size": 3,
+ "access": "read-only"
+ },
+ "DMDIS": {
+ "description": "Direct mode disable",
+ "offset": 2,
+ "size": 1
+ },
+ "FTH": {
+ "description": "FIFO threshold selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "S6CR": {
+ "description": "stream x configuration\n register",
+ "offset": 160,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CHSEL": {
+ "description": "Channel selection",
+ "offset": 25,
+ "size": 3
+ },
+ "MBURST": {
+ "description": "Memory burst transfer\n configuration",
+ "offset": 23,
+ "size": 2
+ },
+ "PBURST": {
+ "description": "Peripheral burst transfer\n configuration",
+ "offset": 21,
+ "size": 2
+ },
+ "ACK": {
+ "description": "ACK",
+ "offset": 20,
+ "size": 1
+ },
+ "CT": {
+ "description": "Current target (only in double buffer\n mode)",
+ "offset": 19,
+ "size": 1
+ },
+ "DBM": {
+ "description": "Double buffer mode",
+ "offset": 18,
+ "size": 1
+ },
+ "PL": {
+ "description": "Priority level",
+ "offset": 16,
+ "size": 2
+ },
+ "PINCOS": {
+ "description": "Peripheral increment offset\n size",
+ "offset": 15,
+ "size": 1
+ },
+ "MSIZE": {
+ "description": "Memory data size",
+ "offset": 13,
+ "size": 2
+ },
+ "PSIZE": {
+ "description": "Peripheral data size",
+ "offset": 11,
+ "size": 2
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 10,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 9,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 8,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 6,
+ "size": 2
+ },
+ "PFCTRL": {
+ "description": "Peripheral flow controller",
+ "offset": 5,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half transfer interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "DMEIE": {
+ "description": "Direct mode error interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "EN": {
+ "description": "Stream enable / flag stream ready when\n read low",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "S6NDTR": {
+ "description": "stream x number of data\n register",
+ "offset": 164,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data items to\n transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "S6PAR": {
+ "description": "stream x peripheral address\n register",
+ "offset": 168,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S6M0AR": {
+ "description": "stream x memory 0 address\n register",
+ "offset": 172,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M0A": {
+ "description": "Memory 0 address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S6M1AR": {
+ "description": "stream x memory 1 address\n register",
+ "offset": 176,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M1A": {
+ "description": "Memory 1 address (used in case of Double\n buffer mode)",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S6FCR": {
+ "description": "stream x FIFO control register",
+ "offset": 180,
+ "size": 32,
+ "reset_value": 33,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEIE": {
+ "description": "FIFO error interrupt\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "FS": {
+ "description": "FIFO status",
+ "offset": 3,
+ "size": 3,
+ "access": "read-only"
+ },
+ "DMDIS": {
+ "description": "Direct mode disable",
+ "offset": 2,
+ "size": 1
+ },
+ "FTH": {
+ "description": "FIFO threshold selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "S7CR": {
+ "description": "stream x configuration\n register",
+ "offset": 184,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CHSEL": {
+ "description": "Channel selection",
+ "offset": 25,
+ "size": 3
+ },
+ "MBURST": {
+ "description": "Memory burst transfer\n configuration",
+ "offset": 23,
+ "size": 2
+ },
+ "PBURST": {
+ "description": "Peripheral burst transfer\n configuration",
+ "offset": 21,
+ "size": 2
+ },
+ "ACK": {
+ "description": "ACK",
+ "offset": 20,
+ "size": 1
+ },
+ "CT": {
+ "description": "Current target (only in double buffer\n mode)",
+ "offset": 19,
+ "size": 1
+ },
+ "DBM": {
+ "description": "Double buffer mode",
+ "offset": 18,
+ "size": 1
+ },
+ "PL": {
+ "description": "Priority level",
+ "offset": 16,
+ "size": 2
+ },
+ "PINCOS": {
+ "description": "Peripheral increment offset\n size",
+ "offset": 15,
+ "size": 1
+ },
+ "MSIZE": {
+ "description": "Memory data size",
+ "offset": 13,
+ "size": 2
+ },
+ "PSIZE": {
+ "description": "Peripheral data size",
+ "offset": 11,
+ "size": 2
+ },
+ "MINC": {
+ "description": "Memory increment mode",
+ "offset": 10,
+ "size": 1
+ },
+ "PINC": {
+ "description": "Peripheral increment mode",
+ "offset": 9,
+ "size": 1
+ },
+ "CIRC": {
+ "description": "Circular mode",
+ "offset": 8,
+ "size": 1
+ },
+ "DIR": {
+ "description": "Data transfer direction",
+ "offset": 6,
+ "size": 2
+ },
+ "PFCTRL": {
+ "description": "Peripheral flow controller",
+ "offset": 5,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "HTIE": {
+ "description": "Half transfer interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "DMEIE": {
+ "description": "Direct mode error interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "EN": {
+ "description": "Stream enable / flag stream ready when\n read low",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "S7NDTR": {
+ "description": "stream x number of data\n register",
+ "offset": 188,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NDT": {
+ "description": "Number of data items to\n transfer",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "S7PAR": {
+ "description": "stream x peripheral address\n register",
+ "offset": 192,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PA": {
+ "description": "Peripheral address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S7M0AR": {
+ "description": "stream x memory 0 address\n register",
+ "offset": 196,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M0A": {
+ "description": "Memory 0 address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S7M1AR": {
+ "description": "stream x memory 1 address\n register",
+ "offset": 200,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "M1A": {
+ "description": "Memory 1 address (used in case of Double\n buffer mode)",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "S7FCR": {
+ "description": "stream x FIFO control register",
+ "offset": 204,
+ "size": 32,
+ "reset_value": 33,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FEIE": {
+ "description": "FIFO error interrupt\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "FS": {
+ "description": "FIFO status",
+ "offset": 3,
+ "size": 3,
+ "access": "read-only"
+ },
+ "DMDIS": {
+ "description": "Direct mode disable",
+ "offset": 2,
+ "size": 1
+ },
+ "FTH": {
+ "description": "FIFO threshold selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "SCB_ACTRL": {
+ "description": "System control block ACTLR",
+ "children": {
+ "registers": {
+ "ACTRL": {
+ "description": "Auxiliary control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DISMCYCINT": {
+ "description": "DISMCYCINT",
+ "offset": 0,
+ "size": 1
+ },
+ "DISDEFWBUF": {
+ "description": "DISDEFWBUF",
+ "offset": 1,
+ "size": 1
+ },
+ "DISFOLD": {
+ "description": "DISFOLD",
+ "offset": 2,
+ "size": 1
+ },
+ "DISFPCA": {
+ "description": "DISFPCA",
+ "offset": 8,
+ "size": 1
+ },
+ "DISOOFP": {
+ "description": "DISOOFP",
+ "offset": 9,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "RCC": {
+ "description": "Reset and clock control",
+ "children": {
+ "registers": {
+ "CR": {
+ "description": "clock control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 131,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PLLI2SRDY": {
+ "description": "PLLI2S clock ready flag",
+ "offset": 27,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PLLI2SON": {
+ "description": "PLLI2S enable",
+ "offset": 26,
+ "size": 1
+ },
+ "PLLRDY": {
+ "description": "Main PLL (PLL) clock ready\n flag",
+ "offset": 25,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PLLON": {
+ "description": "Main PLL (PLL) enable",
+ "offset": 24,
+ "size": 1
+ },
+ "CSSON": {
+ "description": "Clock security system\n enable",
+ "offset": 19,
+ "size": 1
+ },
+ "HSEBYP": {
+ "description": "HSE clock bypass",
+ "offset": 18,
+ "size": 1
+ },
+ "HSERDY": {
+ "description": "HSE clock ready flag",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HSEON": {
+ "description": "HSE clock enable",
+ "offset": 16,
+ "size": 1
+ },
+ "HSICAL": {
+ "description": "Internal high-speed clock\n calibration",
+ "offset": 8,
+ "size": 8,
+ "access": "read-only"
+ },
+ "HSITRIM": {
+ "description": "Internal high-speed clock\n trimming",
+ "offset": 3,
+ "size": 5
+ },
+ "HSIRDY": {
+ "description": "Internal high-speed clock ready\n flag",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HSION": {
+ "description": "Internal high-speed clock\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PLLCFGR": {
+ "description": "PLL configuration register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 603992080,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PLLQ3": {
+ "description": "Main PLL (PLL) division factor for USB\n OTG FS, SDIO and random number generator\n clocks",
+ "offset": 27,
+ "size": 1
+ },
+ "PLLQ2": {
+ "description": "Main PLL (PLL) division factor for USB\n OTG FS, SDIO and random number generator\n clocks",
+ "offset": 26,
+ "size": 1
+ },
+ "PLLQ1": {
+ "description": "Main PLL (PLL) division factor for USB\n OTG FS, SDIO and random number generator\n clocks",
+ "offset": 25,
+ "size": 1
+ },
+ "PLLQ0": {
+ "description": "Main PLL (PLL) division factor for USB\n OTG FS, SDIO and random number generator\n clocks",
+ "offset": 24,
+ "size": 1
+ },
+ "PLLSRC": {
+ "description": "Main PLL(PLL) and audio PLL (PLLI2S)\n entry clock source",
+ "offset": 22,
+ "size": 1
+ },
+ "PLLP1": {
+ "description": "Main PLL (PLL) division factor for main\n system clock",
+ "offset": 17,
+ "size": 1
+ },
+ "PLLP0": {
+ "description": "Main PLL (PLL) division factor for main\n system clock",
+ "offset": 16,
+ "size": 1
+ },
+ "PLLN8": {
+ "description": "Main PLL (PLL) multiplication factor for\n VCO",
+ "offset": 14,
+ "size": 1
+ },
+ "PLLN7": {
+ "description": "Main PLL (PLL) multiplication factor for\n VCO",
+ "offset": 13,
+ "size": 1
+ },
+ "PLLN6": {
+ "description": "Main PLL (PLL) multiplication factor for\n VCO",
+ "offset": 12,
+ "size": 1
+ },
+ "PLLN5": {
+ "description": "Main PLL (PLL) multiplication factor for\n VCO",
+ "offset": 11,
+ "size": 1
+ },
+ "PLLN4": {
+ "description": "Main PLL (PLL) multiplication factor for\n VCO",
+ "offset": 10,
+ "size": 1
+ },
+ "PLLN3": {
+ "description": "Main PLL (PLL) multiplication factor for\n VCO",
+ "offset": 9,
+ "size": 1
+ },
+ "PLLN2": {
+ "description": "Main PLL (PLL) multiplication factor for\n VCO",
+ "offset": 8,
+ "size": 1
+ },
+ "PLLN1": {
+ "description": "Main PLL (PLL) multiplication factor for\n VCO",
+ "offset": 7,
+ "size": 1
+ },
+ "PLLN0": {
+ "description": "Main PLL (PLL) multiplication factor for\n VCO",
+ "offset": 6,
+ "size": 1
+ },
+ "PLLM5": {
+ "description": "Division factor for the main PLL (PLL)\n and audio PLL (PLLI2S) input clock",
+ "offset": 5,
+ "size": 1
+ },
+ "PLLM4": {
+ "description": "Division factor for the main PLL (PLL)\n and audio PLL (PLLI2S) input clock",
+ "offset": 4,
+ "size": 1
+ },
+ "PLLM3": {
+ "description": "Division factor for the main PLL (PLL)\n and audio PLL (PLLI2S) input clock",
+ "offset": 3,
+ "size": 1
+ },
+ "PLLM2": {
+ "description": "Division factor for the main PLL (PLL)\n and audio PLL (PLLI2S) input clock",
+ "offset": 2,
+ "size": 1
+ },
+ "PLLM1": {
+ "description": "Division factor for the main PLL (PLL)\n and audio PLL (PLLI2S) input clock",
+ "offset": 1,
+ "size": 1
+ },
+ "PLLM0": {
+ "description": "Division factor for the main PLL (PLL)\n and audio PLL (PLLI2S) input clock",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CFGR": {
+ "description": "clock configuration register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MCO2": {
+ "description": "Microcontroller clock output\n 2",
+ "offset": 30,
+ "size": 2
+ },
+ "MCO2PRE": {
+ "description": "MCO2 prescaler",
+ "offset": 27,
+ "size": 3
+ },
+ "MCO1PRE": {
+ "description": "MCO1 prescaler",
+ "offset": 24,
+ "size": 3
+ },
+ "I2SSRC": {
+ "description": "I2S clock selection",
+ "offset": 23,
+ "size": 1
+ },
+ "MCO1": {
+ "description": "Microcontroller clock output\n 1",
+ "offset": 21,
+ "size": 2
+ },
+ "RTCPRE": {
+ "description": "HSE division factor for RTC\n clock",
+ "offset": 16,
+ "size": 5
+ },
+ "PPRE2": {
+ "description": "APB high-speed prescaler\n (APB2)",
+ "offset": 13,
+ "size": 3
+ },
+ "PPRE1": {
+ "description": "APB Low speed prescaler\n (APB1)",
+ "offset": 10,
+ "size": 3
+ },
+ "HPRE": {
+ "description": "AHB prescaler",
+ "offset": 4,
+ "size": 4
+ },
+ "SWS1": {
+ "description": "System clock switch status",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SWS0": {
+ "description": "System clock switch status",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SW1": {
+ "description": "System clock switch",
+ "offset": 1,
+ "size": 1
+ },
+ "SW0": {
+ "description": "System clock switch",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CIR": {
+ "description": "clock interrupt register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSSC": {
+ "description": "Clock security system interrupt\n clear",
+ "offset": 23,
+ "size": 1,
+ "access": "write-only"
+ },
+ "PLLI2SRDYC": {
+ "description": "PLLI2S ready interrupt\n clear",
+ "offset": 21,
+ "size": 1,
+ "access": "write-only"
+ },
+ "PLLRDYC": {
+ "description": "Main PLL(PLL) ready interrupt\n clear",
+ "offset": 20,
+ "size": 1,
+ "access": "write-only"
+ },
+ "HSERDYC": {
+ "description": "HSE ready interrupt clear",
+ "offset": 19,
+ "size": 1,
+ "access": "write-only"
+ },
+ "HSIRDYC": {
+ "description": "HSI ready interrupt clear",
+ "offset": 18,
+ "size": 1,
+ "access": "write-only"
+ },
+ "LSERDYC": {
+ "description": "LSE ready interrupt clear",
+ "offset": 17,
+ "size": 1,
+ "access": "write-only"
+ },
+ "LSIRDYC": {
+ "description": "LSI ready interrupt clear",
+ "offset": 16,
+ "size": 1,
+ "access": "write-only"
+ },
+ "PLLI2SRDYIE": {
+ "description": "PLLI2S ready interrupt\n enable",
+ "offset": 13,
+ "size": 1
+ },
+ "PLLRDYIE": {
+ "description": "Main PLL (PLL) ready interrupt\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "HSERDYIE": {
+ "description": "HSE ready interrupt enable",
+ "offset": 11,
+ "size": 1
+ },
+ "HSIRDYIE": {
+ "description": "HSI ready interrupt enable",
+ "offset": 10,
+ "size": 1
+ },
+ "LSERDYIE": {
+ "description": "LSE ready interrupt enable",
+ "offset": 9,
+ "size": 1
+ },
+ "LSIRDYIE": {
+ "description": "LSI ready interrupt enable",
+ "offset": 8,
+ "size": 1
+ },
+ "CSSF": {
+ "description": "Clock security system interrupt\n flag",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PLLI2SRDYF": {
+ "description": "PLLI2S ready interrupt\n flag",
+ "offset": 5,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PLLRDYF": {
+ "description": "Main PLL (PLL) ready interrupt\n flag",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HSERDYF": {
+ "description": "HSE ready interrupt flag",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HSIRDYF": {
+ "description": "HSI ready interrupt flag",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "LSERDYF": {
+ "description": "LSE ready interrupt flag",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "LSIRDYF": {
+ "description": "LSI ready interrupt flag",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "AHB1RSTR": {
+ "description": "AHB1 peripheral reset register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OTGHSRST": {
+ "description": "USB OTG HS module reset",
+ "offset": 29,
+ "size": 1
+ },
+ "ETHMACRST": {
+ "description": "Ethernet MAC reset",
+ "offset": 25,
+ "size": 1
+ },
+ "DMA2RST": {
+ "description": "DMA2 reset",
+ "offset": 22,
+ "size": 1
+ },
+ "DMA1RST": {
+ "description": "DMA2 reset",
+ "offset": 21,
+ "size": 1
+ },
+ "CRCRST": {
+ "description": "CRC reset",
+ "offset": 12,
+ "size": 1
+ },
+ "GPIOIRST": {
+ "description": "IO port I reset",
+ "offset": 8,
+ "size": 1
+ },
+ "GPIOHRST": {
+ "description": "IO port H reset",
+ "offset": 7,
+ "size": 1
+ },
+ "GPIOGRST": {
+ "description": "IO port G reset",
+ "offset": 6,
+ "size": 1
+ },
+ "GPIOFRST": {
+ "description": "IO port F reset",
+ "offset": 5,
+ "size": 1
+ },
+ "GPIOERST": {
+ "description": "IO port E reset",
+ "offset": 4,
+ "size": 1
+ },
+ "GPIODRST": {
+ "description": "IO port D reset",
+ "offset": 3,
+ "size": 1
+ },
+ "GPIOCRST": {
+ "description": "IO port C reset",
+ "offset": 2,
+ "size": 1
+ },
+ "GPIOBRST": {
+ "description": "IO port B reset",
+ "offset": 1,
+ "size": 1
+ },
+ "GPIOARST": {
+ "description": "IO port A reset",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "AHB2RSTR": {
+ "description": "AHB2 peripheral reset register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OTGFSRST": {
+ "description": "USB OTG FS module reset",
+ "offset": 7,
+ "size": 1
+ },
+ "RNGRST": {
+ "description": "Random number generator module\n reset",
+ "offset": 6,
+ "size": 1
+ },
+ "HSAHRST": {
+ "description": "Hash module reset",
+ "offset": 5,
+ "size": 1
+ },
+ "CRYPRST": {
+ "description": "Cryptographic module reset",
+ "offset": 4,
+ "size": 1
+ },
+ "DCMIRST": {
+ "description": "Camera interface reset",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "AHB3RSTR": {
+ "description": "AHB3 peripheral reset register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FMCRST": {
+ "description": "Flexible memory controller module\n reset",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "APB1RSTR": {
+ "description": "APB1 peripheral reset register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIM2RST": {
+ "description": "TIM2 reset",
+ "offset": 0,
+ "size": 1
+ },
+ "TIM3RST": {
+ "description": "TIM3 reset",
+ "offset": 1,
+ "size": 1
+ },
+ "TIM4RST": {
+ "description": "TIM4 reset",
+ "offset": 2,
+ "size": 1
+ },
+ "TIM5RST": {
+ "description": "TIM5 reset",
+ "offset": 3,
+ "size": 1
+ },
+ "TIM6RST": {
+ "description": "TIM6 reset",
+ "offset": 4,
+ "size": 1
+ },
+ "TIM7RST": {
+ "description": "TIM7 reset",
+ "offset": 5,
+ "size": 1
+ },
+ "TIM12RST": {
+ "description": "TIM12 reset",
+ "offset": 6,
+ "size": 1
+ },
+ "TIM13RST": {
+ "description": "TIM13 reset",
+ "offset": 7,
+ "size": 1
+ },
+ "TIM14RST": {
+ "description": "TIM14 reset",
+ "offset": 8,
+ "size": 1
+ },
+ "WWDGRST": {
+ "description": "Window watchdog reset",
+ "offset": 11,
+ "size": 1
+ },
+ "SPI2RST": {
+ "description": "SPI 2 reset",
+ "offset": 14,
+ "size": 1
+ },
+ "SPI3RST": {
+ "description": "SPI 3 reset",
+ "offset": 15,
+ "size": 1
+ },
+ "UART2RST": {
+ "description": "USART 2 reset",
+ "offset": 17,
+ "size": 1
+ },
+ "UART3RST": {
+ "description": "USART 3 reset",
+ "offset": 18,
+ "size": 1
+ },
+ "UART4RST": {
+ "description": "USART 4 reset",
+ "offset": 19,
+ "size": 1
+ },
+ "UART5RST": {
+ "description": "USART 5 reset",
+ "offset": 20,
+ "size": 1
+ },
+ "I2C1RST": {
+ "description": "I2C 1 reset",
+ "offset": 21,
+ "size": 1
+ },
+ "I2C2RST": {
+ "description": "I2C 2 reset",
+ "offset": 22,
+ "size": 1
+ },
+ "I2C3RST": {
+ "description": "I2C3 reset",
+ "offset": 23,
+ "size": 1
+ },
+ "CAN1RST": {
+ "description": "CAN1 reset",
+ "offset": 25,
+ "size": 1
+ },
+ "CAN2RST": {
+ "description": "CAN2 reset",
+ "offset": 26,
+ "size": 1
+ },
+ "PWRRST": {
+ "description": "Power interface reset",
+ "offset": 28,
+ "size": 1
+ },
+ "DACRST": {
+ "description": "DAC reset",
+ "offset": 29,
+ "size": 1
+ }
+ }
+ }
+ },
+ "APB2RSTR": {
+ "description": "APB2 peripheral reset register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIM1RST": {
+ "description": "TIM1 reset",
+ "offset": 0,
+ "size": 1
+ },
+ "TIM8RST": {
+ "description": "TIM8 reset",
+ "offset": 1,
+ "size": 1
+ },
+ "USART1RST": {
+ "description": "USART1 reset",
+ "offset": 4,
+ "size": 1
+ },
+ "USART6RST": {
+ "description": "USART6 reset",
+ "offset": 5,
+ "size": 1
+ },
+ "ADCRST": {
+ "description": "ADC interface reset (common to all\n ADCs)",
+ "offset": 8,
+ "size": 1
+ },
+ "SDIORST": {
+ "description": "SDIO reset",
+ "offset": 11,
+ "size": 1
+ },
+ "SPI1RST": {
+ "description": "SPI 1 reset",
+ "offset": 12,
+ "size": 1
+ },
+ "SYSCFGRST": {
+ "description": "System configuration controller\n reset",
+ "offset": 14,
+ "size": 1
+ },
+ "TIM9RST": {
+ "description": "TIM9 reset",
+ "offset": 16,
+ "size": 1
+ },
+ "TIM10RST": {
+ "description": "TIM10 reset",
+ "offset": 17,
+ "size": 1
+ },
+ "TIM11RST": {
+ "description": "TIM11 reset",
+ "offset": 18,
+ "size": 1
+ }
+ }
+ }
+ },
+ "AHB1ENR": {
+ "description": "AHB1 peripheral clock register",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 1048576,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OTGHSULPIEN": {
+ "description": "USB OTG HSULPI clock\n enable",
+ "offset": 30,
+ "size": 1
+ },
+ "OTGHSEN": {
+ "description": "USB OTG HS clock enable",
+ "offset": 29,
+ "size": 1
+ },
+ "ETHMACPTPEN": {
+ "description": "Ethernet PTP clock enable",
+ "offset": 28,
+ "size": 1
+ },
+ "ETHMACRXEN": {
+ "description": "Ethernet Reception clock\n enable",
+ "offset": 27,
+ "size": 1
+ },
+ "ETHMACTXEN": {
+ "description": "Ethernet Transmission clock\n enable",
+ "offset": 26,
+ "size": 1
+ },
+ "ETHMACEN": {
+ "description": "Ethernet MAC clock enable",
+ "offset": 25,
+ "size": 1
+ },
+ "DMA2EN": {
+ "description": "DMA2 clock enable",
+ "offset": 22,
+ "size": 1
+ },
+ "DMA1EN": {
+ "description": "DMA1 clock enable",
+ "offset": 21,
+ "size": 1
+ },
+ "CCMDATARAMEN": {
+ "description": "CCM data RAM clock enable",
+ "offset": 20,
+ "size": 1
+ },
+ "BKPSRAMEN": {
+ "description": "Backup SRAM interface clock\n enable",
+ "offset": 18,
+ "size": 1
+ },
+ "CRCEN": {
+ "description": "CRC clock enable",
+ "offset": 12,
+ "size": 1
+ },
+ "GPIOIEN": {
+ "description": "IO port I clock enable",
+ "offset": 8,
+ "size": 1
+ },
+ "GPIOHEN": {
+ "description": "IO port H clock enable",
+ "offset": 7,
+ "size": 1
+ },
+ "GPIOGEN": {
+ "description": "IO port G clock enable",
+ "offset": 6,
+ "size": 1
+ },
+ "GPIOFEN": {
+ "description": "IO port F clock enable",
+ "offset": 5,
+ "size": 1
+ },
+ "GPIOEEN": {
+ "description": "IO port E clock enable",
+ "offset": 4,
+ "size": 1
+ },
+ "GPIODEN": {
+ "description": "IO port D clock enable",
+ "offset": 3,
+ "size": 1
+ },
+ "GPIOCEN": {
+ "description": "IO port C clock enable",
+ "offset": 2,
+ "size": 1
+ },
+ "GPIOBEN": {
+ "description": "IO port B clock enable",
+ "offset": 1,
+ "size": 1
+ },
+ "GPIOAEN": {
+ "description": "IO port A clock enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "AHB2ENR": {
+ "description": "AHB2 peripheral clock enable\n register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OTGFSEN": {
+ "description": "USB OTG FS clock enable",
+ "offset": 7,
+ "size": 1
+ },
+ "RNGEN": {
+ "description": "Random number generator clock\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "HASHEN": {
+ "description": "Hash modules clock enable",
+ "offset": 5,
+ "size": 1
+ },
+ "CRYPEN": {
+ "description": "Cryptographic modules clock\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "DCMIEN": {
+ "description": "Camera interface enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "AHB3ENR": {
+ "description": "AHB3 peripheral clock enable\n register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FMCEN": {
+ "description": "Flexible memory controller module clock\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "APB1ENR": {
+ "description": "APB1 peripheral clock enable\n register",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIM2EN": {
+ "description": "TIM2 clock enable",
+ "offset": 0,
+ "size": 1
+ },
+ "TIM3EN": {
+ "description": "TIM3 clock enable",
+ "offset": 1,
+ "size": 1
+ },
+ "TIM4EN": {
+ "description": "TIM4 clock enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TIM5EN": {
+ "description": "TIM5 clock enable",
+ "offset": 3,
+ "size": 1
+ },
+ "TIM6EN": {
+ "description": "TIM6 clock enable",
+ "offset": 4,
+ "size": 1
+ },
+ "TIM7EN": {
+ "description": "TIM7 clock enable",
+ "offset": 5,
+ "size": 1
+ },
+ "TIM12EN": {
+ "description": "TIM12 clock enable",
+ "offset": 6,
+ "size": 1
+ },
+ "TIM13EN": {
+ "description": "TIM13 clock enable",
+ "offset": 7,
+ "size": 1
+ },
+ "TIM14EN": {
+ "description": "TIM14 clock enable",
+ "offset": 8,
+ "size": 1
+ },
+ "WWDGEN": {
+ "description": "Window watchdog clock\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "SPI2EN": {
+ "description": "SPI2 clock enable",
+ "offset": 14,
+ "size": 1
+ },
+ "SPI3EN": {
+ "description": "SPI3 clock enable",
+ "offset": 15,
+ "size": 1
+ },
+ "USART2EN": {
+ "description": "USART 2 clock enable",
+ "offset": 17,
+ "size": 1
+ },
+ "USART3EN": {
+ "description": "USART3 clock enable",
+ "offset": 18,
+ "size": 1
+ },
+ "UART4EN": {
+ "description": "UART4 clock enable",
+ "offset": 19,
+ "size": 1
+ },
+ "UART5EN": {
+ "description": "UART5 clock enable",
+ "offset": 20,
+ "size": 1
+ },
+ "I2C1EN": {
+ "description": "I2C1 clock enable",
+ "offset": 21,
+ "size": 1
+ },
+ "I2C2EN": {
+ "description": "I2C2 clock enable",
+ "offset": 22,
+ "size": 1
+ },
+ "I2C3EN": {
+ "description": "I2C3 clock enable",
+ "offset": 23,
+ "size": 1
+ },
+ "CAN1EN": {
+ "description": "CAN 1 clock enable",
+ "offset": 25,
+ "size": 1
+ },
+ "CAN2EN": {
+ "description": "CAN 2 clock enable",
+ "offset": 26,
+ "size": 1
+ },
+ "PWREN": {
+ "description": "Power interface clock\n enable",
+ "offset": 28,
+ "size": 1
+ },
+ "DACEN": {
+ "description": "DAC interface clock enable",
+ "offset": 29,
+ "size": 1
+ }
+ }
+ }
+ },
+ "APB2ENR": {
+ "description": "APB2 peripheral clock enable\n register",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIM1EN": {
+ "description": "TIM1 clock enable",
+ "offset": 0,
+ "size": 1
+ },
+ "TIM8EN": {
+ "description": "TIM8 clock enable",
+ "offset": 1,
+ "size": 1
+ },
+ "USART1EN": {
+ "description": "USART1 clock enable",
+ "offset": 4,
+ "size": 1
+ },
+ "USART6EN": {
+ "description": "USART6 clock enable",
+ "offset": 5,
+ "size": 1
+ },
+ "ADC1EN": {
+ "description": "ADC1 clock enable",
+ "offset": 8,
+ "size": 1
+ },
+ "ADC2EN": {
+ "description": "ADC2 clock enable",
+ "offset": 9,
+ "size": 1
+ },
+ "ADC3EN": {
+ "description": "ADC3 clock enable",
+ "offset": 10,
+ "size": 1
+ },
+ "SDIOEN": {
+ "description": "SDIO clock enable",
+ "offset": 11,
+ "size": 1
+ },
+ "SPI1EN": {
+ "description": "SPI1 clock enable",
+ "offset": 12,
+ "size": 1
+ },
+ "SYSCFGEN": {
+ "description": "System configuration controller clock\n enable",
+ "offset": 14,
+ "size": 1
+ },
+ "TIM9EN": {
+ "description": "TIM9 clock enable",
+ "offset": 16,
+ "size": 1
+ },
+ "TIM10EN": {
+ "description": "TIM10 clock enable",
+ "offset": 17,
+ "size": 1
+ },
+ "TIM11EN": {
+ "description": "TIM11 clock enable",
+ "offset": 18,
+ "size": 1
+ }
+ }
+ }
+ },
+ "AHB1LPENR": {
+ "description": "AHB1 peripheral clock enable in low power\n mode register",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 2120716799,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "GPIOALPEN": {
+ "description": "IO port A clock enable during sleep\n mode",
+ "offset": 0,
+ "size": 1
+ },
+ "GPIOBLPEN": {
+ "description": "IO port B clock enable during Sleep\n mode",
+ "offset": 1,
+ "size": 1
+ },
+ "GPIOCLPEN": {
+ "description": "IO port C clock enable during Sleep\n mode",
+ "offset": 2,
+ "size": 1
+ },
+ "GPIODLPEN": {
+ "description": "IO port D clock enable during Sleep\n mode",
+ "offset": 3,
+ "size": 1
+ },
+ "GPIOELPEN": {
+ "description": "IO port E clock enable during Sleep\n mode",
+ "offset": 4,
+ "size": 1
+ },
+ "GPIOFLPEN": {
+ "description": "IO port F clock enable during Sleep\n mode",
+ "offset": 5,
+ "size": 1
+ },
+ "GPIOGLPEN": {
+ "description": "IO port G clock enable during Sleep\n mode",
+ "offset": 6,
+ "size": 1
+ },
+ "GPIOHLPEN": {
+ "description": "IO port H clock enable during Sleep\n mode",
+ "offset": 7,
+ "size": 1
+ },
+ "GPIOILPEN": {
+ "description": "IO port I clock enable during Sleep\n mode",
+ "offset": 8,
+ "size": 1
+ },
+ "CRCLPEN": {
+ "description": "CRC clock enable during Sleep\n mode",
+ "offset": 12,
+ "size": 1
+ },
+ "FLITFLPEN": {
+ "description": "Flash interface clock enable during\n Sleep mode",
+ "offset": 15,
+ "size": 1
+ },
+ "SRAM1LPEN": {
+ "description": "SRAM 1interface clock enable during\n Sleep mode",
+ "offset": 16,
+ "size": 1
+ },
+ "SRAM2LPEN": {
+ "description": "SRAM 2 interface clock enable during\n Sleep mode",
+ "offset": 17,
+ "size": 1
+ },
+ "BKPSRAMLPEN": {
+ "description": "Backup SRAM interface clock enable\n during Sleep mode",
+ "offset": 18,
+ "size": 1
+ },
+ "DMA1LPEN": {
+ "description": "DMA1 clock enable during Sleep\n mode",
+ "offset": 21,
+ "size": 1
+ },
+ "DMA2LPEN": {
+ "description": "DMA2 clock enable during Sleep\n mode",
+ "offset": 22,
+ "size": 1
+ },
+ "ETHMACLPEN": {
+ "description": "Ethernet MAC clock enable during Sleep\n mode",
+ "offset": 25,
+ "size": 1
+ },
+ "ETHMACTXLPEN": {
+ "description": "Ethernet transmission clock enable\n during Sleep mode",
+ "offset": 26,
+ "size": 1
+ },
+ "ETHMACRXLPEN": {
+ "description": "Ethernet reception clock enable during\n Sleep mode",
+ "offset": 27,
+ "size": 1
+ },
+ "ETHMACPTPLPEN": {
+ "description": "Ethernet PTP clock enable during Sleep\n mode",
+ "offset": 28,
+ "size": 1
+ },
+ "OTGHSLPEN": {
+ "description": "USB OTG HS clock enable during Sleep\n mode",
+ "offset": 29,
+ "size": 1
+ },
+ "OTGHSULPILPEN": {
+ "description": "USB OTG HS ULPI clock enable during\n Sleep mode",
+ "offset": 30,
+ "size": 1
+ }
+ }
+ }
+ },
+ "AHB2LPENR": {
+ "description": "AHB2 peripheral clock enable in low power\n mode register",
+ "offset": 84,
+ "size": 32,
+ "reset_value": 241,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OTGFSLPEN": {
+ "description": "USB OTG FS clock enable during Sleep\n mode",
+ "offset": 7,
+ "size": 1
+ },
+ "RNGLPEN": {
+ "description": "Random number generator clock enable\n during Sleep mode",
+ "offset": 6,
+ "size": 1
+ },
+ "HASHLPEN": {
+ "description": "Hash modules clock enable during Sleep\n mode",
+ "offset": 5,
+ "size": 1
+ },
+ "CRYPLPEN": {
+ "description": "Cryptography modules clock enable during\n Sleep mode",
+ "offset": 4,
+ "size": 1
+ },
+ "DCMILPEN": {
+ "description": "Camera interface enable during Sleep\n mode",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "AHB3LPENR": {
+ "description": "AHB3 peripheral clock enable in low power\n mode register",
+ "offset": 88,
+ "size": 32,
+ "reset_value": 1,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FMCLPEN": {
+ "description": "Flexible memory controller module clock\n enable during Sleep mode",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "APB1LPENR": {
+ "description": "APB1 peripheral clock enable in low power\n mode register",
+ "offset": 96,
+ "size": 32,
+ "reset_value": 922667519,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIM2LPEN": {
+ "description": "TIM2 clock enable during Sleep\n mode",
+ "offset": 0,
+ "size": 1
+ },
+ "TIM3LPEN": {
+ "description": "TIM3 clock enable during Sleep\n mode",
+ "offset": 1,
+ "size": 1
+ },
+ "TIM4LPEN": {
+ "description": "TIM4 clock enable during Sleep\n mode",
+ "offset": 2,
+ "size": 1
+ },
+ "TIM5LPEN": {
+ "description": "TIM5 clock enable during Sleep\n mode",
+ "offset": 3,
+ "size": 1
+ },
+ "TIM6LPEN": {
+ "description": "TIM6 clock enable during Sleep\n mode",
+ "offset": 4,
+ "size": 1
+ },
+ "TIM7LPEN": {
+ "description": "TIM7 clock enable during Sleep\n mode",
+ "offset": 5,
+ "size": 1
+ },
+ "TIM12LPEN": {
+ "description": "TIM12 clock enable during Sleep\n mode",
+ "offset": 6,
+ "size": 1
+ },
+ "TIM13LPEN": {
+ "description": "TIM13 clock enable during Sleep\n mode",
+ "offset": 7,
+ "size": 1
+ },
+ "TIM14LPEN": {
+ "description": "TIM14 clock enable during Sleep\n mode",
+ "offset": 8,
+ "size": 1
+ },
+ "WWDGLPEN": {
+ "description": "Window watchdog clock enable during\n Sleep mode",
+ "offset": 11,
+ "size": 1
+ },
+ "SPI2LPEN": {
+ "description": "SPI2 clock enable during Sleep\n mode",
+ "offset": 14,
+ "size": 1
+ },
+ "SPI3LPEN": {
+ "description": "SPI3 clock enable during Sleep\n mode",
+ "offset": 15,
+ "size": 1
+ },
+ "USART2LPEN": {
+ "description": "USART2 clock enable during Sleep\n mode",
+ "offset": 17,
+ "size": 1
+ },
+ "USART3LPEN": {
+ "description": "USART3 clock enable during Sleep\n mode",
+ "offset": 18,
+ "size": 1
+ },
+ "UART4LPEN": {
+ "description": "UART4 clock enable during Sleep\n mode",
+ "offset": 19,
+ "size": 1
+ },
+ "UART5LPEN": {
+ "description": "UART5 clock enable during Sleep\n mode",
+ "offset": 20,
+ "size": 1
+ },
+ "I2C1LPEN": {
+ "description": "I2C1 clock enable during Sleep\n mode",
+ "offset": 21,
+ "size": 1
+ },
+ "I2C2LPEN": {
+ "description": "I2C2 clock enable during Sleep\n mode",
+ "offset": 22,
+ "size": 1
+ },
+ "I2C3LPEN": {
+ "description": "I2C3 clock enable during Sleep\n mode",
+ "offset": 23,
+ "size": 1
+ },
+ "CAN1LPEN": {
+ "description": "CAN 1 clock enable during Sleep\n mode",
+ "offset": 25,
+ "size": 1
+ },
+ "CAN2LPEN": {
+ "description": "CAN 2 clock enable during Sleep\n mode",
+ "offset": 26,
+ "size": 1
+ },
+ "PWRLPEN": {
+ "description": "Power interface clock enable during\n Sleep mode",
+ "offset": 28,
+ "size": 1
+ },
+ "DACLPEN": {
+ "description": "DAC interface clock enable during Sleep\n mode",
+ "offset": 29,
+ "size": 1
+ }
+ }
+ }
+ },
+ "APB2LPENR": {
+ "description": "APB2 peripheral clock enabled in low power\n mode register",
+ "offset": 100,
+ "size": 32,
+ "reset_value": 483123,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIM1LPEN": {
+ "description": "TIM1 clock enable during Sleep\n mode",
+ "offset": 0,
+ "size": 1
+ },
+ "TIM8LPEN": {
+ "description": "TIM8 clock enable during Sleep\n mode",
+ "offset": 1,
+ "size": 1
+ },
+ "USART1LPEN": {
+ "description": "USART1 clock enable during Sleep\n mode",
+ "offset": 4,
+ "size": 1
+ },
+ "USART6LPEN": {
+ "description": "USART6 clock enable during Sleep\n mode",
+ "offset": 5,
+ "size": 1
+ },
+ "ADC1LPEN": {
+ "description": "ADC1 clock enable during Sleep\n mode",
+ "offset": 8,
+ "size": 1
+ },
+ "ADC2LPEN": {
+ "description": "ADC2 clock enable during Sleep\n mode",
+ "offset": 9,
+ "size": 1
+ },
+ "ADC3LPEN": {
+ "description": "ADC 3 clock enable during Sleep\n mode",
+ "offset": 10,
+ "size": 1
+ },
+ "SDIOLPEN": {
+ "description": "SDIO clock enable during Sleep\n mode",
+ "offset": 11,
+ "size": 1
+ },
+ "SPI1LPEN": {
+ "description": "SPI 1 clock enable during Sleep\n mode",
+ "offset": 12,
+ "size": 1
+ },
+ "SYSCFGLPEN": {
+ "description": "System configuration controller clock\n enable during Sleep mode",
+ "offset": 14,
+ "size": 1
+ },
+ "TIM9LPEN": {
+ "description": "TIM9 clock enable during sleep\n mode",
+ "offset": 16,
+ "size": 1
+ },
+ "TIM10LPEN": {
+ "description": "TIM10 clock enable during Sleep\n mode",
+ "offset": 17,
+ "size": 1
+ },
+ "TIM11LPEN": {
+ "description": "TIM11 clock enable during Sleep\n mode",
+ "offset": 18,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BDCR": {
+ "description": "Backup domain control register",
+ "offset": 112,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BDRST": {
+ "description": "Backup domain software\n reset",
+ "offset": 16,
+ "size": 1
+ },
+ "RTCEN": {
+ "description": "RTC clock enable",
+ "offset": 15,
+ "size": 1
+ },
+ "RTCSEL1": {
+ "description": "RTC clock source selection",
+ "offset": 9,
+ "size": 1
+ },
+ "RTCSEL0": {
+ "description": "RTC clock source selection",
+ "offset": 8,
+ "size": 1
+ },
+ "LSEBYP": {
+ "description": "External low-speed oscillator\n bypass",
+ "offset": 2,
+ "size": 1
+ },
+ "LSERDY": {
+ "description": "External low-speed oscillator\n ready",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "LSEON": {
+ "description": "External low-speed oscillator\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CSR": {
+ "description": "clock control & status\n register",
+ "offset": 116,
+ "size": 32,
+ "reset_value": 234881024,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LPWRRSTF": {
+ "description": "Low-power reset flag",
+ "offset": 31,
+ "size": 1
+ },
+ "WWDGRSTF": {
+ "description": "Window watchdog reset flag",
+ "offset": 30,
+ "size": 1
+ },
+ "WDGRSTF": {
+ "description": "Independent watchdog reset\n flag",
+ "offset": 29,
+ "size": 1
+ },
+ "SFTRSTF": {
+ "description": "Software reset flag",
+ "offset": 28,
+ "size": 1
+ },
+ "PORRSTF": {
+ "description": "POR/PDR reset flag",
+ "offset": 27,
+ "size": 1
+ },
+ "PADRSTF": {
+ "description": "PIN reset flag",
+ "offset": 26,
+ "size": 1
+ },
+ "BORRSTF": {
+ "description": "BOR reset flag",
+ "offset": 25,
+ "size": 1
+ },
+ "RMVF": {
+ "description": "Remove reset flag",
+ "offset": 24,
+ "size": 1
+ },
+ "LSIRDY": {
+ "description": "Internal low-speed oscillator\n ready",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "LSION": {
+ "description": "Internal low-speed oscillator\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SSCGR": {
+ "description": "spread spectrum clock generation\n register",
+ "offset": 128,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SSCGEN": {
+ "description": "Spread spectrum modulation\n enable",
+ "offset": 31,
+ "size": 1
+ },
+ "SPREADSEL": {
+ "description": "Spread Select",
+ "offset": 30,
+ "size": 1
+ },
+ "INCSTEP": {
+ "description": "Incrementation step",
+ "offset": 13,
+ "size": 15
+ },
+ "MODPER": {
+ "description": "Modulation period",
+ "offset": 0,
+ "size": 13
+ }
+ }
+ }
+ },
+ "PLLI2SCFGR": {
+ "description": "PLLI2S configuration register",
+ "offset": 132,
+ "size": 32,
+ "reset_value": 536883200,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PLLI2SR": {
+ "description": "PLLI2S division factor for I2S\n clocks",
+ "offset": 28,
+ "size": 3
+ },
+ "PLLI2SQ": {
+ "description": "PLLI2S division factor for SAI1\n clock",
+ "offset": 24,
+ "size": 4
+ },
+ "PLLI2SN": {
+ "description": "PLLI2S multiplication factor for\n VCO",
+ "offset": 6,
+ "size": 9
+ }
+ }
+ }
+ },
+ "DCKCFGR": {
+ "description": "RCC Dedicated Clock Configuration\n Register",
+ "offset": 140,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PLLI2SDIVQ": {
+ "description": "PLLI2S division factor for SAI1\n clock",
+ "offset": 0,
+ "size": 5
+ },
+ "PLLSAIDIVQ": {
+ "description": "PLLSAI division factor for SAI1\n clock",
+ "offset": 8,
+ "size": 5
+ },
+ "PLLSAIDIVR": {
+ "description": "division factor for\n LCD_CLK",
+ "offset": 16,
+ "size": 2
+ },
+ "SAI1ASRC": {
+ "description": "SAI1-A clock source\n selection",
+ "offset": 20,
+ "size": 2
+ },
+ "SAI1BSRC": {
+ "description": "SAI1-B clock source\n selection",
+ "offset": 22,
+ "size": 2
+ },
+ "TIMPRE": {
+ "description": "Timers clocks prescalers\n selection",
+ "offset": 24,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PLLSAICFGR": {
+ "description": "RCC PLL configuration register",
+ "offset": 136,
+ "size": 32,
+ "reset_value": 603992064,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PLLSAIR": {
+ "description": "PLLSAI division factor for LCD\n clock",
+ "offset": 28,
+ "size": 3
+ },
+ "PLLSAIQ": {
+ "description": "PLLSAI division factor for SAI1\n clock",
+ "offset": 24,
+ "size": 4
+ },
+ "PLLSAIN": {
+ "description": "PLLSAI division factor for\n VCO",
+ "offset": 6,
+ "size": 9
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "GPIOK": {
+ "description": "General-purpose I/Os",
+ "children": {
+ "registers": {
+ "MODER": {
+ "description": "GPIO port mode register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MODER15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 30,
+ "size": 2
+ },
+ "MODER14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 28,
+ "size": 2
+ },
+ "MODER13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 26,
+ "size": 2
+ },
+ "MODER12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 24,
+ "size": 2
+ },
+ "MODER11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 22,
+ "size": 2
+ },
+ "MODER10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 20,
+ "size": 2
+ },
+ "MODER9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 18,
+ "size": 2
+ },
+ "MODER8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 16,
+ "size": 2
+ },
+ "MODER7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 2
+ },
+ "MODER6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 2
+ },
+ "MODER5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 2
+ },
+ "MODER4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 2
+ },
+ "MODER3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 2
+ },
+ "MODER2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 2
+ },
+ "MODER1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 2
+ },
+ "MODER0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTYPER": {
+ "description": "GPIO port output type register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OT15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "OT14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "OT13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "OT12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "OT11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "OT10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "OT9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "OT8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "OT7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "OT6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "OT5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "OT4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "OT3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "OT2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "OT1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "OT0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OSPEEDR": {
+ "description": "GPIO port output speed\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OSPEEDR15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 30,
+ "size": 2
+ },
+ "OSPEEDR14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 28,
+ "size": 2
+ },
+ "OSPEEDR13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 26,
+ "size": 2
+ },
+ "OSPEEDR12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 24,
+ "size": 2
+ },
+ "OSPEEDR11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 22,
+ "size": 2
+ },
+ "OSPEEDR10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 20,
+ "size": 2
+ },
+ "OSPEEDR9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 18,
+ "size": 2
+ },
+ "OSPEEDR8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 16,
+ "size": 2
+ },
+ "OSPEEDR7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 2
+ },
+ "OSPEEDR6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 2
+ },
+ "OSPEEDR5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 2
+ },
+ "OSPEEDR4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 2
+ },
+ "OSPEEDR3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 2
+ },
+ "OSPEEDR2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 2
+ },
+ "OSPEEDR1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 2
+ },
+ "OSPEEDR0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "PUPDR": {
+ "description": "GPIO port pull-up/pull-down\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PUPDR15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 30,
+ "size": 2
+ },
+ "PUPDR14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 28,
+ "size": 2
+ },
+ "PUPDR13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 26,
+ "size": 2
+ },
+ "PUPDR12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 24,
+ "size": 2
+ },
+ "PUPDR11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 22,
+ "size": 2
+ },
+ "PUPDR10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 20,
+ "size": 2
+ },
+ "PUPDR9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 18,
+ "size": 2
+ },
+ "PUPDR8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 16,
+ "size": 2
+ },
+ "PUPDR7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 2
+ },
+ "PUPDR6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 2
+ },
+ "PUPDR5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 2
+ },
+ "PUPDR4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 2
+ },
+ "PUPDR3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 2
+ },
+ "PUPDR2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 2
+ },
+ "PUPDR1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 2
+ },
+ "PUPDR0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "IDR": {
+ "description": "GPIO port input data register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "IDR15": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "IDR14": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "IDR13": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "IDR12": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "IDR11": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "IDR10": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "IDR9": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "IDR8": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "IDR7": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "IDR6": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "IDR5": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "IDR4": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "IDR3": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "IDR2": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "IDR1": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "IDR0": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ODR": {
+ "description": "GPIO port output data register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ODR15": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "ODR14": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "ODR13": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "ODR12": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "ODR11": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "ODR10": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "ODR9": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "ODR8": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "ODR7": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "ODR6": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "ODR5": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "ODR4": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "ODR3": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "ODR2": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "ODR1": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "ODR0": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BSRR": {
+ "description": "GPIO port bit set/reset\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "BR15": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 31,
+ "size": 1
+ },
+ "BR14": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 30,
+ "size": 1
+ },
+ "BR13": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 29,
+ "size": 1
+ },
+ "BR12": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 28,
+ "size": 1
+ },
+ "BR11": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 27,
+ "size": 1
+ },
+ "BR10": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 26,
+ "size": 1
+ },
+ "BR9": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 25,
+ "size": 1
+ },
+ "BR8": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 24,
+ "size": 1
+ },
+ "BR7": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 23,
+ "size": 1
+ },
+ "BR6": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 22,
+ "size": 1
+ },
+ "BR5": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 21,
+ "size": 1
+ },
+ "BR4": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 20,
+ "size": 1
+ },
+ "BR3": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 19,
+ "size": 1
+ },
+ "BR2": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 18,
+ "size": 1
+ },
+ "BR1": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 17,
+ "size": 1
+ },
+ "BR0": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 16,
+ "size": 1
+ },
+ "BS15": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "BS14": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "BS13": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "BS12": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "BS11": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "BS10": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "BS9": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "BS8": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "BS7": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "BS6": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "BS5": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "BS4": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "BS3": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "BS2": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "BS1": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "BS0": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "LCKR": {
+ "description": "GPIO port configuration lock\n register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LCKK": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 16,
+ "size": 1
+ },
+ "LCK15": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "LCK14": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "LCK13": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "LCK12": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "LCK11": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "LCK10": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "LCK9": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "LCK8": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "LCK7": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "LCK6": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "LCK5": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "LCK4": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "LCK3": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "LCK2": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "LCK1": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "LCK0": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "AFRL": {
+ "description": "GPIO alternate function low\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "AFRL7": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 28,
+ "size": 4
+ },
+ "AFRL6": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 24,
+ "size": 4
+ },
+ "AFRL5": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 20,
+ "size": 4
+ },
+ "AFRL4": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 16,
+ "size": 4
+ },
+ "AFRL3": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 12,
+ "size": 4
+ },
+ "AFRL2": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 8,
+ "size": 4
+ },
+ "AFRL1": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 4,
+ "size": 4
+ },
+ "AFRL0": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "AFRH": {
+ "description": "GPIO alternate function high\n register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "AFRH15": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 28,
+ "size": 4
+ },
+ "AFRH14": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 24,
+ "size": 4
+ },
+ "AFRH13": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 20,
+ "size": 4
+ },
+ "AFRH12": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 16,
+ "size": 4
+ },
+ "AFRH11": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 12,
+ "size": 4
+ },
+ "AFRH10": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 8,
+ "size": 4
+ },
+ "AFRH9": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 4,
+ "size": 4
+ },
+ "AFRH8": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "FPU_CPACR": {
+ "description": "Floating point unit CPACR",
+ "children": {
+ "registers": {
+ "CPACR": {
+ "description": "Coprocessor access control\n register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CP": {
+ "description": "CP",
+ "offset": 20,
+ "size": 4
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "NVIC_STIR": {
+ "description": "Nested vectored interrupt\n controller",
+ "children": {
+ "registers": {
+ "STIR": {
+ "description": "Software trigger interrupt\n register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INTID": {
+ "description": "Software generated interrupt\n ID",
+ "offset": 0,
+ "size": 9
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "SCB": {
+ "description": "System control block",
+ "children": {
+ "registers": {
+ "CPUID": {
+ "description": "CPUID base register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 1091551809,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "Revision": {
+ "description": "Revision number",
+ "offset": 0,
+ "size": 4
+ },
+ "PartNo": {
+ "description": "Part number of the\n processor",
+ "offset": 4,
+ "size": 12
+ },
+ "Constant": {
+ "description": "Reads as 0xF",
+ "offset": 16,
+ "size": 4
+ },
+ "Variant": {
+ "description": "Variant number",
+ "offset": 20,
+ "size": 4
+ },
+ "Implementer": {
+ "description": "Implementer code",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "ICSR": {
+ "description": "Interrupt control and state\n register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "VECTACTIVE": {
+ "description": "Active vector",
+ "offset": 0,
+ "size": 9
+ },
+ "RETTOBASE": {
+ "description": "Return to base level",
+ "offset": 11,
+ "size": 1
+ },
+ "VECTPENDING": {
+ "description": "Pending vector",
+ "offset": 12,
+ "size": 7
+ },
+ "ISRPENDING": {
+ "description": "Interrupt pending flag",
+ "offset": 22,
+ "size": 1
+ },
+ "PENDSTCLR": {
+ "description": "SysTick exception clear-pending\n bit",
+ "offset": 25,
+ "size": 1
+ },
+ "PENDSTSET": {
+ "description": "SysTick exception set-pending\n bit",
+ "offset": 26,
+ "size": 1
+ },
+ "PENDSVCLR": {
+ "description": "PendSV clear-pending bit",
+ "offset": 27,
+ "size": 1
+ },
+ "PENDSVSET": {
+ "description": "PendSV set-pending bit",
+ "offset": 28,
+ "size": 1
+ },
+ "NMIPENDSET": {
+ "description": "NMI set-pending bit.",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "VTOR": {
+ "description": "Vector table offset register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TBLOFF": {
+ "description": "Vector table base offset\n field",
+ "offset": 9,
+ "size": 21
+ }
+ }
+ }
+ },
+ "AIRCR": {
+ "description": "Application interrupt and reset control\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "VECTRESET": {
+ "description": "VECTRESET",
+ "offset": 0,
+ "size": 1
+ },
+ "VECTCLRACTIVE": {
+ "description": "VECTCLRACTIVE",
+ "offset": 1,
+ "size": 1
+ },
+ "SYSRESETREQ": {
+ "description": "SYSRESETREQ",
+ "offset": 2,
+ "size": 1
+ },
+ "PRIGROUP": {
+ "description": "PRIGROUP",
+ "offset": 8,
+ "size": 3
+ },
+ "ENDIANESS": {
+ "description": "ENDIANESS",
+ "offset": 15,
+ "size": 1
+ },
+ "VECTKEYSTAT": {
+ "description": "Register key",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "SCR": {
+ "description": "System control register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SLEEPONEXIT": {
+ "description": "SLEEPONEXIT",
+ "offset": 1,
+ "size": 1
+ },
+ "SLEEPDEEP": {
+ "description": "SLEEPDEEP",
+ "offset": 2,
+ "size": 1
+ },
+ "SEVEONPEND": {
+ "description": "Send Event on Pending bit",
+ "offset": 4,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCR": {
+ "description": "Configuration and control\n register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NONBASETHRDENA": {
+ "description": "Configures how the processor enters\n Thread mode",
+ "offset": 0,
+ "size": 1
+ },
+ "USERSETMPEND": {
+ "description": "USERSETMPEND",
+ "offset": 1,
+ "size": 1
+ },
+ "UNALIGN__TRP": {
+ "description": "UNALIGN_ TRP",
+ "offset": 3,
+ "size": 1
+ },
+ "DIV_0_TRP": {
+ "description": "DIV_0_TRP",
+ "offset": 4,
+ "size": 1
+ },
+ "BFHFNMIGN": {
+ "description": "BFHFNMIGN",
+ "offset": 8,
+ "size": 1
+ },
+ "STKALIGN": {
+ "description": "STKALIGN",
+ "offset": 9,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SHPR1": {
+ "description": "System handler priority\n registers",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRI_4": {
+ "description": "Priority of system handler\n 4",
+ "offset": 0,
+ "size": 8
+ },
+ "PRI_5": {
+ "description": "Priority of system handler\n 5",
+ "offset": 8,
+ "size": 8
+ },
+ "PRI_6": {
+ "description": "Priority of system handler\n 6",
+ "offset": 16,
+ "size": 8
+ }
+ }
+ }
+ },
+ "SHPR2": {
+ "description": "System handler priority\n registers",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRI_11": {
+ "description": "Priority of system handler\n 11",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "SHPR3": {
+ "description": "System handler priority\n registers",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRI_14": {
+ "description": "Priority of system handler\n 14",
+ "offset": 16,
+ "size": 8
+ },
+ "PRI_15": {
+ "description": "Priority of system handler\n 15",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "SHCRS": {
+ "description": "System handler control and state\n register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MEMFAULTACT": {
+ "description": "Memory management fault exception active\n bit",
+ "offset": 0,
+ "size": 1
+ },
+ "BUSFAULTACT": {
+ "description": "Bus fault exception active\n bit",
+ "offset": 1,
+ "size": 1
+ },
+ "USGFAULTACT": {
+ "description": "Usage fault exception active\n bit",
+ "offset": 3,
+ "size": 1
+ },
+ "SVCALLACT": {
+ "description": "SVC call active bit",
+ "offset": 7,
+ "size": 1
+ },
+ "MONITORACT": {
+ "description": "Debug monitor active bit",
+ "offset": 8,
+ "size": 1
+ },
+ "PENDSVACT": {
+ "description": "PendSV exception active\n bit",
+ "offset": 10,
+ "size": 1
+ },
+ "SYSTICKACT": {
+ "description": "SysTick exception active\n bit",
+ "offset": 11,
+ "size": 1
+ },
+ "USGFAULTPENDED": {
+ "description": "Usage fault exception pending\n bit",
+ "offset": 12,
+ "size": 1
+ },
+ "MEMFAULTPENDED": {
+ "description": "Memory management fault exception\n pending bit",
+ "offset": 13,
+ "size": 1
+ },
+ "BUSFAULTPENDED": {
+ "description": "Bus fault exception pending\n bit",
+ "offset": 14,
+ "size": 1
+ },
+ "SVCALLPENDED": {
+ "description": "SVC call pending bit",
+ "offset": 15,
+ "size": 1
+ },
+ "MEMFAULTENA": {
+ "description": "Memory management fault enable\n bit",
+ "offset": 16,
+ "size": 1
+ },
+ "BUSFAULTENA": {
+ "description": "Bus fault enable bit",
+ "offset": 17,
+ "size": 1
+ },
+ "USGFAULTENA": {
+ "description": "Usage fault enable bit",
+ "offset": 18,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CFSR_UFSR_BFSR_MMFSR": {
+ "description": "Configurable fault status\n register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IACCVIOL": {
+ "description": "Instruction access violation\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "MUNSTKERR": {
+ "description": "Memory manager fault on unstacking for a\n return from exception",
+ "offset": 3,
+ "size": 1
+ },
+ "MSTKERR": {
+ "description": "Memory manager fault on stacking for\n exception entry.",
+ "offset": 4,
+ "size": 1
+ },
+ "MLSPERR": {
+ "description": "MLSPERR",
+ "offset": 5,
+ "size": 1
+ },
+ "MMARVALID": {
+ "description": "Memory Management Fault Address Register\n (MMAR) valid flag",
+ "offset": 7,
+ "size": 1
+ },
+ "IBUSERR": {
+ "description": "Instruction bus error",
+ "offset": 8,
+ "size": 1
+ },
+ "PRECISERR": {
+ "description": "Precise data bus error",
+ "offset": 9,
+ "size": 1
+ },
+ "IMPRECISERR": {
+ "description": "Imprecise data bus error",
+ "offset": 10,
+ "size": 1
+ },
+ "UNSTKERR": {
+ "description": "Bus fault on unstacking for a return\n from exception",
+ "offset": 11,
+ "size": 1
+ },
+ "STKERR": {
+ "description": "Bus fault on stacking for exception\n entry",
+ "offset": 12,
+ "size": 1
+ },
+ "LSPERR": {
+ "description": "Bus fault on floating-point lazy state\n preservation",
+ "offset": 13,
+ "size": 1
+ },
+ "BFARVALID": {
+ "description": "Bus Fault Address Register (BFAR) valid\n flag",
+ "offset": 15,
+ "size": 1
+ },
+ "UNDEFINSTR": {
+ "description": "Undefined instruction usage\n fault",
+ "offset": 16,
+ "size": 1
+ },
+ "INVSTATE": {
+ "description": "Invalid state usage fault",
+ "offset": 17,
+ "size": 1
+ },
+ "INVPC": {
+ "description": "Invalid PC load usage\n fault",
+ "offset": 18,
+ "size": 1
+ },
+ "NOCP": {
+ "description": "No coprocessor usage\n fault.",
+ "offset": 19,
+ "size": 1
+ },
+ "UNALIGNED": {
+ "description": "Unaligned access usage\n fault",
+ "offset": 24,
+ "size": 1
+ },
+ "DIVBYZERO": {
+ "description": "Divide by zero usage fault",
+ "offset": 25,
+ "size": 1
+ }
+ }
+ }
+ },
+ "HFSR": {
+ "description": "Hard fault status register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "VECTTBL": {
+ "description": "Vector table hard fault",
+ "offset": 1,
+ "size": 1
+ },
+ "FORCED": {
+ "description": "Forced hard fault",
+ "offset": 30,
+ "size": 1
+ },
+ "DEBUG_VT": {
+ "description": "Reserved for Debug use",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MMFAR": {
+ "description": "Memory management fault address\n register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MMFAR": {
+ "description": "Memory management fault\n address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BFAR": {
+ "description": "Bus fault address register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BFAR": {
+ "description": "Bus fault address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "AFSR": {
+ "description": "Auxiliary fault status\n register",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IMPDEF": {
+ "description": "Implementation defined",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "STK": {
+ "description": "SysTick timer",
+ "children": {
+ "registers": {
+ "CTRL": {
+ "description": "SysTick control and status\n register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ENABLE": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ },
+ "TICKINT": {
+ "description": "SysTick exception request\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "CLKSOURCE": {
+ "description": "Clock source selection",
+ "offset": 2,
+ "size": 1
+ },
+ "COUNTFLAG": {
+ "description": "COUNTFLAG",
+ "offset": 16,
+ "size": 1
+ }
+ }
+ }
+ },
+ "LOAD": {
+ "description": "SysTick reload value register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RELOAD": {
+ "description": "RELOAD value",
+ "offset": 0,
+ "size": 24
+ }
+ }
+ }
+ },
+ "VAL": {
+ "description": "SysTick current value register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CURRENT": {
+ "description": "Current counter value",
+ "offset": 0,
+ "size": 24
+ }
+ }
+ }
+ },
+ "CALIB": {
+ "description": "SysTick calibration value\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TENMS": {
+ "description": "Calibration value",
+ "offset": 0,
+ "size": 24
+ },
+ "SKEW": {
+ "description": "SKEW flag: Indicates whether the TENMS\n value is exact",
+ "offset": 30,
+ "size": 1
+ },
+ "NOREF": {
+ "description": "NOREF flag. Reads as zero",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "MPU": {
+ "description": "Memory protection unit",
+ "children": {
+ "registers": {
+ "MPU_TYPER": {
+ "description": "MPU type register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 2048,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "SEPARATE": {
+ "description": "Separate flag",
+ "offset": 0,
+ "size": 1
+ },
+ "DREGION": {
+ "description": "Number of MPU data regions",
+ "offset": 8,
+ "size": 8
+ },
+ "IREGION": {
+ "description": "Number of MPU instruction\n regions",
+ "offset": 16,
+ "size": 8
+ }
+ }
+ }
+ },
+ "MPU_CTRL": {
+ "description": "MPU control register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "ENABLE": {
+ "description": "Enables the MPU",
+ "offset": 0,
+ "size": 1
+ },
+ "HFNMIENA": {
+ "description": "Enables the operation of MPU during hard\n fault",
+ "offset": 1,
+ "size": 1
+ },
+ "PRIVDEFENA": {
+ "description": "Enable priviliged software access to\n default memory map",
+ "offset": 2,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MPU_RNR": {
+ "description": "MPU region number register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "REGION": {
+ "description": "MPU region",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "MPU_RBAR": {
+ "description": "MPU region base address\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "REGION": {
+ "description": "MPU region field",
+ "offset": 0,
+ "size": 4
+ },
+ "VALID": {
+ "description": "MPU region number valid",
+ "offset": 4,
+ "size": 1
+ },
+ "ADDR": {
+ "description": "Region base address field",
+ "offset": 5,
+ "size": 27
+ }
+ }
+ }
+ },
+ "MPU_RASR": {
+ "description": "MPU region attribute and size\n register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ENABLE": {
+ "description": "Region enable bit.",
+ "offset": 0,
+ "size": 1
+ },
+ "SIZE": {
+ "description": "Size of the MPU protection\n region",
+ "offset": 1,
+ "size": 5
+ },
+ "SRD": {
+ "description": "Subregion disable bits",
+ "offset": 8,
+ "size": 8
+ },
+ "B": {
+ "description": "memory attribute",
+ "offset": 16,
+ "size": 1
+ },
+ "C": {
+ "description": "memory attribute",
+ "offset": 17,
+ "size": 1
+ },
+ "S": {
+ "description": "Shareable memory attribute",
+ "offset": 18,
+ "size": 1
+ },
+ "TEX": {
+ "description": "memory attribute",
+ "offset": 19,
+ "size": 3
+ },
+ "AP": {
+ "description": "Access permission",
+ "offset": 24,
+ "size": 3
+ },
+ "XN": {
+ "description": "Instruction access disable\n bit",
+ "offset": 28,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "FPU": {
+ "description": "Floting point unit",
+ "children": {
+ "registers": {
+ "FPCCR": {
+ "description": "Floating-point context control\n register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LSPACT": {
+ "description": "LSPACT",
+ "offset": 0,
+ "size": 1
+ },
+ "USER": {
+ "description": "USER",
+ "offset": 1,
+ "size": 1
+ },
+ "THREAD": {
+ "description": "THREAD",
+ "offset": 3,
+ "size": 1
+ },
+ "HFRDY": {
+ "description": "HFRDY",
+ "offset": 4,
+ "size": 1
+ },
+ "MMRDY": {
+ "description": "MMRDY",
+ "offset": 5,
+ "size": 1
+ },
+ "BFRDY": {
+ "description": "BFRDY",
+ "offset": 6,
+ "size": 1
+ },
+ "MONRDY": {
+ "description": "MONRDY",
+ "offset": 8,
+ "size": 1
+ },
+ "LSPEN": {
+ "description": "LSPEN",
+ "offset": 30,
+ "size": 1
+ },
+ "ASPEN": {
+ "description": "ASPEN",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FPCAR": {
+ "description": "Floating-point context address\n register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ADDRESS": {
+ "description": "Location of unpopulated\n floating-point",
+ "offset": 3,
+ "size": 29
+ }
+ }
+ }
+ },
+ "FPSCR": {
+ "description": "Floating-point status control\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IOC": {
+ "description": "Invalid operation cumulative exception\n bit",
+ "offset": 0,
+ "size": 1
+ },
+ "DZC": {
+ "description": "Division by zero cumulative exception\n bit.",
+ "offset": 1,
+ "size": 1
+ },
+ "OFC": {
+ "description": "Overflow cumulative exception\n bit",
+ "offset": 2,
+ "size": 1
+ },
+ "UFC": {
+ "description": "Underflow cumulative exception\n bit",
+ "offset": 3,
+ "size": 1
+ },
+ "IXC": {
+ "description": "Inexact cumulative exception\n bit",
+ "offset": 4,
+ "size": 1
+ },
+ "IDC": {
+ "description": "Input denormal cumulative exception\n bit.",
+ "offset": 7,
+ "size": 1
+ },
+ "RMode": {
+ "description": "Rounding Mode control\n field",
+ "offset": 22,
+ "size": 2
+ },
+ "FZ": {
+ "description": "Flush-to-zero mode control\n bit:",
+ "offset": 24,
+ "size": 1
+ },
+ "DN": {
+ "description": "Default NaN mode control\n bit",
+ "offset": 25,
+ "size": 1
+ },
+ "AHP": {
+ "description": "Alternative half-precision control\n bit",
+ "offset": 26,
+ "size": 1
+ },
+ "V": {
+ "description": "Overflow condition code\n flag",
+ "offset": 28,
+ "size": 1
+ },
+ "C": {
+ "description": "Carry condition code flag",
+ "offset": 29,
+ "size": 1
+ },
+ "Z": {
+ "description": "Zero condition code flag",
+ "offset": 30,
+ "size": 1
+ },
+ "N": {
+ "description": "Negative condition code\n flag",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "TIM6": {
+ "description": "Basic timers",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARPE": {
+ "description": "Auto-reload preload enable",
+ "offset": 7,
+ "size": 1
+ },
+ "OPM": {
+ "description": "One-pulse mode",
+ "offset": 3,
+ "size": 1
+ },
+ "URS": {
+ "description": "Update request source",
+ "offset": 2,
+ "size": 1
+ },
+ "UDIS": {
+ "description": "Update disable",
+ "offset": 1,
+ "size": 1
+ },
+ "CEN": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MMS": {
+ "description": "Master mode selection",
+ "offset": 4,
+ "size": 3
+ }
+ }
+ }
+ },
+ "DIER": {
+ "description": "DMA/Interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "UDE": {
+ "description": "Update DMA request enable",
+ "offset": 8,
+ "size": 1
+ },
+ "UIE": {
+ "description": "Update interrupt enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "UIF": {
+ "description": "Update interrupt flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EGR": {
+ "description": "event generation register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "UG": {
+ "description": "Update generation",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNT": {
+ "description": "counter",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNT": {
+ "description": "Low counter value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "PSC": {
+ "description": "prescaler",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ARR": {
+ "description": "auto-reload register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARR": {
+ "description": "Low Auto-reload value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "Ethernet_MMC": {
+ "description": "Ethernet: MAC management counters",
+ "children": {
+ "registers": {
+ "MMCCR": {
+ "description": "Ethernet MMC control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CR": {
+ "description": "CR",
+ "offset": 0,
+ "size": 1
+ },
+ "CSR": {
+ "description": "CSR",
+ "offset": 1,
+ "size": 1
+ },
+ "ROR": {
+ "description": "ROR",
+ "offset": 2,
+ "size": 1
+ },
+ "MCF": {
+ "description": "MCF",
+ "offset": 3,
+ "size": 1
+ },
+ "MCP": {
+ "description": "MCP",
+ "offset": 4,
+ "size": 1
+ },
+ "MCFHP": {
+ "description": "MCFHP",
+ "offset": 5,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MMCRIR": {
+ "description": "Ethernet MMC receive interrupt\n register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RFCES": {
+ "description": "RFCES",
+ "offset": 5,
+ "size": 1
+ },
+ "RFAES": {
+ "description": "RFAES",
+ "offset": 6,
+ "size": 1
+ },
+ "RGUFS": {
+ "description": "RGUFS",
+ "offset": 17,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MMCTIR": {
+ "description": "Ethernet MMC transmit interrupt\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "TGFSCS": {
+ "description": "TGFSCS",
+ "offset": 14,
+ "size": 1
+ },
+ "TGFMSCS": {
+ "description": "TGFMSCS",
+ "offset": 15,
+ "size": 1
+ },
+ "TGFS": {
+ "description": "TGFS",
+ "offset": 21,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MMCRIMR": {
+ "description": "Ethernet MMC receive interrupt mask\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RFCEM": {
+ "description": "RFCEM",
+ "offset": 5,
+ "size": 1
+ },
+ "RFAEM": {
+ "description": "RFAEM",
+ "offset": 6,
+ "size": 1
+ },
+ "RGUFM": {
+ "description": "RGUFM",
+ "offset": 17,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MMCTIMR": {
+ "description": "Ethernet MMC transmit interrupt mask\n register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TGFSCM": {
+ "description": "TGFSCM",
+ "offset": 14,
+ "size": 1
+ },
+ "TGFMSCM": {
+ "description": "TGFMSCM",
+ "offset": 15,
+ "size": 1
+ },
+ "TGFM": {
+ "description": "TGFM",
+ "offset": 16,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MMCTGFSCCR": {
+ "description": "Ethernet MMC transmitted good frames after a\n single collision counter",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "TGFSCC": {
+ "description": "TGFSCC",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "MMCTGFMSCCR": {
+ "description": "Ethernet MMC transmitted good frames after\n more than a single collision",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "TGFMSCC": {
+ "description": "TGFMSCC",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "MMCTGFCR": {
+ "description": "Ethernet MMC transmitted good frames counter\n register",
+ "offset": 104,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "TGFC": {
+ "description": "HTL",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "MMCRFCECR": {
+ "description": "Ethernet MMC received frames with CRC error\n counter register",
+ "offset": 148,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "RFCFC": {
+ "description": "RFCFC",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "MMCRFAECR": {
+ "description": "Ethernet MMC received frames with alignment\n error counter register",
+ "offset": 152,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "RFAEC": {
+ "description": "RFAEC",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "MMCRGUFCR": {
+ "description": "MMC received good unicast frames counter\n register",
+ "offset": 196,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "RGUFC": {
+ "description": "RGUFC",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "GPIOB": {
+ "description": "General-purpose I/Os",
+ "children": {
+ "registers": {
+ "MODER": {
+ "description": "GPIO port mode register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 640,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MODER15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 30,
+ "size": 2
+ },
+ "MODER14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 28,
+ "size": 2
+ },
+ "MODER13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 26,
+ "size": 2
+ },
+ "MODER12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 24,
+ "size": 2
+ },
+ "MODER11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 22,
+ "size": 2
+ },
+ "MODER10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 20,
+ "size": 2
+ },
+ "MODER9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 18,
+ "size": 2
+ },
+ "MODER8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 16,
+ "size": 2
+ },
+ "MODER7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 2
+ },
+ "MODER6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 2
+ },
+ "MODER5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 2
+ },
+ "MODER4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 2
+ },
+ "MODER3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 2
+ },
+ "MODER2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 2
+ },
+ "MODER1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 2
+ },
+ "MODER0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTYPER": {
+ "description": "GPIO port output type register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OT15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "OT14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "OT13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "OT12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "OT11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "OT10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "OT9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "OT8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "OT7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "OT6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "OT5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "OT4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "OT3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "OT2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "OT1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "OT0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OSPEEDR": {
+ "description": "GPIO port output speed\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 192,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OSPEEDR15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 30,
+ "size": 2
+ },
+ "OSPEEDR14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 28,
+ "size": 2
+ },
+ "OSPEEDR13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 26,
+ "size": 2
+ },
+ "OSPEEDR12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 24,
+ "size": 2
+ },
+ "OSPEEDR11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 22,
+ "size": 2
+ },
+ "OSPEEDR10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 20,
+ "size": 2
+ },
+ "OSPEEDR9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 18,
+ "size": 2
+ },
+ "OSPEEDR8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 16,
+ "size": 2
+ },
+ "OSPEEDR7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 2
+ },
+ "OSPEEDR6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 2
+ },
+ "OSPEEDR5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 2
+ },
+ "OSPEEDR4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 2
+ },
+ "OSPEEDR3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 2
+ },
+ "OSPEEDR2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 2
+ },
+ "OSPEEDR1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 2
+ },
+ "OSPEEDR0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "PUPDR": {
+ "description": "GPIO port pull-up/pull-down\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 256,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PUPDR15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 30,
+ "size": 2
+ },
+ "PUPDR14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 28,
+ "size": 2
+ },
+ "PUPDR13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 26,
+ "size": 2
+ },
+ "PUPDR12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 24,
+ "size": 2
+ },
+ "PUPDR11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 22,
+ "size": 2
+ },
+ "PUPDR10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 20,
+ "size": 2
+ },
+ "PUPDR9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 18,
+ "size": 2
+ },
+ "PUPDR8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 16,
+ "size": 2
+ },
+ "PUPDR7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 2
+ },
+ "PUPDR6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 2
+ },
+ "PUPDR5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 2
+ },
+ "PUPDR4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 2
+ },
+ "PUPDR3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 2
+ },
+ "PUPDR2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 2
+ },
+ "PUPDR1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 2
+ },
+ "PUPDR0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "IDR": {
+ "description": "GPIO port input data register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "IDR15": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "IDR14": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "IDR13": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "IDR12": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "IDR11": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "IDR10": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "IDR9": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "IDR8": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "IDR7": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "IDR6": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "IDR5": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "IDR4": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "IDR3": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "IDR2": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "IDR1": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "IDR0": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ODR": {
+ "description": "GPIO port output data register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ODR15": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "ODR14": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "ODR13": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "ODR12": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "ODR11": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "ODR10": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "ODR9": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "ODR8": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "ODR7": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "ODR6": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "ODR5": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "ODR4": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "ODR3": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "ODR2": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "ODR1": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "ODR0": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BSRR": {
+ "description": "GPIO port bit set/reset\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "BR15": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 31,
+ "size": 1
+ },
+ "BR14": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 30,
+ "size": 1
+ },
+ "BR13": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 29,
+ "size": 1
+ },
+ "BR12": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 28,
+ "size": 1
+ },
+ "BR11": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 27,
+ "size": 1
+ },
+ "BR10": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 26,
+ "size": 1
+ },
+ "BR9": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 25,
+ "size": 1
+ },
+ "BR8": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 24,
+ "size": 1
+ },
+ "BR7": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 23,
+ "size": 1
+ },
+ "BR6": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 22,
+ "size": 1
+ },
+ "BR5": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 21,
+ "size": 1
+ },
+ "BR4": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 20,
+ "size": 1
+ },
+ "BR3": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 19,
+ "size": 1
+ },
+ "BR2": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 18,
+ "size": 1
+ },
+ "BR1": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 17,
+ "size": 1
+ },
+ "BR0": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 16,
+ "size": 1
+ },
+ "BS15": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "BS14": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "BS13": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "BS12": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "BS11": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "BS10": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "BS9": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "BS8": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "BS7": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "BS6": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "BS5": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "BS4": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "BS3": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "BS2": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "BS1": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "BS0": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "LCKR": {
+ "description": "GPIO port configuration lock\n register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LCKK": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 16,
+ "size": 1
+ },
+ "LCK15": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "LCK14": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "LCK13": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "LCK12": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "LCK11": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "LCK10": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "LCK9": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "LCK8": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "LCK7": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "LCK6": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "LCK5": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "LCK4": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "LCK3": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "LCK2": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "LCK1": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "LCK0": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "AFRL": {
+ "description": "GPIO alternate function low\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "AFRL7": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 28,
+ "size": 4
+ },
+ "AFRL6": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 24,
+ "size": 4
+ },
+ "AFRL5": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 20,
+ "size": 4
+ },
+ "AFRL4": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 16,
+ "size": 4
+ },
+ "AFRL3": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 12,
+ "size": 4
+ },
+ "AFRL2": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 8,
+ "size": 4
+ },
+ "AFRL1": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 4,
+ "size": 4
+ },
+ "AFRL0": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "AFRH": {
+ "description": "GPIO alternate function high\n register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "AFRH15": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 28,
+ "size": 4
+ },
+ "AFRH14": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 24,
+ "size": 4
+ },
+ "AFRH13": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 20,
+ "size": 4
+ },
+ "AFRH12": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 16,
+ "size": 4
+ },
+ "AFRH11": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 12,
+ "size": 4
+ },
+ "AFRH10": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 8,
+ "size": 4
+ },
+ "AFRH9": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 4,
+ "size": 4
+ },
+ "AFRH8": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "GPIOA": {
+ "description": "General-purpose I/Os",
+ "children": {
+ "registers": {
+ "MODER": {
+ "description": "GPIO port mode register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 2818572288,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MODER15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 30,
+ "size": 2
+ },
+ "MODER14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 28,
+ "size": 2
+ },
+ "MODER13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 26,
+ "size": 2
+ },
+ "MODER12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 24,
+ "size": 2
+ },
+ "MODER11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 22,
+ "size": 2
+ },
+ "MODER10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 20,
+ "size": 2
+ },
+ "MODER9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 18,
+ "size": 2
+ },
+ "MODER8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 16,
+ "size": 2
+ },
+ "MODER7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 2
+ },
+ "MODER6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 2
+ },
+ "MODER5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 2
+ },
+ "MODER4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 2
+ },
+ "MODER3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 2
+ },
+ "MODER2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 2
+ },
+ "MODER1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 2
+ },
+ "MODER0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTYPER": {
+ "description": "GPIO port output type register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OT15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "OT14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "OT13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "OT12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "OT11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "OT10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "OT9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "OT8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "OT7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "OT6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "OT5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "OT4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "OT3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "OT2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "OT1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "OT0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OSPEEDR": {
+ "description": "GPIO port output speed\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OSPEEDR15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 30,
+ "size": 2
+ },
+ "OSPEEDR14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 28,
+ "size": 2
+ },
+ "OSPEEDR13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 26,
+ "size": 2
+ },
+ "OSPEEDR12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 24,
+ "size": 2
+ },
+ "OSPEEDR11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 22,
+ "size": 2
+ },
+ "OSPEEDR10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 20,
+ "size": 2
+ },
+ "OSPEEDR9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 18,
+ "size": 2
+ },
+ "OSPEEDR8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 16,
+ "size": 2
+ },
+ "OSPEEDR7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 2
+ },
+ "OSPEEDR6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 2
+ },
+ "OSPEEDR5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 2
+ },
+ "OSPEEDR4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 2
+ },
+ "OSPEEDR3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 2
+ },
+ "OSPEEDR2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 2
+ },
+ "OSPEEDR1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 2
+ },
+ "OSPEEDR0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "PUPDR": {
+ "description": "GPIO port pull-up/pull-down\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 1677721600,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PUPDR15": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 30,
+ "size": 2
+ },
+ "PUPDR14": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 28,
+ "size": 2
+ },
+ "PUPDR13": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 26,
+ "size": 2
+ },
+ "PUPDR12": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 24,
+ "size": 2
+ },
+ "PUPDR11": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 22,
+ "size": 2
+ },
+ "PUPDR10": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 20,
+ "size": 2
+ },
+ "PUPDR9": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 18,
+ "size": 2
+ },
+ "PUPDR8": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 16,
+ "size": 2
+ },
+ "PUPDR7": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 14,
+ "size": 2
+ },
+ "PUPDR6": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 12,
+ "size": 2
+ },
+ "PUPDR5": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 10,
+ "size": 2
+ },
+ "PUPDR4": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 8,
+ "size": 2
+ },
+ "PUPDR3": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 6,
+ "size": 2
+ },
+ "PUPDR2": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 4,
+ "size": 2
+ },
+ "PUPDR1": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 2,
+ "size": 2
+ },
+ "PUPDR0": {
+ "description": "Port x configuration bits (y =\n 0..15)",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "IDR": {
+ "description": "GPIO port input data register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "IDR15": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "IDR14": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "IDR13": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "IDR12": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "IDR11": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "IDR10": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "IDR9": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "IDR8": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "IDR7": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "IDR6": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "IDR5": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "IDR4": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "IDR3": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "IDR2": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "IDR1": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "IDR0": {
+ "description": "Port input data (y =\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ODR": {
+ "description": "GPIO port output data register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ODR15": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "ODR14": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "ODR13": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "ODR12": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "ODR11": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "ODR10": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "ODR9": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "ODR8": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "ODR7": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "ODR6": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "ODR5": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "ODR4": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "ODR3": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "ODR2": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "ODR1": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "ODR0": {
+ "description": "Port output data (y =\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BSRR": {
+ "description": "GPIO port bit set/reset\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "BR15": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 31,
+ "size": 1
+ },
+ "BR14": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 30,
+ "size": 1
+ },
+ "BR13": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 29,
+ "size": 1
+ },
+ "BR12": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 28,
+ "size": 1
+ },
+ "BR11": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 27,
+ "size": 1
+ },
+ "BR10": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 26,
+ "size": 1
+ },
+ "BR9": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 25,
+ "size": 1
+ },
+ "BR8": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 24,
+ "size": 1
+ },
+ "BR7": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 23,
+ "size": 1
+ },
+ "BR6": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 22,
+ "size": 1
+ },
+ "BR5": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 21,
+ "size": 1
+ },
+ "BR4": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 20,
+ "size": 1
+ },
+ "BR3": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 19,
+ "size": 1
+ },
+ "BR2": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 18,
+ "size": 1
+ },
+ "BR1": {
+ "description": "Port x reset bit y (y =\n 0..15)",
+ "offset": 17,
+ "size": 1
+ },
+ "BR0": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 16,
+ "size": 1
+ },
+ "BS15": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "BS14": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "BS13": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "BS12": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "BS11": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "BS10": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "BS9": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "BS8": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "BS7": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "BS6": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "BS5": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "BS4": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "BS3": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "BS2": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "BS1": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "BS0": {
+ "description": "Port x set bit y (y=\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "LCKR": {
+ "description": "GPIO port configuration lock\n register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LCKK": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 16,
+ "size": 1
+ },
+ "LCK15": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 15,
+ "size": 1
+ },
+ "LCK14": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 14,
+ "size": 1
+ },
+ "LCK13": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 13,
+ "size": 1
+ },
+ "LCK12": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 12,
+ "size": 1
+ },
+ "LCK11": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 11,
+ "size": 1
+ },
+ "LCK10": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 10,
+ "size": 1
+ },
+ "LCK9": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 9,
+ "size": 1
+ },
+ "LCK8": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 8,
+ "size": 1
+ },
+ "LCK7": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 7,
+ "size": 1
+ },
+ "LCK6": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 6,
+ "size": 1
+ },
+ "LCK5": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 5,
+ "size": 1
+ },
+ "LCK4": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 4,
+ "size": 1
+ },
+ "LCK3": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 3,
+ "size": 1
+ },
+ "LCK2": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 2,
+ "size": 1
+ },
+ "LCK1": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 1,
+ "size": 1
+ },
+ "LCK0": {
+ "description": "Port x lock bit y (y=\n 0..15)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "AFRL": {
+ "description": "GPIO alternate function low\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "AFRL7": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 28,
+ "size": 4
+ },
+ "AFRL6": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 24,
+ "size": 4
+ },
+ "AFRL5": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 20,
+ "size": 4
+ },
+ "AFRL4": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 16,
+ "size": 4
+ },
+ "AFRL3": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 12,
+ "size": 4
+ },
+ "AFRL2": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 8,
+ "size": 4
+ },
+ "AFRL1": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 4,
+ "size": 4
+ },
+ "AFRL0": {
+ "description": "Alternate function selection for port x\n bit y (y = 0..7)",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "AFRH": {
+ "description": "GPIO alternate function high\n register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "AFRH15": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 28,
+ "size": 4
+ },
+ "AFRH14": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 24,
+ "size": 4
+ },
+ "AFRH13": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 20,
+ "size": 4
+ },
+ "AFRH12": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 16,
+ "size": 4
+ },
+ "AFRH11": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 12,
+ "size": 4
+ },
+ "AFRH10": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 8,
+ "size": 4
+ },
+ "AFRH9": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 4,
+ "size": 4
+ },
+ "AFRH8": {
+ "description": "Alternate function selection for port x\n bit y (y = 8..15)",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "SYSCFG": {
+ "description": "System configuration controller",
+ "children": {
+ "registers": {
+ "MEMRM": {
+ "description": "memory remap register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MEM_MODE": {
+ "description": "Memory mapping selection",
+ "offset": 0,
+ "size": 3
+ },
+ "FB_MODE": {
+ "description": "Flash bank mode selection",
+ "offset": 8,
+ "size": 1
+ },
+ "SWP_FMC": {
+ "description": "FMC memory mapping swap",
+ "offset": 10,
+ "size": 2
+ }
+ }
+ }
+ },
+ "PMC": {
+ "description": "peripheral mode configuration\n register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MII_RMII_SEL": {
+ "description": "Ethernet PHY interface\n selection",
+ "offset": 23,
+ "size": 1
+ },
+ "ADC1DC2": {
+ "description": "ADC1DC2",
+ "offset": 16,
+ "size": 1
+ },
+ "ADC2DC2": {
+ "description": "ADC2DC2",
+ "offset": 17,
+ "size": 1
+ },
+ "ADC3DC2": {
+ "description": "ADC3DC2",
+ "offset": 18,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EXTICR1": {
+ "description": "external interrupt configuration register\n 1",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EXTI3": {
+ "description": "EXTI x configuration (x = 0 to\n 3)",
+ "offset": 12,
+ "size": 4
+ },
+ "EXTI2": {
+ "description": "EXTI x configuration (x = 0 to\n 3)",
+ "offset": 8,
+ "size": 4
+ },
+ "EXTI1": {
+ "description": "EXTI x configuration (x = 0 to\n 3)",
+ "offset": 4,
+ "size": 4
+ },
+ "EXTI0": {
+ "description": "EXTI x configuration (x = 0 to\n 3)",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "EXTICR2": {
+ "description": "external interrupt configuration register\n 2",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EXTI7": {
+ "description": "EXTI x configuration (x = 4 to\n 7)",
+ "offset": 12,
+ "size": 4
+ },
+ "EXTI6": {
+ "description": "EXTI x configuration (x = 4 to\n 7)",
+ "offset": 8,
+ "size": 4
+ },
+ "EXTI5": {
+ "description": "EXTI x configuration (x = 4 to\n 7)",
+ "offset": 4,
+ "size": 4
+ },
+ "EXTI4": {
+ "description": "EXTI x configuration (x = 4 to\n 7)",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "EXTICR3": {
+ "description": "external interrupt configuration register\n 3",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EXTI11": {
+ "description": "EXTI x configuration (x = 8 to\n 11)",
+ "offset": 12,
+ "size": 4
+ },
+ "EXTI10": {
+ "description": "EXTI10",
+ "offset": 8,
+ "size": 4
+ },
+ "EXTI9": {
+ "description": "EXTI x configuration (x = 8 to\n 11)",
+ "offset": 4,
+ "size": 4
+ },
+ "EXTI8": {
+ "description": "EXTI x configuration (x = 8 to\n 11)",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "EXTICR4": {
+ "description": "external interrupt configuration register\n 4",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EXTI15": {
+ "description": "EXTI x configuration (x = 12 to\n 15)",
+ "offset": 12,
+ "size": 4
+ },
+ "EXTI14": {
+ "description": "EXTI x configuration (x = 12 to\n 15)",
+ "offset": 8,
+ "size": 4
+ },
+ "EXTI13": {
+ "description": "EXTI x configuration (x = 12 to\n 15)",
+ "offset": 4,
+ "size": 4
+ },
+ "EXTI12": {
+ "description": "EXTI x configuration (x = 12 to\n 15)",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "CMPCR": {
+ "description": "Compensation cell control\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "READY": {
+ "description": "READY",
+ "offset": 8,
+ "size": 1
+ },
+ "CMP_PD": {
+ "description": "Compensation cell\n power-down",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "SPI1": {
+ "description": "Serial peripheral interface",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BIDIMODE": {
+ "description": "Bidirectional data mode\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "BIDIOE": {
+ "description": "Output enable in bidirectional\n mode",
+ "offset": 14,
+ "size": 1
+ },
+ "CRCEN": {
+ "description": "Hardware CRC calculation\n enable",
+ "offset": 13,
+ "size": 1
+ },
+ "CRCNEXT": {
+ "description": "CRC transfer next",
+ "offset": 12,
+ "size": 1
+ },
+ "DFF": {
+ "description": "Data frame format",
+ "offset": 11,
+ "size": 1
+ },
+ "RXONLY": {
+ "description": "Receive only",
+ "offset": 10,
+ "size": 1
+ },
+ "SSM": {
+ "description": "Software slave management",
+ "offset": 9,
+ "size": 1
+ },
+ "SSI": {
+ "description": "Internal slave select",
+ "offset": 8,
+ "size": 1
+ },
+ "LSBFIRST": {
+ "description": "Frame format",
+ "offset": 7,
+ "size": 1
+ },
+ "SPE": {
+ "description": "SPI enable",
+ "offset": 6,
+ "size": 1
+ },
+ "BR": {
+ "description": "Baud rate control",
+ "offset": 3,
+ "size": 3
+ },
+ "MSTR": {
+ "description": "Master selection",
+ "offset": 2,
+ "size": 1
+ },
+ "CPOL": {
+ "description": "Clock polarity",
+ "offset": 1,
+ "size": 1
+ },
+ "CPHA": {
+ "description": "Clock phase",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TXEIE": {
+ "description": "Tx buffer empty interrupt\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "RXNEIE": {
+ "description": "RX buffer not empty interrupt\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "ERRIE": {
+ "description": "Error interrupt enable",
+ "offset": 5,
+ "size": 1
+ },
+ "FRF": {
+ "description": "Frame format",
+ "offset": 4,
+ "size": 1
+ },
+ "SSOE": {
+ "description": "SS output enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TXDMAEN": {
+ "description": "Tx buffer DMA enable",
+ "offset": 1,
+ "size": 1
+ },
+ "RXDMAEN": {
+ "description": "Rx buffer DMA enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 2,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIFRFE": {
+ "description": "TI frame format error",
+ "offset": 8,
+ "size": 1,
+ "access": "read-only"
+ },
+ "BSY": {
+ "description": "Busy flag",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "OVR": {
+ "description": "Overrun flag",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "MODF": {
+ "description": "Mode fault",
+ "offset": 5,
+ "size": 1,
+ "access": "read-only"
+ },
+ "CRCERR": {
+ "description": "CRC error flag",
+ "offset": 4,
+ "size": 1
+ },
+ "UDR": {
+ "description": "Underrun flag",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "CHSIDE": {
+ "description": "Channel side",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TXE": {
+ "description": "Transmit buffer empty",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "RXNE": {
+ "description": "Receive buffer not empty",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "DR": {
+ "description": "data register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DR": {
+ "description": "Data register",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CRCPR": {
+ "description": "CRC polynomial register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 7,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CRCPOLY": {
+ "description": "CRC polynomial register",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "RXCRCR": {
+ "description": "RX CRC register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "RxCRC": {
+ "description": "Rx CRC register",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "TXCRCR": {
+ "description": "TX CRC register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "TxCRC": {
+ "description": "Tx CRC register",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "I2SCFGR": {
+ "description": "I2S configuration register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "I2SMOD": {
+ "description": "I2S mode selection",
+ "offset": 11,
+ "size": 1
+ },
+ "I2SE": {
+ "description": "I2S Enable",
+ "offset": 10,
+ "size": 1
+ },
+ "I2SCFG": {
+ "description": "I2S configuration mode",
+ "offset": 8,
+ "size": 2
+ },
+ "PCMSYNC": {
+ "description": "PCM frame synchronization",
+ "offset": 7,
+ "size": 1
+ },
+ "I2SSTD": {
+ "description": "I2S standard selection",
+ "offset": 4,
+ "size": 2
+ },
+ "CKPOL": {
+ "description": "Steady state clock\n polarity",
+ "offset": 3,
+ "size": 1
+ },
+ "DATLEN": {
+ "description": "Data length to be\n transferred",
+ "offset": 1,
+ "size": 2
+ },
+ "CHLEN": {
+ "description": "Channel length (number of bits per audio\n channel)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "I2SPR": {
+ "description": "I2S prescaler register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 10,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MCKOE": {
+ "description": "Master clock output enable",
+ "offset": 9,
+ "size": 1
+ },
+ "ODD": {
+ "description": "Odd factor for the\n prescaler",
+ "offset": 8,
+ "size": 1
+ },
+ "I2SDIV": {
+ "description": "I2S Linear prescaler",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "I2C3": {
+ "description": "Inter-integrated circuit",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "Control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SWRST": {
+ "description": "Software reset",
+ "offset": 15,
+ "size": 1
+ },
+ "ALERT": {
+ "description": "SMBus alert",
+ "offset": 13,
+ "size": 1
+ },
+ "PEC": {
+ "description": "Packet error checking",
+ "offset": 12,
+ "size": 1
+ },
+ "POS": {
+ "description": "Acknowledge/PEC Position (for data\n reception)",
+ "offset": 11,
+ "size": 1
+ },
+ "ACK": {
+ "description": "Acknowledge enable",
+ "offset": 10,
+ "size": 1
+ },
+ "STOP": {
+ "description": "Stop generation",
+ "offset": 9,
+ "size": 1
+ },
+ "START": {
+ "description": "Start generation",
+ "offset": 8,
+ "size": 1
+ },
+ "NOSTRETCH": {
+ "description": "Clock stretching disable (Slave\n mode)",
+ "offset": 7,
+ "size": 1
+ },
+ "ENGC": {
+ "description": "General call enable",
+ "offset": 6,
+ "size": 1
+ },
+ "ENPEC": {
+ "description": "PEC enable",
+ "offset": 5,
+ "size": 1
+ },
+ "ENARP": {
+ "description": "ARP enable",
+ "offset": 4,
+ "size": 1
+ },
+ "SMBTYPE": {
+ "description": "SMBus type",
+ "offset": 3,
+ "size": 1
+ },
+ "SMBUS": {
+ "description": "SMBus mode",
+ "offset": 1,
+ "size": 1
+ },
+ "PE": {
+ "description": "Peripheral enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "Control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LAST": {
+ "description": "DMA last transfer",
+ "offset": 12,
+ "size": 1
+ },
+ "DMAEN": {
+ "description": "DMA requests enable",
+ "offset": 11,
+ "size": 1
+ },
+ "ITBUFEN": {
+ "description": "Buffer interrupt enable",
+ "offset": 10,
+ "size": 1
+ },
+ "ITEVTEN": {
+ "description": "Event interrupt enable",
+ "offset": 9,
+ "size": 1
+ },
+ "ITERREN": {
+ "description": "Error interrupt enable",
+ "offset": 8,
+ "size": 1
+ },
+ "FREQ": {
+ "description": "Peripheral clock frequency",
+ "offset": 0,
+ "size": 6
+ }
+ }
+ }
+ },
+ "OAR1": {
+ "description": "Own address register 1",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ADDMODE": {
+ "description": "Addressing mode (slave\n mode)",
+ "offset": 15,
+ "size": 1
+ },
+ "ADD10": {
+ "description": "Interface address",
+ "offset": 8,
+ "size": 2
+ },
+ "ADD7": {
+ "description": "Interface address",
+ "offset": 1,
+ "size": 7
+ },
+ "ADD0": {
+ "description": "Interface address",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OAR2": {
+ "description": "Own address register 2",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ADD2": {
+ "description": "Interface address",
+ "offset": 1,
+ "size": 7
+ },
+ "ENDUAL": {
+ "description": "Dual addressing mode\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DR": {
+ "description": "Data register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DR": {
+ "description": "8-bit data register",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "SR1": {
+ "description": "Status register 1",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SMBALERT": {
+ "description": "SMBus alert",
+ "offset": 15,
+ "size": 1
+ },
+ "TIMEOUT": {
+ "description": "Timeout or Tlow error",
+ "offset": 14,
+ "size": 1
+ },
+ "PECERR": {
+ "description": "PEC Error in reception",
+ "offset": 12,
+ "size": 1
+ },
+ "OVR": {
+ "description": "Overrun/Underrun",
+ "offset": 11,
+ "size": 1
+ },
+ "AF": {
+ "description": "Acknowledge failure",
+ "offset": 10,
+ "size": 1
+ },
+ "ARLO": {
+ "description": "Arbitration lost (master\n mode)",
+ "offset": 9,
+ "size": 1
+ },
+ "BERR": {
+ "description": "Bus error",
+ "offset": 8,
+ "size": 1
+ },
+ "TxE": {
+ "description": "Data register empty\n (transmitters)",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "RxNE": {
+ "description": "Data register not empty\n (receivers)",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "STOPF": {
+ "description": "Stop detection (slave\n mode)",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ADD10": {
+ "description": "10-bit header sent (Master\n mode)",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "BTF": {
+ "description": "Byte transfer finished",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ADDR": {
+ "description": "Address sent (master mode)/matched\n (slave mode)",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SB": {
+ "description": "Start bit (Master mode)",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "SR2": {
+ "description": "Status register 2",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "PEC": {
+ "description": "acket error checking\n register",
+ "offset": 8,
+ "size": 8
+ },
+ "DUALF": {
+ "description": "Dual flag (Slave mode)",
+ "offset": 7,
+ "size": 1
+ },
+ "SMBHOST": {
+ "description": "SMBus host header (Slave\n mode)",
+ "offset": 6,
+ "size": 1
+ },
+ "SMBDEFAULT": {
+ "description": "SMBus device default address (Slave\n mode)",
+ "offset": 5,
+ "size": 1
+ },
+ "GENCALL": {
+ "description": "General call address (Slave\n mode)",
+ "offset": 4,
+ "size": 1
+ },
+ "TRA": {
+ "description": "Transmitter/receiver",
+ "offset": 2,
+ "size": 1
+ },
+ "BUSY": {
+ "description": "Bus busy",
+ "offset": 1,
+ "size": 1
+ },
+ "MSL": {
+ "description": "Master/slave",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCR": {
+ "description": "Clock control register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "F_S": {
+ "description": "I2C master mode selection",
+ "offset": 15,
+ "size": 1
+ },
+ "DUTY": {
+ "description": "Fast mode duty cycle",
+ "offset": 14,
+ "size": 1
+ },
+ "CCR": {
+ "description": "Clock control register in Fast/Standard\n mode (Master mode)",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "TRISE": {
+ "description": "TRISE register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 2,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TRISE": {
+ "description": "Maximum rise time in Fast/Standard mode\n (Master mode)",
+ "offset": 0,
+ "size": 6
+ }
+ }
+ }
+ },
+ "FLTR": {
+ "description": "I2C FLTR register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DNF": {
+ "description": "Digital noise filter",
+ "offset": 0,
+ "size": 4
+ },
+ "ANOFF": {
+ "description": "Analog noise filter OFF",
+ "offset": 4,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "DMA2D": {
+ "description": "DMA2D controller",
+ "children": {
+ "registers": {
+ "CR": {
+ "description": "control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MODE": {
+ "description": "DMA2D mode",
+ "offset": 16,
+ "size": 2
+ },
+ "CEIE": {
+ "description": "Configuration Error Interrupt\n Enable",
+ "offset": 13,
+ "size": 1
+ },
+ "CTCIE": {
+ "description": "CLUT transfer complete interrupt\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "CAEIE": {
+ "description": "CLUT access error interrupt\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "TWIE": {
+ "description": "Transfer watermark interrupt\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transfer complete interrupt\n enable",
+ "offset": 9,
+ "size": 1
+ },
+ "TEIE": {
+ "description": "Transfer error interrupt\n enable",
+ "offset": 8,
+ "size": 1
+ },
+ "ABORT": {
+ "description": "Abort",
+ "offset": 2,
+ "size": 1
+ },
+ "SUSP": {
+ "description": "Suspend",
+ "offset": 1,
+ "size": 1
+ },
+ "START": {
+ "description": "Start",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ISR": {
+ "description": "Interrupt Status Register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CEIF": {
+ "description": "Configuration error interrupt\n flag",
+ "offset": 5,
+ "size": 1
+ },
+ "CTCIF": {
+ "description": "CLUT transfer complete interrupt\n flag",
+ "offset": 4,
+ "size": 1
+ },
+ "CAEIF": {
+ "description": "CLUT access error interrupt\n flag",
+ "offset": 3,
+ "size": 1
+ },
+ "TWIF": {
+ "description": "Transfer watermark interrupt\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "TCIF": {
+ "description": "Transfer complete interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "TEIF": {
+ "description": "Transfer error interrupt\n flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "IFCR": {
+ "description": "interrupt flag clear register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCEIF": {
+ "description": "Clear configuration error interrupt\n flag",
+ "offset": 5,
+ "size": 1
+ },
+ "CCTCIF": {
+ "description": "Clear CLUT transfer complete interrupt\n flag",
+ "offset": 4,
+ "size": 1
+ },
+ "CAECIF": {
+ "description": "Clear CLUT access error interrupt\n flag",
+ "offset": 3,
+ "size": 1
+ },
+ "CTWIF": {
+ "description": "Clear transfer watermark interrupt\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "CTCIF": {
+ "description": "Clear transfer complete interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "CTEIF": {
+ "description": "Clear Transfer error interrupt\n flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FGMAR": {
+ "description": "foreground memory address\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MA": {
+ "description": "Memory address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "FGOR": {
+ "description": "foreground offset register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LO": {
+ "description": "Line offset",
+ "offset": 0,
+ "size": 14
+ }
+ }
+ }
+ },
+ "BGMAR": {
+ "description": "background memory address\n register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MA": {
+ "description": "Memory address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BGOR": {
+ "description": "background offset register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LO": {
+ "description": "Line offset",
+ "offset": 0,
+ "size": 14
+ }
+ }
+ }
+ },
+ "FGPFCCR": {
+ "description": "foreground PFC control\n register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ALPHA": {
+ "description": "Alpha value",
+ "offset": 24,
+ "size": 8
+ },
+ "AM": {
+ "description": "Alpha mode",
+ "offset": 16,
+ "size": 2
+ },
+ "CS": {
+ "description": "CLUT size",
+ "offset": 8,
+ "size": 8
+ },
+ "START": {
+ "description": "Start",
+ "offset": 5,
+ "size": 1
+ },
+ "CCM": {
+ "description": "CLUT color mode",
+ "offset": 4,
+ "size": 1
+ },
+ "CM": {
+ "description": "Color mode",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "FGCOLR": {
+ "description": "foreground color register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RED": {
+ "description": "Red Value",
+ "offset": 16,
+ "size": 8
+ },
+ "GREEN": {
+ "description": "Green Value",
+ "offset": 8,
+ "size": 8
+ },
+ "BLUE": {
+ "description": "Blue Value",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "BGPFCCR": {
+ "description": "background PFC control\n register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ALPHA": {
+ "description": "Alpha value",
+ "offset": 24,
+ "size": 8
+ },
+ "AM": {
+ "description": "Alpha mode",
+ "offset": 16,
+ "size": 2
+ },
+ "CS": {
+ "description": "CLUT size",
+ "offset": 8,
+ "size": 8
+ },
+ "START": {
+ "description": "Start",
+ "offset": 5,
+ "size": 1
+ },
+ "CCM": {
+ "description": "CLUT Color mode",
+ "offset": 4,
+ "size": 1
+ },
+ "CM": {
+ "description": "Color mode",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "BGCOLR": {
+ "description": "background color register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RED": {
+ "description": "Red Value",
+ "offset": 16,
+ "size": 8
+ },
+ "GREEN": {
+ "description": "Green Value",
+ "offset": 8,
+ "size": 8
+ },
+ "BLUE": {
+ "description": "Blue Value",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "FGCMAR": {
+ "description": "foreground CLUT memory address\n register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MA": {
+ "description": "Memory Address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BGCMAR": {
+ "description": "background CLUT memory address\n register",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MA": {
+ "description": "Memory address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OPFCCR": {
+ "description": "output PFC control register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CM": {
+ "description": "Color mode",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "OCOLR": {
+ "description": "output color register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "APLHA": {
+ "description": "Alpha Channel Value",
+ "offset": 24,
+ "size": 8
+ },
+ "RED": {
+ "description": "Red Value",
+ "offset": 16,
+ "size": 8
+ },
+ "GREEN": {
+ "description": "Green Value",
+ "offset": 8,
+ "size": 8
+ },
+ "BLUE": {
+ "description": "Blue Value",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "OMAR": {
+ "description": "output memory address register",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MA": {
+ "description": "Memory Address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OOR": {
+ "description": "output offset register",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LO": {
+ "description": "Line Offset",
+ "offset": 0,
+ "size": 14
+ }
+ }
+ }
+ },
+ "NLR": {
+ "description": "number of line register",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PL": {
+ "description": "Pixel per lines",
+ "offset": 16,
+ "size": 14
+ },
+ "NL": {
+ "description": "Number of lines",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "LWR": {
+ "description": "line watermark register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LW": {
+ "description": "Line watermark",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "AMTCR": {
+ "description": "AHB master timer configuration\n register",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DT": {
+ "description": "Dead Time",
+ "offset": 8,
+ "size": 8
+ },
+ "EN": {
+ "description": "Enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FGCLUT": {
+ "description": "FGCLUT",
+ "offset": 1024,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "APLHA": {
+ "description": "APLHA",
+ "offset": 24,
+ "size": 8
+ },
+ "RED": {
+ "description": "RED",
+ "offset": 16,
+ "size": 8
+ },
+ "GREEN": {
+ "description": "GREEN",
+ "offset": 8,
+ "size": 8
+ },
+ "BLUE": {
+ "description": "BLUE",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "BGCLUT": {
+ "description": "BGCLUT",
+ "offset": 2048,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "APLHA": {
+ "description": "APLHA",
+ "offset": 24,
+ "size": 8
+ },
+ "RED": {
+ "description": "RED",
+ "offset": 16,
+ "size": 8
+ },
+ "GREEN": {
+ "description": "GREEN",
+ "offset": 8,
+ "size": 8
+ },
+ "BLUE": {
+ "description": "BLUE",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "SAI": {
+ "description": "Serial audio interface",
+ "children": {
+ "registers": {
+ "BCR1": {
+ "description": "BConfiguration register 1",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 64,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MCJDIV": {
+ "description": "Master clock divider",
+ "offset": 20,
+ "size": 4
+ },
+ "NODIV": {
+ "description": "No divider",
+ "offset": 19,
+ "size": 1
+ },
+ "DMAEN": {
+ "description": "DMA enable",
+ "offset": 17,
+ "size": 1
+ },
+ "SAIBEN": {
+ "description": "Audio block B enable",
+ "offset": 16,
+ "size": 1
+ },
+ "OutDri": {
+ "description": "Output drive",
+ "offset": 13,
+ "size": 1
+ },
+ "MONO": {
+ "description": "Mono mode",
+ "offset": 12,
+ "size": 1
+ },
+ "SYNCEN": {
+ "description": "Synchronization enable",
+ "offset": 10,
+ "size": 2
+ },
+ "CKSTR": {
+ "description": "Clock strobing edge",
+ "offset": 9,
+ "size": 1
+ },
+ "LSBFIRST": {
+ "description": "Least significant bit\n first",
+ "offset": 8,
+ "size": 1
+ },
+ "DS": {
+ "description": "Data size",
+ "offset": 5,
+ "size": 3
+ },
+ "PRTCFG": {
+ "description": "Protocol configuration",
+ "offset": 2,
+ "size": 2
+ },
+ "MODE": {
+ "description": "Audio block mode",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "BCR2": {
+ "description": "BConfiguration register 2",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "COMP": {
+ "description": "Companding mode",
+ "offset": 14,
+ "size": 2
+ },
+ "CPL": {
+ "description": "Complement bit",
+ "offset": 13,
+ "size": 1
+ },
+ "MUTECN": {
+ "description": "Mute counter",
+ "offset": 7,
+ "size": 6
+ },
+ "MUTEVAL": {
+ "description": "Mute value",
+ "offset": 6,
+ "size": 1
+ },
+ "MUTE": {
+ "description": "Mute",
+ "offset": 5,
+ "size": 1
+ },
+ "TRIS": {
+ "description": "Tristate management on data\n line",
+ "offset": 4,
+ "size": 1
+ },
+ "FFLUS": {
+ "description": "FIFO flush",
+ "offset": 3,
+ "size": 1
+ },
+ "FTH": {
+ "description": "FIFO threshold",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "BFRCR": {
+ "description": "BFRCR",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 7,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FSOFF": {
+ "description": "Frame synchronization\n offset",
+ "offset": 18,
+ "size": 1
+ },
+ "FSPOL": {
+ "description": "Frame synchronization\n polarity",
+ "offset": 17,
+ "size": 1
+ },
+ "FSDEF": {
+ "description": "Frame synchronization\n definition",
+ "offset": 16,
+ "size": 1
+ },
+ "FSALL": {
+ "description": "Frame synchronization active level\n length",
+ "offset": 8,
+ "size": 7
+ },
+ "FRL": {
+ "description": "Frame length",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "BSLOTR": {
+ "description": "BSlot register",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SLOTEN": {
+ "description": "Slot enable",
+ "offset": 16,
+ "size": 16
+ },
+ "NBSLOT": {
+ "description": "Number of slots in an audio\n frame",
+ "offset": 8,
+ "size": 4
+ },
+ "SLOTSZ": {
+ "description": "Slot size",
+ "offset": 6,
+ "size": 2
+ },
+ "FBOFF": {
+ "description": "First bit offset",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "BIM": {
+ "description": "BInterrupt mask register2",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LFSDETIE": {
+ "description": "Late frame synchronization detection\n interrupt enable",
+ "offset": 6,
+ "size": 1
+ },
+ "AFSDETIE": {
+ "description": "Anticipated frame synchronization\n detection interrupt enable",
+ "offset": 5,
+ "size": 1
+ },
+ "CNRDYIE": {
+ "description": "Codec not ready interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "FREQIE": {
+ "description": "FIFO request interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "WCKCFG": {
+ "description": "Wrong clock configuration interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "MUTEDET": {
+ "description": "Mute detection interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "OVRUDRIE": {
+ "description": "Overrun/underrun interrupt\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BSR": {
+ "description": "BStatus register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "FLVL": {
+ "description": "FIFO level threshold",
+ "offset": 16,
+ "size": 3
+ },
+ "LFSDET": {
+ "description": "Late frame synchronization\n detection",
+ "offset": 6,
+ "size": 1
+ },
+ "AFSDET": {
+ "description": "Anticipated frame synchronization\n detection",
+ "offset": 5,
+ "size": 1
+ },
+ "CNRDY": {
+ "description": "Codec not ready",
+ "offset": 4,
+ "size": 1
+ },
+ "FREQ": {
+ "description": "FIFO request",
+ "offset": 3,
+ "size": 1
+ },
+ "WCKCFG": {
+ "description": "Wrong clock configuration\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "MUTEDET": {
+ "description": "Mute detection",
+ "offset": 1,
+ "size": 1
+ },
+ "OVRUDR": {
+ "description": "Overrun / underrun",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BCLRFR": {
+ "description": "BClear flag register",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "LFSDET": {
+ "description": "Clear late frame synchronization\n detection flag",
+ "offset": 6,
+ "size": 1
+ },
+ "CAFSDET": {
+ "description": "Clear anticipated frame synchronization\n detection flag",
+ "offset": 5,
+ "size": 1
+ },
+ "CNRDY": {
+ "description": "Clear codec not ready flag",
+ "offset": 4,
+ "size": 1
+ },
+ "WCKCFG": {
+ "description": "Clear wrong clock configuration\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "MUTEDET": {
+ "description": "Mute detection flag",
+ "offset": 1,
+ "size": 1
+ },
+ "OVRUDR": {
+ "description": "Clear overrun / underrun",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BDR": {
+ "description": "BData register",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATA": {
+ "description": "Data",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ACR1": {
+ "description": "AConfiguration register 1",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 64,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MCJDIV": {
+ "description": "Master clock divider",
+ "offset": 20,
+ "size": 4
+ },
+ "NODIV": {
+ "description": "No divider",
+ "offset": 19,
+ "size": 1
+ },
+ "DMAEN": {
+ "description": "DMA enable",
+ "offset": 17,
+ "size": 1
+ },
+ "SAIAEN": {
+ "description": "Audio block A enable",
+ "offset": 16,
+ "size": 1
+ },
+ "OutDri": {
+ "description": "Output drive",
+ "offset": 13,
+ "size": 1
+ },
+ "MONO": {
+ "description": "Mono mode",
+ "offset": 12,
+ "size": 1
+ },
+ "SYNCEN": {
+ "description": "Synchronization enable",
+ "offset": 10,
+ "size": 2
+ },
+ "CKSTR": {
+ "description": "Clock strobing edge",
+ "offset": 9,
+ "size": 1
+ },
+ "LSBFIRST": {
+ "description": "Least significant bit\n first",
+ "offset": 8,
+ "size": 1
+ },
+ "DS": {
+ "description": "Data size",
+ "offset": 5,
+ "size": 3
+ },
+ "PRTCFG": {
+ "description": "Protocol configuration",
+ "offset": 2,
+ "size": 2
+ },
+ "MODE": {
+ "description": "Audio block mode",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "ACR2": {
+ "description": "AConfiguration register 2",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "COMP": {
+ "description": "Companding mode",
+ "offset": 14,
+ "size": 2
+ },
+ "CPL": {
+ "description": "Complement bit",
+ "offset": 13,
+ "size": 1
+ },
+ "MUTECN": {
+ "description": "Mute counter",
+ "offset": 7,
+ "size": 6
+ },
+ "MUTEVAL": {
+ "description": "Mute value",
+ "offset": 6,
+ "size": 1
+ },
+ "MUTE": {
+ "description": "Mute",
+ "offset": 5,
+ "size": 1
+ },
+ "TRIS": {
+ "description": "Tristate management on data\n line",
+ "offset": 4,
+ "size": 1
+ },
+ "FFLUS": {
+ "description": "FIFO flush",
+ "offset": 3,
+ "size": 1
+ },
+ "FTH": {
+ "description": "FIFO threshold",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "AFRCR": {
+ "description": "AFRCR",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 7,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FSOFF": {
+ "description": "Frame synchronization\n offset",
+ "offset": 18,
+ "size": 1
+ },
+ "FSPOL": {
+ "description": "Frame synchronization\n polarity",
+ "offset": 17,
+ "size": 1
+ },
+ "FSDEF": {
+ "description": "Frame synchronization\n definition",
+ "offset": 16,
+ "size": 1
+ },
+ "FSALL": {
+ "description": "Frame synchronization active level\n length",
+ "offset": 8,
+ "size": 7
+ },
+ "FRL": {
+ "description": "Frame length",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "ASLOTR": {
+ "description": "ASlot register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SLOTEN": {
+ "description": "Slot enable",
+ "offset": 16,
+ "size": 16
+ },
+ "NBSLOT": {
+ "description": "Number of slots in an audio\n frame",
+ "offset": 8,
+ "size": 4
+ },
+ "SLOTSZ": {
+ "description": "Slot size",
+ "offset": 6,
+ "size": 2
+ },
+ "FBOFF": {
+ "description": "First bit offset",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "AIM": {
+ "description": "AInterrupt mask register2",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LFSDET": {
+ "description": "Late frame synchronization detection\n interrupt enable",
+ "offset": 6,
+ "size": 1
+ },
+ "AFSDETIE": {
+ "description": "Anticipated frame synchronization\n detection interrupt enable",
+ "offset": 5,
+ "size": 1
+ },
+ "CNRDYIE": {
+ "description": "Codec not ready interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "FREQIE": {
+ "description": "FIFO request interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "WCKCFG": {
+ "description": "Wrong clock configuration interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "MUTEDET": {
+ "description": "Mute detection interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "OVRUDRIE": {
+ "description": "Overrun/underrun interrupt\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ASR": {
+ "description": "AStatus register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FLVL": {
+ "description": "FIFO level threshold",
+ "offset": 16,
+ "size": 3
+ },
+ "LFSDET": {
+ "description": "Late frame synchronization\n detection",
+ "offset": 6,
+ "size": 1
+ },
+ "AFSDET": {
+ "description": "Anticipated frame synchronization\n detection",
+ "offset": 5,
+ "size": 1
+ },
+ "CNRDY": {
+ "description": "Codec not ready",
+ "offset": 4,
+ "size": 1
+ },
+ "FREQ": {
+ "description": "FIFO request",
+ "offset": 3,
+ "size": 1
+ },
+ "WCKCFG": {
+ "description": "Wrong clock configuration flag. This bit\n is read only.",
+ "offset": 2,
+ "size": 1
+ },
+ "MUTEDET": {
+ "description": "Mute detection",
+ "offset": 1,
+ "size": 1
+ },
+ "OVRUDR": {
+ "description": "Overrun / underrun",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ACLRFR": {
+ "description": "AClear flag register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LFSDET": {
+ "description": "Clear late frame synchronization\n detection flag",
+ "offset": 6,
+ "size": 1
+ },
+ "CAFSDET": {
+ "description": "Clear anticipated frame synchronization\n detection flag.",
+ "offset": 5,
+ "size": 1
+ },
+ "CNRDY": {
+ "description": "Clear codec not ready flag",
+ "offset": 4,
+ "size": 1
+ },
+ "WCKCFG": {
+ "description": "Clear wrong clock configuration\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "MUTEDET": {
+ "description": "Mute detection flag",
+ "offset": 1,
+ "size": 1
+ },
+ "OVRUDR": {
+ "description": "Clear overrun / underrun",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ADR": {
+ "description": "AData register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATA": {
+ "description": "Data",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "LTDC": {
+ "description": "LCD-TFT Controller",
+ "children": {
+ "registers": {
+ "SSCR": {
+ "description": "Synchronization Size Configuration\n Register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "HSW": {
+ "description": "Horizontal Synchronization Width (in\n units of pixel clock period)",
+ "offset": 16,
+ "size": 10
+ },
+ "VSH": {
+ "description": "Vertical Synchronization Height (in\n units of horizontal scan line)",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "BPCR": {
+ "description": "Back Porch Configuration\n Register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "AHBP": {
+ "description": "Accumulated Horizontal back porch (in\n units of pixel clock period)",
+ "offset": 16,
+ "size": 10
+ },
+ "AVBP": {
+ "description": "Accumulated Vertical back porch (in\n units of horizontal scan line)",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "AWCR": {
+ "description": "Active Width Configuration\n Register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "AAV": {
+ "description": "AAV",
+ "offset": 16,
+ "size": 10
+ },
+ "AAH": {
+ "description": "Accumulated Active Height (in units of\n horizontal scan line)",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "TWCR": {
+ "description": "Total Width Configuration\n Register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TOTALW": {
+ "description": "Total Width (in units of pixel clock\n period)",
+ "offset": 16,
+ "size": 10
+ },
+ "TOTALH": {
+ "description": "Total Height (in units of horizontal\n scan line)",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "GCR": {
+ "description": "Global Control Register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 8736,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "HSPOL": {
+ "description": "Horizontal Synchronization\n Polarity",
+ "offset": 31,
+ "size": 1
+ },
+ "VSPOL": {
+ "description": "Vertical Synchronization\n Polarity",
+ "offset": 30,
+ "size": 1
+ },
+ "DEPOL": {
+ "description": "Data Enable Polarity",
+ "offset": 29,
+ "size": 1
+ },
+ "PCPOL": {
+ "description": "Pixel Clock Polarity",
+ "offset": 28,
+ "size": 1
+ },
+ "DEN": {
+ "description": "Dither Enable",
+ "offset": 16,
+ "size": 1
+ },
+ "DRW": {
+ "description": "Dither Red Width",
+ "offset": 12,
+ "size": 3,
+ "access": "read-only"
+ },
+ "DGW": {
+ "description": "Dither Green Width",
+ "offset": 8,
+ "size": 3,
+ "access": "read-only"
+ },
+ "DBW": {
+ "description": "Dither Blue Width",
+ "offset": 4,
+ "size": 3,
+ "access": "read-only"
+ },
+ "LTDCEN": {
+ "description": "LCD-TFT controller enable\n bit",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SRCR": {
+ "description": "Shadow Reload Configuration\n Register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "VBR": {
+ "description": "Vertical Blanking Reload",
+ "offset": 1,
+ "size": 1
+ },
+ "IMR": {
+ "description": "Immediate Reload",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "BCCR": {
+ "description": "Background Color Configuration\n Register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BC": {
+ "description": "Background Color Red value",
+ "offset": 0,
+ "size": 24
+ }
+ }
+ }
+ },
+ "IER": {
+ "description": "Interrupt Enable Register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RRIE": {
+ "description": "Register Reload interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "TERRIE": {
+ "description": "Transfer Error Interrupt\n Enable",
+ "offset": 2,
+ "size": 1
+ },
+ "FUIE": {
+ "description": "FIFO Underrun Interrupt\n Enable",
+ "offset": 1,
+ "size": 1
+ },
+ "LIE": {
+ "description": "Line Interrupt Enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ISR": {
+ "description": "Interrupt Status Register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "RRIF": {
+ "description": "Register Reload Interrupt\n Flag",
+ "offset": 3,
+ "size": 1
+ },
+ "TERRIF": {
+ "description": "Transfer Error interrupt\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "FUIF": {
+ "description": "FIFO Underrun Interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "LIF": {
+ "description": "Line Interrupt flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ICR": {
+ "description": "Interrupt Clear Register",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "CRRIF": {
+ "description": "Clears Register Reload Interrupt\n Flag",
+ "offset": 3,
+ "size": 1
+ },
+ "CTERRIF": {
+ "description": "Clears the Transfer Error Interrupt\n Flag",
+ "offset": 2,
+ "size": 1
+ },
+ "CFUIF": {
+ "description": "Clears the FIFO Underrun Interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "CLIF": {
+ "description": "Clears the Line Interrupt\n Flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "LIPCR": {
+ "description": "Line Interrupt Position Configuration\n Register",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LIPOS": {
+ "description": "Line Interrupt Position",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "CPSR": {
+ "description": "Current Position Status\n Register",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CXPOS": {
+ "description": "Current X Position",
+ "offset": 16,
+ "size": 16
+ },
+ "CYPOS": {
+ "description": "Current Y Position",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CDSR": {
+ "description": "Current Display Status\n Register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 15,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "HSYNCS": {
+ "description": "Horizontal Synchronization display\n Status",
+ "offset": 3,
+ "size": 1
+ },
+ "VSYNCS": {
+ "description": "Vertical Synchronization display\n Status",
+ "offset": 2,
+ "size": 1
+ },
+ "HDES": {
+ "description": "Horizontal Data Enable display\n Status",
+ "offset": 1,
+ "size": 1
+ },
+ "VDES": {
+ "description": "Vertical Data Enable display\n Status",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "L1CR": {
+ "description": "Layerx Control Register",
+ "offset": 132,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CLUTEN": {
+ "description": "Color Look-Up Table Enable",
+ "offset": 4,
+ "size": 1
+ },
+ "COLKEN": {
+ "description": "Color Keying Enable",
+ "offset": 1,
+ "size": 1
+ },
+ "LEN": {
+ "description": "Layer Enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "L1WHPCR": {
+ "description": "Layerx Window Horizontal Position\n Configuration Register",
+ "offset": 136,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "WHSPPOS": {
+ "description": "Window Horizontal Stop\n Position",
+ "offset": 16,
+ "size": 12
+ },
+ "WHSTPOS": {
+ "description": "Window Horizontal Start\n Position",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "L1WVPCR": {
+ "description": "Layerx Window Vertical Position\n Configuration Register",
+ "offset": 140,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "WVSPPOS": {
+ "description": "Window Vertical Stop\n Position",
+ "offset": 16,
+ "size": 11
+ },
+ "WVSTPOS": {
+ "description": "Window Vertical Start\n Position",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "L1CKCR": {
+ "description": "Layerx Color Keying Configuration\n Register",
+ "offset": 144,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CKRED": {
+ "description": "Color Key Red value",
+ "offset": 16,
+ "size": 8
+ },
+ "CKGREEN": {
+ "description": "Color Key Green value",
+ "offset": 8,
+ "size": 8
+ },
+ "CKBLUE": {
+ "description": "Color Key Blue value",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "L1PFCR": {
+ "description": "Layerx Pixel Format Configuration\n Register",
+ "offset": 148,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PF": {
+ "description": "Pixel Format",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "L1CACR": {
+ "description": "Layerx Constant Alpha Configuration\n Register",
+ "offset": 152,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CONSTA": {
+ "description": "Constant Alpha",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "L1DCCR": {
+ "description": "Layerx Default Color Configuration\n Register",
+ "offset": 156,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DCALPHA": {
+ "description": "Default Color Alpha",
+ "offset": 24,
+ "size": 8
+ },
+ "DCRED": {
+ "description": "Default Color Red",
+ "offset": 16,
+ "size": 8
+ },
+ "DCGREEN": {
+ "description": "Default Color Green",
+ "offset": 8,
+ "size": 8
+ },
+ "DCBLUE": {
+ "description": "Default Color Blue",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "L1BFCR": {
+ "description": "Layerx Blending Factors Configuration\n Register",
+ "offset": 160,
+ "size": 32,
+ "reset_value": 1543,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BF1": {
+ "description": "Blending Factor 1",
+ "offset": 8,
+ "size": 3
+ },
+ "BF2": {
+ "description": "Blending Factor 2",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "L1CFBAR": {
+ "description": "Layerx Color Frame Buffer Address\n Register",
+ "offset": 172,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CFBADD": {
+ "description": "Color Frame Buffer Start\n Address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "L1CFBLR": {
+ "description": "Layerx Color Frame Buffer Length\n Register",
+ "offset": 176,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CFBP": {
+ "description": "Color Frame Buffer Pitch in\n bytes",
+ "offset": 16,
+ "size": 13
+ },
+ "CFBLL": {
+ "description": "Color Frame Buffer Line\n Length",
+ "offset": 0,
+ "size": 13
+ }
+ }
+ }
+ },
+ "L1CFBLNR": {
+ "description": "Layerx ColorFrame Buffer Line Number\n Register",
+ "offset": 180,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CFBLNBR": {
+ "description": "Frame Buffer Line Number",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "L1CLUTWR": {
+ "description": "Layerx CLUT Write Register",
+ "offset": 196,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "CLUTADD": {
+ "description": "CLUT Address",
+ "offset": 24,
+ "size": 8
+ },
+ "RED": {
+ "description": "Red value",
+ "offset": 16,
+ "size": 8
+ },
+ "GREEN": {
+ "description": "Green value",
+ "offset": 8,
+ "size": 8
+ },
+ "BLUE": {
+ "description": "Blue value",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "L2CR": {
+ "description": "Layerx Control Register",
+ "offset": 260,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CLUTEN": {
+ "description": "Color Look-Up Table Enable",
+ "offset": 4,
+ "size": 1
+ },
+ "COLKEN": {
+ "description": "Color Keying Enable",
+ "offset": 1,
+ "size": 1
+ },
+ "LEN": {
+ "description": "Layer Enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "L2WHPCR": {
+ "description": "Layerx Window Horizontal Position\n Configuration Register",
+ "offset": 264,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "WHSPPOS": {
+ "description": "Window Horizontal Stop\n Position",
+ "offset": 16,
+ "size": 12
+ },
+ "WHSTPOS": {
+ "description": "Window Horizontal Start\n Position",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "L2WVPCR": {
+ "description": "Layerx Window Vertical Position\n Configuration Register",
+ "offset": 268,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "WVSPPOS": {
+ "description": "Window Vertical Stop\n Position",
+ "offset": 16,
+ "size": 11
+ },
+ "WVSTPOS": {
+ "description": "Window Vertical Start\n Position",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "L2CKCR": {
+ "description": "Layerx Color Keying Configuration\n Register",
+ "offset": 272,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CKRED": {
+ "description": "Color Key Red value",
+ "offset": 15,
+ "size": 9
+ },
+ "CKGREEN": {
+ "description": "Color Key Green value",
+ "offset": 8,
+ "size": 7
+ },
+ "CKBLUE": {
+ "description": "Color Key Blue value",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "L2PFCR": {
+ "description": "Layerx Pixel Format Configuration\n Register",
+ "offset": 276,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PF": {
+ "description": "Pixel Format",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "L2CACR": {
+ "description": "Layerx Constant Alpha Configuration\n Register",
+ "offset": 280,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CONSTA": {
+ "description": "Constant Alpha",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "L2DCCR": {
+ "description": "Layerx Default Color Configuration\n Register",
+ "offset": 284,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DCALPHA": {
+ "description": "Default Color Alpha",
+ "offset": 24,
+ "size": 8
+ },
+ "DCRED": {
+ "description": "Default Color Red",
+ "offset": 16,
+ "size": 8
+ },
+ "DCGREEN": {
+ "description": "Default Color Green",
+ "offset": 8,
+ "size": 8
+ },
+ "DCBLUE": {
+ "description": "Default Color Blue",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "L2BFCR": {
+ "description": "Layerx Blending Factors Configuration\n Register",
+ "offset": 288,
+ "size": 32,
+ "reset_value": 1543,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BF1": {
+ "description": "Blending Factor 1",
+ "offset": 8,
+ "size": 3
+ },
+ "BF2": {
+ "description": "Blending Factor 2",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "L2CFBAR": {
+ "description": "Layerx Color Frame Buffer Address\n Register",
+ "offset": 300,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CFBADD": {
+ "description": "Color Frame Buffer Start\n Address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "L2CFBLR": {
+ "description": "Layerx Color Frame Buffer Length\n Register",
+ "offset": 304,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CFBP": {
+ "description": "Color Frame Buffer Pitch in\n bytes",
+ "offset": 16,
+ "size": 13
+ },
+ "CFBLL": {
+ "description": "Color Frame Buffer Line\n Length",
+ "offset": 0,
+ "size": 13
+ }
+ }
+ }
+ },
+ "L2CFBLNR": {
+ "description": "Layerx ColorFrame Buffer Line Number\n Register",
+ "offset": 308,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CFBLNBR": {
+ "description": "Frame Buffer Line Number",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "L2CLUTWR": {
+ "description": "Layerx CLUT Write Register",
+ "offset": 324,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "CLUTADD": {
+ "description": "CLUT Address",
+ "offset": 24,
+ "size": 8
+ },
+ "RED": {
+ "description": "Red value",
+ "offset": 16,
+ "size": 8
+ },
+ "GREEN": {
+ "description": "Green value",
+ "offset": 8,
+ "size": 8
+ },
+ "BLUE": {
+ "description": "Blue value",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "OTG_HS_PWRCLK": {
+ "description": "USB on the go high speed",
+ "children": {
+ "registers": {
+ "OTG_HS_PCGCR": {
+ "description": "Power and clock gating control\n register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "STPPCLK": {
+ "description": "Stop PHY clock",
+ "offset": 0,
+ "size": 1
+ },
+ "GATEHCLK": {
+ "description": "Gate HCLK",
+ "offset": 1,
+ "size": 1
+ },
+ "PHYSUSP": {
+ "description": "PHY suspended",
+ "offset": 4,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "OTG_HS_DEVICE": {
+ "description": "USB on the go high speed",
+ "children": {
+ "registers": {
+ "OTG_HS_DCFG": {
+ "description": "OTG_HS device configuration\n register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 35651584,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DSPD": {
+ "description": "Device speed",
+ "offset": 0,
+ "size": 2
+ },
+ "NZLSOHSK": {
+ "description": "Nonzero-length status OUT\n handshake",
+ "offset": 2,
+ "size": 1
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 4,
+ "size": 7
+ },
+ "PFIVL": {
+ "description": "Periodic (micro)frame\n interval",
+ "offset": 11,
+ "size": 2
+ },
+ "PERSCHIVL": {
+ "description": "Periodic scheduling\n interval",
+ "offset": 24,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_DCTL": {
+ "description": "OTG_HS device control register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RWUSIG": {
+ "description": "Remote wakeup signaling",
+ "offset": 0,
+ "size": 1
+ },
+ "SDIS": {
+ "description": "Soft disconnect",
+ "offset": 1,
+ "size": 1
+ },
+ "GINSTS": {
+ "description": "Global IN NAK status",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "GONSTS": {
+ "description": "Global OUT NAK status",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TCTL": {
+ "description": "Test control",
+ "offset": 4,
+ "size": 3
+ },
+ "SGINAK": {
+ "description": "Set global IN NAK",
+ "offset": 7,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CGINAK": {
+ "description": "Clear global IN NAK",
+ "offset": 8,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SGONAK": {
+ "description": "Set global OUT NAK",
+ "offset": 9,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CGONAK": {
+ "description": "Clear global OUT NAK",
+ "offset": 10,
+ "size": 1,
+ "access": "write-only"
+ },
+ "POPRGDNE": {
+ "description": "Power-on programming done",
+ "offset": 11,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DSTS": {
+ "description": "OTG_HS device status register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 16,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "SUSPSTS": {
+ "description": "Suspend status",
+ "offset": 0,
+ "size": 1
+ },
+ "ENUMSPD": {
+ "description": "Enumerated speed",
+ "offset": 1,
+ "size": 2
+ },
+ "EERR": {
+ "description": "Erratic error",
+ "offset": 3,
+ "size": 1
+ },
+ "FNSOF": {
+ "description": "Frame number of the received\n SOF",
+ "offset": 8,
+ "size": 14
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPMSK": {
+ "description": "OTG_HS device IN endpoint common interrupt\n mask register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed interrupt\n mask",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDM": {
+ "description": "Endpoint disabled interrupt\n mask",
+ "offset": 1,
+ "size": 1
+ },
+ "TOM": {
+ "description": "Timeout condition mask (nonisochronous\n endpoints)",
+ "offset": 3,
+ "size": 1
+ },
+ "ITTXFEMSK": {
+ "description": "IN token received when TxFIFO empty\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "INEPNMM": {
+ "description": "IN token received with EP mismatch\n mask",
+ "offset": 5,
+ "size": 1
+ },
+ "INEPNEM": {
+ "description": "IN endpoint NAK effective\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXFURM": {
+ "description": "FIFO underrun mask",
+ "offset": 8,
+ "size": 1
+ },
+ "BIM": {
+ "description": "BNA interrupt mask",
+ "offset": 9,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPMSK": {
+ "description": "OTG_HS device OUT endpoint common interrupt\n mask register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed interrupt\n mask",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDM": {
+ "description": "Endpoint disabled interrupt\n mask",
+ "offset": 1,
+ "size": 1
+ },
+ "STUPM": {
+ "description": "SETUP phase done mask",
+ "offset": 3,
+ "size": 1
+ },
+ "OTEPDM": {
+ "description": "OUT token received when endpoint\n disabled mask",
+ "offset": 4,
+ "size": 1
+ },
+ "B2BSTUP": {
+ "description": "Back-to-back SETUP packets received\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "OPEM": {
+ "description": "OUT packet error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "BOIM": {
+ "description": "BNA interrupt mask",
+ "offset": 9,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DAINT": {
+ "description": "OTG_HS device all endpoints interrupt\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "IEPINT": {
+ "description": "IN endpoint interrupt bits",
+ "offset": 0,
+ "size": 16
+ },
+ "OEPINT": {
+ "description": "OUT endpoint interrupt\n bits",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DAINTMSK": {
+ "description": "OTG_HS all endpoints interrupt mask\n register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IEPM": {
+ "description": "IN EP interrupt mask bits",
+ "offset": 0,
+ "size": 16
+ },
+ "OEPM": {
+ "description": "OUT EP interrupt mask bits",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DVBUSDIS": {
+ "description": "OTG_HS device VBUS discharge time\n register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 6103,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "VBUSDT": {
+ "description": "Device VBUS discharge time",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DVBUSPULSE": {
+ "description": "OTG_HS device VBUS pulsing time\n register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 1464,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DVBUSP": {
+ "description": "Device VBUS pulsing time",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "OTG_HS_DTHRCTL": {
+ "description": "OTG_HS Device threshold control\n register",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NONISOTHREN": {
+ "description": "Nonisochronous IN endpoints threshold\n enable",
+ "offset": 0,
+ "size": 1
+ },
+ "ISOTHREN": {
+ "description": "ISO IN endpoint threshold\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "TXTHRLEN": {
+ "description": "Transmit threshold length",
+ "offset": 2,
+ "size": 9
+ },
+ "RXTHREN": {
+ "description": "Receive threshold enable",
+ "offset": 16,
+ "size": 1
+ },
+ "RXTHRLEN": {
+ "description": "Receive threshold length",
+ "offset": 17,
+ "size": 9
+ },
+ "ARPEN": {
+ "description": "Arbiter parking enable",
+ "offset": 27,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPEMPMSK": {
+ "description": "OTG_HS device IN endpoint FIFO empty\n interrupt mask register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INEPTXFEM": {
+ "description": "IN EP Tx FIFO empty interrupt mask\n bits",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DEACHINT": {
+ "description": "OTG_HS device each endpoint interrupt\n register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IEP1INT": {
+ "description": "IN endpoint 1interrupt bit",
+ "offset": 1,
+ "size": 1
+ },
+ "OEP1INT": {
+ "description": "OUT endpoint 1 interrupt\n bit",
+ "offset": 17,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DEACHINTMSK": {
+ "description": "OTG_HS device each endpoint interrupt\n register mask",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IEP1INTM": {
+ "description": "IN Endpoint 1 interrupt mask\n bit",
+ "offset": 1,
+ "size": 1
+ },
+ "OEP1INTM": {
+ "description": "OUT Endpoint 1 interrupt mask\n bit",
+ "offset": 17,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPEACHMSK1": {
+ "description": "OTG_HS device each in endpoint-1 interrupt\n register",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed interrupt\n mask",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDM": {
+ "description": "Endpoint disabled interrupt\n mask",
+ "offset": 1,
+ "size": 1
+ },
+ "TOM": {
+ "description": "Timeout condition mask (nonisochronous\n endpoints)",
+ "offset": 3,
+ "size": 1
+ },
+ "ITTXFEMSK": {
+ "description": "IN token received when TxFIFO empty\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "INEPNMM": {
+ "description": "IN token received with EP mismatch\n mask",
+ "offset": 5,
+ "size": 1
+ },
+ "INEPNEM": {
+ "description": "IN endpoint NAK effective\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXFURM": {
+ "description": "FIFO underrun mask",
+ "offset": 8,
+ "size": 1
+ },
+ "BIM": {
+ "description": "BNA interrupt mask",
+ "offset": 9,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK interrupt mask",
+ "offset": 13,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPEACHMSK1": {
+ "description": "OTG_HS device each OUT endpoint-1 interrupt\n register",
+ "offset": 128,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed interrupt\n mask",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDM": {
+ "description": "Endpoint disabled interrupt\n mask",
+ "offset": 1,
+ "size": 1
+ },
+ "TOM": {
+ "description": "Timeout condition mask",
+ "offset": 3,
+ "size": 1
+ },
+ "ITTXFEMSK": {
+ "description": "IN token received when TxFIFO empty\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "INEPNMM": {
+ "description": "IN token received with EP mismatch\n mask",
+ "offset": 5,
+ "size": 1
+ },
+ "INEPNEM": {
+ "description": "IN endpoint NAK effective\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXFURM": {
+ "description": "OUT packet error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "BIM": {
+ "description": "BNA interrupt mask",
+ "offset": 9,
+ "size": 1
+ },
+ "BERRM": {
+ "description": "Bubble error interrupt\n mask",
+ "offset": 12,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK interrupt mask",
+ "offset": 13,
+ "size": 1
+ },
+ "NYETM": {
+ "description": "NYET interrupt mask",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPCTL0": {
+ "description": "OTG device endpoint-0 control\n register",
+ "offset": 256,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "USBAEP": {
+ "description": "USB active endpoint",
+ "offset": 15,
+ "size": 1
+ },
+ "EONUM_DPID": {
+ "description": "Even/odd frame",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAK status",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "Stall": {
+ "description": "STALL handshake",
+ "offset": 21,
+ "size": 1
+ },
+ "TXFNUM": {
+ "description": "TxFIFO number",
+ "offset": 22,
+ "size": 4
+ },
+ "CNAK": {
+ "description": "Clear NAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "Set NAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "Set DATA0 PID",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SODDFRM": {
+ "description": "Set odd frame",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "Endpoint disable",
+ "offset": 30,
+ "size": 1
+ },
+ "EPENA": {
+ "description": "Endpoint enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPCTL1": {
+ "description": "OTG device endpoint-1 control\n register",
+ "offset": 288,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "USBAEP": {
+ "description": "USB active endpoint",
+ "offset": 15,
+ "size": 1
+ },
+ "EONUM_DPID": {
+ "description": "Even/odd frame",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAK status",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "Stall": {
+ "description": "STALL handshake",
+ "offset": 21,
+ "size": 1
+ },
+ "TXFNUM": {
+ "description": "TxFIFO number",
+ "offset": 22,
+ "size": 4
+ },
+ "CNAK": {
+ "description": "Clear NAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "Set NAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "Set DATA0 PID",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SODDFRM": {
+ "description": "Set odd frame",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "Endpoint disable",
+ "offset": 30,
+ "size": 1
+ },
+ "EPENA": {
+ "description": "Endpoint enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPCTL2": {
+ "description": "OTG device endpoint-2 control\n register",
+ "offset": 320,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "USBAEP": {
+ "description": "USB active endpoint",
+ "offset": 15,
+ "size": 1
+ },
+ "EONUM_DPID": {
+ "description": "Even/odd frame",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAK status",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "Stall": {
+ "description": "STALL handshake",
+ "offset": 21,
+ "size": 1
+ },
+ "TXFNUM": {
+ "description": "TxFIFO number",
+ "offset": 22,
+ "size": 4
+ },
+ "CNAK": {
+ "description": "Clear NAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "Set NAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "Set DATA0 PID",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SODDFRM": {
+ "description": "Set odd frame",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "Endpoint disable",
+ "offset": 30,
+ "size": 1
+ },
+ "EPENA": {
+ "description": "Endpoint enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPCTL3": {
+ "description": "OTG device endpoint-3 control\n register",
+ "offset": 352,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "USBAEP": {
+ "description": "USB active endpoint",
+ "offset": 15,
+ "size": 1
+ },
+ "EONUM_DPID": {
+ "description": "Even/odd frame",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAK status",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "Stall": {
+ "description": "STALL handshake",
+ "offset": 21,
+ "size": 1
+ },
+ "TXFNUM": {
+ "description": "TxFIFO number",
+ "offset": 22,
+ "size": 4
+ },
+ "CNAK": {
+ "description": "Clear NAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "Set NAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "Set DATA0 PID",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SODDFRM": {
+ "description": "Set odd frame",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "Endpoint disable",
+ "offset": 30,
+ "size": 1
+ },
+ "EPENA": {
+ "description": "Endpoint enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPCTL4": {
+ "description": "OTG device endpoint-4 control\n register",
+ "offset": 384,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "USBAEP": {
+ "description": "USB active endpoint",
+ "offset": 15,
+ "size": 1
+ },
+ "EONUM_DPID": {
+ "description": "Even/odd frame",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAK status",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "Stall": {
+ "description": "STALL handshake",
+ "offset": 21,
+ "size": 1
+ },
+ "TXFNUM": {
+ "description": "TxFIFO number",
+ "offset": 22,
+ "size": 4
+ },
+ "CNAK": {
+ "description": "Clear NAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "Set NAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "Set DATA0 PID",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SODDFRM": {
+ "description": "Set odd frame",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "Endpoint disable",
+ "offset": 30,
+ "size": 1
+ },
+ "EPENA": {
+ "description": "Endpoint enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPCTL5": {
+ "description": "OTG device endpoint-5 control\n register",
+ "offset": 416,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "USBAEP": {
+ "description": "USB active endpoint",
+ "offset": 15,
+ "size": 1
+ },
+ "EONUM_DPID": {
+ "description": "Even/odd frame",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAK status",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "Stall": {
+ "description": "STALL handshake",
+ "offset": 21,
+ "size": 1
+ },
+ "TXFNUM": {
+ "description": "TxFIFO number",
+ "offset": 22,
+ "size": 4
+ },
+ "CNAK": {
+ "description": "Clear NAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "Set NAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "Set DATA0 PID",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SODDFRM": {
+ "description": "Set odd frame",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "Endpoint disable",
+ "offset": 30,
+ "size": 1
+ },
+ "EPENA": {
+ "description": "Endpoint enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPCTL6": {
+ "description": "OTG device endpoint-6 control\n register",
+ "offset": 448,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "USBAEP": {
+ "description": "USB active endpoint",
+ "offset": 15,
+ "size": 1
+ },
+ "EONUM_DPID": {
+ "description": "Even/odd frame",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAK status",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "Stall": {
+ "description": "STALL handshake",
+ "offset": 21,
+ "size": 1
+ },
+ "TXFNUM": {
+ "description": "TxFIFO number",
+ "offset": 22,
+ "size": 4
+ },
+ "CNAK": {
+ "description": "Clear NAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "Set NAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "Set DATA0 PID",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SODDFRM": {
+ "description": "Set odd frame",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "Endpoint disable",
+ "offset": 30,
+ "size": 1
+ },
+ "EPENA": {
+ "description": "Endpoint enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPCTL7": {
+ "description": "OTG device endpoint-7 control\n register",
+ "offset": 480,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "USBAEP": {
+ "description": "USB active endpoint",
+ "offset": 15,
+ "size": 1
+ },
+ "EONUM_DPID": {
+ "description": "Even/odd frame",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAK status",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "Stall": {
+ "description": "STALL handshake",
+ "offset": 21,
+ "size": 1
+ },
+ "TXFNUM": {
+ "description": "TxFIFO number",
+ "offset": 22,
+ "size": 4
+ },
+ "CNAK": {
+ "description": "Clear NAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "Set NAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "Set DATA0 PID",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SODDFRM": {
+ "description": "Set odd frame",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "Endpoint disable",
+ "offset": 30,
+ "size": 1
+ },
+ "EPENA": {
+ "description": "Endpoint enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPINT0": {
+ "description": "OTG device endpoint-0 interrupt\n register",
+ "offset": 264,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "TOC": {
+ "description": "Timeout condition",
+ "offset": 3,
+ "size": 1
+ },
+ "ITTXFE": {
+ "description": "IN token received when TxFIFO is\n empty",
+ "offset": 4,
+ "size": 1
+ },
+ "INEPNE": {
+ "description": "IN endpoint NAK effective",
+ "offset": 6,
+ "size": 1
+ },
+ "TXFE": {
+ "description": "Transmit FIFO empty",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TXFIFOUDRN": {
+ "description": "Transmit Fifo Underrun",
+ "offset": 8,
+ "size": 1
+ },
+ "BNA": {
+ "description": "Buffer not available\n interrupt",
+ "offset": 9,
+ "size": 1
+ },
+ "PKTDRPSTS": {
+ "description": "Packet dropped status",
+ "offset": 11,
+ "size": 1
+ },
+ "BERR": {
+ "description": "Babble error interrupt",
+ "offset": 12,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK interrupt",
+ "offset": 13,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPINT1": {
+ "description": "OTG device endpoint-1 interrupt\n register",
+ "offset": 296,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "TOC": {
+ "description": "Timeout condition",
+ "offset": 3,
+ "size": 1
+ },
+ "ITTXFE": {
+ "description": "IN token received when TxFIFO is\n empty",
+ "offset": 4,
+ "size": 1
+ },
+ "INEPNE": {
+ "description": "IN endpoint NAK effective",
+ "offset": 6,
+ "size": 1
+ },
+ "TXFE": {
+ "description": "Transmit FIFO empty",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TXFIFOUDRN": {
+ "description": "Transmit Fifo Underrun",
+ "offset": 8,
+ "size": 1
+ },
+ "BNA": {
+ "description": "Buffer not available\n interrupt",
+ "offset": 9,
+ "size": 1
+ },
+ "PKTDRPSTS": {
+ "description": "Packet dropped status",
+ "offset": 11,
+ "size": 1
+ },
+ "BERR": {
+ "description": "Babble error interrupt",
+ "offset": 12,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK interrupt",
+ "offset": 13,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPINT2": {
+ "description": "OTG device endpoint-2 interrupt\n register",
+ "offset": 328,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "TOC": {
+ "description": "Timeout condition",
+ "offset": 3,
+ "size": 1
+ },
+ "ITTXFE": {
+ "description": "IN token received when TxFIFO is\n empty",
+ "offset": 4,
+ "size": 1
+ },
+ "INEPNE": {
+ "description": "IN endpoint NAK effective",
+ "offset": 6,
+ "size": 1
+ },
+ "TXFE": {
+ "description": "Transmit FIFO empty",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TXFIFOUDRN": {
+ "description": "Transmit Fifo Underrun",
+ "offset": 8,
+ "size": 1
+ },
+ "BNA": {
+ "description": "Buffer not available\n interrupt",
+ "offset": 9,
+ "size": 1
+ },
+ "PKTDRPSTS": {
+ "description": "Packet dropped status",
+ "offset": 11,
+ "size": 1
+ },
+ "BERR": {
+ "description": "Babble error interrupt",
+ "offset": 12,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK interrupt",
+ "offset": 13,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPINT3": {
+ "description": "OTG device endpoint-3 interrupt\n register",
+ "offset": 360,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "TOC": {
+ "description": "Timeout condition",
+ "offset": 3,
+ "size": 1
+ },
+ "ITTXFE": {
+ "description": "IN token received when TxFIFO is\n empty",
+ "offset": 4,
+ "size": 1
+ },
+ "INEPNE": {
+ "description": "IN endpoint NAK effective",
+ "offset": 6,
+ "size": 1
+ },
+ "TXFE": {
+ "description": "Transmit FIFO empty",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TXFIFOUDRN": {
+ "description": "Transmit Fifo Underrun",
+ "offset": 8,
+ "size": 1
+ },
+ "BNA": {
+ "description": "Buffer not available\n interrupt",
+ "offset": 9,
+ "size": 1
+ },
+ "PKTDRPSTS": {
+ "description": "Packet dropped status",
+ "offset": 11,
+ "size": 1
+ },
+ "BERR": {
+ "description": "Babble error interrupt",
+ "offset": 12,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK interrupt",
+ "offset": 13,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPINT4": {
+ "description": "OTG device endpoint-4 interrupt\n register",
+ "offset": 392,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "TOC": {
+ "description": "Timeout condition",
+ "offset": 3,
+ "size": 1
+ },
+ "ITTXFE": {
+ "description": "IN token received when TxFIFO is\n empty",
+ "offset": 4,
+ "size": 1
+ },
+ "INEPNE": {
+ "description": "IN endpoint NAK effective",
+ "offset": 6,
+ "size": 1
+ },
+ "TXFE": {
+ "description": "Transmit FIFO empty",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TXFIFOUDRN": {
+ "description": "Transmit Fifo Underrun",
+ "offset": 8,
+ "size": 1
+ },
+ "BNA": {
+ "description": "Buffer not available\n interrupt",
+ "offset": 9,
+ "size": 1
+ },
+ "PKTDRPSTS": {
+ "description": "Packet dropped status",
+ "offset": 11,
+ "size": 1
+ },
+ "BERR": {
+ "description": "Babble error interrupt",
+ "offset": 12,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK interrupt",
+ "offset": 13,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPINT5": {
+ "description": "OTG device endpoint-5 interrupt\n register",
+ "offset": 424,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "TOC": {
+ "description": "Timeout condition",
+ "offset": 3,
+ "size": 1
+ },
+ "ITTXFE": {
+ "description": "IN token received when TxFIFO is\n empty",
+ "offset": 4,
+ "size": 1
+ },
+ "INEPNE": {
+ "description": "IN endpoint NAK effective",
+ "offset": 6,
+ "size": 1
+ },
+ "TXFE": {
+ "description": "Transmit FIFO empty",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TXFIFOUDRN": {
+ "description": "Transmit Fifo Underrun",
+ "offset": 8,
+ "size": 1
+ },
+ "BNA": {
+ "description": "Buffer not available\n interrupt",
+ "offset": 9,
+ "size": 1
+ },
+ "PKTDRPSTS": {
+ "description": "Packet dropped status",
+ "offset": 11,
+ "size": 1
+ },
+ "BERR": {
+ "description": "Babble error interrupt",
+ "offset": 12,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK interrupt",
+ "offset": 13,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPINT6": {
+ "description": "OTG device endpoint-6 interrupt\n register",
+ "offset": 456,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "TOC": {
+ "description": "Timeout condition",
+ "offset": 3,
+ "size": 1
+ },
+ "ITTXFE": {
+ "description": "IN token received when TxFIFO is\n empty",
+ "offset": 4,
+ "size": 1
+ },
+ "INEPNE": {
+ "description": "IN endpoint NAK effective",
+ "offset": 6,
+ "size": 1
+ },
+ "TXFE": {
+ "description": "Transmit FIFO empty",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TXFIFOUDRN": {
+ "description": "Transmit Fifo Underrun",
+ "offset": 8,
+ "size": 1
+ },
+ "BNA": {
+ "description": "Buffer not available\n interrupt",
+ "offset": 9,
+ "size": 1
+ },
+ "PKTDRPSTS": {
+ "description": "Packet dropped status",
+ "offset": 11,
+ "size": 1
+ },
+ "BERR": {
+ "description": "Babble error interrupt",
+ "offset": 12,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK interrupt",
+ "offset": 13,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPINT7": {
+ "description": "OTG device endpoint-7 interrupt\n register",
+ "offset": 488,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "TOC": {
+ "description": "Timeout condition",
+ "offset": 3,
+ "size": 1
+ },
+ "ITTXFE": {
+ "description": "IN token received when TxFIFO is\n empty",
+ "offset": 4,
+ "size": 1
+ },
+ "INEPNE": {
+ "description": "IN endpoint NAK effective",
+ "offset": 6,
+ "size": 1
+ },
+ "TXFE": {
+ "description": "Transmit FIFO empty",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TXFIFOUDRN": {
+ "description": "Transmit Fifo Underrun",
+ "offset": 8,
+ "size": 1
+ },
+ "BNA": {
+ "description": "Buffer not available\n interrupt",
+ "offset": 9,
+ "size": 1
+ },
+ "PKTDRPSTS": {
+ "description": "Packet dropped status",
+ "offset": 11,
+ "size": 1
+ },
+ "BERR": {
+ "description": "Babble error interrupt",
+ "offset": 12,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK interrupt",
+ "offset": 13,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPTSIZ0": {
+ "description": "OTG_HS device IN endpoint 0 transfer size\n register",
+ "offset": 272,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 7
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPDMA1": {
+ "description": "OTG_HS device endpoint-1 DMA address\n register",
+ "offset": 276,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPDMA2": {
+ "description": "OTG_HS device endpoint-2 DMA address\n register",
+ "offset": 308,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPDMA3": {
+ "description": "OTG_HS device endpoint-3 DMA address\n register",
+ "offset": 340,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPDMA4": {
+ "description": "OTG_HS device endpoint-4 DMA address\n register",
+ "offset": 372,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPDMA5": {
+ "description": "OTG_HS device endpoint-5 DMA address\n register",
+ "offset": 404,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_DTXFSTS0": {
+ "description": "OTG_HS device IN endpoint transmit FIFO\n status register",
+ "offset": 280,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "INEPTFSAV": {
+ "description": "IN endpoint TxFIFO space\n avail",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DTXFSTS1": {
+ "description": "OTG_HS device IN endpoint transmit FIFO\n status register",
+ "offset": 312,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "INEPTFSAV": {
+ "description": "IN endpoint TxFIFO space\n avail",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DTXFSTS2": {
+ "description": "OTG_HS device IN endpoint transmit FIFO\n status register",
+ "offset": 344,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "INEPTFSAV": {
+ "description": "IN endpoint TxFIFO space\n avail",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DTXFSTS3": {
+ "description": "OTG_HS device IN endpoint transmit FIFO\n status register",
+ "offset": 376,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "INEPTFSAV": {
+ "description": "IN endpoint TxFIFO space\n avail",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DTXFSTS4": {
+ "description": "OTG_HS device IN endpoint transmit FIFO\n status register",
+ "offset": 408,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "INEPTFSAV": {
+ "description": "IN endpoint TxFIFO space\n avail",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DTXFSTS5": {
+ "description": "OTG_HS device IN endpoint transmit FIFO\n status register",
+ "offset": 440,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "INEPTFSAV": {
+ "description": "IN endpoint TxFIFO space\n avail",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPTSIZ1": {
+ "description": "OTG_HS device endpoint transfer size\n register",
+ "offset": 304,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "MCNT": {
+ "description": "Multi count",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPTSIZ2": {
+ "description": "OTG_HS device endpoint transfer size\n register",
+ "offset": 336,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "MCNT": {
+ "description": "Multi count",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPTSIZ3": {
+ "description": "OTG_HS device endpoint transfer size\n register",
+ "offset": 368,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "MCNT": {
+ "description": "Multi count",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPTSIZ4": {
+ "description": "OTG_HS device endpoint transfer size\n register",
+ "offset": 400,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "MCNT": {
+ "description": "Multi count",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPTSIZ5": {
+ "description": "OTG_HS device endpoint transfer size\n register",
+ "offset": 432,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "MCNT": {
+ "description": "Multi count",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPCTL0": {
+ "description": "OTG_HS device control OUT endpoint 0 control\n register",
+ "offset": 768,
+ "size": 32,
+ "reset_value": 32768,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 2,
+ "access": "read-only"
+ },
+ "USBAEP": {
+ "description": "USB active endpoint",
+ "offset": 15,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAK status",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2,
+ "access": "read-only"
+ },
+ "SNPM": {
+ "description": "Snoop mode",
+ "offset": 20,
+ "size": 1
+ },
+ "Stall": {
+ "description": "STALL handshake",
+ "offset": 21,
+ "size": 1
+ },
+ "CNAK": {
+ "description": "Clear NAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "Set NAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "Endpoint disable",
+ "offset": 30,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPENA": {
+ "description": "Endpoint enable",
+ "offset": 31,
+ "size": 1,
+ "access": "write-only"
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPCTL1": {
+ "description": "OTG device endpoint-1 control\n register",
+ "offset": 800,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "USBAEP": {
+ "description": "USB active endpoint",
+ "offset": 15,
+ "size": 1
+ },
+ "EONUM_DPID": {
+ "description": "Even odd frame/Endpoint data\n PID",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAK status",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "SNPM": {
+ "description": "Snoop mode",
+ "offset": 20,
+ "size": 1
+ },
+ "Stall": {
+ "description": "STALL handshake",
+ "offset": 21,
+ "size": 1
+ },
+ "CNAK": {
+ "description": "Clear NAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "Set NAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "Set DATA0 PID/Set even\n frame",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SODDFRM": {
+ "description": "Set odd frame",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "Endpoint disable",
+ "offset": 30,
+ "size": 1
+ },
+ "EPENA": {
+ "description": "Endpoint enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPCTL2": {
+ "description": "OTG device endpoint-2 control\n register",
+ "offset": 832,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "USBAEP": {
+ "description": "USB active endpoint",
+ "offset": 15,
+ "size": 1
+ },
+ "EONUM_DPID": {
+ "description": "Even odd frame/Endpoint data\n PID",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAK status",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "SNPM": {
+ "description": "Snoop mode",
+ "offset": 20,
+ "size": 1
+ },
+ "Stall": {
+ "description": "STALL handshake",
+ "offset": 21,
+ "size": 1
+ },
+ "CNAK": {
+ "description": "Clear NAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "Set NAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "Set DATA0 PID/Set even\n frame",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SODDFRM": {
+ "description": "Set odd frame",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "Endpoint disable",
+ "offset": 30,
+ "size": 1
+ },
+ "EPENA": {
+ "description": "Endpoint enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPCTL3": {
+ "description": "OTG device endpoint-3 control\n register",
+ "offset": 864,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "USBAEP": {
+ "description": "USB active endpoint",
+ "offset": 15,
+ "size": 1
+ },
+ "EONUM_DPID": {
+ "description": "Even odd frame/Endpoint data\n PID",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAK status",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "SNPM": {
+ "description": "Snoop mode",
+ "offset": 20,
+ "size": 1
+ },
+ "Stall": {
+ "description": "STALL handshake",
+ "offset": 21,
+ "size": 1
+ },
+ "CNAK": {
+ "description": "Clear NAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "Set NAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "Set DATA0 PID/Set even\n frame",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SODDFRM": {
+ "description": "Set odd frame",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "Endpoint disable",
+ "offset": 30,
+ "size": 1
+ },
+ "EPENA": {
+ "description": "Endpoint enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPINT0": {
+ "description": "OTG_HS device endpoint-0 interrupt\n register",
+ "offset": 776,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "STUP": {
+ "description": "SETUP phase done",
+ "offset": 3,
+ "size": 1
+ },
+ "OTEPDIS": {
+ "description": "OUT token received when endpoint\n disabled",
+ "offset": 4,
+ "size": 1
+ },
+ "B2BSTUP": {
+ "description": "Back-to-back SETUP packets\n received",
+ "offset": 6,
+ "size": 1
+ },
+ "NYET": {
+ "description": "NYET interrupt",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPINT1": {
+ "description": "OTG_HS device endpoint-1 interrupt\n register",
+ "offset": 808,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "STUP": {
+ "description": "SETUP phase done",
+ "offset": 3,
+ "size": 1
+ },
+ "OTEPDIS": {
+ "description": "OUT token received when endpoint\n disabled",
+ "offset": 4,
+ "size": 1
+ },
+ "B2BSTUP": {
+ "description": "Back-to-back SETUP packets\n received",
+ "offset": 6,
+ "size": 1
+ },
+ "NYET": {
+ "description": "NYET interrupt",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPINT2": {
+ "description": "OTG_HS device endpoint-2 interrupt\n register",
+ "offset": 840,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "STUP": {
+ "description": "SETUP phase done",
+ "offset": 3,
+ "size": 1
+ },
+ "OTEPDIS": {
+ "description": "OUT token received when endpoint\n disabled",
+ "offset": 4,
+ "size": 1
+ },
+ "B2BSTUP": {
+ "description": "Back-to-back SETUP packets\n received",
+ "offset": 6,
+ "size": 1
+ },
+ "NYET": {
+ "description": "NYET interrupt",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPINT3": {
+ "description": "OTG_HS device endpoint-3 interrupt\n register",
+ "offset": 872,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "STUP": {
+ "description": "SETUP phase done",
+ "offset": 3,
+ "size": 1
+ },
+ "OTEPDIS": {
+ "description": "OUT token received when endpoint\n disabled",
+ "offset": 4,
+ "size": 1
+ },
+ "B2BSTUP": {
+ "description": "Back-to-back SETUP packets\n received",
+ "offset": 6,
+ "size": 1
+ },
+ "NYET": {
+ "description": "NYET interrupt",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPINT4": {
+ "description": "OTG_HS device endpoint-4 interrupt\n register",
+ "offset": 904,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "STUP": {
+ "description": "SETUP phase done",
+ "offset": 3,
+ "size": 1
+ },
+ "OTEPDIS": {
+ "description": "OUT token received when endpoint\n disabled",
+ "offset": 4,
+ "size": 1
+ },
+ "B2BSTUP": {
+ "description": "Back-to-back SETUP packets\n received",
+ "offset": 6,
+ "size": 1
+ },
+ "NYET": {
+ "description": "NYET interrupt",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPINT5": {
+ "description": "OTG_HS device endpoint-5 interrupt\n register",
+ "offset": 936,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "STUP": {
+ "description": "SETUP phase done",
+ "offset": 3,
+ "size": 1
+ },
+ "OTEPDIS": {
+ "description": "OUT token received when endpoint\n disabled",
+ "offset": 4,
+ "size": 1
+ },
+ "B2BSTUP": {
+ "description": "Back-to-back SETUP packets\n received",
+ "offset": 6,
+ "size": 1
+ },
+ "NYET": {
+ "description": "NYET interrupt",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPINT6": {
+ "description": "OTG_HS device endpoint-6 interrupt\n register",
+ "offset": 968,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "STUP": {
+ "description": "SETUP phase done",
+ "offset": 3,
+ "size": 1
+ },
+ "OTEPDIS": {
+ "description": "OUT token received when endpoint\n disabled",
+ "offset": 4,
+ "size": 1
+ },
+ "B2BSTUP": {
+ "description": "Back-to-back SETUP packets\n received",
+ "offset": 6,
+ "size": 1
+ },
+ "NYET": {
+ "description": "NYET interrupt",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPINT7": {
+ "description": "OTG_HS device endpoint-7 interrupt\n register",
+ "offset": 1000,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed\n interrupt",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "Endpoint disabled\n interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "STUP": {
+ "description": "SETUP phase done",
+ "offset": 3,
+ "size": 1
+ },
+ "OTEPDIS": {
+ "description": "OUT token received when endpoint\n disabled",
+ "offset": 4,
+ "size": 1
+ },
+ "B2BSTUP": {
+ "description": "Back-to-back SETUP packets\n received",
+ "offset": 6,
+ "size": 1
+ },
+ "NYET": {
+ "description": "NYET interrupt",
+ "offset": 14,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPTSIZ0": {
+ "description": "OTG_HS device endpoint-1 transfer size\n register",
+ "offset": 784,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 7
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 1
+ },
+ "STUPCNT": {
+ "description": "SETUP packet count",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPTSIZ1": {
+ "description": "OTG_HS device endpoint-2 transfer size\n register",
+ "offset": 816,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "RXDPID_STUPCNT": {
+ "description": "Received data PID/SETUP packet\n count",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPTSIZ2": {
+ "description": "OTG_HS device endpoint-3 transfer size\n register",
+ "offset": 848,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "RXDPID_STUPCNT": {
+ "description": "Received data PID/SETUP packet\n count",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPTSIZ3": {
+ "description": "OTG_HS device endpoint-4 transfer size\n register",
+ "offset": 880,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "RXDPID_STUPCNT": {
+ "description": "Received data PID/SETUP packet\n count",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_DOEPTSIZ4": {
+ "description": "OTG_HS device endpoint-5 transfer size\n register",
+ "offset": 912,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "RXDPID_STUPCNT": {
+ "description": "Received data PID/SETUP packet\n count",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "OTG_HS_HOST": {
+ "description": "USB on the go high speed",
+ "children": {
+ "registers": {
+ "OTG_HS_HCFG": {
+ "description": "OTG_HS host configuration\n register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FSLSPCS": {
+ "description": "FS/LS PHY clock select",
+ "offset": 0,
+ "size": 2
+ },
+ "FSLSS": {
+ "description": "FS- and LS-only support",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "OTG_HS_HFIR": {
+ "description": "OTG_HS Host frame interval\n register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 60000,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FRIVL": {
+ "description": "Frame interval",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_HFNUM": {
+ "description": "OTG_HS host frame number/frame time\n remaining register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 16383,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "FRNUM": {
+ "description": "Frame number",
+ "offset": 0,
+ "size": 16
+ },
+ "FTREM": {
+ "description": "Frame time remaining",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_HPTXSTS": {
+ "description": "OTG_HS_Host periodic transmit FIFO/queue\n status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 524544,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PTXFSAVL": {
+ "description": "Periodic transmit data FIFO space\n available",
+ "offset": 0,
+ "size": 16
+ },
+ "PTXQSAV": {
+ "description": "Periodic transmit request queue space\n available",
+ "offset": 16,
+ "size": 8,
+ "access": "read-only"
+ },
+ "PTXQTOP": {
+ "description": "Top of the periodic transmit request\n queue",
+ "offset": 24,
+ "size": 8,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "OTG_HS_HAINT": {
+ "description": "OTG_HS Host all channels interrupt\n register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "HAINT": {
+ "description": "Channel interrupts",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_HAINTMSK": {
+ "description": "OTG_HS host all channels interrupt mask\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "HAINTM": {
+ "description": "Channel interrupt mask",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_HPRT": {
+ "description": "OTG_HS host port control and status\n register",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PCSTS": {
+ "description": "Port connect status",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PCDET": {
+ "description": "Port connect detected",
+ "offset": 1,
+ "size": 1
+ },
+ "PENA": {
+ "description": "Port enable",
+ "offset": 2,
+ "size": 1
+ },
+ "PENCHNG": {
+ "description": "Port enable/disable change",
+ "offset": 3,
+ "size": 1
+ },
+ "POCA": {
+ "description": "Port overcurrent active",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "POCCHNG": {
+ "description": "Port overcurrent change",
+ "offset": 5,
+ "size": 1
+ },
+ "PRES": {
+ "description": "Port resume",
+ "offset": 6,
+ "size": 1
+ },
+ "PSUSP": {
+ "description": "Port suspend",
+ "offset": 7,
+ "size": 1
+ },
+ "PRST": {
+ "description": "Port reset",
+ "offset": 8,
+ "size": 1
+ },
+ "PLSTS": {
+ "description": "Port line status",
+ "offset": 10,
+ "size": 2,
+ "access": "read-only"
+ },
+ "PPWR": {
+ "description": "Port power",
+ "offset": 12,
+ "size": 1
+ },
+ "PTCTL": {
+ "description": "Port test control",
+ "offset": 13,
+ "size": 4
+ },
+ "PSPD": {
+ "description": "Port speed",
+ "offset": 17,
+ "size": 2,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "OTG_HS_HCCHAR0": {
+ "description": "OTG_HS host channel-0 characteristics\n register",
+ "offset": 256,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MC": {
+ "description": "Multi Count (MC) / Error Count\n (EC)",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCCHAR1": {
+ "description": "OTG_HS host channel-1 characteristics\n register",
+ "offset": 288,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MC": {
+ "description": "Multi Count (MC) / Error Count\n (EC)",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCCHAR2": {
+ "description": "OTG_HS host channel-2 characteristics\n register",
+ "offset": 320,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MC": {
+ "description": "Multi Count (MC) / Error Count\n (EC)",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCCHAR3": {
+ "description": "OTG_HS host channel-3 characteristics\n register",
+ "offset": 352,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MC": {
+ "description": "Multi Count (MC) / Error Count\n (EC)",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCCHAR4": {
+ "description": "OTG_HS host channel-4 characteristics\n register",
+ "offset": 384,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MC": {
+ "description": "Multi Count (MC) / Error Count\n (EC)",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCCHAR5": {
+ "description": "OTG_HS host channel-5 characteristics\n register",
+ "offset": 416,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MC": {
+ "description": "Multi Count (MC) / Error Count\n (EC)",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCCHAR6": {
+ "description": "OTG_HS host channel-6 characteristics\n register",
+ "offset": 448,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MC": {
+ "description": "Multi Count (MC) / Error Count\n (EC)",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCCHAR7": {
+ "description": "OTG_HS host channel-7 characteristics\n register",
+ "offset": 480,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MC": {
+ "description": "Multi Count (MC) / Error Count\n (EC)",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCCHAR8": {
+ "description": "OTG_HS host channel-8 characteristics\n register",
+ "offset": 512,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MC": {
+ "description": "Multi Count (MC) / Error Count\n (EC)",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCCHAR9": {
+ "description": "OTG_HS host channel-9 characteristics\n register",
+ "offset": 544,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MC": {
+ "description": "Multi Count (MC) / Error Count\n (EC)",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCCHAR10": {
+ "description": "OTG_HS host channel-10 characteristics\n register",
+ "offset": 576,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MC": {
+ "description": "Multi Count (MC) / Error Count\n (EC)",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCCHAR11": {
+ "description": "OTG_HS host channel-11 characteristics\n register",
+ "offset": 608,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MC": {
+ "description": "Multi Count (MC) / Error Count\n (EC)",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCSPLT0": {
+ "description": "OTG_HS host channel-0 split control\n register",
+ "offset": 260,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRTADDR": {
+ "description": "Port address",
+ "offset": 0,
+ "size": 7
+ },
+ "HUBADDR": {
+ "description": "Hub address",
+ "offset": 7,
+ "size": 7
+ },
+ "XACTPOS": {
+ "description": "XACTPOS",
+ "offset": 14,
+ "size": 2
+ },
+ "COMPLSPLT": {
+ "description": "Do complete split",
+ "offset": 16,
+ "size": 1
+ },
+ "SPLITEN": {
+ "description": "Split enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCSPLT1": {
+ "description": "OTG_HS host channel-1 split control\n register",
+ "offset": 292,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRTADDR": {
+ "description": "Port address",
+ "offset": 0,
+ "size": 7
+ },
+ "HUBADDR": {
+ "description": "Hub address",
+ "offset": 7,
+ "size": 7
+ },
+ "XACTPOS": {
+ "description": "XACTPOS",
+ "offset": 14,
+ "size": 2
+ },
+ "COMPLSPLT": {
+ "description": "Do complete split",
+ "offset": 16,
+ "size": 1
+ },
+ "SPLITEN": {
+ "description": "Split enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCSPLT2": {
+ "description": "OTG_HS host channel-2 split control\n register",
+ "offset": 324,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRTADDR": {
+ "description": "Port address",
+ "offset": 0,
+ "size": 7
+ },
+ "HUBADDR": {
+ "description": "Hub address",
+ "offset": 7,
+ "size": 7
+ },
+ "XACTPOS": {
+ "description": "XACTPOS",
+ "offset": 14,
+ "size": 2
+ },
+ "COMPLSPLT": {
+ "description": "Do complete split",
+ "offset": 16,
+ "size": 1
+ },
+ "SPLITEN": {
+ "description": "Split enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCSPLT3": {
+ "description": "OTG_HS host channel-3 split control\n register",
+ "offset": 356,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRTADDR": {
+ "description": "Port address",
+ "offset": 0,
+ "size": 7
+ },
+ "HUBADDR": {
+ "description": "Hub address",
+ "offset": 7,
+ "size": 7
+ },
+ "XACTPOS": {
+ "description": "XACTPOS",
+ "offset": 14,
+ "size": 2
+ },
+ "COMPLSPLT": {
+ "description": "Do complete split",
+ "offset": 16,
+ "size": 1
+ },
+ "SPLITEN": {
+ "description": "Split enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCSPLT4": {
+ "description": "OTG_HS host channel-4 split control\n register",
+ "offset": 388,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRTADDR": {
+ "description": "Port address",
+ "offset": 0,
+ "size": 7
+ },
+ "HUBADDR": {
+ "description": "Hub address",
+ "offset": 7,
+ "size": 7
+ },
+ "XACTPOS": {
+ "description": "XACTPOS",
+ "offset": 14,
+ "size": 2
+ },
+ "COMPLSPLT": {
+ "description": "Do complete split",
+ "offset": 16,
+ "size": 1
+ },
+ "SPLITEN": {
+ "description": "Split enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCSPLT5": {
+ "description": "OTG_HS host channel-5 split control\n register",
+ "offset": 420,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRTADDR": {
+ "description": "Port address",
+ "offset": 0,
+ "size": 7
+ },
+ "HUBADDR": {
+ "description": "Hub address",
+ "offset": 7,
+ "size": 7
+ },
+ "XACTPOS": {
+ "description": "XACTPOS",
+ "offset": 14,
+ "size": 2
+ },
+ "COMPLSPLT": {
+ "description": "Do complete split",
+ "offset": 16,
+ "size": 1
+ },
+ "SPLITEN": {
+ "description": "Split enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCSPLT6": {
+ "description": "OTG_HS host channel-6 split control\n register",
+ "offset": 452,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRTADDR": {
+ "description": "Port address",
+ "offset": 0,
+ "size": 7
+ },
+ "HUBADDR": {
+ "description": "Hub address",
+ "offset": 7,
+ "size": 7
+ },
+ "XACTPOS": {
+ "description": "XACTPOS",
+ "offset": 14,
+ "size": 2
+ },
+ "COMPLSPLT": {
+ "description": "Do complete split",
+ "offset": 16,
+ "size": 1
+ },
+ "SPLITEN": {
+ "description": "Split enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCSPLT7": {
+ "description": "OTG_HS host channel-7 split control\n register",
+ "offset": 484,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRTADDR": {
+ "description": "Port address",
+ "offset": 0,
+ "size": 7
+ },
+ "HUBADDR": {
+ "description": "Hub address",
+ "offset": 7,
+ "size": 7
+ },
+ "XACTPOS": {
+ "description": "XACTPOS",
+ "offset": 14,
+ "size": 2
+ },
+ "COMPLSPLT": {
+ "description": "Do complete split",
+ "offset": 16,
+ "size": 1
+ },
+ "SPLITEN": {
+ "description": "Split enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCSPLT8": {
+ "description": "OTG_HS host channel-8 split control\n register",
+ "offset": 516,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRTADDR": {
+ "description": "Port address",
+ "offset": 0,
+ "size": 7
+ },
+ "HUBADDR": {
+ "description": "Hub address",
+ "offset": 7,
+ "size": 7
+ },
+ "XACTPOS": {
+ "description": "XACTPOS",
+ "offset": 14,
+ "size": 2
+ },
+ "COMPLSPLT": {
+ "description": "Do complete split",
+ "offset": 16,
+ "size": 1
+ },
+ "SPLITEN": {
+ "description": "Split enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCSPLT9": {
+ "description": "OTG_HS host channel-9 split control\n register",
+ "offset": 548,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRTADDR": {
+ "description": "Port address",
+ "offset": 0,
+ "size": 7
+ },
+ "HUBADDR": {
+ "description": "Hub address",
+ "offset": 7,
+ "size": 7
+ },
+ "XACTPOS": {
+ "description": "XACTPOS",
+ "offset": 14,
+ "size": 2
+ },
+ "COMPLSPLT": {
+ "description": "Do complete split",
+ "offset": 16,
+ "size": 1
+ },
+ "SPLITEN": {
+ "description": "Split enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCSPLT10": {
+ "description": "OTG_HS host channel-10 split control\n register",
+ "offset": 580,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRTADDR": {
+ "description": "Port address",
+ "offset": 0,
+ "size": 7
+ },
+ "HUBADDR": {
+ "description": "Hub address",
+ "offset": 7,
+ "size": 7
+ },
+ "XACTPOS": {
+ "description": "XACTPOS",
+ "offset": 14,
+ "size": 2
+ },
+ "COMPLSPLT": {
+ "description": "Do complete split",
+ "offset": 16,
+ "size": 1
+ },
+ "SPLITEN": {
+ "description": "Split enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCSPLT11": {
+ "description": "OTG_HS host channel-11 split control\n register",
+ "offset": 612,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRTADDR": {
+ "description": "Port address",
+ "offset": 0,
+ "size": 7
+ },
+ "HUBADDR": {
+ "description": "Hub address",
+ "offset": 7,
+ "size": 7
+ },
+ "XACTPOS": {
+ "description": "XACTPOS",
+ "offset": 14,
+ "size": 2
+ },
+ "COMPLSPLT": {
+ "description": "Do complete split",
+ "offset": 16,
+ "size": 1
+ },
+ "SPLITEN": {
+ "description": "Split enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINT0": {
+ "description": "OTG_HS host channel-11 interrupt\n register",
+ "offset": 264,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "Response received\n interrupt",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINT1": {
+ "description": "OTG_HS host channel-1 interrupt\n register",
+ "offset": 296,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "Response received\n interrupt",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINT2": {
+ "description": "OTG_HS host channel-2 interrupt\n register",
+ "offset": 328,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "Response received\n interrupt",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINT3": {
+ "description": "OTG_HS host channel-3 interrupt\n register",
+ "offset": 360,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "Response received\n interrupt",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINT4": {
+ "description": "OTG_HS host channel-4 interrupt\n register",
+ "offset": 392,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "Response received\n interrupt",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINT5": {
+ "description": "OTG_HS host channel-5 interrupt\n register",
+ "offset": 424,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "Response received\n interrupt",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINT6": {
+ "description": "OTG_HS host channel-6 interrupt\n register",
+ "offset": 456,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "Response received\n interrupt",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINT7": {
+ "description": "OTG_HS host channel-7 interrupt\n register",
+ "offset": 488,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "Response received\n interrupt",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINT8": {
+ "description": "OTG_HS host channel-8 interrupt\n register",
+ "offset": 520,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "Response received\n interrupt",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINT9": {
+ "description": "OTG_HS host channel-9 interrupt\n register",
+ "offset": 552,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "Response received\n interrupt",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINT10": {
+ "description": "OTG_HS host channel-10 interrupt\n register",
+ "offset": 584,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "Response received\n interrupt",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINT11": {
+ "description": "OTG_HS host channel-11 interrupt\n register",
+ "offset": 616,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "Response received\n interrupt",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINTMSK0": {
+ "description": "OTG_HS host channel-11 interrupt mask\n register",
+ "offset": 268,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINTMSK1": {
+ "description": "OTG_HS host channel-1 interrupt mask\n register",
+ "offset": 300,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINTMSK2": {
+ "description": "OTG_HS host channel-2 interrupt mask\n register",
+ "offset": 332,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINTMSK3": {
+ "description": "OTG_HS host channel-3 interrupt mask\n register",
+ "offset": 364,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINTMSK4": {
+ "description": "OTG_HS host channel-4 interrupt mask\n register",
+ "offset": 396,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINTMSK5": {
+ "description": "OTG_HS host channel-5 interrupt mask\n register",
+ "offset": 428,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINTMSK6": {
+ "description": "OTG_HS host channel-6 interrupt mask\n register",
+ "offset": 460,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINTMSK7": {
+ "description": "OTG_HS host channel-7 interrupt mask\n register",
+ "offset": 492,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINTMSK8": {
+ "description": "OTG_HS host channel-8 interrupt mask\n register",
+ "offset": 524,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINTMSK9": {
+ "description": "OTG_HS host channel-9 interrupt mask\n register",
+ "offset": 556,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINTMSK10": {
+ "description": "OTG_HS host channel-10 interrupt mask\n register",
+ "offset": 588,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCINTMSK11": {
+ "description": "OTG_HS host channel-11 interrupt mask\n register",
+ "offset": 620,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "AHBERR": {
+ "description": "AHB error",
+ "offset": 2,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_HCTSIZ0": {
+ "description": "OTG_HS host channel-11 transfer size\n register",
+ "offset": 272,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_HCTSIZ1": {
+ "description": "OTG_HS host channel-1 transfer size\n register",
+ "offset": 304,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_HCTSIZ2": {
+ "description": "OTG_HS host channel-2 transfer size\n register",
+ "offset": 336,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_HCTSIZ3": {
+ "description": "OTG_HS host channel-3 transfer size\n register",
+ "offset": 368,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_HCTSIZ4": {
+ "description": "OTG_HS host channel-4 transfer size\n register",
+ "offset": 400,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_HCTSIZ5": {
+ "description": "OTG_HS host channel-5 transfer size\n register",
+ "offset": 432,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_HCTSIZ6": {
+ "description": "OTG_HS host channel-6 transfer size\n register",
+ "offset": 464,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_HCTSIZ7": {
+ "description": "OTG_HS host channel-7 transfer size\n register",
+ "offset": 496,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_HCTSIZ8": {
+ "description": "OTG_HS host channel-8 transfer size\n register",
+ "offset": 528,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_HCTSIZ9": {
+ "description": "OTG_HS host channel-9 transfer size\n register",
+ "offset": 560,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_HCTSIZ10": {
+ "description": "OTG_HS host channel-10 transfer size\n register",
+ "offset": 592,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_HCTSIZ11": {
+ "description": "OTG_HS host channel-11 transfer size\n register",
+ "offset": 624,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "OTG_HS_HCDMA0": {
+ "description": "OTG_HS host channel-0 DMA address\n register",
+ "offset": 276,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_HCDMA1": {
+ "description": "OTG_HS host channel-1 DMA address\n register",
+ "offset": 308,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_HCDMA2": {
+ "description": "OTG_HS host channel-2 DMA address\n register",
+ "offset": 340,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_HCDMA3": {
+ "description": "OTG_HS host channel-3 DMA address\n register",
+ "offset": 372,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_HCDMA4": {
+ "description": "OTG_HS host channel-4 DMA address\n register",
+ "offset": 404,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_HCDMA5": {
+ "description": "OTG_HS host channel-5 DMA address\n register",
+ "offset": 436,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_HCDMA6": {
+ "description": "OTG_HS host channel-6 DMA address\n register",
+ "offset": 468,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_HCDMA7": {
+ "description": "OTG_HS host channel-7 DMA address\n register",
+ "offset": 500,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_HCDMA8": {
+ "description": "OTG_HS host channel-8 DMA address\n register",
+ "offset": 532,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_HCDMA9": {
+ "description": "OTG_HS host channel-9 DMA address\n register",
+ "offset": 564,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_HCDMA10": {
+ "description": "OTG_HS host channel-10 DMA address\n register",
+ "offset": 596,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_HCDMA11": {
+ "description": "OTG_HS host channel-11 DMA address\n register",
+ "offset": 628,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAADDR": {
+ "description": "DMA address",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "SDIO": {
+ "description": "Secure digital input/output\n interface",
+ "children": {
+ "registers": {
+ "POWER": {
+ "description": "power control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PWRCTRL": {
+ "description": "PWRCTRL",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CLKCR": {
+ "description": "SDI clock control register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "HWFC_EN": {
+ "description": "HW Flow Control enable",
+ "offset": 14,
+ "size": 1
+ },
+ "NEGEDGE": {
+ "description": "SDIO_CK dephasing selection\n bit",
+ "offset": 13,
+ "size": 1
+ },
+ "WIDBUS": {
+ "description": "Wide bus mode enable bit",
+ "offset": 11,
+ "size": 2
+ },
+ "BYPASS": {
+ "description": "Clock divider bypass enable\n bit",
+ "offset": 10,
+ "size": 1
+ },
+ "PWRSAV": {
+ "description": "Power saving configuration\n bit",
+ "offset": 9,
+ "size": 1
+ },
+ "CLKEN": {
+ "description": "Clock enable bit",
+ "offset": 8,
+ "size": 1
+ },
+ "CLKDIV": {
+ "description": "Clock divide factor",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "ARG": {
+ "description": "argument register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CMDARG": {
+ "description": "Command argument",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "CMD": {
+ "description": "command register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CE_ATACMD": {
+ "description": "CE-ATA command",
+ "offset": 14,
+ "size": 1
+ },
+ "nIEN": {
+ "description": "not Interrupt Enable",
+ "offset": 13,
+ "size": 1
+ },
+ "ENCMDcompl": {
+ "description": "Enable CMD completion",
+ "offset": 12,
+ "size": 1
+ },
+ "SDIOSuspend": {
+ "description": "SD I/O suspend command",
+ "offset": 11,
+ "size": 1
+ },
+ "CPSMEN": {
+ "description": "Command path state machine (CPSM) Enable\n bit",
+ "offset": 10,
+ "size": 1
+ },
+ "WAITPEND": {
+ "description": "CPSM Waits for ends of data transfer\n (CmdPend internal signal).",
+ "offset": 9,
+ "size": 1
+ },
+ "WAITINT": {
+ "description": "CPSM waits for interrupt\n request",
+ "offset": 8,
+ "size": 1
+ },
+ "WAITRESP": {
+ "description": "Wait for response bits",
+ "offset": 6,
+ "size": 2
+ },
+ "CMDINDEX": {
+ "description": "Command index",
+ "offset": 0,
+ "size": 6
+ }
+ }
+ }
+ },
+ "RESPCMD": {
+ "description": "command response register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "RESPCMD": {
+ "description": "Response command index",
+ "offset": 0,
+ "size": 6
+ }
+ }
+ }
+ },
+ "RESP1": {
+ "description": "response 1..4 register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CARDSTATUS1": {
+ "description": "see Table 132.",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "RESP2": {
+ "description": "response 1..4 register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CARDSTATUS2": {
+ "description": "see Table 132.",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "RESP3": {
+ "description": "response 1..4 register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CARDSTATUS3": {
+ "description": "see Table 132.",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "RESP4": {
+ "description": "response 1..4 register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CARDSTATUS4": {
+ "description": "see Table 132.",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DTIMER": {
+ "description": "data timer register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATATIME": {
+ "description": "Data timeout period",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DLEN": {
+ "description": "data length register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATALENGTH": {
+ "description": "Data length value",
+ "offset": 0,
+ "size": 25
+ }
+ }
+ }
+ },
+ "DCTRL": {
+ "description": "data control register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SDIOEN": {
+ "description": "SD I/O enable functions",
+ "offset": 11,
+ "size": 1
+ },
+ "RWMOD": {
+ "description": "Read wait mode",
+ "offset": 10,
+ "size": 1
+ },
+ "RWSTOP": {
+ "description": "Read wait stop",
+ "offset": 9,
+ "size": 1
+ },
+ "RWSTART": {
+ "description": "Read wait start",
+ "offset": 8,
+ "size": 1
+ },
+ "DBLOCKSIZE": {
+ "description": "Data block size",
+ "offset": 4,
+ "size": 4
+ },
+ "DMAEN": {
+ "description": "DMA enable bit",
+ "offset": 3,
+ "size": 1
+ },
+ "DTMODE": {
+ "description": "Data transfer mode selection 1: Stream\n or SDIO multibyte data transfer.",
+ "offset": 2,
+ "size": 1
+ },
+ "DTDIR": {
+ "description": "Data transfer direction\n selection",
+ "offset": 1,
+ "size": 1
+ },
+ "DTEN": {
+ "description": "DTEN",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DCOUNT": {
+ "description": "data counter register",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DATACOUNT": {
+ "description": "Data count value",
+ "offset": 0,
+ "size": 25
+ }
+ }
+ }
+ },
+ "STA": {
+ "description": "status register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CEATAEND": {
+ "description": "CE-ATA command completion signal\n received for CMD61",
+ "offset": 23,
+ "size": 1
+ },
+ "SDIOIT": {
+ "description": "SDIO interrupt received",
+ "offset": 22,
+ "size": 1
+ },
+ "RXDAVL": {
+ "description": "Data available in receive\n FIFO",
+ "offset": 21,
+ "size": 1
+ },
+ "TXDAVL": {
+ "description": "Data available in transmit\n FIFO",
+ "offset": 20,
+ "size": 1
+ },
+ "RXFIFOE": {
+ "description": "Receive FIFO empty",
+ "offset": 19,
+ "size": 1
+ },
+ "TXFIFOE": {
+ "description": "Transmit FIFO empty",
+ "offset": 18,
+ "size": 1
+ },
+ "RXFIFOF": {
+ "description": "Receive FIFO full",
+ "offset": 17,
+ "size": 1
+ },
+ "TXFIFOF": {
+ "description": "Transmit FIFO full",
+ "offset": 16,
+ "size": 1
+ },
+ "RXFIFOHF": {
+ "description": "Receive FIFO half full: there are at\n least 8 words in the FIFO",
+ "offset": 15,
+ "size": 1
+ },
+ "TXFIFOHE": {
+ "description": "Transmit FIFO half empty: at least 8\n words can be written into the FIFO",
+ "offset": 14,
+ "size": 1
+ },
+ "RXACT": {
+ "description": "Data receive in progress",
+ "offset": 13,
+ "size": 1
+ },
+ "TXACT": {
+ "description": "Data transmit in progress",
+ "offset": 12,
+ "size": 1
+ },
+ "CMDACT": {
+ "description": "Command transfer in\n progress",
+ "offset": 11,
+ "size": 1
+ },
+ "DBCKEND": {
+ "description": "Data block sent/received (CRC check\n passed)",
+ "offset": 10,
+ "size": 1
+ },
+ "STBITERR": {
+ "description": "Start bit not detected on all data\n signals in wide bus mode",
+ "offset": 9,
+ "size": 1
+ },
+ "DATAEND": {
+ "description": "Data end (data counter, SDIDCOUNT, is\n zero)",
+ "offset": 8,
+ "size": 1
+ },
+ "CMDSENT": {
+ "description": "Command sent (no response\n required)",
+ "offset": 7,
+ "size": 1
+ },
+ "CMDREND": {
+ "description": "Command response received (CRC check\n passed)",
+ "offset": 6,
+ "size": 1
+ },
+ "RXOVERR": {
+ "description": "Received FIFO overrun\n error",
+ "offset": 5,
+ "size": 1
+ },
+ "TXUNDERR": {
+ "description": "Transmit FIFO underrun\n error",
+ "offset": 4,
+ "size": 1
+ },
+ "DTIMEOUT": {
+ "description": "Data timeout",
+ "offset": 3,
+ "size": 1
+ },
+ "CTIMEOUT": {
+ "description": "Command response timeout",
+ "offset": 2,
+ "size": 1
+ },
+ "DCRCFAIL": {
+ "description": "Data block sent/received (CRC check\n failed)",
+ "offset": 1,
+ "size": 1
+ },
+ "CCRCFAIL": {
+ "description": "Command response received (CRC check\n failed)",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ICR": {
+ "description": "interrupt clear register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CEATAENDC": {
+ "description": "CEATAEND flag clear bit",
+ "offset": 23,
+ "size": 1
+ },
+ "SDIOITC": {
+ "description": "SDIOIT flag clear bit",
+ "offset": 22,
+ "size": 1
+ },
+ "DBCKENDC": {
+ "description": "DBCKEND flag clear bit",
+ "offset": 10,
+ "size": 1
+ },
+ "STBITERRC": {
+ "description": "STBITERR flag clear bit",
+ "offset": 9,
+ "size": 1
+ },
+ "DATAENDC": {
+ "description": "DATAEND flag clear bit",
+ "offset": 8,
+ "size": 1
+ },
+ "CMDSENTC": {
+ "description": "CMDSENT flag clear bit",
+ "offset": 7,
+ "size": 1
+ },
+ "CMDRENDC": {
+ "description": "CMDREND flag clear bit",
+ "offset": 6,
+ "size": 1
+ },
+ "RXOVERRC": {
+ "description": "RXOVERR flag clear bit",
+ "offset": 5,
+ "size": 1
+ },
+ "TXUNDERRC": {
+ "description": "TXUNDERR flag clear bit",
+ "offset": 4,
+ "size": 1
+ },
+ "DTIMEOUTC": {
+ "description": "DTIMEOUT flag clear bit",
+ "offset": 3,
+ "size": 1
+ },
+ "CTIMEOUTC": {
+ "description": "CTIMEOUT flag clear bit",
+ "offset": 2,
+ "size": 1
+ },
+ "DCRCFAILC": {
+ "description": "DCRCFAIL flag clear bit",
+ "offset": 1,
+ "size": 1
+ },
+ "CCRCFAILC": {
+ "description": "CCRCFAIL flag clear bit",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MASK": {
+ "description": "mask register",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CEATAENDIE": {
+ "description": "CE-ATA command completion signal\n received interrupt enable",
+ "offset": 23,
+ "size": 1
+ },
+ "SDIOITIE": {
+ "description": "SDIO mode interrupt received interrupt\n enable",
+ "offset": 22,
+ "size": 1
+ },
+ "RXDAVLIE": {
+ "description": "Data available in Rx FIFO interrupt\n enable",
+ "offset": 21,
+ "size": 1
+ },
+ "TXDAVLIE": {
+ "description": "Data available in Tx FIFO interrupt\n enable",
+ "offset": 20,
+ "size": 1
+ },
+ "RXFIFOEIE": {
+ "description": "Rx FIFO empty interrupt\n enable",
+ "offset": 19,
+ "size": 1
+ },
+ "TXFIFOEIE": {
+ "description": "Tx FIFO empty interrupt\n enable",
+ "offset": 18,
+ "size": 1
+ },
+ "RXFIFOFIE": {
+ "description": "Rx FIFO full interrupt\n enable",
+ "offset": 17,
+ "size": 1
+ },
+ "TXFIFOFIE": {
+ "description": "Tx FIFO full interrupt\n enable",
+ "offset": 16,
+ "size": 1
+ },
+ "RXFIFOHFIE": {
+ "description": "Rx FIFO half full interrupt\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "TXFIFOHEIE": {
+ "description": "Tx FIFO half empty interrupt\n enable",
+ "offset": 14,
+ "size": 1
+ },
+ "RXACTIE": {
+ "description": "Data receive acting interrupt\n enable",
+ "offset": 13,
+ "size": 1
+ },
+ "TXACTIE": {
+ "description": "Data transmit acting interrupt\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "CMDACTIE": {
+ "description": "Command acting interrupt\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "DBCKENDIE": {
+ "description": "Data block end interrupt\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "STBITERRIE": {
+ "description": "Start bit error interrupt\n enable",
+ "offset": 9,
+ "size": 1
+ },
+ "DATAENDIE": {
+ "description": "Data end interrupt enable",
+ "offset": 8,
+ "size": 1
+ },
+ "CMDSENTIE": {
+ "description": "Command sent interrupt\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "CMDRENDIE": {
+ "description": "Command response received interrupt\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "RXOVERRIE": {
+ "description": "Rx FIFO overrun error interrupt\n enable",
+ "offset": 5,
+ "size": 1
+ },
+ "TXUNDERRIE": {
+ "description": "Tx FIFO underrun error interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "DTIMEOUTIE": {
+ "description": "Data timeout interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "CTIMEOUTIE": {
+ "description": "Command timeout interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "DCRCFAILIE": {
+ "description": "Data CRC fail interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "CCRCFAILIE": {
+ "description": "Command CRC fail interrupt\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FIFOCNT": {
+ "description": "FIFO counter register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "FIFOCOUNT": {
+ "description": "Remaining number of words to be written\n to or read from the FIFO.",
+ "offset": 0,
+ "size": 24
+ }
+ }
+ }
+ },
+ "FIFO": {
+ "description": "data FIFO register",
+ "offset": 128,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FIFOData": {
+ "description": "Receive and transmit FIFO\n data",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "ADC1": {
+ "description": "Analog-to-digital converter",
+ "children": {
+ "registers": {
+ "SR": {
+ "description": "status register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OVR": {
+ "description": "Overrun",
+ "offset": 5,
+ "size": 1
+ },
+ "STRT": {
+ "description": "Regular channel start flag",
+ "offset": 4,
+ "size": 1
+ },
+ "JSTRT": {
+ "description": "Injected channel start\n flag",
+ "offset": 3,
+ "size": 1
+ },
+ "JEOC": {
+ "description": "Injected channel end of\n conversion",
+ "offset": 2,
+ "size": 1
+ },
+ "EOC": {
+ "description": "Regular channel end of\n conversion",
+ "offset": 1,
+ "size": 1
+ },
+ "AWD": {
+ "description": "Analog watchdog flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR1": {
+ "description": "control register 1",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OVRIE": {
+ "description": "Overrun interrupt enable",
+ "offset": 26,
+ "size": 1
+ },
+ "RES": {
+ "description": "Resolution",
+ "offset": 24,
+ "size": 2
+ },
+ "AWDEN": {
+ "description": "Analog watchdog enable on regular\n channels",
+ "offset": 23,
+ "size": 1
+ },
+ "JAWDEN": {
+ "description": "Analog watchdog enable on injected\n channels",
+ "offset": 22,
+ "size": 1
+ },
+ "DISCNUM": {
+ "description": "Discontinuous mode channel\n count",
+ "offset": 13,
+ "size": 3
+ },
+ "JDISCEN": {
+ "description": "Discontinuous mode on injected\n channels",
+ "offset": 12,
+ "size": 1
+ },
+ "DISCEN": {
+ "description": "Discontinuous mode on regular\n channels",
+ "offset": 11,
+ "size": 1
+ },
+ "JAUTO": {
+ "description": "Automatic injected group\n conversion",
+ "offset": 10,
+ "size": 1
+ },
+ "AWDSGL": {
+ "description": "Enable the watchdog on a single channel\n in scan mode",
+ "offset": 9,
+ "size": 1
+ },
+ "SCAN": {
+ "description": "Scan mode",
+ "offset": 8,
+ "size": 1
+ },
+ "JEOCIE": {
+ "description": "Interrupt enable for injected\n channels",
+ "offset": 7,
+ "size": 1
+ },
+ "AWDIE": {
+ "description": "Analog watchdog interrupt\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "EOCIE": {
+ "description": "Interrupt enable for EOC",
+ "offset": 5,
+ "size": 1
+ },
+ "AWDCH": {
+ "description": "Analog watchdog channel select\n bits",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SWSTART": {
+ "description": "Start conversion of regular\n channels",
+ "offset": 30,
+ "size": 1
+ },
+ "EXTEN": {
+ "description": "External trigger enable for regular\n channels",
+ "offset": 28,
+ "size": 2
+ },
+ "EXTSEL": {
+ "description": "External event select for regular\n group",
+ "offset": 24,
+ "size": 4
+ },
+ "JSWSTART": {
+ "description": "Start conversion of injected\n channels",
+ "offset": 22,
+ "size": 1
+ },
+ "JEXTEN": {
+ "description": "External trigger enable for injected\n channels",
+ "offset": 20,
+ "size": 2
+ },
+ "JEXTSEL": {
+ "description": "External event select for injected\n group",
+ "offset": 16,
+ "size": 4
+ },
+ "ALIGN": {
+ "description": "Data alignment",
+ "offset": 11,
+ "size": 1
+ },
+ "EOCS": {
+ "description": "End of conversion\n selection",
+ "offset": 10,
+ "size": 1
+ },
+ "DDS": {
+ "description": "DMA disable selection (for single ADC\n mode)",
+ "offset": 9,
+ "size": 1
+ },
+ "DMA": {
+ "description": "Direct memory access mode (for single\n ADC mode)",
+ "offset": 8,
+ "size": 1
+ },
+ "CONT": {
+ "description": "Continuous conversion",
+ "offset": 1,
+ "size": 1
+ },
+ "ADON": {
+ "description": "A/D Converter ON / OFF",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SMPR1": {
+ "description": "sample time register 1",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SMPx_x": {
+ "description": "Sample time bits",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "SMPR2": {
+ "description": "sample time register 2",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SMPx_x": {
+ "description": "Sample time bits",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "JOFR1": {
+ "description": "injected channel data offset register\n x",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "JOFFSET1": {
+ "description": "Data offset for injected channel\n x",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "JOFR2": {
+ "description": "injected channel data offset register\n x",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "JOFFSET2": {
+ "description": "Data offset for injected channel\n x",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "JOFR3": {
+ "description": "injected channel data offset register\n x",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "JOFFSET3": {
+ "description": "Data offset for injected channel\n x",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "JOFR4": {
+ "description": "injected channel data offset register\n x",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "JOFFSET4": {
+ "description": "Data offset for injected channel\n x",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "HTR": {
+ "description": "watchdog higher threshold\n register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 4095,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "HT": {
+ "description": "Analog watchdog higher\n threshold",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "LTR": {
+ "description": "watchdog lower threshold\n register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LT": {
+ "description": "Analog watchdog lower\n threshold",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "SQR1": {
+ "description": "regular sequence register 1",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "L": {
+ "description": "Regular channel sequence\n length",
+ "offset": 20,
+ "size": 4
+ },
+ "SQ16": {
+ "description": "16th conversion in regular\n sequence",
+ "offset": 15,
+ "size": 5
+ },
+ "SQ15": {
+ "description": "15th conversion in regular\n sequence",
+ "offset": 10,
+ "size": 5
+ },
+ "SQ14": {
+ "description": "14th conversion in regular\n sequence",
+ "offset": 5,
+ "size": 5
+ },
+ "SQ13": {
+ "description": "13th conversion in regular\n sequence",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "SQR2": {
+ "description": "regular sequence register 2",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SQ12": {
+ "description": "12th conversion in regular\n sequence",
+ "offset": 25,
+ "size": 5
+ },
+ "SQ11": {
+ "description": "11th conversion in regular\n sequence",
+ "offset": 20,
+ "size": 5
+ },
+ "SQ10": {
+ "description": "10th conversion in regular\n sequence",
+ "offset": 15,
+ "size": 5
+ },
+ "SQ9": {
+ "description": "9th conversion in regular\n sequence",
+ "offset": 10,
+ "size": 5
+ },
+ "SQ8": {
+ "description": "8th conversion in regular\n sequence",
+ "offset": 5,
+ "size": 5
+ },
+ "SQ7": {
+ "description": "7th conversion in regular\n sequence",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "SQR3": {
+ "description": "regular sequence register 3",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SQ6": {
+ "description": "6th conversion in regular\n sequence",
+ "offset": 25,
+ "size": 5
+ },
+ "SQ5": {
+ "description": "5th conversion in regular\n sequence",
+ "offset": 20,
+ "size": 5
+ },
+ "SQ4": {
+ "description": "4th conversion in regular\n sequence",
+ "offset": 15,
+ "size": 5
+ },
+ "SQ3": {
+ "description": "3rd conversion in regular\n sequence",
+ "offset": 10,
+ "size": 5
+ },
+ "SQ2": {
+ "description": "2nd conversion in regular\n sequence",
+ "offset": 5,
+ "size": 5
+ },
+ "SQ1": {
+ "description": "1st conversion in regular\n sequence",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "JSQR": {
+ "description": "injected sequence register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "JL": {
+ "description": "Injected sequence length",
+ "offset": 20,
+ "size": 2
+ },
+ "JSQ4": {
+ "description": "4th conversion in injected\n sequence",
+ "offset": 15,
+ "size": 5
+ },
+ "JSQ3": {
+ "description": "3rd conversion in injected\n sequence",
+ "offset": 10,
+ "size": 5
+ },
+ "JSQ2": {
+ "description": "2nd conversion in injected\n sequence",
+ "offset": 5,
+ "size": 5
+ },
+ "JSQ1": {
+ "description": "1st conversion in injected\n sequence",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "JDR1": {
+ "description": "injected data register x",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "JDATA": {
+ "description": "Injected data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "JDR2": {
+ "description": "injected data register x",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "JDATA": {
+ "description": "Injected data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "JDR3": {
+ "description": "injected data register x",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "JDATA": {
+ "description": "Injected data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "JDR4": {
+ "description": "injected data register x",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "JDATA": {
+ "description": "Injected data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DR": {
+ "description": "regular data register",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DATA": {
+ "description": "Regular data",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "OTG_HS_GLOBAL": {
+ "description": "USB on the go high speed",
+ "children": {
+ "registers": {
+ "OTG_HS_GOTGCTL": {
+ "description": "OTG_HS control and status\n register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 2048,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SRQSCS": {
+ "description": "Session request success",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SRQ": {
+ "description": "Session request",
+ "offset": 1,
+ "size": 1
+ },
+ "HNGSCS": {
+ "description": "Host negotiation success",
+ "offset": 8,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HNPRQ": {
+ "description": "HNP request",
+ "offset": 9,
+ "size": 1
+ },
+ "HSHNPEN": {
+ "description": "Host set HNP enable",
+ "offset": 10,
+ "size": 1
+ },
+ "DHNPEN": {
+ "description": "Device HNP enabled",
+ "offset": 11,
+ "size": 1
+ },
+ "CIDSTS": {
+ "description": "Connector ID status",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "DBCT": {
+ "description": "Long/short debounce time",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ASVLD": {
+ "description": "A-session valid",
+ "offset": 18,
+ "size": 1,
+ "access": "read-only"
+ },
+ "BSVLD": {
+ "description": "B-session valid",
+ "offset": 19,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "OTG_HS_GOTGINT": {
+ "description": "OTG_HS interrupt register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SEDET": {
+ "description": "Session end detected",
+ "offset": 2,
+ "size": 1
+ },
+ "SRSSCHG": {
+ "description": "Session request success status\n change",
+ "offset": 8,
+ "size": 1
+ },
+ "HNSSCHG": {
+ "description": "Host negotiation success status\n change",
+ "offset": 9,
+ "size": 1
+ },
+ "HNGDET": {
+ "description": "Host negotiation detected",
+ "offset": 17,
+ "size": 1
+ },
+ "ADTOCHG": {
+ "description": "A-device timeout change",
+ "offset": 18,
+ "size": 1
+ },
+ "DBCDNE": {
+ "description": "Debounce done",
+ "offset": 19,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_GAHBCFG": {
+ "description": "OTG_HS AHB configuration\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "GINT": {
+ "description": "Global interrupt mask",
+ "offset": 0,
+ "size": 1
+ },
+ "HBSTLEN": {
+ "description": "Burst length/type",
+ "offset": 1,
+ "size": 4
+ },
+ "DMAEN": {
+ "description": "DMA enable",
+ "offset": 5,
+ "size": 1
+ },
+ "TXFELVL": {
+ "description": "TxFIFO empty level",
+ "offset": 7,
+ "size": 1
+ },
+ "PTXFELVL": {
+ "description": "Periodic TxFIFO empty\n level",
+ "offset": 8,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_GUSBCFG": {
+ "description": "OTG_HS USB configuration\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 2560,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TOCAL": {
+ "description": "FS timeout calibration",
+ "offset": 0,
+ "size": 3
+ },
+ "PHYSEL": {
+ "description": "USB 2.0 high-speed ULPI PHY or USB 1.1\n full-speed serial transceiver select",
+ "offset": 6,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SRPCAP": {
+ "description": "SRP-capable",
+ "offset": 8,
+ "size": 1
+ },
+ "HNPCAP": {
+ "description": "HNP-capable",
+ "offset": 9,
+ "size": 1
+ },
+ "TRDT": {
+ "description": "USB turnaround time",
+ "offset": 10,
+ "size": 4
+ },
+ "PHYLPCS": {
+ "description": "PHY Low-power clock select",
+ "offset": 15,
+ "size": 1
+ },
+ "ULPIFSLS": {
+ "description": "ULPI FS/LS select",
+ "offset": 17,
+ "size": 1
+ },
+ "ULPIAR": {
+ "description": "ULPI Auto-resume",
+ "offset": 18,
+ "size": 1
+ },
+ "ULPICSM": {
+ "description": "ULPI Clock SuspendM",
+ "offset": 19,
+ "size": 1
+ },
+ "ULPIEVBUSD": {
+ "description": "ULPI External VBUS Drive",
+ "offset": 20,
+ "size": 1
+ },
+ "ULPIEVBUSI": {
+ "description": "ULPI external VBUS\n indicator",
+ "offset": 21,
+ "size": 1
+ },
+ "TSDPS": {
+ "description": "TermSel DLine pulsing\n selection",
+ "offset": 22,
+ "size": 1
+ },
+ "PCCI": {
+ "description": "Indicator complement",
+ "offset": 23,
+ "size": 1
+ },
+ "PTCI": {
+ "description": "Indicator pass through",
+ "offset": 24,
+ "size": 1
+ },
+ "ULPIIPD": {
+ "description": "ULPI interface protect\n disable",
+ "offset": 25,
+ "size": 1
+ },
+ "FHMOD": {
+ "description": "Forced host mode",
+ "offset": 29,
+ "size": 1
+ },
+ "FDMOD": {
+ "description": "Forced peripheral mode",
+ "offset": 30,
+ "size": 1
+ },
+ "CTXPKT": {
+ "description": "Corrupt Tx packet",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_GRSTCTL": {
+ "description": "OTG_HS reset register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 536870912,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSRST": {
+ "description": "Core soft reset",
+ "offset": 0,
+ "size": 1
+ },
+ "HSRST": {
+ "description": "HCLK soft reset",
+ "offset": 1,
+ "size": 1
+ },
+ "FCRST": {
+ "description": "Host frame counter reset",
+ "offset": 2,
+ "size": 1
+ },
+ "RXFFLSH": {
+ "description": "RxFIFO flush",
+ "offset": 4,
+ "size": 1
+ },
+ "TXFFLSH": {
+ "description": "TxFIFO flush",
+ "offset": 5,
+ "size": 1
+ },
+ "TXFNUM": {
+ "description": "TxFIFO number",
+ "offset": 6,
+ "size": 5
+ },
+ "DMAREQ": {
+ "description": "DMA request signal",
+ "offset": 30,
+ "size": 1,
+ "access": "read-only"
+ },
+ "AHBIDL": {
+ "description": "AHB master idle",
+ "offset": 31,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "OTG_HS_GINTSTS": {
+ "description": "OTG_HS core interrupt register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 67108896,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CMOD": {
+ "description": "Current mode of operation",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ },
+ "MMIS": {
+ "description": "Mode mismatch interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "OTGINT": {
+ "description": "OTG interrupt",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SOF": {
+ "description": "Start of frame",
+ "offset": 3,
+ "size": 1
+ },
+ "RXFLVL": {
+ "description": "RxFIFO nonempty",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NPTXFE": {
+ "description": "Nonperiodic TxFIFO empty",
+ "offset": 5,
+ "size": 1,
+ "access": "read-only"
+ },
+ "GINAKEFF": {
+ "description": "Global IN nonperiodic NAK\n effective",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "BOUTNAKEFF": {
+ "description": "Global OUT NAK effective",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ESUSP": {
+ "description": "Early suspend",
+ "offset": 10,
+ "size": 1
+ },
+ "USBSUSP": {
+ "description": "USB suspend",
+ "offset": 11,
+ "size": 1
+ },
+ "USBRST": {
+ "description": "USB reset",
+ "offset": 12,
+ "size": 1
+ },
+ "ENUMDNE": {
+ "description": "Enumeration done",
+ "offset": 13,
+ "size": 1
+ },
+ "ISOODRP": {
+ "description": "Isochronous OUT packet dropped\n interrupt",
+ "offset": 14,
+ "size": 1
+ },
+ "EOPF": {
+ "description": "End of periodic frame\n interrupt",
+ "offset": 15,
+ "size": 1
+ },
+ "IEPINT": {
+ "description": "IN endpoint interrupt",
+ "offset": 18,
+ "size": 1,
+ "access": "read-only"
+ },
+ "OEPINT": {
+ "description": "OUT endpoint interrupt",
+ "offset": 19,
+ "size": 1,
+ "access": "read-only"
+ },
+ "IISOIXFR": {
+ "description": "Incomplete isochronous IN\n transfer",
+ "offset": 20,
+ "size": 1
+ },
+ "PXFR_INCOMPISOOUT": {
+ "description": "Incomplete periodic\n transfer",
+ "offset": 21,
+ "size": 1
+ },
+ "DATAFSUSP": {
+ "description": "Data fetch suspended",
+ "offset": 22,
+ "size": 1
+ },
+ "HPRTINT": {
+ "description": "Host port interrupt",
+ "offset": 24,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HCINT": {
+ "description": "Host channels interrupt",
+ "offset": 25,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PTXFE": {
+ "description": "Periodic TxFIFO empty",
+ "offset": 26,
+ "size": 1,
+ "access": "read-only"
+ },
+ "CIDSCHG": {
+ "description": "Connector ID status change",
+ "offset": 28,
+ "size": 1
+ },
+ "DISCINT": {
+ "description": "Disconnect detected\n interrupt",
+ "offset": 29,
+ "size": 1
+ },
+ "SRQINT": {
+ "description": "Session request/new session detected\n interrupt",
+ "offset": 30,
+ "size": 1
+ },
+ "WKUINT": {
+ "description": "Resume/remote wakeup detected\n interrupt",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_GINTMSK": {
+ "description": "OTG_HS interrupt mask register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MMISM": {
+ "description": "Mode mismatch interrupt\n mask",
+ "offset": 1,
+ "size": 1
+ },
+ "OTGINT": {
+ "description": "OTG interrupt mask",
+ "offset": 2,
+ "size": 1
+ },
+ "SOFM": {
+ "description": "Start of frame mask",
+ "offset": 3,
+ "size": 1
+ },
+ "RXFLVLM": {
+ "description": "Receive FIFO nonempty mask",
+ "offset": 4,
+ "size": 1
+ },
+ "NPTXFEM": {
+ "description": "Nonperiodic TxFIFO empty\n mask",
+ "offset": 5,
+ "size": 1
+ },
+ "GINAKEFFM": {
+ "description": "Global nonperiodic IN NAK effective\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "GONAKEFFM": {
+ "description": "Global OUT NAK effective\n mask",
+ "offset": 7,
+ "size": 1
+ },
+ "ESUSPM": {
+ "description": "Early suspend mask",
+ "offset": 10,
+ "size": 1
+ },
+ "USBSUSPM": {
+ "description": "USB suspend mask",
+ "offset": 11,
+ "size": 1
+ },
+ "USBRST": {
+ "description": "USB reset mask",
+ "offset": 12,
+ "size": 1
+ },
+ "ENUMDNEM": {
+ "description": "Enumeration done mask",
+ "offset": 13,
+ "size": 1
+ },
+ "ISOODRPM": {
+ "description": "Isochronous OUT packet dropped interrupt\n mask",
+ "offset": 14,
+ "size": 1
+ },
+ "EOPFM": {
+ "description": "End of periodic frame interrupt\n mask",
+ "offset": 15,
+ "size": 1
+ },
+ "EPMISM": {
+ "description": "Endpoint mismatch interrupt\n mask",
+ "offset": 17,
+ "size": 1
+ },
+ "IEPINT": {
+ "description": "IN endpoints interrupt\n mask",
+ "offset": 18,
+ "size": 1
+ },
+ "OEPINT": {
+ "description": "OUT endpoints interrupt\n mask",
+ "offset": 19,
+ "size": 1
+ },
+ "IISOIXFRM": {
+ "description": "Incomplete isochronous IN transfer\n mask",
+ "offset": 20,
+ "size": 1
+ },
+ "PXFRM_IISOOXFRM": {
+ "description": "Incomplete periodic transfer\n mask",
+ "offset": 21,
+ "size": 1
+ },
+ "FSUSPM": {
+ "description": "Data fetch suspended mask",
+ "offset": 22,
+ "size": 1
+ },
+ "PRTIM": {
+ "description": "Host port interrupt mask",
+ "offset": 24,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HCIM": {
+ "description": "Host channels interrupt\n mask",
+ "offset": 25,
+ "size": 1
+ },
+ "PTXFEM": {
+ "description": "Periodic TxFIFO empty mask",
+ "offset": 26,
+ "size": 1
+ },
+ "CIDSCHGM": {
+ "description": "Connector ID status change\n mask",
+ "offset": 28,
+ "size": 1
+ },
+ "DISCINT": {
+ "description": "Disconnect detected interrupt\n mask",
+ "offset": 29,
+ "size": 1
+ },
+ "SRQIM": {
+ "description": "Session request/new session detected\n interrupt mask",
+ "offset": 30,
+ "size": 1
+ },
+ "WUIM": {
+ "description": "Resume/remote wakeup detected interrupt\n mask",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_GRXSTSR_Host": {
+ "description": "OTG_HS Receive status debug read register\n (host mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CHNUM": {
+ "description": "Channel number",
+ "offset": 0,
+ "size": 4
+ },
+ "BCNT": {
+ "description": "Byte count",
+ "offset": 4,
+ "size": 11
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 15,
+ "size": 2
+ },
+ "PKTSTS": {
+ "description": "Packet status",
+ "offset": 17,
+ "size": 4
+ }
+ }
+ }
+ },
+ "OTG_HS_GRXSTSP_Host": {
+ "description": "OTG_HS status read and pop register (host\n mode)",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CHNUM": {
+ "description": "Channel number",
+ "offset": 0,
+ "size": 4
+ },
+ "BCNT": {
+ "description": "Byte count",
+ "offset": 4,
+ "size": 11
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 15,
+ "size": 2
+ },
+ "PKTSTS": {
+ "description": "Packet status",
+ "offset": 17,
+ "size": 4
+ }
+ }
+ }
+ },
+ "OTG_HS_GRXFSIZ": {
+ "description": "OTG_HS Receive FIFO size\n register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 512,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RXFD": {
+ "description": "RxFIFO depth",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_GNPTXFSIZ_Host": {
+ "description": "OTG_HS nonperiodic transmit FIFO size\n register (host mode)",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 512,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NPTXFSA": {
+ "description": "Nonperiodic transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "NPTXFD": {
+ "description": "Nonperiodic TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_TX0FSIZ_Peripheral": {
+ "description": "Endpoint 0 transmit FIFO size (peripheral\n mode)",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 512,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TX0FSA": {
+ "description": "Endpoint 0 transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "TX0FD": {
+ "description": "Endpoint 0 TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_GNPTXSTS": {
+ "description": "OTG_HS nonperiodic transmit FIFO/queue\n status register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 524800,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "NPTXFSAV": {
+ "description": "Nonperiodic TxFIFO space\n available",
+ "offset": 0,
+ "size": 16
+ },
+ "NPTQXSAV": {
+ "description": "Nonperiodic transmit request queue space\n available",
+ "offset": 16,
+ "size": 8
+ },
+ "NPTXQTOP": {
+ "description": "Top of the nonperiodic transmit request\n queue",
+ "offset": 24,
+ "size": 7
+ }
+ }
+ }
+ },
+ "OTG_HS_GCCFG": {
+ "description": "OTG_HS general core configuration\n register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PWRDWN": {
+ "description": "Power down",
+ "offset": 16,
+ "size": 1
+ },
+ "I2CPADEN": {
+ "description": "Enable I2C bus connection for the\n external I2C PHY interface",
+ "offset": 17,
+ "size": 1
+ },
+ "VBUSASEN": {
+ "description": "Enable the VBUS sensing\n device",
+ "offset": 18,
+ "size": 1
+ },
+ "VBUSBSEN": {
+ "description": "Enable the VBUS sensing\n device",
+ "offset": 19,
+ "size": 1
+ },
+ "SOFOUTEN": {
+ "description": "SOF output enable",
+ "offset": 20,
+ "size": 1
+ },
+ "NOVBUSSENS": {
+ "description": "VBUS sensing disable\n option",
+ "offset": 21,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OTG_HS_CID": {
+ "description": "OTG_HS core ID register",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 4608,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRODUCT_ID": {
+ "description": "Product ID field",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OTG_HS_HPTXFSIZ": {
+ "description": "OTG_HS Host periodic transmit FIFO size\n register",
+ "offset": 256,
+ "size": 32,
+ "reset_value": 33555968,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PTXSA": {
+ "description": "Host periodic TxFIFO start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "PTXFD": {
+ "description": "Host periodic TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPTXF1": {
+ "description": "OTG_HS device IN endpoint transmit FIFO size\n register",
+ "offset": 260,
+ "size": 32,
+ "reset_value": 33555456,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INEPTXSA": {
+ "description": "IN endpoint FIFOx transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "INEPTXFD": {
+ "description": "IN endpoint TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPTXF2": {
+ "description": "OTG_HS device IN endpoint transmit FIFO size\n register",
+ "offset": 264,
+ "size": 32,
+ "reset_value": 33555456,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INEPTXSA": {
+ "description": "IN endpoint FIFOx transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "INEPTXFD": {
+ "description": "IN endpoint TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPTXF3": {
+ "description": "OTG_HS device IN endpoint transmit FIFO size\n register",
+ "offset": 284,
+ "size": 32,
+ "reset_value": 33555456,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INEPTXSA": {
+ "description": "IN endpoint FIFOx transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "INEPTXFD": {
+ "description": "IN endpoint TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPTXF4": {
+ "description": "OTG_HS device IN endpoint transmit FIFO size\n register",
+ "offset": 288,
+ "size": 32,
+ "reset_value": 33555456,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INEPTXSA": {
+ "description": "IN endpoint FIFOx transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "INEPTXFD": {
+ "description": "IN endpoint TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPTXF5": {
+ "description": "OTG_HS device IN endpoint transmit FIFO size\n register",
+ "offset": 292,
+ "size": 32,
+ "reset_value": 33555456,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INEPTXSA": {
+ "description": "IN endpoint FIFOx transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "INEPTXFD": {
+ "description": "IN endpoint TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPTXF6": {
+ "description": "OTG_HS device IN endpoint transmit FIFO size\n register",
+ "offset": 296,
+ "size": 32,
+ "reset_value": 33555456,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INEPTXSA": {
+ "description": "IN endpoint FIFOx transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "INEPTXFD": {
+ "description": "IN endpoint TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_DIEPTXF7": {
+ "description": "OTG_HS device IN endpoint transmit FIFO size\n register",
+ "offset": 300,
+ "size": 32,
+ "reset_value": 33555456,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INEPTXSA": {
+ "description": "IN endpoint FIFOx transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "INEPTXFD": {
+ "description": "IN endpoint TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OTG_HS_GRXSTSR_Peripheral": {
+ "description": "OTG_HS Receive status debug read register\n (peripheral mode mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 0,
+ "size": 4
+ },
+ "BCNT": {
+ "description": "Byte count",
+ "offset": 4,
+ "size": 11
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 15,
+ "size": 2
+ },
+ "PKTSTS": {
+ "description": "Packet status",
+ "offset": 17,
+ "size": 4
+ },
+ "FRMNUM": {
+ "description": "Frame number",
+ "offset": 21,
+ "size": 4
+ }
+ }
+ }
+ },
+ "OTG_HS_GRXSTSP_Peripheral": {
+ "description": "OTG_HS status read and pop register\n (peripheral mode)",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 0,
+ "size": 4
+ },
+ "BCNT": {
+ "description": "Byte count",
+ "offset": 4,
+ "size": 11
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 15,
+ "size": 2
+ },
+ "PKTSTS": {
+ "description": "Packet status",
+ "offset": 17,
+ "size": 4
+ },
+ "FRMNUM": {
+ "description": "Frame number",
+ "offset": 21,
+ "size": 4
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "EXTI": {
+ "description": "External interrupt/event\n controller",
+ "children": {
+ "registers": {
+ "IMR": {
+ "description": "Interrupt mask register\n (EXTI_IMR)",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MR0": {
+ "description": "Interrupt Mask on line 0",
+ "offset": 0,
+ "size": 1
+ },
+ "MR1": {
+ "description": "Interrupt Mask on line 1",
+ "offset": 1,
+ "size": 1
+ },
+ "MR2": {
+ "description": "Interrupt Mask on line 2",
+ "offset": 2,
+ "size": 1
+ },
+ "MR3": {
+ "description": "Interrupt Mask on line 3",
+ "offset": 3,
+ "size": 1
+ },
+ "MR4": {
+ "description": "Interrupt Mask on line 4",
+ "offset": 4,
+ "size": 1
+ },
+ "MR5": {
+ "description": "Interrupt Mask on line 5",
+ "offset": 5,
+ "size": 1
+ },
+ "MR6": {
+ "description": "Interrupt Mask on line 6",
+ "offset": 6,
+ "size": 1
+ },
+ "MR7": {
+ "description": "Interrupt Mask on line 7",
+ "offset": 7,
+ "size": 1
+ },
+ "MR8": {
+ "description": "Interrupt Mask on line 8",
+ "offset": 8,
+ "size": 1
+ },
+ "MR9": {
+ "description": "Interrupt Mask on line 9",
+ "offset": 9,
+ "size": 1
+ },
+ "MR10": {
+ "description": "Interrupt Mask on line 10",
+ "offset": 10,
+ "size": 1
+ },
+ "MR11": {
+ "description": "Interrupt Mask on line 11",
+ "offset": 11,
+ "size": 1
+ },
+ "MR12": {
+ "description": "Interrupt Mask on line 12",
+ "offset": 12,
+ "size": 1
+ },
+ "MR13": {
+ "description": "Interrupt Mask on line 13",
+ "offset": 13,
+ "size": 1
+ },
+ "MR14": {
+ "description": "Interrupt Mask on line 14",
+ "offset": 14,
+ "size": 1
+ },
+ "MR15": {
+ "description": "Interrupt Mask on line 15",
+ "offset": 15,
+ "size": 1
+ },
+ "MR16": {
+ "description": "Interrupt Mask on line 16",
+ "offset": 16,
+ "size": 1
+ },
+ "MR17": {
+ "description": "Interrupt Mask on line 17",
+ "offset": 17,
+ "size": 1
+ },
+ "MR18": {
+ "description": "Interrupt Mask on line 18",
+ "offset": 18,
+ "size": 1
+ },
+ "MR19": {
+ "description": "Interrupt Mask on line 19",
+ "offset": 19,
+ "size": 1
+ },
+ "MR20": {
+ "description": "Interrupt Mask on line 20",
+ "offset": 20,
+ "size": 1
+ },
+ "MR21": {
+ "description": "Interrupt Mask on line 21",
+ "offset": 21,
+ "size": 1
+ },
+ "MR22": {
+ "description": "Interrupt Mask on line 22",
+ "offset": 22,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EMR": {
+ "description": "Event mask register (EXTI_EMR)",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MR0": {
+ "description": "Event Mask on line 0",
+ "offset": 0,
+ "size": 1
+ },
+ "MR1": {
+ "description": "Event Mask on line 1",
+ "offset": 1,
+ "size": 1
+ },
+ "MR2": {
+ "description": "Event Mask on line 2",
+ "offset": 2,
+ "size": 1
+ },
+ "MR3": {
+ "description": "Event Mask on line 3",
+ "offset": 3,
+ "size": 1
+ },
+ "MR4": {
+ "description": "Event Mask on line 4",
+ "offset": 4,
+ "size": 1
+ },
+ "MR5": {
+ "description": "Event Mask on line 5",
+ "offset": 5,
+ "size": 1
+ },
+ "MR6": {
+ "description": "Event Mask on line 6",
+ "offset": 6,
+ "size": 1
+ },
+ "MR7": {
+ "description": "Event Mask on line 7",
+ "offset": 7,
+ "size": 1
+ },
+ "MR8": {
+ "description": "Event Mask on line 8",
+ "offset": 8,
+ "size": 1
+ },
+ "MR9": {
+ "description": "Event Mask on line 9",
+ "offset": 9,
+ "size": 1
+ },
+ "MR10": {
+ "description": "Event Mask on line 10",
+ "offset": 10,
+ "size": 1
+ },
+ "MR11": {
+ "description": "Event Mask on line 11",
+ "offset": 11,
+ "size": 1
+ },
+ "MR12": {
+ "description": "Event Mask on line 12",
+ "offset": 12,
+ "size": 1
+ },
+ "MR13": {
+ "description": "Event Mask on line 13",
+ "offset": 13,
+ "size": 1
+ },
+ "MR14": {
+ "description": "Event Mask on line 14",
+ "offset": 14,
+ "size": 1
+ },
+ "MR15": {
+ "description": "Event Mask on line 15",
+ "offset": 15,
+ "size": 1
+ },
+ "MR16": {
+ "description": "Event Mask on line 16",
+ "offset": 16,
+ "size": 1
+ },
+ "MR17": {
+ "description": "Event Mask on line 17",
+ "offset": 17,
+ "size": 1
+ },
+ "MR18": {
+ "description": "Event Mask on line 18",
+ "offset": 18,
+ "size": 1
+ },
+ "MR19": {
+ "description": "Event Mask on line 19",
+ "offset": 19,
+ "size": 1
+ },
+ "MR20": {
+ "description": "Event Mask on line 20",
+ "offset": 20,
+ "size": 1
+ },
+ "MR21": {
+ "description": "Event Mask on line 21",
+ "offset": 21,
+ "size": 1
+ },
+ "MR22": {
+ "description": "Event Mask on line 22",
+ "offset": 22,
+ "size": 1
+ }
+ }
+ }
+ },
+ "RTSR": {
+ "description": "Rising Trigger selection register\n (EXTI_RTSR)",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TR0": {
+ "description": "Rising trigger event configuration of\n line 0",
+ "offset": 0,
+ "size": 1
+ },
+ "TR1": {
+ "description": "Rising trigger event configuration of\n line 1",
+ "offset": 1,
+ "size": 1
+ },
+ "TR2": {
+ "description": "Rising trigger event configuration of\n line 2",
+ "offset": 2,
+ "size": 1
+ },
+ "TR3": {
+ "description": "Rising trigger event configuration of\n line 3",
+ "offset": 3,
+ "size": 1
+ },
+ "TR4": {
+ "description": "Rising trigger event configuration of\n line 4",
+ "offset": 4,
+ "size": 1
+ },
+ "TR5": {
+ "description": "Rising trigger event configuration of\n line 5",
+ "offset": 5,
+ "size": 1
+ },
+ "TR6": {
+ "description": "Rising trigger event configuration of\n line 6",
+ "offset": 6,
+ "size": 1
+ },
+ "TR7": {
+ "description": "Rising trigger event configuration of\n line 7",
+ "offset": 7,
+ "size": 1
+ },
+ "TR8": {
+ "description": "Rising trigger event configuration of\n line 8",
+ "offset": 8,
+ "size": 1
+ },
+ "TR9": {
+ "description": "Rising trigger event configuration of\n line 9",
+ "offset": 9,
+ "size": 1
+ },
+ "TR10": {
+ "description": "Rising trigger event configuration of\n line 10",
+ "offset": 10,
+ "size": 1
+ },
+ "TR11": {
+ "description": "Rising trigger event configuration of\n line 11",
+ "offset": 11,
+ "size": 1
+ },
+ "TR12": {
+ "description": "Rising trigger event configuration of\n line 12",
+ "offset": 12,
+ "size": 1
+ },
+ "TR13": {
+ "description": "Rising trigger event configuration of\n line 13",
+ "offset": 13,
+ "size": 1
+ },
+ "TR14": {
+ "description": "Rising trigger event configuration of\n line 14",
+ "offset": 14,
+ "size": 1
+ },
+ "TR15": {
+ "description": "Rising trigger event configuration of\n line 15",
+ "offset": 15,
+ "size": 1
+ },
+ "TR16": {
+ "description": "Rising trigger event configuration of\n line 16",
+ "offset": 16,
+ "size": 1
+ },
+ "TR17": {
+ "description": "Rising trigger event configuration of\n line 17",
+ "offset": 17,
+ "size": 1
+ },
+ "TR18": {
+ "description": "Rising trigger event configuration of\n line 18",
+ "offset": 18,
+ "size": 1
+ },
+ "TR19": {
+ "description": "Rising trigger event configuration of\n line 19",
+ "offset": 19,
+ "size": 1
+ },
+ "TR20": {
+ "description": "Rising trigger event configuration of\n line 20",
+ "offset": 20,
+ "size": 1
+ },
+ "TR21": {
+ "description": "Rising trigger event configuration of\n line 21",
+ "offset": 21,
+ "size": 1
+ },
+ "TR22": {
+ "description": "Rising trigger event configuration of\n line 22",
+ "offset": 22,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FTSR": {
+ "description": "Falling Trigger selection register\n (EXTI_FTSR)",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TR0": {
+ "description": "Falling trigger event configuration of\n line 0",
+ "offset": 0,
+ "size": 1
+ },
+ "TR1": {
+ "description": "Falling trigger event configuration of\n line 1",
+ "offset": 1,
+ "size": 1
+ },
+ "TR2": {
+ "description": "Falling trigger event configuration of\n line 2",
+ "offset": 2,
+ "size": 1
+ },
+ "TR3": {
+ "description": "Falling trigger event configuration of\n line 3",
+ "offset": 3,
+ "size": 1
+ },
+ "TR4": {
+ "description": "Falling trigger event configuration of\n line 4",
+ "offset": 4,
+ "size": 1
+ },
+ "TR5": {
+ "description": "Falling trigger event configuration of\n line 5",
+ "offset": 5,
+ "size": 1
+ },
+ "TR6": {
+ "description": "Falling trigger event configuration of\n line 6",
+ "offset": 6,
+ "size": 1
+ },
+ "TR7": {
+ "description": "Falling trigger event configuration of\n line 7",
+ "offset": 7,
+ "size": 1
+ },
+ "TR8": {
+ "description": "Falling trigger event configuration of\n line 8",
+ "offset": 8,
+ "size": 1
+ },
+ "TR9": {
+ "description": "Falling trigger event configuration of\n line 9",
+ "offset": 9,
+ "size": 1
+ },
+ "TR10": {
+ "description": "Falling trigger event configuration of\n line 10",
+ "offset": 10,
+ "size": 1
+ },
+ "TR11": {
+ "description": "Falling trigger event configuration of\n line 11",
+ "offset": 11,
+ "size": 1
+ },
+ "TR12": {
+ "description": "Falling trigger event configuration of\n line 12",
+ "offset": 12,
+ "size": 1
+ },
+ "TR13": {
+ "description": "Falling trigger event configuration of\n line 13",
+ "offset": 13,
+ "size": 1
+ },
+ "TR14": {
+ "description": "Falling trigger event configuration of\n line 14",
+ "offset": 14,
+ "size": 1
+ },
+ "TR15": {
+ "description": "Falling trigger event configuration of\n line 15",
+ "offset": 15,
+ "size": 1
+ },
+ "TR16": {
+ "description": "Falling trigger event configuration of\n line 16",
+ "offset": 16,
+ "size": 1
+ },
+ "TR17": {
+ "description": "Falling trigger event configuration of\n line 17",
+ "offset": 17,
+ "size": 1
+ },
+ "TR18": {
+ "description": "Falling trigger event configuration of\n line 18",
+ "offset": 18,
+ "size": 1
+ },
+ "TR19": {
+ "description": "Falling trigger event configuration of\n line 19",
+ "offset": 19,
+ "size": 1
+ },
+ "TR20": {
+ "description": "Falling trigger event configuration of\n line 20",
+ "offset": 20,
+ "size": 1
+ },
+ "TR21": {
+ "description": "Falling trigger event configuration of\n line 21",
+ "offset": 21,
+ "size": 1
+ },
+ "TR22": {
+ "description": "Falling trigger event configuration of\n line 22",
+ "offset": 22,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SWIER": {
+ "description": "Software interrupt event register\n (EXTI_SWIER)",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SWIER0": {
+ "description": "Software Interrupt on line\n 0",
+ "offset": 0,
+ "size": 1
+ },
+ "SWIER1": {
+ "description": "Software Interrupt on line\n 1",
+ "offset": 1,
+ "size": 1
+ },
+ "SWIER2": {
+ "description": "Software Interrupt on line\n 2",
+ "offset": 2,
+ "size": 1
+ },
+ "SWIER3": {
+ "description": "Software Interrupt on line\n 3",
+ "offset": 3,
+ "size": 1
+ },
+ "SWIER4": {
+ "description": "Software Interrupt on line\n 4",
+ "offset": 4,
+ "size": 1
+ },
+ "SWIER5": {
+ "description": "Software Interrupt on line\n 5",
+ "offset": 5,
+ "size": 1
+ },
+ "SWIER6": {
+ "description": "Software Interrupt on line\n 6",
+ "offset": 6,
+ "size": 1
+ },
+ "SWIER7": {
+ "description": "Software Interrupt on line\n 7",
+ "offset": 7,
+ "size": 1
+ },
+ "SWIER8": {
+ "description": "Software Interrupt on line\n 8",
+ "offset": 8,
+ "size": 1
+ },
+ "SWIER9": {
+ "description": "Software Interrupt on line\n 9",
+ "offset": 9,
+ "size": 1
+ },
+ "SWIER10": {
+ "description": "Software Interrupt on line\n 10",
+ "offset": 10,
+ "size": 1
+ },
+ "SWIER11": {
+ "description": "Software Interrupt on line\n 11",
+ "offset": 11,
+ "size": 1
+ },
+ "SWIER12": {
+ "description": "Software Interrupt on line\n 12",
+ "offset": 12,
+ "size": 1
+ },
+ "SWIER13": {
+ "description": "Software Interrupt on line\n 13",
+ "offset": 13,
+ "size": 1
+ },
+ "SWIER14": {
+ "description": "Software Interrupt on line\n 14",
+ "offset": 14,
+ "size": 1
+ },
+ "SWIER15": {
+ "description": "Software Interrupt on line\n 15",
+ "offset": 15,
+ "size": 1
+ },
+ "SWIER16": {
+ "description": "Software Interrupt on line\n 16",
+ "offset": 16,
+ "size": 1
+ },
+ "SWIER17": {
+ "description": "Software Interrupt on line\n 17",
+ "offset": 17,
+ "size": 1
+ },
+ "SWIER18": {
+ "description": "Software Interrupt on line\n 18",
+ "offset": 18,
+ "size": 1
+ },
+ "SWIER19": {
+ "description": "Software Interrupt on line\n 19",
+ "offset": 19,
+ "size": 1
+ },
+ "SWIER20": {
+ "description": "Software Interrupt on line\n 20",
+ "offset": 20,
+ "size": 1
+ },
+ "SWIER21": {
+ "description": "Software Interrupt on line\n 21",
+ "offset": 21,
+ "size": 1
+ },
+ "SWIER22": {
+ "description": "Software Interrupt on line\n 22",
+ "offset": 22,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PR": {
+ "description": "Pending register (EXTI_PR)",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PR0": {
+ "description": "Pending bit 0",
+ "offset": 0,
+ "size": 1
+ },
+ "PR1": {
+ "description": "Pending bit 1",
+ "offset": 1,
+ "size": 1
+ },
+ "PR2": {
+ "description": "Pending bit 2",
+ "offset": 2,
+ "size": 1
+ },
+ "PR3": {
+ "description": "Pending bit 3",
+ "offset": 3,
+ "size": 1
+ },
+ "PR4": {
+ "description": "Pending bit 4",
+ "offset": 4,
+ "size": 1
+ },
+ "PR5": {
+ "description": "Pending bit 5",
+ "offset": 5,
+ "size": 1
+ },
+ "PR6": {
+ "description": "Pending bit 6",
+ "offset": 6,
+ "size": 1
+ },
+ "PR7": {
+ "description": "Pending bit 7",
+ "offset": 7,
+ "size": 1
+ },
+ "PR8": {
+ "description": "Pending bit 8",
+ "offset": 8,
+ "size": 1
+ },
+ "PR9": {
+ "description": "Pending bit 9",
+ "offset": 9,
+ "size": 1
+ },
+ "PR10": {
+ "description": "Pending bit 10",
+ "offset": 10,
+ "size": 1
+ },
+ "PR11": {
+ "description": "Pending bit 11",
+ "offset": 11,
+ "size": 1
+ },
+ "PR12": {
+ "description": "Pending bit 12",
+ "offset": 12,
+ "size": 1
+ },
+ "PR13": {
+ "description": "Pending bit 13",
+ "offset": 13,
+ "size": 1
+ },
+ "PR14": {
+ "description": "Pending bit 14",
+ "offset": 14,
+ "size": 1
+ },
+ "PR15": {
+ "description": "Pending bit 15",
+ "offset": 15,
+ "size": 1
+ },
+ "PR16": {
+ "description": "Pending bit 16",
+ "offset": 16,
+ "size": 1
+ },
+ "PR17": {
+ "description": "Pending bit 17",
+ "offset": 17,
+ "size": 1
+ },
+ "PR18": {
+ "description": "Pending bit 18",
+ "offset": 18,
+ "size": 1
+ },
+ "PR19": {
+ "description": "Pending bit 19",
+ "offset": 19,
+ "size": 1
+ },
+ "PR20": {
+ "description": "Pending bit 20",
+ "offset": 20,
+ "size": 1
+ },
+ "PR21": {
+ "description": "Pending bit 21",
+ "offset": 21,
+ "size": 1
+ },
+ "PR22": {
+ "description": "Pending bit 22",
+ "offset": 22,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "USART6": {
+ "description": "Universal synchronous asynchronous receiver\n transmitter",
+ "children": {
+ "registers": {
+ "SR": {
+ "description": "Status register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 12582912,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CTS": {
+ "description": "CTS flag",
+ "offset": 9,
+ "size": 1
+ },
+ "LBD": {
+ "description": "LIN break detection flag",
+ "offset": 8,
+ "size": 1
+ },
+ "TXE": {
+ "description": "Transmit data register\n empty",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TC": {
+ "description": "Transmission complete",
+ "offset": 6,
+ "size": 1
+ },
+ "RXNE": {
+ "description": "Read data register not\n empty",
+ "offset": 5,
+ "size": 1
+ },
+ "IDLE": {
+ "description": "IDLE line detected",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ORE": {
+ "description": "Overrun error",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NF": {
+ "description": "Noise detected flag",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "FE": {
+ "description": "Framing error",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PE": {
+ "description": "Parity error",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "DR": {
+ "description": "Data register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DR": {
+ "description": "Data value",
+ "offset": 0,
+ "size": 9
+ }
+ }
+ }
+ },
+ "BRR": {
+ "description": "Baud rate register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DIV_Mantissa": {
+ "description": "mantissa of USARTDIV",
+ "offset": 4,
+ "size": 12
+ },
+ "DIV_Fraction": {
+ "description": "fraction of USARTDIV",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "CR1": {
+ "description": "Control register 1",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OVER8": {
+ "description": "Oversampling mode",
+ "offset": 15,
+ "size": 1
+ },
+ "UE": {
+ "description": "USART enable",
+ "offset": 13,
+ "size": 1
+ },
+ "M": {
+ "description": "Word length",
+ "offset": 12,
+ "size": 1
+ },
+ "WAKE": {
+ "description": "Wakeup method",
+ "offset": 11,
+ "size": 1
+ },
+ "PCE": {
+ "description": "Parity control enable",
+ "offset": 10,
+ "size": 1
+ },
+ "PS": {
+ "description": "Parity selection",
+ "offset": 9,
+ "size": 1
+ },
+ "PEIE": {
+ "description": "PE interrupt enable",
+ "offset": 8,
+ "size": 1
+ },
+ "TXEIE": {
+ "description": "TXE interrupt enable",
+ "offset": 7,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transmission complete interrupt\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "RXNEIE": {
+ "description": "RXNE interrupt enable",
+ "offset": 5,
+ "size": 1
+ },
+ "IDLEIE": {
+ "description": "IDLE interrupt enable",
+ "offset": 4,
+ "size": 1
+ },
+ "TE": {
+ "description": "Transmitter enable",
+ "offset": 3,
+ "size": 1
+ },
+ "RE": {
+ "description": "Receiver enable",
+ "offset": 2,
+ "size": 1
+ },
+ "RWU": {
+ "description": "Receiver wakeup",
+ "offset": 1,
+ "size": 1
+ },
+ "SBK": {
+ "description": "Send break",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "Control register 2",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LINEN": {
+ "description": "LIN mode enable",
+ "offset": 14,
+ "size": 1
+ },
+ "STOP": {
+ "description": "STOP bits",
+ "offset": 12,
+ "size": 2
+ },
+ "CLKEN": {
+ "description": "Clock enable",
+ "offset": 11,
+ "size": 1
+ },
+ "CPOL": {
+ "description": "Clock polarity",
+ "offset": 10,
+ "size": 1
+ },
+ "CPHA": {
+ "description": "Clock phase",
+ "offset": 9,
+ "size": 1
+ },
+ "LBCL": {
+ "description": "Last bit clock pulse",
+ "offset": 8,
+ "size": 1
+ },
+ "LBDIE": {
+ "description": "LIN break detection interrupt\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "LBDL": {
+ "description": "lin break detection length",
+ "offset": 5,
+ "size": 1
+ },
+ "ADD": {
+ "description": "Address of the USART node",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "CR3": {
+ "description": "Control register 3",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ONEBIT": {
+ "description": "One sample bit method\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "CTSIE": {
+ "description": "CTS interrupt enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CTSE": {
+ "description": "CTS enable",
+ "offset": 9,
+ "size": 1
+ },
+ "RTSE": {
+ "description": "RTS enable",
+ "offset": 8,
+ "size": 1
+ },
+ "DMAT": {
+ "description": "DMA enable transmitter",
+ "offset": 7,
+ "size": 1
+ },
+ "DMAR": {
+ "description": "DMA enable receiver",
+ "offset": 6,
+ "size": 1
+ },
+ "SCEN": {
+ "description": "Smartcard mode enable",
+ "offset": 5,
+ "size": 1
+ },
+ "NACK": {
+ "description": "Smartcard NACK enable",
+ "offset": 4,
+ "size": 1
+ },
+ "HDSEL": {
+ "description": "Half-duplex selection",
+ "offset": 3,
+ "size": 1
+ },
+ "IRLP": {
+ "description": "IrDA low-power",
+ "offset": 2,
+ "size": 1
+ },
+ "IREN": {
+ "description": "IrDA mode enable",
+ "offset": 1,
+ "size": 1
+ },
+ "EIE": {
+ "description": "Error interrupt enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "GTPR": {
+ "description": "Guard time and prescaler\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "GT": {
+ "description": "Guard time value",
+ "offset": 8,
+ "size": 8
+ },
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "FLASH": {
+ "description": "FLASH",
+ "children": {
+ "registers": {
+ "ACR": {
+ "description": "Flash access control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LATENCY": {
+ "description": "Latency",
+ "offset": 0,
+ "size": 3
+ },
+ "PRFTEN": {
+ "description": "Prefetch enable",
+ "offset": 8,
+ "size": 1
+ },
+ "ICEN": {
+ "description": "Instruction cache enable",
+ "offset": 9,
+ "size": 1
+ },
+ "DCEN": {
+ "description": "Data cache enable",
+ "offset": 10,
+ "size": 1
+ },
+ "ICRST": {
+ "description": "Instruction cache reset",
+ "offset": 11,
+ "size": 1,
+ "access": "write-only"
+ },
+ "DCRST": {
+ "description": "Data cache reset",
+ "offset": 12,
+ "size": 1
+ }
+ }
+ }
+ },
+ "KEYR": {
+ "description": "Flash key register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "KEY": {
+ "description": "FPEC key",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "OPTKEYR": {
+ "description": "Flash option key register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "OPTKEY": {
+ "description": "Option byte key",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "Status register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EOP": {
+ "description": "End of operation",
+ "offset": 0,
+ "size": 1
+ },
+ "OPERR": {
+ "description": "Operation error",
+ "offset": 1,
+ "size": 1
+ },
+ "WRPERR": {
+ "description": "Write protection error",
+ "offset": 4,
+ "size": 1
+ },
+ "PGAERR": {
+ "description": "Programming alignment\n error",
+ "offset": 5,
+ "size": 1
+ },
+ "PGPERR": {
+ "description": "Programming parallelism\n error",
+ "offset": 6,
+ "size": 1
+ },
+ "PGSERR": {
+ "description": "Programming sequence error",
+ "offset": 7,
+ "size": 1
+ },
+ "BSY": {
+ "description": "Busy",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "CR": {
+ "description": "Control register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 2147483648,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PG": {
+ "description": "Programming",
+ "offset": 0,
+ "size": 1
+ },
+ "SER": {
+ "description": "Sector Erase",
+ "offset": 1,
+ "size": 1
+ },
+ "MER": {
+ "description": "Mass Erase of sectors 0 to\n 11",
+ "offset": 2,
+ "size": 1
+ },
+ "SNB": {
+ "description": "Sector number",
+ "offset": 3,
+ "size": 5
+ },
+ "PSIZE": {
+ "description": "Program size",
+ "offset": 8,
+ "size": 2
+ },
+ "MER1": {
+ "description": "Mass Erase of sectors 12 to\n 23",
+ "offset": 15,
+ "size": 1
+ },
+ "STRT": {
+ "description": "Start",
+ "offset": 16,
+ "size": 1
+ },
+ "EOPIE": {
+ "description": "End of operation interrupt\n enable",
+ "offset": 24,
+ "size": 1
+ },
+ "ERRIE": {
+ "description": "Error interrupt enable",
+ "offset": 25,
+ "size": 1
+ },
+ "LOCK": {
+ "description": "Lock",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "OPTCR": {
+ "description": "Flash option control register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 268413677,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OPTLOCK": {
+ "description": "Option lock",
+ "offset": 0,
+ "size": 1
+ },
+ "OPTSTRT": {
+ "description": "Option start",
+ "offset": 1,
+ "size": 1
+ },
+ "BOR_LEV": {
+ "description": "BOR reset Level",
+ "offset": 2,
+ "size": 2
+ },
+ "WDG_SW": {
+ "description": "WDG_SW User option bytes",
+ "offset": 5,
+ "size": 1
+ },
+ "nRST_STOP": {
+ "description": "nRST_STOP User option\n bytes",
+ "offset": 6,
+ "size": 1
+ },
+ "nRST_STDBY": {
+ "description": "nRST_STDBY User option\n bytes",
+ "offset": 7,
+ "size": 1
+ },
+ "RDP": {
+ "description": "Read protect",
+ "offset": 8,
+ "size": 8
+ },
+ "nWRP": {
+ "description": "Not write protect",
+ "offset": 16,
+ "size": 12
+ }
+ }
+ }
+ },
+ "OPTCR1": {
+ "description": "Flash option control register\n 1",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 268369920,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "nWRP": {
+ "description": "Not write protect",
+ "offset": 16,
+ "size": 12
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "NVIC": {
+ "description": "Nested Vectored Interrupt\n Controller",
+ "children": {
+ "registers": {
+ "ISER0": {
+ "description": "Interrupt Set-Enable Register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SETENA": {
+ "description": "SETENA",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ISER1": {
+ "description": "Interrupt Set-Enable Register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SETENA": {
+ "description": "SETENA",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ISER2": {
+ "description": "Interrupt Set-Enable Register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SETENA": {
+ "description": "SETENA",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ICER0": {
+ "description": "Interrupt Clear-Enable\n Register",
+ "offset": 128,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CLRENA": {
+ "description": "CLRENA",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ICER1": {
+ "description": "Interrupt Clear-Enable\n Register",
+ "offset": 132,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CLRENA": {
+ "description": "CLRENA",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ICER2": {
+ "description": "Interrupt Clear-Enable\n Register",
+ "offset": 136,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CLRENA": {
+ "description": "CLRENA",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ISPR0": {
+ "description": "Interrupt Set-Pending Register",
+ "offset": 256,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SETPEND": {
+ "description": "SETPEND",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ISPR1": {
+ "description": "Interrupt Set-Pending Register",
+ "offset": 260,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SETPEND": {
+ "description": "SETPEND",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ISPR2": {
+ "description": "Interrupt Set-Pending Register",
+ "offset": 264,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SETPEND": {
+ "description": "SETPEND",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ICPR0": {
+ "description": "Interrupt Clear-Pending\n Register",
+ "offset": 384,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CLRPEND": {
+ "description": "CLRPEND",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ICPR1": {
+ "description": "Interrupt Clear-Pending\n Register",
+ "offset": 388,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CLRPEND": {
+ "description": "CLRPEND",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "ICPR2": {
+ "description": "Interrupt Clear-Pending\n Register",
+ "offset": 392,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CLRPEND": {
+ "description": "CLRPEND",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "IABR0": {
+ "description": "Interrupt Active Bit Register",
+ "offset": 512,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "ACTIVE": {
+ "description": "ACTIVE",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "IABR1": {
+ "description": "Interrupt Active Bit Register",
+ "offset": 516,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "ACTIVE": {
+ "description": "ACTIVE",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "IABR2": {
+ "description": "Interrupt Active Bit Register",
+ "offset": 520,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "ACTIVE": {
+ "description": "ACTIVE",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "IPR0": {
+ "description": "Interrupt Priority Register",
+ "offset": 768,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR1": {
+ "description": "Interrupt Priority Register",
+ "offset": 772,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR2": {
+ "description": "Interrupt Priority Register",
+ "offset": 776,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR3": {
+ "description": "Interrupt Priority Register",
+ "offset": 780,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR4": {
+ "description": "Interrupt Priority Register",
+ "offset": 784,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR5": {
+ "description": "Interrupt Priority Register",
+ "offset": 788,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR6": {
+ "description": "Interrupt Priority Register",
+ "offset": 792,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR7": {
+ "description": "Interrupt Priority Register",
+ "offset": 796,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR8": {
+ "description": "Interrupt Priority Register",
+ "offset": 800,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR9": {
+ "description": "Interrupt Priority Register",
+ "offset": 804,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR10": {
+ "description": "Interrupt Priority Register",
+ "offset": 808,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR11": {
+ "description": "Interrupt Priority Register",
+ "offset": 812,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR12": {
+ "description": "Interrupt Priority Register",
+ "offset": 816,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR13": {
+ "description": "Interrupt Priority Register",
+ "offset": 820,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR14": {
+ "description": "Interrupt Priority Register",
+ "offset": 824,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR15": {
+ "description": "Interrupt Priority Register",
+ "offset": 828,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR16": {
+ "description": "Interrupt Priority Register",
+ "offset": 832,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR17": {
+ "description": "Interrupt Priority Register",
+ "offset": 836,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR18": {
+ "description": "Interrupt Priority Register",
+ "offset": 840,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR19": {
+ "description": "Interrupt Priority Register",
+ "offset": 844,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ },
+ "IPR20": {
+ "description": "Interrupt Priority Register",
+ "offset": 848,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IPR_N0": {
+ "description": "IPR_N0",
+ "offset": 0,
+ "size": 8
+ },
+ "IPR_N1": {
+ "description": "IPR_N1",
+ "offset": 8,
+ "size": 8
+ },
+ "IPR_N2": {
+ "description": "IPR_N2",
+ "offset": 16,
+ "size": 8
+ },
+ "IPR_N3": {
+ "description": "IPR_N3",
+ "offset": 24,
+ "size": 8
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "Ethernet_MAC": {
+ "description": "Ethernet: media access control\n (MAC)",
+ "children": {
+ "registers": {
+ "MACCR": {
+ "description": "Ethernet MAC configuration\n register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 32768,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RE": {
+ "description": "RE",
+ "offset": 2,
+ "size": 1
+ },
+ "TE": {
+ "description": "TE",
+ "offset": 3,
+ "size": 1
+ },
+ "DC": {
+ "description": "DC",
+ "offset": 4,
+ "size": 1
+ },
+ "BL": {
+ "description": "BL",
+ "offset": 5,
+ "size": 2
+ },
+ "APCS": {
+ "description": "APCS",
+ "offset": 7,
+ "size": 1
+ },
+ "RD": {
+ "description": "RD",
+ "offset": 9,
+ "size": 1
+ },
+ "IPCO": {
+ "description": "IPCO",
+ "offset": 10,
+ "size": 1
+ },
+ "DM": {
+ "description": "DM",
+ "offset": 11,
+ "size": 1
+ },
+ "LM": {
+ "description": "LM",
+ "offset": 12,
+ "size": 1
+ },
+ "ROD": {
+ "description": "ROD",
+ "offset": 13,
+ "size": 1
+ },
+ "FES": {
+ "description": "FES",
+ "offset": 14,
+ "size": 1
+ },
+ "CSD": {
+ "description": "CSD",
+ "offset": 16,
+ "size": 1
+ },
+ "IFG": {
+ "description": "IFG",
+ "offset": 17,
+ "size": 3
+ },
+ "JD": {
+ "description": "JD",
+ "offset": 22,
+ "size": 1
+ },
+ "WD": {
+ "description": "WD",
+ "offset": 23,
+ "size": 1
+ },
+ "CSTF": {
+ "description": "CSTF",
+ "offset": 25,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MACFFR": {
+ "description": "Ethernet MAC frame filter\n register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PM": {
+ "description": "PM",
+ "offset": 0,
+ "size": 1
+ },
+ "HU": {
+ "description": "HU",
+ "offset": 1,
+ "size": 1
+ },
+ "HM": {
+ "description": "HM",
+ "offset": 2,
+ "size": 1
+ },
+ "DAIF": {
+ "description": "DAIF",
+ "offset": 3,
+ "size": 1
+ },
+ "RAM": {
+ "description": "RAM",
+ "offset": 4,
+ "size": 1
+ },
+ "BFD": {
+ "description": "BFD",
+ "offset": 5,
+ "size": 1
+ },
+ "PCF": {
+ "description": "PCF",
+ "offset": 6,
+ "size": 1
+ },
+ "SAIF": {
+ "description": "SAIF",
+ "offset": 7,
+ "size": 1
+ },
+ "SAF": {
+ "description": "SAF",
+ "offset": 8,
+ "size": 1
+ },
+ "HPF": {
+ "description": "HPF",
+ "offset": 9,
+ "size": 1
+ },
+ "RA": {
+ "description": "RA",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MACHTHR": {
+ "description": "Ethernet MAC hash table high\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "HTH": {
+ "description": "HTH",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "MACHTLR": {
+ "description": "Ethernet MAC hash table low\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "HTL": {
+ "description": "HTL",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "MACMIIAR": {
+ "description": "Ethernet MAC MII address\n register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MB": {
+ "description": "MB",
+ "offset": 0,
+ "size": 1
+ },
+ "MW": {
+ "description": "MW",
+ "offset": 1,
+ "size": 1
+ },
+ "CR": {
+ "description": "CR",
+ "offset": 2,
+ "size": 3
+ },
+ "MR": {
+ "description": "MR",
+ "offset": 6,
+ "size": 5
+ },
+ "PA": {
+ "description": "PA",
+ "offset": 11,
+ "size": 5
+ }
+ }
+ }
+ },
+ "MACMIIDR": {
+ "description": "Ethernet MAC MII data register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TD": {
+ "description": "TD",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "MACFCR": {
+ "description": "Ethernet MAC flow control\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FCB": {
+ "description": "FCB",
+ "offset": 0,
+ "size": 1
+ },
+ "TFCE": {
+ "description": "TFCE",
+ "offset": 1,
+ "size": 1
+ },
+ "RFCE": {
+ "description": "RFCE",
+ "offset": 2,
+ "size": 1
+ },
+ "UPFD": {
+ "description": "UPFD",
+ "offset": 3,
+ "size": 1
+ },
+ "PLT": {
+ "description": "PLT",
+ "offset": 4,
+ "size": 2
+ },
+ "ZQPD": {
+ "description": "ZQPD",
+ "offset": 7,
+ "size": 1
+ },
+ "PT": {
+ "description": "PT",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "MACVLANTR": {
+ "description": "Ethernet MAC VLAN tag register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "VLANTI": {
+ "description": "VLANTI",
+ "offset": 0,
+ "size": 16
+ },
+ "VLANTC": {
+ "description": "VLANTC",
+ "offset": 16,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MACPMTCSR": {
+ "description": "Ethernet MAC PMT control and status\n register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PD": {
+ "description": "PD",
+ "offset": 0,
+ "size": 1
+ },
+ "MPE": {
+ "description": "MPE",
+ "offset": 1,
+ "size": 1
+ },
+ "WFE": {
+ "description": "WFE",
+ "offset": 2,
+ "size": 1
+ },
+ "MPR": {
+ "description": "MPR",
+ "offset": 5,
+ "size": 1
+ },
+ "WFR": {
+ "description": "WFR",
+ "offset": 6,
+ "size": 1
+ },
+ "GU": {
+ "description": "GU",
+ "offset": 9,
+ "size": 1
+ },
+ "WFFRPR": {
+ "description": "WFFRPR",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MACDBGR": {
+ "description": "Ethernet MAC debug register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "CR": {
+ "description": "CR",
+ "offset": 0,
+ "size": 1
+ },
+ "CSR": {
+ "description": "CSR",
+ "offset": 1,
+ "size": 1
+ },
+ "ROR": {
+ "description": "ROR",
+ "offset": 2,
+ "size": 1
+ },
+ "MCF": {
+ "description": "MCF",
+ "offset": 3,
+ "size": 1
+ },
+ "MCP": {
+ "description": "MCP",
+ "offset": 4,
+ "size": 1
+ },
+ "MCFHP": {
+ "description": "MCFHP",
+ "offset": 5,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MACSR": {
+ "description": "Ethernet MAC interrupt status\n register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PMTS": {
+ "description": "PMTS",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "MMCS": {
+ "description": "MMCS",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "MMCRS": {
+ "description": "MMCRS",
+ "offset": 5,
+ "size": 1,
+ "access": "read-only"
+ },
+ "MMCTS": {
+ "description": "MMCTS",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TSTS": {
+ "description": "TSTS",
+ "offset": 9,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MACIMR": {
+ "description": "Ethernet MAC interrupt mask\n register",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PMTIM": {
+ "description": "PMTIM",
+ "offset": 3,
+ "size": 1
+ },
+ "TSTIM": {
+ "description": "TSTIM",
+ "offset": 9,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MACA0HR": {
+ "description": "Ethernet MAC address 0 high\n register",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 1114111,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MACA0H": {
+ "description": "MAC address0 high",
+ "offset": 0,
+ "size": 16
+ },
+ "MO": {
+ "description": "Always 1",
+ "offset": 31,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "MACA0LR": {
+ "description": "Ethernet MAC address 0 low\n register",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MACA0L": {
+ "description": "0",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "MACA1HR": {
+ "description": "Ethernet MAC address 1 high\n register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 65535,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MACA1H": {
+ "description": "MACA1H",
+ "offset": 0,
+ "size": 16
+ },
+ "MBC": {
+ "description": "MBC",
+ "offset": 24,
+ "size": 6
+ },
+ "SA": {
+ "description": "SA",
+ "offset": 30,
+ "size": 1
+ },
+ "AE": {
+ "description": "AE",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MACA1LR": {
+ "description": "Ethernet MAC address1 low\n register",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MACA1LR": {
+ "description": "MACA1LR",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "MACA2HR": {
+ "description": "Ethernet MAC address 2 high\n register",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 65535,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MAC2AH": {
+ "description": "MAC2AH",
+ "offset": 0,
+ "size": 16
+ },
+ "MBC": {
+ "description": "MBC",
+ "offset": 24,
+ "size": 6
+ },
+ "SA": {
+ "description": "SA",
+ "offset": 30,
+ "size": 1
+ },
+ "AE": {
+ "description": "AE",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MACA2LR": {
+ "description": "Ethernet MAC address 2 low\n register",
+ "offset": 84,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MACA2L": {
+ "description": "MACA2L",
+ "offset": 0,
+ "size": 31
+ }
+ }
+ }
+ },
+ "MACA3HR": {
+ "description": "Ethernet MAC address 3 high\n register",
+ "offset": 88,
+ "size": 32,
+ "reset_value": 65535,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MACA3H": {
+ "description": "MACA3H",
+ "offset": 0,
+ "size": 16
+ },
+ "MBC": {
+ "description": "MBC",
+ "offset": 24,
+ "size": 6
+ },
+ "SA": {
+ "description": "SA",
+ "offset": 30,
+ "size": 1
+ },
+ "AE": {
+ "description": "AE",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MACA3LR": {
+ "description": "Ethernet MAC address 3 low\n register",
+ "offset": 92,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MBCA3L": {
+ "description": "MBCA3L",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "CAN1": {
+ "description": "Controller area network",
+ "children": {
+ "registers": {
+ "MCR": {
+ "description": "master control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 65538,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBF": {
+ "description": "DBF",
+ "offset": 16,
+ "size": 1
+ },
+ "RESET": {
+ "description": "RESET",
+ "offset": 15,
+ "size": 1
+ },
+ "TTCM": {
+ "description": "TTCM",
+ "offset": 7,
+ "size": 1
+ },
+ "ABOM": {
+ "description": "ABOM",
+ "offset": 6,
+ "size": 1
+ },
+ "AWUM": {
+ "description": "AWUM",
+ "offset": 5,
+ "size": 1
+ },
+ "NART": {
+ "description": "NART",
+ "offset": 4,
+ "size": 1
+ },
+ "RFLM": {
+ "description": "RFLM",
+ "offset": 3,
+ "size": 1
+ },
+ "TXFP": {
+ "description": "TXFP",
+ "offset": 2,
+ "size": 1
+ },
+ "SLEEP": {
+ "description": "SLEEP",
+ "offset": 1,
+ "size": 1
+ },
+ "INRQ": {
+ "description": "INRQ",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "MSR": {
+ "description": "master status register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 3074,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RX": {
+ "description": "RX",
+ "offset": 11,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SAMP": {
+ "description": "SAMP",
+ "offset": 10,
+ "size": 1,
+ "access": "read-only"
+ },
+ "RXM": {
+ "description": "RXM",
+ "offset": 9,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TXM": {
+ "description": "TXM",
+ "offset": 8,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SLAKI": {
+ "description": "SLAKI",
+ "offset": 4,
+ "size": 1
+ },
+ "WKUI": {
+ "description": "WKUI",
+ "offset": 3,
+ "size": 1
+ },
+ "ERRI": {
+ "description": "ERRI",
+ "offset": 2,
+ "size": 1
+ },
+ "SLAK": {
+ "description": "SLAK",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "INAK": {
+ "description": "INAK",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "TSR": {
+ "description": "transmit status register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 469762048,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LOW2": {
+ "description": "Lowest priority flag for mailbox\n 2",
+ "offset": 31,
+ "size": 1,
+ "access": "read-only"
+ },
+ "LOW1": {
+ "description": "Lowest priority flag for mailbox\n 1",
+ "offset": 30,
+ "size": 1,
+ "access": "read-only"
+ },
+ "LOW0": {
+ "description": "Lowest priority flag for mailbox\n 0",
+ "offset": 29,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TME2": {
+ "description": "Lowest priority flag for mailbox\n 2",
+ "offset": 28,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TME1": {
+ "description": "Lowest priority flag for mailbox\n 1",
+ "offset": 27,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TME0": {
+ "description": "Lowest priority flag for mailbox\n 0",
+ "offset": 26,
+ "size": 1,
+ "access": "read-only"
+ },
+ "CODE": {
+ "description": "CODE",
+ "offset": 24,
+ "size": 2,
+ "access": "read-only"
+ },
+ "ABRQ2": {
+ "description": "ABRQ2",
+ "offset": 23,
+ "size": 1
+ },
+ "TERR2": {
+ "description": "TERR2",
+ "offset": 19,
+ "size": 1
+ },
+ "ALST2": {
+ "description": "ALST2",
+ "offset": 18,
+ "size": 1
+ },
+ "TXOK2": {
+ "description": "TXOK2",
+ "offset": 17,
+ "size": 1
+ },
+ "RQCP2": {
+ "description": "RQCP2",
+ "offset": 16,
+ "size": 1
+ },
+ "ABRQ1": {
+ "description": "ABRQ1",
+ "offset": 15,
+ "size": 1
+ },
+ "TERR1": {
+ "description": "TERR1",
+ "offset": 11,
+ "size": 1
+ },
+ "ALST1": {
+ "description": "ALST1",
+ "offset": 10,
+ "size": 1
+ },
+ "TXOK1": {
+ "description": "TXOK1",
+ "offset": 9,
+ "size": 1
+ },
+ "RQCP1": {
+ "description": "RQCP1",
+ "offset": 8,
+ "size": 1
+ },
+ "ABRQ0": {
+ "description": "ABRQ0",
+ "offset": 7,
+ "size": 1
+ },
+ "TERR0": {
+ "description": "TERR0",
+ "offset": 3,
+ "size": 1
+ },
+ "ALST0": {
+ "description": "ALST0",
+ "offset": 2,
+ "size": 1
+ },
+ "TXOK0": {
+ "description": "TXOK0",
+ "offset": 1,
+ "size": 1
+ },
+ "RQCP0": {
+ "description": "RQCP0",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "RF0R": {
+ "description": "receive FIFO 0 register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RFOM0": {
+ "description": "RFOM0",
+ "offset": 5,
+ "size": 1
+ },
+ "FOVR0": {
+ "description": "FOVR0",
+ "offset": 4,
+ "size": 1
+ },
+ "FULL0": {
+ "description": "FULL0",
+ "offset": 3,
+ "size": 1
+ },
+ "FMP0": {
+ "description": "FMP0",
+ "offset": 0,
+ "size": 2,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "RF1R": {
+ "description": "receive FIFO 1 register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RFOM1": {
+ "description": "RFOM1",
+ "offset": 5,
+ "size": 1
+ },
+ "FOVR1": {
+ "description": "FOVR1",
+ "offset": 4,
+ "size": 1
+ },
+ "FULL1": {
+ "description": "FULL1",
+ "offset": 3,
+ "size": 1
+ },
+ "FMP1": {
+ "description": "FMP1",
+ "offset": 0,
+ "size": 2,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "IER": {
+ "description": "interrupt enable register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SLKIE": {
+ "description": "SLKIE",
+ "offset": 17,
+ "size": 1
+ },
+ "WKUIE": {
+ "description": "WKUIE",
+ "offset": 16,
+ "size": 1
+ },
+ "ERRIE": {
+ "description": "ERRIE",
+ "offset": 15,
+ "size": 1
+ },
+ "LECIE": {
+ "description": "LECIE",
+ "offset": 11,
+ "size": 1
+ },
+ "BOFIE": {
+ "description": "BOFIE",
+ "offset": 10,
+ "size": 1
+ },
+ "EPVIE": {
+ "description": "EPVIE",
+ "offset": 9,
+ "size": 1
+ },
+ "EWGIE": {
+ "description": "EWGIE",
+ "offset": 8,
+ "size": 1
+ },
+ "FOVIE1": {
+ "description": "FOVIE1",
+ "offset": 6,
+ "size": 1
+ },
+ "FFIE1": {
+ "description": "FFIE1",
+ "offset": 5,
+ "size": 1
+ },
+ "FMPIE1": {
+ "description": "FMPIE1",
+ "offset": 4,
+ "size": 1
+ },
+ "FOVIE0": {
+ "description": "FOVIE0",
+ "offset": 3,
+ "size": 1
+ },
+ "FFIE0": {
+ "description": "FFIE0",
+ "offset": 2,
+ "size": 1
+ },
+ "FMPIE0": {
+ "description": "FMPIE0",
+ "offset": 1,
+ "size": 1
+ },
+ "TMEIE": {
+ "description": "TMEIE",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ESR": {
+ "description": "interrupt enable register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "REC": {
+ "description": "REC",
+ "offset": 24,
+ "size": 8,
+ "access": "read-only"
+ },
+ "TEC": {
+ "description": "TEC",
+ "offset": 16,
+ "size": 8,
+ "access": "read-only"
+ },
+ "LEC": {
+ "description": "LEC",
+ "offset": 4,
+ "size": 3
+ },
+ "BOFF": {
+ "description": "BOFF",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPVF": {
+ "description": "EPVF",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EWGF": {
+ "description": "EWGF",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "BTR": {
+ "description": "bit timing register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SILM": {
+ "description": "SILM",
+ "offset": 31,
+ "size": 1
+ },
+ "LBKM": {
+ "description": "LBKM",
+ "offset": 30,
+ "size": 1
+ },
+ "SJW": {
+ "description": "SJW",
+ "offset": 24,
+ "size": 2
+ },
+ "TS2": {
+ "description": "TS2",
+ "offset": 20,
+ "size": 3
+ },
+ "TS1": {
+ "description": "TS1",
+ "offset": 16,
+ "size": 4
+ },
+ "BRP": {
+ "description": "BRP",
+ "offset": 0,
+ "size": 10
+ }
+ }
+ }
+ },
+ "TI0R": {
+ "description": "TX mailbox identifier register",
+ "offset": 384,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "STID": {
+ "description": "STID",
+ "offset": 21,
+ "size": 11
+ },
+ "EXID": {
+ "description": "EXID",
+ "offset": 3,
+ "size": 18
+ },
+ "IDE": {
+ "description": "IDE",
+ "offset": 2,
+ "size": 1
+ },
+ "RTR": {
+ "description": "RTR",
+ "offset": 1,
+ "size": 1
+ },
+ "TXRQ": {
+ "description": "TXRQ",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "TDT0R": {
+ "description": "mailbox data length control and time stamp\n register",
+ "offset": 388,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIME": {
+ "description": "TIME",
+ "offset": 16,
+ "size": 16
+ },
+ "TGT": {
+ "description": "TGT",
+ "offset": 8,
+ "size": 1
+ },
+ "DLC": {
+ "description": "DLC",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "TDL0R": {
+ "description": "mailbox data low register",
+ "offset": 392,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATA3": {
+ "description": "DATA3",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA2": {
+ "description": "DATA2",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA1": {
+ "description": "DATA1",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA0": {
+ "description": "DATA0",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "TDH0R": {
+ "description": "mailbox data high register",
+ "offset": 396,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATA7": {
+ "description": "DATA7",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA6": {
+ "description": "DATA6",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA5": {
+ "description": "DATA5",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA4": {
+ "description": "DATA4",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "TI1R": {
+ "description": "mailbox identifier register",
+ "offset": 400,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "STID": {
+ "description": "STID",
+ "offset": 21,
+ "size": 11
+ },
+ "EXID": {
+ "description": "EXID",
+ "offset": 3,
+ "size": 18
+ },
+ "IDE": {
+ "description": "IDE",
+ "offset": 2,
+ "size": 1
+ },
+ "RTR": {
+ "description": "RTR",
+ "offset": 1,
+ "size": 1
+ },
+ "TXRQ": {
+ "description": "TXRQ",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "TDT1R": {
+ "description": "mailbox data length control and time stamp\n register",
+ "offset": 404,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIME": {
+ "description": "TIME",
+ "offset": 16,
+ "size": 16
+ },
+ "TGT": {
+ "description": "TGT",
+ "offset": 8,
+ "size": 1
+ },
+ "DLC": {
+ "description": "DLC",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "TDL1R": {
+ "description": "mailbox data low register",
+ "offset": 408,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATA3": {
+ "description": "DATA3",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA2": {
+ "description": "DATA2",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA1": {
+ "description": "DATA1",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA0": {
+ "description": "DATA0",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "TDH1R": {
+ "description": "mailbox data high register",
+ "offset": 412,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATA7": {
+ "description": "DATA7",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA6": {
+ "description": "DATA6",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA5": {
+ "description": "DATA5",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA4": {
+ "description": "DATA4",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "TI2R": {
+ "description": "mailbox identifier register",
+ "offset": 416,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "STID": {
+ "description": "STID",
+ "offset": 21,
+ "size": 11
+ },
+ "EXID": {
+ "description": "EXID",
+ "offset": 3,
+ "size": 18
+ },
+ "IDE": {
+ "description": "IDE",
+ "offset": 2,
+ "size": 1
+ },
+ "RTR": {
+ "description": "RTR",
+ "offset": 1,
+ "size": 1
+ },
+ "TXRQ": {
+ "description": "TXRQ",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "TDT2R": {
+ "description": "mailbox data length control and time stamp\n register",
+ "offset": 420,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIME": {
+ "description": "TIME",
+ "offset": 16,
+ "size": 16
+ },
+ "TGT": {
+ "description": "TGT",
+ "offset": 8,
+ "size": 1
+ },
+ "DLC": {
+ "description": "DLC",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "TDL2R": {
+ "description": "mailbox data low register",
+ "offset": 424,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATA3": {
+ "description": "DATA3",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA2": {
+ "description": "DATA2",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA1": {
+ "description": "DATA1",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA0": {
+ "description": "DATA0",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "TDH2R": {
+ "description": "mailbox data high register",
+ "offset": 428,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DATA7": {
+ "description": "DATA7",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA6": {
+ "description": "DATA6",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA5": {
+ "description": "DATA5",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA4": {
+ "description": "DATA4",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "RI0R": {
+ "description": "receive FIFO mailbox identifier\n register",
+ "offset": 432,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "STID": {
+ "description": "STID",
+ "offset": 21,
+ "size": 11
+ },
+ "EXID": {
+ "description": "EXID",
+ "offset": 3,
+ "size": 18
+ },
+ "IDE": {
+ "description": "IDE",
+ "offset": 2,
+ "size": 1
+ },
+ "RTR": {
+ "description": "RTR",
+ "offset": 1,
+ "size": 1
+ }
+ }
+ }
+ },
+ "RDT0R": {
+ "description": "mailbox data high register",
+ "offset": 436,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "TIME": {
+ "description": "TIME",
+ "offset": 16,
+ "size": 16
+ },
+ "FMI": {
+ "description": "FMI",
+ "offset": 8,
+ "size": 8
+ },
+ "DLC": {
+ "description": "DLC",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "RDL0R": {
+ "description": "mailbox data high register",
+ "offset": 440,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DATA3": {
+ "description": "DATA3",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA2": {
+ "description": "DATA2",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA1": {
+ "description": "DATA1",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA0": {
+ "description": "DATA0",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "RDH0R": {
+ "description": "receive FIFO mailbox data high\n register",
+ "offset": 444,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DATA7": {
+ "description": "DATA7",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA6": {
+ "description": "DATA6",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA5": {
+ "description": "DATA5",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA4": {
+ "description": "DATA4",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "RI1R": {
+ "description": "mailbox data high register",
+ "offset": 448,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "STID": {
+ "description": "STID",
+ "offset": 21,
+ "size": 11
+ },
+ "EXID": {
+ "description": "EXID",
+ "offset": 3,
+ "size": 18
+ },
+ "IDE": {
+ "description": "IDE",
+ "offset": 2,
+ "size": 1
+ },
+ "RTR": {
+ "description": "RTR",
+ "offset": 1,
+ "size": 1
+ }
+ }
+ }
+ },
+ "RDT1R": {
+ "description": "mailbox data high register",
+ "offset": 452,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "TIME": {
+ "description": "TIME",
+ "offset": 16,
+ "size": 16
+ },
+ "FMI": {
+ "description": "FMI",
+ "offset": 8,
+ "size": 8
+ },
+ "DLC": {
+ "description": "DLC",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "RDL1R": {
+ "description": "mailbox data high register",
+ "offset": 456,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DATA3": {
+ "description": "DATA3",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA2": {
+ "description": "DATA2",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA1": {
+ "description": "DATA1",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA0": {
+ "description": "DATA0",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "RDH1R": {
+ "description": "mailbox data high register",
+ "offset": 460,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DATA7": {
+ "description": "DATA7",
+ "offset": 24,
+ "size": 8
+ },
+ "DATA6": {
+ "description": "DATA6",
+ "offset": 16,
+ "size": 8
+ },
+ "DATA5": {
+ "description": "DATA5",
+ "offset": 8,
+ "size": 8
+ },
+ "DATA4": {
+ "description": "DATA4",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "FMR": {
+ "description": "filter master register",
+ "offset": 512,
+ "size": 32,
+ "reset_value": 706481665,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CAN2SB": {
+ "description": "CAN2SB",
+ "offset": 8,
+ "size": 6
+ },
+ "FINIT": {
+ "description": "FINIT",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FM1R": {
+ "description": "filter mode register",
+ "offset": 516,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FBM0": {
+ "description": "Filter mode",
+ "offset": 0,
+ "size": 1
+ },
+ "FBM1": {
+ "description": "Filter mode",
+ "offset": 1,
+ "size": 1
+ },
+ "FBM2": {
+ "description": "Filter mode",
+ "offset": 2,
+ "size": 1
+ },
+ "FBM3": {
+ "description": "Filter mode",
+ "offset": 3,
+ "size": 1
+ },
+ "FBM4": {
+ "description": "Filter mode",
+ "offset": 4,
+ "size": 1
+ },
+ "FBM5": {
+ "description": "Filter mode",
+ "offset": 5,
+ "size": 1
+ },
+ "FBM6": {
+ "description": "Filter mode",
+ "offset": 6,
+ "size": 1
+ },
+ "FBM7": {
+ "description": "Filter mode",
+ "offset": 7,
+ "size": 1
+ },
+ "FBM8": {
+ "description": "Filter mode",
+ "offset": 8,
+ "size": 1
+ },
+ "FBM9": {
+ "description": "Filter mode",
+ "offset": 9,
+ "size": 1
+ },
+ "FBM10": {
+ "description": "Filter mode",
+ "offset": 10,
+ "size": 1
+ },
+ "FBM11": {
+ "description": "Filter mode",
+ "offset": 11,
+ "size": 1
+ },
+ "FBM12": {
+ "description": "Filter mode",
+ "offset": 12,
+ "size": 1
+ },
+ "FBM13": {
+ "description": "Filter mode",
+ "offset": 13,
+ "size": 1
+ },
+ "FBM14": {
+ "description": "Filter mode",
+ "offset": 14,
+ "size": 1
+ },
+ "FBM15": {
+ "description": "Filter mode",
+ "offset": 15,
+ "size": 1
+ },
+ "FBM16": {
+ "description": "Filter mode",
+ "offset": 16,
+ "size": 1
+ },
+ "FBM17": {
+ "description": "Filter mode",
+ "offset": 17,
+ "size": 1
+ },
+ "FBM18": {
+ "description": "Filter mode",
+ "offset": 18,
+ "size": 1
+ },
+ "FBM19": {
+ "description": "Filter mode",
+ "offset": 19,
+ "size": 1
+ },
+ "FBM20": {
+ "description": "Filter mode",
+ "offset": 20,
+ "size": 1
+ },
+ "FBM21": {
+ "description": "Filter mode",
+ "offset": 21,
+ "size": 1
+ },
+ "FBM22": {
+ "description": "Filter mode",
+ "offset": 22,
+ "size": 1
+ },
+ "FBM23": {
+ "description": "Filter mode",
+ "offset": 23,
+ "size": 1
+ },
+ "FBM24": {
+ "description": "Filter mode",
+ "offset": 24,
+ "size": 1
+ },
+ "FBM25": {
+ "description": "Filter mode",
+ "offset": 25,
+ "size": 1
+ },
+ "FBM26": {
+ "description": "Filter mode",
+ "offset": 26,
+ "size": 1
+ },
+ "FBM27": {
+ "description": "Filter mode",
+ "offset": 27,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS1R": {
+ "description": "filter scale register",
+ "offset": 524,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FSC0": {
+ "description": "Filter scale configuration",
+ "offset": 0,
+ "size": 1
+ },
+ "FSC1": {
+ "description": "Filter scale configuration",
+ "offset": 1,
+ "size": 1
+ },
+ "FSC2": {
+ "description": "Filter scale configuration",
+ "offset": 2,
+ "size": 1
+ },
+ "FSC3": {
+ "description": "Filter scale configuration",
+ "offset": 3,
+ "size": 1
+ },
+ "FSC4": {
+ "description": "Filter scale configuration",
+ "offset": 4,
+ "size": 1
+ },
+ "FSC5": {
+ "description": "Filter scale configuration",
+ "offset": 5,
+ "size": 1
+ },
+ "FSC6": {
+ "description": "Filter scale configuration",
+ "offset": 6,
+ "size": 1
+ },
+ "FSC7": {
+ "description": "Filter scale configuration",
+ "offset": 7,
+ "size": 1
+ },
+ "FSC8": {
+ "description": "Filter scale configuration",
+ "offset": 8,
+ "size": 1
+ },
+ "FSC9": {
+ "description": "Filter scale configuration",
+ "offset": 9,
+ "size": 1
+ },
+ "FSC10": {
+ "description": "Filter scale configuration",
+ "offset": 10,
+ "size": 1
+ },
+ "FSC11": {
+ "description": "Filter scale configuration",
+ "offset": 11,
+ "size": 1
+ },
+ "FSC12": {
+ "description": "Filter scale configuration",
+ "offset": 12,
+ "size": 1
+ },
+ "FSC13": {
+ "description": "Filter scale configuration",
+ "offset": 13,
+ "size": 1
+ },
+ "FSC14": {
+ "description": "Filter scale configuration",
+ "offset": 14,
+ "size": 1
+ },
+ "FSC15": {
+ "description": "Filter scale configuration",
+ "offset": 15,
+ "size": 1
+ },
+ "FSC16": {
+ "description": "Filter scale configuration",
+ "offset": 16,
+ "size": 1
+ },
+ "FSC17": {
+ "description": "Filter scale configuration",
+ "offset": 17,
+ "size": 1
+ },
+ "FSC18": {
+ "description": "Filter scale configuration",
+ "offset": 18,
+ "size": 1
+ },
+ "FSC19": {
+ "description": "Filter scale configuration",
+ "offset": 19,
+ "size": 1
+ },
+ "FSC20": {
+ "description": "Filter scale configuration",
+ "offset": 20,
+ "size": 1
+ },
+ "FSC21": {
+ "description": "Filter scale configuration",
+ "offset": 21,
+ "size": 1
+ },
+ "FSC22": {
+ "description": "Filter scale configuration",
+ "offset": 22,
+ "size": 1
+ },
+ "FSC23": {
+ "description": "Filter scale configuration",
+ "offset": 23,
+ "size": 1
+ },
+ "FSC24": {
+ "description": "Filter scale configuration",
+ "offset": 24,
+ "size": 1
+ },
+ "FSC25": {
+ "description": "Filter scale configuration",
+ "offset": 25,
+ "size": 1
+ },
+ "FSC26": {
+ "description": "Filter scale configuration",
+ "offset": 26,
+ "size": 1
+ },
+ "FSC27": {
+ "description": "Filter scale configuration",
+ "offset": 27,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FFA1R": {
+ "description": "filter FIFO assignment\n register",
+ "offset": 532,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FFA0": {
+ "description": "Filter FIFO assignment for filter\n 0",
+ "offset": 0,
+ "size": 1
+ },
+ "FFA1": {
+ "description": "Filter FIFO assignment for filter\n 1",
+ "offset": 1,
+ "size": 1
+ },
+ "FFA2": {
+ "description": "Filter FIFO assignment for filter\n 2",
+ "offset": 2,
+ "size": 1
+ },
+ "FFA3": {
+ "description": "Filter FIFO assignment for filter\n 3",
+ "offset": 3,
+ "size": 1
+ },
+ "FFA4": {
+ "description": "Filter FIFO assignment for filter\n 4",
+ "offset": 4,
+ "size": 1
+ },
+ "FFA5": {
+ "description": "Filter FIFO assignment for filter\n 5",
+ "offset": 5,
+ "size": 1
+ },
+ "FFA6": {
+ "description": "Filter FIFO assignment for filter\n 6",
+ "offset": 6,
+ "size": 1
+ },
+ "FFA7": {
+ "description": "Filter FIFO assignment for filter\n 7",
+ "offset": 7,
+ "size": 1
+ },
+ "FFA8": {
+ "description": "Filter FIFO assignment for filter\n 8",
+ "offset": 8,
+ "size": 1
+ },
+ "FFA9": {
+ "description": "Filter FIFO assignment for filter\n 9",
+ "offset": 9,
+ "size": 1
+ },
+ "FFA10": {
+ "description": "Filter FIFO assignment for filter\n 10",
+ "offset": 10,
+ "size": 1
+ },
+ "FFA11": {
+ "description": "Filter FIFO assignment for filter\n 11",
+ "offset": 11,
+ "size": 1
+ },
+ "FFA12": {
+ "description": "Filter FIFO assignment for filter\n 12",
+ "offset": 12,
+ "size": 1
+ },
+ "FFA13": {
+ "description": "Filter FIFO assignment for filter\n 13",
+ "offset": 13,
+ "size": 1
+ },
+ "FFA14": {
+ "description": "Filter FIFO assignment for filter\n 14",
+ "offset": 14,
+ "size": 1
+ },
+ "FFA15": {
+ "description": "Filter FIFO assignment for filter\n 15",
+ "offset": 15,
+ "size": 1
+ },
+ "FFA16": {
+ "description": "Filter FIFO assignment for filter\n 16",
+ "offset": 16,
+ "size": 1
+ },
+ "FFA17": {
+ "description": "Filter FIFO assignment for filter\n 17",
+ "offset": 17,
+ "size": 1
+ },
+ "FFA18": {
+ "description": "Filter FIFO assignment for filter\n 18",
+ "offset": 18,
+ "size": 1
+ },
+ "FFA19": {
+ "description": "Filter FIFO assignment for filter\n 19",
+ "offset": 19,
+ "size": 1
+ },
+ "FFA20": {
+ "description": "Filter FIFO assignment for filter\n 20",
+ "offset": 20,
+ "size": 1
+ },
+ "FFA21": {
+ "description": "Filter FIFO assignment for filter\n 21",
+ "offset": 21,
+ "size": 1
+ },
+ "FFA22": {
+ "description": "Filter FIFO assignment for filter\n 22",
+ "offset": 22,
+ "size": 1
+ },
+ "FFA23": {
+ "description": "Filter FIFO assignment for filter\n 23",
+ "offset": 23,
+ "size": 1
+ },
+ "FFA24": {
+ "description": "Filter FIFO assignment for filter\n 24",
+ "offset": 24,
+ "size": 1
+ },
+ "FFA25": {
+ "description": "Filter FIFO assignment for filter\n 25",
+ "offset": 25,
+ "size": 1
+ },
+ "FFA26": {
+ "description": "Filter FIFO assignment for filter\n 26",
+ "offset": 26,
+ "size": 1
+ },
+ "FFA27": {
+ "description": "Filter FIFO assignment for filter\n 27",
+ "offset": 27,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FA1R": {
+ "description": "filter activation register",
+ "offset": 540,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FACT0": {
+ "description": "Filter active",
+ "offset": 0,
+ "size": 1
+ },
+ "FACT1": {
+ "description": "Filter active",
+ "offset": 1,
+ "size": 1
+ },
+ "FACT2": {
+ "description": "Filter active",
+ "offset": 2,
+ "size": 1
+ },
+ "FACT3": {
+ "description": "Filter active",
+ "offset": 3,
+ "size": 1
+ },
+ "FACT4": {
+ "description": "Filter active",
+ "offset": 4,
+ "size": 1
+ },
+ "FACT5": {
+ "description": "Filter active",
+ "offset": 5,
+ "size": 1
+ },
+ "FACT6": {
+ "description": "Filter active",
+ "offset": 6,
+ "size": 1
+ },
+ "FACT7": {
+ "description": "Filter active",
+ "offset": 7,
+ "size": 1
+ },
+ "FACT8": {
+ "description": "Filter active",
+ "offset": 8,
+ "size": 1
+ },
+ "FACT9": {
+ "description": "Filter active",
+ "offset": 9,
+ "size": 1
+ },
+ "FACT10": {
+ "description": "Filter active",
+ "offset": 10,
+ "size": 1
+ },
+ "FACT11": {
+ "description": "Filter active",
+ "offset": 11,
+ "size": 1
+ },
+ "FACT12": {
+ "description": "Filter active",
+ "offset": 12,
+ "size": 1
+ },
+ "FACT13": {
+ "description": "Filter active",
+ "offset": 13,
+ "size": 1
+ },
+ "FACT14": {
+ "description": "Filter active",
+ "offset": 14,
+ "size": 1
+ },
+ "FACT15": {
+ "description": "Filter active",
+ "offset": 15,
+ "size": 1
+ },
+ "FACT16": {
+ "description": "Filter active",
+ "offset": 16,
+ "size": 1
+ },
+ "FACT17": {
+ "description": "Filter active",
+ "offset": 17,
+ "size": 1
+ },
+ "FACT18": {
+ "description": "Filter active",
+ "offset": 18,
+ "size": 1
+ },
+ "FACT19": {
+ "description": "Filter active",
+ "offset": 19,
+ "size": 1
+ },
+ "FACT20": {
+ "description": "Filter active",
+ "offset": 20,
+ "size": 1
+ },
+ "FACT21": {
+ "description": "Filter active",
+ "offset": 21,
+ "size": 1
+ },
+ "FACT22": {
+ "description": "Filter active",
+ "offset": 22,
+ "size": 1
+ },
+ "FACT23": {
+ "description": "Filter active",
+ "offset": 23,
+ "size": 1
+ },
+ "FACT24": {
+ "description": "Filter active",
+ "offset": 24,
+ "size": 1
+ },
+ "FACT25": {
+ "description": "Filter active",
+ "offset": 25,
+ "size": 1
+ },
+ "FACT26": {
+ "description": "Filter active",
+ "offset": 26,
+ "size": 1
+ },
+ "FACT27": {
+ "description": "Filter active",
+ "offset": 27,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F0R1": {
+ "description": "Filter bank 0 register 1",
+ "offset": 576,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F0R2": {
+ "description": "Filter bank 0 register 2",
+ "offset": 580,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F1R1": {
+ "description": "Filter bank 1 register 1",
+ "offset": 584,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F1R2": {
+ "description": "Filter bank 1 register 2",
+ "offset": 588,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F2R1": {
+ "description": "Filter bank 2 register 1",
+ "offset": 592,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F2R2": {
+ "description": "Filter bank 2 register 2",
+ "offset": 596,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F3R1": {
+ "description": "Filter bank 3 register 1",
+ "offset": 600,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F3R2": {
+ "description": "Filter bank 3 register 2",
+ "offset": 604,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F4R1": {
+ "description": "Filter bank 4 register 1",
+ "offset": 608,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F4R2": {
+ "description": "Filter bank 4 register 2",
+ "offset": 612,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F5R1": {
+ "description": "Filter bank 5 register 1",
+ "offset": 616,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F5R2": {
+ "description": "Filter bank 5 register 2",
+ "offset": 620,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F6R1": {
+ "description": "Filter bank 6 register 1",
+ "offset": 624,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F6R2": {
+ "description": "Filter bank 6 register 2",
+ "offset": 628,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F7R1": {
+ "description": "Filter bank 7 register 1",
+ "offset": 632,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F7R2": {
+ "description": "Filter bank 7 register 2",
+ "offset": 636,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F8R1": {
+ "description": "Filter bank 8 register 1",
+ "offset": 640,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F8R2": {
+ "description": "Filter bank 8 register 2",
+ "offset": 644,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F9R1": {
+ "description": "Filter bank 9 register 1",
+ "offset": 648,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F9R2": {
+ "description": "Filter bank 9 register 2",
+ "offset": 652,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F10R1": {
+ "description": "Filter bank 10 register 1",
+ "offset": 656,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F10R2": {
+ "description": "Filter bank 10 register 2",
+ "offset": 660,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F11R1": {
+ "description": "Filter bank 11 register 1",
+ "offset": 664,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F11R2": {
+ "description": "Filter bank 11 register 2",
+ "offset": 668,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F12R1": {
+ "description": "Filter bank 4 register 1",
+ "offset": 672,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F12R2": {
+ "description": "Filter bank 12 register 2",
+ "offset": 676,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F13R1": {
+ "description": "Filter bank 13 register 1",
+ "offset": 680,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F13R2": {
+ "description": "Filter bank 13 register 2",
+ "offset": 684,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F14R1": {
+ "description": "Filter bank 14 register 1",
+ "offset": 688,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F14R2": {
+ "description": "Filter bank 14 register 2",
+ "offset": 692,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F15R1": {
+ "description": "Filter bank 15 register 1",
+ "offset": 696,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F15R2": {
+ "description": "Filter bank 15 register 2",
+ "offset": 700,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F16R1": {
+ "description": "Filter bank 16 register 1",
+ "offset": 704,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F16R2": {
+ "description": "Filter bank 16 register 2",
+ "offset": 708,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F17R1": {
+ "description": "Filter bank 17 register 1",
+ "offset": 712,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F17R2": {
+ "description": "Filter bank 17 register 2",
+ "offset": 716,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F18R1": {
+ "description": "Filter bank 18 register 1",
+ "offset": 720,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F18R2": {
+ "description": "Filter bank 18 register 2",
+ "offset": 724,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F19R1": {
+ "description": "Filter bank 19 register 1",
+ "offset": 728,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F19R2": {
+ "description": "Filter bank 19 register 2",
+ "offset": 732,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F20R1": {
+ "description": "Filter bank 20 register 1",
+ "offset": 736,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F20R2": {
+ "description": "Filter bank 20 register 2",
+ "offset": 740,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F21R1": {
+ "description": "Filter bank 21 register 1",
+ "offset": 744,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F21R2": {
+ "description": "Filter bank 21 register 2",
+ "offset": 748,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F22R1": {
+ "description": "Filter bank 22 register 1",
+ "offset": 752,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F22R2": {
+ "description": "Filter bank 22 register 2",
+ "offset": 756,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F23R1": {
+ "description": "Filter bank 23 register 1",
+ "offset": 760,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F23R2": {
+ "description": "Filter bank 23 register 2",
+ "offset": 764,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F24R1": {
+ "description": "Filter bank 24 register 1",
+ "offset": 768,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F24R2": {
+ "description": "Filter bank 24 register 2",
+ "offset": 772,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F25R1": {
+ "description": "Filter bank 25 register 1",
+ "offset": 776,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F25R2": {
+ "description": "Filter bank 25 register 2",
+ "offset": 780,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F26R1": {
+ "description": "Filter bank 26 register 1",
+ "offset": 784,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F26R2": {
+ "description": "Filter bank 26 register 2",
+ "offset": 788,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F27R1": {
+ "description": "Filter bank 27 register 1",
+ "offset": 792,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "F27R2": {
+ "description": "Filter bank 27 register 2",
+ "offset": 796,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FB0": {
+ "description": "Filter bits",
+ "offset": 0,
+ "size": 1
+ },
+ "FB1": {
+ "description": "Filter bits",
+ "offset": 1,
+ "size": 1
+ },
+ "FB2": {
+ "description": "Filter bits",
+ "offset": 2,
+ "size": 1
+ },
+ "FB3": {
+ "description": "Filter bits",
+ "offset": 3,
+ "size": 1
+ },
+ "FB4": {
+ "description": "Filter bits",
+ "offset": 4,
+ "size": 1
+ },
+ "FB5": {
+ "description": "Filter bits",
+ "offset": 5,
+ "size": 1
+ },
+ "FB6": {
+ "description": "Filter bits",
+ "offset": 6,
+ "size": 1
+ },
+ "FB7": {
+ "description": "Filter bits",
+ "offset": 7,
+ "size": 1
+ },
+ "FB8": {
+ "description": "Filter bits",
+ "offset": 8,
+ "size": 1
+ },
+ "FB9": {
+ "description": "Filter bits",
+ "offset": 9,
+ "size": 1
+ },
+ "FB10": {
+ "description": "Filter bits",
+ "offset": 10,
+ "size": 1
+ },
+ "FB11": {
+ "description": "Filter bits",
+ "offset": 11,
+ "size": 1
+ },
+ "FB12": {
+ "description": "Filter bits",
+ "offset": 12,
+ "size": 1
+ },
+ "FB13": {
+ "description": "Filter bits",
+ "offset": 13,
+ "size": 1
+ },
+ "FB14": {
+ "description": "Filter bits",
+ "offset": 14,
+ "size": 1
+ },
+ "FB15": {
+ "description": "Filter bits",
+ "offset": 15,
+ "size": 1
+ },
+ "FB16": {
+ "description": "Filter bits",
+ "offset": 16,
+ "size": 1
+ },
+ "FB17": {
+ "description": "Filter bits",
+ "offset": 17,
+ "size": 1
+ },
+ "FB18": {
+ "description": "Filter bits",
+ "offset": 18,
+ "size": 1
+ },
+ "FB19": {
+ "description": "Filter bits",
+ "offset": 19,
+ "size": 1
+ },
+ "FB20": {
+ "description": "Filter bits",
+ "offset": 20,
+ "size": 1
+ },
+ "FB21": {
+ "description": "Filter bits",
+ "offset": 21,
+ "size": 1
+ },
+ "FB22": {
+ "description": "Filter bits",
+ "offset": 22,
+ "size": 1
+ },
+ "FB23": {
+ "description": "Filter bits",
+ "offset": 23,
+ "size": 1
+ },
+ "FB24": {
+ "description": "Filter bits",
+ "offset": 24,
+ "size": 1
+ },
+ "FB25": {
+ "description": "Filter bits",
+ "offset": 25,
+ "size": 1
+ },
+ "FB26": {
+ "description": "Filter bits",
+ "offset": 26,
+ "size": 1
+ },
+ "FB27": {
+ "description": "Filter bits",
+ "offset": 27,
+ "size": 1
+ },
+ "FB28": {
+ "description": "Filter bits",
+ "offset": 28,
+ "size": 1
+ },
+ "FB29": {
+ "description": "Filter bits",
+ "offset": 29,
+ "size": 1
+ },
+ "FB30": {
+ "description": "Filter bits",
+ "offset": 30,
+ "size": 1
+ },
+ "FB31": {
+ "description": "Filter bits",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "OTG_FS_PWRCLK": {
+ "description": "USB on the go full speed",
+ "children": {
+ "registers": {
+ "FS_PCGCCTL": {
+ "description": "OTG_FS power and clock gating control\n register (OTG_FS_PCGCCTL)",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "STPPCLK": {
+ "description": "Stop PHY clock",
+ "offset": 0,
+ "size": 1
+ },
+ "GATEHCLK": {
+ "description": "Gate HCLK",
+ "offset": 1,
+ "size": 1
+ },
+ "PHYSUSP": {
+ "description": "PHY Suspended",
+ "offset": 4,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "DAC": {
+ "description": "Digital-to-analog converter",
+ "children": {
+ "registers": {
+ "CR": {
+ "description": "control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAUDRIE2": {
+ "description": "DAC channel2 DMA underrun interrupt\n enable",
+ "offset": 29,
+ "size": 1
+ },
+ "DMAEN2": {
+ "description": "DAC channel2 DMA enable",
+ "offset": 28,
+ "size": 1
+ },
+ "MAMP2": {
+ "description": "DAC channel2 mask/amplitude\n selector",
+ "offset": 24,
+ "size": 4
+ },
+ "WAVE2": {
+ "description": "DAC channel2 noise/triangle wave\n generation enable",
+ "offset": 22,
+ "size": 2
+ },
+ "TSEL2": {
+ "description": "DAC channel2 trigger\n selection",
+ "offset": 19,
+ "size": 3
+ },
+ "TEN2": {
+ "description": "DAC channel2 trigger\n enable",
+ "offset": 18,
+ "size": 1
+ },
+ "BOFF2": {
+ "description": "DAC channel2 output buffer\n disable",
+ "offset": 17,
+ "size": 1
+ },
+ "EN2": {
+ "description": "DAC channel2 enable",
+ "offset": 16,
+ "size": 1
+ },
+ "DMAUDRIE1": {
+ "description": "DAC channel1 DMA Underrun Interrupt\n enable",
+ "offset": 13,
+ "size": 1
+ },
+ "DMAEN1": {
+ "description": "DAC channel1 DMA enable",
+ "offset": 12,
+ "size": 1
+ },
+ "MAMP1": {
+ "description": "DAC channel1 mask/amplitude\n selector",
+ "offset": 8,
+ "size": 4
+ },
+ "WAVE1": {
+ "description": "DAC channel1 noise/triangle wave\n generation enable",
+ "offset": 6,
+ "size": 2
+ },
+ "TSEL1": {
+ "description": "DAC channel1 trigger\n selection",
+ "offset": 3,
+ "size": 3
+ },
+ "TEN1": {
+ "description": "DAC channel1 trigger\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "BOFF1": {
+ "description": "DAC channel1 output buffer\n disable",
+ "offset": 1,
+ "size": 1
+ },
+ "EN1": {
+ "description": "DAC channel1 enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SWTRIGR": {
+ "description": "software trigger register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "SWTRIG2": {
+ "description": "DAC channel2 software\n trigger",
+ "offset": 1,
+ "size": 1
+ },
+ "SWTRIG1": {
+ "description": "DAC channel1 software\n trigger",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DHR12R1": {
+ "description": "channel1 12-bit right-aligned data holding\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC1DHR": {
+ "description": "DAC channel1 12-bit right-aligned\n data",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DHR12L1": {
+ "description": "channel1 12-bit left aligned data holding\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC1DHR": {
+ "description": "DAC channel1 12-bit left-aligned\n data",
+ "offset": 4,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DHR8R1": {
+ "description": "channel1 8-bit right aligned data holding\n register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC1DHR": {
+ "description": "DAC channel1 8-bit right-aligned\n data",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "DHR12R2": {
+ "description": "channel2 12-bit right aligned data holding\n register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC2DHR": {
+ "description": "DAC channel2 12-bit right-aligned\n data",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DHR12L2": {
+ "description": "channel2 12-bit left aligned data holding\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC2DHR": {
+ "description": "DAC channel2 12-bit left-aligned\n data",
+ "offset": 4,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DHR8R2": {
+ "description": "channel2 8-bit right-aligned data holding\n register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC2DHR": {
+ "description": "DAC channel2 8-bit right-aligned\n data",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "DHR12RD": {
+ "description": "Dual DAC 12-bit right-aligned data holding\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC2DHR": {
+ "description": "DAC channel2 12-bit right-aligned\n data",
+ "offset": 16,
+ "size": 12
+ },
+ "DACC1DHR": {
+ "description": "DAC channel1 12-bit right-aligned\n data",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DHR12LD": {
+ "description": "DUAL DAC 12-bit left aligned data holding\n register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC2DHR": {
+ "description": "DAC channel2 12-bit left-aligned\n data",
+ "offset": 20,
+ "size": 12
+ },
+ "DACC1DHR": {
+ "description": "DAC channel1 12-bit left-aligned\n data",
+ "offset": 4,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DHR8RD": {
+ "description": "DUAL DAC 8-bit right aligned data holding\n register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DACC2DHR": {
+ "description": "DAC channel2 8-bit right-aligned\n data",
+ "offset": 8,
+ "size": 8
+ },
+ "DACC1DHR": {
+ "description": "DAC channel1 8-bit right-aligned\n data",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "DOR1": {
+ "description": "channel1 data output register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DACC1DOR": {
+ "description": "DAC channel1 data output",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DOR2": {
+ "description": "channel2 data output register",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DACC2DOR": {
+ "description": "DAC channel2 data output",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAUDR2": {
+ "description": "DAC channel2 DMA underrun\n flag",
+ "offset": 29,
+ "size": 1
+ },
+ "DMAUDR1": {
+ "description": "DAC channel1 DMA underrun\n flag",
+ "offset": 13,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "PWR": {
+ "description": "Power control",
+ "children": {
+ "registers": {
+ "CR": {
+ "description": "power control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 49152,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LPDS": {
+ "description": "Low-power deep sleep",
+ "offset": 0,
+ "size": 1
+ },
+ "PDDS": {
+ "description": "Power down deepsleep",
+ "offset": 1,
+ "size": 1
+ },
+ "CWUF": {
+ "description": "Clear wakeup flag",
+ "offset": 2,
+ "size": 1
+ },
+ "CSBF": {
+ "description": "Clear standby flag",
+ "offset": 3,
+ "size": 1
+ },
+ "PVDE": {
+ "description": "Power voltage detector\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "PLS": {
+ "description": "PVD level selection",
+ "offset": 5,
+ "size": 3
+ },
+ "DBP": {
+ "description": "Disable backup domain write\n protection",
+ "offset": 8,
+ "size": 1
+ },
+ "FPDS": {
+ "description": "Flash power down in Stop\n mode",
+ "offset": 9,
+ "size": 1
+ },
+ "LPLVDS": {
+ "description": "Low-Power Regulator Low Voltage in\n deepsleep",
+ "offset": 10,
+ "size": 1
+ },
+ "MRLVDS": {
+ "description": "Main regulator low voltage in deepsleep\n mode",
+ "offset": 11,
+ "size": 1
+ },
+ "VOS": {
+ "description": "Regulator voltage scaling output\n selection",
+ "offset": 14,
+ "size": 2
+ },
+ "ODEN": {
+ "description": "Over-drive enable",
+ "offset": 16,
+ "size": 1
+ },
+ "ODSWEN": {
+ "description": "Over-drive switching\n enabled",
+ "offset": 17,
+ "size": 1
+ },
+ "UDEN": {
+ "description": "Under-drive enable in stop\n mode",
+ "offset": 18,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CSR": {
+ "description": "power control/status register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "WUF": {
+ "description": "Wakeup flag",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SBF": {
+ "description": "Standby flag",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PVDO": {
+ "description": "PVD output",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "BRR": {
+ "description": "Backup regulator ready",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EWUP": {
+ "description": "Enable WKUP pin",
+ "offset": 8,
+ "size": 1
+ },
+ "BRE": {
+ "description": "Backup regulator enable",
+ "offset": 9,
+ "size": 1
+ },
+ "VOSRDY": {
+ "description": "Regulator voltage scaling output\n selection ready bit",
+ "offset": 14,
+ "size": 1
+ },
+ "ODRDY": {
+ "description": "Over-drive mode ready",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ODSWRDY": {
+ "description": "Over-drive mode switching\n ready",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "UDRDY": {
+ "description": "Under-drive ready flag",
+ "offset": 18,
+ "size": 2
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "IWDG": {
+ "description": "Independent watchdog",
+ "children": {
+ "registers": {
+ "KR": {
+ "description": "Key register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "KEY": {
+ "description": "Key value (write only, read\n 0000h)",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "PR": {
+ "description": "Prescaler register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PR": {
+ "description": "Prescaler divider",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "RLR": {
+ "description": "Reload register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 4095,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RL": {
+ "description": "Watchdog counter reload\n value",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "Status register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "RVU": {
+ "description": "Watchdog counter reload value\n update",
+ "offset": 1,
+ "size": 1
+ },
+ "PVU": {
+ "description": "Watchdog prescaler value\n update",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "WWDG": {
+ "description": "Window watchdog",
+ "children": {
+ "registers": {
+ "CR": {
+ "description": "Control register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 127,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "WDGA": {
+ "description": "Activation bit",
+ "offset": 7,
+ "size": 1
+ },
+ "T": {
+ "description": "7-bit counter (MSB to LSB)",
+ "offset": 0,
+ "size": 7
+ }
+ }
+ }
+ },
+ "CFR": {
+ "description": "Configuration register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 127,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EWI": {
+ "description": "Early wakeup interrupt",
+ "offset": 9,
+ "size": 1
+ },
+ "WDGTB1": {
+ "description": "Timer base",
+ "offset": 8,
+ "size": 1
+ },
+ "WDGTB0": {
+ "description": "Timer base",
+ "offset": 7,
+ "size": 1
+ },
+ "W": {
+ "description": "7-bit window value",
+ "offset": 0,
+ "size": 7
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "Status register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EWIF": {
+ "description": "Early wakeup interrupt\n flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "RTC": {
+ "description": "Real-time clock",
+ "children": {
+ "registers": {
+ "TR": {
+ "description": "time register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PM": {
+ "description": "AM/PM notation",
+ "offset": 22,
+ "size": 1
+ },
+ "HT": {
+ "description": "Hour tens in BCD format",
+ "offset": 20,
+ "size": 2
+ },
+ "HU": {
+ "description": "Hour units in BCD format",
+ "offset": 16,
+ "size": 4
+ },
+ "MNT": {
+ "description": "Minute tens in BCD format",
+ "offset": 12,
+ "size": 3
+ },
+ "MNU": {
+ "description": "Minute units in BCD format",
+ "offset": 8,
+ "size": 4
+ },
+ "ST": {
+ "description": "Second tens in BCD format",
+ "offset": 4,
+ "size": 3
+ },
+ "SU": {
+ "description": "Second units in BCD format",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "DR": {
+ "description": "date register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 8449,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "YT": {
+ "description": "Year tens in BCD format",
+ "offset": 20,
+ "size": 4
+ },
+ "YU": {
+ "description": "Year units in BCD format",
+ "offset": 16,
+ "size": 4
+ },
+ "WDU": {
+ "description": "Week day units",
+ "offset": 13,
+ "size": 3
+ },
+ "MT": {
+ "description": "Month tens in BCD format",
+ "offset": 12,
+ "size": 1
+ },
+ "MU": {
+ "description": "Month units in BCD format",
+ "offset": 8,
+ "size": 4
+ },
+ "DT": {
+ "description": "Date tens in BCD format",
+ "offset": 4,
+ "size": 2
+ },
+ "DU": {
+ "description": "Date units in BCD format",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "CR": {
+ "description": "control register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "COE": {
+ "description": "Calibration output enable",
+ "offset": 23,
+ "size": 1
+ },
+ "OSEL": {
+ "description": "Output selection",
+ "offset": 21,
+ "size": 2
+ },
+ "POL": {
+ "description": "Output polarity",
+ "offset": 20,
+ "size": 1
+ },
+ "BKP": {
+ "description": "Backup",
+ "offset": 18,
+ "size": 1
+ },
+ "SUB1H": {
+ "description": "Subtract 1 hour (winter time\n change)",
+ "offset": 17,
+ "size": 1
+ },
+ "ADD1H": {
+ "description": "Add 1 hour (summer time\n change)",
+ "offset": 16,
+ "size": 1
+ },
+ "TSIE": {
+ "description": "Time-stamp interrupt\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "WUTIE": {
+ "description": "Wakeup timer interrupt\n enable",
+ "offset": 14,
+ "size": 1
+ },
+ "ALRBIE": {
+ "description": "Alarm B interrupt enable",
+ "offset": 13,
+ "size": 1
+ },
+ "ALRAIE": {
+ "description": "Alarm A interrupt enable",
+ "offset": 12,
+ "size": 1
+ },
+ "TSE": {
+ "description": "Time stamp enable",
+ "offset": 11,
+ "size": 1
+ },
+ "WUTE": {
+ "description": "Wakeup timer enable",
+ "offset": 10,
+ "size": 1
+ },
+ "ALRBE": {
+ "description": "Alarm B enable",
+ "offset": 9,
+ "size": 1
+ },
+ "ALRAE": {
+ "description": "Alarm A enable",
+ "offset": 8,
+ "size": 1
+ },
+ "DCE": {
+ "description": "Coarse digital calibration\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "FMT": {
+ "description": "Hour format",
+ "offset": 6,
+ "size": 1
+ },
+ "REFCKON": {
+ "description": "Reference clock detection enable (50 or\n 60 Hz)",
+ "offset": 4,
+ "size": 1
+ },
+ "TSEDGE": {
+ "description": "Time-stamp event active\n edge",
+ "offset": 3,
+ "size": 1
+ },
+ "WCKSEL": {
+ "description": "Wakeup clock selection",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "ISR": {
+ "description": "initialization and status\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 7,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ALRAWF": {
+ "description": "Alarm A write flag",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ALRBWF": {
+ "description": "Alarm B write flag",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "WUTWF": {
+ "description": "Wakeup timer write flag",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SHPF": {
+ "description": "Shift operation pending",
+ "offset": 3,
+ "size": 1
+ },
+ "INITS": {
+ "description": "Initialization status flag",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "RSF": {
+ "description": "Registers synchronization\n flag",
+ "offset": 5,
+ "size": 1
+ },
+ "INITF": {
+ "description": "Initialization flag",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "INIT": {
+ "description": "Initialization mode",
+ "offset": 7,
+ "size": 1
+ },
+ "ALRAF": {
+ "description": "Alarm A flag",
+ "offset": 8,
+ "size": 1
+ },
+ "ALRBF": {
+ "description": "Alarm B flag",
+ "offset": 9,
+ "size": 1
+ },
+ "WUTF": {
+ "description": "Wakeup timer flag",
+ "offset": 10,
+ "size": 1
+ },
+ "TSF": {
+ "description": "Time-stamp flag",
+ "offset": 11,
+ "size": 1
+ },
+ "TSOVF": {
+ "description": "Time-stamp overflow flag",
+ "offset": 12,
+ "size": 1
+ },
+ "TAMP1F": {
+ "description": "Tamper detection flag",
+ "offset": 13,
+ "size": 1
+ },
+ "TAMP2F": {
+ "description": "TAMPER2 detection flag",
+ "offset": 14,
+ "size": 1
+ },
+ "RECALPF": {
+ "description": "Recalibration pending Flag",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "PRER": {
+ "description": "prescaler register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 8323327,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PREDIV_A": {
+ "description": "Asynchronous prescaler\n factor",
+ "offset": 16,
+ "size": 7
+ },
+ "PREDIV_S": {
+ "description": "Synchronous prescaler\n factor",
+ "offset": 0,
+ "size": 15
+ }
+ }
+ }
+ },
+ "WUTR": {
+ "description": "wakeup timer register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 65535,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "WUT": {
+ "description": "Wakeup auto-reload value\n bits",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CALIBR": {
+ "description": "calibration register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DCS": {
+ "description": "Digital calibration sign",
+ "offset": 7,
+ "size": 1
+ },
+ "DC": {
+ "description": "Digital calibration",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "ALRMAR": {
+ "description": "alarm A register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MSK4": {
+ "description": "Alarm A date mask",
+ "offset": 31,
+ "size": 1
+ },
+ "WDSEL": {
+ "description": "Week day selection",
+ "offset": 30,
+ "size": 1
+ },
+ "DT": {
+ "description": "Date tens in BCD format",
+ "offset": 28,
+ "size": 2
+ },
+ "DU": {
+ "description": "Date units or day in BCD\n format",
+ "offset": 24,
+ "size": 4
+ },
+ "MSK3": {
+ "description": "Alarm A hours mask",
+ "offset": 23,
+ "size": 1
+ },
+ "PM": {
+ "description": "AM/PM notation",
+ "offset": 22,
+ "size": 1
+ },
+ "HT": {
+ "description": "Hour tens in BCD format",
+ "offset": 20,
+ "size": 2
+ },
+ "HU": {
+ "description": "Hour units in BCD format",
+ "offset": 16,
+ "size": 4
+ },
+ "MSK2": {
+ "description": "Alarm A minutes mask",
+ "offset": 15,
+ "size": 1
+ },
+ "MNT": {
+ "description": "Minute tens in BCD format",
+ "offset": 12,
+ "size": 3
+ },
+ "MNU": {
+ "description": "Minute units in BCD format",
+ "offset": 8,
+ "size": 4
+ },
+ "MSK1": {
+ "description": "Alarm A seconds mask",
+ "offset": 7,
+ "size": 1
+ },
+ "ST": {
+ "description": "Second tens in BCD format",
+ "offset": 4,
+ "size": 3
+ },
+ "SU": {
+ "description": "Second units in BCD format",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "ALRMBR": {
+ "description": "alarm B register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MSK4": {
+ "description": "Alarm B date mask",
+ "offset": 31,
+ "size": 1
+ },
+ "WDSEL": {
+ "description": "Week day selection",
+ "offset": 30,
+ "size": 1
+ },
+ "DT": {
+ "description": "Date tens in BCD format",
+ "offset": 28,
+ "size": 2
+ },
+ "DU": {
+ "description": "Date units or day in BCD\n format",
+ "offset": 24,
+ "size": 4
+ },
+ "MSK3": {
+ "description": "Alarm B hours mask",
+ "offset": 23,
+ "size": 1
+ },
+ "PM": {
+ "description": "AM/PM notation",
+ "offset": 22,
+ "size": 1
+ },
+ "HT": {
+ "description": "Hour tens in BCD format",
+ "offset": 20,
+ "size": 2
+ },
+ "HU": {
+ "description": "Hour units in BCD format",
+ "offset": 16,
+ "size": 4
+ },
+ "MSK2": {
+ "description": "Alarm B minutes mask",
+ "offset": 15,
+ "size": 1
+ },
+ "MNT": {
+ "description": "Minute tens in BCD format",
+ "offset": 12,
+ "size": 3
+ },
+ "MNU": {
+ "description": "Minute units in BCD format",
+ "offset": 8,
+ "size": 4
+ },
+ "MSK1": {
+ "description": "Alarm B seconds mask",
+ "offset": 7,
+ "size": 1
+ },
+ "ST": {
+ "description": "Second tens in BCD format",
+ "offset": 4,
+ "size": 3
+ },
+ "SU": {
+ "description": "Second units in BCD format",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "WPR": {
+ "description": "write protection register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "KEY": {
+ "description": "Write protection key",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "SSR": {
+ "description": "sub second register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "SS": {
+ "description": "Sub second value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "SHIFTR": {
+ "description": "shift control register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "ADD1S": {
+ "description": "Add one second",
+ "offset": 31,
+ "size": 1
+ },
+ "SUBFS": {
+ "description": "Subtract a fraction of a\n second",
+ "offset": 0,
+ "size": 15
+ }
+ }
+ }
+ },
+ "TSTR": {
+ "description": "time stamp time register",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "ALARMOUTTYPE": {
+ "description": "AFO_ALARM output type",
+ "offset": 18,
+ "size": 1
+ },
+ "TSINSEL": {
+ "description": "TIMESTAMP mapping",
+ "offset": 17,
+ "size": 1
+ },
+ "TAMP1INSEL": {
+ "description": "TAMPER1 mapping",
+ "offset": 16,
+ "size": 1
+ },
+ "TAMPIE": {
+ "description": "Tamper interrupt enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TAMP1TRG": {
+ "description": "Active level for tamper 1",
+ "offset": 1,
+ "size": 1
+ },
+ "TAMP1E": {
+ "description": "Tamper 1 detection enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "TSDR": {
+ "description": "time stamp date register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "WDU": {
+ "description": "Week day units",
+ "offset": 13,
+ "size": 3
+ },
+ "MT": {
+ "description": "Month tens in BCD format",
+ "offset": 12,
+ "size": 1
+ },
+ "MU": {
+ "description": "Month units in BCD format",
+ "offset": 8,
+ "size": 4
+ },
+ "DT": {
+ "description": "Date tens in BCD format",
+ "offset": 4,
+ "size": 2
+ },
+ "DU": {
+ "description": "Date units in BCD format",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "TSSSR": {
+ "description": "timestamp sub second register",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "SS": {
+ "description": "Sub second value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CALR": {
+ "description": "calibration register",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CALP": {
+ "description": "Increase frequency of RTC by 488.5\n ppm",
+ "offset": 15,
+ "size": 1
+ },
+ "CALW8": {
+ "description": "Use an 8-second calibration cycle\n period",
+ "offset": 14,
+ "size": 1
+ },
+ "CALW16": {
+ "description": "Use a 16-second calibration cycle\n period",
+ "offset": 13,
+ "size": 1
+ },
+ "CALM": {
+ "description": "Calibration minus",
+ "offset": 0,
+ "size": 9
+ }
+ }
+ }
+ },
+ "TAFCR": {
+ "description": "tamper and alternate function configuration\n register",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ALARMOUTTYPE": {
+ "description": "AFO_ALARM output type",
+ "offset": 18,
+ "size": 1
+ },
+ "TSINSEL": {
+ "description": "TIMESTAMP mapping",
+ "offset": 17,
+ "size": 1
+ },
+ "TAMP1INSEL": {
+ "description": "TAMPER1 mapping",
+ "offset": 16,
+ "size": 1
+ },
+ "TAMPPUDIS": {
+ "description": "TAMPER pull-up disable",
+ "offset": 15,
+ "size": 1
+ },
+ "TAMPPRCH": {
+ "description": "Tamper precharge duration",
+ "offset": 13,
+ "size": 2
+ },
+ "TAMPFLT": {
+ "description": "Tamper filter count",
+ "offset": 11,
+ "size": 2
+ },
+ "TAMPFREQ": {
+ "description": "Tamper sampling frequency",
+ "offset": 8,
+ "size": 3
+ },
+ "TAMPTS": {
+ "description": "Activate timestamp on tamper detection\n event",
+ "offset": 7,
+ "size": 1
+ },
+ "TAMP2TRG": {
+ "description": "Active level for tamper 2",
+ "offset": 4,
+ "size": 1
+ },
+ "TAMP2E": {
+ "description": "Tamper 2 detection enable",
+ "offset": 3,
+ "size": 1
+ },
+ "TAMPIE": {
+ "description": "Tamper interrupt enable",
+ "offset": 2,
+ "size": 1
+ },
+ "TAMP1TRG": {
+ "description": "Active level for tamper 1",
+ "offset": 1,
+ "size": 1
+ },
+ "TAMP1E": {
+ "description": "Tamper 1 detection enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "ALRMASSR": {
+ "description": "alarm A sub second register",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MASKSS": {
+ "description": "Mask the most-significant bits starting\n at this bit",
+ "offset": 24,
+ "size": 4
+ },
+ "SS": {
+ "description": "Sub seconds value",
+ "offset": 0,
+ "size": 15
+ }
+ }
+ }
+ },
+ "ALRMBSSR": {
+ "description": "alarm B sub second register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MASKSS": {
+ "description": "Mask the most-significant bits starting\n at this bit",
+ "offset": 24,
+ "size": 4
+ },
+ "SS": {
+ "description": "Sub seconds value",
+ "offset": 0,
+ "size": 15
+ }
+ }
+ }
+ },
+ "BKP0R": {
+ "description": "backup register",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP1R": {
+ "description": "backup register",
+ "offset": 84,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP2R": {
+ "description": "backup register",
+ "offset": 88,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP3R": {
+ "description": "backup register",
+ "offset": 92,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP4R": {
+ "description": "backup register",
+ "offset": 96,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP5R": {
+ "description": "backup register",
+ "offset": 100,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP6R": {
+ "description": "backup register",
+ "offset": 104,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP7R": {
+ "description": "backup register",
+ "offset": 108,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP8R": {
+ "description": "backup register",
+ "offset": 112,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP9R": {
+ "description": "backup register",
+ "offset": 116,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP10R": {
+ "description": "backup register",
+ "offset": 120,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP11R": {
+ "description": "backup register",
+ "offset": 124,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP12R": {
+ "description": "backup register",
+ "offset": 128,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP13R": {
+ "description": "backup register",
+ "offset": 132,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP14R": {
+ "description": "backup register",
+ "offset": 136,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP15R": {
+ "description": "backup register",
+ "offset": 140,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP16R": {
+ "description": "backup register",
+ "offset": 144,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP17R": {
+ "description": "backup register",
+ "offset": 148,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP18R": {
+ "description": "backup register",
+ "offset": 152,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "BKP19R": {
+ "description": "backup register",
+ "offset": 156,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "BKP": {
+ "description": "BKP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "UART4": {
+ "description": "Universal synchronous asynchronous receiver\n transmitter",
+ "children": {
+ "registers": {
+ "SR": {
+ "description": "Status register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 12582912,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LBD": {
+ "description": "LIN break detection flag",
+ "offset": 8,
+ "size": 1
+ },
+ "TXE": {
+ "description": "Transmit data register\n empty",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TC": {
+ "description": "Transmission complete",
+ "offset": 6,
+ "size": 1
+ },
+ "RXNE": {
+ "description": "Read data register not\n empty",
+ "offset": 5,
+ "size": 1
+ },
+ "IDLE": {
+ "description": "IDLE line detected",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ORE": {
+ "description": "Overrun error",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NF": {
+ "description": "Noise detected flag",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "FE": {
+ "description": "Framing error",
+ "offset": 1,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PE": {
+ "description": "Parity error",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "DR": {
+ "description": "Data register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DR": {
+ "description": "Data value",
+ "offset": 0,
+ "size": 9
+ }
+ }
+ }
+ },
+ "BRR": {
+ "description": "Baud rate register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DIV_Mantissa": {
+ "description": "mantissa of USARTDIV",
+ "offset": 4,
+ "size": 12
+ },
+ "DIV_Fraction": {
+ "description": "fraction of USARTDIV",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "CR1": {
+ "description": "Control register 1",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OVER8": {
+ "description": "Oversampling mode",
+ "offset": 15,
+ "size": 1
+ },
+ "UE": {
+ "description": "USART enable",
+ "offset": 13,
+ "size": 1
+ },
+ "M": {
+ "description": "Word length",
+ "offset": 12,
+ "size": 1
+ },
+ "WAKE": {
+ "description": "Wakeup method",
+ "offset": 11,
+ "size": 1
+ },
+ "PCE": {
+ "description": "Parity control enable",
+ "offset": 10,
+ "size": 1
+ },
+ "PS": {
+ "description": "Parity selection",
+ "offset": 9,
+ "size": 1
+ },
+ "PEIE": {
+ "description": "PE interrupt enable",
+ "offset": 8,
+ "size": 1
+ },
+ "TXEIE": {
+ "description": "TXE interrupt enable",
+ "offset": 7,
+ "size": 1
+ },
+ "TCIE": {
+ "description": "Transmission complete interrupt\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "RXNEIE": {
+ "description": "RXNE interrupt enable",
+ "offset": 5,
+ "size": 1
+ },
+ "IDLEIE": {
+ "description": "IDLE interrupt enable",
+ "offset": 4,
+ "size": 1
+ },
+ "TE": {
+ "description": "Transmitter enable",
+ "offset": 3,
+ "size": 1
+ },
+ "RE": {
+ "description": "Receiver enable",
+ "offset": 2,
+ "size": 1
+ },
+ "RWU": {
+ "description": "Receiver wakeup",
+ "offset": 1,
+ "size": 1
+ },
+ "SBK": {
+ "description": "Send break",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "Control register 2",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "LINEN": {
+ "description": "LIN mode enable",
+ "offset": 14,
+ "size": 1
+ },
+ "STOP": {
+ "description": "STOP bits",
+ "offset": 12,
+ "size": 2
+ },
+ "LBDIE": {
+ "description": "LIN break detection interrupt\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "LBDL": {
+ "description": "lin break detection length",
+ "offset": 5,
+ "size": 1
+ },
+ "ADD": {
+ "description": "Address of the USART node",
+ "offset": 0,
+ "size": 4
+ }
+ }
+ }
+ },
+ "CR3": {
+ "description": "Control register 3",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ONEBIT": {
+ "description": "One sample bit method\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "DMAT": {
+ "description": "DMA enable transmitter",
+ "offset": 7,
+ "size": 1
+ },
+ "DMAR": {
+ "description": "DMA enable receiver",
+ "offset": 6,
+ "size": 1
+ },
+ "HDSEL": {
+ "description": "Half-duplex selection",
+ "offset": 3,
+ "size": 1
+ },
+ "IRLP": {
+ "description": "IrDA low-power",
+ "offset": 2,
+ "size": 1
+ },
+ "IREN": {
+ "description": "IrDA mode enable",
+ "offset": 1,
+ "size": 1
+ },
+ "EIE": {
+ "description": "Error interrupt enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "OTG_FS_DEVICE": {
+ "description": "USB on the go full speed",
+ "children": {
+ "registers": {
+ "FS_DCFG": {
+ "description": "OTG_FS device configuration register\n (OTG_FS_DCFG)",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 35651584,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DSPD": {
+ "description": "Device speed",
+ "offset": 0,
+ "size": 2
+ },
+ "NZLSOHSK": {
+ "description": "Non-zero-length status OUT\n handshake",
+ "offset": 2,
+ "size": 1
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 4,
+ "size": 7
+ },
+ "PFIVL": {
+ "description": "Periodic frame interval",
+ "offset": 11,
+ "size": 2
+ }
+ }
+ }
+ },
+ "FS_DCTL": {
+ "description": "OTG_FS device control register\n (OTG_FS_DCTL)",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RWUSIG": {
+ "description": "Remote wakeup signaling",
+ "offset": 0,
+ "size": 1
+ },
+ "SDIS": {
+ "description": "Soft disconnect",
+ "offset": 1,
+ "size": 1
+ },
+ "GINSTS": {
+ "description": "Global IN NAK status",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "GONSTS": {
+ "description": "Global OUT NAK status",
+ "offset": 3,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TCTL": {
+ "description": "Test control",
+ "offset": 4,
+ "size": 3
+ },
+ "SGINAK": {
+ "description": "Set global IN NAK",
+ "offset": 7,
+ "size": 1
+ },
+ "CGINAK": {
+ "description": "Clear global IN NAK",
+ "offset": 8,
+ "size": 1
+ },
+ "SGONAK": {
+ "description": "Set global OUT NAK",
+ "offset": 9,
+ "size": 1
+ },
+ "CGONAK": {
+ "description": "Clear global OUT NAK",
+ "offset": 10,
+ "size": 1
+ },
+ "POPRGDNE": {
+ "description": "Power-on programming done",
+ "offset": 11,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_DSTS": {
+ "description": "OTG_FS device status register\n (OTG_FS_DSTS)",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 16,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "SUSPSTS": {
+ "description": "Suspend status",
+ "offset": 0,
+ "size": 1
+ },
+ "ENUMSPD": {
+ "description": "Enumerated speed",
+ "offset": 1,
+ "size": 2
+ },
+ "EERR": {
+ "description": "Erratic error",
+ "offset": 3,
+ "size": 1
+ },
+ "FNSOF": {
+ "description": "Frame number of the received\n SOF",
+ "offset": 8,
+ "size": 14
+ }
+ }
+ }
+ },
+ "FS_DIEPMSK": {
+ "description": "OTG_FS device IN endpoint common interrupt\n mask register (OTG_FS_DIEPMSK)",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed interrupt\n mask",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDM": {
+ "description": "Endpoint disabled interrupt\n mask",
+ "offset": 1,
+ "size": 1
+ },
+ "TOM": {
+ "description": "Timeout condition mask (Non-isochronous\n endpoints)",
+ "offset": 3,
+ "size": 1
+ },
+ "ITTXFEMSK": {
+ "description": "IN token received when TxFIFO empty\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "INEPNMM": {
+ "description": "IN token received with EP mismatch\n mask",
+ "offset": 5,
+ "size": 1
+ },
+ "INEPNEM": {
+ "description": "IN endpoint NAK effective\n mask",
+ "offset": 6,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_DOEPMSK": {
+ "description": "OTG_FS device OUT endpoint common interrupt\n mask register (OTG_FS_DOEPMSK)",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed interrupt\n mask",
+ "offset": 0,
+ "size": 1
+ },
+ "EPDM": {
+ "description": "Endpoint disabled interrupt\n mask",
+ "offset": 1,
+ "size": 1
+ },
+ "STUPM": {
+ "description": "SETUP phase done mask",
+ "offset": 3,
+ "size": 1
+ },
+ "OTEPDM": {
+ "description": "OUT token received when endpoint\n disabled mask",
+ "offset": 4,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_DAINT": {
+ "description": "OTG_FS device all endpoints interrupt\n register (OTG_FS_DAINT)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "IEPINT": {
+ "description": "IN endpoint interrupt bits",
+ "offset": 0,
+ "size": 16
+ },
+ "OEPINT": {
+ "description": "OUT endpoint interrupt\n bits",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_DAINTMSK": {
+ "description": "OTG_FS all endpoints interrupt mask register\n (OTG_FS_DAINTMSK)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IEPM": {
+ "description": "IN EP interrupt mask bits",
+ "offset": 0,
+ "size": 16
+ },
+ "OEPINT": {
+ "description": "OUT endpoint interrupt\n bits",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DVBUSDIS": {
+ "description": "OTG_FS device VBUS discharge time\n register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 6103,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "VBUSDT": {
+ "description": "Device VBUS discharge time",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DVBUSPULSE": {
+ "description": "OTG_FS device VBUS pulsing time\n register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 1464,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DVBUSP": {
+ "description": "Device VBUS pulsing time",
+ "offset": 0,
+ "size": 12
+ }
+ }
+ }
+ },
+ "DIEPEMPMSK": {
+ "description": "OTG_FS device IN endpoint FIFO empty\n interrupt mask register",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INEPTXFEM": {
+ "description": "IN EP Tx FIFO empty interrupt mask\n bits",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_DIEPCTL0": {
+ "description": "OTG_FS device control IN endpoint 0 control\n register (OTG_FS_DIEPCTL0)",
+ "offset": 256,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 2
+ },
+ "USBAEP": {
+ "description": "USB active endpoint",
+ "offset": 15,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAK status",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2,
+ "access": "read-only"
+ },
+ "STALL": {
+ "description": "STALL handshake",
+ "offset": 21,
+ "size": 1
+ },
+ "TXFNUM": {
+ "description": "TxFIFO number",
+ "offset": 22,
+ "size": 4
+ },
+ "CNAK": {
+ "description": "Clear NAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "Set NAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "Endpoint disable",
+ "offset": 30,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EPENA": {
+ "description": "Endpoint enable",
+ "offset": 31,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "DIEPCTL1": {
+ "description": "OTG device endpoint-1 control\n register",
+ "offset": 288,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EPENA": {
+ "description": "EPENA",
+ "offset": 31,
+ "size": 1
+ },
+ "EPDIS": {
+ "description": "EPDIS",
+ "offset": 30,
+ "size": 1
+ },
+ "SODDFRM_SD1PID": {
+ "description": "SODDFRM/SD1PID",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "SD0PID/SEVNFRM",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "SNAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CNAK": {
+ "description": "CNAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "TXFNUM": {
+ "description": "TXFNUM",
+ "offset": 22,
+ "size": 4
+ },
+ "Stall": {
+ "description": "Stall",
+ "offset": 21,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "EPTYP",
+ "offset": 18,
+ "size": 2
+ },
+ "NAKSTS": {
+ "description": "NAKSTS",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EONUM_DPID": {
+ "description": "EONUM/DPID",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "USBAEP": {
+ "description": "USBAEP",
+ "offset": 15,
+ "size": 1
+ },
+ "MPSIZ": {
+ "description": "MPSIZ",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "DIEPCTL2": {
+ "description": "OTG device endpoint-2 control\n register",
+ "offset": 320,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EPENA": {
+ "description": "EPENA",
+ "offset": 31,
+ "size": 1
+ },
+ "EPDIS": {
+ "description": "EPDIS",
+ "offset": 30,
+ "size": 1
+ },
+ "SODDFRM": {
+ "description": "SODDFRM",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "SD0PID/SEVNFRM",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "SNAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CNAK": {
+ "description": "CNAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "TXFNUM": {
+ "description": "TXFNUM",
+ "offset": 22,
+ "size": 4
+ },
+ "Stall": {
+ "description": "Stall",
+ "offset": 21,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "EPTYP",
+ "offset": 18,
+ "size": 2
+ },
+ "NAKSTS": {
+ "description": "NAKSTS",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EONUM_DPID": {
+ "description": "EONUM/DPID",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "USBAEP": {
+ "description": "USBAEP",
+ "offset": 15,
+ "size": 1
+ },
+ "MPSIZ": {
+ "description": "MPSIZ",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "DIEPCTL3": {
+ "description": "OTG device endpoint-3 control\n register",
+ "offset": 352,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EPENA": {
+ "description": "EPENA",
+ "offset": 31,
+ "size": 1
+ },
+ "EPDIS": {
+ "description": "EPDIS",
+ "offset": 30,
+ "size": 1
+ },
+ "SODDFRM": {
+ "description": "SODDFRM",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "SD0PID/SEVNFRM",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "SNAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CNAK": {
+ "description": "CNAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "TXFNUM": {
+ "description": "TXFNUM",
+ "offset": 22,
+ "size": 4
+ },
+ "Stall": {
+ "description": "Stall",
+ "offset": 21,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "EPTYP",
+ "offset": 18,
+ "size": 2
+ },
+ "NAKSTS": {
+ "description": "NAKSTS",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EONUM_DPID": {
+ "description": "EONUM/DPID",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "USBAEP": {
+ "description": "USBAEP",
+ "offset": 15,
+ "size": 1
+ },
+ "MPSIZ": {
+ "description": "MPSIZ",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "DOEPCTL0": {
+ "description": "device endpoint-0 control\n register",
+ "offset": 768,
+ "size": 32,
+ "reset_value": 32768,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EPENA": {
+ "description": "EPENA",
+ "offset": 31,
+ "size": 1,
+ "access": "write-only"
+ },
+ "EPDIS": {
+ "description": "EPDIS",
+ "offset": 30,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SNAK": {
+ "description": "SNAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CNAK": {
+ "description": "CNAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "Stall": {
+ "description": "Stall",
+ "offset": 21,
+ "size": 1
+ },
+ "SNPM": {
+ "description": "SNPM",
+ "offset": 20,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "EPTYP",
+ "offset": 18,
+ "size": 2,
+ "access": "read-only"
+ },
+ "NAKSTS": {
+ "description": "NAKSTS",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "USBAEP": {
+ "description": "USBAEP",
+ "offset": 15,
+ "size": 1,
+ "access": "read-only"
+ },
+ "MPSIZ": {
+ "description": "MPSIZ",
+ "offset": 0,
+ "size": 2,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "DOEPCTL1": {
+ "description": "device endpoint-1 control\n register",
+ "offset": 800,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EPENA": {
+ "description": "EPENA",
+ "offset": 31,
+ "size": 1
+ },
+ "EPDIS": {
+ "description": "EPDIS",
+ "offset": 30,
+ "size": 1
+ },
+ "SODDFRM": {
+ "description": "SODDFRM",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "SD0PID/SEVNFRM",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "SNAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CNAK": {
+ "description": "CNAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "Stall": {
+ "description": "Stall",
+ "offset": 21,
+ "size": 1
+ },
+ "SNPM": {
+ "description": "SNPM",
+ "offset": 20,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "EPTYP",
+ "offset": 18,
+ "size": 2
+ },
+ "NAKSTS": {
+ "description": "NAKSTS",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EONUM_DPID": {
+ "description": "EONUM/DPID",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "USBAEP": {
+ "description": "USBAEP",
+ "offset": 15,
+ "size": 1
+ },
+ "MPSIZ": {
+ "description": "MPSIZ",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "DOEPCTL2": {
+ "description": "device endpoint-2 control\n register",
+ "offset": 832,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EPENA": {
+ "description": "EPENA",
+ "offset": 31,
+ "size": 1
+ },
+ "EPDIS": {
+ "description": "EPDIS",
+ "offset": 30,
+ "size": 1
+ },
+ "SODDFRM": {
+ "description": "SODDFRM",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "SD0PID/SEVNFRM",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "SNAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CNAK": {
+ "description": "CNAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "Stall": {
+ "description": "Stall",
+ "offset": 21,
+ "size": 1
+ },
+ "SNPM": {
+ "description": "SNPM",
+ "offset": 20,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "EPTYP",
+ "offset": 18,
+ "size": 2
+ },
+ "NAKSTS": {
+ "description": "NAKSTS",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EONUM_DPID": {
+ "description": "EONUM/DPID",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "USBAEP": {
+ "description": "USBAEP",
+ "offset": 15,
+ "size": 1
+ },
+ "MPSIZ": {
+ "description": "MPSIZ",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "DOEPCTL3": {
+ "description": "device endpoint-3 control\n register",
+ "offset": 864,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "EPENA": {
+ "description": "EPENA",
+ "offset": 31,
+ "size": 1
+ },
+ "EPDIS": {
+ "description": "EPDIS",
+ "offset": 30,
+ "size": 1
+ },
+ "SODDFRM": {
+ "description": "SODDFRM",
+ "offset": 29,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SD0PID_SEVNFRM": {
+ "description": "SD0PID/SEVNFRM",
+ "offset": 28,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SNAK": {
+ "description": "SNAK",
+ "offset": 27,
+ "size": 1,
+ "access": "write-only"
+ },
+ "CNAK": {
+ "description": "CNAK",
+ "offset": 26,
+ "size": 1,
+ "access": "write-only"
+ },
+ "Stall": {
+ "description": "Stall",
+ "offset": 21,
+ "size": 1
+ },
+ "SNPM": {
+ "description": "SNPM",
+ "offset": 20,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "EPTYP",
+ "offset": 18,
+ "size": 2
+ },
+ "NAKSTS": {
+ "description": "NAKSTS",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "EONUM_DPID": {
+ "description": "EONUM/DPID",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "USBAEP": {
+ "description": "USBAEP",
+ "offset": 15,
+ "size": 1
+ },
+ "MPSIZ": {
+ "description": "MPSIZ",
+ "offset": 0,
+ "size": 11
+ }
+ }
+ }
+ },
+ "DIEPINT0": {
+ "description": "device endpoint-x interrupt\n register",
+ "offset": 264,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TXFE": {
+ "description": "TXFE",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "INEPNE": {
+ "description": "INEPNE",
+ "offset": 6,
+ "size": 1
+ },
+ "ITTXFE": {
+ "description": "ITTXFE",
+ "offset": 4,
+ "size": 1
+ },
+ "TOC": {
+ "description": "TOC",
+ "offset": 3,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "EPDISD",
+ "offset": 1,
+ "size": 1
+ },
+ "XFRC": {
+ "description": "XFRC",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DIEPINT1": {
+ "description": "device endpoint-1 interrupt\n register",
+ "offset": 296,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TXFE": {
+ "description": "TXFE",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "INEPNE": {
+ "description": "INEPNE",
+ "offset": 6,
+ "size": 1
+ },
+ "ITTXFE": {
+ "description": "ITTXFE",
+ "offset": 4,
+ "size": 1
+ },
+ "TOC": {
+ "description": "TOC",
+ "offset": 3,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "EPDISD",
+ "offset": 1,
+ "size": 1
+ },
+ "XFRC": {
+ "description": "XFRC",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DIEPINT2": {
+ "description": "device endpoint-2 interrupt\n register",
+ "offset": 328,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TXFE": {
+ "description": "TXFE",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "INEPNE": {
+ "description": "INEPNE",
+ "offset": 6,
+ "size": 1
+ },
+ "ITTXFE": {
+ "description": "ITTXFE",
+ "offset": 4,
+ "size": 1
+ },
+ "TOC": {
+ "description": "TOC",
+ "offset": 3,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "EPDISD",
+ "offset": 1,
+ "size": 1
+ },
+ "XFRC": {
+ "description": "XFRC",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DIEPINT3": {
+ "description": "device endpoint-3 interrupt\n register",
+ "offset": 360,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TXFE": {
+ "description": "TXFE",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "INEPNE": {
+ "description": "INEPNE",
+ "offset": 6,
+ "size": 1
+ },
+ "ITTXFE": {
+ "description": "ITTXFE",
+ "offset": 4,
+ "size": 1
+ },
+ "TOC": {
+ "description": "TOC",
+ "offset": 3,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "EPDISD",
+ "offset": 1,
+ "size": 1
+ },
+ "XFRC": {
+ "description": "XFRC",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DOEPINT0": {
+ "description": "device endpoint-0 interrupt\n register",
+ "offset": 776,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "B2BSTUP": {
+ "description": "B2BSTUP",
+ "offset": 6,
+ "size": 1
+ },
+ "OTEPDIS": {
+ "description": "OTEPDIS",
+ "offset": 4,
+ "size": 1
+ },
+ "STUP": {
+ "description": "STUP",
+ "offset": 3,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "EPDISD",
+ "offset": 1,
+ "size": 1
+ },
+ "XFRC": {
+ "description": "XFRC",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DOEPINT1": {
+ "description": "device endpoint-1 interrupt\n register",
+ "offset": 808,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "B2BSTUP": {
+ "description": "B2BSTUP",
+ "offset": 6,
+ "size": 1
+ },
+ "OTEPDIS": {
+ "description": "OTEPDIS",
+ "offset": 4,
+ "size": 1
+ },
+ "STUP": {
+ "description": "STUP",
+ "offset": 3,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "EPDISD",
+ "offset": 1,
+ "size": 1
+ },
+ "XFRC": {
+ "description": "XFRC",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DOEPINT2": {
+ "description": "device endpoint-2 interrupt\n register",
+ "offset": 840,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "B2BSTUP": {
+ "description": "B2BSTUP",
+ "offset": 6,
+ "size": 1
+ },
+ "OTEPDIS": {
+ "description": "OTEPDIS",
+ "offset": 4,
+ "size": 1
+ },
+ "STUP": {
+ "description": "STUP",
+ "offset": 3,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "EPDISD",
+ "offset": 1,
+ "size": 1
+ },
+ "XFRC": {
+ "description": "XFRC",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DOEPINT3": {
+ "description": "device endpoint-3 interrupt\n register",
+ "offset": 872,
+ "size": 32,
+ "reset_value": 128,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "B2BSTUP": {
+ "description": "B2BSTUP",
+ "offset": 6,
+ "size": 1
+ },
+ "OTEPDIS": {
+ "description": "OTEPDIS",
+ "offset": 4,
+ "size": 1
+ },
+ "STUP": {
+ "description": "STUP",
+ "offset": 3,
+ "size": 1
+ },
+ "EPDISD": {
+ "description": "EPDISD",
+ "offset": 1,
+ "size": 1
+ },
+ "XFRC": {
+ "description": "XFRC",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DIEPTSIZ0": {
+ "description": "device endpoint-0 transfer size\n register",
+ "offset": 272,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 2
+ },
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 7
+ }
+ }
+ }
+ },
+ "DOEPTSIZ0": {
+ "description": "device OUT endpoint-0 transfer size\n register",
+ "offset": 784,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "STUPCNT": {
+ "description": "SETUP packet count",
+ "offset": 29,
+ "size": 2
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 1
+ },
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 7
+ }
+ }
+ }
+ },
+ "DIEPTSIZ1": {
+ "description": "device endpoint-1 transfer size\n register",
+ "offset": 304,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MCNT": {
+ "description": "Multi count",
+ "offset": 29,
+ "size": 2
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ }
+ }
+ }
+ },
+ "DIEPTSIZ2": {
+ "description": "device endpoint-2 transfer size\n register",
+ "offset": 336,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MCNT": {
+ "description": "Multi count",
+ "offset": 29,
+ "size": 2
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ }
+ }
+ }
+ },
+ "DIEPTSIZ3": {
+ "description": "device endpoint-3 transfer size\n register",
+ "offset": 368,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MCNT": {
+ "description": "Multi count",
+ "offset": 29,
+ "size": 2
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ }
+ }
+ }
+ },
+ "DTXFSTS0": {
+ "description": "OTG_FS device IN endpoint transmit FIFO\n status register",
+ "offset": 280,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "INEPTFSAV": {
+ "description": "IN endpoint TxFIFO space\n available",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DTXFSTS1": {
+ "description": "OTG_FS device IN endpoint transmit FIFO\n status register",
+ "offset": 312,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "INEPTFSAV": {
+ "description": "IN endpoint TxFIFO space\n available",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DTXFSTS2": {
+ "description": "OTG_FS device IN endpoint transmit FIFO\n status register",
+ "offset": 344,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "INEPTFSAV": {
+ "description": "IN endpoint TxFIFO space\n available",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DTXFSTS3": {
+ "description": "OTG_FS device IN endpoint transmit FIFO\n status register",
+ "offset": 376,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "INEPTFSAV": {
+ "description": "IN endpoint TxFIFO space\n available",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DOEPTSIZ1": {
+ "description": "device OUT endpoint-1 transfer size\n register",
+ "offset": 816,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RXDPID_STUPCNT": {
+ "description": "Received data PID/SETUP packet\n count",
+ "offset": 29,
+ "size": 2
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ }
+ }
+ }
+ },
+ "DOEPTSIZ2": {
+ "description": "device OUT endpoint-2 transfer size\n register",
+ "offset": 848,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RXDPID_STUPCNT": {
+ "description": "Received data PID/SETUP packet\n count",
+ "offset": 29,
+ "size": 2
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ }
+ }
+ }
+ },
+ "DOEPTSIZ3": {
+ "description": "device OUT endpoint-3 transfer size\n register",
+ "offset": 880,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RXDPID_STUPCNT": {
+ "description": "Received data PID/SETUP packet\n count",
+ "offset": 29,
+ "size": 2
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "C_ADC": {
+ "description": "Common ADC registers",
+ "children": {
+ "registers": {
+ "CSR": {
+ "description": "ADC Common status register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "OVR3": {
+ "description": "Overrun flag of ADC3",
+ "offset": 21,
+ "size": 1
+ },
+ "STRT3": {
+ "description": "Regular channel Start flag of ADC\n 3",
+ "offset": 20,
+ "size": 1
+ },
+ "JSTRT3": {
+ "description": "Injected channel Start flag of ADC\n 3",
+ "offset": 19,
+ "size": 1
+ },
+ "JEOC3": {
+ "description": "Injected channel end of conversion of\n ADC 3",
+ "offset": 18,
+ "size": 1
+ },
+ "EOC3": {
+ "description": "End of conversion of ADC 3",
+ "offset": 17,
+ "size": 1
+ },
+ "AWD3": {
+ "description": "Analog watchdog flag of ADC\n 3",
+ "offset": 16,
+ "size": 1
+ },
+ "OVR2": {
+ "description": "Overrun flag of ADC 2",
+ "offset": 13,
+ "size": 1
+ },
+ "STRT2": {
+ "description": "Regular channel Start flag of ADC\n 2",
+ "offset": 12,
+ "size": 1
+ },
+ "JSTRT2": {
+ "description": "Injected channel Start flag of ADC\n 2",
+ "offset": 11,
+ "size": 1
+ },
+ "JEOC2": {
+ "description": "Injected channel end of conversion of\n ADC 2",
+ "offset": 10,
+ "size": 1
+ },
+ "EOC2": {
+ "description": "End of conversion of ADC 2",
+ "offset": 9,
+ "size": 1
+ },
+ "AWD2": {
+ "description": "Analog watchdog flag of ADC\n 2",
+ "offset": 8,
+ "size": 1
+ },
+ "OVR1": {
+ "description": "Overrun flag of ADC 1",
+ "offset": 5,
+ "size": 1
+ },
+ "STRT1": {
+ "description": "Regular channel Start flag of ADC\n 1",
+ "offset": 4,
+ "size": 1
+ },
+ "JSTRT1": {
+ "description": "Injected channel Start flag of ADC\n 1",
+ "offset": 3,
+ "size": 1
+ },
+ "JEOC1": {
+ "description": "Injected channel end of conversion of\n ADC 1",
+ "offset": 2,
+ "size": 1
+ },
+ "EOC1": {
+ "description": "End of conversion of ADC 1",
+ "offset": 1,
+ "size": 1
+ },
+ "AWD1": {
+ "description": "Analog watchdog flag of ADC\n 1",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCR": {
+ "description": "ADC common control register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TSVREFE": {
+ "description": "Temperature sensor and VREFINT\n enable",
+ "offset": 23,
+ "size": 1
+ },
+ "VBATE": {
+ "description": "VBAT enable",
+ "offset": 22,
+ "size": 1
+ },
+ "ADCPRE": {
+ "description": "ADC prescaler",
+ "offset": 16,
+ "size": 2
+ },
+ "DMA": {
+ "description": "Direct memory access mode for multi ADC\n mode",
+ "offset": 14,
+ "size": 2
+ },
+ "DDS": {
+ "description": "DMA disable selection for multi-ADC\n mode",
+ "offset": 13,
+ "size": 1
+ },
+ "DELAY": {
+ "description": "Delay between 2 sampling\n phases",
+ "offset": 8,
+ "size": 4
+ },
+ "MULT": {
+ "description": "Multi ADC mode selection",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "CDR": {
+ "description": "ADC common regular data register for dual\n and triple modes",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "DATA2": {
+ "description": "2nd data item of a pair of regular\n conversions",
+ "offset": 16,
+ "size": 16
+ },
+ "DATA1": {
+ "description": "1st data item of a pair of regular\n conversions",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "TIM1": {
+ "description": "Advanced-timers",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CKD": {
+ "description": "Clock division",
+ "offset": 8,
+ "size": 2
+ },
+ "ARPE": {
+ "description": "Auto-reload preload enable",
+ "offset": 7,
+ "size": 1
+ },
+ "CMS": {
+ "description": "Center-aligned mode\n selection",
+ "offset": 5,
+ "size": 2
+ },
+ "DIR": {
+ "description": "Direction",
+ "offset": 4,
+ "size": 1
+ },
+ "OPM": {
+ "description": "One-pulse mode",
+ "offset": 3,
+ "size": 1
+ },
+ "URS": {
+ "description": "Update request source",
+ "offset": 2,
+ "size": 1
+ },
+ "UDIS": {
+ "description": "Update disable",
+ "offset": 1,
+ "size": 1
+ },
+ "CEN": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OIS4": {
+ "description": "Output Idle state 4",
+ "offset": 14,
+ "size": 1
+ },
+ "OIS3N": {
+ "description": "Output Idle state 3",
+ "offset": 13,
+ "size": 1
+ },
+ "OIS3": {
+ "description": "Output Idle state 3",
+ "offset": 12,
+ "size": 1
+ },
+ "OIS2N": {
+ "description": "Output Idle state 2",
+ "offset": 11,
+ "size": 1
+ },
+ "OIS2": {
+ "description": "Output Idle state 2",
+ "offset": 10,
+ "size": 1
+ },
+ "OIS1N": {
+ "description": "Output Idle state 1",
+ "offset": 9,
+ "size": 1
+ },
+ "OIS1": {
+ "description": "Output Idle state 1",
+ "offset": 8,
+ "size": 1
+ },
+ "TI1S": {
+ "description": "TI1 selection",
+ "offset": 7,
+ "size": 1
+ },
+ "MMS": {
+ "description": "Master mode selection",
+ "offset": 4,
+ "size": 3
+ },
+ "CCDS": {
+ "description": "Capture/compare DMA\n selection",
+ "offset": 3,
+ "size": 1
+ },
+ "CCUS": {
+ "description": "Capture/compare control update\n selection",
+ "offset": 2,
+ "size": 1
+ },
+ "CCPC": {
+ "description": "Capture/compare preloaded\n control",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SMCR": {
+ "description": "slave mode control register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ETP": {
+ "description": "External trigger polarity",
+ "offset": 15,
+ "size": 1
+ },
+ "ECE": {
+ "description": "External clock enable",
+ "offset": 14,
+ "size": 1
+ },
+ "ETPS": {
+ "description": "External trigger prescaler",
+ "offset": 12,
+ "size": 2
+ },
+ "ETF": {
+ "description": "External trigger filter",
+ "offset": 8,
+ "size": 4
+ },
+ "MSM": {
+ "description": "Master/Slave mode",
+ "offset": 7,
+ "size": 1
+ },
+ "TS": {
+ "description": "Trigger selection",
+ "offset": 4,
+ "size": 3
+ },
+ "SMS": {
+ "description": "Slave mode selection",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "DIER": {
+ "description": "DMA/Interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TDE": {
+ "description": "Trigger DMA request enable",
+ "offset": 14,
+ "size": 1
+ },
+ "COMDE": {
+ "description": "COM DMA request enable",
+ "offset": 13,
+ "size": 1
+ },
+ "CC4DE": {
+ "description": "Capture/Compare 4 DMA request\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3DE": {
+ "description": "Capture/Compare 3 DMA request\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "CC2DE": {
+ "description": "Capture/Compare 2 DMA request\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC1DE": {
+ "description": "Capture/Compare 1 DMA request\n enable",
+ "offset": 9,
+ "size": 1
+ },
+ "UDE": {
+ "description": "Update DMA request enable",
+ "offset": 8,
+ "size": 1
+ },
+ "TIE": {
+ "description": "Trigger interrupt enable",
+ "offset": 6,
+ "size": 1
+ },
+ "CC4IE": {
+ "description": "Capture/Compare 4 interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3IE": {
+ "description": "Capture/Compare 3 interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2IE": {
+ "description": "Capture/Compare 2 interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IE": {
+ "description": "Capture/Compare 1 interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "UIE": {
+ "description": "Update interrupt enable",
+ "offset": 0,
+ "size": 1
+ },
+ "BIE": {
+ "description": "Break interrupt enable",
+ "offset": 7,
+ "size": 1
+ },
+ "COMIE": {
+ "description": "COM interrupt enable",
+ "offset": 5,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC4OF": {
+ "description": "Capture/Compare 4 overcapture\n flag",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3OF": {
+ "description": "Capture/Compare 3 overcapture\n flag",
+ "offset": 11,
+ "size": 1
+ },
+ "CC2OF": {
+ "description": "Capture/compare 2 overcapture\n flag",
+ "offset": 10,
+ "size": 1
+ },
+ "CC1OF": {
+ "description": "Capture/Compare 1 overcapture\n flag",
+ "offset": 9,
+ "size": 1
+ },
+ "BIF": {
+ "description": "Break interrupt flag",
+ "offset": 7,
+ "size": 1
+ },
+ "TIF": {
+ "description": "Trigger interrupt flag",
+ "offset": 6,
+ "size": 1
+ },
+ "COMIF": {
+ "description": "COM interrupt flag",
+ "offset": 5,
+ "size": 1
+ },
+ "CC4IF": {
+ "description": "Capture/Compare 4 interrupt\n flag",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3IF": {
+ "description": "Capture/Compare 3 interrupt\n flag",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2IF": {
+ "description": "Capture/Compare 2 interrupt\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IF": {
+ "description": "Capture/compare 1 interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "UIF": {
+ "description": "Update interrupt flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EGR": {
+ "description": "event generation register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "BG": {
+ "description": "Break generation",
+ "offset": 7,
+ "size": 1
+ },
+ "TG": {
+ "description": "Trigger generation",
+ "offset": 6,
+ "size": 1
+ },
+ "COMG": {
+ "description": "Capture/Compare control update\n generation",
+ "offset": 5,
+ "size": 1
+ },
+ "CC4G": {
+ "description": "Capture/compare 4\n generation",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3G": {
+ "description": "Capture/compare 3\n generation",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2G": {
+ "description": "Capture/compare 2\n generation",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1G": {
+ "description": "Capture/compare 1\n generation",
+ "offset": 1,
+ "size": 1
+ },
+ "UG": {
+ "description": "Update generation",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Output": {
+ "description": "capture/compare mode register 1 (output\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OC2CE": {
+ "description": "Output Compare 2 clear\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "OC2M": {
+ "description": "Output Compare 2 mode",
+ "offset": 12,
+ "size": 3
+ },
+ "OC2PE": {
+ "description": "Output Compare 2 preload\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "OC2FE": {
+ "description": "Output Compare 2 fast\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC2S": {
+ "description": "Capture/Compare 2\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "OC1CE": {
+ "description": "Output Compare 1 clear\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "OC1M": {
+ "description": "Output Compare 1 mode",
+ "offset": 4,
+ "size": 3
+ },
+ "OC1PE": {
+ "description": "Output Compare 1 preload\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "OC1FE": {
+ "description": "Output Compare 1 fast\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR1_Input": {
+ "description": "capture/compare mode register 1 (input\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC2F": {
+ "description": "Input capture 2 filter",
+ "offset": 12,
+ "size": 4
+ },
+ "IC2PCS": {
+ "description": "Input capture 2 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC2S": {
+ "description": "Capture/Compare 2\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC1F": {
+ "description": "Input capture 1 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "ICPCS": {
+ "description": "Input capture 1 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR2_Output": {
+ "description": "capture/compare mode register 2 (output\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OC4CE": {
+ "description": "Output compare 4 clear\n enable",
+ "offset": 15,
+ "size": 1
+ },
+ "OC4M": {
+ "description": "Output compare 4 mode",
+ "offset": 12,
+ "size": 3
+ },
+ "OC4PE": {
+ "description": "Output compare 4 preload\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "OC4FE": {
+ "description": "Output compare 4 fast\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC4S": {
+ "description": "Capture/Compare 4\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "OC3CE": {
+ "description": "Output compare 3 clear\n enable",
+ "offset": 7,
+ "size": 1
+ },
+ "OC3M": {
+ "description": "Output compare 3 mode",
+ "offset": 4,
+ "size": 3
+ },
+ "OC3PE": {
+ "description": "Output compare 3 preload\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "OC3FE": {
+ "description": "Output compare 3 fast\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC3S": {
+ "description": "Capture/Compare 3\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR2_Input": {
+ "description": "capture/compare mode register 2 (input\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC4F": {
+ "description": "Input capture 4 filter",
+ "offset": 12,
+ "size": 4
+ },
+ "IC4PSC": {
+ "description": "Input capture 4 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC4S": {
+ "description": "Capture/Compare 4\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC3F": {
+ "description": "Input capture 3 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "IC3PSC": {
+ "description": "Input capture 3 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC3S": {
+ "description": "Capture/compare 3\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCER": {
+ "description": "capture/compare enable\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC4P": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 13,
+ "size": 1
+ },
+ "CC4E": {
+ "description": "Capture/Compare 4 output\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3NP": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 11,
+ "size": 1
+ },
+ "CC3NE": {
+ "description": "Capture/Compare 3 complementary output\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC3P": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 9,
+ "size": 1
+ },
+ "CC3E": {
+ "description": "Capture/Compare 3 output\n enable",
+ "offset": 8,
+ "size": 1
+ },
+ "CC2NP": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 7,
+ "size": 1
+ },
+ "CC2NE": {
+ "description": "Capture/Compare 2 complementary output\n enable",
+ "offset": 6,
+ "size": 1
+ },
+ "CC2P": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 5,
+ "size": 1
+ },
+ "CC2E": {
+ "description": "Capture/Compare 2 output\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC1NP": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 3,
+ "size": 1
+ },
+ "CC1NE": {
+ "description": "Capture/Compare 1 complementary output\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1P": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 1,
+ "size": 1
+ },
+ "CC1E": {
+ "description": "Capture/Compare 1 output\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNT": {
+ "description": "counter",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNT": {
+ "description": "counter value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "PSC": {
+ "description": "prescaler",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ARR": {
+ "description": "auto-reload register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARR": {
+ "description": "Auto-reload value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR1": {
+ "description": "capture/compare register 1",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR1": {
+ "description": "Capture/Compare 1 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR2": {
+ "description": "capture/compare register 2",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR2": {
+ "description": "Capture/Compare 2 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR3": {
+ "description": "capture/compare register 3",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR3": {
+ "description": "Capture/Compare value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR4": {
+ "description": "capture/compare register 4",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR4": {
+ "description": "Capture/Compare value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DCR": {
+ "description": "DMA control register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBL": {
+ "description": "DMA burst length",
+ "offset": 8,
+ "size": 5
+ },
+ "DBA": {
+ "description": "DMA base address",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "DMAR": {
+ "description": "DMA address for full transfer",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAB": {
+ "description": "DMA register for burst\n accesses",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "RCR": {
+ "description": "repetition counter register",
+ "offset": 48,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "REP": {
+ "description": "Repetition counter value",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "BDTR": {
+ "description": "break and dead-time register",
+ "offset": 68,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MOE": {
+ "description": "Main output enable",
+ "offset": 15,
+ "size": 1
+ },
+ "AOE": {
+ "description": "Automatic output enable",
+ "offset": 14,
+ "size": 1
+ },
+ "BKP": {
+ "description": "Break polarity",
+ "offset": 13,
+ "size": 1
+ },
+ "BKE": {
+ "description": "Break enable",
+ "offset": 12,
+ "size": 1
+ },
+ "OSSR": {
+ "description": "Off-state selection for Run\n mode",
+ "offset": 11,
+ "size": 1
+ },
+ "OSSI": {
+ "description": "Off-state selection for Idle\n mode",
+ "offset": 10,
+ "size": 1
+ },
+ "LOCK": {
+ "description": "Lock configuration",
+ "offset": 8,
+ "size": 2
+ },
+ "DTG": {
+ "description": "Dead-time generator setup",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "OTG_FS_HOST": {
+ "description": "USB on the go full speed",
+ "children": {
+ "registers": {
+ "FS_HCFG": {
+ "description": "OTG_FS host configuration register\n (OTG_FS_HCFG)",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FSLSPCS": {
+ "description": "FS/LS PHY clock select",
+ "offset": 0,
+ "size": 2
+ },
+ "FSLSS": {
+ "description": "FS- and LS-only support",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "HFIR": {
+ "description": "OTG_FS Host frame interval\n register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 60000,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "FRIVL": {
+ "description": "Frame interval",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_HFNUM": {
+ "description": "OTG_FS host frame number/frame time\n remaining register (OTG_FS_HFNUM)",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 16383,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "FRNUM": {
+ "description": "Frame number",
+ "offset": 0,
+ "size": 16
+ },
+ "FTREM": {
+ "description": "Frame time remaining",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_HPTXSTS": {
+ "description": "OTG_FS_Host periodic transmit FIFO/queue\n status register (OTG_FS_HPTXSTS)",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 524544,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PTXFSAVL": {
+ "description": "Periodic transmit data FIFO space\n available",
+ "offset": 0,
+ "size": 16
+ },
+ "PTXQSAV": {
+ "description": "Periodic transmit request queue space\n available",
+ "offset": 16,
+ "size": 8,
+ "access": "read-only"
+ },
+ "PTXQTOP": {
+ "description": "Top of the periodic transmit request\n queue",
+ "offset": 24,
+ "size": 8,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "HAINT": {
+ "description": "OTG_FS Host all channels interrupt\n register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "HAINT": {
+ "description": "Channel interrupts",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "HAINTMSK": {
+ "description": "OTG_FS host all channels interrupt mask\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "HAINTM": {
+ "description": "Channel interrupt mask",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_HPRT": {
+ "description": "OTG_FS host port control and status register\n (OTG_FS_HPRT)",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PCSTS": {
+ "description": "Port connect status",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PCDET": {
+ "description": "Port connect detected",
+ "offset": 1,
+ "size": 1
+ },
+ "PENA": {
+ "description": "Port enable",
+ "offset": 2,
+ "size": 1
+ },
+ "PENCHNG": {
+ "description": "Port enable/disable change",
+ "offset": 3,
+ "size": 1
+ },
+ "POCA": {
+ "description": "Port overcurrent active",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "POCCHNG": {
+ "description": "Port overcurrent change",
+ "offset": 5,
+ "size": 1
+ },
+ "PRES": {
+ "description": "Port resume",
+ "offset": 6,
+ "size": 1
+ },
+ "PSUSP": {
+ "description": "Port suspend",
+ "offset": 7,
+ "size": 1
+ },
+ "PRST": {
+ "description": "Port reset",
+ "offset": 8,
+ "size": 1
+ },
+ "PLSTS": {
+ "description": "Port line status",
+ "offset": 10,
+ "size": 2,
+ "access": "read-only"
+ },
+ "PPWR": {
+ "description": "Port power",
+ "offset": 12,
+ "size": 1
+ },
+ "PTCTL": {
+ "description": "Port test control",
+ "offset": 13,
+ "size": 4
+ },
+ "PSPD": {
+ "description": "Port speed",
+ "offset": 17,
+ "size": 2,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "FS_HCCHAR0": {
+ "description": "OTG_FS host channel-0 characteristics\n register (OTG_FS_HCCHAR0)",
+ "offset": 256,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MCNT": {
+ "description": "Multicount",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCCHAR1": {
+ "description": "OTG_FS host channel-1 characteristics\n register (OTG_FS_HCCHAR1)",
+ "offset": 288,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MCNT": {
+ "description": "Multicount",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCCHAR2": {
+ "description": "OTG_FS host channel-2 characteristics\n register (OTG_FS_HCCHAR2)",
+ "offset": 320,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MCNT": {
+ "description": "Multicount",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCCHAR3": {
+ "description": "OTG_FS host channel-3 characteristics\n register (OTG_FS_HCCHAR3)",
+ "offset": 352,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MCNT": {
+ "description": "Multicount",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCCHAR4": {
+ "description": "OTG_FS host channel-4 characteristics\n register (OTG_FS_HCCHAR4)",
+ "offset": 384,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MCNT": {
+ "description": "Multicount",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCCHAR5": {
+ "description": "OTG_FS host channel-5 characteristics\n register (OTG_FS_HCCHAR5)",
+ "offset": 416,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MCNT": {
+ "description": "Multicount",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCCHAR6": {
+ "description": "OTG_FS host channel-6 characteristics\n register (OTG_FS_HCCHAR6)",
+ "offset": 448,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MCNT": {
+ "description": "Multicount",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCCHAR7": {
+ "description": "OTG_FS host channel-7 characteristics\n register (OTG_FS_HCCHAR7)",
+ "offset": 480,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MPSIZ": {
+ "description": "Maximum packet size",
+ "offset": 0,
+ "size": 11
+ },
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 11,
+ "size": 4
+ },
+ "EPDIR": {
+ "description": "Endpoint direction",
+ "offset": 15,
+ "size": 1
+ },
+ "LSDEV": {
+ "description": "Low-speed device",
+ "offset": 17,
+ "size": 1
+ },
+ "EPTYP": {
+ "description": "Endpoint type",
+ "offset": 18,
+ "size": 2
+ },
+ "MCNT": {
+ "description": "Multicount",
+ "offset": 20,
+ "size": 2
+ },
+ "DAD": {
+ "description": "Device address",
+ "offset": 22,
+ "size": 7
+ },
+ "ODDFRM": {
+ "description": "Odd frame",
+ "offset": 29,
+ "size": 1
+ },
+ "CHDIS": {
+ "description": "Channel disable",
+ "offset": 30,
+ "size": 1
+ },
+ "CHENA": {
+ "description": "Channel enable",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINT0": {
+ "description": "OTG_FS host channel-0 interrupt register\n (OTG_FS_HCINT0)",
+ "offset": 264,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINT1": {
+ "description": "OTG_FS host channel-1 interrupt register\n (OTG_FS_HCINT1)",
+ "offset": 296,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINT2": {
+ "description": "OTG_FS host channel-2 interrupt register\n (OTG_FS_HCINT2)",
+ "offset": 328,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINT3": {
+ "description": "OTG_FS host channel-3 interrupt register\n (OTG_FS_HCINT3)",
+ "offset": 360,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINT4": {
+ "description": "OTG_FS host channel-4 interrupt register\n (OTG_FS_HCINT4)",
+ "offset": 392,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINT5": {
+ "description": "OTG_FS host channel-5 interrupt register\n (OTG_FS_HCINT5)",
+ "offset": 424,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINT6": {
+ "description": "OTG_FS host channel-6 interrupt register\n (OTG_FS_HCINT6)",
+ "offset": 456,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINT7": {
+ "description": "OTG_FS host channel-7 interrupt register\n (OTG_FS_HCINT7)",
+ "offset": 488,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRC": {
+ "description": "Transfer completed",
+ "offset": 0,
+ "size": 1
+ },
+ "CHH": {
+ "description": "Channel halted",
+ "offset": 1,
+ "size": 1
+ },
+ "STALL": {
+ "description": "STALL response received\n interrupt",
+ "offset": 3,
+ "size": 1
+ },
+ "NAK": {
+ "description": "NAK response received\n interrupt",
+ "offset": 4,
+ "size": 1
+ },
+ "ACK": {
+ "description": "ACK response received/transmitted\n interrupt",
+ "offset": 5,
+ "size": 1
+ },
+ "TXERR": {
+ "description": "Transaction error",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERR": {
+ "description": "Babble error",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMOR": {
+ "description": "Frame overrun",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERR": {
+ "description": "Data toggle error",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINTMSK0": {
+ "description": "OTG_FS host channel-0 mask register\n (OTG_FS_HCINTMSK0)",
+ "offset": 268,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINTMSK1": {
+ "description": "OTG_FS host channel-1 mask register\n (OTG_FS_HCINTMSK1)",
+ "offset": 300,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINTMSK2": {
+ "description": "OTG_FS host channel-2 mask register\n (OTG_FS_HCINTMSK2)",
+ "offset": 332,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINTMSK3": {
+ "description": "OTG_FS host channel-3 mask register\n (OTG_FS_HCINTMSK3)",
+ "offset": 364,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINTMSK4": {
+ "description": "OTG_FS host channel-4 mask register\n (OTG_FS_HCINTMSK4)",
+ "offset": 396,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINTMSK5": {
+ "description": "OTG_FS host channel-5 mask register\n (OTG_FS_HCINTMSK5)",
+ "offset": 428,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINTMSK6": {
+ "description": "OTG_FS host channel-6 mask register\n (OTG_FS_HCINTMSK6)",
+ "offset": 460,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCINTMSK7": {
+ "description": "OTG_FS host channel-7 mask register\n (OTG_FS_HCINTMSK7)",
+ "offset": 492,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRCM": {
+ "description": "Transfer completed mask",
+ "offset": 0,
+ "size": 1
+ },
+ "CHHM": {
+ "description": "Channel halted mask",
+ "offset": 1,
+ "size": 1
+ },
+ "STALLM": {
+ "description": "STALL response received interrupt\n mask",
+ "offset": 3,
+ "size": 1
+ },
+ "NAKM": {
+ "description": "NAK response received interrupt\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "ACKM": {
+ "description": "ACK response received/transmitted\n interrupt mask",
+ "offset": 5,
+ "size": 1
+ },
+ "NYET": {
+ "description": "response received interrupt\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "TXERRM": {
+ "description": "Transaction error mask",
+ "offset": 7,
+ "size": 1
+ },
+ "BBERRM": {
+ "description": "Babble error mask",
+ "offset": 8,
+ "size": 1
+ },
+ "FRMORM": {
+ "description": "Frame overrun mask",
+ "offset": 9,
+ "size": 1
+ },
+ "DTERRM": {
+ "description": "Data toggle error mask",
+ "offset": 10,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_HCTSIZ0": {
+ "description": "OTG_FS host channel-0 transfer size\n register",
+ "offset": 272,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "FS_HCTSIZ1": {
+ "description": "OTG_FS host channel-1 transfer size\n register",
+ "offset": 304,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "FS_HCTSIZ2": {
+ "description": "OTG_FS host channel-2 transfer size\n register",
+ "offset": 336,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "FS_HCTSIZ3": {
+ "description": "OTG_FS host channel-3 transfer size\n register",
+ "offset": 368,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "FS_HCTSIZ4": {
+ "description": "OTG_FS host channel-x transfer size\n register",
+ "offset": 400,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "FS_HCTSIZ5": {
+ "description": "OTG_FS host channel-5 transfer size\n register",
+ "offset": 432,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "FS_HCTSIZ6": {
+ "description": "OTG_FS host channel-6 transfer size\n register",
+ "offset": 464,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ },
+ "FS_HCTSIZ7": {
+ "description": "OTG_FS host channel-7 transfer size\n register",
+ "offset": 496,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "XFRSIZ": {
+ "description": "Transfer size",
+ "offset": 0,
+ "size": 19
+ },
+ "PKTCNT": {
+ "description": "Packet count",
+ "offset": 19,
+ "size": 10
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 29,
+ "size": 2
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "TIM2": {
+ "description": "General purpose timers",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CKD": {
+ "description": "Clock division",
+ "offset": 8,
+ "size": 2
+ },
+ "ARPE": {
+ "description": "Auto-reload preload enable",
+ "offset": 7,
+ "size": 1
+ },
+ "CMS": {
+ "description": "Center-aligned mode\n selection",
+ "offset": 5,
+ "size": 2
+ },
+ "DIR": {
+ "description": "Direction",
+ "offset": 4,
+ "size": 1
+ },
+ "OPM": {
+ "description": "One-pulse mode",
+ "offset": 3,
+ "size": 1
+ },
+ "URS": {
+ "description": "Update request source",
+ "offset": 2,
+ "size": 1
+ },
+ "UDIS": {
+ "description": "Update disable",
+ "offset": 1,
+ "size": 1
+ },
+ "CEN": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TI1S": {
+ "description": "TI1 selection",
+ "offset": 7,
+ "size": 1
+ },
+ "MMS": {
+ "description": "Master mode selection",
+ "offset": 4,
+ "size": 3
+ },
+ "CCDS": {
+ "description": "Capture/compare DMA\n selection",
+ "offset": 3,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SMCR": {
+ "description": "slave mode control register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ETP": {
+ "description": "External trigger polarity",
+ "offset": 15,
+ "size": 1
+ },
+ "ECE": {
+ "description": "External clock enable",
+ "offset": 14,
+ "size": 1
+ },
+ "ETPS": {
+ "description": "External trigger prescaler",
+ "offset": 12,
+ "size": 2
+ },
+ "ETF": {
+ "description": "External trigger filter",
+ "offset": 8,
+ "size": 4
+ },
+ "MSM": {
+ "description": "Master/Slave mode",
+ "offset": 7,
+ "size": 1
+ },
+ "TS": {
+ "description": "Trigger selection",
+ "offset": 4,
+ "size": 3
+ },
+ "SMS": {
+ "description": "Slave mode selection",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "DIER": {
+ "description": "DMA/Interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TDE": {
+ "description": "Trigger DMA request enable",
+ "offset": 14,
+ "size": 1
+ },
+ "CC4DE": {
+ "description": "Capture/Compare 4 DMA request\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3DE": {
+ "description": "Capture/Compare 3 DMA request\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "CC2DE": {
+ "description": "Capture/Compare 2 DMA request\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC1DE": {
+ "description": "Capture/Compare 1 DMA request\n enable",
+ "offset": 9,
+ "size": 1
+ },
+ "UDE": {
+ "description": "Update DMA request enable",
+ "offset": 8,
+ "size": 1
+ },
+ "TIE": {
+ "description": "Trigger interrupt enable",
+ "offset": 6,
+ "size": 1
+ },
+ "CC4IE": {
+ "description": "Capture/Compare 4 interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3IE": {
+ "description": "Capture/Compare 3 interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2IE": {
+ "description": "Capture/Compare 2 interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IE": {
+ "description": "Capture/Compare 1 interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "UIE": {
+ "description": "Update interrupt enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC4OF": {
+ "description": "Capture/Compare 4 overcapture\n flag",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3OF": {
+ "description": "Capture/Compare 3 overcapture\n flag",
+ "offset": 11,
+ "size": 1
+ },
+ "CC2OF": {
+ "description": "Capture/compare 2 overcapture\n flag",
+ "offset": 10,
+ "size": 1
+ },
+ "CC1OF": {
+ "description": "Capture/Compare 1 overcapture\n flag",
+ "offset": 9,
+ "size": 1
+ },
+ "TIF": {
+ "description": "Trigger interrupt flag",
+ "offset": 6,
+ "size": 1
+ },
+ "CC4IF": {
+ "description": "Capture/Compare 4 interrupt\n flag",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3IF": {
+ "description": "Capture/Compare 3 interrupt\n flag",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2IF": {
+ "description": "Capture/Compare 2 interrupt\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IF": {
+ "description": "Capture/compare 1 interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "UIF": {
+ "description": "Update interrupt flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EGR": {
+ "description": "event generation register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "TG": {
+ "description": "Trigger generation",
+ "offset": 6,
+ "size": 1
+ },
+ "CC4G": {
+ "description": "Capture/compare 4\n generation",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3G": {
+ "description": "Capture/compare 3\n generation",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2G": {
+ "description": "Capture/compare 2\n generation",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1G": {
+ "description": "Capture/compare 1\n generation",
+ "offset": 1,
+ "size": 1
+ },
+ "UG": {
+ "description": "Update generation",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Output": {
+ "description": "capture/compare mode register 1 (output\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OC2CE": {
+ "description": "OC2CE",
+ "offset": 15,
+ "size": 1
+ },
+ "OC2M": {
+ "description": "OC2M",
+ "offset": 12,
+ "size": 3
+ },
+ "OC2PE": {
+ "description": "OC2PE",
+ "offset": 11,
+ "size": 1
+ },
+ "OC2FE": {
+ "description": "OC2FE",
+ "offset": 10,
+ "size": 1
+ },
+ "CC2S": {
+ "description": "CC2S",
+ "offset": 8,
+ "size": 2
+ },
+ "OC1CE": {
+ "description": "OC1CE",
+ "offset": 7,
+ "size": 1
+ },
+ "OC1M": {
+ "description": "OC1M",
+ "offset": 4,
+ "size": 3
+ },
+ "OC1PE": {
+ "description": "OC1PE",
+ "offset": 3,
+ "size": 1
+ },
+ "OC1FE": {
+ "description": "OC1FE",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1S": {
+ "description": "CC1S",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR1_Input": {
+ "description": "capture/compare mode register 1 (input\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC2F": {
+ "description": "Input capture 2 filter",
+ "offset": 12,
+ "size": 4
+ },
+ "IC2PCS": {
+ "description": "Input capture 2 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC2S": {
+ "description": "Capture/Compare 2\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC1F": {
+ "description": "Input capture 1 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "ICPCS": {
+ "description": "Input capture 1 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR2_Output": {
+ "description": "capture/compare mode register 2 (output\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "O24CE": {
+ "description": "O24CE",
+ "offset": 15,
+ "size": 1
+ },
+ "OC4M": {
+ "description": "OC4M",
+ "offset": 12,
+ "size": 3
+ },
+ "OC4PE": {
+ "description": "OC4PE",
+ "offset": 11,
+ "size": 1
+ },
+ "OC4FE": {
+ "description": "OC4FE",
+ "offset": 10,
+ "size": 1
+ },
+ "CC4S": {
+ "description": "CC4S",
+ "offset": 8,
+ "size": 2
+ },
+ "OC3CE": {
+ "description": "OC3CE",
+ "offset": 7,
+ "size": 1
+ },
+ "OC3M": {
+ "description": "OC3M",
+ "offset": 4,
+ "size": 3
+ },
+ "OC3PE": {
+ "description": "OC3PE",
+ "offset": 3,
+ "size": 1
+ },
+ "OC3FE": {
+ "description": "OC3FE",
+ "offset": 2,
+ "size": 1
+ },
+ "CC3S": {
+ "description": "CC3S",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR2_Input": {
+ "description": "capture/compare mode register 2 (input\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC4F": {
+ "description": "Input capture 4 filter",
+ "offset": 12,
+ "size": 4
+ },
+ "IC4PSC": {
+ "description": "Input capture 4 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC4S": {
+ "description": "Capture/Compare 4\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC3F": {
+ "description": "Input capture 3 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "IC3PSC": {
+ "description": "Input capture 3 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC3S": {
+ "description": "Capture/compare 3\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCER": {
+ "description": "capture/compare enable\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC4NP": {
+ "description": "Capture/Compare 4 output\n Polarity",
+ "offset": 15,
+ "size": 1
+ },
+ "CC4P": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 13,
+ "size": 1
+ },
+ "CC4E": {
+ "description": "Capture/Compare 4 output\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3NP": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 11,
+ "size": 1
+ },
+ "CC3P": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 9,
+ "size": 1
+ },
+ "CC3E": {
+ "description": "Capture/Compare 3 output\n enable",
+ "offset": 8,
+ "size": 1
+ },
+ "CC2NP": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 7,
+ "size": 1
+ },
+ "CC2P": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 5,
+ "size": 1
+ },
+ "CC2E": {
+ "description": "Capture/Compare 2 output\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC1NP": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 3,
+ "size": 1
+ },
+ "CC1P": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 1,
+ "size": 1
+ },
+ "CC1E": {
+ "description": "Capture/Compare 1 output\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNT": {
+ "description": "counter",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNT_H": {
+ "description": "High counter value",
+ "offset": 16,
+ "size": 16
+ },
+ "CNT_L": {
+ "description": "Low counter value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "PSC": {
+ "description": "prescaler",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ARR": {
+ "description": "auto-reload register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARR_H": {
+ "description": "High Auto-reload value",
+ "offset": 16,
+ "size": 16
+ },
+ "ARR_L": {
+ "description": "Low Auto-reload value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR1": {
+ "description": "capture/compare register 1",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR1_H": {
+ "description": "High Capture/Compare 1\n value",
+ "offset": 16,
+ "size": 16
+ },
+ "CCR1_L": {
+ "description": "Low Capture/Compare 1\n value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR2": {
+ "description": "capture/compare register 2",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR2_H": {
+ "description": "High Capture/Compare 2\n value",
+ "offset": 16,
+ "size": 16
+ },
+ "CCR2_L": {
+ "description": "Low Capture/Compare 2\n value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR3": {
+ "description": "capture/compare register 3",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR3_H": {
+ "description": "High Capture/Compare value",
+ "offset": 16,
+ "size": 16
+ },
+ "CCR3_L": {
+ "description": "Low Capture/Compare value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR4": {
+ "description": "capture/compare register 4",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR4_H": {
+ "description": "High Capture/Compare value",
+ "offset": 16,
+ "size": 16
+ },
+ "CCR4_L": {
+ "description": "Low Capture/Compare value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DCR": {
+ "description": "DMA control register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBL": {
+ "description": "DMA burst length",
+ "offset": 8,
+ "size": 5
+ },
+ "DBA": {
+ "description": "DMA base address",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "DMAR": {
+ "description": "DMA address for full transfer",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAB": {
+ "description": "DMA register for burst\n accesses",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OR": {
+ "description": "TIM5 option register",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ITR1_RMP": {
+ "description": "Timer Input 4 remap",
+ "offset": 10,
+ "size": 2
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "TIM3": {
+ "description": "General purpose timers",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CKD": {
+ "description": "Clock division",
+ "offset": 8,
+ "size": 2
+ },
+ "ARPE": {
+ "description": "Auto-reload preload enable",
+ "offset": 7,
+ "size": 1
+ },
+ "CMS": {
+ "description": "Center-aligned mode\n selection",
+ "offset": 5,
+ "size": 2
+ },
+ "DIR": {
+ "description": "Direction",
+ "offset": 4,
+ "size": 1
+ },
+ "OPM": {
+ "description": "One-pulse mode",
+ "offset": 3,
+ "size": 1
+ },
+ "URS": {
+ "description": "Update request source",
+ "offset": 2,
+ "size": 1
+ },
+ "UDIS": {
+ "description": "Update disable",
+ "offset": 1,
+ "size": 1
+ },
+ "CEN": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TI1S": {
+ "description": "TI1 selection",
+ "offset": 7,
+ "size": 1
+ },
+ "MMS": {
+ "description": "Master mode selection",
+ "offset": 4,
+ "size": 3
+ },
+ "CCDS": {
+ "description": "Capture/compare DMA\n selection",
+ "offset": 3,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SMCR": {
+ "description": "slave mode control register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ETP": {
+ "description": "External trigger polarity",
+ "offset": 15,
+ "size": 1
+ },
+ "ECE": {
+ "description": "External clock enable",
+ "offset": 14,
+ "size": 1
+ },
+ "ETPS": {
+ "description": "External trigger prescaler",
+ "offset": 12,
+ "size": 2
+ },
+ "ETF": {
+ "description": "External trigger filter",
+ "offset": 8,
+ "size": 4
+ },
+ "MSM": {
+ "description": "Master/Slave mode",
+ "offset": 7,
+ "size": 1
+ },
+ "TS": {
+ "description": "Trigger selection",
+ "offset": 4,
+ "size": 3
+ },
+ "SMS": {
+ "description": "Slave mode selection",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "DIER": {
+ "description": "DMA/Interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TDE": {
+ "description": "Trigger DMA request enable",
+ "offset": 14,
+ "size": 1
+ },
+ "CC4DE": {
+ "description": "Capture/Compare 4 DMA request\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3DE": {
+ "description": "Capture/Compare 3 DMA request\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "CC2DE": {
+ "description": "Capture/Compare 2 DMA request\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC1DE": {
+ "description": "Capture/Compare 1 DMA request\n enable",
+ "offset": 9,
+ "size": 1
+ },
+ "UDE": {
+ "description": "Update DMA request enable",
+ "offset": 8,
+ "size": 1
+ },
+ "TIE": {
+ "description": "Trigger interrupt enable",
+ "offset": 6,
+ "size": 1
+ },
+ "CC4IE": {
+ "description": "Capture/Compare 4 interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3IE": {
+ "description": "Capture/Compare 3 interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2IE": {
+ "description": "Capture/Compare 2 interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IE": {
+ "description": "Capture/Compare 1 interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "UIE": {
+ "description": "Update interrupt enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC4OF": {
+ "description": "Capture/Compare 4 overcapture\n flag",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3OF": {
+ "description": "Capture/Compare 3 overcapture\n flag",
+ "offset": 11,
+ "size": 1
+ },
+ "CC2OF": {
+ "description": "Capture/compare 2 overcapture\n flag",
+ "offset": 10,
+ "size": 1
+ },
+ "CC1OF": {
+ "description": "Capture/Compare 1 overcapture\n flag",
+ "offset": 9,
+ "size": 1
+ },
+ "TIF": {
+ "description": "Trigger interrupt flag",
+ "offset": 6,
+ "size": 1
+ },
+ "CC4IF": {
+ "description": "Capture/Compare 4 interrupt\n flag",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3IF": {
+ "description": "Capture/Compare 3 interrupt\n flag",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2IF": {
+ "description": "Capture/Compare 2 interrupt\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IF": {
+ "description": "Capture/compare 1 interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "UIF": {
+ "description": "Update interrupt flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EGR": {
+ "description": "event generation register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "TG": {
+ "description": "Trigger generation",
+ "offset": 6,
+ "size": 1
+ },
+ "CC4G": {
+ "description": "Capture/compare 4\n generation",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3G": {
+ "description": "Capture/compare 3\n generation",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2G": {
+ "description": "Capture/compare 2\n generation",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1G": {
+ "description": "Capture/compare 1\n generation",
+ "offset": 1,
+ "size": 1
+ },
+ "UG": {
+ "description": "Update generation",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Output": {
+ "description": "capture/compare mode register 1 (output\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OC2CE": {
+ "description": "OC2CE",
+ "offset": 15,
+ "size": 1
+ },
+ "OC2M": {
+ "description": "OC2M",
+ "offset": 12,
+ "size": 3
+ },
+ "OC2PE": {
+ "description": "OC2PE",
+ "offset": 11,
+ "size": 1
+ },
+ "OC2FE": {
+ "description": "OC2FE",
+ "offset": 10,
+ "size": 1
+ },
+ "CC2S": {
+ "description": "CC2S",
+ "offset": 8,
+ "size": 2
+ },
+ "OC1CE": {
+ "description": "OC1CE",
+ "offset": 7,
+ "size": 1
+ },
+ "OC1M": {
+ "description": "OC1M",
+ "offset": 4,
+ "size": 3
+ },
+ "OC1PE": {
+ "description": "OC1PE",
+ "offset": 3,
+ "size": 1
+ },
+ "OC1FE": {
+ "description": "OC1FE",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1S": {
+ "description": "CC1S",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR1_Input": {
+ "description": "capture/compare mode register 1 (input\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC2F": {
+ "description": "Input capture 2 filter",
+ "offset": 12,
+ "size": 4
+ },
+ "IC2PCS": {
+ "description": "Input capture 2 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC2S": {
+ "description": "Capture/Compare 2\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC1F": {
+ "description": "Input capture 1 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "ICPCS": {
+ "description": "Input capture 1 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR2_Output": {
+ "description": "capture/compare mode register 2 (output\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "O24CE": {
+ "description": "O24CE",
+ "offset": 15,
+ "size": 1
+ },
+ "OC4M": {
+ "description": "OC4M",
+ "offset": 12,
+ "size": 3
+ },
+ "OC4PE": {
+ "description": "OC4PE",
+ "offset": 11,
+ "size": 1
+ },
+ "OC4FE": {
+ "description": "OC4FE",
+ "offset": 10,
+ "size": 1
+ },
+ "CC4S": {
+ "description": "CC4S",
+ "offset": 8,
+ "size": 2
+ },
+ "OC3CE": {
+ "description": "OC3CE",
+ "offset": 7,
+ "size": 1
+ },
+ "OC3M": {
+ "description": "OC3M",
+ "offset": 4,
+ "size": 3
+ },
+ "OC3PE": {
+ "description": "OC3PE",
+ "offset": 3,
+ "size": 1
+ },
+ "OC3FE": {
+ "description": "OC3FE",
+ "offset": 2,
+ "size": 1
+ },
+ "CC3S": {
+ "description": "CC3S",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR2_Input": {
+ "description": "capture/compare mode register 2 (input\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC4F": {
+ "description": "Input capture 4 filter",
+ "offset": 12,
+ "size": 4
+ },
+ "IC4PSC": {
+ "description": "Input capture 4 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC4S": {
+ "description": "Capture/Compare 4\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC3F": {
+ "description": "Input capture 3 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "IC3PSC": {
+ "description": "Input capture 3 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC3S": {
+ "description": "Capture/compare 3\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCER": {
+ "description": "capture/compare enable\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC4NP": {
+ "description": "Capture/Compare 4 output\n Polarity",
+ "offset": 15,
+ "size": 1
+ },
+ "CC4P": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 13,
+ "size": 1
+ },
+ "CC4E": {
+ "description": "Capture/Compare 4 output\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3NP": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 11,
+ "size": 1
+ },
+ "CC3P": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 9,
+ "size": 1
+ },
+ "CC3E": {
+ "description": "Capture/Compare 3 output\n enable",
+ "offset": 8,
+ "size": 1
+ },
+ "CC2NP": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 7,
+ "size": 1
+ },
+ "CC2P": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 5,
+ "size": 1
+ },
+ "CC2E": {
+ "description": "Capture/Compare 2 output\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC1NP": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 3,
+ "size": 1
+ },
+ "CC1P": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 1,
+ "size": 1
+ },
+ "CC1E": {
+ "description": "Capture/Compare 1 output\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNT": {
+ "description": "counter",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNT_H": {
+ "description": "High counter value",
+ "offset": 16,
+ "size": 16
+ },
+ "CNT_L": {
+ "description": "Low counter value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "PSC": {
+ "description": "prescaler",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ARR": {
+ "description": "auto-reload register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARR_H": {
+ "description": "High Auto-reload value",
+ "offset": 16,
+ "size": 16
+ },
+ "ARR_L": {
+ "description": "Low Auto-reload value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR1": {
+ "description": "capture/compare register 1",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR1_H": {
+ "description": "High Capture/Compare 1\n value",
+ "offset": 16,
+ "size": 16
+ },
+ "CCR1_L": {
+ "description": "Low Capture/Compare 1\n value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR2": {
+ "description": "capture/compare register 2",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR2_H": {
+ "description": "High Capture/Compare 2\n value",
+ "offset": 16,
+ "size": 16
+ },
+ "CCR2_L": {
+ "description": "Low Capture/Compare 2\n value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR3": {
+ "description": "capture/compare register 3",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR3_H": {
+ "description": "High Capture/Compare value",
+ "offset": 16,
+ "size": 16
+ },
+ "CCR3_L": {
+ "description": "Low Capture/Compare value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR4": {
+ "description": "capture/compare register 4",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR4_H": {
+ "description": "High Capture/Compare value",
+ "offset": 16,
+ "size": 16
+ },
+ "CCR4_L": {
+ "description": "Low Capture/Compare value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DCR": {
+ "description": "DMA control register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBL": {
+ "description": "DMA burst length",
+ "offset": 8,
+ "size": 5
+ },
+ "DBA": {
+ "description": "DMA base address",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "DMAR": {
+ "description": "DMA address for full transfer",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAB": {
+ "description": "DMA register for burst\n accesses",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "OTG_FS_GLOBAL": {
+ "description": "USB on the go full speed",
+ "children": {
+ "registers": {
+ "FS_GOTGCTL": {
+ "description": "OTG_FS control and status register\n (OTG_FS_GOTGCTL)",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 2048,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SRQSCS": {
+ "description": "Session request success",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SRQ": {
+ "description": "Session request",
+ "offset": 1,
+ "size": 1
+ },
+ "HNGSCS": {
+ "description": "Host negotiation success",
+ "offset": 8,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HNPRQ": {
+ "description": "HNP request",
+ "offset": 9,
+ "size": 1
+ },
+ "HSHNPEN": {
+ "description": "Host set HNP enable",
+ "offset": 10,
+ "size": 1
+ },
+ "DHNPEN": {
+ "description": "Device HNP enabled",
+ "offset": 11,
+ "size": 1
+ },
+ "CIDSTS": {
+ "description": "Connector ID status",
+ "offset": 16,
+ "size": 1,
+ "access": "read-only"
+ },
+ "DBCT": {
+ "description": "Long/short debounce time",
+ "offset": 17,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ASVLD": {
+ "description": "A-session valid",
+ "offset": 18,
+ "size": 1,
+ "access": "read-only"
+ },
+ "BSVLD": {
+ "description": "B-session valid",
+ "offset": 19,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "FS_GOTGINT": {
+ "description": "OTG_FS interrupt register\n (OTG_FS_GOTGINT)",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SEDET": {
+ "description": "Session end detected",
+ "offset": 2,
+ "size": 1
+ },
+ "SRSSCHG": {
+ "description": "Session request success status\n change",
+ "offset": 8,
+ "size": 1
+ },
+ "HNSSCHG": {
+ "description": "Host negotiation success status\n change",
+ "offset": 9,
+ "size": 1
+ },
+ "HNGDET": {
+ "description": "Host negotiation detected",
+ "offset": 17,
+ "size": 1
+ },
+ "ADTOCHG": {
+ "description": "A-device timeout change",
+ "offset": 18,
+ "size": 1
+ },
+ "DBCDNE": {
+ "description": "Debounce done",
+ "offset": 19,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_GAHBCFG": {
+ "description": "OTG_FS AHB configuration register\n (OTG_FS_GAHBCFG)",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "GINT": {
+ "description": "Global interrupt mask",
+ "offset": 0,
+ "size": 1
+ },
+ "TXFELVL": {
+ "description": "TxFIFO empty level",
+ "offset": 7,
+ "size": 1
+ },
+ "PTXFELVL": {
+ "description": "Periodic TxFIFO empty\n level",
+ "offset": 8,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_GUSBCFG": {
+ "description": "OTG_FS USB configuration register\n (OTG_FS_GUSBCFG)",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 2560,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TOCAL": {
+ "description": "FS timeout calibration",
+ "offset": 0,
+ "size": 3
+ },
+ "PHYSEL": {
+ "description": "Full Speed serial transceiver\n select",
+ "offset": 6,
+ "size": 1,
+ "access": "write-only"
+ },
+ "SRPCAP": {
+ "description": "SRP-capable",
+ "offset": 8,
+ "size": 1
+ },
+ "HNPCAP": {
+ "description": "HNP-capable",
+ "offset": 9,
+ "size": 1
+ },
+ "TRDT": {
+ "description": "USB turnaround time",
+ "offset": 10,
+ "size": 4
+ },
+ "FHMOD": {
+ "description": "Force host mode",
+ "offset": 29,
+ "size": 1
+ },
+ "FDMOD": {
+ "description": "Force device mode",
+ "offset": 30,
+ "size": 1
+ },
+ "CTXPKT": {
+ "description": "Corrupt Tx packet",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_GRSTCTL": {
+ "description": "OTG_FS reset register\n (OTG_FS_GRSTCTL)",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 536870912,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CSRST": {
+ "description": "Core soft reset",
+ "offset": 0,
+ "size": 1
+ },
+ "HSRST": {
+ "description": "HCLK soft reset",
+ "offset": 1,
+ "size": 1
+ },
+ "FCRST": {
+ "description": "Host frame counter reset",
+ "offset": 2,
+ "size": 1
+ },
+ "RXFFLSH": {
+ "description": "RxFIFO flush",
+ "offset": 4,
+ "size": 1
+ },
+ "TXFFLSH": {
+ "description": "TxFIFO flush",
+ "offset": 5,
+ "size": 1
+ },
+ "TXFNUM": {
+ "description": "TxFIFO number",
+ "offset": 6,
+ "size": 5
+ },
+ "AHBIDL": {
+ "description": "AHB master idle",
+ "offset": 31,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "FS_GINTSTS": {
+ "description": "OTG_FS core interrupt register\n (OTG_FS_GINTSTS)",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 67108896,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CMOD": {
+ "description": "Current mode of operation",
+ "offset": 0,
+ "size": 1,
+ "access": "read-only"
+ },
+ "MMIS": {
+ "description": "Mode mismatch interrupt",
+ "offset": 1,
+ "size": 1
+ },
+ "OTGINT": {
+ "description": "OTG interrupt",
+ "offset": 2,
+ "size": 1,
+ "access": "read-only"
+ },
+ "SOF": {
+ "description": "Start of frame",
+ "offset": 3,
+ "size": 1
+ },
+ "RXFLVL": {
+ "description": "RxFIFO non-empty",
+ "offset": 4,
+ "size": 1,
+ "access": "read-only"
+ },
+ "NPTXFE": {
+ "description": "Non-periodic TxFIFO empty",
+ "offset": 5,
+ "size": 1,
+ "access": "read-only"
+ },
+ "GINAKEFF": {
+ "description": "Global IN non-periodic NAK\n effective",
+ "offset": 6,
+ "size": 1,
+ "access": "read-only"
+ },
+ "GOUTNAKEFF": {
+ "description": "Global OUT NAK effective",
+ "offset": 7,
+ "size": 1,
+ "access": "read-only"
+ },
+ "ESUSP": {
+ "description": "Early suspend",
+ "offset": 10,
+ "size": 1
+ },
+ "USBSUSP": {
+ "description": "USB suspend",
+ "offset": 11,
+ "size": 1
+ },
+ "USBRST": {
+ "description": "USB reset",
+ "offset": 12,
+ "size": 1
+ },
+ "ENUMDNE": {
+ "description": "Enumeration done",
+ "offset": 13,
+ "size": 1
+ },
+ "ISOODRP": {
+ "description": "Isochronous OUT packet dropped\n interrupt",
+ "offset": 14,
+ "size": 1
+ },
+ "EOPF": {
+ "description": "End of periodic frame\n interrupt",
+ "offset": 15,
+ "size": 1
+ },
+ "IEPINT": {
+ "description": "IN endpoint interrupt",
+ "offset": 18,
+ "size": 1,
+ "access": "read-only"
+ },
+ "OEPINT": {
+ "description": "OUT endpoint interrupt",
+ "offset": 19,
+ "size": 1,
+ "access": "read-only"
+ },
+ "IISOIXFR": {
+ "description": "Incomplete isochronous IN\n transfer",
+ "offset": 20,
+ "size": 1
+ },
+ "IPXFR_INCOMPISOOUT": {
+ "description": "Incomplete periodic transfer(Host\n mode)/Incomplete isochronous OUT transfer(Device\n mode)",
+ "offset": 21,
+ "size": 1
+ },
+ "HPRTINT": {
+ "description": "Host port interrupt",
+ "offset": 24,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HCINT": {
+ "description": "Host channels interrupt",
+ "offset": 25,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PTXFE": {
+ "description": "Periodic TxFIFO empty",
+ "offset": 26,
+ "size": 1,
+ "access": "read-only"
+ },
+ "CIDSCHG": {
+ "description": "Connector ID status change",
+ "offset": 28,
+ "size": 1
+ },
+ "DISCINT": {
+ "description": "Disconnect detected\n interrupt",
+ "offset": 29,
+ "size": 1
+ },
+ "SRQINT": {
+ "description": "Session request/new session detected\n interrupt",
+ "offset": 30,
+ "size": 1
+ },
+ "WKUPINT": {
+ "description": "Resume/remote wakeup detected\n interrupt",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_GINTMSK": {
+ "description": "OTG_FS interrupt mask register\n (OTG_FS_GINTMSK)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MMISM": {
+ "description": "Mode mismatch interrupt\n mask",
+ "offset": 1,
+ "size": 1
+ },
+ "OTGINT": {
+ "description": "OTG interrupt mask",
+ "offset": 2,
+ "size": 1
+ },
+ "SOFM": {
+ "description": "Start of frame mask",
+ "offset": 3,
+ "size": 1
+ },
+ "RXFLVLM": {
+ "description": "Receive FIFO non-empty\n mask",
+ "offset": 4,
+ "size": 1
+ },
+ "NPTXFEM": {
+ "description": "Non-periodic TxFIFO empty\n mask",
+ "offset": 5,
+ "size": 1
+ },
+ "GINAKEFFM": {
+ "description": "Global non-periodic IN NAK effective\n mask",
+ "offset": 6,
+ "size": 1
+ },
+ "GONAKEFFM": {
+ "description": "Global OUT NAK effective\n mask",
+ "offset": 7,
+ "size": 1
+ },
+ "ESUSPM": {
+ "description": "Early suspend mask",
+ "offset": 10,
+ "size": 1
+ },
+ "USBSUSPM": {
+ "description": "USB suspend mask",
+ "offset": 11,
+ "size": 1
+ },
+ "USBRST": {
+ "description": "USB reset mask",
+ "offset": 12,
+ "size": 1
+ },
+ "ENUMDNEM": {
+ "description": "Enumeration done mask",
+ "offset": 13,
+ "size": 1
+ },
+ "ISOODRPM": {
+ "description": "Isochronous OUT packet dropped interrupt\n mask",
+ "offset": 14,
+ "size": 1
+ },
+ "EOPFM": {
+ "description": "End of periodic frame interrupt\n mask",
+ "offset": 15,
+ "size": 1
+ },
+ "EPMISM": {
+ "description": "Endpoint mismatch interrupt\n mask",
+ "offset": 17,
+ "size": 1
+ },
+ "IEPINT": {
+ "description": "IN endpoints interrupt\n mask",
+ "offset": 18,
+ "size": 1
+ },
+ "OEPINT": {
+ "description": "OUT endpoints interrupt\n mask",
+ "offset": 19,
+ "size": 1
+ },
+ "IISOIXFRM": {
+ "description": "Incomplete isochronous IN transfer\n mask",
+ "offset": 20,
+ "size": 1
+ },
+ "IPXFRM_IISOOXFRM": {
+ "description": "Incomplete periodic transfer mask(Host\n mode)/Incomplete isochronous OUT transfer mask(Device\n mode)",
+ "offset": 21,
+ "size": 1
+ },
+ "PRTIM": {
+ "description": "Host port interrupt mask",
+ "offset": 24,
+ "size": 1,
+ "access": "read-only"
+ },
+ "HCIM": {
+ "description": "Host channels interrupt\n mask",
+ "offset": 25,
+ "size": 1
+ },
+ "PTXFEM": {
+ "description": "Periodic TxFIFO empty mask",
+ "offset": 26,
+ "size": 1
+ },
+ "CIDSCHGM": {
+ "description": "Connector ID status change\n mask",
+ "offset": 28,
+ "size": 1
+ },
+ "DISCINT": {
+ "description": "Disconnect detected interrupt\n mask",
+ "offset": 29,
+ "size": 1
+ },
+ "SRQIM": {
+ "description": "Session request/new session detected\n interrupt mask",
+ "offset": 30,
+ "size": 1
+ },
+ "WUIM": {
+ "description": "Resume/remote wakeup detected interrupt\n mask",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_GRXSTSR_Device": {
+ "description": "OTG_FS Receive status debug read(Device\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 0,
+ "size": 4
+ },
+ "BCNT": {
+ "description": "Byte count",
+ "offset": 4,
+ "size": 11
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 15,
+ "size": 2
+ },
+ "PKTSTS": {
+ "description": "Packet status",
+ "offset": 17,
+ "size": 4
+ },
+ "FRMNUM": {
+ "description": "Frame number",
+ "offset": 21,
+ "size": 4
+ }
+ }
+ }
+ },
+ "FS_GRXSTSR_Host": {
+ "description": "OTG_FS Receive status debug\n read(Hostmode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "EPNUM": {
+ "description": "Endpoint number",
+ "offset": 0,
+ "size": 4
+ },
+ "BCNT": {
+ "description": "Byte count",
+ "offset": 4,
+ "size": 11
+ },
+ "DPID": {
+ "description": "Data PID",
+ "offset": 15,
+ "size": 2
+ },
+ "PKTSTS": {
+ "description": "Packet status",
+ "offset": 17,
+ "size": 4
+ },
+ "FRMNUM": {
+ "description": "Frame number",
+ "offset": 21,
+ "size": 4
+ }
+ }
+ }
+ },
+ "FS_GRXFSIZ": {
+ "description": "OTG_FS Receive FIFO size register\n (OTG_FS_GRXFSIZ)",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 512,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RXFD": {
+ "description": "RxFIFO depth",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_GNPTXFSIZ_Device": {
+ "description": "OTG_FS non-periodic transmit FIFO size\n register (Device mode)",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 512,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TX0FSA": {
+ "description": "Endpoint 0 transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "TX0FD": {
+ "description": "Endpoint 0 TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_GNPTXFSIZ_Host": {
+ "description": "OTG_FS non-periodic transmit FIFO size\n register (Host mode)",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 512,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "NPTXFSA": {
+ "description": "Non-periodic transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "NPTXFD": {
+ "description": "Non-periodic TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_GNPTXSTS": {
+ "description": "OTG_FS non-periodic transmit FIFO/queue\n status register (OTG_FS_GNPTXSTS)",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 524800,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "NPTXFSAV": {
+ "description": "Non-periodic TxFIFO space\n available",
+ "offset": 0,
+ "size": 16
+ },
+ "NPTQXSAV": {
+ "description": "Non-periodic transmit request queue\n space available",
+ "offset": 16,
+ "size": 8
+ },
+ "NPTXQTOP": {
+ "description": "Top of the non-periodic transmit request\n queue",
+ "offset": 24,
+ "size": 7
+ }
+ }
+ }
+ },
+ "FS_GCCFG": {
+ "description": "OTG_FS general core configuration register\n (OTG_FS_GCCFG)",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PWRDWN": {
+ "description": "Power down",
+ "offset": 16,
+ "size": 1
+ },
+ "VBUSASEN": {
+ "description": "Enable the VBUS sensing\n device",
+ "offset": 18,
+ "size": 1
+ },
+ "VBUSBSEN": {
+ "description": "Enable the VBUS sensing\n device",
+ "offset": 19,
+ "size": 1
+ },
+ "SOFOUTEN": {
+ "description": "SOF output enable",
+ "offset": 20,
+ "size": 1
+ }
+ }
+ }
+ },
+ "FS_CID": {
+ "description": "core ID register",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 4096,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PRODUCT_ID": {
+ "description": "Product ID field",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "FS_HPTXFSIZ": {
+ "description": "OTG_FS Host periodic transmit FIFO size\n register (OTG_FS_HPTXFSIZ)",
+ "offset": 256,
+ "size": 32,
+ "reset_value": 33555968,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PTXSA": {
+ "description": "Host periodic TxFIFO start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "PTXFSIZ": {
+ "description": "Host periodic TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_DIEPTXF1": {
+ "description": "OTG_FS device IN endpoint transmit FIFO size\n register (OTG_FS_DIEPTXF2)",
+ "offset": 260,
+ "size": 32,
+ "reset_value": 33555456,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INEPTXSA": {
+ "description": "IN endpoint FIFO2 transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "INEPTXFD": {
+ "description": "IN endpoint TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_DIEPTXF2": {
+ "description": "OTG_FS device IN endpoint transmit FIFO size\n register (OTG_FS_DIEPTXF3)",
+ "offset": 264,
+ "size": 32,
+ "reset_value": 33555456,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INEPTXSA": {
+ "description": "IN endpoint FIFO3 transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "INEPTXFD": {
+ "description": "IN endpoint TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ },
+ "FS_DIEPTXF3": {
+ "description": "OTG_FS device IN endpoint transmit FIFO size\n register (OTG_FS_DIEPTXF4)",
+ "offset": 268,
+ "size": 32,
+ "reset_value": 33555456,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "INEPTXSA": {
+ "description": "IN endpoint FIFO4 transmit RAM start\n address",
+ "offset": 0,
+ "size": 16
+ },
+ "INEPTXFD": {
+ "description": "IN endpoint TxFIFO depth",
+ "offset": 16,
+ "size": 16
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "TIM5": {
+ "description": "General-purpose-timers",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CKD": {
+ "description": "Clock division",
+ "offset": 8,
+ "size": 2
+ },
+ "ARPE": {
+ "description": "Auto-reload preload enable",
+ "offset": 7,
+ "size": 1
+ },
+ "CMS": {
+ "description": "Center-aligned mode\n selection",
+ "offset": 5,
+ "size": 2
+ },
+ "DIR": {
+ "description": "Direction",
+ "offset": 4,
+ "size": 1
+ },
+ "OPM": {
+ "description": "One-pulse mode",
+ "offset": 3,
+ "size": 1
+ },
+ "URS": {
+ "description": "Update request source",
+ "offset": 2,
+ "size": 1
+ },
+ "UDIS": {
+ "description": "Update disable",
+ "offset": 1,
+ "size": 1
+ },
+ "CEN": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TI1S": {
+ "description": "TI1 selection",
+ "offset": 7,
+ "size": 1
+ },
+ "MMS": {
+ "description": "Master mode selection",
+ "offset": 4,
+ "size": 3
+ },
+ "CCDS": {
+ "description": "Capture/compare DMA\n selection",
+ "offset": 3,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SMCR": {
+ "description": "slave mode control register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ETP": {
+ "description": "External trigger polarity",
+ "offset": 15,
+ "size": 1
+ },
+ "ECE": {
+ "description": "External clock enable",
+ "offset": 14,
+ "size": 1
+ },
+ "ETPS": {
+ "description": "External trigger prescaler",
+ "offset": 12,
+ "size": 2
+ },
+ "ETF": {
+ "description": "External trigger filter",
+ "offset": 8,
+ "size": 4
+ },
+ "MSM": {
+ "description": "Master/Slave mode",
+ "offset": 7,
+ "size": 1
+ },
+ "TS": {
+ "description": "Trigger selection",
+ "offset": 4,
+ "size": 3
+ },
+ "SMS": {
+ "description": "Slave mode selection",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "DIER": {
+ "description": "DMA/Interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TDE": {
+ "description": "Trigger DMA request enable",
+ "offset": 14,
+ "size": 1
+ },
+ "CC4DE": {
+ "description": "Capture/Compare 4 DMA request\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3DE": {
+ "description": "Capture/Compare 3 DMA request\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "CC2DE": {
+ "description": "Capture/Compare 2 DMA request\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC1DE": {
+ "description": "Capture/Compare 1 DMA request\n enable",
+ "offset": 9,
+ "size": 1
+ },
+ "UDE": {
+ "description": "Update DMA request enable",
+ "offset": 8,
+ "size": 1
+ },
+ "TIE": {
+ "description": "Trigger interrupt enable",
+ "offset": 6,
+ "size": 1
+ },
+ "CC4IE": {
+ "description": "Capture/Compare 4 interrupt\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3IE": {
+ "description": "Capture/Compare 3 interrupt\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2IE": {
+ "description": "Capture/Compare 2 interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IE": {
+ "description": "Capture/Compare 1 interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "UIE": {
+ "description": "Update interrupt enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC4OF": {
+ "description": "Capture/Compare 4 overcapture\n flag",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3OF": {
+ "description": "Capture/Compare 3 overcapture\n flag",
+ "offset": 11,
+ "size": 1
+ },
+ "CC2OF": {
+ "description": "Capture/compare 2 overcapture\n flag",
+ "offset": 10,
+ "size": 1
+ },
+ "CC1OF": {
+ "description": "Capture/Compare 1 overcapture\n flag",
+ "offset": 9,
+ "size": 1
+ },
+ "TIF": {
+ "description": "Trigger interrupt flag",
+ "offset": 6,
+ "size": 1
+ },
+ "CC4IF": {
+ "description": "Capture/Compare 4 interrupt\n flag",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3IF": {
+ "description": "Capture/Compare 3 interrupt\n flag",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2IF": {
+ "description": "Capture/Compare 2 interrupt\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IF": {
+ "description": "Capture/compare 1 interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "UIF": {
+ "description": "Update interrupt flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EGR": {
+ "description": "event generation register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "TG": {
+ "description": "Trigger generation",
+ "offset": 6,
+ "size": 1
+ },
+ "CC4G": {
+ "description": "Capture/compare 4\n generation",
+ "offset": 4,
+ "size": 1
+ },
+ "CC3G": {
+ "description": "Capture/compare 3\n generation",
+ "offset": 3,
+ "size": 1
+ },
+ "CC2G": {
+ "description": "Capture/compare 2\n generation",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1G": {
+ "description": "Capture/compare 1\n generation",
+ "offset": 1,
+ "size": 1
+ },
+ "UG": {
+ "description": "Update generation",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Output": {
+ "description": "capture/compare mode register 1 (output\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OC2CE": {
+ "description": "OC2CE",
+ "offset": 15,
+ "size": 1
+ },
+ "OC2M": {
+ "description": "OC2M",
+ "offset": 12,
+ "size": 3
+ },
+ "OC2PE": {
+ "description": "OC2PE",
+ "offset": 11,
+ "size": 1
+ },
+ "OC2FE": {
+ "description": "OC2FE",
+ "offset": 10,
+ "size": 1
+ },
+ "CC2S": {
+ "description": "CC2S",
+ "offset": 8,
+ "size": 2
+ },
+ "OC1CE": {
+ "description": "OC1CE",
+ "offset": 7,
+ "size": 1
+ },
+ "OC1M": {
+ "description": "OC1M",
+ "offset": 4,
+ "size": 3
+ },
+ "OC1PE": {
+ "description": "OC1PE",
+ "offset": 3,
+ "size": 1
+ },
+ "OC1FE": {
+ "description": "OC1FE",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1S": {
+ "description": "CC1S",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR1_Input": {
+ "description": "capture/compare mode register 1 (input\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC2F": {
+ "description": "Input capture 2 filter",
+ "offset": 12,
+ "size": 4
+ },
+ "IC2PCS": {
+ "description": "Input capture 2 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC2S": {
+ "description": "Capture/Compare 2\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC1F": {
+ "description": "Input capture 1 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "ICPCS": {
+ "description": "Input capture 1 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR2_Output": {
+ "description": "capture/compare mode register 2 (output\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "O24CE": {
+ "description": "O24CE",
+ "offset": 15,
+ "size": 1
+ },
+ "OC4M": {
+ "description": "OC4M",
+ "offset": 12,
+ "size": 3
+ },
+ "OC4PE": {
+ "description": "OC4PE",
+ "offset": 11,
+ "size": 1
+ },
+ "OC4FE": {
+ "description": "OC4FE",
+ "offset": 10,
+ "size": 1
+ },
+ "CC4S": {
+ "description": "CC4S",
+ "offset": 8,
+ "size": 2
+ },
+ "OC3CE": {
+ "description": "OC3CE",
+ "offset": 7,
+ "size": 1
+ },
+ "OC3M": {
+ "description": "OC3M",
+ "offset": 4,
+ "size": 3
+ },
+ "OC3PE": {
+ "description": "OC3PE",
+ "offset": 3,
+ "size": 1
+ },
+ "OC3FE": {
+ "description": "OC3FE",
+ "offset": 2,
+ "size": 1
+ },
+ "CC3S": {
+ "description": "CC3S",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR2_Input": {
+ "description": "capture/compare mode register 2 (input\n mode)",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC4F": {
+ "description": "Input capture 4 filter",
+ "offset": 12,
+ "size": 4
+ },
+ "IC4PSC": {
+ "description": "Input capture 4 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC4S": {
+ "description": "Capture/Compare 4\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC3F": {
+ "description": "Input capture 3 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "IC3PSC": {
+ "description": "Input capture 3 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC3S": {
+ "description": "Capture/compare 3\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCER": {
+ "description": "capture/compare enable\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC4NP": {
+ "description": "Capture/Compare 4 output\n Polarity",
+ "offset": 15,
+ "size": 1
+ },
+ "CC4P": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 13,
+ "size": 1
+ },
+ "CC4E": {
+ "description": "Capture/Compare 4 output\n enable",
+ "offset": 12,
+ "size": 1
+ },
+ "CC3NP": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 11,
+ "size": 1
+ },
+ "CC3P": {
+ "description": "Capture/Compare 3 output\n Polarity",
+ "offset": 9,
+ "size": 1
+ },
+ "CC3E": {
+ "description": "Capture/Compare 3 output\n enable",
+ "offset": 8,
+ "size": 1
+ },
+ "CC2NP": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 7,
+ "size": 1
+ },
+ "CC2P": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 5,
+ "size": 1
+ },
+ "CC2E": {
+ "description": "Capture/Compare 2 output\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC1NP": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 3,
+ "size": 1
+ },
+ "CC1P": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 1,
+ "size": 1
+ },
+ "CC1E": {
+ "description": "Capture/Compare 1 output\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNT": {
+ "description": "counter",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNT_H": {
+ "description": "High counter value",
+ "offset": 16,
+ "size": 16
+ },
+ "CNT_L": {
+ "description": "Low counter value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "PSC": {
+ "description": "prescaler",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ARR": {
+ "description": "auto-reload register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARR_H": {
+ "description": "High Auto-reload value",
+ "offset": 16,
+ "size": 16
+ },
+ "ARR_L": {
+ "description": "Low Auto-reload value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR1": {
+ "description": "capture/compare register 1",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR1_H": {
+ "description": "High Capture/Compare 1\n value",
+ "offset": 16,
+ "size": 16
+ },
+ "CCR1_L": {
+ "description": "Low Capture/Compare 1\n value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR2": {
+ "description": "capture/compare register 2",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR2_H": {
+ "description": "High Capture/Compare 2\n value",
+ "offset": 16,
+ "size": 16
+ },
+ "CCR2_L": {
+ "description": "Low Capture/Compare 2\n value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR3": {
+ "description": "capture/compare register 3",
+ "offset": 60,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR3_H": {
+ "description": "High Capture/Compare value",
+ "offset": 16,
+ "size": 16
+ },
+ "CCR3_L": {
+ "description": "Low Capture/Compare value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR4": {
+ "description": "capture/compare register 4",
+ "offset": 64,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR4_H": {
+ "description": "High Capture/Compare value",
+ "offset": 16,
+ "size": 16
+ },
+ "CCR4_L": {
+ "description": "Low Capture/Compare value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "DCR": {
+ "description": "DMA control register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DBL": {
+ "description": "DMA burst length",
+ "offset": 8,
+ "size": 5
+ },
+ "DBA": {
+ "description": "DMA base address",
+ "offset": 0,
+ "size": 5
+ }
+ }
+ }
+ },
+ "DMAR": {
+ "description": "DMA address for full transfer",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DMAB": {
+ "description": "DMA register for burst\n accesses",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OR": {
+ "description": "TIM5 option register",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IT4_RMP": {
+ "description": "Timer Input 4 remap",
+ "offset": 6,
+ "size": 2
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "TIM9": {
+ "description": "General purpose timers",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CKD": {
+ "description": "Clock division",
+ "offset": 8,
+ "size": 2
+ },
+ "ARPE": {
+ "description": "Auto-reload preload enable",
+ "offset": 7,
+ "size": 1
+ },
+ "OPM": {
+ "description": "One-pulse mode",
+ "offset": 3,
+ "size": 1
+ },
+ "URS": {
+ "description": "Update request source",
+ "offset": 2,
+ "size": 1
+ },
+ "UDIS": {
+ "description": "Update disable",
+ "offset": 1,
+ "size": 1
+ },
+ "CEN": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CR2": {
+ "description": "control register 2",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MMS": {
+ "description": "Master mode selection",
+ "offset": 4,
+ "size": 3
+ }
+ }
+ }
+ },
+ "SMCR": {
+ "description": "slave mode control register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MSM": {
+ "description": "Master/Slave mode",
+ "offset": 7,
+ "size": 1
+ },
+ "TS": {
+ "description": "Trigger selection",
+ "offset": 4,
+ "size": 3
+ },
+ "SMS": {
+ "description": "Slave mode selection",
+ "offset": 0,
+ "size": 3
+ }
+ }
+ }
+ },
+ "DIER": {
+ "description": "DMA/Interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIE": {
+ "description": "Trigger interrupt enable",
+ "offset": 6,
+ "size": 1
+ },
+ "CC2IE": {
+ "description": "Capture/Compare 2 interrupt\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IE": {
+ "description": "Capture/Compare 1 interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "UIE": {
+ "description": "Update interrupt enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC2OF": {
+ "description": "Capture/compare 2 overcapture\n flag",
+ "offset": 10,
+ "size": 1
+ },
+ "CC1OF": {
+ "description": "Capture/Compare 1 overcapture\n flag",
+ "offset": 9,
+ "size": 1
+ },
+ "TIF": {
+ "description": "Trigger interrupt flag",
+ "offset": 6,
+ "size": 1
+ },
+ "CC2IF": {
+ "description": "Capture/Compare 2 interrupt\n flag",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1IF": {
+ "description": "Capture/compare 1 interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "UIF": {
+ "description": "Update interrupt flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EGR": {
+ "description": "event generation register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "TG": {
+ "description": "Trigger generation",
+ "offset": 6,
+ "size": 1
+ },
+ "CC2G": {
+ "description": "Capture/compare 2\n generation",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1G": {
+ "description": "Capture/compare 1\n generation",
+ "offset": 1,
+ "size": 1
+ },
+ "UG": {
+ "description": "Update generation",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Output": {
+ "description": "capture/compare mode register 1 (output\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OC2M": {
+ "description": "Output Compare 2 mode",
+ "offset": 12,
+ "size": 3
+ },
+ "OC2PE": {
+ "description": "Output Compare 2 preload\n enable",
+ "offset": 11,
+ "size": 1
+ },
+ "OC2FE": {
+ "description": "Output Compare 2 fast\n enable",
+ "offset": 10,
+ "size": 1
+ },
+ "CC2S": {
+ "description": "Capture/Compare 2\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "OC1M": {
+ "description": "Output Compare 1 mode",
+ "offset": 4,
+ "size": 3
+ },
+ "OC1PE": {
+ "description": "Output Compare 1 preload\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "OC1FE": {
+ "description": "Output Compare 1 fast\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR1_Input": {
+ "description": "capture/compare mode register 1 (input\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC2F": {
+ "description": "Input capture 2 filter",
+ "offset": 12,
+ "size": 3
+ },
+ "IC2PCS": {
+ "description": "Input capture 2 prescaler",
+ "offset": 10,
+ "size": 2
+ },
+ "CC2S": {
+ "description": "Capture/Compare 2\n selection",
+ "offset": 8,
+ "size": 2
+ },
+ "IC1F": {
+ "description": "Input capture 1 filter",
+ "offset": 4,
+ "size": 3
+ },
+ "ICPCS": {
+ "description": "Input capture 1 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCER": {
+ "description": "capture/compare enable\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC2NP": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 7,
+ "size": 1
+ },
+ "CC2P": {
+ "description": "Capture/Compare 2 output\n Polarity",
+ "offset": 5,
+ "size": 1
+ },
+ "CC2E": {
+ "description": "Capture/Compare 2 output\n enable",
+ "offset": 4,
+ "size": 1
+ },
+ "CC1NP": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 3,
+ "size": 1
+ },
+ "CC1P": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 1,
+ "size": 1
+ },
+ "CC1E": {
+ "description": "Capture/Compare 1 output\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNT": {
+ "description": "counter",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNT": {
+ "description": "counter value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "PSC": {
+ "description": "prescaler",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ARR": {
+ "description": "auto-reload register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARR": {
+ "description": "Auto-reload value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR1": {
+ "description": "capture/compare register 1",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR1": {
+ "description": "Capture/Compare 1 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR2": {
+ "description": "capture/compare register 2",
+ "offset": 56,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR2": {
+ "description": "Capture/Compare 2 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "CRC": {
+ "description": "Cryptographic processor",
+ "children": {
+ "registers": {
+ "DR": {
+ "description": "Data register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 4294967295,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "DR": {
+ "description": "Data Register",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "IDR": {
+ "description": "Independent Data register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IDR": {
+ "description": "Independent Data register",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "CR": {
+ "description": "Control register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "CR": {
+ "description": "Control regidter",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "TIM10": {
+ "description": "General-purpose-timers",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CKD": {
+ "description": "Clock division",
+ "offset": 8,
+ "size": 2
+ },
+ "ARPE": {
+ "description": "Auto-reload preload enable",
+ "offset": 7,
+ "size": 1
+ },
+ "URS": {
+ "description": "Update request source",
+ "offset": 2,
+ "size": 1
+ },
+ "UDIS": {
+ "description": "Update disable",
+ "offset": 1,
+ "size": 1
+ },
+ "CEN": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DIER": {
+ "description": "DMA/Interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC1IE": {
+ "description": "Capture/Compare 1 interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "UIE": {
+ "description": "Update interrupt enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC1OF": {
+ "description": "Capture/Compare 1 overcapture\n flag",
+ "offset": 9,
+ "size": 1
+ },
+ "CC1IF": {
+ "description": "Capture/compare 1 interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "UIF": {
+ "description": "Update interrupt flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EGR": {
+ "description": "event generation register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "CC1G": {
+ "description": "Capture/compare 1\n generation",
+ "offset": 1,
+ "size": 1
+ },
+ "UG": {
+ "description": "Update generation",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Output": {
+ "description": "capture/compare mode register 1 (output\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OC1M": {
+ "description": "Output Compare 1 mode",
+ "offset": 4,
+ "size": 3
+ },
+ "OC1PE": {
+ "description": "Output Compare 1 preload\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "OC1FE": {
+ "description": "Output Compare 1 fast\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR1_Input": {
+ "description": "capture/compare mode register 1 (input\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC1F": {
+ "description": "Input capture 1 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "ICPCS": {
+ "description": "Input capture 1 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCER": {
+ "description": "capture/compare enable\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC1NP": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 3,
+ "size": 1
+ },
+ "CC1P": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 1,
+ "size": 1
+ },
+ "CC1E": {
+ "description": "Capture/Compare 1 output\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNT": {
+ "description": "counter",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNT": {
+ "description": "counter value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "PSC": {
+ "description": "prescaler",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ARR": {
+ "description": "auto-reload register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARR": {
+ "description": "Auto-reload value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR1": {
+ "description": "capture/compare register 1",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR1": {
+ "description": "Capture/Compare 1 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "Ethernet_DMA": {
+ "description": "Ethernet: DMA controller operation",
+ "children": {
+ "registers": {
+ "DMABMR": {
+ "description": "Ethernet DMA bus mode register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 8449,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SR": {
+ "description": "SR",
+ "offset": 0,
+ "size": 1
+ },
+ "DA": {
+ "description": "DA",
+ "offset": 1,
+ "size": 1
+ },
+ "DSL": {
+ "description": "DSL",
+ "offset": 2,
+ "size": 5
+ },
+ "EDFE": {
+ "description": "EDFE",
+ "offset": 7,
+ "size": 1
+ },
+ "PBL": {
+ "description": "PBL",
+ "offset": 8,
+ "size": 6
+ },
+ "RTPR": {
+ "description": "RTPR",
+ "offset": 14,
+ "size": 2
+ },
+ "FB": {
+ "description": "FB",
+ "offset": 16,
+ "size": 1
+ },
+ "RDP": {
+ "description": "RDP",
+ "offset": 17,
+ "size": 6
+ },
+ "USP": {
+ "description": "USP",
+ "offset": 23,
+ "size": 1
+ },
+ "FPM": {
+ "description": "FPM",
+ "offset": 24,
+ "size": 1
+ },
+ "AAB": {
+ "description": "AAB",
+ "offset": 25,
+ "size": 1
+ },
+ "MB": {
+ "description": "MB",
+ "offset": 26,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DMATPDR": {
+ "description": "Ethernet DMA transmit poll demand\n register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TPD": {
+ "description": "TPD",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DMARPDR": {
+ "description": "EHERNET DMA receive poll demand\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RPD": {
+ "description": "RPD",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DMARDLAR": {
+ "description": "Ethernet DMA receive descriptor list address\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SRL": {
+ "description": "SRL",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DMATDLAR": {
+ "description": "Ethernet DMA transmit descriptor list\n address register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "STL": {
+ "description": "STL",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DMASR": {
+ "description": "Ethernet DMA status register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TS": {
+ "description": "TS",
+ "offset": 0,
+ "size": 1
+ },
+ "TPSS": {
+ "description": "TPSS",
+ "offset": 1,
+ "size": 1
+ },
+ "TBUS": {
+ "description": "TBUS",
+ "offset": 2,
+ "size": 1
+ },
+ "TJTS": {
+ "description": "TJTS",
+ "offset": 3,
+ "size": 1
+ },
+ "ROS": {
+ "description": "ROS",
+ "offset": 4,
+ "size": 1
+ },
+ "TUS": {
+ "description": "TUS",
+ "offset": 5,
+ "size": 1
+ },
+ "RS": {
+ "description": "RS",
+ "offset": 6,
+ "size": 1
+ },
+ "RBUS": {
+ "description": "RBUS",
+ "offset": 7,
+ "size": 1
+ },
+ "RPSS": {
+ "description": "RPSS",
+ "offset": 8,
+ "size": 1
+ },
+ "PWTS": {
+ "description": "PWTS",
+ "offset": 9,
+ "size": 1
+ },
+ "ETS": {
+ "description": "ETS",
+ "offset": 10,
+ "size": 1
+ },
+ "FBES": {
+ "description": "FBES",
+ "offset": 13,
+ "size": 1
+ },
+ "ERS": {
+ "description": "ERS",
+ "offset": 14,
+ "size": 1
+ },
+ "AIS": {
+ "description": "AIS",
+ "offset": 15,
+ "size": 1
+ },
+ "NIS": {
+ "description": "NIS",
+ "offset": 16,
+ "size": 1
+ },
+ "RPS": {
+ "description": "RPS",
+ "offset": 17,
+ "size": 3,
+ "access": "read-only"
+ },
+ "TPS": {
+ "description": "TPS",
+ "offset": 20,
+ "size": 3,
+ "access": "read-only"
+ },
+ "EBS": {
+ "description": "EBS",
+ "offset": 23,
+ "size": 3,
+ "access": "read-only"
+ },
+ "MMCS": {
+ "description": "MMCS",
+ "offset": 27,
+ "size": 1,
+ "access": "read-only"
+ },
+ "PMTS": {
+ "description": "PMTS",
+ "offset": 28,
+ "size": 1,
+ "access": "read-only"
+ },
+ "TSTS": {
+ "description": "TSTS",
+ "offset": 29,
+ "size": 1,
+ "access": "read-only"
+ }
+ }
+ }
+ },
+ "DMAOMR": {
+ "description": "Ethernet DMA operation mode\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "SR": {
+ "description": "SR",
+ "offset": 1,
+ "size": 1
+ },
+ "OSF": {
+ "description": "OSF",
+ "offset": 2,
+ "size": 1
+ },
+ "RTC": {
+ "description": "RTC",
+ "offset": 3,
+ "size": 2
+ },
+ "FUGF": {
+ "description": "FUGF",
+ "offset": 6,
+ "size": 1
+ },
+ "FEF": {
+ "description": "FEF",
+ "offset": 7,
+ "size": 1
+ },
+ "ST": {
+ "description": "ST",
+ "offset": 13,
+ "size": 1
+ },
+ "TTC": {
+ "description": "TTC",
+ "offset": 14,
+ "size": 3
+ },
+ "FTF": {
+ "description": "FTF",
+ "offset": 20,
+ "size": 1
+ },
+ "TSF": {
+ "description": "TSF",
+ "offset": 21,
+ "size": 1
+ },
+ "DFRF": {
+ "description": "DFRF",
+ "offset": 24,
+ "size": 1
+ },
+ "RSF": {
+ "description": "RSF",
+ "offset": 25,
+ "size": 1
+ },
+ "DTCEFD": {
+ "description": "DTCEFD",
+ "offset": 26,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DMAIER": {
+ "description": "Ethernet DMA interrupt enable\n register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TIE": {
+ "description": "TIE",
+ "offset": 0,
+ "size": 1
+ },
+ "TPSIE": {
+ "description": "TPSIE",
+ "offset": 1,
+ "size": 1
+ },
+ "TBUIE": {
+ "description": "TBUIE",
+ "offset": 2,
+ "size": 1
+ },
+ "TJTIE": {
+ "description": "TJTIE",
+ "offset": 3,
+ "size": 1
+ },
+ "ROIE": {
+ "description": "ROIE",
+ "offset": 4,
+ "size": 1
+ },
+ "TUIE": {
+ "description": "TUIE",
+ "offset": 5,
+ "size": 1
+ },
+ "RIE": {
+ "description": "RIE",
+ "offset": 6,
+ "size": 1
+ },
+ "RBUIE": {
+ "description": "RBUIE",
+ "offset": 7,
+ "size": 1
+ },
+ "RPSIE": {
+ "description": "RPSIE",
+ "offset": 8,
+ "size": 1
+ },
+ "RWTIE": {
+ "description": "RWTIE",
+ "offset": 9,
+ "size": 1
+ },
+ "ETIE": {
+ "description": "ETIE",
+ "offset": 10,
+ "size": 1
+ },
+ "FBEIE": {
+ "description": "FBEIE",
+ "offset": 13,
+ "size": 1
+ },
+ "ERIE": {
+ "description": "ERIE",
+ "offset": 14,
+ "size": 1
+ },
+ "AISE": {
+ "description": "AISE",
+ "offset": 15,
+ "size": 1
+ },
+ "NISE": {
+ "description": "NISE",
+ "offset": 16,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DMAMFBOCR": {
+ "description": "Ethernet DMA missed frame and buffer\n overflow counter register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "MFC": {
+ "description": "MFC",
+ "offset": 0,
+ "size": 16
+ },
+ "OMFC": {
+ "description": "OMFC",
+ "offset": 16,
+ "size": 1
+ },
+ "MFA": {
+ "description": "MFA",
+ "offset": 17,
+ "size": 11
+ },
+ "OFOC": {
+ "description": "OFOC",
+ "offset": 28,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DMARSWTR": {
+ "description": "Ethernet DMA receive status watchdog timer\n register",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RSWTC": {
+ "description": "RSWTC",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "DMACHTDR": {
+ "description": "Ethernet DMA current host transmit\n descriptor register",
+ "offset": 72,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "HTDAP": {
+ "description": "HTDAP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DMACHRDR": {
+ "description": "Ethernet DMA current host receive descriptor\n register",
+ "offset": 76,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "HRDAP": {
+ "description": "HRDAP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DMACHTBAR": {
+ "description": "Ethernet DMA current host transmit buffer\n address register",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "HTBAP": {
+ "description": "HTBAP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "DMACHRBAR": {
+ "description": "Ethernet DMA current host receive buffer\n address register",
+ "offset": 84,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "HRBAP": {
+ "description": "HRBAP",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "Ethernet_PTP": {
+ "description": "Ethernet: Precision time protocol",
+ "children": {
+ "registers": {
+ "PTPTSCR": {
+ "description": "Ethernet PTP time stamp control\n register",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 8192,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TSE": {
+ "description": "TSE",
+ "offset": 0,
+ "size": 1
+ },
+ "TSFCU": {
+ "description": "TSFCU",
+ "offset": 1,
+ "size": 1
+ },
+ "TSPTPPSV2E": {
+ "description": "TSPTPPSV2E",
+ "offset": 10,
+ "size": 1
+ },
+ "TSSPTPOEFE": {
+ "description": "TSSPTPOEFE",
+ "offset": 11,
+ "size": 1
+ },
+ "TSSIPV6FE": {
+ "description": "TSSIPV6FE",
+ "offset": 12,
+ "size": 1
+ },
+ "TSSIPV4FE": {
+ "description": "TSSIPV4FE",
+ "offset": 13,
+ "size": 1
+ },
+ "TSSEME": {
+ "description": "TSSEME",
+ "offset": 14,
+ "size": 1
+ },
+ "TSSMRME": {
+ "description": "TSSMRME",
+ "offset": 15,
+ "size": 1
+ },
+ "TSCNT": {
+ "description": "TSCNT",
+ "offset": 16,
+ "size": 2
+ },
+ "TSPFFMAE": {
+ "description": "TSPFFMAE",
+ "offset": 18,
+ "size": 1
+ },
+ "TSSTI": {
+ "description": "TSSTI",
+ "offset": 2,
+ "size": 1
+ },
+ "TSSTU": {
+ "description": "TSSTU",
+ "offset": 3,
+ "size": 1
+ },
+ "TSITE": {
+ "description": "TSITE",
+ "offset": 4,
+ "size": 1
+ },
+ "TTSARU": {
+ "description": "TTSARU",
+ "offset": 5,
+ "size": 1
+ },
+ "TSSARFE": {
+ "description": "TSSARFE",
+ "offset": 8,
+ "size": 1
+ },
+ "TSSSR": {
+ "description": "TSSSR",
+ "offset": 9,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PTPSSIR": {
+ "description": "Ethernet PTP subsecond increment\n register",
+ "offset": 4,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "STSSI": {
+ "description": "STSSI",
+ "offset": 0,
+ "size": 8
+ }
+ }
+ }
+ },
+ "PTPTSHR": {
+ "description": "Ethernet PTP time stamp high\n register",
+ "offset": 8,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "STS": {
+ "description": "STS",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "PTPTSLR": {
+ "description": "Ethernet PTP time stamp low\n register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "STSS": {
+ "description": "STSS",
+ "offset": 0,
+ "size": 31
+ },
+ "STPNS": {
+ "description": "STPNS",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PTPTSHUR": {
+ "description": "Ethernet PTP time stamp high update\n register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TSUS": {
+ "description": "TSUS",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "PTPTSLUR": {
+ "description": "Ethernet PTP time stamp low update\n register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TSUSS": {
+ "description": "TSUSS",
+ "offset": 0,
+ "size": 31
+ },
+ "TSUPNS": {
+ "description": "TSUSS",
+ "offset": 31,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PTPTSAR": {
+ "description": "Ethernet PTP time stamp addend\n register",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TSA": {
+ "description": "TSA",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "PTPTTHR": {
+ "description": "Ethernet PTP target time high\n register",
+ "offset": 28,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TTSH": {
+ "description": "0",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "PTPTTLR": {
+ "description": "Ethernet PTP target time low\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "TTSL": {
+ "description": "TTSL",
+ "offset": 0,
+ "size": 32
+ }
+ }
+ }
+ },
+ "PTPTSSR": {
+ "description": "Ethernet PTP time stamp status\n register",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "TSSO": {
+ "description": "TSSO",
+ "offset": 0,
+ "size": 1
+ },
+ "TSTTR": {
+ "description": "TSTTR",
+ "offset": 1,
+ "size": 1
+ }
+ }
+ }
+ },
+ "PTPPPSCR": {
+ "description": "Ethernet PTP PPS control\n register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "read-only",
+ "children": {
+ "fields": {
+ "TSSO": {
+ "description": "TSSO",
+ "offset": 0,
+ "size": 1
+ },
+ "TSTTR": {
+ "description": "TSTTR",
+ "offset": 1,
+ "size": 1
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "TIM11": {
+ "description": "General-purpose-timers",
+ "children": {
+ "registers": {
+ "CR1": {
+ "description": "control register 1",
+ "offset": 0,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CKD": {
+ "description": "Clock division",
+ "offset": 8,
+ "size": 2
+ },
+ "ARPE": {
+ "description": "Auto-reload preload enable",
+ "offset": 7,
+ "size": 1
+ },
+ "URS": {
+ "description": "Update request source",
+ "offset": 2,
+ "size": 1
+ },
+ "UDIS": {
+ "description": "Update disable",
+ "offset": 1,
+ "size": 1
+ },
+ "CEN": {
+ "description": "Counter enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "DIER": {
+ "description": "DMA/Interrupt enable register",
+ "offset": 12,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC1IE": {
+ "description": "Capture/Compare 1 interrupt\n enable",
+ "offset": 1,
+ "size": 1
+ },
+ "UIE": {
+ "description": "Update interrupt enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "SR": {
+ "description": "status register",
+ "offset": 16,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC1OF": {
+ "description": "Capture/Compare 1 overcapture\n flag",
+ "offset": 9,
+ "size": 1
+ },
+ "CC1IF": {
+ "description": "Capture/compare 1 interrupt\n flag",
+ "offset": 1,
+ "size": 1
+ },
+ "UIF": {
+ "description": "Update interrupt flag",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "EGR": {
+ "description": "event generation register",
+ "offset": 20,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "access": "write-only",
+ "children": {
+ "fields": {
+ "CC1G": {
+ "description": "Capture/compare 1\n generation",
+ "offset": 1,
+ "size": 1
+ },
+ "UG": {
+ "description": "Update generation",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CCMR1_Output": {
+ "description": "capture/compare mode register 1 (output\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "OC1M": {
+ "description": "Output Compare 1 mode",
+ "offset": 4,
+ "size": 3
+ },
+ "OC1PE": {
+ "description": "Output Compare 1 preload\n enable",
+ "offset": 3,
+ "size": 1
+ },
+ "OC1FE": {
+ "description": "Output Compare 1 fast\n enable",
+ "offset": 2,
+ "size": 1
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCMR1_Input": {
+ "description": "capture/compare mode register 1 (input\n mode)",
+ "offset": 24,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "IC1F": {
+ "description": "Input capture 1 filter",
+ "offset": 4,
+ "size": 4
+ },
+ "ICPCS": {
+ "description": "Input capture 1 prescaler",
+ "offset": 2,
+ "size": 2
+ },
+ "CC1S": {
+ "description": "Capture/Compare 1\n selection",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ },
+ "CCER": {
+ "description": "capture/compare enable\n register",
+ "offset": 32,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CC1NP": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 3,
+ "size": 1
+ },
+ "CC1P": {
+ "description": "Capture/Compare 1 output\n Polarity",
+ "offset": 1,
+ "size": 1
+ },
+ "CC1E": {
+ "description": "Capture/Compare 1 output\n enable",
+ "offset": 0,
+ "size": 1
+ }
+ }
+ }
+ },
+ "CNT": {
+ "description": "counter",
+ "offset": 36,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CNT": {
+ "description": "counter value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "PSC": {
+ "description": "prescaler",
+ "offset": 40,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "PSC": {
+ "description": "Prescaler value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "ARR": {
+ "description": "auto-reload register",
+ "offset": 44,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "ARR": {
+ "description": "Auto-reload value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "CCR1": {
+ "description": "capture/compare register 1",
+ "offset": 52,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "CCR1": {
+ "description": "Capture/Compare 1 value",
+ "offset": 0,
+ "size": 16
+ }
+ }
+ }
+ },
+ "OR": {
+ "description": "option register",
+ "offset": 80,
+ "size": 32,
+ "reset_value": 0,
+ "reset_mask": 4294967295,
+ "children": {
+ "fields": {
+ "RMP": {
+ "description": "Input 1 remapping\n capability",
+ "offset": 0,
+ "size": 2
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "devices": {
+ "STM32F429": {
+ "arch": "cortex_m4",
+ "description": "STM32F429",
+ "properties": {
+ "cpu.nvic_prio_bits": "3",
+ "cpu.mpu": "false",
+ "cpu.fpu": "false",
+ "cpu.revision": "r1p0",
+ "cpu.vendor_systick_config": "false",
+ "cpu.endian": "little",
+ "cpu.name": "CM4"
+ },
+ "children": {
+ "interrupts": {
+ "MemManageFault": {
+ "index": -12
+ },
+ "BusFault": {
+ "index": -11
+ },
+ "UsageFault": {
+ "index": -10
+ },
+ "DebugMonitor": {
+ "index": -4
+ },
+ "NMI": {
+ "index": -14
+ },
+ "HardFault": {
+ "index": -13
+ },
+ "SVCall": {
+ "index": -5
+ },
+ "PendSV": {
+ "index": -2
+ },
+ "SysTick": {
+ "index": -1
+ },
+ "FPU": {
+ "index": 81,
+ "description": "Floating point unit interrupt"
+ },
+ "HASH_RNG": {
+ "index": 80,
+ "description": "Hash and Rng global interrupt"
+ },
+ "CRYP": {
+ "index": 79,
+ "description": "CRYP crypto global interrupt"
+ },
+ "DCMI": {
+ "index": 78,
+ "description": "DCMI global interrupt"
+ },
+ "FMC": {
+ "index": 48,
+ "description": "FMC global interrupt"
+ },
+ "DMA2_Stream0": {
+ "index": 56,
+ "description": "DMA2 Stream0 global interrupt"
+ },
+ "DMA1_Stream0": {
+ "index": 11,
+ "description": "DMA1 Stream0 global interrupt"
+ },
+ "RCC": {
+ "index": 5,
+ "description": "RCC global interrupt"
+ },
+ "SPI1": {
+ "index": 35,
+ "description": "SPI1 global interrupt"
+ },
+ "SPI2": {
+ "index": 36,
+ "description": "SPI2 global interrupt"
+ },
+ "SPI3": {
+ "index": 51,
+ "description": "SPI3 global interrupt"
+ },
+ "SPI4": {
+ "index": 84,
+ "description": "SPI 4 global interrupt"
+ },
+ "SPI5": {
+ "index": 85,
+ "description": "SPI 5 global interrupt"
+ },
+ "SPI6": {
+ "index": 86,
+ "description": "SPI 6 global interrupt"
+ },
+ "SDIO": {
+ "index": 49,
+ "description": "SDIO global interrupt"
+ },
+ "ADC": {
+ "index": 18,
+ "description": "ADC2 global interrupts"
+ },
+ "USART6": {
+ "index": 71,
+ "description": "USART6 global interrupt"
+ },
+ "USART1": {
+ "index": 37,
+ "description": "USART1 global interrupt"
+ },
+ "USART2": {
+ "index": 38,
+ "description": "USART2 global interrupt"
+ },
+ "USART3": {
+ "index": 39,
+ "description": "USART3 global interrupt"
+ },
+ "UART7": {
+ "index": 82,
+ "description": "UART 7 global interrupt"
+ },
+ "UART8": {
+ "index": 83,
+ "description": "UART 8 global interrupt"
+ },
+ "TIM6_DAC": {
+ "index": 54,
+ "description": "TIM6 global interrupt, DAC1 and DAC2 underrun\n error interrupt"
+ },
+ "PVD": {
+ "index": 1,
+ "description": "PVD through EXTI line detection\n interrupt"
+ },
+ "WWDG": {
+ "index": 0,
+ "description": "Window Watchdog interrupt"
+ },
+ "RTC_WKUP": {
+ "index": 3,
+ "description": "RTC Wakeup interrupt through the EXTI\n line"
+ },
+ "UART4": {
+ "index": 52,
+ "description": "UART4 global interrupt"
+ },
+ "UART5": {
+ "index": 53,
+ "description": "UART5 global interrupt"
+ },
+ "TIM1_BRK_TIM9": {
+ "index": 24,
+ "description": "TIM1 Break interrupt and TIM9 global\n interrupt"
+ },
+ "TIM8_BRK_TIM12": {
+ "index": 43,
+ "description": "TIM8 Break interrupt and TIM12 global\n interrupt"
+ },
+ "TIM2": {
+ "index": 28,
+ "description": "TIM2 global interrupt"
+ },
+ "TIM3": {
+ "index": 29,
+ "description": "TIM3 global interrupt"
+ },
+ "TIM4": {
+ "index": 30,
+ "description": "TIM4 global interrupt"
+ },
+ "TIM5": {
+ "index": 50,
+ "description": "TIM5 global interrupt"
+ },
+ "TIM8_UP_TIM13": {
+ "index": 44,
+ "description": "TIM8 Update interrupt and TIM13 global\n interrupt"
+ },
+ "TIM8_TRG_COM_TIM14": {
+ "index": 45,
+ "description": "TIM8 Trigger and Commutation interrupts and\n TIM14 global interrupt"
+ },
+ "TIM7": {
+ "index": 55,
+ "description": "TIM7 global interrupt"
+ },
+ "ETH": {
+ "index": 61,
+ "description": "Ethernet global interrupt"
+ },
+ "OTG_FS_WKUP": {
+ "index": 42,
+ "description": "USB On-The-Go FS Wakeup through EXTI line\n interrupt"
+ },
+ "CAN1_TX": {
+ "index": 19,
+ "description": "CAN1 TX interrupts"
+ },
+ "CAN2_TX": {
+ "index": 63,
+ "description": "CAN2 TX interrupts"
+ },
+ "FLASH": {
+ "index": 4,
+ "description": "Flash global interrupt"
+ },
+ "TAMP_STAMP": {
+ "index": 2,
+ "description": "Tamper and TimeStamp interrupts through the\n EXTI line"
+ },
+ "OTG_HS_EP1_OUT": {
+ "index": 74,
+ "description": "USB On The Go HS End Point 1 Out global\n interrupt"
+ },
+ "LCD_TFT": {
+ "index": 88,
+ "description": "LTDC global interrupt"
+ },
+ "SAI1": {
+ "index": 87,
+ "description": "SAI1 global interrupt"
+ },
+ "DMA2D": {
+ "index": 90,
+ "description": "DMA2D global interrupt"
+ },
+ "I2C3_EV": {
+ "index": 72,
+ "description": "I2C3 event interrupt"
+ },
+ "I2C2_EV": {
+ "index": 33,
+ "description": "I2C2 event interrupt"
+ },
+ "I2C1_EV": {
+ "index": 31,
+ "description": "I2C1 event interrupt"
+ }
+ },
+ "peripheral_instances": {
+ "RNG": {
+ "description": "Random number generator",
+ "offset": 1342572544,
+ "type": "types.peripherals.RNG"
+ },
+ "HASH": {
+ "description": "Hash processor",
+ "offset": 1342571520,
+ "type": "types.peripherals.HASH"
+ },
+ "CRYP": {
+ "description": "Cryptographic processor",
+ "offset": 1342570496,
+ "type": "types.peripherals.CRYP"
+ },
+ "DCMI": {
+ "description": "Digital camera interface",
+ "offset": 1342504960,
+ "type": "types.peripherals.DCMI"
+ },
+ "FMC": {
+ "description": "Flexible memory controller",
+ "offset": 2684354560,
+ "type": "types.peripherals.FMC"
+ },
+ "DBG": {
+ "description": "Debug support",
+ "offset": 3758366720,
+ "type": "types.peripherals.DBG"
+ },
+ "DMA2": {
+ "description": "DMA controller",
+ "offset": 1073898496,
+ "type": "types.peripherals.DMA2"
+ },
+ "DMA1": {
+ "offset": 1073897472,
+ "type": "types.peripherals.DMA2"
+ },
+ "RCC": {
+ "description": "Reset and clock control",
+ "offset": 1073887232,
+ "type": "types.peripherals.RCC"
+ },
+ "GPIOK": {
+ "description": "General-purpose I/Os",
+ "offset": 1073883136,
+ "type": "types.peripherals.GPIOK"
+ },
+ "GPIOJ": {
+ "offset": 1073882112,
+ "type": "types.peripherals.GPIOK"
+ },
+ "GPIOI": {
+ "offset": 1073881088,
+ "type": "types.peripherals.GPIOK"
+ },
+ "GPIOH": {
+ "offset": 1073880064,
+ "type": "types.peripherals.GPIOK"
+ },
+ "GPIOG": {
+ "offset": 1073879040,
+ "type": "types.peripherals.GPIOK"
+ },
+ "GPIOF": {
+ "offset": 1073878016,
+ "type": "types.peripherals.GPIOK"
+ },
+ "GPIOE": {
+ "offset": 1073876992,
+ "type": "types.peripherals.GPIOK"
+ },
+ "GPIOD": {
+ "offset": 1073875968,
+ "type": "types.peripherals.GPIOK"
+ },
+ "GPIOC": {
+ "offset": 1073874944,
+ "type": "types.peripherals.GPIOK"
+ },
+ "GPIOB": {
+ "description": "General-purpose I/Os",
+ "offset": 1073873920,
+ "type": "types.peripherals.GPIOB"
+ },
+ "GPIOA": {
+ "description": "General-purpose I/Os",
+ "offset": 1073872896,
+ "type": "types.peripherals.GPIOA"
+ },
+ "SYSCFG": {
+ "description": "System configuration controller",
+ "offset": 1073821696,
+ "type": "types.peripherals.SYSCFG"
+ },
+ "SPI1": {
+ "description": "Serial peripheral interface",
+ "offset": 1073819648,
+ "type": "types.peripherals.SPI1"
+ },
+ "SPI2": {
+ "offset": 1073756160,
+ "type": "types.peripherals.SPI1"
+ },
+ "SPI3": {
+ "offset": 1073757184,
+ "type": "types.peripherals.SPI1"
+ },
+ "I2S2ext": {
+ "offset": 1073755136,
+ "type": "types.peripherals.SPI1"
+ },
+ "I2S3ext": {
+ "offset": 1073758208,
+ "type": "types.peripherals.SPI1"
+ },
+ "SPI4": {
+ "offset": 1073820672,
+ "type": "types.peripherals.SPI1"
+ },
+ "SPI5": {
+ "offset": 1073827840,
+ "type": "types.peripherals.SPI1"
+ },
+ "SPI6": {
+ "offset": 1073828864,
+ "type": "types.peripherals.SPI1"
+ },
+ "SDIO": {
+ "description": "Secure digital input/output\n interface",
+ "offset": 1073818624,
+ "type": "types.peripherals.SDIO"
+ },
+ "ADC1": {
+ "description": "Analog-to-digital converter",
+ "offset": 1073815552,
+ "type": "types.peripherals.ADC1"
+ },
+ "ADC2": {
+ "offset": 1073815808,
+ "type": "types.peripherals.ADC1"
+ },
+ "ADC3": {
+ "offset": 1073816064,
+ "type": "types.peripherals.ADC1"
+ },
+ "USART6": {
+ "description": "Universal synchronous asynchronous receiver\n transmitter",
+ "offset": 1073812480,
+ "type": "types.peripherals.USART6"
+ },
+ "USART1": {
+ "offset": 1073811456,
+ "type": "types.peripherals.USART6"
+ },
+ "USART2": {
+ "offset": 1073759232,
+ "type": "types.peripherals.USART6"
+ },
+ "USART3": {
+ "offset": 1073760256,
+ "type": "types.peripherals.USART6"
+ },
+ "UART7": {
+ "offset": 1073772544,
+ "type": "types.peripherals.USART6"
+ },
+ "UART8": {
+ "offset": 1073773568,
+ "type": "types.peripherals.USART6"
+ },
+ "DAC": {
+ "description": "Digital-to-analog converter",
+ "offset": 1073771520,
+ "type": "types.peripherals.DAC"
+ },
+ "PWR": {
+ "description": "Power control",
+ "offset": 1073770496,
+ "type": "types.peripherals.PWR"
+ },
+ "IWDG": {
+ "description": "Independent watchdog",
+ "offset": 1073754112,
+ "type": "types.peripherals.IWDG"
+ },
+ "WWDG": {
+ "description": "Window watchdog",
+ "offset": 1073753088,
+ "type": "types.peripherals.WWDG"
+ },
+ "RTC": {
+ "description": "Real-time clock",
+ "offset": 1073752064,
+ "type": "types.peripherals.RTC"
+ },
+ "UART4": {
+ "description": "Universal synchronous asynchronous receiver\n transmitter",
+ "offset": 1073761280,
+ "type": "types.peripherals.UART4"
+ },
+ "UART5": {
+ "offset": 1073762304,
+ "type": "types.peripherals.UART4"
+ },
+ "C_ADC": {
+ "description": "Common ADC registers",
+ "offset": 1073816320,
+ "type": "types.peripherals.C_ADC"
+ },
+ "TIM1": {
+ "description": "Advanced-timers",
+ "offset": 1073807360,
+ "type": "types.peripherals.TIM1"
+ },
+ "TIM8": {
+ "offset": 1073808384,
+ "type": "types.peripherals.TIM1"
+ },
+ "TIM2": {
+ "description": "General purpose timers",
+ "offset": 1073741824,
+ "type": "types.peripherals.TIM2"
+ },
+ "TIM3": {
+ "description": "General purpose timers",
+ "offset": 1073742848,
+ "type": "types.peripherals.TIM3"
+ },
+ "TIM4": {
+ "offset": 1073743872,
+ "type": "types.peripherals.TIM3"
+ },
+ "TIM5": {
+ "description": "General-purpose-timers",
+ "offset": 1073744896,
+ "type": "types.peripherals.TIM5"
+ },
+ "TIM9": {
+ "description": "General purpose timers",
+ "offset": 1073823744,
+ "type": "types.peripherals.TIM9"
+ },
+ "TIM12": {
+ "offset": 1073747968,
+ "type": "types.peripherals.TIM9"
+ },
+ "TIM10": {
+ "description": "General-purpose-timers",
+ "offset": 1073824768,
+ "type": "types.peripherals.TIM10"
+ },
+ "TIM13": {
+ "offset": 1073748992,
+ "type": "types.peripherals.TIM10"
+ },
+ "TIM14": {
+ "offset": 1073750016,
+ "type": "types.peripherals.TIM10"
+ },
+ "TIM11": {
+ "description": "General-purpose-timers",
+ "offset": 1073825792,
+ "type": "types.peripherals.TIM11"
+ },
+ "TIM6": {
+ "description": "Basic timers",
+ "offset": 1073745920,
+ "type": "types.peripherals.TIM6"
+ },
+ "TIM7": {
+ "offset": 1073746944,
+ "type": "types.peripherals.TIM6"
+ },
+ "Ethernet_MAC": {
+ "description": "Ethernet: media access control\n (MAC)",
+ "offset": 1073905664,
+ "type": "types.peripherals.Ethernet_MAC"
+ },
+ "Ethernet_MMC": {
+ "description": "Ethernet: MAC management counters",
+ "offset": 1073905920,
+ "type": "types.peripherals.Ethernet_MMC"
+ },
+ "Ethernet_PTP": {
+ "description": "Ethernet: Precision time protocol",
+ "offset": 1073907456,
+ "type": "types.peripherals.Ethernet_PTP"
+ },
+ "Ethernet_DMA": {
+ "description": "Ethernet: DMA controller operation",
+ "offset": 1073909760,
+ "type": "types.peripherals.Ethernet_DMA"
+ },
+ "CRC": {
+ "description": "Cryptographic processor",
+ "offset": 1073885184,
+ "type": "types.peripherals.CRC"
+ },
+ "OTG_FS_GLOBAL": {
+ "description": "USB on the go full speed",
+ "offset": 1342177280,
+ "type": "types.peripherals.OTG_FS_GLOBAL"
+ },
+ "OTG_FS_HOST": {
+ "description": "USB on the go full speed",
+ "offset": 1342178304,
+ "type": "types.peripherals.OTG_FS_HOST"
+ },
+ "OTG_FS_DEVICE": {
+ "description": "USB on the go full speed",
+ "offset": 1342179328,
+ "type": "types.peripherals.OTG_FS_DEVICE"
+ },
+ "OTG_FS_PWRCLK": {
+ "description": "USB on the go full speed",
+ "offset": 1342180864,
+ "type": "types.peripherals.OTG_FS_PWRCLK"
+ },
+ "CAN1": {
+ "description": "Controller area network",
+ "offset": 1073767424,
+ "type": "types.peripherals.CAN1"
+ },
+ "CAN2": {
+ "offset": 1073768448,
+ "type": "types.peripherals.CAN1"
+ },
+ "NVIC": {
+ "description": "Nested Vectored Interrupt\n Controller",
+ "offset": 3758153984,
+ "type": "types.peripherals.NVIC"
+ },
+ "FLASH": {
+ "description": "FLASH",
+ "offset": 1073888256,
+ "type": "types.peripherals.FLASH"
+ },
+ "EXTI": {
+ "description": "External interrupt/event\n controller",
+ "offset": 1073822720,
+ "type": "types.peripherals.EXTI"
+ },
+ "OTG_HS_GLOBAL": {
+ "description": "USB on the go high speed",
+ "offset": 1074003968,
+ "type": "types.peripherals.OTG_HS_GLOBAL"
+ },
+ "OTG_HS_HOST": {
+ "description": "USB on the go high speed",
+ "offset": 1074004992,
+ "type": "types.peripherals.OTG_HS_HOST"
+ },
+ "OTG_HS_DEVICE": {
+ "description": "USB on the go high speed",
+ "offset": 1074006016,
+ "type": "types.peripherals.OTG_HS_DEVICE"
+ },
+ "OTG_HS_PWRCLK": {
+ "description": "USB on the go high speed",
+ "offset": 1074007552,
+ "type": "types.peripherals.OTG_HS_PWRCLK"
+ },
+ "LTDC": {
+ "description": "LCD-TFT Controller",
+ "offset": 1073833984,
+ "type": "types.peripherals.LTDC"
+ },
+ "SAI": {
+ "description": "Serial audio interface",
+ "offset": 1073829888,
+ "type": "types.peripherals.SAI"
+ },
+ "DMA2D": {
+ "description": "DMA2D controller",
+ "offset": 1073917952,
+ "type": "types.peripherals.DMA2D"
+ },
+ "I2C3": {
+ "description": "Inter-integrated circuit",
+ "offset": 1073765376,
+ "type": "types.peripherals.I2C3"
+ },
+ "I2C2": {
+ "offset": 1073764352,
+ "type": "types.peripherals.I2C3"
+ },
+ "I2C1": {
+ "offset": 1073763328,
+ "type": "types.peripherals.I2C3"
+ },
+ "FPU": {
+ "description": "Floting point unit",
+ "offset": 3758157620,
+ "type": "types.peripherals.FPU"
+ },
+ "MPU": {
+ "description": "Memory protection unit",
+ "offset": 3758157200,
+ "type": "types.peripherals.MPU"
+ },
+ "STK": {
+ "description": "SysTick timer",
+ "offset": 3758153744,
+ "type": "types.peripherals.STK"
+ },
+ "SCB": {
+ "description": "System control block",
+ "offset": 3758157056,
+ "type": "types.peripherals.SCB"
+ },
+ "NVIC_STIR": {
+ "description": "Nested vectored interrupt\n controller",
+ "offset": 3758157568,
+ "type": "types.peripherals.NVIC_STIR"
+ },
+ "FPU_CPACR": {
+ "description": "Floating point unit CPACR",
+ "offset": 3758157192,
+ "type": "types.peripherals.FPU_CPACR"
+ },
+ "SCB_ACTRL": {
+ "description": "System control block ACTLR",
+ "offset": 3758153736,
+ "type": "types.peripherals.SCB_ACTRL"
+ }
+ }
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/board-support/stmicro-stm32/src/chips/STM32L0x1.svd b/board-support/stmicro-stm32/src/chips/STM32L0x1.svd
new file mode 100644
index 0000000..360fdb2
--- /dev/null
+++ b/board-support/stmicro-stm32/src/chips/STM32L0x1.svd
@@ -0,0 +1,16671 @@
+
+
+ STM32L0x1
+ 1.3
+ STM32L0x1
+
+
+ CM0+
+ r0p0
+ little
+ false
+ false
+ 3
+ false
+
+
+
+ 8
+
+ 32
+
+ 0x20
+ 0x0
+ 0xFFFFFFFF
+
+
+ AES
+ Advanced encryption standard hardware
+ accelerator
+ AES
+ 0x40026000
+
+ 0x0
+ 0x400
+ registers
+
+
+ AES_RNG_LPUART1
+ AES global interrupt RNG global interrupt and
+ LPUART1 global interrupt through
+ 29
+
+
+
+ CR
+ CR
+ control register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DMAOUTEN
+ Enable DMA management of data output
+ phase
+ 12
+ 1
+
+
+ DMAINEN
+ Enable DMA management of data input
+ phase
+ 11
+ 1
+
+
+ ERRIE
+ Error interrupt enable
+ 10
+ 1
+
+
+ CCFIE
+ CCF flag interrupt enable
+ 9
+ 1
+
+
+ ERRC
+ Error clear
+ 8
+ 1
+
+
+ CCFC
+ Computation Complete Flag
+ Clear
+ 7
+ 1
+
+
+ CHMOD
+ AES chaining mode
+ 5
+ 2
+
+
+ MODE
+ AES operating mode
+ 3
+ 2
+
+
+ DATATYPE
+ Data type selection (for data in and
+ data out to/from the cryptographic
+ block)
+ 1
+ 2
+
+
+ EN
+ AES enable
+ 0
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x4
+ 0x20
+ read-only
+ 0x00000000
+
+
+ WRERR
+ Write error flag
+ 2
+ 1
+
+
+ RDERR
+ Read error flag
+ 1
+ 1
+
+
+ CCF
+ Computation complete flag
+ 0
+ 1
+
+
+
+
+ DINR
+ DINR
+ data input register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AES_DINR
+ Data Input Register.
+ 0
+ 32
+
+
+
+
+ DOUTR
+ DOUTR
+ data output register
+ 0xC
+ 0x20
+ read-only
+ 0x00000000
+
+
+ AES_DOUTR
+ Data output register
+ 0
+ 32
+
+
+
+
+ KEYR0
+ KEYR0
+ key register 0
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AES_KEYR0
+ Data Output Register (LSB key
+ [31:0])
+ 0
+ 32
+
+
+
+
+ KEYR1
+ KEYR1
+ key register 1
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AES_KEYR1
+ AES key register (key
+ [63:32])
+ 0
+ 32
+
+
+
+
+ KEYR2
+ KEYR2
+ key register 2
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AES_KEYR2
+ AES key register (key
+ [95:64])
+ 0
+ 32
+
+
+
+
+ KEYR3
+ KEYR3
+ key register 3
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AES_KEYR3
+ AES key register (MSB key
+ [127:96])
+ 0
+ 32
+
+
+
+
+ IVR0
+ IVR0
+ initialization vector register
+ 0
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AES_IVR0
+ initialization vector register (LSB IVR
+ [31:0])
+ 0
+ 32
+
+
+
+
+ IVR1
+ IVR1
+ initialization vector register
+ 1
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AES_IVR1
+ Initialization Vector Register (IVR
+ [63:32])
+ 0
+ 32
+
+
+
+
+ IVR2
+ IVR2
+ initialization vector register
+ 2
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AES_IVR2
+ Initialization Vector Register (IVR
+ [95:64])
+ 0
+ 32
+
+
+
+
+ IVR3
+ IVR3
+ initialization vector register
+ 3
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AES_IVR3
+ Initialization Vector Register (MSB IVR
+ [127:96])
+ 0
+ 32
+
+
+
+
+
+
+ DMA1
+ Direct memory access controller
+ DMA
+ 0x40020000
+
+ 0x0
+ 0x400
+ registers
+
+
+ DMA1_Channel1
+ DMA1 Channel1 global interrupt
+ 9
+
+
+ DMA1_Channel2_3
+ DMA1 Channel2 and 3 interrupts
+ 10
+
+
+ DMA1_Channel4_7
+ DMA1 Channel4 to 7 interrupts
+ 11
+
+
+
+ ISR
+ ISR
+ interrupt status register
+ 0x0
+ 0x20
+ read-only
+ 0x00000000
+
+
+ TEIF7
+ Channel x transfer error flag (x = 1
+ ..7)
+ 27
+ 1
+
+
+ HTIF7
+ Channel x half transfer flag (x = 1
+ ..7)
+ 26
+ 1
+
+
+ TCIF7
+ Channel x transfer complete flag (x = 1
+ ..7)
+ 25
+ 1
+
+
+ GIF7
+ Channel x global interrupt flag (x = 1
+ ..7)
+ 24
+ 1
+
+
+ TEIF6
+ Channel x transfer error flag (x = 1
+ ..7)
+ 23
+ 1
+
+
+ HTIF6
+ Channel x half transfer flag (x = 1
+ ..7)
+ 22
+ 1
+
+
+ TCIF6
+ Channel x transfer complete flag (x = 1
+ ..7)
+ 21
+ 1
+
+
+ GIF6
+ Channel x global interrupt flag (x = 1
+ ..7)
+ 20
+ 1
+
+
+ TEIF5
+ Channel x transfer error flag (x = 1
+ ..7)
+ 19
+ 1
+
+
+ HTIF5
+ Channel x half transfer flag (x = 1
+ ..7)
+ 18
+ 1
+
+
+ TCIF5
+ Channel x transfer complete flag (x = 1
+ ..7)
+ 17
+ 1
+
+
+ GIF5
+ Channel x global interrupt flag (x = 1
+ ..7)
+ 16
+ 1
+
+
+ TEIF4
+ Channel x transfer error flag (x = 1
+ ..7)
+ 15
+ 1
+
+
+ HTIF4
+ Channel x half transfer flag (x = 1
+ ..7)
+ 14
+ 1
+
+
+ TCIF4
+ Channel x transfer complete flag (x = 1
+ ..7)
+ 13
+ 1
+
+
+ GIF4
+ Channel x global interrupt flag (x = 1
+ ..7)
+ 12
+ 1
+
+
+ TEIF3
+ Channel x transfer error flag (x = 1
+ ..7)
+ 11
+ 1
+
+
+ HTIF3
+ Channel x half transfer flag (x = 1
+ ..7)
+ 10
+ 1
+
+
+ TCIF3
+ Channel x transfer complete flag (x = 1
+ ..7)
+ 9
+ 1
+
+
+ GIF3
+ Channel x global interrupt flag (x = 1
+ ..7)
+ 8
+ 1
+
+
+ TEIF2
+ Channel x transfer error flag (x = 1
+ ..7)
+ 7
+ 1
+
+
+ HTIF2
+ Channel x half transfer flag (x = 1
+ ..7)
+ 6
+ 1
+
+
+ TCIF2
+ Channel x transfer complete flag (x = 1
+ ..7)
+ 5
+ 1
+
+
+ GIF2
+ Channel x global interrupt flag (x = 1
+ ..7)
+ 4
+ 1
+
+
+ TEIF1
+ Channel x transfer error flag (x = 1
+ ..7)
+ 3
+ 1
+
+
+ HTIF1
+ Channel x half transfer flag (x = 1
+ ..7)
+ 2
+ 1
+
+
+ TCIF1
+ Channel x transfer complete flag (x = 1
+ ..7)
+ 1
+ 1
+
+
+ GIF1
+ Channel x global interrupt flag (x = 1
+ ..7)
+ 0
+ 1
+
+
+
+
+ IFCR
+ IFCR
+ interrupt flag clear register
+ 0x4
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CTEIF7
+ Channel x transfer error clear (x = 1
+ ..7)
+ 27
+ 1
+
+
+ CHTIF7
+ Channel x half transfer clear (x = 1
+ ..7)
+ 26
+ 1
+
+
+ CTCIF7
+ Channel x transfer complete clear (x = 1
+ ..7)
+ 25
+ 1
+
+
+ CGIF7
+ Channel x global interrupt clear (x = 1
+ ..7)
+ 24
+ 1
+
+
+ CTEIF6
+ Channel x transfer error clear (x = 1
+ ..7)
+ 23
+ 1
+
+
+ CHTIF6
+ Channel x half transfer clear (x = 1
+ ..7)
+ 22
+ 1
+
+
+ CTCIF6
+ Channel x transfer complete clear (x = 1
+ ..7)
+ 21
+ 1
+
+
+ CGIF6
+ Channel x global interrupt clear (x = 1
+ ..7)
+ 20
+ 1
+
+
+ CTEIF5
+ Channel x transfer error clear (x = 1
+ ..7)
+ 19
+ 1
+
+
+ CHTIF5
+ Channel x half transfer clear (x = 1
+ ..7)
+ 18
+ 1
+
+
+ CTCIF5
+ Channel x transfer complete clear (x = 1
+ ..7)
+ 17
+ 1
+
+
+ CGIF5
+ Channel x global interrupt clear (x = 1
+ ..7)
+ 16
+ 1
+
+
+ CTEIF4
+ Channel x transfer error clear (x = 1
+ ..7)
+ 15
+ 1
+
+
+ CHTIF4
+ Channel x half transfer clear (x = 1
+ ..7)
+ 14
+ 1
+
+
+ CTCIF4
+ Channel x transfer complete clear (x = 1
+ ..7)
+ 13
+ 1
+
+
+ CGIF4
+ Channel x global interrupt clear (x = 1
+ ..7)
+ 12
+ 1
+
+
+ CTEIF3
+ Channel x transfer error clear (x = 1
+ ..7)
+ 11
+ 1
+
+
+ CHTIF3
+ Channel x half transfer clear (x = 1
+ ..7)
+ 10
+ 1
+
+
+ CTCIF3
+ Channel x transfer complete clear (x = 1
+ ..7)
+ 9
+ 1
+
+
+ CGIF3
+ Channel x global interrupt clear (x = 1
+ ..7)
+ 8
+ 1
+
+
+ CTEIF2
+ Channel x transfer error clear (x = 1
+ ..7)
+ 7
+ 1
+
+
+ CHTIF2
+ Channel x half transfer clear (x = 1
+ ..7)
+ 6
+ 1
+
+
+ CTCIF2
+ Channel x transfer complete clear (x = 1
+ ..7)
+ 5
+ 1
+
+
+ CGIF2
+ Channel x global interrupt clear (x = 1
+ ..7)
+ 4
+ 1
+
+
+ CTEIF1
+ Channel x transfer error clear (x = 1
+ ..7)
+ 3
+ 1
+
+
+ CHTIF1
+ Channel x half transfer clear (x = 1
+ ..7)
+ 2
+ 1
+
+
+ CTCIF1
+ Channel x transfer complete clear (x = 1
+ ..7)
+ 1
+ 1
+
+
+ CGIF1
+ Channel x global interrupt clear (x = 1
+ ..7)
+ 0
+ 1
+
+
+
+
+ CCR1
+ CCR1
+ channel x configuration
+ register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+ PL
+ Channel priority level
+ 12
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ HTIE
+ Half transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+
+
+ CNDTR1
+ CNDTR1
+ channel x number of data
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR1
+ CPAR1
+ channel x peripheral address
+ register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR1
+ CMAR1
+ channel x memory address
+ register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR2
+ CCR2
+ channel x configuration
+ register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+ PL
+ Channel priority level
+ 12
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ HTIE
+ Half transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+
+
+ CNDTR2
+ CNDTR2
+ channel x number of data
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR2
+ CPAR2
+ channel x peripheral address
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR2
+ CMAR2
+ channel x memory address
+ register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR3
+ CCR3
+ channel x configuration
+ register
+ 0x30
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+ PL
+ Channel priority level
+ 12
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ HTIE
+ Half transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+
+
+ CNDTR3
+ CNDTR3
+ channel x number of data
+ register
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR3
+ CPAR3
+ channel x peripheral address
+ register
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR3
+ CMAR3
+ channel x memory address
+ register
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR4
+ CCR4
+ channel x configuration
+ register
+ 0x44
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+ PL
+ Channel priority level
+ 12
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ HTIE
+ Half transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+
+
+ CNDTR4
+ CNDTR4
+ channel x number of data
+ register
+ 0x48
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR4
+ CPAR4
+ channel x peripheral address
+ register
+ 0x4C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR4
+ CMAR4
+ channel x memory address
+ register
+ 0x50
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR5
+ CCR5
+ channel x configuration
+ register
+ 0x58
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+ PL
+ Channel priority level
+ 12
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ HTIE
+ Half transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+
+
+ CNDTR5
+ CNDTR5
+ channel x number of data
+ register
+ 0x5C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR5
+ CPAR5
+ channel x peripheral address
+ register
+ 0x60
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR5
+ CMAR5
+ channel x memory address
+ register
+ 0x64
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR6
+ CCR6
+ channel x configuration
+ register
+ 0x6C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+ PL
+ Channel priority level
+ 12
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ HTIE
+ Half transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+
+
+ CNDTR6
+ CNDTR6
+ channel x number of data
+ register
+ 0x70
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR6
+ CPAR6
+ channel x peripheral address
+ register
+ 0x74
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR6
+ CMAR6
+ channel x memory address
+ register
+ 0x78
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR7
+ CCR7
+ channel x configuration
+ register
+ 0x80
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+ PL
+ Channel priority level
+ 12
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ HTIE
+ Half transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+
+
+ CNDTR7
+ CNDTR7
+ channel x number of data
+ register
+ 0x84
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR7
+ CPAR7
+ channel x peripheral address
+ register
+ 0x88
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR7
+ CMAR7
+ channel x memory address
+ register
+ 0x8C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CSELR
+ CSELR
+ channel selection register
+ 0xA8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ C7S
+ DMA channel 7 selection
+ 24
+ 4
+
+
+ C6S
+ DMA channel 6 selection
+ 20
+ 4
+
+
+ C5S
+ DMA channel 5 selection
+ 16
+ 4
+
+
+ C4S
+ DMA channel 4 selection
+ 12
+ 4
+
+
+ C3S
+ DMA channel 3 selection
+ 8
+ 4
+
+
+ C2S
+ DMA channel 2 selection
+ 4
+ 4
+
+
+ C1S
+ DMA channel 1 selection
+ 0
+ 4
+
+
+
+
+
+
+ CRC
+ Cyclic redundancy check calculation
+ unit
+ CRC
+ 0x40023000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ DR
+ DR
+ Data register
+ 0x0
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ DR
+ Data register bits
+ 0
+ 32
+
+
+
+
+ IDR
+ IDR
+ Independent data register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IDR
+ General-purpose 8-bit data register
+ bits
+ 0
+ 8
+
+
+
+
+ CR
+ CR
+ Control register
+ 0x8
+ 0x20
+ 0x00000000
+
+
+ REV_OUT
+ Reverse output data
+ 7
+ 1
+ read-write
+
+
+ REV_IN
+ Reverse input data
+ 5
+ 2
+ read-write
+
+
+ POLYSIZE
+ Polynomial size
+ 3
+ 2
+ read-write
+
+
+ RESET
+ RESET bit
+ 0
+ 1
+ write-only
+
+
+
+
+ INIT
+ INIT
+ Initial CRC value
+ 0x10
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ CRC_INIT
+ Programmable initial CRC
+ value
+ 0
+ 32
+
+
+
+
+ POL
+ POL
+ polynomial
+ 0x14
+ 0x20
+ read-write
+ 0x04C11DB7
+
+
+ Polynomialcoefficients
+ Programmable polynomial
+ 0
+ 32
+
+
+
+
+
+
+ GPIOA
+ General-purpose I/Os
+ GPIO
+ 0x50000000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ MODER
+ MODER
+ GPIO port mode register
+ 0x0
+ 0x20
+ read-write
+ 0xEBFFFCFF
+
+
+ MODE0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+ MODE1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ MODE2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ MODE3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ MODE4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ MODE5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ MODE6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ MODE7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ MODE8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ MODE9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ MODE10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ MODE11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ MODE12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ MODE13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ MODE14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ MODE15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+
+
+ OTYPER
+ OTYPER
+ GPIO port output type register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OT15
+ Port x configuration bits (y =
+ 0..15)
+ 15
+ 1
+
+
+ OT14
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 1
+
+
+ OT13
+ Port x configuration bits (y =
+ 0..15)
+ 13
+ 1
+
+
+ OT12
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 1
+
+
+ OT11
+ Port x configuration bits (y =
+ 0..15)
+ 11
+ 1
+
+
+ OT10
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 1
+
+
+ OT9
+ Port x configuration bits (y =
+ 0..15)
+ 9
+ 1
+
+
+ OT8
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 1
+
+
+ OT7
+ Port x configuration bits (y =
+ 0..15)
+ 7
+ 1
+
+
+ OT6
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 1
+
+
+ OT5
+ Port x configuration bits (y =
+ 0..15)
+ 5
+ 1
+
+
+ OT4
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 1
+
+
+ OT3
+ Port x configuration bits (y =
+ 0..15)
+ 3
+ 1
+
+
+ OT2
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 1
+
+
+ OT1
+ Port x configuration bits (y =
+ 0..15)
+ 1
+ 1
+
+
+ OT0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ OSPEEDR
+ OSPEEDR
+ GPIO port output speed
+ register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OSPEED15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ OSPEED14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ OSPEED13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ OSPEED12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ OSPEED11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ OSPEED10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ OSPEED9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ OSPEED8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ OSPEED7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ OSPEED6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ OSPEED5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ OSPEED4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ OSPEED3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ OSPEED2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ OSPEED1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ OSPEED0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ PUPDR
+ PUPDR
+ GPIO port pull-up/pull-down
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x24000000
+
+
+ PUPD15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ PUPD14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ PUPD13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ PUPD12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ PUPD11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ PUPD10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ PUPD9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ PUPD8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ PUPD7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ PUPD6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ PUPD5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ PUPD4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ PUPD3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ PUPD2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ PUPD1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ PUPD0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ IDR
+ IDR
+ GPIO port input data register
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ ID15
+ Port input data bit (y =
+ 0..15)
+ 15
+ 1
+
+
+ ID14
+ Port input data bit (y =
+ 0..15)
+ 14
+ 1
+
+
+ ID13
+ Port input data bit (y =
+ 0..15)
+ 13
+ 1
+
+
+ ID12
+ Port input data bit (y =
+ 0..15)
+ 12
+ 1
+
+
+ ID11
+ Port input data bit (y =
+ 0..15)
+ 11
+ 1
+
+
+ ID10
+ Port input data bit (y =
+ 0..15)
+ 10
+ 1
+
+
+ ID9
+ Port input data bit (y =
+ 0..15)
+ 9
+ 1
+
+
+ ID8
+ Port input data bit (y =
+ 0..15)
+ 8
+ 1
+
+
+ ID7
+ Port input data bit (y =
+ 0..15)
+ 7
+ 1
+
+
+ ID6
+ Port input data bit (y =
+ 0..15)
+ 6
+ 1
+
+
+ ID5
+ Port input data bit (y =
+ 0..15)
+ 5
+ 1
+
+
+ ID4
+ Port input data bit (y =
+ 0..15)
+ 4
+ 1
+
+
+ ID3
+ Port input data bit (y =
+ 0..15)
+ 3
+ 1
+
+
+ ID2
+ Port input data bit (y =
+ 0..15)
+ 2
+ 1
+
+
+ ID1
+ Port input data bit (y =
+ 0..15)
+ 1
+ 1
+
+
+ ID0
+ Port input data bit (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ ODR
+ ODR
+ GPIO port output data register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OD15
+ Port output data bit (y =
+ 0..15)
+ 15
+ 1
+
+
+ OD14
+ Port output data bit (y =
+ 0..15)
+ 14
+ 1
+
+
+ OD13
+ Port output data bit (y =
+ 0..15)
+ 13
+ 1
+
+
+ OD12
+ Port output data bit (y =
+ 0..15)
+ 12
+ 1
+
+
+ OD11
+ Port output data bit (y =
+ 0..15)
+ 11
+ 1
+
+
+ OD10
+ Port output data bit (y =
+ 0..15)
+ 10
+ 1
+
+
+ OD9
+ Port output data bit (y =
+ 0..15)
+ 9
+ 1
+
+
+ OD8
+ Port output data bit (y =
+ 0..15)
+ 8
+ 1
+
+
+ OD7
+ Port output data bit (y =
+ 0..15)
+ 7
+ 1
+
+
+ OD6
+ Port output data bit (y =
+ 0..15)
+ 6
+ 1
+
+
+ OD5
+ Port output data bit (y =
+ 0..15)
+ 5
+ 1
+
+
+ OD4
+ Port output data bit (y =
+ 0..15)
+ 4
+ 1
+
+
+ OD3
+ Port output data bit (y =
+ 0..15)
+ 3
+ 1
+
+
+ OD2
+ Port output data bit (y =
+ 0..15)
+ 2
+ 1
+
+
+ OD1
+ Port output data bit (y =
+ 0..15)
+ 1
+ 1
+
+
+ OD0
+ Port output data bit (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ BSRR
+ BSRR
+ GPIO port bit set/reset
+ register
+ 0x18
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BR15
+ Port x reset bit y (y =
+ 0..15)
+ 31
+ 1
+
+
+ BR14
+ Port x reset bit y (y =
+ 0..15)
+ 30
+ 1
+
+
+ BR13
+ Port x reset bit y (y =
+ 0..15)
+ 29
+ 1
+
+
+ BR12
+ Port x reset bit y (y =
+ 0..15)
+ 28
+ 1
+
+
+ BR11
+ Port x reset bit y (y =
+ 0..15)
+ 27
+ 1
+
+
+ BR10
+ Port x reset bit y (y =
+ 0..15)
+ 26
+ 1
+
+
+ BR9
+ Port x reset bit y (y =
+ 0..15)
+ 25
+ 1
+
+
+ BR8
+ Port x reset bit y (y =
+ 0..15)
+ 24
+ 1
+
+
+ BR7
+ Port x reset bit y (y =
+ 0..15)
+ 23
+ 1
+
+
+ BR6
+ Port x reset bit y (y =
+ 0..15)
+ 22
+ 1
+
+
+ BR5
+ Port x reset bit y (y =
+ 0..15)
+ 21
+ 1
+
+
+ BR4
+ Port x reset bit y (y =
+ 0..15)
+ 20
+ 1
+
+
+ BR3
+ Port x reset bit y (y =
+ 0..15)
+ 19
+ 1
+
+
+ BR2
+ Port x reset bit y (y =
+ 0..15)
+ 18
+ 1
+
+
+ BR1
+ Port x reset bit y (y =
+ 0..15)
+ 17
+ 1
+
+
+ BR0
+ Port x reset bit y (y =
+ 0..15)
+ 16
+ 1
+
+
+ BS15
+ Port x set bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ BS14
+ Port x set bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ BS13
+ Port x set bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ BS12
+ Port x set bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ BS11
+ Port x set bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ BS10
+ Port x set bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ BS9
+ Port x set bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ BS8
+ Port x set bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ BS7
+ Port x set bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ BS6
+ Port x set bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ BS5
+ Port x set bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ BS4
+ Port x set bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ BS3
+ Port x set bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ BS2
+ Port x set bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ BS1
+ Port x set bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ BS0
+ Port x set bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ LCKR
+ LCKR
+ GPIO port configuration lock
+ register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LCKK
+ Port x lock bit y (y=
+ 0..15)
+ 16
+ 1
+
+
+ LCK15
+ Port x lock bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ LCK14
+ Port x lock bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ LCK13
+ Port x lock bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ LCK12
+ Port x lock bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ LCK11
+ Port x lock bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ LCK10
+ Port x lock bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ LCK9
+ Port x lock bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ LCK8
+ Port x lock bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ LCK7
+ Port x lock bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ LCK6
+ Port x lock bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ LCK5
+ Port x lock bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ LCK4
+ Port x lock bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ LCK3
+ Port x lock bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ LCK2
+ Port x lock bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ LCK1
+ Port x lock bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ LCK0
+ Port x lock bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ AFRL
+ AFRL
+ GPIO alternate function low
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AFSEL7
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 28
+ 4
+
+
+ AFSEL6
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 24
+ 4
+
+
+ AFSEL5
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 20
+ 4
+
+
+ AFSEL4
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 16
+ 4
+
+
+ AFSEL3
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 12
+ 4
+
+
+ AFSEL2
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 8
+ 4
+
+
+ AFSEL1
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 4
+ 4
+
+
+ AFSEL0
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 0
+ 4
+
+
+
+
+ AFRH
+ AFRH
+ GPIO alternate function high
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AFSEL15
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 28
+ 4
+
+
+ AFSEL14
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 24
+ 4
+
+
+ AFSEL13
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 20
+ 4
+
+
+ AFSEL12
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 16
+ 4
+
+
+ AFSEL11
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 12
+ 4
+
+
+ AFSEL10
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 8
+ 4
+
+
+ AFSEL9
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 4
+ 4
+
+
+ AFSEL8
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 0
+ 4
+
+
+
+
+ BRR
+ BRR
+ GPIO port bit reset register
+ 0x28
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BR15
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 15
+ 1
+
+
+ BR14
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 14
+ 1
+
+
+ BR13
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 13
+ 1
+
+
+ BR12
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 12
+ 1
+
+
+ BR11
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 11
+ 1
+
+
+ BR10
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 10
+ 1
+
+
+ BR9
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 9
+ 1
+
+
+ BR8
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 8
+ 1
+
+
+ BR7
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 7
+ 1
+
+
+ BR6
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 6
+ 1
+
+
+ BR5
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 5
+ 1
+
+
+ BR4
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 4
+ 1
+
+
+ BR3
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 3
+ 1
+
+
+ BR2
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 2
+ 1
+
+
+ BR1
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 1
+ 1
+
+
+ BR0
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 0
+ 1
+
+
+
+
+
+
+ GPIOB
+ General-purpose I/Os
+ GPIO
+ 0x50000400
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ MODER
+ MODER
+ GPIO port mode register
+ 0x0
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ MODE15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ MODE14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ MODE13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ MODE12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ MODE11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ MODE10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ MODE9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ MODE8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ MODE7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ MODE6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ MODE5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ MODE4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ MODE3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ MODE2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ MODE1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ MODE0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ OTYPER
+ OTYPER
+ GPIO port output type register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OT15
+ Port x configuration bits (y =
+ 0..15)
+ 15
+ 1
+
+
+ OT14
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 1
+
+
+ OT13
+ Port x configuration bits (y =
+ 0..15)
+ 13
+ 1
+
+
+ OT12
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 1
+
+
+ OT11
+ Port x configuration bits (y =
+ 0..15)
+ 11
+ 1
+
+
+ OT10
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 1
+
+
+ OT9
+ Port x configuration bits (y =
+ 0..15)
+ 9
+ 1
+
+
+ OT8
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 1
+
+
+ OT7
+ Port x configuration bits (y =
+ 0..15)
+ 7
+ 1
+
+
+ OT6
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 1
+
+
+ OT5
+ Port x configuration bits (y =
+ 0..15)
+ 5
+ 1
+
+
+ OT4
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 1
+
+
+ OT3
+ Port x configuration bits (y =
+ 0..15)
+ 3
+ 1
+
+
+ OT2
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 1
+
+
+ OT1
+ Port x configuration bits (y =
+ 0..15)
+ 1
+ 1
+
+
+ OT0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ OSPEEDR
+ OSPEEDR
+ GPIO port output speed
+ register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OSPEED15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ OSPEED14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ OSPEED13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ OSPEED12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ OSPEED11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ OSPEED10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ OSPEED9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ OSPEED8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ OSPEED7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ OSPEED6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ OSPEED5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ OSPEED4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ OSPEED3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ OSPEED2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ OSPEED1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ OSPEED0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ PUPDR
+ PUPDR
+ GPIO port pull-up/pull-down
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PUPD15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ PUPD14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ PUPD13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ PUPD12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ PUPD11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ PUPD10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ PUPD9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ PUPD8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ PUPD7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ PUPD6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ PUPD5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ PUPD4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ PUPD3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ PUPD2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ PUPD1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ PUPD0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ IDR
+ IDR
+ GPIO port input data register
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ ID15
+ Port input data bit (y =
+ 0..15)
+ 15
+ 1
+
+
+ ID14
+ Port input data bit (y =
+ 0..15)
+ 14
+ 1
+
+
+ ID13
+ Port input data bit (y =
+ 0..15)
+ 13
+ 1
+
+
+ ID12
+ Port input data bit (y =
+ 0..15)
+ 12
+ 1
+
+
+ ID11
+ Port input data bit (y =
+ 0..15)
+ 11
+ 1
+
+
+ ID10
+ Port input data bit (y =
+ 0..15)
+ 10
+ 1
+
+
+ ID9
+ Port input data bit (y =
+ 0..15)
+ 9
+ 1
+
+
+ ID8
+ Port input data bit (y =
+ 0..15)
+ 8
+ 1
+
+
+ ID7
+ Port input data bit (y =
+ 0..15)
+ 7
+ 1
+
+
+ ID6
+ Port input data bit (y =
+ 0..15)
+ 6
+ 1
+
+
+ ID5
+ Port input data bit (y =
+ 0..15)
+ 5
+ 1
+
+
+ ID4
+ Port input data bit (y =
+ 0..15)
+ 4
+ 1
+
+
+ ID3
+ Port input data bit (y =
+ 0..15)
+ 3
+ 1
+
+
+ ID2
+ Port input data bit (y =
+ 0..15)
+ 2
+ 1
+
+
+ ID1
+ Port input data bit (y =
+ 0..15)
+ 1
+ 1
+
+
+ ID0
+ Port input data bit (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ ODR
+ ODR
+ GPIO port output data register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OD15
+ Port output data bit (y =
+ 0..15)
+ 15
+ 1
+
+
+ OD14
+ Port output data bit (y =
+ 0..15)
+ 14
+ 1
+
+
+ OD13
+ Port output data bit (y =
+ 0..15)
+ 13
+ 1
+
+
+ OD12
+ Port output data bit (y =
+ 0..15)
+ 12
+ 1
+
+
+ OD11
+ Port output data bit (y =
+ 0..15)
+ 11
+ 1
+
+
+ OD10
+ Port output data bit (y =
+ 0..15)
+ 10
+ 1
+
+
+ OD9
+ Port output data bit (y =
+ 0..15)
+ 9
+ 1
+
+
+ OD8
+ Port output data bit (y =
+ 0..15)
+ 8
+ 1
+
+
+ OD7
+ Port output data bit (y =
+ 0..15)
+ 7
+ 1
+
+
+ OD6
+ Port output data bit (y =
+ 0..15)
+ 6
+ 1
+
+
+ OD5
+ Port output data bit (y =
+ 0..15)
+ 5
+ 1
+
+
+ OD4
+ Port output data bit (y =
+ 0..15)
+ 4
+ 1
+
+
+ OD3
+ Port output data bit (y =
+ 0..15)
+ 3
+ 1
+
+
+ OD2
+ Port output data bit (y =
+ 0..15)
+ 2
+ 1
+
+
+ OD1
+ Port output data bit (y =
+ 0..15)
+ 1
+ 1
+
+
+ OD0
+ Port output data bit (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ BSRR
+ BSRR
+ GPIO port bit set/reset
+ register
+ 0x18
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BR15
+ Port x reset bit y (y =
+ 0..15)
+ 31
+ 1
+
+
+ BR14
+ Port x reset bit y (y =
+ 0..15)
+ 30
+ 1
+
+
+ BR13
+ Port x reset bit y (y =
+ 0..15)
+ 29
+ 1
+
+
+ BR12
+ Port x reset bit y (y =
+ 0..15)
+ 28
+ 1
+
+
+ BR11
+ Port x reset bit y (y =
+ 0..15)
+ 27
+ 1
+
+
+ BR10
+ Port x reset bit y (y =
+ 0..15)
+ 26
+ 1
+
+
+ BR9
+ Port x reset bit y (y =
+ 0..15)
+ 25
+ 1
+
+
+ BR8
+ Port x reset bit y (y =
+ 0..15)
+ 24
+ 1
+
+
+ BR7
+ Port x reset bit y (y =
+ 0..15)
+ 23
+ 1
+
+
+ BR6
+ Port x reset bit y (y =
+ 0..15)
+ 22
+ 1
+
+
+ BR5
+ Port x reset bit y (y =
+ 0..15)
+ 21
+ 1
+
+
+ BR4
+ Port x reset bit y (y =
+ 0..15)
+ 20
+ 1
+
+
+ BR3
+ Port x reset bit y (y =
+ 0..15)
+ 19
+ 1
+
+
+ BR2
+ Port x reset bit y (y =
+ 0..15)
+ 18
+ 1
+
+
+ BR1
+ Port x reset bit y (y =
+ 0..15)
+ 17
+ 1
+
+
+ BR0
+ Port x reset bit y (y =
+ 0..15)
+ 16
+ 1
+
+
+ BS15
+ Port x set bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ BS14
+ Port x set bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ BS13
+ Port x set bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ BS12
+ Port x set bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ BS11
+ Port x set bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ BS10
+ Port x set bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ BS9
+ Port x set bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ BS8
+ Port x set bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ BS7
+ Port x set bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ BS6
+ Port x set bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ BS5
+ Port x set bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ BS4
+ Port x set bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ BS3
+ Port x set bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ BS2
+ Port x set bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ BS1
+ Port x set bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ BS0
+ Port x set bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ LCKR
+ LCKR
+ GPIO port configuration lock
+ register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LCKK
+ Port x lock bit y (y=
+ 0..15)
+ 16
+ 1
+
+
+ LCK15
+ Port x lock bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ LCK14
+ Port x lock bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ LCK13
+ Port x lock bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ LCK12
+ Port x lock bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ LCK11
+ Port x lock bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ LCK10
+ Port x lock bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ LCK9
+ Port x lock bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ LCK8
+ Port x lock bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ LCK7
+ Port x lock bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ LCK6
+ Port x lock bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ LCK5
+ Port x lock bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ LCK4
+ Port x lock bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ LCK3
+ Port x lock bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ LCK2
+ Port x lock bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ LCK1
+ Port x lock bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ LCK0
+ Port x lock bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ AFRL
+ AFRL
+ GPIO alternate function low
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AFSEL7
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 28
+ 4
+
+
+ AFSEL6
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 24
+ 4
+
+
+ AFSEL5
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 20
+ 4
+
+
+ AFSEL4
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 16
+ 4
+
+
+ AFSEL3
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 12
+ 4
+
+
+ AFSEL2
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 8
+ 4
+
+
+ AFSEL1
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 4
+ 4
+
+
+ AFSEL0
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 0
+ 4
+
+
+
+
+ AFRH
+ AFRH
+ GPIO alternate function high
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AFSEL15
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 28
+ 4
+
+
+ AFSEL14
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 24
+ 4
+
+
+ AFSEL13
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 20
+ 4
+
+
+ AFSEL12
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 16
+ 4
+
+
+ AFSEL11
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 12
+ 4
+
+
+ AFSEL10
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 8
+ 4
+
+
+ AFSEL9
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 4
+ 4
+
+
+ AFSEL8
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 0
+ 4
+
+
+
+
+ BRR
+ BRR
+ GPIO port bit reset register
+ 0x28
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BR15
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 15
+ 1
+
+
+ BR14
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 14
+ 1
+
+
+ BR13
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 13
+ 1
+
+
+ BR12
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 12
+ 1
+
+
+ BR11
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 11
+ 1
+
+
+ BR10
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 10
+ 1
+
+
+ BR9
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 9
+ 1
+
+
+ BR8
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 8
+ 1
+
+
+ BR7
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 7
+ 1
+
+
+ BR6
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 6
+ 1
+
+
+ BR5
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 5
+ 1
+
+
+ BR4
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 4
+ 1
+
+
+ BR3
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 3
+ 1
+
+
+ BR2
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 2
+ 1
+
+
+ BR1
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 1
+ 1
+
+
+ BR0
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 0
+ 1
+
+
+
+
+
+
+ GPIOC
+ 0x50000800
+
+
+ GPIOD
+ 0x50000C00
+
+
+ GPIOH
+ 0x50001C00
+
+
+ GPIOE
+ 0x50001000
+
+
+ LPTIM
+ Low power timer
+ LPTIM
+ 0x40007C00
+
+ 0x0
+ 0x400
+ registers
+
+
+ LPTIM1
+ LPTIMER1 interrupt through
+ EXTI29
+ 13
+
+
+
+ ISR
+ ISR
+ Interrupt and Status Register
+ 0x0
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DOWN
+ Counter direction change up to
+ down
+ 6
+ 1
+
+
+ UP
+ Counter direction change down to
+ up
+ 5
+ 1
+
+
+ ARROK
+ Autoreload register update
+ OK
+ 4
+ 1
+
+
+ CMPOK
+ Compare register update OK
+ 3
+ 1
+
+
+ EXTTRIG
+ External trigger edge
+ event
+ 2
+ 1
+
+
+ ARRM
+ Autoreload match
+ 1
+ 1
+
+
+ CMPM
+ Compare match
+ 0
+ 1
+
+
+
+
+ ICR
+ ICR
+ Interrupt Clear Register
+ 0x4
+ 0x20
+ write-only
+ 0x00000000
+
+
+ DOWNCF
+ Direction change to down Clear
+ Flag
+ 6
+ 1
+
+
+ UPCF
+ Direction change to UP Clear
+ Flag
+ 5
+ 1
+
+
+ ARROKCF
+ Autoreload register update OK Clear
+ Flag
+ 4
+ 1
+
+
+ CMPOKCF
+ Compare register update OK Clear
+ Flag
+ 3
+ 1
+
+
+ EXTTRIGCF
+ External trigger valid edge Clear
+ Flag
+ 2
+ 1
+
+
+ ARRMCF
+ Autoreload match Clear
+ Flag
+ 1
+ 1
+
+
+ CMPMCF
+ compare match Clear Flag
+ 0
+ 1
+
+
+
+
+ IER
+ IER
+ Interrupt Enable Register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DOWNIE
+ Direction change to down Interrupt
+ Enable
+ 6
+ 1
+
+
+ UPIE
+ Direction change to UP Interrupt
+ Enable
+ 5
+ 1
+
+
+ ARROKIE
+ Autoreload register update OK Interrupt
+ Enable
+ 4
+ 1
+
+
+ CMPOKIE
+ Compare register update OK Interrupt
+ Enable
+ 3
+ 1
+
+
+ EXTTRIGIE
+ External trigger valid edge Interrupt
+ Enable
+ 2
+ 1
+
+
+ ARRMIE
+ Autoreload match Interrupt
+ Enable
+ 1
+ 1
+
+
+ CMPMIE
+ Compare match Interrupt
+ Enable
+ 0
+ 1
+
+
+
+
+ CFGR
+ CFGR
+ Configuration Register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ENC
+ Encoder mode enable
+ 24
+ 1
+
+
+ COUNTMODE
+ counter mode enabled
+ 23
+ 1
+
+
+ PRELOAD
+ Registers update mode
+ 22
+ 1
+
+
+ WAVPOL
+ Waveform shape polarity
+ 21
+ 1
+
+
+ WAVE
+ Waveform shape
+ 20
+ 1
+
+
+ TIMOUT
+ Timeout enable
+ 19
+ 1
+
+
+ TRIGEN
+ Trigger enable and
+ polarity
+ 17
+ 2
+
+
+ TRIGSEL
+ Trigger selector
+ 13
+ 3
+
+
+ PRESC
+ Clock prescaler
+ 9
+ 3
+
+
+ TRGFLT
+ Configurable digital filter for
+ trigger
+ 6
+ 2
+
+
+ CKFLT
+ Configurable digital filter for external
+ clock
+ 3
+ 2
+
+
+ CKPOL
+ Clock Polarity
+ 1
+ 2
+
+
+ CKSEL
+ Clock selector
+ 0
+ 1
+
+
+
+
+ CR
+ CR
+ Control Register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNTSTRT
+ Timer start in continuous
+ mode
+ 2
+ 1
+
+
+ SNGSTRT
+ LPTIM start in single mode
+ 1
+ 1
+
+
+ ENABLE
+ LPTIM Enable
+ 0
+ 1
+
+
+
+
+ CMP
+ CMP
+ Compare Register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CMP
+ Compare value.
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ Autoreload Register
+ 0x18
+ 0x20
+ read-write
+ 0x00000001
+
+
+ ARR
+ Auto reload value.
+ 0
+ 16
+
+
+
+
+ CNT
+ CNT
+ Counter Register
+ 0x1C
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CNT
+ Counter value.
+ 0
+ 16
+
+
+
+
+
+
+ RTC
+ Real-time clock
+ RTC
+ 0x40002800
+
+ 0x0
+ 0x400
+ registers
+
+
+ RTC
+ RTC global interrupt
+ 2
+
+
+
+ TR
+ TR
+ RTC time register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PM
+ AM/PM notation
+ 22
+ 1
+
+
+ HT
+ Hour tens in BCD format
+ 20
+ 2
+
+
+ HU
+ Hour units in BCD format
+ 16
+ 4
+
+
+ MNT
+ Minute tens in BCD format
+ 12
+ 3
+
+
+ MNU
+ Minute units in BCD format
+ 8
+ 4
+
+
+ ST
+ Second tens in BCD format
+ 4
+ 3
+
+
+ SU
+ Second units in BCD format
+ 0
+ 4
+
+
+
+
+ DR
+ DR
+ RTC date register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ YT
+ Year tens in BCD format
+ 20
+ 4
+
+
+ YU
+ Year units in BCD format
+ 16
+ 4
+
+
+ WDU
+ Week day units
+ 13
+ 3
+
+
+ MT
+ Month tens in BCD format
+ 12
+ 1
+
+
+ MU
+ Month units in BCD format
+ 8
+ 4
+
+
+ DT
+ Date tens in BCD format
+ 4
+ 2
+
+
+ DU
+ Date units in BCD format
+ 0
+ 4
+
+
+
+
+ CR
+ CR
+ RTC control register
+ 0x8
+ 0x20
+ 0x00000000
+
+
+ COE
+ Calibration output enable
+ 23
+ 1
+ read-write
+
+
+ OSEL
+ Output selection
+ 21
+ 2
+ read-write
+
+
+ POL
+ Output polarity
+ 20
+ 1
+ read-write
+
+
+ COSEL
+ Calibration output
+ selection
+ 19
+ 1
+ read-write
+
+
+ BKP
+ Backup
+ 18
+ 1
+ read-write
+
+
+ SUB1H
+ Subtract 1 hour (winter time
+ change)
+ 17
+ 1
+ write-only
+
+
+ ADD1H
+ Add 1 hour (summer time
+ change)
+ 16
+ 1
+ write-only
+
+
+ TSIE
+ Time-stamp interrupt
+ enable
+ 15
+ 1
+ read-write
+
+
+ WUTIE
+ Wakeup timer interrupt
+ enable
+ 14
+ 1
+ read-write
+
+
+ ALRBIE
+ Alarm B interrupt enable
+ 13
+ 1
+ read-write
+
+
+ ALRAIE
+ Alarm A interrupt enable
+ 12
+ 1
+ read-write
+
+
+ TSE
+ timestamp enable
+ 11
+ 1
+ read-write
+
+
+ WUTE
+ Wakeup timer enable
+ 10
+ 1
+ read-write
+
+
+ ALRBE
+ Alarm B enable
+ 9
+ 1
+ read-write
+
+
+ ALRAE
+ Alarm A enable
+ 8
+ 1
+ read-write
+
+
+ FMT
+ Hour format
+ 6
+ 1
+ read-write
+
+
+ BYPSHAD
+ Bypass the shadow
+ registers
+ 5
+ 1
+ read-write
+
+
+ REFCKON
+ RTC_REFIN reference clock detection
+ enable (50 or 60 Hz)
+ 4
+ 1
+ read-write
+
+
+ TSEDGE
+ Time-stamp event active
+ edge
+ 3
+ 1
+ read-write
+
+
+ WUCKSEL
+ Wakeup clock selection
+ 0
+ 3
+ read-write
+
+
+
+
+ ISR
+ ISR
+ RTC initialization and status
+ register
+ 0xC
+ 0x20
+ 0x00000000
+
+
+ TAMP2F
+ RTC_TAMP2 detection flag
+ 14
+ 1
+ read-write
+
+
+ TAMP1F
+ RTC_TAMP1 detection flag
+ 13
+ 1
+ read-write
+
+
+ TSOVF
+ Time-stamp overflow flag
+ 12
+ 1
+ read-write
+
+
+ TSF
+ Time-stamp flag
+ 11
+ 1
+ read-write
+
+
+ WUTF
+ Wakeup timer flag
+ 10
+ 1
+ read-write
+
+
+ ALRBF
+ Alarm B flag
+ 9
+ 1
+ read-write
+
+
+ ALRAF
+ Alarm A flag
+ 8
+ 1
+ read-write
+
+
+ INIT
+ Initialization mode
+ 7
+ 1
+ read-write
+
+
+ INITF
+ Initialization flag
+ 6
+ 1
+ read-only
+
+
+ RSF
+ Registers synchronization
+ flag
+ 5
+ 1
+ read-write
+
+
+ INITS
+ Initialization status flag
+ 4
+ 1
+ read-only
+
+
+ SHPF
+ Shift operation pending
+ 3
+ 1
+ read-only
+
+
+ WUTWF
+ Wakeup timer write flag
+ 2
+ 1
+ read-only
+
+
+ ALRBWF
+ Alarm B write flag
+ 1
+ 1
+ read-only
+
+
+ ALRAWF
+ Alarm A write flag
+ 0
+ 1
+ read-only
+
+
+
+
+ PRER
+ PRER
+ RTC prescaler register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PREDIV_A
+ Asynchronous prescaler
+ factor
+ 16
+ 7
+
+
+ PREDIV_S
+ Synchronous prescaler
+ factor
+ 0
+ 16
+
+
+
+
+ WUTR
+ WUTR
+ RTC wakeup timer register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ WUT
+ Wakeup auto-reload value
+ bits
+ 0
+ 16
+
+
+
+
+ ALRMAR
+ ALRMAR
+ RTC alarm A register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MSK4
+ Alarm A date mask
+ 31
+ 1
+
+
+ WDSEL
+ Week day selection
+ 30
+ 1
+
+
+ DT
+ Date tens in BCD format.
+ 28
+ 2
+
+
+ DU
+ Date units or day in BCD
+ format.
+ 24
+ 4
+
+
+ MSK3
+ Alarm A hours mask
+ 23
+ 1
+
+
+ PM
+ AM/PM notation
+ 22
+ 1
+
+
+ HT
+ Hour tens in BCD format.
+ 20
+ 2
+
+
+ HU
+ Hour units in BCD format.
+ 16
+ 4
+
+
+ MSK2
+ Alarm A minutes mask
+ 15
+ 1
+
+
+ MNT
+ Minute tens in BCD format.
+ 12
+ 3
+
+
+ MNU
+ Minute units in BCD
+ format.
+ 8
+ 4
+
+
+ MSK1
+ Alarm A seconds mask
+ 7
+ 1
+
+
+ ST
+ Second tens in BCD format.
+ 4
+ 3
+
+
+ SU
+ Second units in BCD
+ format.
+ 0
+ 4
+
+
+
+
+ ALRMBR
+ ALRMBR
+ RTC alarm B register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MSK4
+ Alarm B date mask
+ 31
+ 1
+
+
+ WDSEL
+ Week day selection
+ 30
+ 1
+
+
+ DT
+ Date tens in BCD format
+ 28
+ 2
+
+
+ DU
+ Date units or day in BCD
+ format
+ 24
+ 4
+
+
+ MSK3
+ Alarm B hours mask
+ 23
+ 1
+
+
+ PM
+ AM/PM notation
+ 22
+ 1
+
+
+ HT
+ Hour tens in BCD format
+ 20
+ 2
+
+
+ HU
+ Hour units in BCD format
+ 16
+ 4
+
+
+ MSK2
+ Alarm B minutes mask
+ 15
+ 1
+
+
+ MNT
+ Minute tens in BCD format
+ 12
+ 3
+
+
+ MNU
+ Minute units in BCD format
+ 8
+ 4
+
+
+ MSK1
+ Alarm B seconds mask
+ 7
+ 1
+
+
+ ST
+ Second tens in BCD format
+ 4
+ 3
+
+
+ SU
+ Second units in BCD format
+ 0
+ 4
+
+
+
+
+ WPR
+ WPR
+ write protection register
+ 0x24
+ 0x20
+ write-only
+ 0x00000000
+
+
+ KEY
+ Write protection key
+ 0
+ 8
+
+
+
+
+ SSR
+ SSR
+ RTC sub second register
+ 0x28
+ 0x20
+ read-only
+ 0x00000000
+
+
+ SS
+ Sub second value
+ 0
+ 16
+
+
+
+
+ SHIFTR
+ SHIFTR
+ RTC shift control register
+ 0x2C
+ 0x20
+ write-only
+ 0x00000000
+
+
+ ADD1S
+ Add one second
+ 31
+ 1
+
+
+ SUBFS
+ Subtract a fraction of a
+ second
+ 0
+ 15
+
+
+
+
+ TSTR
+ TSTR
+ RTC timestamp time register
+ 0x30
+ 0x20
+ read-only
+ 0x00000000
+
+
+ PM
+ AM/PM notation
+ 22
+ 1
+
+
+ HT
+ Hour tens in BCD format.
+ 20
+ 2
+
+
+ HU
+ Hour units in BCD format.
+ 16
+ 4
+
+
+ MNT
+ Minute tens in BCD format.
+ 12
+ 3
+
+
+ MNU
+ Minute units in BCD
+ format.
+ 8
+ 4
+
+
+ ST
+ Second tens in BCD format.
+ 4
+ 3
+
+
+ SU
+ Second units in BCD
+ format.
+ 0
+ 4
+
+
+
+
+ TSDR
+ TSDR
+ RTC timestamp date register
+ 0x34
+ 0x20
+ read-only
+ 0x00000000
+
+
+ WDU
+ Week day units
+ 13
+ 3
+
+
+ MT
+ Month tens in BCD format
+ 12
+ 1
+
+
+ MU
+ Month units in BCD format
+ 8
+ 4
+
+
+ DT
+ Date tens in BCD format
+ 4
+ 2
+
+
+ DU
+ Date units in BCD format
+ 0
+ 4
+
+
+
+
+ TSSSR
+ TSSSR
+ RTC time-stamp sub second
+ register
+ 0x38
+ 0x20
+ read-only
+ 0x00000000
+
+
+ SS
+ Sub second value
+ 0
+ 16
+
+
+
+
+ CALR
+ CALR
+ RTC calibration register
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CALP
+ Increase frequency of RTC by 488.5
+ ppm
+ 15
+ 1
+
+
+ CALW8
+ Use an 8-second calibration cycle
+ period
+ 14
+ 1
+
+
+ CALW16
+ Use a 16-second calibration cycle
+ period
+ 13
+ 1
+
+
+ CALM
+ Calibration minus
+ 0
+ 9
+
+
+
+
+ TAMPCR
+ TAMPCR
+ RTC tamper configuration
+ register
+ 0x40
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TAMP2MF
+ Tamper 2 mask flag
+ 21
+ 1
+
+
+ TAMP2NOERASE
+ Tamper 2 no erase
+ 20
+ 1
+
+
+ TAMP2IE
+ Tamper 2 interrupt enable
+ 19
+ 1
+
+
+ TAMP1MF
+ Tamper 1 mask flag
+ 18
+ 1
+
+
+ TAMP1NOERASE
+ Tamper 1 no erase
+ 17
+ 1
+
+
+ TAMP1IE
+ Tamper 1 interrupt enable
+ 16
+ 1
+
+
+ TAMPPUDIS
+ RTC_TAMPx pull-up disable
+ 15
+ 1
+
+
+ TAMPPRCH
+ RTC_TAMPx precharge
+ duration
+ 13
+ 2
+
+
+ TAMPFLT
+ RTC_TAMPx filter count
+ 11
+ 2
+
+
+ TAMPFREQ
+ Tamper sampling frequency
+ 8
+ 3
+
+
+ TAMPTS
+ Activate timestamp on tamper detection
+ event
+ 7
+ 1
+
+
+ TAMP2_TRG
+ Active level for RTC_TAMP2
+ input
+ 4
+ 1
+
+
+ TAMP2E
+ RTC_TAMP2 input detection
+ enable
+ 3
+ 1
+
+
+ TAMPIE
+ Tamper interrupt enable
+ 2
+ 1
+
+
+ TAMP1TRG
+ Active level for RTC_TAMP1
+ input
+ 1
+ 1
+
+
+ TAMP1E
+ RTC_TAMP1 input detection
+ enable
+ 0
+ 1
+
+
+
+
+ ALRMASSR
+ ALRMASSR
+ RTC alarm A sub second
+ register
+ 0x44
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MASKSS
+ Mask the most-significant bits starting
+ at this bit
+ 24
+ 4
+
+
+ SS
+ Sub seconds value
+ 0
+ 15
+
+
+
+
+ ALRMBSSR
+ ALRMBSSR
+ RTC alarm B sub second
+ register
+ 0x48
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MASKSS
+ Mask the most-significant bits starting
+ at this bit
+ 24
+ 4
+
+
+ SS
+ Sub seconds value
+ 0
+ 15
+
+
+
+
+ OR
+ OR
+ option register
+ 0x4C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ RTC_OUT_RMP
+ RTC_ALARM on PC13 output
+ type
+ 1
+ 1
+
+
+ RTC_ALARM_TYPE
+ RTC_ALARM on PC13 output
+ type
+ 0
+ 1
+
+
+
+
+ BKP0R
+ BKP0R
+ RTC backup registers
+ 0x50
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP1R
+ BKP1R
+ RTC backup registers
+ 0x54
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP2R
+ BKP2R
+ RTC backup registers
+ 0x58
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP3R
+ BKP3R
+ RTC backup registers
+ 0x5C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP4R
+ BKP4R
+ RTC backup registers
+ 0x60
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+
+
+ USART1
+ Universal synchronous asynchronous receiver
+ transmitter
+ USART
+ 0x40013800
+
+ 0x0
+ 0x400
+ registers
+
+
+ USART1
+ USART1 global interrupt
+ 27
+
+
+
+ CR1
+ CR1
+ Control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ M1
+ Word length
+ 28
+ 1
+
+
+ EOBIE
+ End of Block interrupt
+ enable
+ 27
+ 1
+
+
+ RTOIE
+ Receiver timeout interrupt
+ enable
+ 26
+ 1
+
+
+ DEAT4
+ Driver Enable assertion
+ time
+ 25
+ 1
+
+
+ DEAT3
+ DEAT3
+ 24
+ 1
+
+
+ DEAT2
+ DEAT2
+ 23
+ 1
+
+
+ DEAT1
+ DEAT1
+ 22
+ 1
+
+
+ DEAT0
+ DEAT0
+ 21
+ 1
+
+
+ DEDT4
+ Driver Enable de-assertion
+ time
+ 20
+ 1
+
+
+ DEDT3
+ DEDT3
+ 19
+ 1
+
+
+ DEDT2
+ DEDT2
+ 18
+ 1
+
+
+ DEDT1
+ DEDT1
+ 17
+ 1
+
+
+ DEDT0
+ DEDT0
+ 16
+ 1
+
+
+ OVER8
+ Oversampling mode
+ 15
+ 1
+
+
+ CMIE
+ Character match interrupt
+ enable
+ 14
+ 1
+
+
+ MME
+ Mute mode enable
+ 13
+ 1
+
+
+ M0
+ Word length
+ 12
+ 1
+
+
+ WAKE
+ Receiver wakeup method
+ 11
+ 1
+
+
+ PCE
+ Parity control enable
+ 10
+ 1
+
+
+ PS
+ Parity selection
+ 9
+ 1
+
+
+ PEIE
+ PE interrupt enable
+ 8
+ 1
+
+
+ TXEIE
+ interrupt enable
+ 7
+ 1
+
+
+ TCIE
+ Transmission complete interrupt
+ enable
+ 6
+ 1
+
+
+ RXNEIE
+ RXNE interrupt enable
+ 5
+ 1
+
+
+ IDLEIE
+ IDLE interrupt enable
+ 4
+ 1
+
+
+ TE
+ Transmitter enable
+ 3
+ 1
+
+
+ RE
+ Receiver enable
+ 2
+ 1
+
+
+ UESM
+ USART enable in Stop mode
+ 1
+ 1
+
+
+ UE
+ USART enable
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ Control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ ADD4_7
+ Address of the USART node
+ 28
+ 4
+
+
+ ADD0_3
+ Address of the USART node
+ 24
+ 4
+
+
+ RTOEN
+ Receiver timeout enable
+ 23
+ 1
+
+
+ ABRMOD1
+ Auto baud rate mode
+ 22
+ 1
+
+
+ ABRMOD0
+ ABRMOD0
+ 21
+ 1
+
+
+ ABREN
+ Auto baud rate enable
+ 20
+ 1
+
+
+ MSBFIRST
+ Most significant bit first
+ 19
+ 1
+
+
+ TAINV
+ Binary data inversion
+ 18
+ 1
+
+
+ TXINV
+ TX pin active level
+ inversion
+ 17
+ 1
+
+
+ RXINV
+ RX pin active level
+ inversion
+ 16
+ 1
+
+
+ SWAP
+ Swap TX/RX pins
+ 15
+ 1
+
+
+ LINEN
+ LIN mode enable
+ 14
+ 1
+
+
+ STOP
+ STOP bits
+ 12
+ 2
+
+
+ CLKEN
+ Clock enable
+ 11
+ 1
+
+
+ CPOL
+ Clock polarity
+ 10
+ 1
+
+
+ CPHA
+ Clock phase
+ 9
+ 1
+
+
+ LBCL
+ Last bit clock pulse
+ 8
+ 1
+
+
+ LBDIE
+ LIN break detection interrupt
+ enable
+ 6
+ 1
+
+
+ LBDL
+ LIN break detection length
+ 5
+ 1
+
+
+ ADDM7
+ 7-bit Address Detection/4-bit Address
+ Detection
+ 4
+ 1
+
+
+
+
+ CR3
+ CR3
+ Control register 3
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ WUFIE
+ Wakeup from Stop mode interrupt
+ enable
+ 22
+ 1
+
+
+ WUS
+ Wakeup from Stop mode interrupt flag
+ selection
+ 20
+ 2
+
+
+ SCARCNT
+ Smartcard auto-retry count
+ 17
+ 3
+
+
+ DEP
+ Driver enable polarity
+ selection
+ 15
+ 1
+
+
+ DEM
+ Driver enable mode
+ 14
+ 1
+
+
+ DDRE
+ DMA Disable on Reception
+ Error
+ 13
+ 1
+
+
+ OVRDIS
+ Overrun Disable
+ 12
+ 1
+
+
+ ONEBIT
+ One sample bit method
+ enable
+ 11
+ 1
+
+
+ CTSIE
+ CTS interrupt enable
+ 10
+ 1
+
+
+ CTSE
+ CTS enable
+ 9
+ 1
+
+
+ RTSE
+ RTS enable
+ 8
+ 1
+
+
+ DMAT
+ DMA enable transmitter
+ 7
+ 1
+
+
+ DMAR
+ DMA enable receiver
+ 6
+ 1
+
+
+ SCEN
+ Smartcard mode enable
+ 5
+ 1
+
+
+ NACK
+ Smartcard NACK enable
+ 4
+ 1
+
+
+ HDSEL
+ Half-duplex selection
+ 3
+ 1
+
+
+ IRLP
+ Ir low-power
+ 2
+ 1
+
+
+ IREN
+ Ir mode enable
+ 1
+ 1
+
+
+ EIE
+ Error interrupt enable
+ 0
+ 1
+
+
+
+
+ BRR
+ BRR
+ Baud rate register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ DIV_Mantissa
+ DIV_Mantissa
+ 4
+ 12
+
+
+ DIV_Fraction
+ DIV_Fraction
+ 0
+ 4
+
+
+
+
+ GTPR
+ GTPR
+ Guard time and prescaler
+ register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ GT
+ Guard time value
+ 8
+ 8
+
+
+ PSC
+ Prescaler value
+ 0
+ 8
+
+
+
+
+ RTOR
+ RTOR
+ Receiver timeout register
+ 0x14
+ 0x20
+ read-write
+ 0x0000
+
+
+ BLEN
+ Block Length
+ 24
+ 8
+
+
+ RTO
+ Receiver timeout value
+ 0
+ 24
+
+
+
+
+ RQR
+ RQR
+ Request register
+ 0x18
+ 0x20
+ write-only
+ 0x0000
+
+
+ TXFRQ
+ Transmit data flush
+ request
+ 4
+ 1
+
+
+ RXFRQ
+ Receive data flush request
+ 3
+ 1
+
+
+ MMRQ
+ Mute mode request
+ 2
+ 1
+
+
+ SBKRQ
+ Send break request
+ 1
+ 1
+
+
+ ABRRQ
+ Auto baud rate request
+ 0
+ 1
+
+
+
+
+ ISR
+ ISR
+ Interrupt & status
+ register
+ 0x1C
+ 0x20
+ read-only
+ 0x00C0
+
+
+ REACK
+ REACK
+ 22
+ 1
+
+
+ TEACK
+ TEACK
+ 21
+ 1
+
+
+ WUF
+ WUF
+ 20
+ 1
+
+
+ RWU
+ RWU
+ 19
+ 1
+
+
+ SBKF
+ SBKF
+ 18
+ 1
+
+
+ CMF
+ CMF
+ 17
+ 1
+
+
+ BUSY
+ BUSY
+ 16
+ 1
+
+
+ ABRF
+ ABRF
+ 15
+ 1
+
+
+ ABRE
+ ABRE
+ 14
+ 1
+
+
+ EOBF
+ EOBF
+ 12
+ 1
+
+
+ RTOF
+ RTOF
+ 11
+ 1
+
+
+ CTS
+ CTS
+ 10
+ 1
+
+
+ CTSIF
+ CTSIF
+ 9
+ 1
+
+
+ LBDF
+ LBDF
+ 8
+ 1
+
+
+ TXE
+ TXE
+ 7
+ 1
+
+
+ TC
+ TC
+ 6
+ 1
+
+
+ RXNE
+ RXNE
+ 5
+ 1
+
+
+ IDLE
+ IDLE
+ 4
+ 1
+
+
+ ORE
+ ORE
+ 3
+ 1
+
+
+ NF
+ NF
+ 2
+ 1
+
+
+ FE
+ FE
+ 1
+ 1
+
+
+ PE
+ PE
+ 0
+ 1
+
+
+
+
+ ICR
+ ICR
+ Interrupt flag clear register
+ 0x20
+ 0x20
+ write-only
+ 0x0000
+
+
+ WUCF
+ Wakeup from Stop mode clear
+ flag
+ 20
+ 1
+
+
+ CMCF
+ Character match clear flag
+ 17
+ 1
+
+
+ EOBCF
+ End of block clear flag
+ 12
+ 1
+
+
+ RTOCF
+ Receiver timeout clear
+ flag
+ 11
+ 1
+
+
+ CTSCF
+ CTS clear flag
+ 9
+ 1
+
+
+ LBDCF
+ LIN break detection clear
+ flag
+ 8
+ 1
+
+
+ TCCF
+ Transmission complete clear
+ flag
+ 6
+ 1
+
+
+ IDLECF
+ Idle line detected clear
+ flag
+ 4
+ 1
+
+
+ ORECF
+ Overrun error clear flag
+ 3
+ 1
+
+
+ NCF
+ Noise detected clear flag
+ 2
+ 1
+
+
+ FECF
+ Framing error clear flag
+ 1
+ 1
+
+
+ PECF
+ Parity error clear flag
+ 0
+ 1
+
+
+
+
+ RDR
+ RDR
+ Receive data register
+ 0x24
+ 0x20
+ read-only
+ 0x0000
+
+
+ RDR
+ Receive data value
+ 0
+ 9
+
+
+
+
+ TDR
+ TDR
+ Transmit data register
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ TDR
+ Transmit data value
+ 0
+ 9
+
+
+
+
+
+
+ USART2
+ 0x40004400
+
+
+ USART4
+ 0x40004C00
+
+ USART4_USART5
+ USART4/USART5 global interrupt
+ 14
+
+
+
+ USART5
+ 0x40005000
+
+ USART2
+ USART2 global interrupt
+ 28
+
+
+
+ IWDG
+ Independent watchdog
+ IWDG
+ 0x40003000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ KR
+ KR
+ Key register
+ 0x0
+ 0x20
+ write-only
+ 0x00000000
+
+
+ KEY
+ Key value (write only, read
+ 0x0000)
+ 0
+ 16
+
+
+
+
+ PR
+ PR
+ Prescaler register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PR
+ Prescaler divider
+ 0
+ 3
+
+
+
+
+ RLR
+ RLR
+ Reload register
+ 0x8
+ 0x20
+ read-write
+ 0x00000FFF
+
+
+ RL
+ Watchdog counter reload
+ value
+ 0
+ 12
+
+
+
+
+ SR
+ SR
+ Status register
+ 0xC
+ 0x20
+ read-only
+ 0x00000000
+
+
+ WVU
+ Watchdog counter window value
+ update
+ 2
+ 1
+
+
+ RVU
+ Watchdog counter reload value
+ update
+ 1
+ 1
+
+
+ PVU
+ Watchdog prescaler value
+ update
+ 0
+ 1
+
+
+
+
+ WINR
+ WINR
+ Window register
+ 0x10
+ 0x20
+ read-write
+ 0x00000FFF
+
+
+ WIN
+ Watchdog counter window
+ value
+ 0
+ 12
+
+
+
+
+
+
+ WWDG
+ System window watchdog
+ WWDG
+ 0x40002C00
+
+ 0x0
+ 0x400
+ registers
+
+
+ WWDG
+ Window Watchdog interrupt
+ 0
+
+
+
+ CR
+ CR
+ Control register
+ 0x0
+ 0x20
+ read-write
+ 0x0000007F
+
+
+ WDGA
+ Activation bit
+ 7
+ 1
+
+
+ T
+ 7-bit counter (MSB to LSB)
+ 0
+ 7
+
+
+
+
+ CFR
+ CFR
+ Configuration register
+ 0x4
+ 0x20
+ read-write
+ 0x0000007F
+
+
+ EWI
+ Early wakeup interrupt
+ 9
+ 1
+
+
+ WDGTB1
+ Timer base
+ 8
+ 1
+
+
+ WDGTB0
+ WDGTB0
+ 7
+ 1
+
+
+ W
+ 7-bit window value
+ 0
+ 7
+
+
+
+
+ SR
+ SR
+ Status register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EWIF
+ Early wakeup interrupt
+ flag
+ 0
+ 1
+
+
+
+
+
+
+ Firewall
+ Firewall
+ Firewall
+ 0x40011C00
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ FIREWALL_CSSA
+ FIREWALL_CSSA
+ Code segment start address
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ADD
+ code segment start address
+ 8
+ 16
+
+
+
+
+ FIREWALL_CSL
+ FIREWALL_CSL
+ Code segment length
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LENG
+ code segment length
+ 8
+ 14
+
+
+
+
+ FIREWALL_NVDSSA
+ FIREWALL_NVDSSA
+ Non-volatile data segment start
+ address
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ADD
+ Non-volatile data segment start
+ address
+ 8
+ 16
+
+
+
+
+ FIREWALL_NVDSL
+ FIREWALL_NVDSL
+ Non-volatile data segment
+ length
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LENG
+ Non-volatile data segment
+ length
+ 8
+ 14
+
+
+
+
+ FIREWALL_VDSSA
+ FIREWALL_VDSSA
+ Volatile data segment start
+ address
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ADD
+ Volatile data segment start
+ address
+ 6
+ 10
+
+
+
+
+ FIREWALL_VDSL
+ FIREWALL_VDSL
+ Volatile data segment length
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LENG
+ Non-volatile data segment
+ length
+ 6
+ 10
+
+
+
+
+ FIREWALL_CR
+ FIREWALL_CR
+ Configuration register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ VDE
+ Volatile data execution
+ 2
+ 1
+
+
+ VDS
+ Volatile data shared
+ 1
+ 1
+
+
+ FPA
+ Firewall pre alarm
+ 0
+ 1
+
+
+
+
+
+
+ RCC
+ Reset and clock control
+ RCC
+ 0x40021000
+
+ 0x0
+ 0x400
+ registers
+
+
+ RCC
+ RCC global interrupt
+ 4
+
+
+
+ CR
+ CR
+ Clock control register
+ 0x0
+ 0x20
+ 0x00000300
+
+
+ PLLRDY
+ PLL clock ready flag
+ 25
+ 1
+ read-only
+
+
+ PLLON
+ PLL enable bit
+ 24
+ 1
+ read-write
+
+
+ RTCPRE
+ TC/LCD prescaler
+ 20
+ 2
+ read-write
+
+
+ CSSLSEON
+ Clock security system on HSE enable
+ bit
+ 19
+ 1
+ read-write
+
+
+ HSEBYP
+ HSE clock bypass bit
+ 18
+ 1
+ read-write
+
+
+ HSERDY
+ HSE clock ready flag
+ 17
+ 1
+ read-only
+
+
+ HSEON
+ HSE clock enable bit
+ 16
+ 1
+ read-write
+
+
+ MSIRDY
+ MSI clock ready flag
+ 9
+ 1
+ read-only
+
+
+ MSION
+ MSI clock enable bit
+ 8
+ 1
+ read-write
+
+
+ HSI16DIVF
+ HSI16DIVF
+ 4
+ 1
+ read-only
+
+
+ HSI16DIVEN
+ HSI16DIVEN
+ 3
+ 1
+ read-write
+
+
+ HSI16RDYF
+ Internal high-speed clock ready
+ flag
+ 2
+ 1
+ read-write
+
+
+ HSI16KERON
+ High-speed internal clock enable bit for
+ some IP kernels
+ 1
+ 1
+ read-only
+
+
+ HSI16ON
+ 16 MHz high-speed internal clock
+ enable
+ 0
+ 1
+ read-write
+
+
+ HSI16OUTEN
+ 16 MHz high-speed internal clock output
+ enable
+ 5
+ 1
+ read-write
+
+
+
+
+ ICSCR
+ ICSCR
+ Internal clock sources calibration
+ register
+ 0x4
+ 0x20
+ 0x0000B000
+
+
+ MSITRIM
+ MSI clock trimming
+ 24
+ 8
+ read-write
+
+
+ MSICAL
+ MSI clock calibration
+ 16
+ 8
+ read-only
+
+
+ MSIRANGE
+ MSI clock ranges
+ 13
+ 3
+ read-write
+
+
+ HSI16TRIM
+ High speed internal clock
+ trimming
+ 8
+ 5
+ read-write
+
+
+ HSI16CAL
+ nternal high speed clock
+ calibration
+ 0
+ 8
+ read-only
+
+
+
+
+ CFGR
+ CFGR
+ Clock configuration register
+ 0xC
+ 0x20
+ 0x00000000
+
+
+ MCOPRE
+ Microcontroller clock output
+ prescaler
+ 28
+ 3
+ read-write
+
+
+ MCOSEL
+ Microcontroller clock output
+ selection
+ 24
+ 3
+ read-write
+
+
+ PLLDIV
+ PLL output division
+ 22
+ 2
+ read-write
+
+
+ PLLMUL
+ PLL multiplication factor
+ 18
+ 4
+ read-write
+
+
+ PLLSRC
+ PLL entry clock source
+ 16
+ 1
+ read-write
+
+
+ STOPWUCK
+ Wake-up from stop clock
+ selection
+ 15
+ 1
+ read-write
+
+
+ PPRE2
+ APB high-speed prescaler
+ (APB2)
+ 11
+ 3
+ read-write
+
+
+ PPRE1
+ APB low-speed prescaler
+ (APB1)
+ 8
+ 3
+ read-write
+
+
+ HPRE
+ AHB prescaler
+ 4
+ 4
+ read-write
+
+
+ SWS
+ System clock switch status
+ 2
+ 2
+ read-only
+
+
+ SW
+ System clock switch
+ 0
+ 2
+ read-write
+
+
+
+
+ CIER
+ CIER
+ Clock interrupt enable
+ register
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CSSLSE
+ LSE CSS interrupt flag
+ 7
+ 1
+
+
+ MSIRDYIE
+ MSI ready interrupt flag
+ 5
+ 1
+
+
+ PLLRDYIE
+ PLL ready interrupt flag
+ 4
+ 1
+
+
+ HSERDYIE
+ HSE ready interrupt flag
+ 3
+ 1
+
+
+ HSI16RDYIE
+ HSI16 ready interrupt flag
+ 2
+ 1
+
+
+ LSERDYIE
+ LSE ready interrupt flag
+ 1
+ 1
+
+
+ LSIRDYIE
+ LSI ready interrupt flag
+ 0
+ 1
+
+
+
+
+ CIFR
+ CIFR
+ Clock interrupt flag register
+ 0x14
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CSSHSEF
+ Clock Security System Interrupt
+ flag
+ 8
+ 1
+
+
+ CSSLSEF
+ LSE Clock Security System Interrupt
+ flag
+ 7
+ 1
+
+
+ MSIRDYF
+ MSI ready interrupt flag
+ 5
+ 1
+
+
+ PLLRDYF
+ PLL ready interrupt flag
+ 4
+ 1
+
+
+ HSERDYF
+ HSE ready interrupt flag
+ 3
+ 1
+
+
+ HSI16RDYF
+ HSI16 ready interrupt flag
+ 2
+ 1
+
+
+ LSERDYF
+ LSE ready interrupt flag
+ 1
+ 1
+
+
+ LSIRDYF
+ LSI ready interrupt flag
+ 0
+ 1
+
+
+
+
+ CICR
+ CICR
+ Clock interrupt clear register
+ 0x18
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CSSHSEC
+ Clock Security System Interrupt
+ clear
+ 8
+ 1
+
+
+ CSSLSEC
+ LSE Clock Security System Interrupt
+ clear
+ 7
+ 1
+
+
+ MSIRDYC
+ MSI ready Interrupt clear
+ 5
+ 1
+
+
+ PLLRDYC
+ PLL ready Interrupt clear
+ 4
+ 1
+
+
+ HSERDYC
+ HSE ready Interrupt clear
+ 3
+ 1
+
+
+ HSI16RDYC
+ HSI16 ready Interrupt
+ clear
+ 2
+ 1
+
+
+ LSERDYC
+ LSE ready Interrupt clear
+ 1
+ 1
+
+
+ LSIRDYC
+ LSI ready Interrupt clear
+ 0
+ 1
+
+
+
+
+ IOPRSTR
+ IOPRSTR
+ GPIO reset register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IOPHRST
+ I/O port H reset
+ 7
+ 1
+
+
+ IOPDRST
+ I/O port D reset
+ 3
+ 1
+
+
+ IOPCRST
+ I/O port A reset
+ 2
+ 1
+
+
+ IOPBRST
+ I/O port B reset
+ 1
+ 1
+
+
+ IOPARST
+ I/O port A reset
+ 0
+ 1
+
+
+ IOPERST
+ I/O port E reset
+ 4
+ 1
+
+
+
+
+ AHBRSTR
+ AHBRSTR
+ AHB peripheral reset register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CRYPRST
+ Crypto module reset
+ 24
+ 1
+
+
+ CRCRST
+ Test integration module
+ reset
+ 12
+ 1
+
+
+ MIFRST
+ Memory interface reset
+ 8
+ 1
+
+
+ DMARST
+ DMA reset
+ 0
+ 1
+
+
+
+
+ APB2RSTR
+ APB2RSTR
+ APB2 peripheral reset register
+ 0x24
+ 0x20
+ read-write
+ 0x000000000
+
+
+ DBGRST
+ DBG reset
+ 22
+ 1
+
+
+ USART1RST
+ USART1 reset
+ 14
+ 1
+
+
+ SPI1RST
+ SPI 1 reset
+ 12
+ 1
+
+
+ ADCRST
+ ADC interface reset
+ 9
+ 1
+
+
+ TIM22RST
+ TIM22 timer reset
+ 5
+ 1
+
+
+ TIM21RST
+ TIM21 timer reset
+ 2
+ 1
+
+
+ SYSCFGRST
+ System configuration controller
+ reset
+ 0
+ 1
+
+
+
+
+ APB1RSTR
+ APB1RSTR
+ APB1 peripheral reset register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LPTIM1RST
+ Low power timer reset
+ 31
+ 1
+
+
+ PWRRST
+ Power interface reset
+ 28
+ 1
+
+
+ I2C2RST
+ I2C2 reset
+ 22
+ 1
+
+
+ I2C1RST
+ I2C1 reset
+ 21
+ 1
+
+
+ LPUART1RST
+ LPUART1 reset
+ 18
+ 1
+
+
+ USART2RST
+ USART2 reset
+ 17
+ 1
+
+
+ SPI2RST
+ SPI2 reset
+ 14
+ 1
+
+
+ WWDGRST
+ Window watchdog reset
+ 11
+ 1
+
+
+ TIM6RST
+ Timer 6 reset
+ 4
+ 1
+
+
+ TIM2RST
+ Timer 2 reset
+ 0
+ 1
+
+
+ TIM3RST
+ Timer 3 reset
+ 1
+ 1
+
+
+ TIM7RST
+ Timer 7 reset
+ 5
+ 1
+
+
+ USART4RST
+ USART4 reset
+ 19
+ 1
+
+
+ USART5RST
+ USART5 reset
+ 20
+ 1
+
+
+ CRCRST
+ CRC reset
+ 27
+ 1
+
+
+ I2C3
+ I2C3 reset
+ 30
+ 1
+
+
+
+
+ IOPENR
+ IOPENR
+ GPIO clock enable register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IOPHEN
+ I/O port H clock enable
+ bit
+ 7
+ 1
+
+
+ IOPDEN
+ I/O port D clock enable
+ bit
+ 3
+ 1
+
+
+ IOPCEN
+ IO port A clock enable bit
+ 2
+ 1
+
+
+ IOPBEN
+ IO port B clock enable bit
+ 1
+ 1
+
+
+ IOPAEN
+ IO port A clock enable bit
+ 0
+ 1
+
+
+ IOPEEN
+ IO port E clock enable bit
+ 4
+ 1
+
+
+
+
+ AHBENR
+ AHBENR
+ AHB peripheral clock enable
+ register
+ 0x30
+ 0x20
+ read-write
+ 0x00000100
+
+
+ CRYPEN
+ Crypto clock enable bit
+ 24
+ 1
+
+
+ CRCEN
+ CRC clock enable bit
+ 12
+ 1
+
+
+ MIFEN
+ NVM interface clock enable
+ bit
+ 8
+ 1
+
+
+ DMAEN
+ DMA clock enable bit
+ 0
+ 1
+
+
+
+
+ APB2ENR
+ APB2ENR
+ APB2 peripheral clock enable
+ register
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DBGEN
+ DBG clock enable bit
+ 22
+ 1
+
+
+ USART1EN
+ USART1 clock enable bit
+ 14
+ 1
+
+
+ SPI1EN
+ SPI1 clock enable bit
+ 12
+ 1
+
+
+ ADCEN
+ ADC clock enable bit
+ 9
+ 1
+
+
+ FWEN
+ Firewall clock enable bit
+ 7
+ 1
+
+
+ TIM22EN
+ TIM22 timer clock enable
+ bit
+ 5
+ 1
+
+
+ TIM21EN
+ TIM21 timer clock enable
+ bit
+ 2
+ 1
+
+
+ SYSCFGEN
+ System configuration controller clock
+ enable bit
+ 0
+ 1
+
+
+
+
+ APB1ENR
+ APB1ENR
+ APB1 peripheral clock enable
+ register
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LPTIM1EN
+ Low power timer clock enable
+ bit
+ 31
+ 1
+
+
+ PWREN
+ Power interface clock enable
+ bit
+ 28
+ 1
+
+
+ I2C2EN
+ I2C2 clock enable bit
+ 22
+ 1
+
+
+ I2C1EN
+ I2C1 clock enable bit
+ 21
+ 1
+
+
+ LPUART1EN
+ LPUART1 clock enable bit
+ 18
+ 1
+
+
+ USART2EN
+ UART2 clock enable bit
+ 17
+ 1
+
+
+ SPI2EN
+ SPI2 clock enable bit
+ 14
+ 1
+
+
+ WWDGEN
+ Window watchdog clock enable
+ bit
+ 11
+ 1
+
+
+ TIM6EN
+ Timer 6 clock enable bit
+ 4
+ 1
+
+
+ TIM2EN
+ Timer2 clock enable bit
+ 0
+ 1
+
+
+ TIM3EN
+ Timer 3 clock enbale bit
+ 2
+ 1
+
+
+ TIM7EN
+ Timer 7 clock enable bit
+ 5
+ 1
+
+
+ USART4EN
+ USART4 clock enable bit
+ 19
+ 1
+
+
+ USART5EN
+ USART5 clock enable bit
+ 20
+ 1
+
+
+ I2C3EN
+ I2C3 clock enable bit
+ 30
+ 1
+
+
+
+
+ IOPSMEN
+ IOPSMEN
+ GPIO clock enable in sleep mode
+ register
+ 0x3C
+ 0x20
+ read-write
+ 0x0000008F
+
+
+ IOPHSMEN
+ Port H clock enable during Sleep mode
+ bit
+ 7
+ 1
+
+
+ IOPDSMEN
+ Port D clock enable during Sleep mode
+ bit
+ 3
+ 1
+
+
+ IOPCSMEN
+ Port C clock enable during Sleep mode
+ bit
+ 2
+ 1
+
+
+ IOPBSMEN
+ Port B clock enable during Sleep mode
+ bit
+ 1
+ 1
+
+
+ IOPASMEN
+ Port A clock enable during Sleep mode
+ bit
+ 0
+ 1
+
+
+ IOPESMEN
+ Port E clock enable during Sleep mode
+ bit
+ 4
+ 1
+
+
+
+
+ AHBSMENR
+ AHBSMENR
+ AHB peripheral clock enable in sleep mode
+ register
+ 0x40
+ 0x20
+ read-write
+ 0x01111301
+
+
+ CRYPTSMEN
+ Crypto clock enable during sleep mode
+ bit
+ 24
+ 1
+
+
+ CRCSMEN
+ CRC clock enable during sleep mode
+ bit
+ 12
+ 1
+
+
+ SRAMSMEN
+ SRAM interface clock enable during sleep
+ mode bit
+ 9
+ 1
+
+
+ MIFSMEN
+ NVM interface clock enable during sleep
+ mode bit
+ 8
+ 1
+
+
+ DMASMEN
+ DMA clock enable during sleep mode
+ bit
+ 0
+ 1
+
+
+
+
+ APB2SMENR
+ APB2SMENR
+ APB2 peripheral clock enable in sleep mode
+ register
+ 0x44
+ 0x20
+ read-write
+ 0x00405225
+
+
+ DBGSMEN
+ DBG clock enable during sleep mode
+ bit
+ 22
+ 1
+
+
+ USART1SMEN
+ USART1 clock enable during sleep mode
+ bit
+ 14
+ 1
+
+
+ SPI1SMEN
+ SPI1 clock enable during sleep mode
+ bit
+ 12
+ 1
+
+
+ ADCSMEN
+ ADC clock enable during sleep mode
+ bit
+ 9
+ 1
+
+
+ TIM22SMEN
+ TIM22 timer clock enable during sleep
+ mode bit
+ 5
+ 1
+
+
+ TIM21SMEN
+ TIM21 timer clock enable during sleep
+ mode bit
+ 2
+ 1
+
+
+ SYSCFGSMEN
+ System configuration controller clock
+ enable during sleep mode bit
+ 0
+ 1
+
+
+
+
+ APB1SMENR
+ APB1SMENR
+ APB1 peripheral clock enable in sleep mode
+ register
+ 0x48
+ 0x20
+ read-write
+ 0xB8E64A11
+
+
+ LPTIM1SMEN
+ Low power timer clock enable during
+ sleep mode bit
+ 31
+ 1
+
+
+ PWRSMEN
+ Power interface clock enable during
+ sleep mode bit
+ 28
+ 1
+
+
+ CRSSMEN
+ Clock recovery system clock enable
+ during sleep mode bit
+ 27
+ 1
+
+
+ I2C2SMEN
+ I2C2 clock enable during sleep mode
+ bit
+ 22
+ 1
+
+
+ I2C1SMEN
+ I2C1 clock enable during sleep mode
+ bit
+ 21
+ 1
+
+
+ LPUART1SMEN
+ LPUART1 clock enable during sleep mode
+ bit
+ 18
+ 1
+
+
+ USART2SMEN
+ UART2 clock enable during sleep mode
+ bit
+ 17
+ 1
+
+
+ SPI2SMEN
+ SPI2 clock enable during sleep mode
+ bit
+ 14
+ 1
+
+
+ WWDGSMEN
+ Window watchdog clock enable during
+ sleep mode bit
+ 11
+ 1
+
+
+ TIM6SMEN
+ Timer 6 clock enable during sleep mode
+ bit
+ 4
+ 1
+
+
+ TIM2SMEN
+ Timer2 clock enable during sleep mode
+ bit
+ 0
+ 1
+
+
+ TIM3SMEN
+ Timer 3 clock enable during sleep mode
+ bit
+ 1
+ 1
+
+
+ TIM7SMEN
+ Timer 7 clock enable during sleep mode
+ bit
+ 5
+ 1
+
+
+ USART4SMEN
+ USART4 clock enabe during sleep mode
+ bit
+ 19
+ 1
+
+
+ USART5SMEN
+ USART5 clock enable during sleep mode
+ bit
+ 20
+ 1
+
+
+ I2C3SMEN
+ I2C3 clock enable during sleep mode
+ bit
+ 30
+ 1
+
+
+
+
+ CCIPR
+ CCIPR
+ Clock configuration register
+ 0x4C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LPTIM1SEL1
+ Low Power Timer clock source selection
+ bits
+ 19
+ 1
+
+
+ LPTIM1SEL0
+ LPTIM1SEL0
+ 18
+ 1
+
+
+ I2C1SEL1
+ I2C1 clock source selection
+ bits
+ 13
+ 1
+
+
+ I2C1SEL0
+ I2C1SEL0
+ 12
+ 1
+
+
+ LPUART1SEL1
+ LPUART1 clock source selection
+ bits
+ 11
+ 1
+
+
+ LPUART1SEL0
+ LPUART1SEL0
+ 10
+ 1
+
+
+ USART2SEL1
+ USART2 clock source selection
+ bits
+ 3
+ 1
+
+
+ USART2SEL0
+ USART2SEL0
+ 2
+ 1
+
+
+ USART1SEL1
+ USART1 clock source selection
+ bits
+ 1
+ 1
+
+
+ USART1SEL0
+ USART1SEL0
+ 0
+ 1
+
+
+ I2C3SEL0
+ I2C3 clock source selection
+ bits
+ 16
+ 1
+
+
+ I2C3SEL1
+ I2C3 clock source selection
+ bits
+ 17
+ 1
+
+
+
+
+ CSR
+ CSR
+ Control and status register
+ 0x50
+ 0x20
+ 0x0C000000
+
+
+ LPWRSTF
+ Low-power reset flag
+ 31
+ 1
+ read-write
+
+
+ WWDGRSTF
+ Window watchdog reset flag
+ 30
+ 1
+ read-write
+
+
+ IWDGRSTF
+ Independent watchdog reset
+ flag
+ 29
+ 1
+ read-write
+
+
+ SFTRSTF
+ Software reset flag
+ 28
+ 1
+ read-write
+
+
+ PORRSTF
+ POR/PDR reset flag
+ 27
+ 1
+ read-write
+
+
+ PINRSTF
+ PIN reset flag
+ 26
+ 1
+ read-write
+
+
+ OBLRSTF
+ OBLRSTF
+ 25
+ 1
+ read-write
+
+
+ FWRSTF
+ Firewall reset flag
+ 24
+ 1
+ read-write
+
+
+ RTCRST
+ RTC software reset bit
+ 19
+ 1
+ read-write
+
+
+ RTCEN
+ RTC clock enable bit
+ 18
+ 1
+ read-write
+
+
+ RTCSEL
+ RTC and LCD clock source selection
+ bits
+ 16
+ 2
+ read-write
+
+
+ CSSLSED
+ CSS on LSE failure detection
+ flag
+ 14
+ 1
+ read-write
+
+
+ CSSLSEON
+ CSSLSEON
+ 13
+ 1
+ read-write
+
+
+ LSEDRV
+ LSEDRV
+ 11
+ 2
+ read-write
+
+
+ LSEBYP
+ External low-speed oscillator bypass
+ bit
+ 10
+ 1
+ read-write
+
+
+ LSERDY
+ External low-speed oscillator ready
+ bit
+ 9
+ 1
+ read-only
+
+
+ LSEON
+ External low-speed oscillator enable
+ bit
+ 8
+ 1
+ read-write
+
+
+ LSIRDY
+ Internal low-speed oscillator ready
+ bit
+ 1
+ 1
+ read-only
+
+
+ LSION
+ Internal low-speed oscillator
+ enable
+ 0
+ 1
+ read-write
+
+
+ LSIIWDGLP
+ LSI clock input to IWDG in
+ Ultra-low-power mode (Stop and Standby) enable
+ bit
+ 2
+ 1
+ read-write
+
+
+ RMVF
+ Remove reset flag
+ 23
+ 1
+ read-write
+
+
+
+
+
+
+ SYSCFG_COMP
+ System configuration controller and COMP
+ register
+ SYSCFG
+ 0x40010000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CFGR1
+ CFGR1
+ SYSCFG configuration register
+ 1
+ 0x0
+ 0x20
+ 0x00000000
+
+
+ BOOT_MODE
+ Boot mode selected by the boot pins
+ status bits
+ 8
+ 2
+ read-only
+
+
+ MEM_MODE
+ Memory mapping selection
+ bits
+ 0
+ 2
+ read-write
+
+
+
+
+ CFGR2
+ CFGR2
+ SYSCFG configuration register
+ 2
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ I2C2_FMP
+ I2C2 Fm+ drive capability enable
+ bit
+ 13
+ 1
+
+
+ I2C1_FMP
+ I2C1 Fm+ drive capability enable
+ bit
+ 12
+ 1
+
+
+ I2C_PB9_FMP
+ Fm+ drive capability on PB9 enable
+ bit
+ 11
+ 1
+
+
+ I2C_PB8_FMP
+ Fm+ drive capability on PB8 enable
+ bit
+ 10
+ 1
+
+
+ I2C_PB7_FMP
+ Fm+ drive capability on PB7 enable
+ bit
+ 9
+ 1
+
+
+ I2C_PB6_FMP
+ Fm+ drive capability on PB6 enable
+ bit
+ 8
+ 1
+
+
+ CAPA
+ Configuration of internal VLCD rail
+ connection to optional external
+ capacitor
+ 1
+ 3
+
+
+ FWDISEN
+ Firewall disable bit
+ 0
+ 1
+
+
+
+
+ EXTICR1
+ EXTICR1
+ external interrupt configuration register
+ 1
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ EXTI3
+ EXTI x configuration (x = 0 to
+ 3)
+ 12
+ 4
+
+
+ EXTI2
+ EXTI x configuration (x = 0 to
+ 3)
+ 8
+ 4
+
+
+ EXTI1
+ EXTI x configuration (x = 0 to
+ 3)
+ 4
+ 4
+
+
+ EXTI0
+ EXTI x configuration (x = 0 to
+ 3)
+ 0
+ 4
+
+
+
+
+ EXTICR2
+ EXTICR2
+ external interrupt configuration register
+ 2
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ EXTI7
+ EXTI x configuration (x = 4 to
+ 7)
+ 12
+ 4
+
+
+ EXTI6
+ EXTI x configuration (x = 4 to
+ 7)
+ 8
+ 4
+
+
+ EXTI5
+ EXTI x configuration (x = 4 to
+ 7)
+ 4
+ 4
+
+
+ EXTI4
+ EXTI x configuration (x = 4 to
+ 7)
+ 0
+ 4
+
+
+
+
+ EXTICR3
+ EXTICR3
+ external interrupt configuration register
+ 3
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ EXTI11
+ EXTI x configuration (x = 8 to
+ 11)
+ 12
+ 4
+
+
+ EXTI10
+ EXTI10
+ 8
+ 4
+
+
+ EXTI9
+ EXTI x configuration (x = 8 to
+ 11)
+ 4
+ 4
+
+
+ EXTI8
+ EXTI x configuration (x = 8 to
+ 11)
+ 0
+ 4
+
+
+
+
+ EXTICR4
+ EXTICR4
+ external interrupt configuration register
+ 4
+ 0x14
+ 0x20
+ read-write
+ 0x0000
+
+
+ EXTI15
+ EXTI x configuration (x = 12 to
+ 15)
+ 12
+ 4
+
+
+ EXTI14
+ EXTI14
+ 8
+ 4
+
+
+ EXTI13
+ EXTI13
+ 4
+ 4
+
+
+ EXTI12
+ EXTI12
+ 0
+ 4
+
+
+
+
+ CFGR3
+ CFGR3
+ SYSCFG configuration register
+ 3
+ 0x20
+ 0x20
+ 0x00000000
+
+
+ REF_LOCK
+ REF_CTRL lock bit
+ 31
+ 1
+ write-only
+
+
+ VREFINT_RDYF
+ VREFINT ready flag
+ 30
+ 1
+ read-only
+
+
+ VREFINT_COMP_RDYF
+ VREFINT for comparator ready
+ flag
+ 29
+ 1
+ read-only
+
+
+ VREFINT_ADC_RDYF
+ VREFINT for ADC ready flag
+ 28
+ 1
+ read-only
+
+
+ SENSOR_ADC_RDYF
+ Sensor for ADC ready flag
+ 27
+ 1
+ read-only
+
+
+ REF_RC48MHz_RDYF
+ VREFINT for 48 MHz RC oscillator ready
+ flag
+ 26
+ 1
+ read-only
+
+
+ ENREF_RC48MHz
+ VREFINT reference for 48 MHz RC
+ oscillator enable bit
+ 13
+ 1
+ read-write
+
+
+ ENBUF_VREFINT_COMP
+ VREFINT reference for comparator 2
+ enable bit
+ 12
+ 1
+ read-write
+
+
+ ENBUF_SENSOR_ADC
+ Sensor reference for ADC enable
+ bit
+ 9
+ 1
+ read-write
+
+
+ ENBUF_BGAP_ADC
+ VREFINT reference for ADC enable
+ bit
+ 8
+ 1
+ read-write
+
+
+ SEL_VREF_OUT
+ BGAP_ADC connection bit
+ 4
+ 2
+ read-write
+
+
+ EN_BGAP
+ Vref Enable bit
+ 0
+ 1
+ read-write
+
+
+
+
+ COMP1_CTRL
+ COMP1_CTRL
+ Comparator 1 control and status
+ register
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ COMP1EN
+ Comparator 1 enable bit
+ 0
+ 1
+
+
+ COMP1INNSEL
+ Comparator 1 Input Minus connection
+ configuration bit
+ 4
+ 2
+
+
+ COMP1WM
+ Comparator 1 window mode selection
+ bit
+ 8
+ 1
+
+
+ COMP1LPTIMIN1
+ Comparator 1 LPTIM input propagation
+ bit
+ 12
+ 1
+
+
+ COMP1POLARITY
+ Comparator 1 polarity selection
+ bit
+ 15
+ 1
+
+
+ COMP1VALUE
+ Comparator 1 output status
+ bit
+ 30
+ 1
+
+
+ COMP1LOCK
+ COMP1_CSR register lock
+ bit
+ 31
+ 1
+
+
+
+
+ COMP2_CTRL
+ COMP2_CTRL
+ Comparator 2 control and status
+ register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ COMP2EN
+ Comparator 2 enable bit
+ 0
+ 1
+
+
+ COMP2SPEED
+ Comparator 2 power mode selection
+ bit
+ 3
+ 1
+
+
+ COMP2INNSEL
+ Comparator 2 Input Minus connection
+ configuration bit
+ 4
+ 3
+
+
+ COMP2INPSEL
+ Comparator 2 Input Plus connection
+ configuration bit
+ 8
+ 3
+
+
+ COMP2LPTIMIN2
+ Comparator 2 LPTIM input 2 propagation
+ bit
+ 12
+ 1
+
+
+ COMP2LPTIMIN1
+ Comparator 2 LPTIM input 1 propagation
+ bit
+ 13
+ 1
+
+
+ COMP2POLARITY
+ Comparator 2 polarity selection
+ bit
+ 15
+ 1
+
+
+ COMP2VALUE
+ Comparator 2 output status
+ bit
+ 30
+ 1
+
+
+ COMP2LOCK
+ COMP2_CSR register lock
+ bit
+ 31
+ 1
+
+
+
+
+
+
+ SPI1
+ Serial peripheral interface
+ SPI
+ 0x40013000
+
+ 0x0
+ 0x400
+ registers
+
+
+ SPI1
+ SPI1_global_interrupt
+ 25
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ BIDIMODE
+ Bidirectional data mode
+ enable
+ 15
+ 1
+
+
+ BIDIOE
+ Output enable in bidirectional
+ mode
+ 14
+ 1
+
+
+ CRCEN
+ Hardware CRC calculation
+ enable
+ 13
+ 1
+
+
+ CRCNEXT
+ CRC transfer next
+ 12
+ 1
+
+
+ DFF
+ Data frame format
+ 11
+ 1
+
+
+ RXONLY
+ Receive only
+ 10
+ 1
+
+
+ SSM
+ Software slave management
+ 9
+ 1
+
+
+ SSI
+ Internal slave select
+ 8
+ 1
+
+
+ LSBFIRST
+ Frame format
+ 7
+ 1
+
+
+ SPE
+ SPI enable
+ 6
+ 1
+
+
+ BR
+ Baud rate control
+ 3
+ 3
+
+
+ MSTR
+ Master selection
+ 2
+ 1
+
+
+ CPOL
+ Clock polarity
+ 1
+ 1
+
+
+ CPHA
+ Clock phase
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ RXDMAEN
+ Rx buffer DMA enable
+ 0
+ 1
+
+
+ TXDMAEN
+ Tx buffer DMA enable
+ 1
+ 1
+
+
+ SSOE
+ SS output enable
+ 2
+ 1
+
+
+ FRF
+ Frame format
+ 4
+ 1
+
+
+ ERRIE
+ Error interrupt enable
+ 5
+ 1
+
+
+ RXNEIE
+ RX buffer not empty interrupt
+ enable
+ 6
+ 1
+
+
+ TXEIE
+ Tx buffer empty interrupt
+ enable
+ 7
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x8
+ 0x20
+ 0x0002
+
+
+ RXNE
+ Receive buffer not empty
+ 0
+ 1
+ read-only
+
+
+ TXE
+ Transmit buffer empty
+ 1
+ 1
+ read-only
+
+
+ CHSIDE
+ Channel side
+ 2
+ 1
+ read-only
+
+
+ UDR
+ Underrun flag
+ 3
+ 1
+ read-only
+
+
+ CRCERR
+ CRC error flag
+ 4
+ 1
+ read-write
+
+
+ MODF
+ Mode fault
+ 5
+ 1
+ read-only
+
+
+ OVR
+ Overrun flag
+ 6
+ 1
+ read-only
+
+
+ BSY
+ Busy flag
+ 7
+ 1
+ read-only
+
+
+ TIFRFE
+ TI frame format error
+ 8
+ 1
+ read-only
+
+
+
+
+ DR
+ DR
+ data register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ DR
+ Data register
+ 0
+ 16
+
+
+
+
+ CRCPR
+ CRCPR
+ CRC polynomial register
+ 0x10
+ 0x20
+ read-write
+ 0x0007
+
+
+ CRCPOLY
+ CRC polynomial register
+ 0
+ 16
+
+
+
+
+ RXCRCR
+ RXCRCR
+ RX CRC register
+ 0x14
+ 0x20
+ read-only
+ 0x0000
+
+
+ RxCRC
+ Rx CRC register
+ 0
+ 16
+
+
+
+
+ TXCRCR
+ TXCRCR
+ TX CRC register
+ 0x18
+ 0x20
+ read-only
+ 0x0000
+
+
+ TxCRC
+ Tx CRC register
+ 0
+ 16
+
+
+
+
+ I2SCFGR
+ I2SCFGR
+ I2S configuration register
+ 0x1C
+ 0x20
+ read-write
+ 0x0000
+
+
+ I2SMOD
+ I2S mode selection
+ 11
+ 1
+
+
+ I2SE
+ I2S Enable
+ 10
+ 1
+
+
+ I2SCFG
+ I2S configuration mode
+ 8
+ 2
+
+
+ PCMSYNC
+ PCM frame synchronization
+ 7
+ 1
+
+
+ I2SSTD
+ I2S standard selection
+ 4
+ 2
+
+
+ CKPOL
+ Steady state clock
+ polarity
+ 3
+ 1
+
+
+ DATLEN
+ Data length to be
+ transferred
+ 1
+ 2
+
+
+ CHLEN
+ Channel length (number of bits per audio
+ channel)
+ 0
+ 1
+
+
+
+
+ I2SPR
+ I2SPR
+ I2S prescaler register
+ 0x20
+ 0x20
+ read-write
+ 0x00000010
+
+
+ MCKOE
+ Master clock output enable
+ 9
+ 1
+
+
+ ODD
+ Odd factor for the
+ prescaler
+ 8
+ 1
+
+
+ I2SDIV
+ I2S Linear prescaler
+ 0
+ 8
+
+
+
+
+
+
+ SPI2
+ 0x40003800
+
+ SPI2
+ SPI2 global interrupt
+ 26
+
+
+
+ I2C1
+ Inter-integrated circuit
+ I2C
+ 0x40005400
+
+ 0x0
+ 0x400
+ registers
+
+
+ I2C1
+ I2C1 global interrupt
+ 23
+
+
+
+ CR1
+ CR1
+ Control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PE
+ Peripheral enable
+ 0
+ 1
+
+
+ TXIE
+ TX Interrupt enable
+ 1
+ 1
+
+
+ RXIE
+ RX Interrupt enable
+ 2
+ 1
+
+
+ ADDRIE
+ Address match interrupt enable (slave
+ only)
+ 3
+ 1
+
+
+ NACKIE
+ Not acknowledge received interrupt
+ enable
+ 4
+ 1
+
+
+ STOPIE
+ STOP detection Interrupt
+ enable
+ 5
+ 1
+
+
+ TCIE
+ Transfer Complete interrupt
+ enable
+ 6
+ 1
+
+
+ ERRIE
+ Error interrupts enable
+ 7
+ 1
+
+
+ DNF
+ Digital noise filter
+ 8
+ 4
+
+
+ ANFOFF
+ Analog noise filter OFF
+ 12
+ 1
+
+
+ TXDMAEN
+ DMA transmission requests
+ enable
+ 14
+ 1
+
+
+ RXDMAEN
+ DMA reception requests
+ enable
+ 15
+ 1
+
+
+ SBC
+ Slave byte control
+ 16
+ 1
+
+
+ NOSTRETCH
+ Clock stretching disable
+ 17
+ 1
+
+
+ WUPEN
+ Wakeup from STOP enable
+ 18
+ 1
+
+
+ GCEN
+ General call enable
+ 19
+ 1
+
+
+ SMBHEN
+ SMBus Host address enable
+ 20
+ 1
+
+
+ SMBDEN
+ SMBus Device Default address
+ enable
+ 21
+ 1
+
+
+ ALERTEN
+ SMBUS alert enable
+ 22
+ 1
+
+
+ PECEN
+ PEC enable
+ 23
+ 1
+
+
+
+
+ CR2
+ CR2
+ Control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PECBYTE
+ Packet error checking byte
+ 26
+ 1
+
+
+ AUTOEND
+ Automatic end mode (master
+ mode)
+ 25
+ 1
+
+
+ RELOAD
+ NBYTES reload mode
+ 24
+ 1
+
+
+ NBYTES
+ Number of bytes
+ 16
+ 8
+
+
+ NACK
+ NACK generation (slave
+ mode)
+ 15
+ 1
+
+
+ STOP
+ Stop generation (master
+ mode)
+ 14
+ 1
+
+
+ START
+ Start generation
+ 13
+ 1
+
+
+ HEAD10R
+ 10-bit address header only read
+ direction (master receiver mode)
+ 12
+ 1
+
+
+ ADD10
+ 10-bit addressing mode (master
+ mode)
+ 11
+ 1
+
+
+ RD_WRN
+ Transfer direction (master
+ mode)
+ 10
+ 1
+
+
+ SADD
+ Slave address bit (master
+ mode)
+ 0
+ 10
+
+
+
+
+ OAR1
+ OAR1
+ Own address register 1
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OA1
+ Interface address
+ 0
+ 10
+
+
+ OA1MODE
+ Own Address 1 10-bit mode
+ 10
+ 1
+
+
+ OA1EN
+ Own Address 1 enable
+ 15
+ 1
+
+
+
+
+ OAR2
+ OAR2
+ Own address register 2
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OA2
+ Interface address
+ 1
+ 7
+
+
+ OA2MSK
+ Own Address 2 masks
+ 8
+ 3
+
+
+ OA2EN
+ Own Address 2 enable
+ 15
+ 1
+
+
+
+
+ TIMINGR
+ TIMINGR
+ Timing register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SCLL
+ SCL low period (master
+ mode)
+ 0
+ 8
+
+
+ SCLH
+ SCL high period (master
+ mode)
+ 8
+ 8
+
+
+ SDADEL
+ Data hold time
+ 16
+ 4
+
+
+ SCLDEL
+ Data setup time
+ 20
+ 4
+
+
+ PRESC
+ Timing prescaler
+ 28
+ 4
+
+
+
+
+ TIMEOUTR
+ TIMEOUTR
+ Status register 1
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIMEOUTA
+ Bus timeout A
+ 0
+ 12
+
+
+ TIDLE
+ Idle clock timeout
+ detection
+ 12
+ 1
+
+
+ TIMOUTEN
+ Clock timeout enable
+ 15
+ 1
+
+
+ TIMEOUTB
+ Bus timeout B
+ 16
+ 12
+
+
+ TEXTEN
+ Extended clock timeout
+ enable
+ 31
+ 1
+
+
+
+
+ ISR
+ ISR
+ Interrupt and Status register
+ 0x18
+ 0x20
+ 0x00000001
+
+
+ ADDCODE
+ Address match code (Slave
+ mode)
+ 17
+ 7
+ read-only
+
+
+ DIR
+ Transfer direction (Slave
+ mode)
+ 16
+ 1
+ read-only
+
+
+ BUSY
+ Bus busy
+ 15
+ 1
+ read-only
+
+
+ ALERT
+ SMBus alert
+ 13
+ 1
+ read-only
+
+
+ TIMEOUT
+ Timeout or t_low detection
+ flag
+ 12
+ 1
+ read-only
+
+
+ PECERR
+ PEC Error in reception
+ 11
+ 1
+ read-only
+
+
+ OVR
+ Overrun/Underrun (slave
+ mode)
+ 10
+ 1
+ read-only
+
+
+ ARLO
+ Arbitration lost
+ 9
+ 1
+ read-only
+
+
+ BERR
+ Bus error
+ 8
+ 1
+ read-only
+
+
+ TCR
+ Transfer Complete Reload
+ 7
+ 1
+ read-only
+
+
+ TC
+ Transfer Complete (master
+ mode)
+ 6
+ 1
+ read-only
+
+
+ STOPF
+ Stop detection flag
+ 5
+ 1
+ read-only
+
+
+ NACKF
+ Not acknowledge received
+ flag
+ 4
+ 1
+ read-only
+
+
+ ADDR
+ Address matched (slave
+ mode)
+ 3
+ 1
+ read-only
+
+
+ RXNE
+ Receive data register not empty
+ (receivers)
+ 2
+ 1
+ read-only
+
+
+ TXIS
+ Transmit interrupt status
+ (transmitters)
+ 1
+ 1
+ read-write
+
+
+ TXE
+ Transmit data register empty
+ (transmitters)
+ 0
+ 1
+ read-write
+
+
+
+
+ ICR
+ ICR
+ Interrupt clear register
+ 0x1C
+ 0x20
+ write-only
+ 0x00000000
+
+
+ ALERTCF
+ Alert flag clear
+ 13
+ 1
+
+
+ TIMOUTCF
+ Timeout detection flag
+ clear
+ 12
+ 1
+
+
+ PECCF
+ PEC Error flag clear
+ 11
+ 1
+
+
+ OVRCF
+ Overrun/Underrun flag
+ clear
+ 10
+ 1
+
+
+ ARLOCF
+ Arbitration lost flag
+ clear
+ 9
+ 1
+
+
+ BERRCF
+ Bus error flag clear
+ 8
+ 1
+
+
+ STOPCF
+ Stop detection flag clear
+ 5
+ 1
+
+
+ NACKCF
+ Not Acknowledge flag clear
+ 4
+ 1
+
+
+ ADDRCF
+ Address Matched flag clear
+ 3
+ 1
+
+
+
+
+ PECR
+ PECR
+ PEC register
+ 0x20
+ 0x20
+ read-only
+ 0x00000000
+
+
+ PEC
+ Packet error checking
+ register
+ 0
+ 8
+
+
+
+
+ RXDR
+ RXDR
+ Receive data register
+ 0x24
+ 0x20
+ read-only
+ 0x00000000
+
+
+ RXDATA
+ 8-bit receive data
+ 0
+ 8
+
+
+
+
+ TXDR
+ TXDR
+ Transmit data register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TXDATA
+ 8-bit transmit data
+ 0
+ 8
+
+
+
+
+
+
+ I2C2
+ 0x40005800
+
+ I2C2
+ I2C2 global interrupt
+ 24
+
+
+
+ I2C3
+ 0x40007800
+
+ I2C3
+ I2C3 global interrupt
+ 21
+
+
+
+ PWR
+ Power control
+ PWR
+ 0x40007000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CR
+ CR
+ power control register
+ 0x0
+ 0x20
+ read-write
+ 0x00001000
+
+
+ LPDS
+ Low-power deep sleep
+ 0
+ 1
+
+
+ PDDS
+ Power down deepsleep
+ 1
+ 1
+
+
+ CWUF
+ Clear wakeup flag
+ 2
+ 1
+
+
+ CSBF
+ Clear standby flag
+ 3
+ 1
+
+
+ PVDE
+ Power voltage detector
+ enable
+ 4
+ 1
+
+
+ PLS
+ PVD level selection
+ 5
+ 3
+
+
+ DBP
+ Disable backup domain write
+ protection
+ 8
+ 1
+
+
+ ULP
+ Ultra-low-power mode
+ 9
+ 1
+
+
+ FWU
+ Fast wakeup
+ 10
+ 1
+
+
+ VOS
+ Voltage scaling range
+ selection
+ 11
+ 2
+
+
+ DS_EE_KOFF
+ Deep sleep mode with Flash memory kept
+ off
+ 13
+ 1
+
+
+ LPRUN
+ Low power run mode
+ 14
+ 1
+
+
+
+
+ CSR
+ CSR
+ power control/status register
+ 0x4
+ 0x20
+ 0x00000000
+
+
+ BRE
+ Backup regulator enable
+ 9
+ 1
+ read-write
+
+
+ EWUP
+ Enable WKUP pin
+ 8
+ 1
+ read-write
+
+
+ BRR
+ Backup regulator ready
+ 3
+ 1
+ read-only
+
+
+ PVDO
+ PVD output
+ 2
+ 1
+ read-only
+
+
+ SBF
+ Standby flag
+ 1
+ 1
+ read-only
+
+
+ WUF
+ Wakeup flag
+ 0
+ 1
+ read-only
+
+
+ VOSF
+ Voltage Scaling select
+ flag
+ 4
+ 1
+ read-only
+
+
+ REGLPF
+ Regulator LP flag
+ 5
+ 1
+ read-only
+
+
+
+
+
+
+ Flash
+ Flash
+ Flash
+ 0x40022000
+
+ 0x0
+ 0x400
+ registers
+
+
+ FLASH
+ Flash global interrupt
+ 3
+
+
+
+ ACR
+ ACR
+ Access control register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LATENCY
+ Latency
+ 0
+ 1
+
+
+ PRFTEN
+ Prefetch enable
+ 1
+ 1
+
+
+ SLEEP_PD
+ Flash mode during Sleep
+ 3
+ 1
+
+
+ RUN_PD
+ Flash mode during Run
+ 4
+ 1
+
+
+ DESAB_BUF
+ Disable Buffer
+ 5
+ 1
+
+
+ PRE_READ
+ Pre-read data address
+ 6
+ 1
+
+
+
+
+ PECR
+ PECR
+ Program/erase control register
+ 0x4
+ 0x20
+ read-write
+ 0x00000007
+
+
+ PELOCK
+ FLASH_PECR and data EEPROM
+ lock
+ 0
+ 1
+
+
+ PRGLOCK
+ Program memory lock
+ 1
+ 1
+
+
+ OPTLOCK
+ Option bytes block lock
+ 2
+ 1
+
+
+ PROG
+ Program memory selection
+ 3
+ 1
+
+
+ DATA
+ Data EEPROM selection
+ 4
+ 1
+
+
+ FTDW
+ Fixed time data write for Byte, Half
+ Word and Word programming
+ 8
+ 1
+
+
+ ERASE
+ Page or Double Word erase
+ mode
+ 9
+ 1
+
+
+ FPRG
+ Half Page/Double Word programming
+ mode
+ 10
+ 1
+
+
+ PARALLELBANK
+ Parallel bank mode
+ 15
+ 1
+
+
+ EOPIE
+ End of programming interrupt
+ enable
+ 16
+ 1
+
+
+ ERRIE
+ Error interrupt enable
+ 17
+ 1
+
+
+ OBL_LAUNCH
+ Launch the option byte
+ loading
+ 18
+ 1
+
+
+
+
+ PDKEYR
+ PDKEYR
+ Power down key register
+ 0x8
+ 0x20
+ write-only
+ 0x00000000
+
+
+ PDKEYR
+ RUN_PD in FLASH_ACR key
+ 0
+ 32
+
+
+
+
+ PEKEYR
+ PEKEYR
+ Program/erase key register
+ 0xC
+ 0x20
+ write-only
+ 0x00000000
+
+
+ PEKEYR
+ FLASH_PEC and data EEPROM
+ key
+ 0
+ 32
+
+
+
+
+ PRGKEYR
+ PRGKEYR
+ Program memory key register
+ 0x10
+ 0x20
+ write-only
+ 0x00000000
+
+
+ PRGKEYR
+ Program memory key
+ 0
+ 32
+
+
+
+
+ OPTKEYR
+ OPTKEYR
+ Option byte key register
+ 0x14
+ 0x20
+ write-only
+ 0x00000000
+
+
+ OPTKEYR
+ Option byte key
+ 0
+ 32
+
+
+
+
+ SR
+ SR
+ Status register
+ 0x18
+ 0x20
+ 0x00000004
+
+
+ BSY
+ Write/erase operations in
+ progress
+ 0
+ 1
+ read-only
+
+
+ EOP
+ End of operation
+ 1
+ 1
+ read-only
+
+
+ ENDHV
+ End of high voltage
+ 2
+ 1
+ read-only
+
+
+ READY
+ Flash memory module ready after low
+ power mode
+ 3
+ 1
+ read-only
+
+
+ WRPERR
+ Write protected error
+ 8
+ 1
+ read-write
+
+
+ PGAERR
+ Programming alignment
+ error
+ 9
+ 1
+ read-write
+
+
+ SIZERR
+ Size error
+ 10
+ 1
+ read-write
+
+
+ OPTVERR
+ Option validity error
+ 11
+ 1
+ read-write
+
+
+ RDERR
+ RDERR
+ 14
+ 1
+ read-write
+
+
+ NOTZEROERR
+ NOTZEROERR
+ 16
+ 1
+ read-write
+
+
+ FWWERR
+ FWWERR
+ 17
+ 1
+ read-write
+
+
+
+
+ OBR
+ OBR
+ Option byte register
+ 0x1C
+ 0x20
+ read-only
+ 0x00F80000
+
+
+ RDPRT
+ Read protection
+ 0
+ 8
+
+
+ BOR_LEV
+ BOR_LEV
+ 16
+ 4
+
+
+ SPRMOD
+ Selection of protection mode of WPR
+ bits
+ 8
+ 1
+
+
+
+
+ WRPR
+ WRPR
+ Write protection register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ WRP
+ Write protection
+ 0
+ 16
+
+
+
+
+
+
+ EXTI
+ External interrupt/event
+ controller
+ EXTI
+ 0x40010400
+
+ 0x0
+ 0x400
+ registers
+
+
+ PVD
+ PVD through EXTI line detection
+ 1
+
+
+ EXTI0_1
+ EXTI Line[1:0] interrupts
+ 5
+
+
+ EXTI2_3
+ EXTI Line[3:2] interrupts
+ 6
+
+
+ EXTI4_15
+ EXTI Line15 and EXTI4 interrupts
+ 7
+
+
+
+ IMR
+ IMR
+ Interrupt mask register
+ (EXTI_IMR)
+ 0x0
+ 0x20
+ read-write
+ 0xFF840000
+
+
+ IM0
+ Interrupt Mask on line 0
+ 0
+ 1
+
+
+ IM1
+ Interrupt Mask on line 1
+ 1
+ 1
+
+
+ IM2
+ Interrupt Mask on line 2
+ 2
+ 1
+
+
+ IM3
+ Interrupt Mask on line 3
+ 3
+ 1
+
+
+ IM4
+ Interrupt Mask on line 4
+ 4
+ 1
+
+
+ IM5
+ Interrupt Mask on line 5
+ 5
+ 1
+
+
+ IM6
+ Interrupt Mask on line 6
+ 6
+ 1
+
+
+ IM7
+ Interrupt Mask on line 7
+ 7
+ 1
+
+
+ IM8
+ Interrupt Mask on line 8
+ 8
+ 1
+
+
+ IM9
+ Interrupt Mask on line 9
+ 9
+ 1
+
+
+ IM10
+ Interrupt Mask on line 10
+ 10
+ 1
+
+
+ IM11
+ Interrupt Mask on line 11
+ 11
+ 1
+
+
+ IM12
+ Interrupt Mask on line 12
+ 12
+ 1
+
+
+ IM13
+ Interrupt Mask on line 13
+ 13
+ 1
+
+
+ IM14
+ Interrupt Mask on line 14
+ 14
+ 1
+
+
+ IM15
+ Interrupt Mask on line 15
+ 15
+ 1
+
+
+ IM16
+ Interrupt Mask on line 16
+ 16
+ 1
+
+
+ IM17
+ Interrupt Mask on line 17
+ 17
+ 1
+
+
+ IM18
+ Interrupt Mask on line 18
+ 18
+ 1
+
+
+ IM19
+ Interrupt Mask on line 19
+ 19
+ 1
+
+
+ IM20
+ Interrupt Mask on line 20
+ 20
+ 1
+
+
+ IM21
+ Interrupt Mask on line 21
+ 21
+ 1
+
+
+ IM22
+ Interrupt Mask on line 22
+ 22
+ 1
+
+
+ IM23
+ Interrupt Mask on line 23
+ 23
+ 1
+
+
+ IM24
+ Interrupt Mask on line 24
+ 24
+ 1
+
+
+ IM25
+ Interrupt Mask on line 25
+ 25
+ 1
+
+
+ IM26
+ Interrupt Mask on line 27
+ 26
+ 1
+
+
+ IM28
+ Interrupt Mask on line 27
+ 28
+ 1
+
+
+ IM29
+ Interrupt Mask on line 27
+ 29
+ 1
+
+
+
+
+ EMR
+ EMR
+ Event mask register (EXTI_EMR)
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EM0
+ Event Mask on line 0
+ 0
+ 1
+
+
+ EM1
+ Event Mask on line 1
+ 1
+ 1
+
+
+ EM2
+ Event Mask on line 2
+ 2
+ 1
+
+
+ EM3
+ Event Mask on line 3
+ 3
+ 1
+
+
+ EM4
+ Event Mask on line 4
+ 4
+ 1
+
+
+ EM5
+ Event Mask on line 5
+ 5
+ 1
+
+
+ EM6
+ Event Mask on line 6
+ 6
+ 1
+
+
+ EM7
+ Event Mask on line 7
+ 7
+ 1
+
+
+ EM8
+ Event Mask on line 8
+ 8
+ 1
+
+
+ EM9
+ Event Mask on line 9
+ 9
+ 1
+
+
+ EM10
+ Event Mask on line 10
+ 10
+ 1
+
+
+ EM11
+ Event Mask on line 11
+ 11
+ 1
+
+
+ EM12
+ Event Mask on line 12
+ 12
+ 1
+
+
+ EM13
+ Event Mask on line 13
+ 13
+ 1
+
+
+ EM14
+ Event Mask on line 14
+ 14
+ 1
+
+
+ EM15
+ Event Mask on line 15
+ 15
+ 1
+
+
+ EM16
+ Event Mask on line 16
+ 16
+ 1
+
+
+ EM17
+ Event Mask on line 17
+ 17
+ 1
+
+
+ EM18
+ Event Mask on line 18
+ 18
+ 1
+
+
+ EM19
+ Event Mask on line 19
+ 19
+ 1
+
+
+ EM20
+ Event Mask on line 20
+ 20
+ 1
+
+
+ EM21
+ Event Mask on line 21
+ 21
+ 1
+
+
+ EM22
+ Event Mask on line 22
+ 22
+ 1
+
+
+ EM23
+ Event Mask on line 23
+ 23
+ 1
+
+
+ EM24
+ Event Mask on line 24
+ 24
+ 1
+
+
+ EM25
+ Event Mask on line 25
+ 25
+ 1
+
+
+ EM26
+ Event Mask on line 26
+ 26
+ 1
+
+
+ EM28
+ Event Mask on line 28
+ 28
+ 1
+
+
+ EM29
+ Event Mask on line 29
+ 29
+ 1
+
+
+
+
+ RTSR
+ RTSR
+ Rising Trigger selection register
+ (EXTI_RTSR)
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ RT0
+ Rising trigger event configuration of
+ line 0
+ 0
+ 1
+
+
+ RT1
+ Rising trigger event configuration of
+ line 1
+ 1
+ 1
+
+
+ RT2
+ Rising trigger event configuration of
+ line 2
+ 2
+ 1
+
+
+ RT3
+ Rising trigger event configuration of
+ line 3
+ 3
+ 1
+
+
+ RT4
+ Rising trigger event configuration of
+ line 4
+ 4
+ 1
+
+
+ RT5
+ Rising trigger event configuration of
+ line 5
+ 5
+ 1
+
+
+ RT6
+ Rising trigger event configuration of
+ line 6
+ 6
+ 1
+
+
+ RT7
+ Rising trigger event configuration of
+ line 7
+ 7
+ 1
+
+
+ RT8
+ Rising trigger event configuration of
+ line 8
+ 8
+ 1
+
+
+ RT9
+ Rising trigger event configuration of
+ line 9
+ 9
+ 1
+
+
+ RT10
+ Rising trigger event configuration of
+ line 10
+ 10
+ 1
+
+
+ RT11
+ Rising trigger event configuration of
+ line 11
+ 11
+ 1
+
+
+ RT12
+ Rising trigger event configuration of
+ line 12
+ 12
+ 1
+
+
+ RT13
+ Rising trigger event configuration of
+ line 13
+ 13
+ 1
+
+
+ RT14
+ Rising trigger event configuration of
+ line 14
+ 14
+ 1
+
+
+ RT15
+ Rising trigger event configuration of
+ line 15
+ 15
+ 1
+
+
+ RT16
+ Rising trigger event configuration of
+ line 16
+ 16
+ 1
+
+
+ RT17
+ Rising trigger event configuration of
+ line 17
+ 17
+ 1
+
+
+ RT19
+ Rising trigger event configuration of
+ line 19
+ 19
+ 1
+
+
+ RT20
+ Rising trigger event configuration of
+ line 20
+ 20
+ 1
+
+
+ RT21
+ Rising trigger event configuration of
+ line 21
+ 21
+ 1
+
+
+ RT22
+ Rising trigger event configuration of
+ line 22
+ 22
+ 1
+
+
+
+
+ FTSR
+ FTSR
+ Falling Trigger selection register
+ (EXTI_FTSR)
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FT0
+ Falling trigger event configuration of
+ line 0
+ 0
+ 1
+
+
+ FT1
+ Falling trigger event configuration of
+ line 1
+ 1
+ 1
+
+
+ FT2
+ Falling trigger event configuration of
+ line 2
+ 2
+ 1
+
+
+ FT3
+ Falling trigger event configuration of
+ line 3
+ 3
+ 1
+
+
+ FT4
+ Falling trigger event configuration of
+ line 4
+ 4
+ 1
+
+
+ FT5
+ Falling trigger event configuration of
+ line 5
+ 5
+ 1
+
+
+ FT6
+ Falling trigger event configuration of
+ line 6
+ 6
+ 1
+
+
+ FT7
+ Falling trigger event configuration of
+ line 7
+ 7
+ 1
+
+
+ FT8
+ Falling trigger event configuration of
+ line 8
+ 8
+ 1
+
+
+ FT9
+ Falling trigger event configuration of
+ line 9
+ 9
+ 1
+
+
+ FT10
+ Falling trigger event configuration of
+ line 10
+ 10
+ 1
+
+
+ FT11
+ Falling trigger event configuration of
+ line 11
+ 11
+ 1
+
+
+ FT12
+ Falling trigger event configuration of
+ line 12
+ 12
+ 1
+
+
+ FT13
+ Falling trigger event configuration of
+ line 13
+ 13
+ 1
+
+
+ FT14
+ Falling trigger event configuration of
+ line 14
+ 14
+ 1
+
+
+ FT15
+ Falling trigger event configuration of
+ line 15
+ 15
+ 1
+
+
+ FT16
+ Falling trigger event configuration of
+ line 16
+ 16
+ 1
+
+
+ FT17
+ Falling trigger event configuration of
+ line 17
+ 17
+ 1
+
+
+ FT19
+ Falling trigger event configuration of
+ line 19
+ 19
+ 1
+
+
+ FT20
+ Falling trigger event configuration of
+ line 20
+ 20
+ 1
+
+
+ FT21
+ Falling trigger event configuration of
+ line 21
+ 21
+ 1
+
+
+ FT22
+ Falling trigger event configuration of
+ line 22
+ 22
+ 1
+
+
+
+
+ SWIER
+ SWIER
+ Software interrupt event register
+ (EXTI_SWIER)
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SWI0
+ Software Interrupt on line
+ 0
+ 0
+ 1
+
+
+ SWI1
+ Software Interrupt on line
+ 1
+ 1
+ 1
+
+
+ SWI2
+ Software Interrupt on line
+ 2
+ 2
+ 1
+
+
+ SWI3
+ Software Interrupt on line
+ 3
+ 3
+ 1
+
+
+ SWI4
+ Software Interrupt on line
+ 4
+ 4
+ 1
+
+
+ SWI5
+ Software Interrupt on line
+ 5
+ 5
+ 1
+
+
+ SWI6
+ Software Interrupt on line
+ 6
+ 6
+ 1
+
+
+ SWI7
+ Software Interrupt on line
+ 7
+ 7
+ 1
+
+
+ SWI8
+ Software Interrupt on line
+ 8
+ 8
+ 1
+
+
+ SWI9
+ Software Interrupt on line
+ 9
+ 9
+ 1
+
+
+ SWI10
+ Software Interrupt on line
+ 10
+ 10
+ 1
+
+
+ SWI11
+ Software Interrupt on line
+ 11
+ 11
+ 1
+
+
+ SWI12
+ Software Interrupt on line
+ 12
+ 12
+ 1
+
+
+ SWI13
+ Software Interrupt on line
+ 13
+ 13
+ 1
+
+
+ SWI14
+ Software Interrupt on line
+ 14
+ 14
+ 1
+
+
+ SWI15
+ Software Interrupt on line
+ 15
+ 15
+ 1
+
+
+ SWI16
+ Software Interrupt on line
+ 16
+ 16
+ 1
+
+
+ SWI17
+ Software Interrupt on line
+ 17
+ 17
+ 1
+
+
+ SWI19
+ Software Interrupt on line
+ 19
+ 19
+ 1
+
+
+ SWI20
+ Software Interrupt on line
+ 20
+ 20
+ 1
+
+
+ SWI21
+ Software Interrupt on line
+ 21
+ 21
+ 1
+
+
+ SWI22
+ Software Interrupt on line
+ 22
+ 22
+ 1
+
+
+
+
+ PR
+ PR
+ Pending register (EXTI_PR)
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PIF0
+ Pending bit 0
+ 0
+ 1
+
+
+ PIF1
+ Pending bit 1
+ 1
+ 1
+
+
+ PIF2
+ Pending bit 2
+ 2
+ 1
+
+
+ PIF3
+ Pending bit 3
+ 3
+ 1
+
+
+ PIF4
+ Pending bit 4
+ 4
+ 1
+
+
+ PIF5
+ Pending bit 5
+ 5
+ 1
+
+
+ PIF6
+ Pending bit 6
+ 6
+ 1
+
+
+ PIF7
+ Pending bit 7
+ 7
+ 1
+
+
+ PIF8
+ Pending bit 8
+ 8
+ 1
+
+
+ PIF9
+ Pending bit 9
+ 9
+ 1
+
+
+ PIF10
+ Pending bit 10
+ 10
+ 1
+
+
+ PIF11
+ Pending bit 11
+ 11
+ 1
+
+
+ PIF12
+ Pending bit 12
+ 12
+ 1
+
+
+ PIF13
+ Pending bit 13
+ 13
+ 1
+
+
+ PIF14
+ Pending bit 14
+ 14
+ 1
+
+
+ PIF15
+ Pending bit 15
+ 15
+ 1
+
+
+ PIF16
+ Pending bit 16
+ 16
+ 1
+
+
+ PIF17
+ Pending bit 17
+ 17
+ 1
+
+
+ PIF19
+ Pending bit 19
+ 19
+ 1
+
+
+ PIF20
+ Pending bit 20
+ 20
+ 1
+
+
+ PIF21
+ Pending bit 21
+ 21
+ 1
+
+
+ PIF22
+ Pending bit 22
+ 22
+ 1
+
+
+
+
+
+
+ ADC
+ Analog-to-digital converter
+ ADC
+ 0x40012400
+
+ 0x0
+ 0x400
+ registers
+
+
+ ADC_COMP
+ ADC and comparator 1 and 2
+ 12
+
+
+
+ ISR
+ ISR
+ interrupt and status register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ADRDY
+ ADC ready
+ 0
+ 1
+
+
+ EOSMP
+ End of sampling flag
+ 1
+ 1
+
+
+ EOC
+ End of conversion flag
+ 2
+ 1
+
+
+ EOS
+ End of sequence flag
+ 3
+ 1
+
+
+ OVR
+ ADC overrun
+ 4
+ 1
+
+
+ AWD
+ Analog watchdog flag
+ 7
+ 1
+
+
+ EOCAL
+ End Of Calibration flag
+ 11
+ 1
+
+
+
+
+ IER
+ IER
+ interrupt enable register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ADRDYIE
+ ADC ready interrupt enable
+ 0
+ 1
+
+
+ EOSMPIE
+ End of sampling flag interrupt
+ enable
+ 1
+ 1
+
+
+ EOCIE
+ End of conversion interrupt
+ enable
+ 2
+ 1
+
+
+ EOSIE
+ End of conversion sequence interrupt
+ enable
+ 3
+ 1
+
+
+ OVRIE
+ Overrun interrupt enable
+ 4
+ 1
+
+
+ AWDIE
+ Analog watchdog interrupt
+ enable
+ 7
+ 1
+
+
+ EOCALIE
+ End of calibration interrupt
+ enable
+ 11
+ 1
+
+
+
+
+ CR
+ CR
+ control register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ADEN
+ ADC enable command
+ 0
+ 1
+
+
+ ADDIS
+ ADC disable command
+ 1
+ 1
+
+
+ ADSTART
+ ADC start conversion
+ command
+ 2
+ 1
+
+
+ ADSTP
+ ADC stop conversion
+ command
+ 4
+ 1
+
+
+ ADVREGEN
+ ADC Voltage Regulator
+ Enable
+ 28
+ 1
+
+
+ ADCAL
+ ADC calibration
+ 31
+ 1
+
+
+
+
+ CFGR1
+ CFGR1
+ configuration register 1
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AWDCH
+ Analog watchdog channel
+ selection
+ 26
+ 5
+
+
+ AWDEN
+ Analog watchdog enable
+ 23
+ 1
+
+
+ AWDSGL
+ Enable the watchdog on a single channel
+ or on all channels
+ 22
+ 1
+
+
+ DISCEN
+ Discontinuous mode
+ 16
+ 1
+
+
+ AUTOFF
+ Auto-off mode
+ 15
+ 1
+
+
+ AUTDLY
+ Auto-delayed conversion
+ mode
+ 14
+ 1
+
+
+ CONT
+ Single / continuous conversion
+ mode
+ 13
+ 1
+
+
+ OVRMOD
+ Overrun management mode
+ 12
+ 1
+
+
+ EXTEN
+ External trigger enable and polarity
+ selection
+ 10
+ 2
+
+
+ EXTSEL
+ External trigger selection
+ 6
+ 3
+
+
+ ALIGN
+ Data alignment
+ 5
+ 1
+
+
+ RES
+ Data resolution
+ 3
+ 2
+
+
+ SCANDIR
+ Scan sequence direction
+ 2
+ 1
+
+
+ DMACFG
+ Direct memery access
+ configuration
+ 1
+ 1
+
+
+ DMAEN
+ Direct memory access
+ enable
+ 0
+ 1
+
+
+
+
+ CFGR2
+ CFGR2
+ configuration register 2
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OVSE
+ Oversampler Enable
+ 0
+ 1
+
+
+ OVSR
+ Oversampling ratio
+ 2
+ 3
+
+
+ OVSS
+ Oversampling shift
+ 5
+ 4
+
+
+ TOVS
+ Triggered Oversampling
+ 9
+ 1
+
+
+ CKMODE
+ ADC clock mode
+ 30
+ 2
+
+
+
+
+ SMPR
+ SMPR
+ sampling time register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SMPR
+ Sampling time selection
+ 0
+ 3
+
+
+
+
+ TR
+ TR
+ watchdog threshold register
+ 0x20
+ 0x20
+ read-write
+ 0x0FFF0000
+
+
+ HT
+ Analog watchdog higher
+ threshold
+ 16
+ 12
+
+
+ LT
+ Analog watchdog lower
+ threshold
+ 0
+ 12
+
+
+
+
+ CHSELR
+ CHSELR
+ channel selection register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CHSEL18
+ Channel-x selection
+ 18
+ 1
+
+
+ CHSEL17
+ Channel-x selection
+ 17
+ 1
+
+
+ CHSEL16
+ Channel-x selection
+ 16
+ 1
+
+
+ CHSEL15
+ Channel-x selection
+ 15
+ 1
+
+
+ CHSEL14
+ Channel-x selection
+ 14
+ 1
+
+
+ CHSEL13
+ Channel-x selection
+ 13
+ 1
+
+
+ CHSEL12
+ Channel-x selection
+ 12
+ 1
+
+
+ CHSEL11
+ Channel-x selection
+ 11
+ 1
+
+
+ CHSEL10
+ Channel-x selection
+ 10
+ 1
+
+
+ CHSEL9
+ Channel-x selection
+ 9
+ 1
+
+
+ CHSEL8
+ Channel-x selection
+ 8
+ 1
+
+
+ CHSEL7
+ Channel-x selection
+ 7
+ 1
+
+
+ CHSEL6
+ Channel-x selection
+ 6
+ 1
+
+
+ CHSEL5
+ Channel-x selection
+ 5
+ 1
+
+
+ CHSEL4
+ Channel-x selection
+ 4
+ 1
+
+
+ CHSEL3
+ Channel-x selection
+ 3
+ 1
+
+
+ CHSEL2
+ Channel-x selection
+ 2
+ 1
+
+
+ CHSEL1
+ Channel-x selection
+ 1
+ 1
+
+
+ CHSEL0
+ Channel-x selection
+ 0
+ 1
+
+
+
+
+ DR
+ DR
+ data register
+ 0x40
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DATA
+ Converted data
+ 0
+ 16
+
+
+
+
+ CALFACT
+ CALFACT
+ ADC Calibration factor
+ 0xB4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CALFACT
+ Calibration factor
+ 0
+ 7
+
+
+
+
+ CCR
+ CCR
+ ADC common configuration
+ register
+ 0x308
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRESC
+ ADC prescaler
+ 18
+ 4
+
+
+ VREFEN
+ VREFINT enable
+ 22
+ 1
+
+
+ TSEN
+ Temperature sensor enable
+ 23
+ 1
+
+
+ VLCDEN
+ VLCD enable
+ 24
+ 1
+
+
+ LFMEN
+ Low Frequency Mode enable
+ 25
+ 1
+
+
+
+
+
+
+ DBG
+ Debug support
+ DBGMCU
+ 0x40015800
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ IDCODE
+ IDCODE
+ MCU Device ID Code Register
+ 0x0
+ 0x20
+ read-only
+ 0x0
+
+
+ DEV_ID
+ Device Identifier
+ 0
+ 12
+
+
+ REV_ID
+ Revision Identifier
+ 16
+ 16
+
+
+
+
+ CR
+ CR
+ Debug MCU Configuration
+ Register
+ 0x4
+ 0x20
+ read-write
+ 0x0
+
+
+ DBG_STOP
+ Debug Stop Mode
+ 1
+ 1
+
+
+ DBG_STANDBY
+ Debug Standby Mode
+ 2
+ 1
+
+
+ DBG_SLEEP
+ Debug Sleep Mode
+ 0
+ 1
+
+
+
+
+ APB1_FZ
+ APB1_FZ
+ APB Low Freeze Register
+ 0x8
+ 0x20
+ read-write
+ 0x0
+
+
+ DBG_TIMER2_STOP
+ Debug Timer 2 stopped when Core is
+ halted
+ 0
+ 1
+
+
+ DBG_TIMER6_STOP
+ Debug Timer 6 stopped when Core is
+ halted
+ 4
+ 1
+
+
+ DBG_RTC_STOP
+ Debug RTC stopped when Core is
+ halted
+ 10
+ 1
+
+
+ DBG_WWDG_STOP
+ Debug Window Wachdog stopped when Core
+ is halted
+ 11
+ 1
+
+
+ DBG_IWDG_STOP
+ Debug Independent Wachdog stopped when
+ Core is halted
+ 12
+ 1
+
+
+ DBG_I2C1_STOP
+ I2C1 SMBUS timeout mode stopped when
+ core is halted
+ 21
+ 1
+
+
+ DBG_I2C2_STOP
+ I2C2 SMBUS timeout mode stopped when
+ core is halted
+ 22
+ 1
+
+
+ DBG_LPTIMER_STOP
+ LPTIM1 counter stopped when core is
+ halted
+ 31
+ 1
+
+
+
+
+ APB2_FZ
+ APB2_FZ
+ APB High Freeze Register
+ 0xC
+ 0x20
+ read-write
+ 0x0
+
+
+ DBG_TIMER21_STOP
+ Debug Timer 21 stopped when Core is
+ halted
+ 2
+ 1
+
+
+ DBG_TIMER22_STO
+ Debug Timer 22 stopped when Core is
+ halted
+ 6
+ 1
+
+
+
+
+
+
+ TIM2
+ General-purpose-timers
+ TIM
+ 0x40000000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM2
+ TIM2 global interrupt
+ 15
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CKD
+ Clock division
+ 8
+ 2
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ CMS
+ Center-aligned mode
+ selection
+ 5
+ 2
+
+
+ DIR
+ Direction
+ 4
+ 1
+
+
+ OPM
+ One-pulse mode
+ 3
+ 1
+
+
+ URS
+ Update request source
+ 2
+ 1
+
+
+ UDIS
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ TI1S
+ TI1 selection
+ 7
+ 1
+
+
+ MMS
+ Master mode selection
+ 4
+ 3
+
+
+ CCDS
+ Capture/compare DMA
+ selection
+ 3
+ 1
+
+
+
+
+ SMCR
+ SMCR
+ slave mode control register
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ ETP
+ External trigger polarity
+ 15
+ 1
+
+
+ ECE
+ External clock enable
+ 14
+ 1
+
+
+ ETPS
+ External trigger prescaler
+ 12
+ 2
+
+
+ ETF
+ External trigger filter
+ 8
+ 4
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ TS
+ Trigger selection
+ 4
+ 3
+
+
+ SMS
+ Slave mode selection
+ 0
+ 3
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ TDE
+ Trigger DMA request enable
+ 14
+ 1
+
+
+ CC4DE
+ Capture/Compare 4 DMA request
+ enable
+ 12
+ 1
+
+
+ CC3DE
+ Capture/Compare 3 DMA request
+ enable
+ 11
+ 1
+
+
+ CC2DE
+ Capture/Compare 2 DMA request
+ enable
+ 10
+ 1
+
+
+ CC1DE
+ Capture/Compare 1 DMA request
+ enable
+ 9
+ 1
+
+
+ UDE
+ Update DMA request enable
+ 8
+ 1
+
+
+ TIE
+ Trigger interrupt enable
+ 6
+ 1
+
+
+ CC4IE
+ Capture/Compare 4 interrupt
+ enable
+ 4
+ 1
+
+
+ CC3IE
+ Capture/Compare 3 interrupt
+ enable
+ 3
+ 1
+
+
+ CC2IE
+ Capture/Compare 2 interrupt
+ enable
+ 2
+ 1
+
+
+ CC1IE
+ Capture/Compare 1 interrupt
+ enable
+ 1
+ 1
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC4OF
+ Capture/Compare 4 overcapture
+ flag
+ 12
+ 1
+
+
+ CC3OF
+ Capture/Compare 3 overcapture
+ flag
+ 11
+ 1
+
+
+ CC2OF
+ Capture/compare 2 overcapture
+ flag
+ 10
+ 1
+
+
+ CC1OF
+ Capture/Compare 1 overcapture
+ flag
+ 9
+ 1
+
+
+ TIF
+ Trigger interrupt flag
+ 6
+ 1
+
+
+ CC4IF
+ Capture/Compare 4 interrupt
+ flag
+ 4
+ 1
+
+
+ CC3IF
+ Capture/Compare 3 interrupt
+ flag
+ 3
+ 1
+
+
+ CC2IF
+ Capture/Compare 2 interrupt
+ flag
+ 2
+ 1
+
+
+ CC1IF
+ Capture/compare 1 interrupt
+ flag
+ 1
+ 1
+
+
+ UIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ TG
+ Trigger generation
+ 6
+ 1
+
+
+ CC4G
+ Capture/compare 4
+ generation
+ 4
+ 1
+
+
+ CC3G
+ Capture/compare 3
+ generation
+ 3
+ 1
+
+
+ CC2G
+ Capture/compare 2
+ generation
+ 2
+ 1
+
+
+ CC1G
+ Capture/compare 1
+ generation
+ 1
+ 1
+
+
+ UG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CCMR1_Output
+ CCMR1_Output
+ capture/compare mode register 1 (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OC2CE
+ Output compare 2 clear
+ enable
+ 15
+ 1
+
+
+ OC2M
+ Output compare 2 mode
+ 12
+ 3
+
+
+ OC2PE
+ Output compare 2 preload
+ enable
+ 11
+ 1
+
+
+ OC2FE
+ Output compare 2 fast
+ enable
+ 10
+ 1
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ OC1CE
+ Output compare 1 clear
+ enable
+ 7
+ 1
+
+
+ OC1M
+ Output compare 1 mode
+ 4
+ 3
+
+
+ OC1PE
+ Output compare 1 preload
+ enable
+ 3
+ 1
+
+
+ OC1FE
+ Output compare 1 fast
+ enable
+ 2
+ 1
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR1_Input
+ CCMR1_Input
+ capture/compare mode register 1 (input
+ mode)
+ CCMR1_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC2F
+ Input capture 2 filter
+ 12
+ 4
+
+
+ IC2PSC
+ Input capture 2 prescaler
+ 10
+ 2
+
+
+ CC2S
+ Capture/compare 2
+ selection
+ 8
+ 2
+
+
+ IC1F
+ Input capture 1 filter
+ 4
+ 4
+
+
+ IC1PSC
+ Input capture 1 prescaler
+ 2
+ 2
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR2_Output
+ CCMR2_Output
+ capture/compare mode register 2 (output
+ mode)
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OC4CE
+ Output compare 4 clear
+ enable
+ 15
+ 1
+
+
+ OC4M
+ Output compare 4 mode
+ 12
+ 3
+
+
+ OC4PE
+ Output compare 4 preload
+ enable
+ 11
+ 1
+
+
+ OC4FE
+ Output compare 4 fast
+ enable
+ 10
+ 1
+
+
+ CC4S
+ Capture/Compare 4
+ selection
+ 8
+ 2
+
+
+ OC3CE
+ Output compare 3 clear
+ enable
+ 7
+ 1
+
+
+ OC3M
+ Output compare 3 mode
+ 4
+ 3
+
+
+ OC3PE
+ Output compare 3 preload
+ enable
+ 3
+ 1
+
+
+ OC3FE
+ Output compare 3 fast
+ enable
+ 2
+ 1
+
+
+ CC3S
+ Capture/Compare 3
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR2_Input
+ CCMR2_Input
+ capture/compare mode register 2 (input
+ mode)
+ CCMR2_Output
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC4F
+ Input capture 4 filter
+ 12
+ 4
+
+
+ IC4PSC
+ Input capture 4 prescaler
+ 10
+ 2
+
+
+ CC4S
+ Capture/Compare 4
+ selection
+ 8
+ 2
+
+
+ IC3F
+ Input capture 3 filter
+ 4
+ 4
+
+
+ IC3PSC
+ Input capture 3 prescaler
+ 2
+ 2
+
+
+ CC3S
+ Capture/Compare 3
+ selection
+ 0
+ 2
+
+
+
+
+ CCER
+ CCER
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC4NP
+ Capture/Compare 4 output
+ Polarity
+ 15
+ 1
+
+
+ CC4P
+ Capture/Compare 3 output
+ Polarity
+ 13
+ 1
+
+
+ CC4E
+ Capture/Compare 4 output
+ enable
+ 12
+ 1
+
+
+ CC3NP
+ Capture/Compare 3 output
+ Polarity
+ 11
+ 1
+
+
+ CC3P
+ Capture/Compare 3 output
+ Polarity
+ 9
+ 1
+
+
+ CC3E
+ Capture/Compare 3 output
+ enable
+ 8
+ 1
+
+
+ CC2NP
+ Capture/Compare 2 output
+ Polarity
+ 7
+ 1
+
+
+ CC2P
+ Capture/Compare 2 output
+ Polarity
+ 5
+ 1
+
+
+ CC2E
+ Capture/Compare 2 output
+ enable
+ 4
+ 1
+
+
+ CC1NP
+ Capture/Compare 1 output
+ Polarity
+ 3
+ 1
+
+
+ CC1P
+ Capture/Compare 1 output
+ Polarity
+ 1
+ 1
+
+
+ CC1E
+ Capture/Compare 1 output
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT_H
+ High counter value (TIM2
+ only)
+ 16
+ 16
+
+
+ CNT_L
+ Low counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ARR_H
+ High Auto-reload value (TIM2
+ only)
+ 16
+ 16
+
+
+ ARR_L
+ Low Auto-reload value
+ 0
+ 16
+
+
+
+
+ CCR1
+ CCR1
+ capture/compare register 1
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR1_H
+ High Capture/Compare 1 value (TIM2
+ only)
+ 16
+ 16
+
+
+ CCR1_L
+ Low Capture/Compare 1
+ value
+ 0
+ 16
+
+
+
+
+ CCR2
+ CCR2
+ capture/compare register 2
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR2_H
+ High Capture/Compare 2 value (TIM2
+ only)
+ 16
+ 16
+
+
+ CCR2_L
+ Low Capture/Compare 2
+ value
+ 0
+ 16
+
+
+
+
+ CCR3
+ CCR3
+ capture/compare register 3
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR3_H
+ High Capture/Compare value (TIM2
+ only)
+ 16
+ 16
+
+
+ CCR3_L
+ Low Capture/Compare value
+ 0
+ 16
+
+
+
+
+ CCR4
+ CCR4
+ capture/compare register 4
+ 0x40
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR4_H
+ High Capture/Compare value (TIM2
+ only)
+ 16
+ 16
+
+
+ CCR4_L
+ Low Capture/Compare value
+ 0
+ 16
+
+
+
+
+ DCR
+ DCR
+ DMA control register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DBL
+ DMA burst length
+ 8
+ 5
+
+
+ DBA
+ DMA base address
+ 0
+ 5
+
+
+
+
+ DMAR
+ DMAR
+ DMA address for full transfer
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMAB
+ DMA register for burst
+ accesses
+ 0
+ 16
+
+
+
+
+ OR
+ OR
+ TIM2 option register
+ 0x50
+ 0x20
+ read-write
+ 0x0000
+
+
+ ETR_RMP
+ Timer2 ETR remap
+ 0
+ 3
+
+
+ TI4_RMP
+ Internal trigger
+ 3
+ 2
+
+
+
+
+
+
+ TIM3
+ 0x40000400
+
+ TIM3
+ TIM3 global interrupt
+ 16
+
+
+
+ TIM6
+ Basic-timers
+ TIM
+ 0x40001000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM6
+ TIM6 global interrupt and DAC
+ 17
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ OPM
+ One-pulse mode
+ 3
+ 1
+
+
+ URS
+ Update request source
+ 2
+ 1
+
+
+ UDIS
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ MMS
+ Master mode selection
+ 4
+ 3
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ UDE
+ Update DMA request enable
+ 8
+ 1
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ UIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ UG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ Low counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ARR
+ Low Auto-reload value
+ 0
+ 16
+
+
+
+
+
+
+ TIM7
+ 0x40001400
+
+ TIM7
+ TIM7 global interrupt and DAC
+ 18
+
+
+
+ TIM21
+ General-purpose-timers
+ TIM
+ 0x40010800
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM21
+ TIMER21 global interrupt
+ 20
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+ UDIS
+ Update disable
+ 1
+ 1
+
+
+ URS
+ Update request source
+ 2
+ 1
+
+
+ OPM
+ One-pulse mode
+ 3
+ 1
+
+
+ DIR
+ Direction
+ 4
+ 1
+
+
+ CMS
+ Center-aligned mode
+ selection
+ 5
+ 2
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ CKD
+ Clock division
+ 8
+ 2
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ MMS
+ Master mode selection
+ 4
+ 3
+
+
+
+
+ SMCR
+ SMCR
+ slave mode control register
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ SMS
+ Slave mode selection
+ 0
+ 3
+
+
+ TS
+ Trigger selection
+ 4
+ 3
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ ETF
+ External trigger filter
+ 8
+ 4
+
+
+ ETPS
+ External trigger prescaler
+ 12
+ 2
+
+
+ ECE
+ External clock enable
+ 14
+ 1
+
+
+ ETP
+ External trigger polarity
+ 15
+ 1
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ TIE
+ Trigger interrupt enable
+ 6
+ 1
+
+
+ CC2IE
+ Capture/Compare 2 interrupt
+ enable
+ 2
+ 1
+
+
+ CC1IE
+ Capture/Compare 1 interrupt
+ enable
+ 1
+ 1
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC2OF
+ Capture/compare 2 overcapture
+ flag
+ 10
+ 1
+
+
+ CC1OF
+ Capture/Compare 1 overcapture
+ flag
+ 9
+ 1
+
+
+ TIF
+ Trigger interrupt flag
+ 6
+ 1
+
+
+ CC2IF
+ Capture/Compare 2 interrupt
+ flag
+ 2
+ 1
+
+
+ CC1IF
+ Capture/compare 1 interrupt
+ flag
+ 1
+ 1
+
+
+ UIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ TG
+ Trigger generation
+ 6
+ 1
+
+
+ CC2G
+ Capture/compare 2
+ generation
+ 2
+ 1
+
+
+ CC1G
+ Capture/compare 1
+ generation
+ 1
+ 1
+
+
+ UG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CCMR1_Output
+ CCMR1_Output
+ capture/compare mode register (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OC2M
+ Output Compare 2 mode
+ 12
+ 3
+
+
+ OC2PE
+ Output Compare 2 preload
+ enable
+ 11
+ 1
+
+
+ OC2FE
+ Output Compare 2 fast
+ enable
+ 10
+ 1
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ OC1M
+ Output Compare 1 mode
+ 4
+ 3
+
+
+ OC1PE
+ Output Compare 1 preload
+ enable
+ 3
+ 1
+
+
+ OC1FE
+ Output Compare 1 fast
+ enable
+ 2
+ 1
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR1_Input
+ CCMR1_Input
+ capture/compare mode register 1 (input
+ mode)
+ CCMR1_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC2F
+ Input capture 2 filter
+ 12
+ 4
+
+
+ IC2PSC
+ Input capture 2 prescaler
+ 10
+ 2
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ IC1F
+ Input capture 1 filter
+ 4
+ 4
+
+
+ IC1PSC
+ Input capture 1 prescaler
+ 2
+ 2
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCER
+ CCER
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC2NP
+ Capture/Compare 2 output
+ Polarity
+ 7
+ 1
+
+
+ CC2P
+ Capture/Compare 2 output
+ Polarity
+ 5
+ 1
+
+
+ CC2E
+ Capture/Compare 2 output
+ enable
+ 4
+ 1
+
+
+ CC1NP
+ Capture/Compare 1 output
+ Polarity
+ 3
+ 1
+
+
+ CC1P
+ Capture/Compare 1 output
+ Polarity
+ 1
+ 1
+
+
+ CC1E
+ Capture/Compare 1 output
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ARR
+ Auto-reload value
+ 0
+ 16
+
+
+
+
+ CCR1
+ CCR1
+ capture/compare register 1
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR1
+ Capture/Compare 1 value
+ 0
+ 16
+
+
+
+
+ CCR2
+ CCR2
+ capture/compare register 2
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR2
+ Capture/Compare 2 value
+ 0
+ 16
+
+
+
+
+ OR
+ OR
+ TIM21 option register
+ 0x50
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ETR_RMP
+ Timer21 ETR remap
+ 0
+ 2
+
+
+ TI1_RMP
+ Timer21 TI1
+ 2
+ 3
+
+
+ TI2_RMP
+ Timer21 TI2
+ 5
+ 1
+
+
+
+
+
+
+ TIM22
+ General-purpose-timers
+ TIM
+ 0x40011400
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM22
+ TIMER22 global interrupt
+ 22
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+ UDIS
+ Update disable
+ 1
+ 1
+
+
+ URS
+ Update request source
+ 2
+ 1
+
+
+ OPM
+ One-pulse mode
+ 3
+ 1
+
+
+ DIR
+ Direction
+ 4
+ 1
+
+
+ CMS
+ Center-aligned mode
+ selection
+ 5
+ 2
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ CKD
+ Clock division
+ 8
+ 2
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ MMS
+ Master mode selection
+ 4
+ 3
+
+
+
+
+ SMCR
+ SMCR
+ slave mode control register
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ SMS
+ Slave mode selection
+ 0
+ 3
+
+
+ TS
+ Trigger selection
+ 4
+ 3
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ ETF
+ External trigger filter
+ 8
+ 4
+
+
+ ETPS
+ External trigger prescaler
+ 12
+ 2
+
+
+ ECE
+ External clock enable
+ 14
+ 1
+
+
+ ETP
+ External trigger polarity
+ 15
+ 1
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ TIE
+ Trigger interrupt enable
+ 6
+ 1
+
+
+ CC2IE
+ Capture/Compare 2 interrupt
+ enable
+ 2
+ 1
+
+
+ CC1IE
+ Capture/Compare 1 interrupt
+ enable
+ 1
+ 1
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC2OF
+ Capture/compare 2 overcapture
+ flag
+ 10
+ 1
+
+
+ CC1OF
+ Capture/Compare 1 overcapture
+ flag
+ 9
+ 1
+
+
+ TIF
+ Trigger interrupt flag
+ 6
+ 1
+
+
+ CC2IF
+ Capture/Compare 2 interrupt
+ flag
+ 2
+ 1
+
+
+ CC1IF
+ Capture/compare 1 interrupt
+ flag
+ 1
+ 1
+
+
+ UIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ TG
+ Trigger generation
+ 6
+ 1
+
+
+ CC2G
+ Capture/compare 2
+ generation
+ 2
+ 1
+
+
+ CC1G
+ Capture/compare 1
+ generation
+ 1
+ 1
+
+
+ UG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CCMR1_Output
+ CCMR1_Output
+ capture/compare mode register (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OC2M
+ Output Compare 2 mode
+ 12
+ 3
+
+
+ OC2PE
+ Output Compare 2 preload
+ enable
+ 11
+ 1
+
+
+ OC2FE
+ Output Compare 2 fast
+ enable
+ 10
+ 1
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ OC1M
+ Output Compare 1 mode
+ 4
+ 3
+
+
+ OC1PE
+ Output Compare 1 preload
+ enable
+ 3
+ 1
+
+
+ OC1FE
+ Output Compare 1 fast
+ enable
+ 2
+ 1
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR1_Input
+ CCMR1_Input
+ capture/compare mode register 1 (input
+ mode)
+ CCMR1_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC2F
+ Input capture 2 filter
+ 12
+ 4
+
+
+ IC2PSC
+ Input capture 2 prescaler
+ 10
+ 2
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ IC1F
+ Input capture 1 filter
+ 4
+ 4
+
+
+ IC1PSC
+ Input capture 1 prescaler
+ 2
+ 2
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCER
+ CCER
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC2NP
+ Capture/Compare 2 output
+ Polarity
+ 7
+ 1
+
+
+ CC2P
+ Capture/Compare 2 output
+ Polarity
+ 5
+ 1
+
+
+ CC2E
+ Capture/Compare 2 output
+ enable
+ 4
+ 1
+
+
+ CC1NP
+ Capture/Compare 1 output
+ Polarity
+ 3
+ 1
+
+
+ CC1P
+ Capture/Compare 1 output
+ Polarity
+ 1
+ 1
+
+
+ CC1E
+ Capture/Compare 1 output
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ARR
+ Auto-reload value
+ 0
+ 16
+
+
+
+
+ CCR1
+ CCR1
+ capture/compare register 1
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR1
+ Capture/Compare 1 value
+ 0
+ 16
+
+
+
+
+ CCR2
+ CCR2
+ capture/compare register 2
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR2
+ Capture/Compare 2 value
+ 0
+ 16
+
+
+
+
+ OR
+ OR
+ TIM22 option register
+ 0x50
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ETR_RMP
+ Timer22 ETR remap
+ 0
+ 2
+
+
+ TI1_RMP
+ Timer22 TI1
+ 2
+ 2
+
+
+
+
+
+
+ LPUART1
+ Lower power Universal asynchronous receiver
+ transmitter
+ USART
+ 0x40004800
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CR1
+ CR1
+ Control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ M1
+ Word length
+ 28
+ 1
+
+
+ DEAT4
+ Driver Enable assertion
+ time
+ 25
+ 1
+
+
+ DEAT3
+ DEAT3
+ 24
+ 1
+
+
+ DEAT2
+ DEAT2
+ 23
+ 1
+
+
+ DEAT1
+ DEAT1
+ 22
+ 1
+
+
+ DEAT0
+ DEAT0
+ 21
+ 1
+
+
+ DEDT4
+ Driver Enable de-assertion
+ time
+ 20
+ 1
+
+
+ DEDT3
+ DEDT3
+ 19
+ 1
+
+
+ DEDT2
+ DEDT2
+ 18
+ 1
+
+
+ DEDT1
+ DEDT1
+ 17
+ 1
+
+
+ DEDT0
+ DEDT0
+ 16
+ 1
+
+
+ CMIE
+ Character match interrupt
+ enable
+ 14
+ 1
+
+
+ MME
+ Mute mode enable
+ 13
+ 1
+
+
+ M0
+ Word length
+ 12
+ 1
+
+
+ WAKE
+ Receiver wakeup method
+ 11
+ 1
+
+
+ PCE
+ Parity control enable
+ 10
+ 1
+
+
+ PS
+ Parity selection
+ 9
+ 1
+
+
+ PEIE
+ PE interrupt enable
+ 8
+ 1
+
+
+ TXEIE
+ interrupt enable
+ 7
+ 1
+
+
+ TCIE
+ Transmission complete interrupt
+ enable
+ 6
+ 1
+
+
+ RXNEIE
+ RXNE interrupt enable
+ 5
+ 1
+
+
+ IDLEIE
+ IDLE interrupt enable
+ 4
+ 1
+
+
+ TE
+ Transmitter enable
+ 3
+ 1
+
+
+ RE
+ Receiver enable
+ 2
+ 1
+
+
+ UESM
+ USART enable in Stop mode
+ 1
+ 1
+
+
+ UE
+ USART enable
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ Control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ ADD4_7
+ Address of the USART node
+ 28
+ 4
+
+
+ ADD0_3
+ Address of the USART node
+ 24
+ 4
+
+
+ MSBFIRST
+ Most significant bit first
+ 19
+ 1
+
+
+ TAINV
+ Binary data inversion
+ 18
+ 1
+
+
+ TXINV
+ TX pin active level
+ inversion
+ 17
+ 1
+
+
+ RXINV
+ RX pin active level
+ inversion
+ 16
+ 1
+
+
+ SWAP
+ Swap TX/RX pins
+ 15
+ 1
+
+
+ STOP
+ STOP bits
+ 12
+ 2
+
+
+ CLKEN
+ Clock enable
+ 11
+ 1
+
+
+ ADDM7
+ 7-bit Address Detection/4-bit Address
+ Detection
+ 4
+ 1
+
+
+
+
+ CR3
+ CR3
+ Control register 3
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ WUFIE
+ Wakeup from Stop mode interrupt
+ enable
+ 22
+ 1
+
+
+ WUS
+ Wakeup from Stop mode interrupt flag
+ selection
+ 20
+ 2
+
+
+ DEP
+ Driver enable polarity
+ selection
+ 15
+ 1
+
+
+ DEM
+ Driver enable mode
+ 14
+ 1
+
+
+ DDRE
+ DMA Disable on Reception
+ Error
+ 13
+ 1
+
+
+ OVRDIS
+ Overrun Disable
+ 12
+ 1
+
+
+ CTSIE
+ CTS interrupt enable
+ 10
+ 1
+
+
+ CTSE
+ CTS enable
+ 9
+ 1
+
+
+ RTSE
+ RTS enable
+ 8
+ 1
+
+
+ DMAT
+ DMA enable transmitter
+ 7
+ 1
+
+
+ DMAR
+ DMA enable receiver
+ 6
+ 1
+
+
+ HDSEL
+ Half-duplex selection
+ 3
+ 1
+
+
+ EIE
+ Error interrupt enable
+ 0
+ 1
+
+
+
+
+ BRR
+ BRR
+ Baud rate register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ BRR
+ BRR
+ 0
+ 20
+
+
+
+
+ RQR
+ RQR
+ Request register
+ 0x18
+ 0x20
+ write-only
+ 0x0000
+
+
+ RXFRQ
+ Receive data flush request
+ 3
+ 1
+
+
+ MMRQ
+ Mute mode request
+ 2
+ 1
+
+
+ SBKRQ
+ Send break request
+ 1
+ 1
+
+
+
+
+ ISR
+ ISR
+ Interrupt & status
+ register
+ 0x1C
+ 0x20
+ read-only
+ 0x00C0
+
+
+ REACK
+ REACK
+ 22
+ 1
+
+
+ TEACK
+ TEACK
+ 21
+ 1
+
+
+ WUF
+ WUF
+ 20
+ 1
+
+
+ RWU
+ RWU
+ 19
+ 1
+
+
+ SBKF
+ SBKF
+ 18
+ 1
+
+
+ CMF
+ CMF
+ 17
+ 1
+
+
+ BUSY
+ BUSY
+ 16
+ 1
+
+
+ CTS
+ CTS
+ 10
+ 1
+
+
+ CTSIF
+ CTSIF
+ 9
+ 1
+
+
+ TXE
+ TXE
+ 7
+ 1
+
+
+ TC
+ TC
+ 6
+ 1
+
+
+ RXNE
+ RXNE
+ 5
+ 1
+
+
+ IDLE
+ IDLE
+ 4
+ 1
+
+
+ ORE
+ ORE
+ 3
+ 1
+
+
+ NF
+ NF
+ 2
+ 1
+
+
+ FE
+ FE
+ 1
+ 1
+
+
+ PE
+ PE
+ 0
+ 1
+
+
+
+
+ ICR
+ ICR
+ Interrupt flag clear register
+ 0x20
+ 0x20
+ write-only
+ 0x0000
+
+
+ WUCF
+ Wakeup from Stop mode clear
+ flag
+ 20
+ 1
+
+
+ CMCF
+ Character match clear flag
+ 17
+ 1
+
+
+ CTSCF
+ CTS clear flag
+ 9
+ 1
+
+
+ TCCF
+ Transmission complete clear
+ flag
+ 6
+ 1
+
+
+ IDLECF
+ Idle line detected clear
+ flag
+ 4
+ 1
+
+
+ ORECF
+ Overrun error clear flag
+ 3
+ 1
+
+
+ NCF
+ Noise detected clear flag
+ 2
+ 1
+
+
+ FECF
+ Framing error clear flag
+ 1
+ 1
+
+
+ PECF
+ Parity error clear flag
+ 0
+ 1
+
+
+
+
+ RDR
+ RDR
+ Receive data register
+ 0x24
+ 0x20
+ read-only
+ 0x0000
+
+
+ RDR
+ Receive data value
+ 0
+ 9
+
+
+
+
+ TDR
+ TDR
+ Transmit data register
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ TDR
+ Transmit data value
+ 0
+ 9
+
+
+
+
+
+
+ NVIC
+ Nested Vectored Interrupt
+ Controller
+ NVIC
+ 0xE000E100
+
+ 0x0
+ 0x33D
+ registers
+
+
+
+ ISER
+ ISER
+ Interrupt Set Enable Register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ICER
+ ICER
+ Interrupt Clear Enable
+ Register
+ 0x80
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ISPR
+ ISPR
+ Interrupt Set-Pending Register
+ 0x100
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ICPR
+ ICPR
+ Interrupt Clear-Pending
+ Register
+ 0x180
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ IPR0
+ IPR0
+ Interrupt Priority Register 0
+ 0x300
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_0
+ priority for interrupt 0
+ 0
+ 8
+
+
+ PRI_1
+ priority for interrupt 1
+ 8
+ 8
+
+
+ PRI_2
+ priority for interrupt 2
+ 16
+ 8
+
+
+ PRI_3
+ priority for interrupt 3
+ 24
+ 8
+
+
+
+
+ IPR1
+ IPR1
+ Interrupt Priority Register 1
+ 0x304
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_4
+ priority for interrupt n
+ 0
+ 8
+
+
+ PRI_5
+ priority for interrupt n
+ 8
+ 8
+
+
+ PRI_6
+ priority for interrupt n
+ 16
+ 8
+
+
+ PRI_7
+ priority for interrupt n
+ 24
+ 8
+
+
+
+
+ IPR2
+ IPR2
+ Interrupt Priority Register 2
+ 0x308
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_8
+ priority for interrupt n
+ 0
+ 8
+
+
+ PRI_9
+ priority for interrupt n
+ 8
+ 8
+
+
+ PRI_10
+ priority for interrupt n
+ 16
+ 8
+
+
+ PRI_11
+ priority for interrupt n
+ 24
+ 8
+
+
+
+
+ IPR3
+ IPR3
+ Interrupt Priority Register 3
+ 0x30C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_12
+ priority for interrupt n
+ 0
+ 8
+
+
+ PRI_13
+ priority for interrupt n
+ 8
+ 8
+
+
+ PRI_14
+ priority for interrupt n
+ 16
+ 8
+
+
+ PRI_15
+ priority for interrupt n
+ 24
+ 8
+
+
+
+
+ IPR4
+ IPR4
+ Interrupt Priority Register 4
+ 0x310
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_16
+ priority for interrupt n
+ 0
+ 8
+
+
+ PRI_17
+ priority for interrupt n
+ 8
+ 8
+
+
+ PRI_18
+ priority for interrupt n
+ 16
+ 8
+
+
+ PRI_19
+ priority for interrupt n
+ 24
+ 8
+
+
+
+
+ IPR5
+ IPR5
+ Interrupt Priority Register 5
+ 0x314
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_20
+ priority for interrupt n
+ 0
+ 8
+
+
+ PRI_21
+ priority for interrupt n
+ 8
+ 8
+
+
+ PRI_22
+ priority for interrupt n
+ 16
+ 8
+
+
+ PRI_23
+ priority for interrupt n
+ 24
+ 8
+
+
+
+
+ IPR6
+ IPR6
+ Interrupt Priority Register 6
+ 0x318
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_24
+ priority for interrupt n
+ 0
+ 8
+
+
+ PRI_25
+ priority for interrupt n
+ 8
+ 8
+
+
+ PRI_26
+ priority for interrupt n
+ 16
+ 8
+
+
+ PRI_27
+ priority for interrupt n
+ 24
+ 8
+
+
+
+
+ IPR7
+ IPR7
+ Interrupt Priority Register 7
+ 0x31C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_28
+ priority for interrupt n
+ 0
+ 8
+
+
+ PRI_29
+ priority for interrupt n
+ 8
+ 8
+
+
+ PRI_30
+ priority for interrupt n
+ 16
+ 8
+
+
+ PRI_31
+ priority for interrupt n
+ 24
+ 8
+
+
+
+
+
+
+ MPU
+ Memory protection unit
+ MPU
+ 0xE000ED90
+
+ 0x0
+ 0x15
+ registers
+
+
+
+ MPU_TYPER
+ MPU_TYPER
+ MPU type register
+ 0x0
+ 0x20
+ read-only
+ 0X00000800
+
+
+ SEPARATE
+ Separate flag
+ 0
+ 1
+
+
+ DREGION
+ Number of MPU data regions
+ 8
+ 8
+
+
+ IREGION
+ Number of MPU instruction
+ regions
+ 16
+ 8
+
+
+
+
+ MPU_CTRL
+ MPU_CTRL
+ MPU control register
+ 0x4
+ 0x20
+ read-only
+ 0X00000000
+
+
+ ENABLE
+ Enables the MPU
+ 0
+ 1
+
+
+ HFNMIENA
+ Enables the operation of MPU during hard
+ fault
+ 1
+ 1
+
+
+ PRIVDEFENA
+ Enable priviliged software access to
+ default memory map
+ 2
+ 1
+
+
+
+
+ MPU_RNR
+ MPU_RNR
+ MPU region number register
+ 0x8
+ 0x20
+ read-write
+ 0X00000000
+
+
+ REGION
+ MPU region
+ 0
+ 8
+
+
+
+
+ MPU_RBAR
+ MPU_RBAR
+ MPU region base address
+ register
+ 0xC
+ 0x20
+ read-write
+ 0X00000000
+
+
+ REGION
+ MPU region field
+ 0
+ 4
+
+
+ VALID
+ MPU region number valid
+ 4
+ 1
+
+
+ ADDR
+ Region base address field
+ 5
+ 27
+
+
+
+
+ MPU_RASR
+ MPU_RASR
+ MPU region attribute and size
+ register
+ 0x10
+ 0x20
+ read-write
+ 0X00000000
+
+
+ ENABLE
+ Region enable bit.
+ 0
+ 1
+
+
+ SIZE
+ Size of the MPU protection
+ region
+ 1
+ 5
+
+
+ SRD
+ Subregion disable bits
+ 8
+ 8
+
+
+ B
+ memory attribute
+ 16
+ 1
+
+
+ C
+ memory attribute
+ 17
+ 1
+
+
+ S
+ Shareable memory attribute
+ 18
+ 1
+
+
+ TEX
+ memory attribute
+ 19
+ 3
+
+
+ AP
+ Access permission
+ 24
+ 3
+
+
+ XN
+ Instruction access disable
+ bit
+ 28
+ 1
+
+
+
+
+
+
+ STK
+ SysTick timer
+ STK
+ 0xE000E010
+
+ 0x0
+ 0x11
+ registers
+
+
+
+ CSR
+ CSR
+ SysTick control and status
+ register
+ 0x0
+ 0x20
+ read-write
+ 0X00000000
+
+
+ ENABLE
+ Counter enable
+ 0
+ 1
+
+
+ TICKINT
+ SysTick exception request
+ enable
+ 1
+ 1
+
+
+ CLKSOURCE
+ Clock source selection
+ 2
+ 1
+
+
+ COUNTFLAG
+ COUNTFLAG
+ 16
+ 1
+
+
+
+
+ RVR
+ RVR
+ SysTick reload value register
+ 0x4
+ 0x20
+ read-write
+ 0X00000000
+
+
+ RELOAD
+ RELOAD value
+ 0
+ 24
+
+
+
+
+ CVR
+ CVR
+ SysTick current value register
+ 0x8
+ 0x20
+ read-write
+ 0X00000000
+
+
+ CURRENT
+ Current counter value
+ 0
+ 24
+
+
+
+
+ CALIB
+ CALIB
+ SysTick calibration value
+ register
+ 0xC
+ 0x20
+ read-write
+ 0X00000000
+
+
+ TENMS
+ Calibration value
+ 0
+ 24
+
+
+ SKEW
+ SKEW flag: Indicates whether the TENMS
+ value is exact
+ 30
+ 1
+
+
+ NOREF
+ NOREF flag. Reads as zero
+ 31
+ 1
+
+
+
+
+
+
+ SCB
+ System control block
+ SCB
+ 0xE000ED00
+
+ 0x0
+ 0x41
+ registers
+
+
+
+ CPUID
+ CPUID
+ CPUID base register
+ 0x0
+ 0x20
+ read-only
+ 0x410FC241
+
+
+ Revision
+ Revision number
+ 0
+ 4
+
+
+ PartNo
+ Part number of the
+ processor
+ 4
+ 12
+
+
+ Architecture
+ Reads as 0xF
+ 16
+ 4
+
+
+ Variant
+ Variant number
+ 20
+ 4
+
+
+ Implementer
+ Implementer code
+ 24
+ 8
+
+
+
+
+ ICSR
+ ICSR
+ Interrupt control and state
+ register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ VECTACTIVE
+ Active vector
+ 0
+ 9
+
+
+ RETTOBASE
+ Return to base level
+ 11
+ 1
+
+
+ VECTPENDING
+ Pending vector
+ 12
+ 7
+
+
+ ISRPENDING
+ Interrupt pending flag
+ 22
+ 1
+
+
+ PENDSTCLR
+ SysTick exception clear-pending
+ bit
+ 25
+ 1
+
+
+ PENDSTSET
+ SysTick exception set-pending
+ bit
+ 26
+ 1
+
+
+ PENDSVCLR
+ PendSV clear-pending bit
+ 27
+ 1
+
+
+ PENDSVSET
+ PendSV set-pending bit
+ 28
+ 1
+
+
+ NMIPENDSET
+ NMI set-pending bit.
+ 31
+ 1
+
+
+
+
+ VTOR
+ VTOR
+ Vector table offset register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TBLOFF
+ Vector table base offset
+ field
+ 7
+ 25
+
+
+
+
+ AIRCR
+ AIRCR
+ Application interrupt and reset control
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ VECTCLRACTIVE
+ VECTCLRACTIVE
+ 1
+ 1
+
+
+ SYSRESETREQ
+ SYSRESETREQ
+ 2
+ 1
+
+
+ ENDIANESS
+ ENDIANESS
+ 15
+ 1
+
+
+ VECTKEYSTAT
+ Register key
+ 16
+ 16
+
+
+
+
+ SCR
+ SCR
+ System control register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SLEEPONEXIT
+ SLEEPONEXIT
+ 1
+ 1
+
+
+ SLEEPDEEP
+ SLEEPDEEP
+ 2
+ 1
+
+
+ SEVEONPEND
+ Send Event on Pending bit
+ 4
+ 1
+
+
+
+
+ CCR
+ CCR
+ Configuration and control
+ register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NONBASETHRDENA
+ Configures how the processor enters
+ Thread mode
+ 0
+ 1
+
+
+ USERSETMPEND
+ USERSETMPEND
+ 1
+ 1
+
+
+ UNALIGN__TRP
+ UNALIGN_ TRP
+ 3
+ 1
+
+
+ DIV_0_TRP
+ DIV_0_TRP
+ 4
+ 1
+
+
+ BFHFNMIGN
+ BFHFNMIGN
+ 8
+ 1
+
+
+ STKALIGN
+ STKALIGN
+ 9
+ 1
+
+
+
+
+ SHPR2
+ SHPR2
+ System handler priority
+ registers
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_11
+ Priority of system handler
+ 11
+ 24
+ 8
+
+
+
+
+ SHPR3
+ SHPR3
+ System handler priority
+ registers
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_14
+ Priority of system handler
+ 14
+ 16
+ 8
+
+
+ PRI_15
+ Priority of system handler
+ 15
+ 24
+ 8
+
+
+
+
+
+
+
diff --git a/board-support/stmicro-stm32/src/chips/STM32L0x2.svd b/board-support/stmicro-stm32/src/chips/STM32L0x2.svd
new file mode 100644
index 0000000..bc19e6f
--- /dev/null
+++ b/board-support/stmicro-stm32/src/chips/STM32L0x2.svd
@@ -0,0 +1,20698 @@
+
+
+ STM32L0x2
+ 1.3
+ STM32L0x2
+
+
+ CM0+
+ r0p0
+ little
+ false
+ false
+ 3
+ false
+
+
+
+ 8
+
+ 32
+
+ 0x20
+ 0x0
+ 0xFFFFFFFF
+
+
+ AES
+ Advanced encryption standard hardware
+ accelerator
+ AES
+ 0x40026000
+
+ 0x0
+ 0x400
+ registers
+
+
+ AES_RNG_LPUART1
+ AES global interrupt RNG global interrupt and
+ LPUART1 global interrupt through
+ 29
+
+
+
+ CR
+ CR
+ control register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DMAOUTEN
+ Enable DMA management of data output
+ phase
+ 12
+ 1
+
+
+ DMAINEN
+ Enable DMA management of data input
+ phase
+ 11
+ 1
+
+
+ ERRIE
+ Error interrupt enable
+ 10
+ 1
+
+
+ CCFIE
+ CCF flag interrupt enable
+ 9
+ 1
+
+
+ ERRC
+ Error clear
+ 8
+ 1
+
+
+ CCFC
+ Computation Complete Flag
+ Clear
+ 7
+ 1
+
+
+ CHMOD
+ AES chaining mode
+ 5
+ 2
+
+
+ MODE
+ AES operating mode
+ 3
+ 2
+
+
+ DATATYPE
+ Data type selection (for data in and
+ data out to/from the cryptographic
+ block)
+ 1
+ 2
+
+
+ EN
+ AES enable
+ 0
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x4
+ 0x20
+ read-only
+ 0x00000000
+
+
+ WRERR
+ Write error flag
+ 2
+ 1
+
+
+ RDERR
+ Read error flag
+ 1
+ 1
+
+
+ CCF
+ Computation complete flag
+ 0
+ 1
+
+
+
+
+ DINR
+ DINR
+ data input register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AES_DINR
+ Data Input Register.
+ 0
+ 32
+
+
+
+
+ DOUTR
+ DOUTR
+ data output register
+ 0xC
+ 0x20
+ read-only
+ 0x00000000
+
+
+ AES_DOUTR
+ Data output register
+ 0
+ 32
+
+
+
+
+ KEYR0
+ KEYR0
+ key register 0
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AES_KEYR0
+ Data Output Register (LSB key
+ [31:0])
+ 0
+ 32
+
+
+
+
+ KEYR1
+ KEYR1
+ key register 1
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AES_KEYR1
+ AES key register (key
+ [63:32])
+ 0
+ 32
+
+
+
+
+ KEYR2
+ KEYR2
+ key register 2
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AES_KEYR2
+ AES key register (key
+ [95:64])
+ 0
+ 32
+
+
+
+
+ KEYR3
+ KEYR3
+ key register 3
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AES_KEYR3
+ AES key register (MSB key
+ [127:96])
+ 0
+ 32
+
+
+
+
+ IVR0
+ IVR0
+ initialization vector register
+ 0
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AES_IVR0
+ initialization vector register (LSB IVR
+ [31:0])
+ 0
+ 32
+
+
+
+
+ IVR1
+ IVR1
+ initialization vector register
+ 1
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AES_IVR1
+ Initialization Vector Register (IVR
+ [63:32])
+ 0
+ 32
+
+
+
+
+ IVR2
+ IVR2
+ initialization vector register
+ 2
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AES_IVR2
+ Initialization Vector Register (IVR
+ [95:64])
+ 0
+ 32
+
+
+
+
+ IVR3
+ IVR3
+ initialization vector register
+ 3
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AES_IVR3
+ Initialization Vector Register (MSB IVR
+ [127:96])
+ 0
+ 32
+
+
+
+
+
+
+ DAC
+ Digital-to-analog converter
+ DAC
+ 0x40007400
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CR
+ CR
+ control register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DMAUDRIE1
+ DAC channel1 DMA Underrun Interrupt
+ enable
+ 13
+ 1
+
+
+ DMAEN1
+ DAC channel1 DMA enable
+ 12
+ 1
+
+
+ MAMP1
+ DAC channel1 mask/amplitude
+ selector
+ 8
+ 4
+
+
+ WAVE1
+ DAC channel1 noise/triangle wave
+ generation enable
+ 6
+ 2
+
+
+ TSEL1
+ DAC channel1 trigger
+ selection
+ 3
+ 3
+
+
+ TEN1
+ DAC channel1 trigger
+ enable
+ 2
+ 1
+
+
+ BOFF1
+ DAC channel1 output buffer
+ disable
+ 1
+ 1
+
+
+ EN1
+ DAC channel1 enable
+ 0
+ 1
+
+
+
+
+ SWTRIGR
+ SWTRIGR
+ software trigger register
+ 0x4
+ 0x20
+ write-only
+ 0x00000000
+
+
+ SWTRIG1
+ DAC channel1 software
+ trigger
+ 0
+ 1
+
+
+
+
+ DHR12R1
+ DHR12R1
+ channel1 12-bit right-aligned data holding
+ register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC1DHR
+ DAC channel1 12-bit right-aligned
+ data
+ 0
+ 12
+
+
+
+
+ DHR12L1
+ DHR12L1
+ channel1 12-bit left-aligned data holding
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC1DHR
+ DAC channel1 12-bit left-aligned
+ data
+ 4
+ 12
+
+
+
+
+ DHR8R1
+ DHR8R1
+ channel1 8-bit right-aligned data holding
+ register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC1DHR
+ DAC channel1 8-bit right-aligned
+ data
+ 0
+ 8
+
+
+
+
+ DOR1
+ DOR1
+ channel1 data output register
+ 0x2C
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DACC1DOR
+ DAC channel1 data output
+ 0
+ 12
+
+
+
+
+ SR
+ SR
+ status register
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DMAUDR1
+ DAC channel1 DMA underrun
+ flag
+ 13
+ 1
+
+
+
+
+ DHR12R2
+ DHR12R2
+ channel2 12-bit right-aligned data holding
+ register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC2DHR
+ DAC channel2 12-bit right-aligned
+ data
+ 0
+ 12
+
+
+
+
+ DHR12L2
+ DHR12L2
+ channel2 12-bit left-aligned data holding
+ register
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC2DHR
+ DAC channel2 12-bit left-aligned
+ data
+ 4
+ 12
+
+
+
+
+ DHR8R2
+ DHR8R2
+ channel2 8-bit right-aligned data holding
+ register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC2DHR
+ DAC channel2 8-bit right-aligned
+ data
+ 0
+ 8
+
+
+
+
+ DHR12RD
+ DHR12RD
+ Dual DAC 12-bit right-aligned data holding
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC1DHR
+ DAC channel1 12-bit right-aligned
+ data
+ 0
+ 12
+
+
+ DACC2DHR
+ DAC channel2 12-bit right-aligned
+ data
+ 16
+ 12
+
+
+
+
+ DHR12LD
+ DHR12LD
+ Dual DAC 12-bit left-aligned data holding
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC1DHR
+ DAC channel1 12-bit left-aligned
+ data
+ 4
+ 12
+
+
+ DACC2DHR
+ DAC channel2 12-bit left-aligned
+ data
+ 20
+ 12
+
+
+
+
+ DHR8RD
+ DHR8RD
+ Dual DAC 8-bit right-aligned data holding
+ register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC1DHR
+ DAC channel1 8-bit right-aligned
+ data
+ 0
+ 8
+
+
+ DACC2DHR
+ DAC channel2 8-bit right-aligned
+ data
+ 8
+ 8
+
+
+
+
+ DOR2
+ DOR2
+ channel2 data output register
+ 0x30
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DACC2DOR
+ DAC channel2 data output
+ 0
+ 12
+
+
+
+
+
+
+ DMA1
+ Direct memory access controller
+ DMA
+ 0x40020000
+
+ 0x0
+ 0x400
+ registers
+
+
+ DMA1_Channel1
+ DMA1 Channel1 global interrupt
+ 9
+
+
+ DMA1_Channel2_3
+ DMA1 Channel2 and 3 interrupts
+ 10
+
+
+ DMA1_Channel4_7
+ DMA1 Channel4 to 7 interrupts
+ 11
+
+
+
+ ISR
+ ISR
+ interrupt status register
+ 0x0
+ 0x20
+ read-only
+ 0x00000000
+
+
+ TEIF7
+ Channel x transfer error flag (x = 1
+ ..7)
+ 27
+ 1
+
+
+ HTIF7
+ Channel x half transfer flag (x = 1
+ ..7)
+ 26
+ 1
+
+
+ TCIF7
+ Channel x transfer complete flag (x = 1
+ ..7)
+ 25
+ 1
+
+
+ GIF7
+ Channel x global interrupt flag (x = 1
+ ..7)
+ 24
+ 1
+
+
+ TEIF6
+ Channel x transfer error flag (x = 1
+ ..7)
+ 23
+ 1
+
+
+ HTIF6
+ Channel x half transfer flag (x = 1
+ ..7)
+ 22
+ 1
+
+
+ TCIF6
+ Channel x transfer complete flag (x = 1
+ ..7)
+ 21
+ 1
+
+
+ GIF6
+ Channel x global interrupt flag (x = 1
+ ..7)
+ 20
+ 1
+
+
+ TEIF5
+ Channel x transfer error flag (x = 1
+ ..7)
+ 19
+ 1
+
+
+ HTIF5
+ Channel x half transfer flag (x = 1
+ ..7)
+ 18
+ 1
+
+
+ TCIF5
+ Channel x transfer complete flag (x = 1
+ ..7)
+ 17
+ 1
+
+
+ GIF5
+ Channel x global interrupt flag (x = 1
+ ..7)
+ 16
+ 1
+
+
+ TEIF4
+ Channel x transfer error flag (x = 1
+ ..7)
+ 15
+ 1
+
+
+ HTIF4
+ Channel x half transfer flag (x = 1
+ ..7)
+ 14
+ 1
+
+
+ TCIF4
+ Channel x transfer complete flag (x = 1
+ ..7)
+ 13
+ 1
+
+
+ GIF4
+ Channel x global interrupt flag (x = 1
+ ..7)
+ 12
+ 1
+
+
+ TEIF3
+ Channel x transfer error flag (x = 1
+ ..7)
+ 11
+ 1
+
+
+ HTIF3
+ Channel x half transfer flag (x = 1
+ ..7)
+ 10
+ 1
+
+
+ TCIF3
+ Channel x transfer complete flag (x = 1
+ ..7)
+ 9
+ 1
+
+
+ GIF3
+ Channel x global interrupt flag (x = 1
+ ..7)
+ 8
+ 1
+
+
+ TEIF2
+ Channel x transfer error flag (x = 1
+ ..7)
+ 7
+ 1
+
+
+ HTIF2
+ Channel x half transfer flag (x = 1
+ ..7)
+ 6
+ 1
+
+
+ TCIF2
+ Channel x transfer complete flag (x = 1
+ ..7)
+ 5
+ 1
+
+
+ GIF2
+ Channel x global interrupt flag (x = 1
+ ..7)
+ 4
+ 1
+
+
+ TEIF1
+ Channel x transfer error flag (x = 1
+ ..7)
+ 3
+ 1
+
+
+ HTIF1
+ Channel x half transfer flag (x = 1
+ ..7)
+ 2
+ 1
+
+
+ TCIF1
+ Channel x transfer complete flag (x = 1
+ ..7)
+ 1
+ 1
+
+
+ GIF1
+ Channel x global interrupt flag (x = 1
+ ..7)
+ 0
+ 1
+
+
+
+
+ IFCR
+ IFCR
+ interrupt flag clear register
+ 0x4
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CTEIF7
+ Channel x transfer error clear (x = 1
+ ..7)
+ 27
+ 1
+
+
+ CHTIF7
+ Channel x half transfer clear (x = 1
+ ..7)
+ 26
+ 1
+
+
+ CTCIF7
+ Channel x transfer complete clear (x = 1
+ ..7)
+ 25
+ 1
+
+
+ CGIF7
+ Channel x global interrupt clear (x = 1
+ ..7)
+ 24
+ 1
+
+
+ CTEIF6
+ Channel x transfer error clear (x = 1
+ ..7)
+ 23
+ 1
+
+
+ CHTIF6
+ Channel x half transfer clear (x = 1
+ ..7)
+ 22
+ 1
+
+
+ CTCIF6
+ Channel x transfer complete clear (x = 1
+ ..7)
+ 21
+ 1
+
+
+ CGIF6
+ Channel x global interrupt clear (x = 1
+ ..7)
+ 20
+ 1
+
+
+ CTEIF5
+ Channel x transfer error clear (x = 1
+ ..7)
+ 19
+ 1
+
+
+ CHTIF5
+ Channel x half transfer clear (x = 1
+ ..7)
+ 18
+ 1
+
+
+ CTCIF5
+ Channel x transfer complete clear (x = 1
+ ..7)
+ 17
+ 1
+
+
+ CGIF5
+ Channel x global interrupt clear (x = 1
+ ..7)
+ 16
+ 1
+
+
+ CTEIF4
+ Channel x transfer error clear (x = 1
+ ..7)
+ 15
+ 1
+
+
+ CHTIF4
+ Channel x half transfer clear (x = 1
+ ..7)
+ 14
+ 1
+
+
+ CTCIF4
+ Channel x transfer complete clear (x = 1
+ ..7)
+ 13
+ 1
+
+
+ CGIF4
+ Channel x global interrupt clear (x = 1
+ ..7)
+ 12
+ 1
+
+
+ CTEIF3
+ Channel x transfer error clear (x = 1
+ ..7)
+ 11
+ 1
+
+
+ CHTIF3
+ Channel x half transfer clear (x = 1
+ ..7)
+ 10
+ 1
+
+
+ CTCIF3
+ Channel x transfer complete clear (x = 1
+ ..7)
+ 9
+ 1
+
+
+ CGIF3
+ Channel x global interrupt clear (x = 1
+ ..7)
+ 8
+ 1
+
+
+ CTEIF2
+ Channel x transfer error clear (x = 1
+ ..7)
+ 7
+ 1
+
+
+ CHTIF2
+ Channel x half transfer clear (x = 1
+ ..7)
+ 6
+ 1
+
+
+ CTCIF2
+ Channel x transfer complete clear (x = 1
+ ..7)
+ 5
+ 1
+
+
+ CGIF2
+ Channel x global interrupt clear (x = 1
+ ..7)
+ 4
+ 1
+
+
+ CTEIF1
+ Channel x transfer error clear (x = 1
+ ..7)
+ 3
+ 1
+
+
+ CHTIF1
+ Channel x half transfer clear (x = 1
+ ..7)
+ 2
+ 1
+
+
+ CTCIF1
+ Channel x transfer complete clear (x = 1
+ ..7)
+ 1
+ 1
+
+
+ CGIF1
+ Channel x global interrupt clear (x = 1
+ ..7)
+ 0
+ 1
+
+
+
+
+ CCR1
+ CCR1
+ channel x configuration
+ register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+ PL
+ Channel priority level
+ 12
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ HTIE
+ Half transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+
+
+ CNDTR1
+ CNDTR1
+ channel x number of data
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR1
+ CPAR1
+ channel x peripheral address
+ register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR1
+ CMAR1
+ channel x memory address
+ register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR2
+ CCR2
+ channel x configuration
+ register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+ PL
+ Channel priority level
+ 12
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ HTIE
+ Half transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+
+
+ CNDTR2
+ CNDTR2
+ channel x number of data
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR2
+ CPAR2
+ channel x peripheral address
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR2
+ CMAR2
+ channel x memory address
+ register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR3
+ CCR3
+ channel x configuration
+ register
+ 0x30
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+ PL
+ Channel priority level
+ 12
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ HTIE
+ Half transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+
+
+ CNDTR3
+ CNDTR3
+ channel x number of data
+ register
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR3
+ CPAR3
+ channel x peripheral address
+ register
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR3
+ CMAR3
+ channel x memory address
+ register
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR4
+ CCR4
+ channel x configuration
+ register
+ 0x44
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+ PL
+ Channel priority level
+ 12
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ HTIE
+ Half transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+
+
+ CNDTR4
+ CNDTR4
+ channel x number of data
+ register
+ 0x48
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR4
+ CPAR4
+ channel x peripheral address
+ register
+ 0x4C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR4
+ CMAR4
+ channel x memory address
+ register
+ 0x50
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR5
+ CCR5
+ channel x configuration
+ register
+ 0x58
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+ PL
+ Channel priority level
+ 12
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ HTIE
+ Half transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+
+
+ CNDTR5
+ CNDTR5
+ channel x number of data
+ register
+ 0x5C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR5
+ CPAR5
+ channel x peripheral address
+ register
+ 0x60
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR5
+ CMAR5
+ channel x memory address
+ register
+ 0x64
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR6
+ CCR6
+ channel x configuration
+ register
+ 0x6C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+ PL
+ Channel priority level
+ 12
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ HTIE
+ Half transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+
+
+ CNDTR6
+ CNDTR6
+ channel x number of data
+ register
+ 0x70
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR6
+ CPAR6
+ channel x peripheral address
+ register
+ 0x74
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR6
+ CMAR6
+ channel x memory address
+ register
+ 0x78
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR7
+ CCR7
+ channel x configuration
+ register
+ 0x80
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+ PL
+ Channel priority level
+ 12
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ HTIE
+ Half transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+
+
+ CNDTR7
+ CNDTR7
+ channel x number of data
+ register
+ 0x84
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR7
+ CPAR7
+ channel x peripheral address
+ register
+ 0x88
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR7
+ CMAR7
+ channel x memory address
+ register
+ 0x8C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CSELR
+ CSELR
+ channel selection register
+ 0xA8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ C7S
+ DMA channel 7 selection
+ 24
+ 4
+
+
+ C6S
+ DMA channel 6 selection
+ 20
+ 4
+
+
+ C5S
+ DMA channel 5 selection
+ 16
+ 4
+
+
+ C4S
+ DMA channel 4 selection
+ 12
+ 4
+
+
+ C3S
+ DMA channel 3 selection
+ 8
+ 4
+
+
+ C2S
+ DMA channel 2 selection
+ 4
+ 4
+
+
+ C1S
+ DMA channel 1 selection
+ 0
+ 4
+
+
+
+
+
+
+ CRC
+ Cyclic redundancy check calculation
+ unit
+ CRC
+ 0x40023000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ DR
+ DR
+ Data register
+ 0x0
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ DR
+ Data register bits
+ 0
+ 32
+
+
+
+
+ IDR
+ IDR
+ Independent data register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IDR
+ General-purpose 8-bit data register
+ bits
+ 0
+ 8
+
+
+
+
+ CR
+ CR
+ Control register
+ 0x8
+ 0x20
+ 0x00000000
+
+
+ REV_OUT
+ Reverse output data
+ 7
+ 1
+ read-write
+
+
+ REV_IN
+ Reverse input data
+ 5
+ 2
+ read-write
+
+
+ POLYSIZE
+ Polynomial size
+ 3
+ 2
+ read-write
+
+
+ RESET
+ RESET bit
+ 0
+ 1
+ write-only
+
+
+
+
+ INIT
+ INIT
+ Initial CRC value
+ 0x10
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ CRC_INIT
+ Programmable initial CRC
+ value
+ 0
+ 32
+
+
+
+
+ POL
+ POL
+ polynomial
+ 0x14
+ 0x20
+ read-write
+ 0x04C11DB7
+
+
+ Polynomialcoefficients
+ Programmable polynomial
+ 0
+ 32
+
+
+
+
+
+
+ GPIOA
+ General-purpose I/Os
+ GPIO
+ 0x50000000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ MODER
+ MODER
+ GPIO port mode register
+ 0x0
+ 0x20
+ read-write
+ 0xEBFFFCFF
+
+
+ MODE0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+ MODE1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ MODE2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ MODE3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ MODE4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ MODE5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ MODE6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ MODE7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ MODE8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ MODE9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ MODE10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ MODE11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ MODE12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ MODE13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ MODE14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ MODE15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+
+
+ OTYPER
+ OTYPER
+ GPIO port output type register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OT15
+ Port x configuration bits (y =
+ 0..15)
+ 15
+ 1
+
+
+ OT14
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 1
+
+
+ OT13
+ Port x configuration bits (y =
+ 0..15)
+ 13
+ 1
+
+
+ OT12
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 1
+
+
+ OT11
+ Port x configuration bits (y =
+ 0..15)
+ 11
+ 1
+
+
+ OT10
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 1
+
+
+ OT9
+ Port x configuration bits (y =
+ 0..15)
+ 9
+ 1
+
+
+ OT8
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 1
+
+
+ OT7
+ Port x configuration bits (y =
+ 0..15)
+ 7
+ 1
+
+
+ OT6
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 1
+
+
+ OT5
+ Port x configuration bits (y =
+ 0..15)
+ 5
+ 1
+
+
+ OT4
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 1
+
+
+ OT3
+ Port x configuration bits (y =
+ 0..15)
+ 3
+ 1
+
+
+ OT2
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 1
+
+
+ OT1
+ Port x configuration bits (y =
+ 0..15)
+ 1
+ 1
+
+
+ OT0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ OSPEEDR
+ OSPEEDR
+ GPIO port output speed
+ register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OSPEED15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ OSPEED14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ OSPEED13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ OSPEED12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ OSPEED11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ OSPEED10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ OSPEED9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ OSPEED8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ OSPEED7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ OSPEED6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ OSPEED5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ OSPEED4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ OSPEED3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ OSPEED2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ OSPEED1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ OSPEED0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ PUPDR
+ PUPDR
+ GPIO port pull-up/pull-down
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x24000000
+
+
+ PUPD15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ PUPD14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ PUPD13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ PUPD12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ PUPD11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ PUPD10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ PUPD9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ PUPD8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ PUPD7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ PUPD6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ PUPD5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ PUPD4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ PUPD3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ PUPD2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ PUPD1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ PUPD0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ IDR
+ IDR
+ GPIO port input data register
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ ID15
+ Port input data bit (y =
+ 0..15)
+ 15
+ 1
+
+
+ ID14
+ Port input data bit (y =
+ 0..15)
+ 14
+ 1
+
+
+ ID13
+ Port input data bit (y =
+ 0..15)
+ 13
+ 1
+
+
+ ID12
+ Port input data bit (y =
+ 0..15)
+ 12
+ 1
+
+
+ ID11
+ Port input data bit (y =
+ 0..15)
+ 11
+ 1
+
+
+ ID10
+ Port input data bit (y =
+ 0..15)
+ 10
+ 1
+
+
+ ID9
+ Port input data bit (y =
+ 0..15)
+ 9
+ 1
+
+
+ ID8
+ Port input data bit (y =
+ 0..15)
+ 8
+ 1
+
+
+ ID7
+ Port input data bit (y =
+ 0..15)
+ 7
+ 1
+
+
+ ID6
+ Port input data bit (y =
+ 0..15)
+ 6
+ 1
+
+
+ ID5
+ Port input data bit (y =
+ 0..15)
+ 5
+ 1
+
+
+ ID4
+ Port input data bit (y =
+ 0..15)
+ 4
+ 1
+
+
+ ID3
+ Port input data bit (y =
+ 0..15)
+ 3
+ 1
+
+
+ ID2
+ Port input data bit (y =
+ 0..15)
+ 2
+ 1
+
+
+ ID1
+ Port input data bit (y =
+ 0..15)
+ 1
+ 1
+
+
+ ID0
+ Port input data bit (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ ODR
+ ODR
+ GPIO port output data register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OD15
+ Port output data bit (y =
+ 0..15)
+ 15
+ 1
+
+
+ OD14
+ Port output data bit (y =
+ 0..15)
+ 14
+ 1
+
+
+ OD13
+ Port output data bit (y =
+ 0..15)
+ 13
+ 1
+
+
+ OD12
+ Port output data bit (y =
+ 0..15)
+ 12
+ 1
+
+
+ OD11
+ Port output data bit (y =
+ 0..15)
+ 11
+ 1
+
+
+ OD10
+ Port output data bit (y =
+ 0..15)
+ 10
+ 1
+
+
+ OD9
+ Port output data bit (y =
+ 0..15)
+ 9
+ 1
+
+
+ OD8
+ Port output data bit (y =
+ 0..15)
+ 8
+ 1
+
+
+ OD7
+ Port output data bit (y =
+ 0..15)
+ 7
+ 1
+
+
+ OD6
+ Port output data bit (y =
+ 0..15)
+ 6
+ 1
+
+
+ OD5
+ Port output data bit (y =
+ 0..15)
+ 5
+ 1
+
+
+ OD4
+ Port output data bit (y =
+ 0..15)
+ 4
+ 1
+
+
+ OD3
+ Port output data bit (y =
+ 0..15)
+ 3
+ 1
+
+
+ OD2
+ Port output data bit (y =
+ 0..15)
+ 2
+ 1
+
+
+ OD1
+ Port output data bit (y =
+ 0..15)
+ 1
+ 1
+
+
+ OD0
+ Port output data bit (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ BSRR
+ BSRR
+ GPIO port bit set/reset
+ register
+ 0x18
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BR15
+ Port x reset bit y (y =
+ 0..15)
+ 31
+ 1
+
+
+ BR14
+ Port x reset bit y (y =
+ 0..15)
+ 30
+ 1
+
+
+ BR13
+ Port x reset bit y (y =
+ 0..15)
+ 29
+ 1
+
+
+ BR12
+ Port x reset bit y (y =
+ 0..15)
+ 28
+ 1
+
+
+ BR11
+ Port x reset bit y (y =
+ 0..15)
+ 27
+ 1
+
+
+ BR10
+ Port x reset bit y (y =
+ 0..15)
+ 26
+ 1
+
+
+ BR9
+ Port x reset bit y (y =
+ 0..15)
+ 25
+ 1
+
+
+ BR8
+ Port x reset bit y (y =
+ 0..15)
+ 24
+ 1
+
+
+ BR7
+ Port x reset bit y (y =
+ 0..15)
+ 23
+ 1
+
+
+ BR6
+ Port x reset bit y (y =
+ 0..15)
+ 22
+ 1
+
+
+ BR5
+ Port x reset bit y (y =
+ 0..15)
+ 21
+ 1
+
+
+ BR4
+ Port x reset bit y (y =
+ 0..15)
+ 20
+ 1
+
+
+ BR3
+ Port x reset bit y (y =
+ 0..15)
+ 19
+ 1
+
+
+ BR2
+ Port x reset bit y (y =
+ 0..15)
+ 18
+ 1
+
+
+ BR1
+ Port x reset bit y (y =
+ 0..15)
+ 17
+ 1
+
+
+ BR0
+ Port x reset bit y (y =
+ 0..15)
+ 16
+ 1
+
+
+ BS15
+ Port x set bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ BS14
+ Port x set bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ BS13
+ Port x set bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ BS12
+ Port x set bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ BS11
+ Port x set bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ BS10
+ Port x set bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ BS9
+ Port x set bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ BS8
+ Port x set bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ BS7
+ Port x set bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ BS6
+ Port x set bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ BS5
+ Port x set bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ BS4
+ Port x set bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ BS3
+ Port x set bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ BS2
+ Port x set bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ BS1
+ Port x set bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ BS0
+ Port x set bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ LCKR
+ LCKR
+ GPIO port configuration lock
+ register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LCKK
+ Port x lock bit y (y=
+ 0..15)
+ 16
+ 1
+
+
+ LCK15
+ Port x lock bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ LCK14
+ Port x lock bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ LCK13
+ Port x lock bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ LCK12
+ Port x lock bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ LCK11
+ Port x lock bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ LCK10
+ Port x lock bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ LCK9
+ Port x lock bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ LCK8
+ Port x lock bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ LCK7
+ Port x lock bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ LCK6
+ Port x lock bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ LCK5
+ Port x lock bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ LCK4
+ Port x lock bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ LCK3
+ Port x lock bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ LCK2
+ Port x lock bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ LCK1
+ Port x lock bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ LCK0
+ Port x lock bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ AFRL
+ AFRL
+ GPIO alternate function low
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AFSEL7
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 28
+ 4
+
+
+ AFSEL6
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 24
+ 4
+
+
+ AFSEL5
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 20
+ 4
+
+
+ AFSEL4
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 16
+ 4
+
+
+ AFSEL3
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 12
+ 4
+
+
+ AFSEL2
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 8
+ 4
+
+
+ AFSEL1
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 4
+ 4
+
+
+ AFSEL0
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 0
+ 4
+
+
+
+
+ AFRH
+ AFRH
+ GPIO alternate function high
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AFSEL15
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 28
+ 4
+
+
+ AFSEL14
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 24
+ 4
+
+
+ AFSEL13
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 20
+ 4
+
+
+ AFSEL12
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 16
+ 4
+
+
+ AFSEL11
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 12
+ 4
+
+
+ AFSEL10
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 8
+ 4
+
+
+ AFSEL9
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 4
+ 4
+
+
+ AFSEL8
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 0
+ 4
+
+
+
+
+ BRR
+ BRR
+ GPIO port bit reset register
+ 0x28
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BR15
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 15
+ 1
+
+
+ BR14
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 14
+ 1
+
+
+ BR13
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 13
+ 1
+
+
+ BR12
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 12
+ 1
+
+
+ BR11
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 11
+ 1
+
+
+ BR10
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 10
+ 1
+
+
+ BR9
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 9
+ 1
+
+
+ BR8
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 8
+ 1
+
+
+ BR7
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 7
+ 1
+
+
+ BR6
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 6
+ 1
+
+
+ BR5
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 5
+ 1
+
+
+ BR4
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 4
+ 1
+
+
+ BR3
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 3
+ 1
+
+
+ BR2
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 2
+ 1
+
+
+ BR1
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 1
+ 1
+
+
+ BR0
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 0
+ 1
+
+
+
+
+
+
+ GPIOB
+ General-purpose I/Os
+ GPIO
+ 0x50000400
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ MODER
+ MODER
+ GPIO port mode register
+ 0x0
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ MODE15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ MODE14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ MODE13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ MODE12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ MODE11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ MODE10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ MODE9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ MODE8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ MODE7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ MODE6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ MODE5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ MODE4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ MODE3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ MODE2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ MODE1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ MODE0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ OTYPER
+ OTYPER
+ GPIO port output type register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OT15
+ Port x configuration bits (y =
+ 0..15)
+ 15
+ 1
+
+
+ OT14
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 1
+
+
+ OT13
+ Port x configuration bits (y =
+ 0..15)
+ 13
+ 1
+
+
+ OT12
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 1
+
+
+ OT11
+ Port x configuration bits (y =
+ 0..15)
+ 11
+ 1
+
+
+ OT10
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 1
+
+
+ OT9
+ Port x configuration bits (y =
+ 0..15)
+ 9
+ 1
+
+
+ OT8
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 1
+
+
+ OT7
+ Port x configuration bits (y =
+ 0..15)
+ 7
+ 1
+
+
+ OT6
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 1
+
+
+ OT5
+ Port x configuration bits (y =
+ 0..15)
+ 5
+ 1
+
+
+ OT4
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 1
+
+
+ OT3
+ Port x configuration bits (y =
+ 0..15)
+ 3
+ 1
+
+
+ OT2
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 1
+
+
+ OT1
+ Port x configuration bits (y =
+ 0..15)
+ 1
+ 1
+
+
+ OT0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ OSPEEDR
+ OSPEEDR
+ GPIO port output speed
+ register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OSPEED15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ OSPEED14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ OSPEED13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ OSPEED12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ OSPEED11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ OSPEED10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ OSPEED9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ OSPEED8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ OSPEED7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ OSPEED6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ OSPEED5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ OSPEED4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ OSPEED3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ OSPEED2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ OSPEED1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ OSPEED0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ PUPDR
+ PUPDR
+ GPIO port pull-up/pull-down
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PUPD15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ PUPD14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ PUPD13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ PUPD12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ PUPD11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ PUPD10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ PUPD9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ PUPD8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ PUPD7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ PUPD6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ PUPD5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ PUPD4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ PUPD3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ PUPD2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ PUPD1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ PUPD0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ IDR
+ IDR
+ GPIO port input data register
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ ID15
+ Port input data bit (y =
+ 0..15)
+ 15
+ 1
+
+
+ ID14
+ Port input data bit (y =
+ 0..15)
+ 14
+ 1
+
+
+ ID13
+ Port input data bit (y =
+ 0..15)
+ 13
+ 1
+
+
+ ID12
+ Port input data bit (y =
+ 0..15)
+ 12
+ 1
+
+
+ ID11
+ Port input data bit (y =
+ 0..15)
+ 11
+ 1
+
+
+ ID10
+ Port input data bit (y =
+ 0..15)
+ 10
+ 1
+
+
+ ID9
+ Port input data bit (y =
+ 0..15)
+ 9
+ 1
+
+
+ ID8
+ Port input data bit (y =
+ 0..15)
+ 8
+ 1
+
+
+ ID7
+ Port input data bit (y =
+ 0..15)
+ 7
+ 1
+
+
+ ID6
+ Port input data bit (y =
+ 0..15)
+ 6
+ 1
+
+
+ ID5
+ Port input data bit (y =
+ 0..15)
+ 5
+ 1
+
+
+ ID4
+ Port input data bit (y =
+ 0..15)
+ 4
+ 1
+
+
+ ID3
+ Port input data bit (y =
+ 0..15)
+ 3
+ 1
+
+
+ ID2
+ Port input data bit (y =
+ 0..15)
+ 2
+ 1
+
+
+ ID1
+ Port input data bit (y =
+ 0..15)
+ 1
+ 1
+
+
+ ID0
+ Port input data bit (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ ODR
+ ODR
+ GPIO port output data register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OD15
+ Port output data bit (y =
+ 0..15)
+ 15
+ 1
+
+
+ OD14
+ Port output data bit (y =
+ 0..15)
+ 14
+ 1
+
+
+ OD13
+ Port output data bit (y =
+ 0..15)
+ 13
+ 1
+
+
+ OD12
+ Port output data bit (y =
+ 0..15)
+ 12
+ 1
+
+
+ OD11
+ Port output data bit (y =
+ 0..15)
+ 11
+ 1
+
+
+ OD10
+ Port output data bit (y =
+ 0..15)
+ 10
+ 1
+
+
+ OD9
+ Port output data bit (y =
+ 0..15)
+ 9
+ 1
+
+
+ OD8
+ Port output data bit (y =
+ 0..15)
+ 8
+ 1
+
+
+ OD7
+ Port output data bit (y =
+ 0..15)
+ 7
+ 1
+
+
+ OD6
+ Port output data bit (y =
+ 0..15)
+ 6
+ 1
+
+
+ OD5
+ Port output data bit (y =
+ 0..15)
+ 5
+ 1
+
+
+ OD4
+ Port output data bit (y =
+ 0..15)
+ 4
+ 1
+
+
+ OD3
+ Port output data bit (y =
+ 0..15)
+ 3
+ 1
+
+
+ OD2
+ Port output data bit (y =
+ 0..15)
+ 2
+ 1
+
+
+ OD1
+ Port output data bit (y =
+ 0..15)
+ 1
+ 1
+
+
+ OD0
+ Port output data bit (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ BSRR
+ BSRR
+ GPIO port bit set/reset
+ register
+ 0x18
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BR15
+ Port x reset bit y (y =
+ 0..15)
+ 31
+ 1
+
+
+ BR14
+ Port x reset bit y (y =
+ 0..15)
+ 30
+ 1
+
+
+ BR13
+ Port x reset bit y (y =
+ 0..15)
+ 29
+ 1
+
+
+ BR12
+ Port x reset bit y (y =
+ 0..15)
+ 28
+ 1
+
+
+ BR11
+ Port x reset bit y (y =
+ 0..15)
+ 27
+ 1
+
+
+ BR10
+ Port x reset bit y (y =
+ 0..15)
+ 26
+ 1
+
+
+ BR9
+ Port x reset bit y (y =
+ 0..15)
+ 25
+ 1
+
+
+ BR8
+ Port x reset bit y (y =
+ 0..15)
+ 24
+ 1
+
+
+ BR7
+ Port x reset bit y (y =
+ 0..15)
+ 23
+ 1
+
+
+ BR6
+ Port x reset bit y (y =
+ 0..15)
+ 22
+ 1
+
+
+ BR5
+ Port x reset bit y (y =
+ 0..15)
+ 21
+ 1
+
+
+ BR4
+ Port x reset bit y (y =
+ 0..15)
+ 20
+ 1
+
+
+ BR3
+ Port x reset bit y (y =
+ 0..15)
+ 19
+ 1
+
+
+ BR2
+ Port x reset bit y (y =
+ 0..15)
+ 18
+ 1
+
+
+ BR1
+ Port x reset bit y (y =
+ 0..15)
+ 17
+ 1
+
+
+ BR0
+ Port x reset bit y (y =
+ 0..15)
+ 16
+ 1
+
+
+ BS15
+ Port x set bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ BS14
+ Port x set bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ BS13
+ Port x set bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ BS12
+ Port x set bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ BS11
+ Port x set bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ BS10
+ Port x set bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ BS9
+ Port x set bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ BS8
+ Port x set bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ BS7
+ Port x set bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ BS6
+ Port x set bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ BS5
+ Port x set bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ BS4
+ Port x set bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ BS3
+ Port x set bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ BS2
+ Port x set bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ BS1
+ Port x set bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ BS0
+ Port x set bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ LCKR
+ LCKR
+ GPIO port configuration lock
+ register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LCKK
+ Port x lock bit y (y=
+ 0..15)
+ 16
+ 1
+
+
+ LCK15
+ Port x lock bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ LCK14
+ Port x lock bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ LCK13
+ Port x lock bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ LCK12
+ Port x lock bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ LCK11
+ Port x lock bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ LCK10
+ Port x lock bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ LCK9
+ Port x lock bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ LCK8
+ Port x lock bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ LCK7
+ Port x lock bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ LCK6
+ Port x lock bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ LCK5
+ Port x lock bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ LCK4
+ Port x lock bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ LCK3
+ Port x lock bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ LCK2
+ Port x lock bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ LCK1
+ Port x lock bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ LCK0
+ Port x lock bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ AFRL
+ AFRL
+ GPIO alternate function low
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AFSEL7
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 28
+ 4
+
+
+ AFSEL6
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 24
+ 4
+
+
+ AFSEL5
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 20
+ 4
+
+
+ AFSEL4
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 16
+ 4
+
+
+ AFSEL3
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 12
+ 4
+
+
+ AFSEL2
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 8
+ 4
+
+
+ AFSEL1
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 4
+ 4
+
+
+ AFSEL0
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 0
+ 4
+
+
+
+
+ AFRH
+ AFRH
+ GPIO alternate function high
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AFSEL15
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 28
+ 4
+
+
+ AFSEL14
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 24
+ 4
+
+
+ AFSEL13
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 20
+ 4
+
+
+ AFSEL12
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 16
+ 4
+
+
+ AFSEL11
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 12
+ 4
+
+
+ AFSEL10
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 8
+ 4
+
+
+ AFSEL9
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 4
+ 4
+
+
+ AFSEL8
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 0
+ 4
+
+
+
+
+ BRR
+ BRR
+ GPIO port bit reset register
+ 0x28
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BR15
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 15
+ 1
+
+
+ BR14
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 14
+ 1
+
+
+ BR13
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 13
+ 1
+
+
+ BR12
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 12
+ 1
+
+
+ BR11
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 11
+ 1
+
+
+ BR10
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 10
+ 1
+
+
+ BR9
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 9
+ 1
+
+
+ BR8
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 8
+ 1
+
+
+ BR7
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 7
+ 1
+
+
+ BR6
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 6
+ 1
+
+
+ BR5
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 5
+ 1
+
+
+ BR4
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 4
+ 1
+
+
+ BR3
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 3
+ 1
+
+
+ BR2
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 2
+ 1
+
+
+ BR1
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 1
+ 1
+
+
+ BR0
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 0
+ 1
+
+
+
+
+
+
+ GPIOC
+ 0x50000800
+
+
+ GPIOD
+ 0x50000C00
+
+
+ GPIOH
+ 0x50001C00
+
+
+ GPIOE
+ 0x50001000
+
+
+ LPTIM
+ Low power timer
+ LPTIM
+ 0x40007C00
+
+ 0x0
+ 0x400
+ registers
+
+
+ LPTIM1
+ LPTIMER1 interrupt through
+ EXTI29
+ 13
+
+
+
+ ISR
+ ISR
+ Interrupt and Status Register
+ 0x0
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DOWN
+ Counter direction change up to
+ down
+ 6
+ 1
+
+
+ UP
+ Counter direction change down to
+ up
+ 5
+ 1
+
+
+ ARROK
+ Autoreload register update
+ OK
+ 4
+ 1
+
+
+ CMPOK
+ Compare register update OK
+ 3
+ 1
+
+
+ EXTTRIG
+ External trigger edge
+ event
+ 2
+ 1
+
+
+ ARRM
+ Autoreload match
+ 1
+ 1
+
+
+ CMPM
+ Compare match
+ 0
+ 1
+
+
+
+
+ ICR
+ ICR
+ Interrupt Clear Register
+ 0x4
+ 0x20
+ write-only
+ 0x00000000
+
+
+ DOWNCF
+ Direction change to down Clear
+ Flag
+ 6
+ 1
+
+
+ UPCF
+ Direction change to UP Clear
+ Flag
+ 5
+ 1
+
+
+ ARROKCF
+ Autoreload register update OK Clear
+ Flag
+ 4
+ 1
+
+
+ CMPOKCF
+ Compare register update OK Clear
+ Flag
+ 3
+ 1
+
+
+ EXTTRIGCF
+ External trigger valid edge Clear
+ Flag
+ 2
+ 1
+
+
+ ARRMCF
+ Autoreload match Clear
+ Flag
+ 1
+ 1
+
+
+ CMPMCF
+ compare match Clear Flag
+ 0
+ 1
+
+
+
+
+ IER
+ IER
+ Interrupt Enable Register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DOWNIE
+ Direction change to down Interrupt
+ Enable
+ 6
+ 1
+
+
+ UPIE
+ Direction change to UP Interrupt
+ Enable
+ 5
+ 1
+
+
+ ARROKIE
+ Autoreload register update OK Interrupt
+ Enable
+ 4
+ 1
+
+
+ CMPOKIE
+ Compare register update OK Interrupt
+ Enable
+ 3
+ 1
+
+
+ EXTTRIGIE
+ External trigger valid edge Interrupt
+ Enable
+ 2
+ 1
+
+
+ ARRMIE
+ Autoreload match Interrupt
+ Enable
+ 1
+ 1
+
+
+ CMPMIE
+ Compare match Interrupt
+ Enable
+ 0
+ 1
+
+
+
+
+ CFGR
+ CFGR
+ Configuration Register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ENC
+ Encoder mode enable
+ 24
+ 1
+
+
+ COUNTMODE
+ counter mode enabled
+ 23
+ 1
+
+
+ PRELOAD
+ Registers update mode
+ 22
+ 1
+
+
+ WAVPOL
+ Waveform shape polarity
+ 21
+ 1
+
+
+ WAVE
+ Waveform shape
+ 20
+ 1
+
+
+ TIMOUT
+ Timeout enable
+ 19
+ 1
+
+
+ TRIGEN
+ Trigger enable and
+ polarity
+ 17
+ 2
+
+
+ TRIGSEL
+ Trigger selector
+ 13
+ 3
+
+
+ PRESC
+ Clock prescaler
+ 9
+ 3
+
+
+ TRGFLT
+ Configurable digital filter for
+ trigger
+ 6
+ 2
+
+
+ CKFLT
+ Configurable digital filter for external
+ clock
+ 3
+ 2
+
+
+ CKPOL
+ Clock Polarity
+ 1
+ 2
+
+
+ CKSEL
+ Clock selector
+ 0
+ 1
+
+
+
+
+ CR
+ CR
+ Control Register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNTSTRT
+ Timer start in continuous
+ mode
+ 2
+ 1
+
+
+ SNGSTRT
+ LPTIM start in single mode
+ 1
+ 1
+
+
+ ENABLE
+ LPTIM Enable
+ 0
+ 1
+
+
+
+
+ CMP
+ CMP
+ Compare Register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CMP
+ Compare value.
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ Autoreload Register
+ 0x18
+ 0x20
+ read-write
+ 0x00000001
+
+
+ ARR
+ Auto reload value.
+ 0
+ 16
+
+
+
+
+ CNT
+ CNT
+ Counter Register
+ 0x1C
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CNT
+ Counter value.
+ 0
+ 16
+
+
+
+
+
+
+ RNG
+ Random number generator
+ RNG
+ 0x40025000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CR
+ CR
+ control register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IE
+ Interrupt enable
+ 3
+ 1
+
+
+ RNGEN
+ Random number generator
+ enable
+ 2
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x4
+ 0x20
+ 0x00000000
+
+
+ SEIS
+ Seed error interrupt
+ status
+ 6
+ 1
+ read-write
+
+
+ CEIS
+ Clock error interrupt
+ status
+ 5
+ 1
+ read-write
+
+
+ SECS
+ Seed error current status
+ 2
+ 1
+ read-only
+
+
+ CECS
+ Clock error current status
+ 1
+ 1
+ read-only
+
+
+ DRDY
+ Data ready
+ 0
+ 1
+ read-only
+
+
+
+
+ DR
+ DR
+ data register
+ 0x8
+ 0x20
+ read-only
+ 0x00000000
+
+
+ RNDATA
+ Random data
+ 0
+ 32
+
+
+
+
+
+
+ RTC
+ Real-time clock
+ RTC
+ 0x40002800
+
+ 0x0
+ 0x400
+ registers
+
+
+ RTC
+ RTC global interrupt
+ 2
+
+
+
+ TR
+ TR
+ RTC time register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PM
+ AM/PM notation
+ 22
+ 1
+
+
+ HT
+ Hour tens in BCD format
+ 20
+ 2
+
+
+ HU
+ Hour units in BCD format
+ 16
+ 4
+
+
+ MNT
+ Minute tens in BCD format
+ 12
+ 3
+
+
+ MNU
+ Minute units in BCD format
+ 8
+ 4
+
+
+ ST
+ Second tens in BCD format
+ 4
+ 3
+
+
+ SU
+ Second units in BCD format
+ 0
+ 4
+
+
+
+
+ DR
+ DR
+ RTC date register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ YT
+ Year tens in BCD format
+ 20
+ 4
+
+
+ YU
+ Year units in BCD format
+ 16
+ 4
+
+
+ WDU
+ Week day units
+ 13
+ 3
+
+
+ MT
+ Month tens in BCD format
+ 12
+ 1
+
+
+ MU
+ Month units in BCD format
+ 8
+ 4
+
+
+ DT
+ Date tens in BCD format
+ 4
+ 2
+
+
+ DU
+ Date units in BCD format
+ 0
+ 4
+
+
+
+
+ CR
+ CR
+ RTC control register
+ 0x8
+ 0x20
+ 0x00000000
+
+
+ COE
+ Calibration output enable
+ 23
+ 1
+ read-write
+
+
+ OSEL
+ Output selection
+ 21
+ 2
+ read-write
+
+
+ POL
+ Output polarity
+ 20
+ 1
+ read-write
+
+
+ COSEL
+ Calibration output
+ selection
+ 19
+ 1
+ read-write
+
+
+ BKP
+ Backup
+ 18
+ 1
+ read-write
+
+
+ SUB1H
+ Subtract 1 hour (winter time
+ change)
+ 17
+ 1
+ write-only
+
+
+ ADD1H
+ Add 1 hour (summer time
+ change)
+ 16
+ 1
+ write-only
+
+
+ TSIE
+ Time-stamp interrupt
+ enable
+ 15
+ 1
+ read-write
+
+
+ WUTIE
+ Wakeup timer interrupt
+ enable
+ 14
+ 1
+ read-write
+
+
+ ALRBIE
+ Alarm B interrupt enable
+ 13
+ 1
+ read-write
+
+
+ ALRAIE
+ Alarm A interrupt enable
+ 12
+ 1
+ read-write
+
+
+ TSE
+ timestamp enable
+ 11
+ 1
+ read-write
+
+
+ WUTE
+ Wakeup timer enable
+ 10
+ 1
+ read-write
+
+
+ ALRBE
+ Alarm B enable
+ 9
+ 1
+ read-write
+
+
+ ALRAE
+ Alarm A enable
+ 8
+ 1
+ read-write
+
+
+ FMT
+ Hour format
+ 6
+ 1
+ read-write
+
+
+ BYPSHAD
+ Bypass the shadow
+ registers
+ 5
+ 1
+ read-write
+
+
+ REFCKON
+ RTC_REFIN reference clock detection
+ enable (50 or 60 Hz)
+ 4
+ 1
+ read-write
+
+
+ TSEDGE
+ Time-stamp event active
+ edge
+ 3
+ 1
+ read-write
+
+
+ WUCKSEL
+ Wakeup clock selection
+ 0
+ 3
+ read-write
+
+
+
+
+ ISR
+ ISR
+ RTC initialization and status
+ register
+ 0xC
+ 0x20
+ 0x00000000
+
+
+ TAMP2F
+ RTC_TAMP2 detection flag
+ 14
+ 1
+ read-write
+
+
+ TAMP1F
+ RTC_TAMP1 detection flag
+ 13
+ 1
+ read-write
+
+
+ TSOVF
+ Time-stamp overflow flag
+ 12
+ 1
+ read-write
+
+
+ TSF
+ Time-stamp flag
+ 11
+ 1
+ read-write
+
+
+ WUTF
+ Wakeup timer flag
+ 10
+ 1
+ read-write
+
+
+ ALRBF
+ Alarm B flag
+ 9
+ 1
+ read-write
+
+
+ ALRAF
+ Alarm A flag
+ 8
+ 1
+ read-write
+
+
+ INIT
+ Initialization mode
+ 7
+ 1
+ read-write
+
+
+ INITF
+ Initialization flag
+ 6
+ 1
+ read-only
+
+
+ RSF
+ Registers synchronization
+ flag
+ 5
+ 1
+ read-write
+
+
+ INITS
+ Initialization status flag
+ 4
+ 1
+ read-only
+
+
+ SHPF
+ Shift operation pending
+ 3
+ 1
+ read-only
+
+
+ WUTWF
+ Wakeup timer write flag
+ 2
+ 1
+ read-only
+
+
+ ALRBWF
+ Alarm B write flag
+ 1
+ 1
+ read-only
+
+
+ ALRAWF
+ Alarm A write flag
+ 0
+ 1
+ read-only
+
+
+
+
+ PRER
+ PRER
+ RTC prescaler register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PREDIV_A
+ Asynchronous prescaler
+ factor
+ 16
+ 7
+
+
+ PREDIV_S
+ Synchronous prescaler
+ factor
+ 0
+ 16
+
+
+
+
+ WUTR
+ WUTR
+ RTC wakeup timer register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ WUT
+ Wakeup auto-reload value
+ bits
+ 0
+ 16
+
+
+
+
+ ALRMAR
+ ALRMAR
+ RTC alarm A register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MSK4
+ Alarm A date mask
+ 31
+ 1
+
+
+ WDSEL
+ Week day selection
+ 30
+ 1
+
+
+ DT
+ Date tens in BCD format.
+ 28
+ 2
+
+
+ DU
+ Date units or day in BCD
+ format.
+ 24
+ 4
+
+
+ MSK3
+ Alarm A hours mask
+ 23
+ 1
+
+
+ PM
+ AM/PM notation
+ 22
+ 1
+
+
+ HT
+ Hour tens in BCD format.
+ 20
+ 2
+
+
+ HU
+ Hour units in BCD format.
+ 16
+ 4
+
+
+ MSK2
+ Alarm A minutes mask
+ 15
+ 1
+
+
+ MNT
+ Minute tens in BCD format.
+ 12
+ 3
+
+
+ MNU
+ Minute units in BCD
+ format.
+ 8
+ 4
+
+
+ MSK1
+ Alarm A seconds mask
+ 7
+ 1
+
+
+ ST
+ Second tens in BCD format.
+ 4
+ 3
+
+
+ SU
+ Second units in BCD
+ format.
+ 0
+ 4
+
+
+
+
+ ALRMBR
+ ALRMBR
+ RTC alarm B register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MSK4
+ Alarm B date mask
+ 31
+ 1
+
+
+ WDSEL
+ Week day selection
+ 30
+ 1
+
+
+ DT
+ Date tens in BCD format
+ 28
+ 2
+
+
+ DU
+ Date units or day in BCD
+ format
+ 24
+ 4
+
+
+ MSK3
+ Alarm B hours mask
+ 23
+ 1
+
+
+ PM
+ AM/PM notation
+ 22
+ 1
+
+
+ HT
+ Hour tens in BCD format
+ 20
+ 2
+
+
+ HU
+ Hour units in BCD format
+ 16
+ 4
+
+
+ MSK2
+ Alarm B minutes mask
+ 15
+ 1
+
+
+ MNT
+ Minute tens in BCD format
+ 12
+ 3
+
+
+ MNU
+ Minute units in BCD format
+ 8
+ 4
+
+
+ MSK1
+ Alarm B seconds mask
+ 7
+ 1
+
+
+ ST
+ Second tens in BCD format
+ 4
+ 3
+
+
+ SU
+ Second units in BCD format
+ 0
+ 4
+
+
+
+
+ WPR
+ WPR
+ write protection register
+ 0x24
+ 0x20
+ write-only
+ 0x00000000
+
+
+ KEY
+ Write protection key
+ 0
+ 8
+
+
+
+
+ SSR
+ SSR
+ RTC sub second register
+ 0x28
+ 0x20
+ read-only
+ 0x00000000
+
+
+ SS
+ Sub second value
+ 0
+ 16
+
+
+
+
+ SHIFTR
+ SHIFTR
+ RTC shift control register
+ 0x2C
+ 0x20
+ write-only
+ 0x00000000
+
+
+ ADD1S
+ Add one second
+ 31
+ 1
+
+
+ SUBFS
+ Subtract a fraction of a
+ second
+ 0
+ 15
+
+
+
+
+ TSTR
+ TSTR
+ RTC timestamp time register
+ 0x30
+ 0x20
+ read-only
+ 0x00000000
+
+
+ PM
+ AM/PM notation
+ 22
+ 1
+
+
+ HT
+ Hour tens in BCD format.
+ 20
+ 2
+
+
+ HU
+ Hour units in BCD format.
+ 16
+ 4
+
+
+ MNT
+ Minute tens in BCD format.
+ 12
+ 3
+
+
+ MNU
+ Minute units in BCD
+ format.
+ 8
+ 4
+
+
+ ST
+ Second tens in BCD format.
+ 4
+ 3
+
+
+ SU
+ Second units in BCD
+ format.
+ 0
+ 4
+
+
+
+
+ TSDR
+ TSDR
+ RTC timestamp date register
+ 0x34
+ 0x20
+ read-only
+ 0x00000000
+
+
+ WDU
+ Week day units
+ 13
+ 3
+
+
+ MT
+ Month tens in BCD format
+ 12
+ 1
+
+
+ MU
+ Month units in BCD format
+ 8
+ 4
+
+
+ DT
+ Date tens in BCD format
+ 4
+ 2
+
+
+ DU
+ Date units in BCD format
+ 0
+ 4
+
+
+
+
+ TSSSR
+ TSSSR
+ RTC time-stamp sub second
+ register
+ 0x38
+ 0x20
+ read-only
+ 0x00000000
+
+
+ SS
+ Sub second value
+ 0
+ 16
+
+
+
+
+ CALR
+ CALR
+ RTC calibration register
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CALP
+ Increase frequency of RTC by 488.5
+ ppm
+ 15
+ 1
+
+
+ CALW8
+ Use a 8-second calibration cycle
+ period
+ 14
+ 1
+
+
+ CALW16
+ Use a 16-second calibration cycle
+ period
+ 13
+ 1
+
+
+ CALM
+ Calibration minus
+ 0
+ 9
+
+
+
+
+ TAMPCR
+ TAMPCR
+ RTC tamper configuration
+ register
+ 0x40
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TAMP2MF
+ Tamper 2 mask flag
+ 21
+ 1
+
+
+ TAMP2NOERASE
+ Tamper 2 no erase
+ 20
+ 1
+
+
+ TAMP2IE
+ Tamper 2 interrupt enable
+ 19
+ 1
+
+
+ TAMP1MF
+ Tamper 1 mask flag
+ 18
+ 1
+
+
+ TAMP1NOERASE
+ Tamper 1 no erase
+ 17
+ 1
+
+
+ TAMP1IE
+ Tamper 1 interrupt enable
+ 16
+ 1
+
+
+ TAMPPUDIS
+ RTC_TAMPx pull-up disable
+ 15
+ 1
+
+
+ TAMPPRCH
+ RTC_TAMPx precharge
+ duration
+ 13
+ 2
+
+
+ TAMPFLT
+ RTC_TAMPx filter count
+ 11
+ 2
+
+
+ TAMPFREQ
+ Tamper sampling frequency
+ 8
+ 3
+
+
+ TAMPTS
+ Activate timestamp on tamper detection
+ event
+ 7
+ 1
+
+
+ TAMP2_TRG
+ Active level for RTC_TAMP2
+ input
+ 4
+ 1
+
+
+ TAMP2E
+ RTC_TAMP2 input detection
+ enable
+ 3
+ 1
+
+
+ TAMPIE
+ Tamper interrupt enable
+ 2
+ 1
+
+
+ TAMP1TRG
+ Active level for RTC_TAMP1
+ input
+ 1
+ 1
+
+
+ TAMP1E
+ RTC_TAMP1 input detection
+ enable
+ 0
+ 1
+
+
+
+
+ ALRMASSR
+ ALRMASSR
+ RTC alarm A sub second
+ register
+ 0x44
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MASKSS
+ Mask the most-significant bits starting
+ at this bit
+ 24
+ 4
+
+
+ SS
+ Sub seconds value
+ 0
+ 15
+
+
+
+
+ ALRMBSSR
+ ALRMBSSR
+ RTC alarm B sub second
+ register
+ 0x48
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MASKSS
+ Mask the most-significant bits starting
+ at this bit
+ 24
+ 4
+
+
+ SS
+ Sub seconds value
+ 0
+ 15
+
+
+
+
+ OR
+ OR
+ option register
+ 0x4C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ RTC_OUT_RMP
+ RTC_ALARM on PC13 output
+ type
+ 1
+ 1
+
+
+ RTC_ALARM_TYPE
+ RTC_ALARM on PC13 output
+ type
+ 0
+ 1
+
+
+
+
+ BKP0R
+ BKP0R
+ RTC backup registers
+ 0x50
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP1R
+ BKP1R
+ RTC backup registers
+ 0x54
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP2R
+ BKP2R
+ RTC backup registers
+ 0x58
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP3R
+ BKP3R
+ RTC backup registers
+ 0x5C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP4R
+ BKP4R
+ RTC backup registers
+ 0x60
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+
+
+ USART1
+ Universal synchronous asynchronous receiver
+ transmitter
+ USART
+ 0x40013800
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CR1
+ CR1
+ Control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ M1
+ Word length
+ 28
+ 1
+
+
+ EOBIE
+ End of Block interrupt
+ enable
+ 27
+ 1
+
+
+ RTOIE
+ Receiver timeout interrupt
+ enable
+ 26
+ 1
+
+
+ DEAT4
+ Driver Enable assertion
+ time
+ 25
+ 1
+
+
+ DEAT3
+ DEAT3
+ 24
+ 1
+
+
+ DEAT2
+ DEAT2
+ 23
+ 1
+
+
+ DEAT1
+ DEAT1
+ 22
+ 1
+
+
+ DEAT0
+ DEAT0
+ 21
+ 1
+
+
+ DEDT4
+ Driver Enable de-assertion
+ time
+ 20
+ 1
+
+
+ DEDT3
+ DEDT3
+ 19
+ 1
+
+
+ DEDT2
+ DEDT2
+ 18
+ 1
+
+
+ DEDT1
+ DEDT1
+ 17
+ 1
+
+
+ DEDT0
+ DEDT0
+ 16
+ 1
+
+
+ OVER8
+ Oversampling mode
+ 15
+ 1
+
+
+ CMIE
+ Character match interrupt
+ enable
+ 14
+ 1
+
+
+ MME
+ Mute mode enable
+ 13
+ 1
+
+
+ M0
+ Word length
+ 12
+ 1
+
+
+ WAKE
+ Receiver wakeup method
+ 11
+ 1
+
+
+ PCE
+ Parity control enable
+ 10
+ 1
+
+
+ PS
+ Parity selection
+ 9
+ 1
+
+
+ PEIE
+ PE interrupt enable
+ 8
+ 1
+
+
+ TXEIE
+ interrupt enable
+ 7
+ 1
+
+
+ TCIE
+ Transmission complete interrupt
+ enable
+ 6
+ 1
+
+
+ RXNEIE
+ RXNE interrupt enable
+ 5
+ 1
+
+
+ IDLEIE
+ IDLE interrupt enable
+ 4
+ 1
+
+
+ TE
+ Transmitter enable
+ 3
+ 1
+
+
+ RE
+ Receiver enable
+ 2
+ 1
+
+
+ UESM
+ USART enable in Stop mode
+ 1
+ 1
+
+
+ UE
+ USART enable
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ Control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ ADD4_7
+ Address of the USART node
+ 28
+ 4
+
+
+ ADD0_3
+ Address of the USART node
+ 24
+ 4
+
+
+ RTOEN
+ Receiver timeout enable
+ 23
+ 1
+
+
+ ABRMOD1
+ Auto baud rate mode
+ 22
+ 1
+
+
+ ABRMOD0
+ ABRMOD0
+ 21
+ 1
+
+
+ ABREN
+ Auto baud rate enable
+ 20
+ 1
+
+
+ MSBFIRST
+ Most significant bit first
+ 19
+ 1
+
+
+ TAINV
+ Binary data inversion
+ 18
+ 1
+
+
+ TXINV
+ TX pin active level
+ inversion
+ 17
+ 1
+
+
+ RXINV
+ RX pin active level
+ inversion
+ 16
+ 1
+
+
+ SWAP
+ Swap TX/RX pins
+ 15
+ 1
+
+
+ LINEN
+ LIN mode enable
+ 14
+ 1
+
+
+ STOP
+ STOP bits
+ 12
+ 2
+
+
+ CLKEN
+ Clock enable
+ 11
+ 1
+
+
+ CPOL
+ Clock polarity
+ 10
+ 1
+
+
+ CPHA
+ Clock phase
+ 9
+ 1
+
+
+ LBCL
+ Last bit clock pulse
+ 8
+ 1
+
+
+ LBDIE
+ LIN break detection interrupt
+ enable
+ 6
+ 1
+
+
+ LBDL
+ LIN break detection length
+ 5
+ 1
+
+
+ ADDM7
+ 7-bit Address Detection/4-bit Address
+ Detection
+ 4
+ 1
+
+
+
+
+ CR3
+ CR3
+ Control register 3
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ WUFIE
+ Wakeup from Stop mode interrupt
+ enable
+ 22
+ 1
+
+
+ WUS
+ Wakeup from Stop mode interrupt flag
+ selection
+ 20
+ 2
+
+
+ SCARCNT
+ Smartcard auto-retry count
+ 17
+ 3
+
+
+ DEP
+ Driver enable polarity
+ selection
+ 15
+ 1
+
+
+ DEM
+ Driver enable mode
+ 14
+ 1
+
+
+ DDRE
+ DMA Disable on Reception
+ Error
+ 13
+ 1
+
+
+ OVRDIS
+ Overrun Disable
+ 12
+ 1
+
+
+ ONEBIT
+ One sample bit method
+ enable
+ 11
+ 1
+
+
+ CTSIE
+ CTS interrupt enable
+ 10
+ 1
+
+
+ CTSE
+ CTS enable
+ 9
+ 1
+
+
+ RTSE
+ RTS enable
+ 8
+ 1
+
+
+ DMAT
+ DMA enable transmitter
+ 7
+ 1
+
+
+ DMAR
+ DMA enable receiver
+ 6
+ 1
+
+
+ SCEN
+ Smartcard mode enable
+ 5
+ 1
+
+
+ NACK
+ Smartcard NACK enable
+ 4
+ 1
+
+
+ HDSEL
+ Half-duplex selection
+ 3
+ 1
+
+
+ IRLP
+ Ir low-power
+ 2
+ 1
+
+
+ IREN
+ Ir mode enable
+ 1
+ 1
+
+
+ EIE
+ Error interrupt enable
+ 0
+ 1
+
+
+
+
+ BRR
+ BRR
+ Baud rate register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ DIV_Mantissa
+ DIV_Mantissa
+ 4
+ 12
+
+
+ DIV_Fraction
+ DIV_Fraction
+ 0
+ 4
+
+
+
+
+ GTPR
+ GTPR
+ Guard time and prescaler
+ register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ GT
+ Guard time value
+ 8
+ 8
+
+
+ PSC
+ Prescaler value
+ 0
+ 8
+
+
+
+
+ RTOR
+ RTOR
+ Receiver timeout register
+ 0x14
+ 0x20
+ read-write
+ 0x0000
+
+
+ BLEN
+ Block Length
+ 24
+ 8
+
+
+ RTO
+ Receiver timeout value
+ 0
+ 24
+
+
+
+
+ RQR
+ RQR
+ Request register
+ 0x18
+ 0x20
+ write-only
+ 0x0000
+
+
+ TXFRQ
+ Transmit data flush
+ request
+ 4
+ 1
+
+
+ RXFRQ
+ Receive data flush request
+ 3
+ 1
+
+
+ MMRQ
+ Mute mode request
+ 2
+ 1
+
+
+ SBKRQ
+ Send break request
+ 1
+ 1
+
+
+ ABRRQ
+ Auto baud rate request
+ 0
+ 1
+
+
+
+
+ ISR
+ ISR
+ Interrupt & status
+ register
+ 0x1C
+ 0x20
+ read-only
+ 0x00C0
+
+
+ REACK
+ REACK
+ 22
+ 1
+
+
+ TEACK
+ TEACK
+ 21
+ 1
+
+
+ WUF
+ WUF
+ 20
+ 1
+
+
+ RWU
+ RWU
+ 19
+ 1
+
+
+ SBKF
+ SBKF
+ 18
+ 1
+
+
+ CMF
+ CMF
+ 17
+ 1
+
+
+ BUSY
+ BUSY
+ 16
+ 1
+
+
+ ABRF
+ ABRF
+ 15
+ 1
+
+
+ ABRE
+ ABRE
+ 14
+ 1
+
+
+ EOBF
+ EOBF
+ 12
+ 1
+
+
+ RTOF
+ RTOF
+ 11
+ 1
+
+
+ CTS
+ CTS
+ 10
+ 1
+
+
+ CTSIF
+ CTSIF
+ 9
+ 1
+
+
+ LBDF
+ LBDF
+ 8
+ 1
+
+
+ TXE
+ TXE
+ 7
+ 1
+
+
+ TC
+ TC
+ 6
+ 1
+
+
+ RXNE
+ RXNE
+ 5
+ 1
+
+
+ IDLE
+ IDLE
+ 4
+ 1
+
+
+ ORE
+ ORE
+ 3
+ 1
+
+
+ NF
+ NF
+ 2
+ 1
+
+
+ FE
+ FE
+ 1
+ 1
+
+
+ PE
+ PE
+ 0
+ 1
+
+
+
+
+ ICR
+ ICR
+ Interrupt flag clear register
+ 0x20
+ 0x20
+ write-only
+ 0x0000
+
+
+ WUCF
+ Wakeup from Stop mode clear
+ flag
+ 20
+ 1
+
+
+ CMCF
+ Character match clear flag
+ 17
+ 1
+
+
+ EOBCF
+ End of block clear flag
+ 12
+ 1
+
+
+ RTOCF
+ Receiver timeout clear
+ flag
+ 11
+ 1
+
+
+ CTSCF
+ CTS clear flag
+ 9
+ 1
+
+
+ LBDCF
+ LIN break detection clear
+ flag
+ 8
+ 1
+
+
+ TCCF
+ Transmission complete clear
+ flag
+ 6
+ 1
+
+
+ IDLECF
+ Idle line detected clear
+ flag
+ 4
+ 1
+
+
+ ORECF
+ Overrun error clear flag
+ 3
+ 1
+
+
+ NCF
+ Noise detected clear flag
+ 2
+ 1
+
+
+ FECF
+ Framing error clear flag
+ 1
+ 1
+
+
+ PECF
+ Parity error clear flag
+ 0
+ 1
+
+
+
+
+ RDR
+ RDR
+ Receive data register
+ 0x24
+ 0x20
+ read-only
+ 0x0000
+
+
+ RDR
+ Receive data value
+ 0
+ 9
+
+
+
+
+ TDR
+ TDR
+ Transmit data register
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ TDR
+ Transmit data value
+ 0
+ 9
+
+
+
+
+
+
+ USART2
+ 0x40004400
+
+
+ USART4
+ 0x40004C00
+
+ USART4_USART5
+ USART4/USART5 global interrupt
+ 14
+
+
+ USART1
+ USART1 global interrupt
+ 27
+
+
+
+ USART5
+ 0x40005000
+
+ USART2
+ USART2 global interrupt
+ 28
+
+
+
+ TSC
+ Touch sensing controller
+ TSC
+ 0x40024000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TSC
+ Touch sensing interrupt
+ 8
+
+
+
+ CR
+ CR
+ control register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CTPH
+ Charge transfer pulse high
+ 28
+ 4
+
+
+ CTPL
+ Charge transfer pulse low
+ 24
+ 4
+
+
+ SSD
+ Spread spectrum deviation
+ 17
+ 7
+
+
+ SSE
+ Spread spectrum enable
+ 16
+ 1
+
+
+ SSPSC
+ Spread spectrum prescaler
+ 15
+ 1
+
+
+ PGPSC
+ pulse generator prescaler
+ 12
+ 3
+
+
+ MCV
+ Max count value
+ 5
+ 3
+
+
+ IODEF
+ I/O Default mode
+ 4
+ 1
+
+
+ SYNCPOL
+ Synchronization pin
+ polarity
+ 3
+ 1
+
+
+ AM
+ Acquisition mode
+ 2
+ 1
+
+
+ START
+ Start a new acquisition
+ 1
+ 1
+
+
+ TSCE
+ Touch sensing controller
+ enable
+ 0
+ 1
+
+
+
+
+ IER
+ IER
+ interrupt enable register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MCEIE
+ Max count error interrupt
+ enable
+ 1
+ 1
+
+
+ EOAIE
+ End of acquisition interrupt
+ enable
+ 0
+ 1
+
+
+
+
+ ICR
+ ICR
+ interrupt clear register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MCEIC
+ Max count error interrupt
+ clear
+ 1
+ 1
+
+
+ EOAIC
+ End of acquisition interrupt
+ clear
+ 0
+ 1
+
+
+
+
+ ISR
+ ISR
+ interrupt status register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MCEF
+ Max count error flag
+ 1
+ 1
+
+
+ EOAF
+ End of acquisition flag
+ 0
+ 1
+
+
+
+
+ IOHCR
+ IOHCR
+ I/O hysteresis control
+ register
+ 0x10
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ G8_IO4
+ G8_IO4
+ 31
+ 1
+
+
+ G8_IO3
+ G8_IO3
+ 30
+ 1
+
+
+ G8_IO2
+ G8_IO2
+ 29
+ 1
+
+
+ G8_IO1
+ G8_IO1
+ 28
+ 1
+
+
+ G7_IO4
+ G7_IO4
+ 27
+ 1
+
+
+ G7_IO3
+ G7_IO3
+ 26
+ 1
+
+
+ G7_IO2
+ G7_IO2
+ 25
+ 1
+
+
+ G7_IO1
+ G7_IO1
+ 24
+ 1
+
+
+ G6_IO4
+ G6_IO4
+ 23
+ 1
+
+
+ G6_IO3
+ G6_IO3
+ 22
+ 1
+
+
+ G6_IO2
+ G6_IO2
+ 21
+ 1
+
+
+ G6_IO1
+ G6_IO1
+ 20
+ 1
+
+
+ G5_IO4
+ G5_IO4
+ 19
+ 1
+
+
+ G5_IO3
+ G5_IO3
+ 18
+ 1
+
+
+ G5_IO2
+ G5_IO2
+ 17
+ 1
+
+
+ G5_IO1
+ G5_IO1
+ 16
+ 1
+
+
+ G4_IO4
+ G4_IO4
+ 15
+ 1
+
+
+ G4_IO3
+ G4_IO3
+ 14
+ 1
+
+
+ G4_IO2
+ G4_IO2
+ 13
+ 1
+
+
+ G4_IO1
+ G4_IO1
+ 12
+ 1
+
+
+ G3_IO4
+ G3_IO4
+ 11
+ 1
+
+
+ G3_IO3
+ G3_IO3
+ 10
+ 1
+
+
+ G3_IO2
+ G3_IO2
+ 9
+ 1
+
+
+ G3_IO1
+ G3_IO1
+ 8
+ 1
+
+
+ G2_IO4
+ G2_IO4
+ 7
+ 1
+
+
+ G2_IO3
+ G2_IO3
+ 6
+ 1
+
+
+ G2_IO2
+ G2_IO2
+ 5
+ 1
+
+
+ G2_IO1
+ G2_IO1
+ 4
+ 1
+
+
+ G1_IO4
+ G1_IO4
+ 3
+ 1
+
+
+ G1_IO3
+ G1_IO3
+ 2
+ 1
+
+
+ G1_IO2
+ G1_IO2
+ 1
+ 1
+
+
+ G1_IO1
+ G1_IO1
+ 0
+ 1
+
+
+
+
+ IOASCR
+ IOASCR
+ I/O analog switch control
+ register
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ G8_IO4
+ G8_IO4
+ 31
+ 1
+
+
+ G8_IO3
+ G8_IO3
+ 30
+ 1
+
+
+ G8_IO2
+ G8_IO2
+ 29
+ 1
+
+
+ G8_IO1
+ G8_IO1
+ 28
+ 1
+
+
+ G7_IO4
+ G7_IO4
+ 27
+ 1
+
+
+ G7_IO3
+ G7_IO3
+ 26
+ 1
+
+
+ G7_IO2
+ G7_IO2
+ 25
+ 1
+
+
+ G7_IO1
+ G7_IO1
+ 24
+ 1
+
+
+ G6_IO4
+ G6_IO4
+ 23
+ 1
+
+
+ G6_IO3
+ G6_IO3
+ 22
+ 1
+
+
+ G6_IO2
+ G6_IO2
+ 21
+ 1
+
+
+ G6_IO1
+ G6_IO1
+ 20
+ 1
+
+
+ G5_IO4
+ G5_IO4
+ 19
+ 1
+
+
+ G5_IO3
+ G5_IO3
+ 18
+ 1
+
+
+ G5_IO2
+ G5_IO2
+ 17
+ 1
+
+
+ G5_IO1
+ G5_IO1
+ 16
+ 1
+
+
+ G4_IO4
+ G4_IO4
+ 15
+ 1
+
+
+ G4_IO3
+ G4_IO3
+ 14
+ 1
+
+
+ G4_IO2
+ G4_IO2
+ 13
+ 1
+
+
+ G4_IO1
+ G4_IO1
+ 12
+ 1
+
+
+ G3_IO4
+ G3_IO4
+ 11
+ 1
+
+
+ G3_IO3
+ G3_IO3
+ 10
+ 1
+
+
+ G3_IO2
+ G3_IO2
+ 9
+ 1
+
+
+ G3_IO1
+ G3_IO1
+ 8
+ 1
+
+
+ G2_IO4
+ G2_IO4
+ 7
+ 1
+
+
+ G2_IO3
+ G2_IO3
+ 6
+ 1
+
+
+ G2_IO2
+ G2_IO2
+ 5
+ 1
+
+
+ G2_IO1
+ G2_IO1
+ 4
+ 1
+
+
+ G1_IO4
+ G1_IO4
+ 3
+ 1
+
+
+ G1_IO3
+ G1_IO3
+ 2
+ 1
+
+
+ G1_IO2
+ G1_IO2
+ 1
+ 1
+
+
+ G1_IO1
+ G1_IO1
+ 0
+ 1
+
+
+
+
+ IOSCR
+ IOSCR
+ I/O sampling control register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ G8_IO4
+ G8_IO4
+ 31
+ 1
+
+
+ G8_IO3
+ G8_IO3
+ 30
+ 1
+
+
+ G8_IO2
+ G8_IO2
+ 29
+ 1
+
+
+ G8_IO1
+ G8_IO1
+ 28
+ 1
+
+
+ G7_IO4
+ G7_IO4
+ 27
+ 1
+
+
+ G7_IO3
+ G7_IO3
+ 26
+ 1
+
+
+ G7_IO2
+ G7_IO2
+ 25
+ 1
+
+
+ G7_IO1
+ G7_IO1
+ 24
+ 1
+
+
+ G6_IO4
+ G6_IO4
+ 23
+ 1
+
+
+ G6_IO3
+ G6_IO3
+ 22
+ 1
+
+
+ G6_IO2
+ G6_IO2
+ 21
+ 1
+
+
+ G6_IO1
+ G6_IO1
+ 20
+ 1
+
+
+ G5_IO4
+ G5_IO4
+ 19
+ 1
+
+
+ G5_IO3
+ G5_IO3
+ 18
+ 1
+
+
+ G5_IO2
+ G5_IO2
+ 17
+ 1
+
+
+ G5_IO1
+ G5_IO1
+ 16
+ 1
+
+
+ G4_IO4
+ G4_IO4
+ 15
+ 1
+
+
+ G4_IO3
+ G4_IO3
+ 14
+ 1
+
+
+ G4_IO2
+ G4_IO2
+ 13
+ 1
+
+
+ G4_IO1
+ G4_IO1
+ 12
+ 1
+
+
+ G3_IO4
+ G3_IO4
+ 11
+ 1
+
+
+ G3_IO3
+ G3_IO3
+ 10
+ 1
+
+
+ G3_IO2
+ G3_IO2
+ 9
+ 1
+
+
+ G3_IO1
+ G3_IO1
+ 8
+ 1
+
+
+ G2_IO4
+ G2_IO4
+ 7
+ 1
+
+
+ G2_IO3
+ G2_IO3
+ 6
+ 1
+
+
+ G2_IO2
+ G2_IO2
+ 5
+ 1
+
+
+ G2_IO1
+ G2_IO1
+ 4
+ 1
+
+
+ G1_IO4
+ G1_IO4
+ 3
+ 1
+
+
+ G1_IO3
+ G1_IO3
+ 2
+ 1
+
+
+ G1_IO2
+ G1_IO2
+ 1
+ 1
+
+
+ G1_IO1
+ G1_IO1
+ 0
+ 1
+
+
+
+
+ IOCCR
+ IOCCR
+ I/O channel control register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ G8_IO4
+ G8_IO4
+ 31
+ 1
+
+
+ G8_IO3
+ G8_IO3
+ 30
+ 1
+
+
+ G8_IO2
+ G8_IO2
+ 29
+ 1
+
+
+ G8_IO1
+ G8_IO1
+ 28
+ 1
+
+
+ G7_IO4
+ G7_IO4
+ 27
+ 1
+
+
+ G7_IO3
+ G7_IO3
+ 26
+ 1
+
+
+ G7_IO2
+ G7_IO2
+ 25
+ 1
+
+
+ G7_IO1
+ G7_IO1
+ 24
+ 1
+
+
+ G6_IO4
+ G6_IO4
+ 23
+ 1
+
+
+ G6_IO3
+ G6_IO3
+ 22
+ 1
+
+
+ G6_IO2
+ G6_IO2
+ 21
+ 1
+
+
+ G6_IO1
+ G6_IO1
+ 20
+ 1
+
+
+ G5_IO4
+ G5_IO4
+ 19
+ 1
+
+
+ G5_IO3
+ G5_IO3
+ 18
+ 1
+
+
+ G5_IO2
+ G5_IO2
+ 17
+ 1
+
+
+ G5_IO1
+ G5_IO1
+ 16
+ 1
+
+
+ G4_IO4
+ G4_IO4
+ 15
+ 1
+
+
+ G4_IO3
+ G4_IO3
+ 14
+ 1
+
+
+ G4_IO2
+ G4_IO2
+ 13
+ 1
+
+
+ G4_IO1
+ G4_IO1
+ 12
+ 1
+
+
+ G3_IO4
+ G3_IO4
+ 11
+ 1
+
+
+ G3_IO3
+ G3_IO3
+ 10
+ 1
+
+
+ G3_IO2
+ G3_IO2
+ 9
+ 1
+
+
+ G3_IO1
+ G3_IO1
+ 8
+ 1
+
+
+ G2_IO4
+ G2_IO4
+ 7
+ 1
+
+
+ G2_IO3
+ G2_IO3
+ 6
+ 1
+
+
+ G2_IO2
+ G2_IO2
+ 5
+ 1
+
+
+ G2_IO1
+ G2_IO1
+ 4
+ 1
+
+
+ G1_IO4
+ G1_IO4
+ 3
+ 1
+
+
+ G1_IO3
+ G1_IO3
+ 2
+ 1
+
+
+ G1_IO2
+ G1_IO2
+ 1
+ 1
+
+
+ G1_IO1
+ G1_IO1
+ 0
+ 1
+
+
+
+
+ IOGCSR
+ IOGCSR
+ I/O group control status
+ register
+ 0x30
+ 0x20
+ 0x00000000
+
+
+ G8S
+ Analog I/O group x status
+ 23
+ 1
+ read-only
+
+
+ G7S
+ Analog I/O group x status
+ 22
+ 1
+ read-only
+
+
+ G6S
+ Analog I/O group x status
+ 21
+ 1
+ read-only
+
+
+ G5S
+ Analog I/O group x status
+ 20
+ 1
+ read-only
+
+
+ G4S
+ Analog I/O group x status
+ 19
+ 1
+ read-only
+
+
+ G3S
+ Analog I/O group x status
+ 18
+ 1
+ read-only
+
+
+ G2S
+ Analog I/O group x status
+ 17
+ 1
+ read-only
+
+
+ G1S
+ Analog I/O group x status
+ 16
+ 1
+ read-only
+
+
+ G8E
+ Analog I/O group x enable
+ 7
+ 1
+ read-write
+
+
+ G7E
+ Analog I/O group x enable
+ 6
+ 1
+ read-write
+
+
+ G6E
+ Analog I/O group x enable
+ 5
+ 1
+ read-write
+
+
+ G5E
+ Analog I/O group x enable
+ 4
+ 1
+ read-write
+
+
+ G4E
+ Analog I/O group x enable
+ 3
+ 1
+ read-write
+
+
+ G3E
+ Analog I/O group x enable
+ 2
+ 1
+ read-write
+
+
+ G2E
+ Analog I/O group x enable
+ 1
+ 1
+ read-write
+
+
+ G1E
+ Analog I/O group x enable
+ 0
+ 1
+ read-write
+
+
+
+
+ IOG1CR
+ IOG1CR
+ I/O group x counter register
+ 0x34
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CNT
+ Counter value
+ 0
+ 14
+
+
+
+
+ IOG2CR
+ IOG2CR
+ I/O group x counter register
+ 0x38
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CNT
+ Counter value
+ 0
+ 14
+
+
+
+
+ IOG3CR
+ IOG3CR
+ I/O group x counter register
+ 0x3C
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CNT
+ Counter value
+ 0
+ 14
+
+
+
+
+ IOG4CR
+ IOG4CR
+ I/O group x counter register
+ 0x40
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CNT
+ Counter value
+ 0
+ 14
+
+
+
+
+ IOG5CR
+ IOG5CR
+ I/O group x counter register
+ 0x44
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CNT
+ Counter value
+ 0
+ 14
+
+
+
+
+ IOG6CR
+ IOG6CR
+ I/O group x counter register
+ 0x48
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CNT
+ Counter value
+ 0
+ 14
+
+
+
+
+ IOG7CR
+ IOG7CR
+ I/O group x counter register
+ 0x4C
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CNT
+ Counter value
+ 0
+ 14
+
+
+
+
+ IOG8CR
+ IOG8CR
+ I/O group x counter register
+ 0x50
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CNT
+ Counter value
+ 0
+ 14
+
+
+
+
+
+
+ IWDG
+ Independent watchdog
+ IWDG
+ 0x40003000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ KR
+ KR
+ Key register
+ 0x0
+ 0x20
+ write-only
+ 0x00000000
+
+
+ KEY
+ Key value (write only, read
+ 0x0000)
+ 0
+ 16
+
+
+
+
+ PR
+ PR
+ Prescaler register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PR
+ Prescaler divider
+ 0
+ 3
+
+
+
+
+ RLR
+ RLR
+ Reload register
+ 0x8
+ 0x20
+ read-write
+ 0x00000FFF
+
+
+ RL
+ Watchdog counter reload
+ value
+ 0
+ 12
+
+
+
+
+ SR
+ SR
+ Status register
+ 0xC
+ 0x20
+ read-only
+ 0x00000000
+
+
+ WVU
+ Watchdog counter window value
+ update
+ 2
+ 1
+
+
+ RVU
+ Watchdog counter reload value
+ update
+ 1
+ 1
+
+
+ PVU
+ Watchdog prescaler value
+ update
+ 0
+ 1
+
+
+
+
+ WINR
+ WINR
+ Window register
+ 0x10
+ 0x20
+ read-write
+ 0x00000FFF
+
+
+ WIN
+ Watchdog counter window
+ value
+ 0
+ 12
+
+
+
+
+
+
+ WWDG
+ System window watchdog
+ WWDG
+ 0x40002C00
+
+ 0x0
+ 0x400
+ registers
+
+
+ WWDG
+ Window Watchdog interrupt
+ 0
+
+
+
+ CR
+ CR
+ Control register
+ 0x0
+ 0x20
+ read-write
+ 0x0000007F
+
+
+ WDGA
+ Activation bit
+ 7
+ 1
+
+
+ T
+ 7-bit counter (MSB to LSB)
+ 0
+ 7
+
+
+
+
+ CFR
+ CFR
+ Configuration register
+ 0x4
+ 0x20
+ read-write
+ 0x0000007F
+
+
+ EWI
+ Early wakeup interrupt
+ 9
+ 1
+
+
+ WDGTB1
+ Timer base
+ 8
+ 1
+
+
+ WDGTB0
+ WDGTB0
+ 7
+ 1
+
+
+ W
+ 7-bit window value
+ 0
+ 7
+
+
+
+
+ SR
+ SR
+ Status register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EWIF
+ Early wakeup interrupt
+ flag
+ 0
+ 1
+
+
+
+
+
+
+ USB_FS
+ Universal serial bus full-speed device
+ interface
+ USB
+ 0x40005C00
+
+ 0x0
+ 0x400
+ registers
+
+
+ USB
+ USB event interrupt through
+ EXTI18
+ 31
+
+
+
+ EP0R
+ EP0R
+ endpoint register
+ 0x0
+ 0x20
+ read-write
+ 0x0
+
+
+ CTR_RX
+ CTR_RX
+ 15
+ 1
+
+
+ DTOG_RX
+ DTOG_RX
+ 14
+ 1
+
+
+ STAT_RX
+ STAT_RX
+ 12
+ 2
+
+
+ SETUP
+ SETUP
+ 11
+ 1
+
+
+ EPTYPE
+ EPTYPE
+ 9
+ 2
+
+
+ EP_KIND
+ EP_KIND
+ 8
+ 1
+
+
+ CTR_TX
+ CTR_TX
+ 7
+ 1
+
+
+ DTOG_TX
+ DTOG_TX
+ 6
+ 1
+
+
+ STAT_TX
+ STAT_TX
+ 4
+ 2
+
+
+ EA
+ EA
+ 0
+ 4
+
+
+
+
+ EP1R
+ EP1R
+ endpoint register
+ 0x4
+ 0x20
+ read-write
+ 0x0
+
+
+ CTR_RX
+ CTR_RX
+ 15
+ 1
+
+
+ DTOG_RX
+ DTOG_RX
+ 14
+ 1
+
+
+ STAT_RX
+ STAT_RX
+ 12
+ 2
+
+
+ SETUP
+ SETUP
+ 11
+ 1
+
+
+ EPTYPE
+ EPTYPE
+ 9
+ 2
+
+
+ EP_KIND
+ EP_KIND
+ 8
+ 1
+
+
+ CTR_TX
+ CTR_TX
+ 7
+ 1
+
+
+ DTOG_TX
+ DTOG_TX
+ 6
+ 1
+
+
+ STAT_TX
+ STAT_TX
+ 4
+ 2
+
+
+ EA
+ EA
+ 0
+ 4
+
+
+
+
+ EP2R
+ EP2R
+ endpoint register
+ 0x8
+ 0x20
+ read-write
+ 0x0
+
+
+ CTR_RX
+ CTR_RX
+ 15
+ 1
+
+
+ DTOG_RX
+ DTOG_RX
+ 14
+ 1
+
+
+ STAT_RX
+ STAT_RX
+ 12
+ 2
+
+
+ SETUP
+ SETUP
+ 11
+ 1
+
+
+ EPTYPE
+ EPTYPE
+ 9
+ 2
+
+
+ EP_KIND
+ EP_KIND
+ 8
+ 1
+
+
+ CTR_TX
+ CTR_TX
+ 7
+ 1
+
+
+ DTOG_TX
+ DTOG_TX
+ 6
+ 1
+
+
+ STAT_TX
+ STAT_TX
+ 4
+ 2
+
+
+ EA
+ EA
+ 0
+ 4
+
+
+
+
+ EP3R
+ EP3R
+ endpoint register
+ 0xC
+ 0x20
+ read-write
+ 0x0
+
+
+ CTR_RX
+ CTR_RX
+ 15
+ 1
+
+
+ DTOG_RX
+ DTOG_RX
+ 14
+ 1
+
+
+ STAT_RX
+ STAT_RX
+ 12
+ 2
+
+
+ SETUP
+ SETUP
+ 11
+ 1
+
+
+ EPTYPE
+ EPTYPE
+ 9
+ 2
+
+
+ EP_KIND
+ EP_KIND
+ 8
+ 1
+
+
+ CTR_TX
+ CTR_TX
+ 7
+ 1
+
+
+ DTOG_TX
+ DTOG_TX
+ 6
+ 1
+
+
+ STAT_TX
+ STAT_TX
+ 4
+ 2
+
+
+ EA
+ EA
+ 0
+ 4
+
+
+
+
+ EP4R
+ EP4R
+ endpoint register
+ 0x10
+ 0x20
+ read-write
+ 0x0
+
+
+ CTR_RX
+ CTR_RX
+ 15
+ 1
+
+
+ DTOG_RX
+ DTOG_RX
+ 14
+ 1
+
+
+ STAT_RX
+ STAT_RX
+ 12
+ 2
+
+
+ SETUP
+ SETUP
+ 11
+ 1
+
+
+ EPTYPE
+ EPTYPE
+ 9
+ 2
+
+
+ EP_KIND
+ EP_KIND
+ 8
+ 1
+
+
+ CTR_TX
+ CTR_TX
+ 7
+ 1
+
+
+ DTOG_TX
+ DTOG_TX
+ 6
+ 1
+
+
+ STAT_TX
+ STAT_TX
+ 4
+ 2
+
+
+ EA
+ EA
+ 0
+ 4
+
+
+
+
+ EP5R
+ EP5R
+ endpoint register
+ 0x14
+ 0x20
+ read-write
+ 0x0
+
+
+ CTR_RX
+ CTR_RX
+ 15
+ 1
+
+
+ DTOG_RX
+ DTOG_RX
+ 14
+ 1
+
+
+ STAT_RX
+ STAT_RX
+ 12
+ 2
+
+
+ SETUP
+ SETUP
+ 11
+ 1
+
+
+ EPTYPE
+ EPTYPE
+ 9
+ 2
+
+
+ EP_KIND
+ EP_KIND
+ 8
+ 1
+
+
+ CTR_TX
+ CTR_TX
+ 7
+ 1
+
+
+ DTOG_TX
+ DTOG_TX
+ 6
+ 1
+
+
+ STAT_TX
+ STAT_TX
+ 4
+ 2
+
+
+ EA
+ EA
+ 0
+ 4
+
+
+
+
+ EP6R
+ EP6R
+ endpoint register
+ 0x18
+ 0x20
+ read-write
+ 0x0
+
+
+ CTR_RX
+ CTR_RX
+ 15
+ 1
+
+
+ DTOG_RX
+ DTOG_RX
+ 14
+ 1
+
+
+ STAT_RX
+ STAT_RX
+ 12
+ 2
+
+
+ SETUP
+ SETUP
+ 11
+ 1
+
+
+ EPTYPE
+ EPTYPE
+ 9
+ 2
+
+
+ EP_KIND
+ EP_KIND
+ 8
+ 1
+
+
+ CTR_TX
+ CTR_TX
+ 7
+ 1
+
+
+ DTOG_TX
+ DTOG_TX
+ 6
+ 1
+
+
+ STAT_TX
+ STAT_TX
+ 4
+ 2
+
+
+ EA
+ EA
+ 0
+ 4
+
+
+
+
+ EP7R
+ EP7R
+ endpoint register
+ 0x1C
+ 0x20
+ read-write
+ 0x0
+
+
+ CTR_RX
+ CTR_RX
+ 15
+ 1
+
+
+ DTOG_RX
+ DTOG_RX
+ 14
+ 1
+
+
+ STAT_RX
+ STAT_RX
+ 12
+ 2
+
+
+ SETUP
+ SETUP
+ 11
+ 1
+
+
+ EPTYPE
+ EPTYPE
+ 9
+ 2
+
+
+ EP_KIND
+ EP_KIND
+ 8
+ 1
+
+
+ CTR_TX
+ CTR_TX
+ 7
+ 1
+
+
+ DTOG_TX
+ DTOG_TX
+ 6
+ 1
+
+
+ STAT_TX
+ STAT_TX
+ 4
+ 2
+
+
+ EA
+ EA
+ 0
+ 4
+
+
+
+
+ CNTR
+ CNTR
+ control register
+ 0x40
+ 0x20
+ read-write
+ 0x0
+
+
+ CTRM
+ CTRM
+ 15
+ 1
+
+
+ PMAOVRM
+ PMAOVRM
+ 14
+ 1
+
+
+ ERRM
+ ERRM
+ 13
+ 1
+
+
+ WKUPM
+ WKUPM
+ 12
+ 1
+
+
+ SUSPM
+ SUSPM
+ 11
+ 1
+
+
+ RESETM
+ RESETM
+ 10
+ 1
+
+
+ SOFM
+ SOFM
+ 9
+ 1
+
+
+ ESOFM
+ ESOFM
+ 8
+ 1
+
+
+ L1REQM
+ L1REQM
+ 7
+ 1
+
+
+ L1RESUME
+ L1RESUME
+ 5
+ 1
+
+
+ RESUME
+ RESUME
+ 4
+ 1
+
+
+ FSUSP
+ FSUSP
+ 3
+ 1
+
+
+ LPMODE
+ LPMODE
+ 2
+ 1
+
+
+ PDWN
+ PDWN
+ 1
+ 1
+
+
+ FRES
+ FRES
+ 0
+ 1
+
+
+
+
+ ISTR
+ ISTR
+ interrupt status register
+ 0x44
+ 0x20
+ read-write
+ 0x0
+
+
+ CTR
+ CTR
+ 15
+ 1
+
+
+ PMAOVR
+ PMAOVR
+ 14
+ 1
+
+
+ ERR
+ ERR
+ 13
+ 1
+
+
+ WKUP
+ WKUP
+ 12
+ 1
+
+
+ SUSP
+ SUSP
+ 11
+ 1
+
+
+ RESET
+ RESET
+ 10
+ 1
+
+
+ SOF
+ SOF
+ 9
+ 1
+
+
+ ESOF
+ ESOF
+ 8
+ 1
+
+
+ L1REQ
+ L1REQ
+ 7
+ 1
+
+
+ DIR
+ DIR
+ 4
+ 1
+
+
+ EP_ID
+ EP_ID
+ 0
+ 4
+
+
+
+
+ FNR
+ FNR
+ frame number register
+ 0x48
+ 0x20
+ read-only
+ 0x0
+
+
+ RXDP
+ RXDP
+ 15
+ 1
+
+
+ RXDM
+ RXDM
+ 14
+ 1
+
+
+ LCK
+ LCK
+ 13
+ 1
+
+
+ LSOF
+ LSOF
+ 11
+ 2
+
+
+ FN
+ FN
+ 0
+ 11
+
+
+
+
+ DADDR
+ DADDR
+ device address
+ 0x4C
+ 0x20
+ read-write
+ 0x0
+
+
+ EF
+ EF
+ 7
+ 1
+
+
+ ADD
+ ADD
+ 0
+ 7
+
+
+
+
+ BTABLE
+ BTABLE
+ Buffer table address
+ 0x50
+ 0x20
+ read-write
+ 0x0
+
+
+ BTABLE
+ BTABLE
+ 3
+ 13
+
+
+
+
+ LPMCSR
+ LPMCSR
+ LPM control and status
+ register
+ 0x54
+ 0x20
+ 0x0
+
+
+ BESL
+ BESL
+ 4
+ 4
+ read-only
+
+
+ REMWAKE
+ REMWAKE
+ 3
+ 1
+ read-only
+
+
+ LPMACK
+ LPMACK
+ 1
+ 1
+ read-write
+
+
+ LPMEN
+ LPMEN
+ 0
+ 1
+ read-write
+
+
+
+
+ BCDR
+ BCDR
+ Battery charging detector
+ 0x58
+ 0x20
+ 0x0
+
+
+ DPPU
+ DPPU
+ 15
+ 1
+ read-write
+
+
+ PS2DET
+ PS2DET
+ 7
+ 1
+ read-only
+
+
+ SDET
+ SDET
+ 6
+ 1
+ read-only
+
+
+ PDET
+ PDET
+ 5
+ 1
+ read-only
+
+
+ DCDET
+ DCDET
+ 4
+ 1
+ read-only
+
+
+ SDEN
+ SDEN
+ 3
+ 1
+ read-write
+
+
+ PDEN
+ PDEN
+ 2
+ 1
+ read-write
+
+
+ DCDEN
+ DCDEN
+ 1
+ 1
+ read-write
+
+
+ BCDEN
+ BCDEN
+ 0
+ 1
+ read-write
+
+
+
+
+
+
+ CRS
+ Clock recovery system
+ CRS
+ 0x40006C00
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CR
+ CR
+ control register
+ 0x0
+ 0x20
+ read-write
+ 0x00002000
+
+
+ TRIM
+ HSI48 oscillator smooth
+ trimming
+ 8
+ 6
+
+
+ SWSYNC
+ Generate software SYNC
+ event
+ 7
+ 1
+
+
+ AUTOTRIMEN
+ Automatic trimming enable
+ 6
+ 1
+
+
+ CEN
+ Frequency error counter
+ enable
+ 5
+ 1
+
+
+ ESYNCIE
+ Expected SYNC interrupt
+ enable
+ 3
+ 1
+
+
+ ERRIE
+ Synchronization or trimming error
+ interrupt enable
+ 2
+ 1
+
+
+ SYNCWARNIE
+ SYNC warning interrupt
+ enable
+ 1
+ 1
+
+
+ SYNCOKIE
+ SYNC event OK interrupt
+ enable
+ 0
+ 1
+
+
+
+
+ CFGR
+ CFGR
+ configuration register
+ 0x4
+ 0x20
+ read-write
+ 0x2022BB7F
+
+
+ SYNCPOL
+ SYNC polarity selection
+ 31
+ 1
+
+
+ SYNCSRC
+ SYNC signal source
+ selection
+ 28
+ 2
+
+
+ SYNCDIV
+ SYNC divider
+ 24
+ 3
+
+
+ FELIM
+ Frequency error limit
+ 16
+ 8
+
+
+ RELOAD
+ Counter reload value
+ 0
+ 16
+
+
+
+
+ ISR
+ ISR
+ interrupt and status register
+ 0x8
+ 0x20
+ read-only
+ 0x00000000
+
+
+ FECAP
+ Frequency error capture
+ 16
+ 16
+
+
+ FEDIR
+ Frequency error direction
+ 15
+ 1
+
+
+ TRIMOVF
+ Trimming overflow or
+ underflow
+ 10
+ 1
+
+
+ SYNCMISS
+ SYNC missed
+ 9
+ 1
+
+
+ SYNCERR
+ SYNC error
+ 8
+ 1
+
+
+ ESYNCF
+ Expected SYNC flag
+ 3
+ 1
+
+
+ ERRF
+ Error flag
+ 2
+ 1
+
+
+ SYNCWARNF
+ SYNC warning flag
+ 1
+ 1
+
+
+ SYNCOKF
+ SYNC event OK flag
+ 0
+ 1
+
+
+
+
+ ICR
+ ICR
+ interrupt flag clear register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ESYNCC
+ Expected SYNC clear flag
+ 3
+ 1
+
+
+ ERRC
+ Error clear flag
+ 2
+ 1
+
+
+ SYNCWARNC
+ SYNC warning clear flag
+ 1
+ 1
+
+
+ SYNCOKC
+ SYNC event OK clear flag
+ 0
+ 1
+
+
+
+
+
+
+ Firewall
+ Firewall
+ Firewall
+ 0x40011C00
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ FIREWALL_CSSA
+ FIREWALL_CSSA
+ Code segment start address
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ADD
+ code segment start address
+ 8
+ 16
+
+
+
+
+ FIREWALL_CSL
+ FIREWALL_CSL
+ Code segment length
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LENG
+ code segment length
+ 8
+ 14
+
+
+
+
+ FIREWALL_NVDSSA
+ FIREWALL_NVDSSA
+ Non-volatile data segment start
+ address
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ADD
+ Non-volatile data segment start
+ address
+ 8
+ 16
+
+
+
+
+ FIREWALL_NVDSL
+ FIREWALL_NVDSL
+ Non-volatile data segment
+ length
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LENG
+ Non-volatile data segment
+ length
+ 8
+ 14
+
+
+
+
+ FIREWALL_VDSSA
+ FIREWALL_VDSSA
+ Volatile data segment start
+ address
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ADD
+ Volatile data segment start
+ address
+ 6
+ 10
+
+
+
+
+ FIREWALL_VDSL
+ FIREWALL_VDSL
+ Volatile data segment length
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LENG
+ Non-volatile data segment
+ length
+ 6
+ 10
+
+
+
+
+ FIREWALL_CR
+ FIREWALL_CR
+ Configuration register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ VDE
+ Volatile data execution
+ 2
+ 1
+
+
+ VDS
+ Volatile data shared
+ 1
+ 1
+
+
+ FPA
+ Firewall pre alarm
+ 0
+ 1
+
+
+
+
+
+
+ RCC
+ Reset and clock control
+ RCC
+ 0x40021000
+
+ 0x0
+ 0x400
+ registers
+
+
+ RCC
+ RCC global interrupt
+ 4
+
+
+
+ CR
+ CR
+ Clock control register
+ 0x0
+ 0x20
+ 0x00000300
+
+
+ PLLRDY
+ PLL clock ready flag
+ 25
+ 1
+ read-only
+
+
+ PLLON
+ PLL enable bit
+ 24
+ 1
+ read-write
+
+
+ RTCPRE
+ TC/LCD prescaler
+ 20
+ 2
+ read-write
+
+
+ CSSLSEON
+ Clock security system on HSE enable
+ bit
+ 19
+ 1
+ read-write
+
+
+ HSEBYP
+ HSE clock bypass bit
+ 18
+ 1
+ read-write
+
+
+ HSERDY
+ HSE clock ready flag
+ 17
+ 1
+ read-only
+
+
+ HSEON
+ HSE clock enable bit
+ 16
+ 1
+ read-write
+
+
+ MSIRDY
+ MSI clock ready flag
+ 9
+ 1
+ read-only
+
+
+ MSION
+ MSI clock enable bit
+ 8
+ 1
+ read-write
+
+
+ HSI16DIVF
+ HSI16DIVF
+ 4
+ 1
+ read-only
+
+
+ HSI16DIVEN
+ HSI16DIVEN
+ 3
+ 1
+ read-write
+
+
+ HSI16RDYF
+ Internal high-speed clock ready
+ flag
+ 2
+ 1
+ read-write
+
+
+ HSI16KERON
+ High-speed internal clock enable bit for
+ some IP kernels
+ 1
+ 1
+ read-only
+
+
+ HSI16ON
+ 16 MHz high-speed internal clock
+ enable
+ 0
+ 1
+ read-write
+
+
+ HSI16OUTEN
+ 16 MHz high-speed internal clock output
+ enable
+ 5
+ 1
+ read-write
+
+
+
+
+ ICSCR
+ ICSCR
+ Internal clock sources calibration
+ register
+ 0x4
+ 0x20
+ 0x0000B000
+
+
+ MSITRIM
+ MSI clock trimming
+ 24
+ 8
+ read-write
+
+
+ MSICAL
+ MSI clock calibration
+ 16
+ 8
+ read-only
+
+
+ MSIRANGE
+ MSI clock ranges
+ 13
+ 3
+ read-write
+
+
+ HSI16TRIM
+ High speed internal clock
+ trimming
+ 8
+ 5
+ read-write
+
+
+ HSI16CAL
+ nternal high speed clock
+ calibration
+ 0
+ 8
+ read-only
+
+
+
+
+ CRRCR
+ CRRCR
+ Clock recovery RC register
+ 0x8
+ 0x20
+ 0x00000000
+
+
+ HSI48CAL
+ 48 MHz HSI clock
+ calibration
+ 8
+ 8
+ read-only
+
+
+ HSI48RDY
+ 48MHz HSI clock ready flag
+ 1
+ 1
+ read-only
+
+
+ HSI48ON
+ 48MHz HSI clock enable bit
+ 0
+ 1
+ read-write
+
+
+ HSI48DIV6EN
+ 48 MHz HSI clock divided by 6 output
+ enable
+ 2
+ 1
+ read-write
+
+
+
+
+ CFGR
+ CFGR
+ Clock configuration register
+ 0xC
+ 0x20
+ 0x00000000
+
+
+ MCOPRE
+ Microcontroller clock output
+ prescaler
+ 28
+ 3
+ read-write
+
+
+ MCOSEL
+ Microcontroller clock output
+ selection
+ 24
+ 4
+ read-write
+
+
+ PLLDIV
+ PLL output division
+ 22
+ 2
+ read-write
+
+
+ PLLMUL
+ PLL multiplication factor
+ 18
+ 4
+ read-write
+
+
+ PLLSRC
+ PLL entry clock source
+ 16
+ 1
+ read-write
+
+
+ STOPWUCK
+ Wake-up from stop clock
+ selection
+ 15
+ 1
+ read-write
+
+
+ PPRE2
+ APB high-speed prescaler
+ (APB2)
+ 11
+ 3
+ read-write
+
+
+ PPRE1
+ APB low-speed prescaler
+ (APB1)
+ 8
+ 3
+ read-write
+
+
+ HPRE
+ AHB prescaler
+ 4
+ 4
+ read-write
+
+
+ SWS
+ System clock switch status
+ 2
+ 2
+ read-only
+
+
+ SW
+ System clock switch
+ 0
+ 2
+ read-write
+
+
+
+
+ CIER
+ CIER
+ Clock interrupt enable
+ register
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CSSLSE
+ LSE CSS interrupt flag
+ 7
+ 1
+
+
+ HSI48RDYIE
+ HSI48 ready interrupt flag
+ 6
+ 1
+
+
+ MSIRDYIE
+ MSI ready interrupt flag
+ 5
+ 1
+
+
+ PLLRDYIE
+ PLL ready interrupt flag
+ 4
+ 1
+
+
+ HSERDYIE
+ HSE ready interrupt flag
+ 3
+ 1
+
+
+ HSI16RDYIE
+ HSI16 ready interrupt flag
+ 2
+ 1
+
+
+ LSERDYIE
+ LSE ready interrupt flag
+ 1
+ 1
+
+
+ LSIRDYIE
+ LSI ready interrupt flag
+ 0
+ 1
+
+
+
+
+ CIFR
+ CIFR
+ Clock interrupt flag register
+ 0x14
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CSSHSEF
+ Clock Security System Interrupt
+ flag
+ 8
+ 1
+
+
+ CSSLSEF
+ LSE Clock Security System Interrupt
+ flag
+ 7
+ 1
+
+
+ HSI48RDYF
+ HSI48 ready interrupt flag
+ 6
+ 1
+
+
+ MSIRDYF
+ MSI ready interrupt flag
+ 5
+ 1
+
+
+ PLLRDYF
+ PLL ready interrupt flag
+ 4
+ 1
+
+
+ HSERDYF
+ HSE ready interrupt flag
+ 3
+ 1
+
+
+ HSI16RDYF
+ HSI16 ready interrupt flag
+ 2
+ 1
+
+
+ LSERDYF
+ LSE ready interrupt flag
+ 1
+ 1
+
+
+ LSIRDYF
+ LSI ready interrupt flag
+ 0
+ 1
+
+
+
+
+ CICR
+ CICR
+ Clock interrupt clear register
+ 0x18
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CSSHSEC
+ Clock Security System Interrupt
+ clear
+ 8
+ 1
+
+
+ CSSLSEC
+ LSE Clock Security System Interrupt
+ clear
+ 7
+ 1
+
+
+ HSI48RDYC
+ HSI48 ready Interrupt
+ clear
+ 6
+ 1
+
+
+ MSIRDYC
+ MSI ready Interrupt clear
+ 5
+ 1
+
+
+ PLLRDYC
+ PLL ready Interrupt clear
+ 4
+ 1
+
+
+ HSERDYC
+ HSE ready Interrupt clear
+ 3
+ 1
+
+
+ HSI16RDYC
+ HSI16 ready Interrupt
+ clear
+ 2
+ 1
+
+
+ LSERDYC
+ LSE ready Interrupt clear
+ 1
+ 1
+
+
+ LSIRDYC
+ LSI ready Interrupt clear
+ 0
+ 1
+
+
+
+
+ IOPRSTR
+ IOPRSTR
+ GPIO reset register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IOPHRST
+ I/O port H reset
+ 7
+ 1
+
+
+ IOPDRST
+ I/O port D reset
+ 3
+ 1
+
+
+ IOPCRST
+ I/O port A reset
+ 2
+ 1
+
+
+ IOPBRST
+ I/O port B reset
+ 1
+ 1
+
+
+ IOPARST
+ I/O port A reset
+ 0
+ 1
+
+
+ IOPERST
+ I/O port E reset
+ 4
+ 1
+
+
+
+
+ AHBRSTR
+ AHBRSTR
+ AHB peripheral reset register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CRYPRST
+ Crypto module reset
+ 24
+ 1
+
+
+ RNGRST
+ Random Number Generator module
+ reset
+ 20
+ 1
+
+
+ TOUCHRST
+ Touch Sensing reset
+ 16
+ 1
+
+
+ CRCRST
+ Test integration module
+ reset
+ 12
+ 1
+
+
+ MIFRST
+ Memory interface reset
+ 8
+ 1
+
+
+ DMARST
+ DMA reset
+ 0
+ 1
+
+
+
+
+ APB2RSTR
+ APB2RSTR
+ APB2 peripheral reset register
+ 0x24
+ 0x20
+ read-write
+ 0x000000000
+
+
+ DBGRST
+ DBG reset
+ 22
+ 1
+
+
+ USART1RST
+ USART1 reset
+ 14
+ 1
+
+
+ SPI1RST
+ SPI 1 reset
+ 12
+ 1
+
+
+ ADCRST
+ ADC interface reset
+ 9
+ 1
+
+
+ TM12RST
+ TIM22 timer reset
+ 5
+ 1
+
+
+ TIM21RST
+ TIM21 timer reset
+ 2
+ 1
+
+
+ SYSCFGRST
+ System configuration controller
+ reset
+ 0
+ 1
+
+
+
+
+ APB1RSTR
+ APB1RSTR
+ APB1 peripheral reset register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LPTIM1RST
+ Low power timer reset
+ 31
+ 1
+
+
+ DACRST
+ DAC interface reset
+ 29
+ 1
+
+
+ PWRRST
+ Power interface reset
+ 28
+ 1
+
+
+ CRSRST
+ Clock recovery system
+ reset
+ 27
+ 1
+
+
+ USBRST
+ USB reset
+ 23
+ 1
+
+
+ I2C2RST
+ I2C2 reset
+ 22
+ 1
+
+
+ I2C1RST
+ I2C1 reset
+ 21
+ 1
+
+
+ LPUART1RST
+ LPUART1 reset
+ 18
+ 1
+
+
+ LPUART12RST
+ UART2 reset
+ 17
+ 1
+
+
+ SPI2RST
+ SPI2 reset
+ 14
+ 1
+
+
+ WWDRST
+ Window watchdog reset
+ 11
+ 1
+
+
+ TIM6RST
+ Timer 6 reset
+ 4
+ 1
+
+
+ TIM2RST
+ Timer2 reset
+ 0
+ 1
+
+
+ TIM3RST
+ Timer3 reset
+ 1
+ 1
+
+
+ TIM7RST
+ Timer 7 reset
+ 5
+ 1
+
+
+ USART4RST
+ USART4 reset
+ 19
+ 1
+
+
+ USART5RST
+ USART5 reset
+ 20
+ 1
+
+
+ I2C3RST
+ I2C3 reset
+ 30
+ 1
+
+
+
+
+ IOPENR
+ IOPENR
+ GPIO clock enable register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IOPHEN
+ I/O port H clock enable
+ bit
+ 7
+ 1
+
+
+ IOPDEN
+ I/O port D clock enable
+ bit
+ 3
+ 1
+
+
+ IOPCEN
+ IO port A clock enable bit
+ 2
+ 1
+
+
+ IOPBEN
+ IO port B clock enable bit
+ 1
+ 1
+
+
+ IOPAEN
+ IO port A clock enable bit
+ 0
+ 1
+
+
+ IOPEEN
+ I/O port E clock enable
+ bit
+ 4
+ 1
+
+
+
+
+ AHBENR
+ AHBENR
+ AHB peripheral clock enable
+ register
+ 0x30
+ 0x20
+ read-write
+ 0x00000100
+
+
+ CRYPEN
+ Crypto clock enable bit
+ 24
+ 1
+
+
+ RNGEN
+ Random Number Generator clock enable
+ bit
+ 20
+ 1
+
+
+ TOUCHEN
+ Touch Sensing clock enable
+ bit
+ 16
+ 1
+
+
+ CRCEN
+ CRC clock enable bit
+ 12
+ 1
+
+
+ MIFEN
+ NVM interface clock enable
+ bit
+ 8
+ 1
+
+
+ DMAEN
+ DMA clock enable bit
+ 0
+ 1
+
+
+
+
+ APB2ENR
+ APB2ENR
+ APB2 peripheral clock enable
+ register
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DBGEN
+ DBG clock enable bit
+ 22
+ 1
+
+
+ USART1EN
+ USART1 clock enable bit
+ 14
+ 1
+
+
+ SPI1EN
+ SPI1 clock enable bit
+ 12
+ 1
+
+
+ ADCEN
+ ADC clock enable bit
+ 9
+ 1
+
+
+ MIFIEN
+ MiFaRe Firewall clock enable
+ bit
+ 7
+ 1
+
+
+ TIM22EN
+ TIM22 timer clock enable
+ bit
+ 5
+ 1
+
+
+ TIM21EN
+ TIM21 timer clock enable
+ bit
+ 2
+ 1
+
+
+ SYSCFGEN
+ System configuration controller clock
+ enable bit
+ 0
+ 1
+
+
+
+
+ APB1ENR
+ APB1ENR
+ APB1 peripheral clock enable
+ register
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LPTIM1EN
+ Low power timer clock enable
+ bit
+ 31
+ 1
+
+
+ DACEN
+ DAC interface clock enable
+ bit
+ 29
+ 1
+
+
+ PWREN
+ Power interface clock enable
+ bit
+ 28
+ 1
+
+
+ CRSEN
+ Clock recovery system clock enable
+ bit
+ 27
+ 1
+
+
+ USBEN
+ USB clock enable bit
+ 23
+ 1
+
+
+ I2C2EN
+ I2C2 clock enable bit
+ 22
+ 1
+
+
+ I2C1EN
+ I2C1 clock enable bit
+ 21
+ 1
+
+
+ LPUART1EN
+ LPUART1 clock enable bit
+ 18
+ 1
+
+
+ USART2EN
+ UART2 clock enable bit
+ 17
+ 1
+
+
+ SPI2EN
+ SPI2 clock enable bit
+ 14
+ 1
+
+
+ WWDGEN
+ Window watchdog clock enable
+ bit
+ 11
+ 1
+
+
+ TIM6EN
+ Timer 6 clock enable bit
+ 4
+ 1
+
+
+ TIM2EN
+ Timer2 clock enable bit
+ 0
+ 1
+
+
+ TIM3EN
+ Timer3 clock enable bit
+ 1
+ 1
+
+
+ TIM7EN
+ Timer 7 clock enable bit
+ 5
+ 1
+
+
+ USART4EN
+ USART4 clock enable bit
+ 19
+ 1
+
+
+ USART5EN
+ USART5 clock enable bit
+ 20
+ 1
+
+
+ I2C3EN
+ I2C3 clock enable bit
+ 30
+ 1
+
+
+
+
+ IOPSMEN
+ IOPSMEN
+ GPIO clock enable in sleep mode
+ register
+ 0x3C
+ 0x20
+ read-write
+ 0x0000008F
+
+
+ IOPHSMEN
+ IOPHSMEN
+ 7
+ 1
+
+
+ IOPDSMEN
+ IOPDSMEN
+ 3
+ 1
+
+
+ IOPCSMEN
+ IOPCSMEN
+ 2
+ 1
+
+
+ IOPBSMEN
+ IOPBSMEN
+ 1
+ 1
+
+
+ IOPASMEN
+ IOPASMEN
+ 0
+ 1
+
+
+ IOPESMEN
+ Port E clock enable during Sleep mode
+ bit
+ 4
+ 1
+
+
+
+
+ AHBSMENR
+ AHBSMENR
+ AHB peripheral clock enable in sleep mode
+ register
+ 0x40
+ 0x20
+ read-write
+ 0x01111301
+
+
+ CRYPSMEN
+ Crypto clock enable during sleep mode
+ bit
+ 24
+ 1
+
+
+ RNGSMEN
+ Random Number Generator clock enable
+ during sleep mode bit
+ 20
+ 1
+
+
+ TOUCHSMEN
+ Touch Sensing clock enable during sleep
+ mode bit
+ 16
+ 1
+
+
+ CRCSMEN
+ CRC clock enable during sleep mode
+ bit
+ 12
+ 1
+
+
+ SRAMSMEN
+ SRAM interface clock enable during sleep
+ mode bit
+ 9
+ 1
+
+
+ MIFSMEN
+ NVM interface clock enable during sleep
+ mode bit
+ 8
+ 1
+
+
+ DMASMEN
+ DMA clock enable during sleep mode
+ bit
+ 0
+ 1
+
+
+
+
+ APB2SMENR
+ APB2SMENR
+ APB2 peripheral clock enable in sleep mode
+ register
+ 0x44
+ 0x20
+ read-write
+ 0x00405225
+
+
+ DBGSMEN
+ DBG clock enable during sleep mode
+ bit
+ 22
+ 1
+
+
+ USART1SMEN
+ USART1 clock enable during sleep mode
+ bit
+ 14
+ 1
+
+
+ SPI1SMEN
+ SPI1 clock enable during sleep mode
+ bit
+ 12
+ 1
+
+
+ ADCSMEN
+ ADC clock enable during sleep mode
+ bit
+ 9
+ 1
+
+
+ TIM22SMEN
+ TIM22 timer clock enable during sleep
+ mode bit
+ 5
+ 1
+
+
+ TIM21SMEN
+ TIM21 timer clock enable during sleep
+ mode bit
+ 2
+ 1
+
+
+ SYSCFGSMEN
+ System configuration controller clock
+ enable during sleep mode bit
+ 0
+ 1
+
+
+
+
+ APB1SMENR
+ APB1SMENR
+ APB1 peripheral clock enable in sleep mode
+ register
+ 0x48
+ 0x20
+ read-write
+ 0xB8E64A11
+
+
+ LPTIM1SMEN
+ Low power timer clock enable during
+ sleep mode bit
+ 31
+ 1
+
+
+ DACSMEN
+ DAC interface clock enable during sleep
+ mode bit
+ 29
+ 1
+
+
+ PWRSMEN
+ Power interface clock enable during
+ sleep mode bit
+ 28
+ 1
+
+
+ CRSSMEN
+ Clock recovery system clock enable
+ during sleep mode bit
+ 27
+ 1
+
+
+ USBSMEN
+ USB clock enable during sleep mode
+ bit
+ 23
+ 1
+
+
+ I2C2SMEN
+ I2C2 clock enable during sleep mode
+ bit
+ 22
+ 1
+
+
+ I2C1SMEN
+ I2C1 clock enable during sleep mode
+ bit
+ 21
+ 1
+
+
+ LPUART1SMEN
+ LPUART1 clock enable during sleep mode
+ bit
+ 18
+ 1
+
+
+ USART2SMEN
+ UART2 clock enable during sleep mode
+ bit
+ 17
+ 1
+
+
+ SPI2SMEN
+ SPI2 clock enable during sleep mode
+ bit
+ 14
+ 1
+
+
+ WWDGSMEN
+ Window watchdog clock enable during
+ sleep mode bit
+ 11
+ 1
+
+
+ TIM6SMEN
+ Timer 6 clock enable during sleep mode
+ bit
+ 4
+ 1
+
+
+ TIM2SMEN
+ Timer2 clock enable during sleep mode
+ bit
+ 0
+ 1
+
+
+ TIM3SMEN
+ Timer3 clock enable during Sleep mode
+ bit
+ 1
+ 1
+
+
+ TIM7SMEN
+ Timer 7 clock enable during Sleep mode
+ bit
+ 5
+ 1
+
+
+ USART4SMEN
+ USART4 clock enable during Sleep mode
+ bit
+ 19
+ 1
+
+
+ USART5SMEN
+ USART5 clock enable during Sleep mode
+ bit
+ 20
+ 1
+
+
+ I2C3SMEN
+ 2C3 clock enable during Sleep mode
+ bit
+ 30
+ 1
+
+
+
+
+ CCIPR
+ CCIPR
+ Clock configuration register
+ 0x4C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ HSI48MSEL
+ 48 MHz HSI48 clock source selection
+ bit
+ 26
+ 1
+
+
+ LPTIM1SEL1
+ Low Power Timer clock source selection
+ bits
+ 19
+ 1
+
+
+ LPTIM1SEL0
+ LPTIM1SEL0
+ 18
+ 1
+
+
+ I2C1SEL1
+ I2C1 clock source selection
+ bits
+ 13
+ 1
+
+
+ I2C1SEL0
+ I2C1SEL0
+ 12
+ 1
+
+
+ LPUART1SEL1
+ LPUART1 clock source selection
+ bits
+ 11
+ 1
+
+
+ LPUART1SEL0
+ LPUART1SEL0
+ 10
+ 1
+
+
+ USART2SEL1
+ USART2 clock source selection
+ bits
+ 3
+ 1
+
+
+ USART2SEL0
+ USART2SEL0
+ 2
+ 1
+
+
+ USART1SEL1
+ USART1 clock source selection
+ bits
+ 1
+ 1
+
+
+ USART1SEL0
+ USART1SEL0
+ 0
+ 1
+
+
+ I2C3SEL
+ I2C3 clock source selection
+ bits
+ 16
+ 2
+
+
+
+
+ CSR
+ CSR
+ Control and status register
+ 0x50
+ 0x20
+ 0x0C000000
+
+
+ LPWRSTF
+ Low-power reset flag
+ 31
+ 1
+ read-write
+
+
+ WWDGRSTF
+ Window watchdog reset flag
+ 30
+ 1
+ read-write
+
+
+ IWDGRSTF
+ Independent watchdog reset
+ flag
+ 29
+ 1
+ read-write
+
+
+ SFTRSTF
+ Software reset flag
+ 28
+ 1
+ read-write
+
+
+ PORRSTF
+ POR/PDR reset flag
+ 27
+ 1
+ read-write
+
+
+ PINRSTF
+ PIN reset flag
+ 26
+ 1
+ read-write
+
+
+ OBLRSTF
+ OBLRSTF
+ 25
+ 1
+ read-write
+
+
+ RMVF
+ Remove reset flag
+ 24
+ 1
+ read-write
+
+
+ RTCRST
+ RTC software reset bit
+ 19
+ 1
+ read-write
+
+
+ RTCEN
+ RTC clock enable bit
+ 18
+ 1
+ read-write
+
+
+ RTCSEL
+ RTC and LCD clock source selection
+ bits
+ 16
+ 2
+ read-write
+
+
+ CSSLSED
+ CSS on LSE failure detection
+ flag
+ 14
+ 1
+ read-write
+
+
+ CSSLSEON
+ CSSLSEON
+ 13
+ 1
+ read-write
+
+
+ LSEDRV
+ LSEDRV
+ 11
+ 2
+ read-write
+
+
+ LSEBYP
+ External low-speed oscillator bypass
+ bit
+ 10
+ 1
+ read-write
+
+
+ LSERDY
+ External low-speed oscillator ready
+ bit
+ 9
+ 1
+ read-only
+
+
+ LSEON
+ External low-speed oscillator enable
+ bit
+ 8
+ 1
+ read-write
+
+
+ LSIRDY
+ Internal low-speed oscillator ready
+ bit
+ 1
+ 1
+ read-write
+
+
+ LSION
+ Internal low-speed oscillator
+ enable
+ 0
+ 1
+ read-write
+
+
+
+
+
+
+ SYSCFG_COMP
+ System configuration controller and
+ Comparator
+ SYSCFG
+ 0x40010000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CFGR1
+ CFGR1
+ SYSCFG configuration register
+ 1
+ 0x0
+ 0x20
+ 0x00000000
+
+
+ BOOT_MODE
+ Boot mode selected by the boot pins
+ status bits
+ 8
+ 2
+ read-only
+
+
+ MEM_MODE
+ Memory mapping selection
+ bits
+ 0
+ 2
+ read-write
+
+
+
+
+ CFGR2
+ CFGR2
+ SYSCFG configuration register
+ 2
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ I2C2_FMP
+ I2C2 Fm+ drive capability enable
+ bit
+ 13
+ 1
+
+
+ I2C1_FMP
+ I2C1 Fm+ drive capability enable
+ bit
+ 12
+ 1
+
+
+ I2C_PB9_FMP
+ Fm+ drive capability on PB9 enable
+ bit
+ 11
+ 1
+
+
+ I2C_PB8_FMP
+ Fm+ drive capability on PB8 enable
+ bit
+ 10
+ 1
+
+
+ I2C_PB7_FMP
+ Fm+ drive capability on PB7 enable
+ bit
+ 9
+ 1
+
+
+ I2C_PB6_FMP
+ Fm+ drive capability on PB6 enable
+ bit
+ 8
+ 1
+
+
+ FWDISEN
+ Firewall disable bit
+ 0
+ 1
+
+
+
+
+ EXTICR1
+ EXTICR1
+ external interrupt configuration register
+ 1
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ EXTI3
+ EXTI x configuration (x = 0 to
+ 3)
+ 12
+ 4
+
+
+ EXTI2
+ EXTI x configuration (x = 0 to
+ 3)
+ 8
+ 4
+
+
+ EXTI1
+ EXTI x configuration (x = 0 to
+ 3)
+ 4
+ 4
+
+
+ EXTI0
+ EXTI x configuration (x = 0 to
+ 3)
+ 0
+ 4
+
+
+
+
+ EXTICR2
+ EXTICR2
+ external interrupt configuration register
+ 2
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ EXTI7
+ EXTI x configuration (x = 4 to
+ 7)
+ 12
+ 4
+
+
+ EXTI6
+ EXTI x configuration (x = 4 to
+ 7)
+ 8
+ 4
+
+
+ EXTI5
+ EXTI x configuration (x = 4 to
+ 7)
+ 4
+ 4
+
+
+ EXTI4
+ EXTI x configuration (x = 4 to
+ 7)
+ 0
+ 4
+
+
+
+
+ EXTICR3
+ EXTICR3
+ external interrupt configuration register
+ 3
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ EXTI11
+ EXTI x configuration (x = 8 to
+ 11)
+ 12
+ 4
+
+
+ EXTI10
+ EXTI10
+ 8
+ 4
+
+
+ EXTI9
+ EXTI x configuration (x = 8 to
+ 11)
+ 4
+ 4
+
+
+ EXTI8
+ EXTI x configuration (x = 8 to
+ 11)
+ 0
+ 4
+
+
+
+
+ EXTICR4
+ EXTICR4
+ external interrupt configuration register
+ 4
+ 0x14
+ 0x20
+ read-write
+ 0x0000
+
+
+ EXTI15
+ EXTI x configuration (x = 12 to
+ 15)
+ 12
+ 4
+
+
+ EXTI14
+ EXTI14
+ 8
+ 4
+
+
+ EXTI13
+ EXTI13
+ 4
+ 4
+
+
+ EXTI12
+ EXTI12
+ 0
+ 4
+
+
+
+
+ CFGR3
+ CFGR3
+ SYSCFG configuration register
+ 3
+ 0x20
+ 0x20
+ 0x00000000
+
+
+ REF_LOCK
+ REF_CTRL lock bit
+ 31
+ 1
+ write-only
+
+
+ VREFINT_RDYF
+ VREFINT ready flag
+ 30
+ 1
+ read-only
+
+
+ VREFINT_COMP_RDYF
+ VREFINT for comparator ready
+ flag
+ 29
+ 1
+ read-only
+
+
+ VREFINT_ADC_RDYF
+ VREFINT for ADC ready flag
+ 28
+ 1
+ read-only
+
+
+ SENSOR_ADC_RDYF
+ Sensor for ADC ready flag
+ 27
+ 1
+ read-only
+
+
+ REF_RC48MHz_RDYF
+ VREFINT for 48 MHz RC oscillator ready
+ flag
+ 26
+ 1
+ read-only
+
+
+ ENREF_RC48MHz
+ VREFINT reference for 48 MHz RC
+ oscillator enable bit
+ 13
+ 1
+ read-write
+
+
+ ENBUF_VREFINT_COMP
+ VREFINT reference for comparator 2
+ enable bit
+ 12
+ 1
+ read-write
+
+
+ ENBUF_SENSOR_ADC
+ Sensor reference for ADC enable
+ bit
+ 9
+ 1
+ read-write
+
+
+ ENBUF_BGAP_ADC
+ VREFINT reference for ADC enable
+ bit
+ 8
+ 1
+ read-write
+
+
+ SEL_VREF_OUT
+ BGAP_ADC connection bit
+ 4
+ 2
+ read-write
+
+
+ EN_BGAP
+ Vref Enable bit
+ 0
+ 1
+ read-write
+
+
+
+
+ COMP1_CSR
+ COMP1_CSR
+ Comparator 1 control and status
+ register
+ 0x18
+ 0x20
+ 0x00000000
+
+
+ COMP1LOCK
+ COMP1_CSR register lock
+ bit
+ 31
+ 1
+ read-only
+
+
+ COMP1VALUE
+ Comparator 1 output status
+ bit
+ 30
+ 1
+ read-only
+
+
+ COMP1POLARITY
+ Comparator 1 polarity selection
+ bit
+ 15
+ 1
+ read-write
+
+
+ COMP1LPTIMIN1
+ Comparator 1 LPTIM input propagation
+ bit
+ 12
+ 1
+ read-write
+
+
+ COMP1WM
+ Comparator 1 window mode selection
+ bit
+ 8
+ 1
+ read-write
+
+
+ COMP1INNSEL
+ Comparator 1 Input Minus connection
+ configuration bit
+ 4
+ 2
+ read-write
+
+
+ COMP1EN
+ Comparator 1 enable bit
+ 0
+ 1
+ read-write
+
+
+
+
+ COMP2_CSR
+ COMP2_CSR
+ Comparator 2 control and status
+ register
+ 0x1C
+ 0x20
+ 0x00000000
+
+
+ COMP2LOCK
+ COMP2_CSR register lock
+ bit
+ 31
+ 1
+ read-only
+
+
+ COMP2VALUE
+ Comparator 2 output status
+ bit
+ 20
+ 1
+ read-only
+
+
+ COMP2POLARITY
+ Comparator 2 polarity selection
+ bit
+ 15
+ 1
+ read-write
+
+
+ COMP2LPTIMIN1
+ Comparator 2 LPTIM input 1 propagation
+ bit
+ 13
+ 1
+ read-write
+
+
+ COMP2LPTIMIN2
+ Comparator 2 LPTIM input 2 propagation
+ bit
+ 12
+ 1
+ read-write
+
+
+ COMP2INPSEL
+ Comparator 2 Input Plus connection
+ configuration bit
+ 8
+ 3
+ read-write
+
+
+ COMP2INNSEL
+ Comparator 2 Input Minus connection
+ configuration bit
+ 4
+ 3
+ read-write
+
+
+ COMP2SPEED
+ Comparator 2 power mode selection
+ bit
+ 3
+ 1
+ read-write
+
+
+ COMP2EN
+ Comparator 2 enable bit
+ 0
+ 1
+ read-write
+
+
+
+
+
+
+ SPI1
+ Serial peripheral interface
+ SPI
+ 0x40013000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ BIDIMODE
+ Bidirectional data mode
+ enable
+ 15
+ 1
+
+
+ BIDIOE
+ Output enable in bidirectional
+ mode
+ 14
+ 1
+
+
+ CRCEN
+ Hardware CRC calculation
+ enable
+ 13
+ 1
+
+
+ CRCNEXT
+ CRC transfer next
+ 12
+ 1
+
+
+ DFF
+ Data frame format
+ 11
+ 1
+
+
+ RXONLY
+ Receive only
+ 10
+ 1
+
+
+ SSM
+ Software slave management
+ 9
+ 1
+
+
+ SSI
+ Internal slave select
+ 8
+ 1
+
+
+ LSBFIRST
+ Frame format
+ 7
+ 1
+
+
+ SPE
+ SPI enable
+ 6
+ 1
+
+
+ BR
+ Baud rate control
+ 3
+ 3
+
+
+ MSTR
+ Master selection
+ 2
+ 1
+
+
+ CPOL
+ Clock polarity
+ 1
+ 1
+
+
+ CPHA
+ Clock phase
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ RXDMAEN
+ Rx buffer DMA enable
+ 0
+ 1
+
+
+ TXDMAEN
+ Tx buffer DMA enable
+ 1
+ 1
+
+
+ SSOE
+ SS output enable
+ 2
+ 1
+
+
+ FRF
+ Frame format
+ 4
+ 1
+
+
+ ERRIE
+ Error interrupt enable
+ 5
+ 1
+
+
+ RXNEIE
+ RX buffer not empty interrupt
+ enable
+ 6
+ 1
+
+
+ TXEIE
+ Tx buffer empty interrupt
+ enable
+ 7
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x8
+ 0x20
+ 0x0002
+
+
+ RXNE
+ Receive buffer not empty
+ 0
+ 1
+ read-only
+
+
+ TXE
+ Transmit buffer empty
+ 1
+ 1
+ read-only
+
+
+ CHSIDE
+ Channel side
+ 2
+ 1
+ read-only
+
+
+ UDR
+ Underrun flag
+ 3
+ 1
+ read-only
+
+
+ CRCERR
+ CRC error flag
+ 4
+ 1
+ read-write
+
+
+ MODF
+ Mode fault
+ 5
+ 1
+ read-only
+
+
+ OVR
+ Overrun flag
+ 6
+ 1
+ read-only
+
+
+ BSY
+ Busy flag
+ 7
+ 1
+ read-only
+
+
+ TIFRFE
+ TI frame format error
+ 8
+ 1
+ read-only
+
+
+
+
+ DR
+ DR
+ data register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ DR
+ Data register
+ 0
+ 16
+
+
+
+
+ CRCPR
+ CRCPR
+ CRC polynomial register
+ 0x10
+ 0x20
+ read-write
+ 0x0007
+
+
+ CRCPOLY
+ CRC polynomial register
+ 0
+ 16
+
+
+
+
+ RXCRCR
+ RXCRCR
+ RX CRC register
+ 0x14
+ 0x20
+ read-only
+ 0x0000
+
+
+ RxCRC
+ Rx CRC register
+ 0
+ 16
+
+
+
+
+ TXCRCR
+ TXCRCR
+ TX CRC register
+ 0x18
+ 0x20
+ read-only
+ 0x0000
+
+
+ TxCRC
+ Tx CRC register
+ 0
+ 16
+
+
+
+
+ I2SCFGR
+ I2SCFGR
+ I2S configuration register
+ 0x1C
+ 0x20
+ read-write
+ 0x0000
+
+
+ I2SMOD
+ I2S mode selection
+ 11
+ 1
+
+
+ I2SE
+ I2S Enable
+ 10
+ 1
+
+
+ I2SCFG
+ I2S configuration mode
+ 8
+ 2
+
+
+ PCMSYNC
+ PCM frame synchronization
+ 7
+ 1
+
+
+ I2SSTD
+ I2S standard selection
+ 4
+ 2
+
+
+ CKPOL
+ Steady state clock
+ polarity
+ 3
+ 1
+
+
+ DATLEN
+ Data length to be
+ transferred
+ 1
+ 2
+
+
+ CHLEN
+ Channel length (number of bits per audio
+ channel)
+ 0
+ 1
+
+
+
+
+ I2SPR
+ I2SPR
+ I2S prescaler register
+ 0x20
+ 0x20
+ read-write
+ 0x00000010
+
+
+ MCKOE
+ Master clock output enable
+ 9
+ 1
+
+
+ ODD
+ Odd factor for the
+ prescaler
+ 8
+ 1
+
+
+ I2SDIV
+ I2S Linear prescaler
+ 0
+ 8
+
+
+
+
+
+
+ SPI2
+ 0x40003800
+
+ SPI1
+ SPI1_global_interrupt
+ 25
+
+
+
+ I2C1
+ Inter-integrated circuit
+ I2C
+ 0x40005400
+
+ 0x0
+ 0x400
+ registers
+
+
+ SPI2
+ SPI2 global interrupt
+ 26
+
+
+
+ CR1
+ CR1
+ Control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PE
+ Peripheral enable
+ 0
+ 1
+
+
+ TXIE
+ TX Interrupt enable
+ 1
+ 1
+
+
+ RXIE
+ RX Interrupt enable
+ 2
+ 1
+
+
+ ADDRIE
+ Address match interrupt enable (slave
+ only)
+ 3
+ 1
+
+
+ NACKIE
+ Not acknowledge received interrupt
+ enable
+ 4
+ 1
+
+
+ STOPIE
+ STOP detection Interrupt
+ enable
+ 5
+ 1
+
+
+ TCIE
+ Transfer Complete interrupt
+ enable
+ 6
+ 1
+
+
+ ERRIE
+ Error interrupts enable
+ 7
+ 1
+
+
+ DNF
+ Digital noise filter
+ 8
+ 4
+
+
+ ANFOFF
+ Analog noise filter OFF
+ 12
+ 1
+
+
+ TXDMAEN
+ DMA transmission requests
+ enable
+ 14
+ 1
+
+
+ RXDMAEN
+ DMA reception requests
+ enable
+ 15
+ 1
+
+
+ SBC
+ Slave byte control
+ 16
+ 1
+
+
+ NOSTRETCH
+ Clock stretching disable
+ 17
+ 1
+
+
+ WUPEN
+ Wakeup from STOP enable
+ 18
+ 1
+
+
+ GCEN
+ General call enable
+ 19
+ 1
+
+
+ SMBHEN
+ SMBus Host address enable
+ 20
+ 1
+
+
+ SMBDEN
+ SMBus Device Default address
+ enable
+ 21
+ 1
+
+
+ ALERTEN
+ SMBUS alert enable
+ 22
+ 1
+
+
+ PECEN
+ PEC enable
+ 23
+ 1
+
+
+
+
+ CR2
+ CR2
+ Control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PECBYTE
+ Packet error checking byte
+ 26
+ 1
+
+
+ AUTOEND
+ Automatic end mode (master
+ mode)
+ 25
+ 1
+
+
+ RELOAD
+ NBYTES reload mode
+ 24
+ 1
+
+
+ NBYTES
+ Number of bytes
+ 16
+ 8
+
+
+ NACK
+ NACK generation (slave
+ mode)
+ 15
+ 1
+
+
+ STOP
+ Stop generation (master
+ mode)
+ 14
+ 1
+
+
+ START
+ Start generation
+ 13
+ 1
+
+
+ HEAD10R
+ 10-bit address header only read
+ direction (master receiver mode)
+ 12
+ 1
+
+
+ ADD10
+ 10-bit addressing mode (master
+ mode)
+ 11
+ 1
+
+
+ RD_WRN
+ Transfer direction (master
+ mode)
+ 10
+ 1
+
+
+ SADD
+ Slave address bit (master
+ mode)
+ 0
+ 10
+
+
+
+
+ OAR1
+ OAR1
+ Own address register 1
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OA1
+ Interface address
+ 0
+ 10
+
+
+ OA1MODE
+ Own Address 1 10-bit mode
+ 10
+ 1
+
+
+ OA1EN
+ Own Address 1 enable
+ 15
+ 1
+
+
+
+
+ OAR2
+ OAR2
+ Own address register 2
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OA2
+ Interface address
+ 1
+ 7
+
+
+ OA2MSK
+ Own Address 2 masks
+ 8
+ 3
+
+
+ OA2EN
+ Own Address 2 enable
+ 15
+ 1
+
+
+
+
+ TIMINGR
+ TIMINGR
+ Timing register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SCLL
+ SCL low period (master
+ mode)
+ 0
+ 8
+
+
+ SCLH
+ SCL high period (master
+ mode)
+ 8
+ 8
+
+
+ SDADEL
+ Data hold time
+ 16
+ 4
+
+
+ SCLDEL
+ Data setup time
+ 20
+ 4
+
+
+ PRESC
+ Timing prescaler
+ 28
+ 4
+
+
+
+
+ TIMEOUTR
+ TIMEOUTR
+ Status register 1
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIMEOUTA
+ Bus timeout A
+ 0
+ 12
+
+
+ TIDLE
+ Idle clock timeout
+ detection
+ 12
+ 1
+
+
+ TIMOUTEN
+ Clock timeout enable
+ 15
+ 1
+
+
+ TIMEOUTB
+ Bus timeout B
+ 16
+ 12
+
+
+ TEXTEN
+ Extended clock timeout
+ enable
+ 31
+ 1
+
+
+
+
+ ISR
+ ISR
+ Interrupt and Status register
+ 0x18
+ 0x20
+ 0x00000001
+
+
+ ADDCODE
+ Address match code (Slave
+ mode)
+ 17
+ 7
+ read-only
+
+
+ DIR
+ Transfer direction (Slave
+ mode)
+ 16
+ 1
+ read-only
+
+
+ BUSY
+ Bus busy
+ 15
+ 1
+ read-only
+
+
+ ALERT
+ SMBus alert
+ 13
+ 1
+ read-only
+
+
+ TIMEOUT
+ Timeout or t_low detection
+ flag
+ 12
+ 1
+ read-only
+
+
+ PECERR
+ PEC Error in reception
+ 11
+ 1
+ read-only
+
+
+ OVR
+ Overrun/Underrun (slave
+ mode)
+ 10
+ 1
+ read-only
+
+
+ ARLO
+ Arbitration lost
+ 9
+ 1
+ read-only
+
+
+ BERR
+ Bus error
+ 8
+ 1
+ read-only
+
+
+ TCR
+ Transfer Complete Reload
+ 7
+ 1
+ read-only
+
+
+ TC
+ Transfer Complete (master
+ mode)
+ 6
+ 1
+ read-only
+
+
+ STOPF
+ Stop detection flag
+ 5
+ 1
+ read-only
+
+
+ NACKF
+ Not acknowledge received
+ flag
+ 4
+ 1
+ read-only
+
+
+ ADDR
+ Address matched (slave
+ mode)
+ 3
+ 1
+ read-only
+
+
+ RXNE
+ Receive data register not empty
+ (receivers)
+ 2
+ 1
+ read-only
+
+
+ TXIS
+ Transmit interrupt status
+ (transmitters)
+ 1
+ 1
+ read-write
+
+
+ TXE
+ Transmit data register empty
+ (transmitters)
+ 0
+ 1
+ read-write
+
+
+
+
+ ICR
+ ICR
+ Interrupt clear register
+ 0x1C
+ 0x20
+ write-only
+ 0x00000000
+
+
+ ALERTCF
+ Alert flag clear
+ 13
+ 1
+
+
+ TIMOUTCF
+ Timeout detection flag
+ clear
+ 12
+ 1
+
+
+ PECCF
+ PEC Error flag clear
+ 11
+ 1
+
+
+ OVRCF
+ Overrun/Underrun flag
+ clear
+ 10
+ 1
+
+
+ ARLOCF
+ Arbitration lost flag
+ clear
+ 9
+ 1
+
+
+ BERRCF
+ Bus error flag clear
+ 8
+ 1
+
+
+ STOPCF
+ Stop detection flag clear
+ 5
+ 1
+
+
+ NACKCF
+ Not Acknowledge flag clear
+ 4
+ 1
+
+
+ ADDRCF
+ Address Matched flag clear
+ 3
+ 1
+
+
+
+
+ PECR
+ PECR
+ PEC register
+ 0x20
+ 0x20
+ read-only
+ 0x00000000
+
+
+ PEC
+ Packet error checking
+ register
+ 0
+ 8
+
+
+
+
+ RXDR
+ RXDR
+ Receive data register
+ 0x24
+ 0x20
+ read-only
+ 0x00000000
+
+
+ RXDATA
+ 8-bit receive data
+ 0
+ 8
+
+
+
+
+ TXDR
+ TXDR
+ Transmit data register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TXDATA
+ 8-bit transmit data
+ 0
+ 8
+
+
+
+
+
+
+ I2C2
+ 0x40005800
+
+ I2C1
+ I2C1 global interrupt
+ 23
+
+
+ I2C2
+ I2C2 global interrupt
+ 24
+
+
+
+ I2C3
+ 0x40007800
+
+
+ PWR
+ Power control
+ PWR
+ 0x40007000
+
+ 0x0
+ 0x400
+ registers
+
+
+ I2C3
+ I2C3 global interrupt
+ 21
+
+
+
+ CR
+ CR
+ power control register
+ 0x0
+ 0x20
+ read-write
+ 0x00001000
+
+
+ LPDS
+ Low-power deep sleep
+ 0
+ 1
+
+
+ PDDS
+ Power down deepsleep
+ 1
+ 1
+
+
+ CWUF
+ Clear wakeup flag
+ 2
+ 1
+
+
+ CSBF
+ Clear standby flag
+ 3
+ 1
+
+
+ PVDE
+ Power voltage detector
+ enable
+ 4
+ 1
+
+
+ PLS
+ PVD level selection
+ 5
+ 3
+
+
+ DBP
+ Disable backup domain write
+ protection
+ 8
+ 1
+
+
+ ULP
+ Ultra-low-power mode
+ 9
+ 1
+
+
+ FWU
+ Fast wakeup
+ 10
+ 1
+
+
+ VOS
+ Voltage scaling range
+ selection
+ 11
+ 2
+
+
+ DS_EE_KOFF
+ Deep sleep mode with Flash memory kept
+ off
+ 13
+ 1
+
+
+ LPRUN
+ Low power run mode
+ 14
+ 1
+
+
+
+
+ CSR
+ CSR
+ power control/status register
+ 0x4
+ 0x20
+ 0x00000000
+
+
+ BRE
+ Backup regulator enable
+ 9
+ 1
+ read-write
+
+
+ EWUP
+ Enable WKUP pin
+ 8
+ 1
+ read-write
+
+
+ BRR
+ Backup regulator ready
+ 3
+ 1
+ read-only
+
+
+ PVDO
+ PVD output
+ 2
+ 1
+ read-only
+
+
+ SBF
+ Standby flag
+ 1
+ 1
+ read-only
+
+
+ WUF
+ Wakeup flag
+ 0
+ 1
+ read-only
+
+
+ VOSF
+ Voltage Scaling select
+ flag
+ 4
+ 1
+ read-only
+
+
+ REGLPF
+ Regulator LP flag
+ 5
+ 1
+ read-only
+
+
+
+
+
+
+ Flash
+ Flash
+ Flash
+ 0x40022000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ ACR
+ ACR
+ Access control register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LATENCY
+ Latency
+ 0
+ 1
+
+
+ PRFTEN
+ Prefetch enable
+ 1
+ 1
+
+
+ SLEEP_PD
+ Flash mode during Sleep
+ 3
+ 1
+
+
+ RUN_PD
+ Flash mode during Run
+ 4
+ 1
+
+
+ DESAB_BUF
+ Disable Buffer
+ 5
+ 1
+
+
+ PRE_READ
+ Pre-read data address
+ 6
+ 1
+
+
+
+
+ PECR
+ PECR
+ Program/erase control register
+ 0x4
+ 0x20
+ read-write
+ 0x00000007
+
+
+ PELOCK
+ FLASH_PECR and data EEPROM
+ lock
+ 0
+ 1
+
+
+ PRGLOCK
+ Program memory lock
+ 1
+ 1
+
+
+ OPTLOCK
+ Option bytes block lock
+ 2
+ 1
+
+
+ PROG
+ Program memory selection
+ 3
+ 1
+
+
+ DATA
+ Data EEPROM selection
+ 4
+ 1
+
+
+ FTDW
+ Fixed time data write for Byte, Half
+ Word and Word programming
+ 8
+ 1
+
+
+ ERASE
+ Page or Double Word erase
+ mode
+ 9
+ 1
+
+
+ FPRG
+ Half Page/Double Word programming
+ mode
+ 10
+ 1
+
+
+ PARALLELBANK
+ Parallel bank mode
+ 15
+ 1
+
+
+ EOPIE
+ End of programming interrupt
+ enable
+ 16
+ 1
+
+
+ ERRIE
+ Error interrupt enable
+ 17
+ 1
+
+
+ OBL_LAUNCH
+ Launch the option byte
+ loading
+ 18
+ 1
+
+
+
+
+ PDKEYR
+ PDKEYR
+ Power down key register
+ 0x8
+ 0x20
+ write-only
+ 0x00000000
+
+
+ PDKEYR
+ RUN_PD in FLASH_ACR key
+ 0
+ 32
+
+
+
+
+ PEKEYR
+ PEKEYR
+ Program/erase key register
+ 0xC
+ 0x20
+ write-only
+ 0x00000000
+
+
+ PEKEYR
+ FLASH_PEC and data EEPROM
+ key
+ 0
+ 32
+
+
+
+
+ PRGKEYR
+ PRGKEYR
+ Program memory key register
+ 0x10
+ 0x20
+ write-only
+ 0x00000000
+
+
+ PRGKEYR
+ Program memory key
+ 0
+ 32
+
+
+
+
+ OPTKEYR
+ OPTKEYR
+ Option byte key register
+ 0x14
+ 0x20
+ write-only
+ 0x00000000
+
+
+ OPTKEYR
+ Option byte key
+ 0
+ 32
+
+
+
+
+ SR
+ SR
+ Status register
+ 0x18
+ 0x20
+ 0x00000004
+
+
+ BSY
+ Write/erase operations in
+ progress
+ 0
+ 1
+ read-only
+
+
+ EOP
+ End of operation
+ 1
+ 1
+ read-only
+
+
+ ENDHV
+ End of high voltage
+ 2
+ 1
+ read-only
+
+
+ READY
+ Flash memory module ready after low
+ power mode
+ 3
+ 1
+ read-only
+
+
+ WRPERR
+ Write protected error
+ 8
+ 1
+ read-write
+
+
+ PGAERR
+ Programming alignment
+ error
+ 9
+ 1
+ read-write
+
+
+ SIZERR
+ Size error
+ 10
+ 1
+ read-write
+
+
+ OPTVERR
+ Option validity error
+ 11
+ 1
+ read-write
+
+
+ RDERR
+ RDERR
+ 14
+ 1
+ read-write
+
+
+ NOTZEROERR
+ NOTZEROERR
+ 16
+ 1
+ read-write
+
+
+ FWWERR
+ FWWERR
+ 17
+ 1
+ read-write
+
+
+
+
+ OBR
+ OBR
+ Option byte register
+ 0x1C
+ 0x20
+ read-only
+ 0x00F80000
+
+
+ RDPRT
+ Read protection
+ 0
+ 8
+
+
+ BOR_LEV
+ BOR_LEV
+ 16
+ 4
+
+
+ SPRMOD
+ Selection of protection mode of WPR
+ bits
+ 8
+ 1
+
+
+
+
+ WRPR
+ WRPR
+ Write protection register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ WRP
+ Write protection
+ 0
+ 16
+
+
+
+
+
+
+ EXTI
+ External interrupt/event
+ controller
+ EXTI
+ 0x40010400
+
+ 0x0
+ 0x400
+ registers
+
+
+ PVD
+ PVD through EXTI line detection
+ 1
+
+
+ EXTI0_1
+ EXTI Line[1:0] interrupts
+ 5
+
+
+ EXTI2_3
+ EXTI Line[3:2] interrupts
+ 6
+
+
+ EXTI4_15
+ EXTI Line15 and EXTI4 interrupts
+ 7
+
+
+
+ IMR
+ IMR
+ Interrupt mask register
+ (EXTI_IMR)
+ 0x0
+ 0x20
+ read-write
+ 0xFF840000
+
+
+ IM0
+ Interrupt Mask on line 0
+ 0
+ 1
+
+
+ IM1
+ Interrupt Mask on line 1
+ 1
+ 1
+
+
+ IM2
+ Interrupt Mask on line 2
+ 2
+ 1
+
+
+ IM3
+ Interrupt Mask on line 3
+ 3
+ 1
+
+
+ IM4
+ Interrupt Mask on line 4
+ 4
+ 1
+
+
+ IM5
+ Interrupt Mask on line 5
+ 5
+ 1
+
+
+ IM6
+ Interrupt Mask on line 6
+ 6
+ 1
+
+
+ IM7
+ Interrupt Mask on line 7
+ 7
+ 1
+
+
+ IM8
+ Interrupt Mask on line 8
+ 8
+ 1
+
+
+ IM9
+ Interrupt Mask on line 9
+ 9
+ 1
+
+
+ IM10
+ Interrupt Mask on line 10
+ 10
+ 1
+
+
+ IM11
+ Interrupt Mask on line 11
+ 11
+ 1
+
+
+ IM12
+ Interrupt Mask on line 12
+ 12
+ 1
+
+
+ IM13
+ Interrupt Mask on line 13
+ 13
+ 1
+
+
+ IM14
+ Interrupt Mask on line 14
+ 14
+ 1
+
+
+ IM15
+ Interrupt Mask on line 15
+ 15
+ 1
+
+
+ IM16
+ Interrupt Mask on line 16
+ 16
+ 1
+
+
+ IM17
+ Interrupt Mask on line 17
+ 17
+ 1
+
+
+ IM18
+ Interrupt Mask on line 18
+ 18
+ 1
+
+
+ IM19
+ Interrupt Mask on line 19
+ 19
+ 1
+
+
+ IM20
+ Interrupt Mask on line 20
+ 20
+ 1
+
+
+ IM21
+ Interrupt Mask on line 21
+ 21
+ 1
+
+
+ IM22
+ Interrupt Mask on line 22
+ 22
+ 1
+
+
+ IM23
+ Interrupt Mask on line 23
+ 23
+ 1
+
+
+ IM24
+ Interrupt Mask on line 24
+ 24
+ 1
+
+
+ IM25
+ Interrupt Mask on line 25
+ 25
+ 1
+
+
+ IM26
+ Interrupt Mask on line 27
+ 26
+ 1
+
+
+ IM28
+ Interrupt Mask on line 27
+ 28
+ 1
+
+
+ IM29
+ Interrupt Mask on line 27
+ 29
+ 1
+
+
+
+
+ EMR
+ EMR
+ Event mask register (EXTI_EMR)
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EM0
+ Event Mask on line 0
+ 0
+ 1
+
+
+ EM1
+ Event Mask on line 1
+ 1
+ 1
+
+
+ EM2
+ Event Mask on line 2
+ 2
+ 1
+
+
+ EM3
+ Event Mask on line 3
+ 3
+ 1
+
+
+ EM4
+ Event Mask on line 4
+ 4
+ 1
+
+
+ EM5
+ Event Mask on line 5
+ 5
+ 1
+
+
+ EM6
+ Event Mask on line 6
+ 6
+ 1
+
+
+ EM7
+ Event Mask on line 7
+ 7
+ 1
+
+
+ EM8
+ Event Mask on line 8
+ 8
+ 1
+
+
+ EM9
+ Event Mask on line 9
+ 9
+ 1
+
+
+ EM10
+ Event Mask on line 10
+ 10
+ 1
+
+
+ EM11
+ Event Mask on line 11
+ 11
+ 1
+
+
+ EM12
+ Event Mask on line 12
+ 12
+ 1
+
+
+ EM13
+ Event Mask on line 13
+ 13
+ 1
+
+
+ EM14
+ Event Mask on line 14
+ 14
+ 1
+
+
+ EM15
+ Event Mask on line 15
+ 15
+ 1
+
+
+ EM16
+ Event Mask on line 16
+ 16
+ 1
+
+
+ EM17
+ Event Mask on line 17
+ 17
+ 1
+
+
+ EM18
+ Event Mask on line 18
+ 18
+ 1
+
+
+ EM19
+ Event Mask on line 19
+ 19
+ 1
+
+
+ EM20
+ Event Mask on line 20
+ 20
+ 1
+
+
+ EM21
+ Event Mask on line 21
+ 21
+ 1
+
+
+ EM22
+ Event Mask on line 22
+ 22
+ 1
+
+
+ EM23
+ Event Mask on line 23
+ 23
+ 1
+
+
+ EM24
+ Event Mask on line 24
+ 24
+ 1
+
+
+ EM25
+ Event Mask on line 25
+ 25
+ 1
+
+
+ EM26
+ Event Mask on line 26
+ 26
+ 1
+
+
+ EM28
+ Event Mask on line 28
+ 28
+ 1
+
+
+ EM29
+ Event Mask on line 29
+ 29
+ 1
+
+
+
+
+ RTSR
+ RTSR
+ Rising Trigger selection register
+ (EXTI_RTSR)
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ RT0
+ Rising trigger event configuration of
+ line 0
+ 0
+ 1
+
+
+ RT1
+ Rising trigger event configuration of
+ line 1
+ 1
+ 1
+
+
+ RT2
+ Rising trigger event configuration of
+ line 2
+ 2
+ 1
+
+
+ RT3
+ Rising trigger event configuration of
+ line 3
+ 3
+ 1
+
+
+ RT4
+ Rising trigger event configuration of
+ line 4
+ 4
+ 1
+
+
+ RT5
+ Rising trigger event configuration of
+ line 5
+ 5
+ 1
+
+
+ RT6
+ Rising trigger event configuration of
+ line 6
+ 6
+ 1
+
+
+ RT7
+ Rising trigger event configuration of
+ line 7
+ 7
+ 1
+
+
+ RT8
+ Rising trigger event configuration of
+ line 8
+ 8
+ 1
+
+
+ RT9
+ Rising trigger event configuration of
+ line 9
+ 9
+ 1
+
+
+ RT10
+ Rising trigger event configuration of
+ line 10
+ 10
+ 1
+
+
+ RT11
+ Rising trigger event configuration of
+ line 11
+ 11
+ 1
+
+
+ RT12
+ Rising trigger event configuration of
+ line 12
+ 12
+ 1
+
+
+ RT13
+ Rising trigger event configuration of
+ line 13
+ 13
+ 1
+
+
+ RT14
+ Rising trigger event configuration of
+ line 14
+ 14
+ 1
+
+
+ RT15
+ Rising trigger event configuration of
+ line 15
+ 15
+ 1
+
+
+ RT16
+ Rising trigger event configuration of
+ line 16
+ 16
+ 1
+
+
+ RT17
+ Rising trigger event configuration of
+ line 17
+ 17
+ 1
+
+
+ RT19
+ Rising trigger event configuration of
+ line 19
+ 19
+ 1
+
+
+ RT20
+ Rising trigger event configuration of
+ line 20
+ 20
+ 1
+
+
+ RT21
+ Rising trigger event configuration of
+ line 21
+ 21
+ 1
+
+
+ RT22
+ Rising trigger event configuration of
+ line 22
+ 22
+ 1
+
+
+
+
+ FTSR
+ FTSR
+ Falling Trigger selection register
+ (EXTI_FTSR)
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FT0
+ Falling trigger event configuration of
+ line 0
+ 0
+ 1
+
+
+ FT1
+ Falling trigger event configuration of
+ line 1
+ 1
+ 1
+
+
+ FT2
+ Falling trigger event configuration of
+ line 2
+ 2
+ 1
+
+
+ FT3
+ Falling trigger event configuration of
+ line 3
+ 3
+ 1
+
+
+ FT4
+ Falling trigger event configuration of
+ line 4
+ 4
+ 1
+
+
+ FT5
+ Falling trigger event configuration of
+ line 5
+ 5
+ 1
+
+
+ FT6
+ Falling trigger event configuration of
+ line 6
+ 6
+ 1
+
+
+ FT7
+ Falling trigger event configuration of
+ line 7
+ 7
+ 1
+
+
+ FT8
+ Falling trigger event configuration of
+ line 8
+ 8
+ 1
+
+
+ FT9
+ Falling trigger event configuration of
+ line 9
+ 9
+ 1
+
+
+ FT10
+ Falling trigger event configuration of
+ line 10
+ 10
+ 1
+
+
+ FT11
+ Falling trigger event configuration of
+ line 11
+ 11
+ 1
+
+
+ FT12
+ Falling trigger event configuration of
+ line 12
+ 12
+ 1
+
+
+ FT13
+ Falling trigger event configuration of
+ line 13
+ 13
+ 1
+
+
+ FT14
+ Falling trigger event configuration of
+ line 14
+ 14
+ 1
+
+
+ FT15
+ Falling trigger event configuration of
+ line 15
+ 15
+ 1
+
+
+ FT16
+ Falling trigger event configuration of
+ line 16
+ 16
+ 1
+
+
+ FT17
+ Falling trigger event configuration of
+ line 17
+ 17
+ 1
+
+
+ FT19
+ Falling trigger event configuration of
+ line 19
+ 19
+ 1
+
+
+ FT20
+ Falling trigger event configuration of
+ line 20
+ 20
+ 1
+
+
+ FT21
+ Falling trigger event configuration of
+ line 21
+ 21
+ 1
+
+
+ FT22
+ Falling trigger event configuration of
+ line 22
+ 22
+ 1
+
+
+
+
+ SWIER
+ SWIER
+ Software interrupt event register
+ (EXTI_SWIER)
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SWI0
+ Software Interrupt on line
+ 0
+ 0
+ 1
+
+
+ SWI1
+ Software Interrupt on line
+ 1
+ 1
+ 1
+
+
+ SWI2
+ Software Interrupt on line
+ 2
+ 2
+ 1
+
+
+ SWI3
+ Software Interrupt on line
+ 3
+ 3
+ 1
+
+
+ SWI4
+ Software Interrupt on line
+ 4
+ 4
+ 1
+
+
+ SWI5
+ Software Interrupt on line
+ 5
+ 5
+ 1
+
+
+ SWI6
+ Software Interrupt on line
+ 6
+ 6
+ 1
+
+
+ SWI7
+ Software Interrupt on line
+ 7
+ 7
+ 1
+
+
+ SWI8
+ Software Interrupt on line
+ 8
+ 8
+ 1
+
+
+ SWI9
+ Software Interrupt on line
+ 9
+ 9
+ 1
+
+
+ SWI10
+ Software Interrupt on line
+ 10
+ 10
+ 1
+
+
+ SWI11
+ Software Interrupt on line
+ 11
+ 11
+ 1
+
+
+ SWI12
+ Software Interrupt on line
+ 12
+ 12
+ 1
+
+
+ SWI13
+ Software Interrupt on line
+ 13
+ 13
+ 1
+
+
+ SWI14
+ Software Interrupt on line
+ 14
+ 14
+ 1
+
+
+ SWI15
+ Software Interrupt on line
+ 15
+ 15
+ 1
+
+
+ SWI16
+ Software Interrupt on line
+ 16
+ 16
+ 1
+
+
+ SWI17
+ Software Interrupt on line
+ 17
+ 17
+ 1
+
+
+ SWI19
+ Software Interrupt on line
+ 19
+ 19
+ 1
+
+
+ SWI20
+ Software Interrupt on line
+ 20
+ 20
+ 1
+
+
+ SWI21
+ Software Interrupt on line
+ 21
+ 21
+ 1
+
+
+ SWI22
+ Software Interrupt on line
+ 22
+ 22
+ 1
+
+
+
+
+ PR
+ PR
+ Pending register (EXTI_PR)
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PIF0
+ Pending bit 0
+ 0
+ 1
+
+
+ PIF1
+ Pending bit 1
+ 1
+ 1
+
+
+ PIF2
+ Pending bit 2
+ 2
+ 1
+
+
+ PIF3
+ Pending bit 3
+ 3
+ 1
+
+
+ PIF4
+ Pending bit 4
+ 4
+ 1
+
+
+ PIF5
+ Pending bit 5
+ 5
+ 1
+
+
+ PIF6
+ Pending bit 6
+ 6
+ 1
+
+
+ PIF7
+ Pending bit 7
+ 7
+ 1
+
+
+ PIF8
+ Pending bit 8
+ 8
+ 1
+
+
+ PIF9
+ Pending bit 9
+ 9
+ 1
+
+
+ PIF10
+ Pending bit 10
+ 10
+ 1
+
+
+ PIF11
+ Pending bit 11
+ 11
+ 1
+
+
+ PIF12
+ Pending bit 12
+ 12
+ 1
+
+
+ PIF13
+ Pending bit 13
+ 13
+ 1
+
+
+ PIF14
+ Pending bit 14
+ 14
+ 1
+
+
+ PIF15
+ Pending bit 15
+ 15
+ 1
+
+
+ PIF16
+ Pending bit 16
+ 16
+ 1
+
+
+ PIF17
+ Pending bit 17
+ 17
+ 1
+
+
+ PIF19
+ Pending bit 19
+ 19
+ 1
+
+
+ PIF20
+ Pending bit 20
+ 20
+ 1
+
+
+ PIF21
+ Pending bit 21
+ 21
+ 1
+
+
+ PIF22
+ Pending bit 22
+ 22
+ 1
+
+
+
+
+
+
+ ADC
+ Analog-to-digital converter
+ ADC
+ 0x40012400
+
+ 0x0
+ 0x400
+ registers
+
+
+ EXTI2_3
+ EXTI Line[3:2] interrupts
+ 6
+
+
+
+ ISR
+ ISR
+ interrupt and status register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ADRDY
+ ADC ready
+ 0
+ 1
+
+
+ EOSMP
+ End of sampling flag
+ 1
+ 1
+
+
+ EOC
+ End of conversion flag
+ 2
+ 1
+
+
+ EOS
+ End of sequence flag
+ 3
+ 1
+
+
+ OVR
+ ADC overrun
+ 4
+ 1
+
+
+ AWD
+ Analog watchdog flag
+ 7
+ 1
+
+
+ EOCAL
+ End Of Calibration flag
+ 11
+ 1
+
+
+
+
+ IER
+ IER
+ interrupt enable register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ADRDYIE
+ ADC ready interrupt enable
+ 0
+ 1
+
+
+ EOSMPIE
+ End of sampling flag interrupt
+ enable
+ 1
+ 1
+
+
+ EOCIE
+ End of conversion interrupt
+ enable
+ 2
+ 1
+
+
+ EOSIE
+ End of conversion sequence interrupt
+ enable
+ 3
+ 1
+
+
+ OVRIE
+ Overrun interrupt enable
+ 4
+ 1
+
+
+ AWDIE
+ Analog watchdog interrupt
+ enable
+ 7
+ 1
+
+
+ EOCALIE
+ End of calibration interrupt
+ enable
+ 11
+ 1
+
+
+
+
+ CR
+ CR
+ control register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ADEN
+ ADC enable command
+ 0
+ 1
+
+
+ ADDIS
+ ADC disable command
+ 1
+ 1
+
+
+ ADSTART
+ ADC start conversion
+ command
+ 2
+ 1
+
+
+ ADSTP
+ ADC stop conversion
+ command
+ 4
+ 1
+
+
+ ADVREGEN
+ ADC Voltage Regulator
+ Enable
+ 28
+ 1
+
+
+ ADCAL
+ ADC calibration
+ 31
+ 1
+
+
+
+
+ CFGR1
+ CFGR1
+ configuration register 1
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AWDCH
+ Analog watchdog channel
+ selection
+ 26
+ 5
+
+
+ AWDEN
+ Analog watchdog enable
+ 23
+ 1
+
+
+ AWDSGL
+ Enable the watchdog on a single channel
+ or on all channels
+ 22
+ 1
+
+
+ DISCEN
+ Discontinuous mode
+ 16
+ 1
+
+
+ AUTOFF
+ Auto-off mode
+ 15
+ 1
+
+
+ AUTDLY
+ Auto-delayed conversion
+ mode
+ 14
+ 1
+
+
+ CONT
+ Single / continuous conversion
+ mode
+ 13
+ 1
+
+
+ OVRMOD
+ Overrun management mode
+ 12
+ 1
+
+
+ EXTEN
+ External trigger enable and polarity
+ selection
+ 10
+ 2
+
+
+ EXTSEL
+ External trigger selection
+ 6
+ 3
+
+
+ ALIGN
+ Data alignment
+ 5
+ 1
+
+
+ RES
+ Data resolution
+ 3
+ 2
+
+
+ SCANDIR
+ Scan sequence direction
+ 2
+ 1
+
+
+ DMACFG
+ Direct memery access
+ configuration
+ 1
+ 1
+
+
+ DMAEN
+ Direct memory access
+ enable
+ 0
+ 1
+
+
+
+
+ CFGR2
+ CFGR2
+ configuration register 2
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OVSE
+ Oversampler Enable
+ 0
+ 1
+
+
+ OVSR
+ Oversampling ratio
+ 2
+ 3
+
+
+ OVSS
+ Oversampling shift
+ 5
+ 4
+
+
+ TOVS
+ Triggered Oversampling
+ 9
+ 1
+
+
+ CKMODE
+ ADC clock mode
+ 30
+ 2
+
+
+
+
+ SMPR
+ SMPR
+ sampling time register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SMPR
+ Sampling time selection
+ 0
+ 3
+
+
+
+
+ TR
+ TR
+ watchdog threshold register
+ 0x20
+ 0x20
+ read-write
+ 0x0FFF0000
+
+
+ HT
+ Analog watchdog higher
+ threshold
+ 16
+ 12
+
+
+ LT
+ Analog watchdog lower
+ threshold
+ 0
+ 12
+
+
+
+
+ CHSELR
+ CHSELR
+ channel selection register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CHSEL18
+ Channel-x selection
+ 18
+ 1
+
+
+ CHSEL17
+ Channel-x selection
+ 17
+ 1
+
+
+ CHSEL16
+ Channel-x selection
+ 16
+ 1
+
+
+ CHSEL15
+ Channel-x selection
+ 15
+ 1
+
+
+ CHSEL14
+ Channel-x selection
+ 14
+ 1
+
+
+ CHSEL13
+ Channel-x selection
+ 13
+ 1
+
+
+ CHSEL12
+ Channel-x selection
+ 12
+ 1
+
+
+ CHSEL11
+ Channel-x selection
+ 11
+ 1
+
+
+ CHSEL10
+ Channel-x selection
+ 10
+ 1
+
+
+ CHSEL9
+ Channel-x selection
+ 9
+ 1
+
+
+ CHSEL8
+ Channel-x selection
+ 8
+ 1
+
+
+ CHSEL7
+ Channel-x selection
+ 7
+ 1
+
+
+ CHSEL6
+ Channel-x selection
+ 6
+ 1
+
+
+ CHSEL5
+ Channel-x selection
+ 5
+ 1
+
+
+ CHSEL4
+ Channel-x selection
+ 4
+ 1
+
+
+ CHSEL3
+ Channel-x selection
+ 3
+ 1
+
+
+ CHSEL2
+ Channel-x selection
+ 2
+ 1
+
+
+ CHSEL1
+ Channel-x selection
+ 1
+ 1
+
+
+ CHSEL0
+ Channel-x selection
+ 0
+ 1
+
+
+
+
+ DR
+ DR
+ data register
+ 0x40
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DATA
+ Converted data
+ 0
+ 16
+
+
+
+
+ CALFACT
+ CALFACT
+ ADC Calibration factor
+ 0xB4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CALFACT
+ Calibration factor
+ 0
+ 7
+
+
+
+
+ CCR
+ CCR
+ ADC common configuration
+ register
+ 0x308
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRESC
+ ADC prescaler
+ 18
+ 4
+
+
+ VREFEN
+ VREFINT enable
+ 22
+ 1
+
+
+ TSEN
+ Temperature sensor enable
+ 23
+ 1
+
+
+ LFMEN
+ Low Frequency Mode enable
+ 25
+ 1
+
+
+
+
+
+
+ DBGMCU
+ Debug support
+ DBGMCU
+ 0x40015800
+
+ 0x0
+ 0x400
+ registers
+
+
+ ADC_COMP
+ ADC and comparator 1 and 2
+ 12
+
+
+
+ IDCODE
+ IDCODE
+ MCU Device ID Code Register
+ 0x0
+ 0x20
+ read-only
+ 0x0
+
+
+ DEV_ID
+ Device Identifier
+ 0
+ 12
+
+
+ REV_ID
+ Revision Identifier
+ 16
+ 16
+
+
+
+
+ CR
+ CR
+ Debug MCU Configuration
+ Register
+ 0x4
+ 0x20
+ read-write
+ 0x0
+
+
+ DBG_STOP
+ Debug Stop Mode
+ 1
+ 1
+
+
+ DBG_STANDBY
+ Debug Standby Mode
+ 2
+ 1
+
+
+ DBG_SLEEP
+ Debug Sleep Mode
+ 0
+ 1
+
+
+
+
+ APB1_FZ
+ APB1_FZ
+ APB Low Freeze Register
+ 0x8
+ 0x20
+ read-write
+ 0x0
+
+
+ DBG_TIMER2_STOP
+ Debug Timer 2 stopped when Core is
+ halted
+ 0
+ 1
+
+
+ DBG_TIMER6_STOP
+ Debug Timer 6 stopped when Core is
+ halted
+ 4
+ 1
+
+
+ DBG_RTC_STOP
+ Debug RTC stopped when Core is
+ halted
+ 10
+ 1
+
+
+ DBG_WWDG_STOP
+ Debug Window Wachdog stopped when Core
+ is halted
+ 11
+ 1
+
+
+ DBG_IWDG_STOP
+ Debug Independent Wachdog stopped when
+ Core is halted
+ 12
+ 1
+
+
+ DBG_I2C1_STOP
+ I2C1 SMBUS timeout mode stopped when
+ core is halted
+ 21
+ 1
+
+
+ DBG_I2C2_STOP
+ I2C2 SMBUS timeout mode stopped when
+ core is halted
+ 22
+ 1
+
+
+ DBG_LPTIMER_STOP
+ LPTIM1 counter stopped when core is
+ halted
+ 31
+ 1
+
+
+
+
+ APB2_FZ
+ APB2_FZ
+ APB High Freeze Register
+ 0xC
+ 0x20
+ read-write
+ 0x0
+
+
+ DBG_TIMER21_STOP
+ Debug Timer 21 stopped when Core is
+ halted
+ 2
+ 1
+
+
+ DBG_TIMER22_STO
+ Debug Timer 22 stopped when Core is
+ halted
+ 6
+ 1
+
+
+
+
+
+
+ TIM2
+ General-purpose-timers
+ TIM
+ 0x40000000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CKD
+ Clock division
+ 8
+ 2
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ CMS
+ Center-aligned mode
+ selection
+ 5
+ 2
+
+
+ DIR
+ Direction
+ 4
+ 1
+
+
+ OPM
+ One-pulse mode
+ 3
+ 1
+
+
+ URS
+ Update request source
+ 2
+ 1
+
+
+ UDIS
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ TI1S
+ TI1 selection
+ 7
+ 1
+
+
+ MMS
+ Master mode selection
+ 4
+ 3
+
+
+ CCDS
+ Capture/compare DMA
+ selection
+ 3
+ 1
+
+
+
+
+ SMCR
+ SMCR
+ slave mode control register
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ ETP
+ External trigger polarity
+ 15
+ 1
+
+
+ ECE
+ External clock enable
+ 14
+ 1
+
+
+ ETPS
+ External trigger prescaler
+ 12
+ 2
+
+
+ ETF
+ External trigger filter
+ 8
+ 4
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ TS
+ Trigger selection
+ 4
+ 3
+
+
+ SMS
+ Slave mode selection
+ 0
+ 3
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ TDE
+ Trigger DMA request enable
+ 14
+ 1
+
+
+ CC4DE
+ Capture/Compare 4 DMA request
+ enable
+ 12
+ 1
+
+
+ CC3DE
+ Capture/Compare 3 DMA request
+ enable
+ 11
+ 1
+
+
+ CC2DE
+ Capture/Compare 2 DMA request
+ enable
+ 10
+ 1
+
+
+ CC1DE
+ Capture/Compare 1 DMA request
+ enable
+ 9
+ 1
+
+
+ UDE
+ Update DMA request enable
+ 8
+ 1
+
+
+ TIE
+ Trigger interrupt enable
+ 6
+ 1
+
+
+ CC4IE
+ Capture/Compare 4 interrupt
+ enable
+ 4
+ 1
+
+
+ CC3IE
+ Capture/Compare 3 interrupt
+ enable
+ 3
+ 1
+
+
+ CC2IE
+ Capture/Compare 2 interrupt
+ enable
+ 2
+ 1
+
+
+ CC1IE
+ Capture/Compare 1 interrupt
+ enable
+ 1
+ 1
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC4OF
+ Capture/Compare 4 overcapture
+ flag
+ 12
+ 1
+
+
+ CC3OF
+ Capture/Compare 3 overcapture
+ flag
+ 11
+ 1
+
+
+ CC2OF
+ Capture/compare 2 overcapture
+ flag
+ 10
+ 1
+
+
+ CC1OF
+ Capture/Compare 1 overcapture
+ flag
+ 9
+ 1
+
+
+ TIF
+ Trigger interrupt flag
+ 6
+ 1
+
+
+ CC4IF
+ Capture/Compare 4 interrupt
+ flag
+ 4
+ 1
+
+
+ CC3IF
+ Capture/Compare 3 interrupt
+ flag
+ 3
+ 1
+
+
+ CC2IF
+ Capture/Compare 2 interrupt
+ flag
+ 2
+ 1
+
+
+ CC1IF
+ Capture/compare 1 interrupt
+ flag
+ 1
+ 1
+
+
+ UIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ TG
+ Trigger generation
+ 6
+ 1
+
+
+ CC4G
+ Capture/compare 4
+ generation
+ 4
+ 1
+
+
+ CC3G
+ Capture/compare 3
+ generation
+ 3
+ 1
+
+
+ CC2G
+ Capture/compare 2
+ generation
+ 2
+ 1
+
+
+ CC1G
+ Capture/compare 1
+ generation
+ 1
+ 1
+
+
+ UG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CCMR1_Output
+ CCMR1_Output
+ capture/compare mode register 1 (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OC2CE
+ Output compare 2 clear
+ enable
+ 15
+ 1
+
+
+ OC2M
+ Output compare 2 mode
+ 12
+ 3
+
+
+ OC2PE
+ Output compare 2 preload
+ enable
+ 11
+ 1
+
+
+ OC2FE
+ Output compare 2 fast
+ enable
+ 10
+ 1
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ OC1CE
+ Output compare 1 clear
+ enable
+ 7
+ 1
+
+
+ OC1M
+ Output compare 1 mode
+ 4
+ 3
+
+
+ OC1PE
+ Output compare 1 preload
+ enable
+ 3
+ 1
+
+
+ OC1FE
+ Output compare 1 fast
+ enable
+ 2
+ 1
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR1_Input
+ CCMR1_Input
+ capture/compare mode register 1 (input
+ mode)
+ CCMR1_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC2F
+ Input capture 2 filter
+ 12
+ 4
+
+
+ IC2PSC
+ Input capture 2 prescaler
+ 10
+ 2
+
+
+ CC2S
+ Capture/compare 2
+ selection
+ 8
+ 2
+
+
+ IC1F
+ Input capture 1 filter
+ 4
+ 4
+
+
+ IC1PSC
+ Input capture 1 prescaler
+ 2
+ 2
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR2_Output
+ CCMR2_Output
+ capture/compare mode register 2 (output
+ mode)
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OC4CE
+ Output compare 4 clear
+ enable
+ 15
+ 1
+
+
+ OC4M
+ Output compare 4 mode
+ 12
+ 3
+
+
+ OC4PE
+ Output compare 4 preload
+ enable
+ 11
+ 1
+
+
+ OC4FE
+ Output compare 4 fast
+ enable
+ 10
+ 1
+
+
+ CC4S
+ Capture/Compare 4
+ selection
+ 8
+ 2
+
+
+ OC3CE
+ Output compare 3 clear
+ enable
+ 7
+ 1
+
+
+ OC3M
+ Output compare 3 mode
+ 4
+ 3
+
+
+ OC3PE
+ Output compare 3 preload
+ enable
+ 3
+ 1
+
+
+ OC3FE
+ Output compare 3 fast
+ enable
+ 2
+ 1
+
+
+ CC3S
+ Capture/Compare 3
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR2_Input
+ CCMR2_Input
+ capture/compare mode register 2 (input
+ mode)
+ CCMR2_Output
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC4F
+ Input capture 4 filter
+ 12
+ 4
+
+
+ IC4PSC
+ Input capture 4 prescaler
+ 10
+ 2
+
+
+ CC4S
+ Capture/Compare 4
+ selection
+ 8
+ 2
+
+
+ IC3F
+ Input capture 3 filter
+ 4
+ 4
+
+
+ IC3PSC
+ Input capture 3 prescaler
+ 2
+ 2
+
+
+ CC3S
+ Capture/Compare 3
+ selection
+ 0
+ 2
+
+
+
+
+ CCER
+ CCER
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC4NP
+ Capture/Compare 4 output
+ Polarity
+ 15
+ 1
+
+
+ CC4P
+ Capture/Compare 3 output
+ Polarity
+ 13
+ 1
+
+
+ CC4E
+ Capture/Compare 4 output
+ enable
+ 12
+ 1
+
+
+ CC3NP
+ Capture/Compare 3 output
+ Polarity
+ 11
+ 1
+
+
+ CC3P
+ Capture/Compare 3 output
+ Polarity
+ 9
+ 1
+
+
+ CC3E
+ Capture/Compare 3 output
+ enable
+ 8
+ 1
+
+
+ CC2NP
+ Capture/Compare 2 output
+ Polarity
+ 7
+ 1
+
+
+ CC2P
+ Capture/Compare 2 output
+ Polarity
+ 5
+ 1
+
+
+ CC2E
+ Capture/Compare 2 output
+ enable
+ 4
+ 1
+
+
+ CC1NP
+ Capture/Compare 1 output
+ Polarity
+ 3
+ 1
+
+
+ CC1P
+ Capture/Compare 1 output
+ Polarity
+ 1
+ 1
+
+
+ CC1E
+ Capture/Compare 1 output
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT_H
+ High counter value (TIM2
+ only)
+ 16
+ 16
+
+
+ CNT_L
+ Low counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ARR_H
+ High Auto-reload value (TIM2
+ only)
+ 16
+ 16
+
+
+ ARR_L
+ Low Auto-reload value
+ 0
+ 16
+
+
+
+
+ CCR1
+ CCR1
+ capture/compare register 1
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR1_H
+ High Capture/Compare 1 value (TIM2
+ only)
+ 16
+ 16
+
+
+ CCR1_L
+ Low Capture/Compare 1
+ value
+ 0
+ 16
+
+
+
+
+ CCR2
+ CCR2
+ capture/compare register 2
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR2_H
+ High Capture/Compare 2 value (TIM2
+ only)
+ 16
+ 16
+
+
+ CCR2_L
+ Low Capture/Compare 2
+ value
+ 0
+ 16
+
+
+
+
+ CCR3
+ CCR3
+ capture/compare register 3
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR3_H
+ High Capture/Compare value (TIM2
+ only)
+ 16
+ 16
+
+
+ CCR3_L
+ Low Capture/Compare value
+ 0
+ 16
+
+
+
+
+ CCR4
+ CCR4
+ capture/compare register 4
+ 0x40
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR4_H
+ High Capture/Compare value (TIM2
+ only)
+ 16
+ 16
+
+
+ CCR4_L
+ Low Capture/Compare value
+ 0
+ 16
+
+
+
+
+ DCR
+ DCR
+ DMA control register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DBL
+ DMA burst length
+ 8
+ 5
+
+
+ DBA
+ DMA base address
+ 0
+ 5
+
+
+
+
+ DMAR
+ DMAR
+ DMA address for full transfer
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMAB
+ DMA register for burst
+ accesses
+ 0
+ 16
+
+
+
+
+ OR
+ OR
+ TIM2 option register
+ 0x50
+ 0x20
+ read-write
+ 0x0000
+
+
+ ETR_RMP
+ Timer2 ETR remap
+ 0
+ 3
+
+
+ TI4_RMP
+ Internal trigger
+ 3
+ 2
+
+
+
+
+
+
+ TIM3
+ 0x40000400
+
+ TIM2
+ TIM2 global interrupt
+ 15
+
+
+
+ TIM6
+ Basic-timers
+ TIM
+ 0x40001000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM3
+ TIM3 global interrupt
+ 16
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ OPM
+ One-pulse mode
+ 3
+ 1
+
+
+ URS
+ Update request source
+ 2
+ 1
+
+
+ UDIS
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ MMS
+ Master mode selection
+ 4
+ 3
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ UDE
+ Update DMA request enable
+ 8
+ 1
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ UIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ UG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ Low counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ARR
+ Low Auto-reload value
+ 0
+ 16
+
+
+
+
+
+
+ TIM7
+ 0x40001400
+
+ TIM6_DAC
+ TIM6 global interrupt and DAC
+ 17
+
+
+
+ TIM21
+ General-purpose-timers
+ TIM
+ 0x40010800
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM7
+ TIM7 global interrupt and DAC
+ 18
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+ UDIS
+ Update disable
+ 1
+ 1
+
+
+ URS
+ Update request source
+ 2
+ 1
+
+
+ OPM
+ One-pulse mode
+ 3
+ 1
+
+
+ DIR
+ Direction
+ 4
+ 1
+
+
+ CMS
+ Center-aligned mode
+ selection
+ 5
+ 2
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ CKD
+ Clock division
+ 8
+ 2
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ MMS
+ Master mode selection
+ 4
+ 3
+
+
+
+
+ SMCR
+ SMCR
+ slave mode control register
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ SMS
+ Slave mode selection
+ 0
+ 3
+
+
+ TS
+ Trigger selection
+ 4
+ 3
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ ETF
+ External trigger filter
+ 8
+ 4
+
+
+ ETPS
+ External trigger prescaler
+ 12
+ 2
+
+
+ ECE
+ External clock enable
+ 14
+ 1
+
+
+ ETP
+ External trigger polarity
+ 15
+ 1
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ TIE
+ Trigger interrupt enable
+ 6
+ 1
+
+
+ CC2IE
+ Capture/Compare 2 interrupt
+ enable
+ 2
+ 1
+
+
+ CC1IE
+ Capture/Compare 1 interrupt
+ enable
+ 1
+ 1
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC2OF
+ Capture/compare 2 overcapture
+ flag
+ 10
+ 1
+
+
+ CC1OF
+ Capture/Compare 1 overcapture
+ flag
+ 9
+ 1
+
+
+ TIF
+ Trigger interrupt flag
+ 6
+ 1
+
+
+ CC2IF
+ Capture/Compare 2 interrupt
+ flag
+ 2
+ 1
+
+
+ CC1IF
+ Capture/compare 1 interrupt
+ flag
+ 1
+ 1
+
+
+ UIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ TG
+ Trigger generation
+ 6
+ 1
+
+
+ CC2G
+ Capture/compare 2
+ generation
+ 2
+ 1
+
+
+ CC1G
+ Capture/compare 1
+ generation
+ 1
+ 1
+
+
+ UG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CCMR1_Output
+ CCMR1_Output
+ capture/compare mode register (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OC2M
+ Output Compare 2 mode
+ 12
+ 3
+
+
+ OC2PE
+ Output Compare 2 preload
+ enable
+ 11
+ 1
+
+
+ OC2FE
+ Output Compare 2 fast
+ enable
+ 10
+ 1
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ OC1M
+ Output Compare 1 mode
+ 4
+ 3
+
+
+ OC1PE
+ Output Compare 1 preload
+ enable
+ 3
+ 1
+
+
+ OC1FE
+ Output Compare 1 fast
+ enable
+ 2
+ 1
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR1_Input
+ CCMR1_Input
+ capture/compare mode register 1 (input
+ mode)
+ CCMR1_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC2F
+ Input capture 2 filter
+ 12
+ 4
+
+
+ IC2PSC
+ Input capture 2 prescaler
+ 10
+ 2
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ IC1F
+ Input capture 1 filter
+ 4
+ 4
+
+
+ IC1PSC
+ Input capture 1 prescaler
+ 2
+ 2
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCER
+ CCER
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC2NP
+ Capture/Compare 2 output
+ Polarity
+ 7
+ 1
+
+
+ CC2P
+ Capture/Compare 2 output
+ Polarity
+ 5
+ 1
+
+
+ CC2E
+ Capture/Compare 2 output
+ enable
+ 4
+ 1
+
+
+ CC1NP
+ Capture/Compare 1 output
+ Polarity
+ 3
+ 1
+
+
+ CC1P
+ Capture/Compare 1 output
+ Polarity
+ 1
+ 1
+
+
+ CC1E
+ Capture/Compare 1 output
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ARR
+ Auto-reload value
+ 0
+ 16
+
+
+
+
+ CCR1
+ CCR1
+ capture/compare register 1
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR1
+ Capture/Compare 1 value
+ 0
+ 16
+
+
+
+
+ CCR2
+ CCR2
+ capture/compare register 2
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR2
+ Capture/Compare 2 value
+ 0
+ 16
+
+
+
+
+ OR
+ OR
+ TIM21 option register
+ 0x50
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ETR_RMP
+ Timer21 ETR remap
+ 0
+ 2
+
+
+ TI1_RMP
+ Timer21 TI1
+ 2
+ 3
+
+
+ TI2_RMP
+ Timer21 TI2
+ 5
+ 1
+
+
+
+
+
+
+ TIM22
+ General-purpose-timers
+ TIM
+ 0x40011400
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM21
+ TIMER21 global interrupt
+ 20
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+ UDIS
+ Update disable
+ 1
+ 1
+
+
+ URS
+ Update request source
+ 2
+ 1
+
+
+ OPM
+ One-pulse mode
+ 3
+ 1
+
+
+ DIR
+ Direction
+ 4
+ 1
+
+
+ CMS
+ Center-aligned mode
+ selection
+ 5
+ 2
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ CKD
+ Clock division
+ 8
+ 2
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ MMS
+ Master mode selection
+ 4
+ 3
+
+
+
+
+ SMCR
+ SMCR
+ slave mode control register
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ SMS
+ Slave mode selection
+ 0
+ 3
+
+
+ TS
+ Trigger selection
+ 4
+ 3
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ ETF
+ External trigger filter
+ 8
+ 4
+
+
+ ETPS
+ External trigger prescaler
+ 12
+ 2
+
+
+ ECE
+ External clock enable
+ 14
+ 1
+
+
+ ETP
+ External trigger polarity
+ 15
+ 1
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ TIE
+ Trigger interrupt enable
+ 6
+ 1
+
+
+ CC2IE
+ Capture/Compare 2 interrupt
+ enable
+ 2
+ 1
+
+
+ CC1IE
+ Capture/Compare 1 interrupt
+ enable
+ 1
+ 1
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC2OF
+ Capture/compare 2 overcapture
+ flag
+ 10
+ 1
+
+
+ CC1OF
+ Capture/Compare 1 overcapture
+ flag
+ 9
+ 1
+
+
+ TIF
+ Trigger interrupt flag
+ 6
+ 1
+
+
+ CC2IF
+ Capture/Compare 2 interrupt
+ flag
+ 2
+ 1
+
+
+ CC1IF
+ Capture/compare 1 interrupt
+ flag
+ 1
+ 1
+
+
+ UIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ TG
+ Trigger generation
+ 6
+ 1
+
+
+ CC2G
+ Capture/compare 2
+ generation
+ 2
+ 1
+
+
+ CC1G
+ Capture/compare 1
+ generation
+ 1
+ 1
+
+
+ UG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CCMR1_Output
+ CCMR1_Output
+ capture/compare mode register (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OC2M
+ Output Compare 2 mode
+ 12
+ 3
+
+
+ OC2PE
+ Output Compare 2 preload
+ enable
+ 11
+ 1
+
+
+ OC2FE
+ Output Compare 2 fast
+ enable
+ 10
+ 1
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ OC1M
+ Output Compare 1 mode
+ 4
+ 3
+
+
+ OC1PE
+ Output Compare 1 preload
+ enable
+ 3
+ 1
+
+
+ OC1FE
+ Output Compare 1 fast
+ enable
+ 2
+ 1
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR1_Input
+ CCMR1_Input
+ capture/compare mode register 1 (input
+ mode)
+ CCMR1_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC2F
+ Input capture 2 filter
+ 12
+ 4
+
+
+ IC2PSC
+ Input capture 2 prescaler
+ 10
+ 2
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ IC1F
+ Input capture 1 filter
+ 4
+ 4
+
+
+ IC1PSC
+ Input capture 1 prescaler
+ 2
+ 2
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCER
+ CCER
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC2NP
+ Capture/Compare 2 output
+ Polarity
+ 7
+ 1
+
+
+ CC2P
+ Capture/Compare 2 output
+ Polarity
+ 5
+ 1
+
+
+ CC2E
+ Capture/Compare 2 output
+ enable
+ 4
+ 1
+
+
+ CC1NP
+ Capture/Compare 1 output
+ Polarity
+ 3
+ 1
+
+
+ CC1P
+ Capture/Compare 1 output
+ Polarity
+ 1
+ 1
+
+
+ CC1E
+ Capture/Compare 1 output
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ARR
+ Auto-reload value
+ 0
+ 16
+
+
+
+
+ CCR1
+ CCR1
+ capture/compare register 1
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR1
+ Capture/Compare 1 value
+ 0
+ 16
+
+
+
+
+ CCR2
+ CCR2
+ capture/compare register 2
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR2
+ Capture/Compare 2 value
+ 0
+ 16
+
+
+
+
+ OR
+ OR
+ TIM22 option register
+ 0x50
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ETR_RMP
+ Timer22 ETR remap
+ 0
+ 2
+
+
+ TI1_RMP
+ Timer22 TI1
+ 2
+ 2
+
+
+
+
+
+
+ LPUSART1
+ Universal synchronous asynchronous receiver
+ transmitter
+ USART
+ 0x40004800
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM22
+ TIMER22 global interrupt
+ 22
+
+
+
+ CR1
+ CR1
+ Control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ M1
+ Word length
+ 28
+ 1
+
+
+ DEAT4
+ Driver Enable assertion
+ time
+ 25
+ 1
+
+
+ DEAT3
+ DEAT3
+ 24
+ 1
+
+
+ DEAT2
+ DEAT2
+ 23
+ 1
+
+
+ DEAT1
+ DEAT1
+ 22
+ 1
+
+
+ DEAT0
+ DEAT0
+ 21
+ 1
+
+
+ DEDT4
+ Driver Enable de-assertion
+ time
+ 20
+ 1
+
+
+ DEDT3
+ DEDT3
+ 19
+ 1
+
+
+ DEDT2
+ DEDT2
+ 18
+ 1
+
+
+ DEDT1
+ DEDT1
+ 17
+ 1
+
+
+ DEDT0
+ DEDT0
+ 16
+ 1
+
+
+ CMIE
+ Character match interrupt
+ enable
+ 14
+ 1
+
+
+ MME
+ Mute mode enable
+ 13
+ 1
+
+
+ M0
+ Word length
+ 12
+ 1
+
+
+ WAKE
+ Receiver wakeup method
+ 11
+ 1
+
+
+ PCE
+ Parity control enable
+ 10
+ 1
+
+
+ PS
+ Parity selection
+ 9
+ 1
+
+
+ PEIE
+ PE interrupt enable
+ 8
+ 1
+
+
+ TXEIE
+ interrupt enable
+ 7
+ 1
+
+
+ TCIE
+ Transmission complete interrupt
+ enable
+ 6
+ 1
+
+
+ RXNEIE
+ RXNE interrupt enable
+ 5
+ 1
+
+
+ IDLEIE
+ IDLE interrupt enable
+ 4
+ 1
+
+
+ TE
+ Transmitter enable
+ 3
+ 1
+
+
+ RE
+ Receiver enable
+ 2
+ 1
+
+
+ UESM
+ USART enable in Stop mode
+ 1
+ 1
+
+
+ UE
+ USART enable
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ Control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ ADD4_7
+ Address of the USART node
+ 28
+ 4
+
+
+ ADD0_3
+ Address of the USART node
+ 24
+ 4
+
+
+ MSBFIRST
+ Most significant bit first
+ 19
+ 1
+
+
+ TAINV
+ Binary data inversion
+ 18
+ 1
+
+
+ TXINV
+ TX pin active level
+ inversion
+ 17
+ 1
+
+
+ RXINV
+ RX pin active level
+ inversion
+ 16
+ 1
+
+
+ SWAP
+ Swap TX/RX pins
+ 15
+ 1
+
+
+ STOP
+ STOP bits
+ 12
+ 2
+
+
+ CLKEN
+ Clock enable
+ 11
+ 1
+
+
+ ADDM7
+ 7-bit Address Detection/4-bit Address
+ Detection
+ 4
+ 1
+
+
+
+
+ CR3
+ CR3
+ Control register 3
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ WUFIE
+ Wakeup from Stop mode interrupt
+ enable
+ 22
+ 1
+
+
+ WUS
+ Wakeup from Stop mode interrupt flag
+ selection
+ 20
+ 2
+
+
+ DEP
+ Driver enable polarity
+ selection
+ 15
+ 1
+
+
+ DEM
+ Driver enable mode
+ 14
+ 1
+
+
+ DDRE
+ DMA Disable on Reception
+ Error
+ 13
+ 1
+
+
+ OVRDIS
+ Overrun Disable
+ 12
+ 1
+
+
+ CTSIE
+ CTS interrupt enable
+ 10
+ 1
+
+
+ CTSE
+ CTS enable
+ 9
+ 1
+
+
+ RTSE
+ RTS enable
+ 8
+ 1
+
+
+ DMAT
+ DMA enable transmitter
+ 7
+ 1
+
+
+ DMAR
+ DMA enable receiver
+ 6
+ 1
+
+
+ HDSEL
+ Half-duplex selection
+ 3
+ 1
+
+
+ EIE
+ Error interrupt enable
+ 0
+ 1
+
+
+
+
+ BRR
+ BRR
+ Baud rate register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ BRR
+ BRR
+ 0
+ 20
+
+
+
+
+ RQR
+ RQR
+ Request register
+ 0x18
+ 0x20
+ write-only
+ 0x0000
+
+
+ RXFRQ
+ Receive data flush request
+ 3
+ 1
+
+
+ MMRQ
+ Mute mode request
+ 2
+ 1
+
+
+ SBKRQ
+ Send break request
+ 1
+ 1
+
+
+
+
+ ISR
+ ISR
+ Interrupt & status
+ register
+ 0x1C
+ 0x20
+ read-only
+ 0x00C0
+
+
+ REACK
+ REACK
+ 22
+ 1
+
+
+ TEACK
+ TEACK
+ 21
+ 1
+
+
+ WUF
+ WUF
+ 20
+ 1
+
+
+ RWU
+ RWU
+ 19
+ 1
+
+
+ SBKF
+ SBKF
+ 18
+ 1
+
+
+ CMF
+ CMF
+ 17
+ 1
+
+
+ BUSY
+ BUSY
+ 16
+ 1
+
+
+ CTS
+ CTS
+ 10
+ 1
+
+
+ CTSIF
+ CTSIF
+ 9
+ 1
+
+
+ TXE
+ TXE
+ 7
+ 1
+
+
+ TC
+ TC
+ 6
+ 1
+
+
+ RXNE
+ RXNE
+ 5
+ 1
+
+
+ IDLE
+ IDLE
+ 4
+ 1
+
+
+ ORE
+ ORE
+ 3
+ 1
+
+
+ NF
+ NF
+ 2
+ 1
+
+
+ FE
+ FE
+ 1
+ 1
+
+
+ PE
+ PE
+ 0
+ 1
+
+
+
+
+ ICR
+ ICR
+ Interrupt flag clear register
+ 0x20
+ 0x20
+ write-only
+ 0x0000
+
+
+ WUCF
+ Wakeup from Stop mode clear
+ flag
+ 20
+ 1
+
+
+ CMCF
+ Character match clear flag
+ 17
+ 1
+
+
+ CTSCF
+ CTS clear flag
+ 9
+ 1
+
+
+ TCCF
+ Transmission complete clear
+ flag
+ 6
+ 1
+
+
+ IDLECF
+ Idle line detected clear
+ flag
+ 4
+ 1
+
+
+ ORECF
+ Overrun error clear flag
+ 3
+ 1
+
+
+ NCF
+ Noise detected clear flag
+ 2
+ 1
+
+
+ FECF
+ Framing error clear flag
+ 1
+ 1
+
+
+ PECF
+ Parity error clear flag
+ 0
+ 1
+
+
+
+
+ RDR
+ RDR
+ Receive data register
+ 0x24
+ 0x20
+ read-only
+ 0x0000
+
+
+ RDR
+ Receive data value
+ 0
+ 9
+
+
+
+
+ TDR
+ TDR
+ Transmit data register
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ TDR
+ Transmit data value
+ 0
+ 9
+
+
+
+
+
+
+ NVIC
+ Nested Vectored Interrupt
+ Controller
+ NVIC
+ 0xE000E100
+
+ 0x0
+ 0x33D
+ registers
+
+
+
+ ISER
+ ISER
+ Interrupt Set Enable Register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ICER
+ ICER
+ Interrupt Clear Enable
+ Register
+ 0x80
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ISPR
+ ISPR
+ Interrupt Set-Pending Register
+ 0x100
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ICPR
+ ICPR
+ Interrupt Clear-Pending
+ Register
+ 0x180
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ IPR0
+ IPR0
+ Interrupt Priority Register 0
+ 0x300
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_0
+ priority for interrupt 0
+ 0
+ 8
+
+
+ PRI_1
+ priority for interrupt 1
+ 8
+ 8
+
+
+ PRI_2
+ priority for interrupt 2
+ 16
+ 8
+
+
+ PRI_3
+ priority for interrupt 3
+ 24
+ 8
+
+
+
+
+ IPR1
+ IPR1
+ Interrupt Priority Register 1
+ 0x304
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_4
+ priority for interrupt n
+ 0
+ 8
+
+
+ PRI_5
+ priority for interrupt n
+ 8
+ 8
+
+
+ PRI_6
+ priority for interrupt n
+ 16
+ 8
+
+
+ PRI_7
+ priority for interrupt n
+ 24
+ 8
+
+
+
+
+ IPR2
+ IPR2
+ Interrupt Priority Register 2
+ 0x308
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_8
+ priority for interrupt n
+ 0
+ 8
+
+
+ PRI_9
+ priority for interrupt n
+ 8
+ 8
+
+
+ PRI_10
+ priority for interrupt n
+ 16
+ 8
+
+
+ PRI_11
+ priority for interrupt n
+ 24
+ 8
+
+
+
+
+ IPR3
+ IPR3
+ Interrupt Priority Register 3
+ 0x30C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_12
+ priority for interrupt n
+ 0
+ 8
+
+
+ PRI_13
+ priority for interrupt n
+ 8
+ 8
+
+
+ PRI_14
+ priority for interrupt n
+ 16
+ 8
+
+
+ PRI_15
+ priority for interrupt n
+ 24
+ 8
+
+
+
+
+ IPR4
+ IPR4
+ Interrupt Priority Register 4
+ 0x310
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_16
+ priority for interrupt n
+ 0
+ 8
+
+
+ PRI_17
+ priority for interrupt n
+ 8
+ 8
+
+
+ PRI_18
+ priority for interrupt n
+ 16
+ 8
+
+
+ PRI_19
+ priority for interrupt n
+ 24
+ 8
+
+
+
+
+ IPR5
+ IPR5
+ Interrupt Priority Register 5
+ 0x314
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_20
+ priority for interrupt n
+ 0
+ 8
+
+
+ PRI_21
+ priority for interrupt n
+ 8
+ 8
+
+
+ PRI_22
+ priority for interrupt n
+ 16
+ 8
+
+
+ PRI_23
+ priority for interrupt n
+ 24
+ 8
+
+
+
+
+ IPR6
+ IPR6
+ Interrupt Priority Register 6
+ 0x318
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_24
+ priority for interrupt n
+ 0
+ 8
+
+
+ PRI_25
+ priority for interrupt n
+ 8
+ 8
+
+
+ PRI_26
+ priority for interrupt n
+ 16
+ 8
+
+
+ PRI_27
+ priority for interrupt n
+ 24
+ 8
+
+
+
+
+ IPR7
+ IPR7
+ Interrupt Priority Register 7
+ 0x31C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_28
+ priority for interrupt n
+ 0
+ 8
+
+
+ PRI_29
+ priority for interrupt n
+ 8
+ 8
+
+
+ PRI_30
+ priority for interrupt n
+ 16
+ 8
+
+
+ PRI_31
+ priority for interrupt n
+ 24
+ 8
+
+
+
+
+
+
+ USB_SRAM
+ Universal serial bus full-speed device
+ interface
+ USB
+ 0x40006000
+
+ 0x0
+ 0x800
+ registers
+
+
+
+ EP0R
+ EP0R
+ endpoint 0 register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+
+
+
+
+ EP1R
+ EP1R
+ endpoint 1 register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+
+
+
+
+ EP2R
+ EP2R
+ endpoint 2 register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+
+
+
+
+ EP3R
+ EP3R
+ endpoint 3 register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+
+
+
+
+ EP4R
+ EP4R
+ endpoint 4 register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+
+
+
+
+ EP5R
+ EP5R
+ endpoint 5 register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+
+
+
+
+ EP6R
+ EP6R
+ endpoint 6 register
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+
+
+
+
+ EP7R
+ EP7R
+ endpoint 7 register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+
+
+
+
+ CNTR
+ CNTR
+ control register
+ 0x40
+ 0x20
+ read-write
+ 0x00000003
+
+
+ FRES
+ Force USB Reset
+ 0
+ 1
+
+
+ PDWN
+ Power down
+ 1
+ 1
+
+
+ LPMODE
+ Low-power mode
+ 2
+ 1
+
+
+ FSUSP
+ Force suspend
+ 3
+ 1
+
+
+ RESUME
+ Resume request
+ 4
+ 1
+
+
+ L1RESUME
+ LPM L1 Resume request
+ 5
+ 1
+
+
+ L1REQM
+ LPM L1 state request interrupt
+ mask
+ 7
+ 1
+
+
+ ESOFM
+ Expected start of frame interrupt
+ mask
+ 8
+ 1
+
+
+ SOFM
+ Start of frame interrupt
+ mask
+ 9
+ 1
+
+
+ RESETM
+ USB reset interrupt mask
+ 10
+ 1
+
+
+ SUSPM
+ Suspend mode interrupt
+ mask
+ 11
+ 1
+
+
+ WKUPM
+ Wakeup interrupt mask
+ 12
+ 1
+
+
+ ERRM
+ Error interrupt mask
+ 13
+ 1
+
+
+ PMAOVRM
+ Packet memory area over / underrun
+ interrupt mask
+ 14
+ 1
+
+
+ CTRM
+ Correct transfer interrupt
+ mask
+ 15
+ 1
+
+
+
+
+ ISTR
+ ISTR
+ interrupt status register
+ 0x44
+ 0x20
+ 0x00000000
+
+
+ EP_ID
+ Endpoint Identifier
+ 0
+ 4
+ read-only
+
+
+ DIR
+ Direction of transaction
+ 4
+ 1
+ read-only
+
+
+ L1REQ
+ LPM L1 state request
+ 7
+ 1
+ read-write
+
+
+ ESOF
+ Expected start frame
+ 8
+ 1
+ read-write
+
+
+ SOF
+ start of frame
+ 9
+ 1
+ read-write
+
+
+ RESET
+ reset request
+ 10
+ 1
+ read-write
+
+
+ SUSP
+ Suspend mode request
+ 11
+ 1
+ read-write
+
+
+ WKUP
+ Wakeup
+ 12
+ 1
+ read-write
+
+
+ ERR
+ Error
+ 13
+ 1
+ read-write
+
+
+ PMAOVR
+ Packet memory area over /
+ underrun
+ 14
+ 1
+ read-write
+
+
+ CTR
+ Correct transfer
+ 15
+ 1
+ read-only
+
+
+
+
+ FNR
+ FNR
+ frame number register
+ 0x48
+ 0x20
+ read-only
+ 0x0000
+
+
+ FN
+ Frame number
+ 0
+ 11
+
+
+ LSOF
+ Lost SOF
+ 11
+ 2
+
+
+ LCK
+ Locked
+ 13
+ 1
+
+
+ RXDM
+ Receive data - line status
+ 14
+ 1
+
+
+ RXDP
+ Receive data + line status
+ 15
+ 1
+
+
+
+
+ DADDR
+ DADDR
+ device address
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ ADD
+ Device address
+ 0
+ 7
+
+
+ EF
+ Enable function
+ 7
+ 1
+
+
+
+
+ BTABLE
+ BTABLE
+ Buffer table address
+ 0x50
+ 0x20
+ read-write
+ 0x0000
+
+
+ BTABLE
+ Buffer table
+ 3
+ 13
+
+
+
+
+ LPMCSR
+ LPMCSR
+ LPM control and status
+ register
+ 0x54
+ 0x20
+ 0x0000
+
+
+ LPMEN
+ LPM support enable
+ 0
+ 1
+ read-write
+
+
+ LPMACK
+ LPM Token acknowledge
+ enable
+ 1
+ 1
+ read-write
+
+
+ REMWAKE
+ bRemoteWake value
+ 3
+ 1
+ read-only
+
+
+ BESL
+ BESL value
+ 4
+ 4
+ read-only
+
+
+
+
+ BCDR
+ BCDR
+ Battery charging detector
+ 0x58
+ 0x20
+ 0x0000
+
+
+ BCDEN
+ Battery charging detector
+ 0
+ 1
+ read-write
+
+
+ DCDEN
+ Data contact detection
+ 1
+ 1
+ read-write
+
+
+ PDEN
+ Primary detection
+ 2
+ 1
+ read-write
+
+
+ SDEN
+ Secondary detection
+ 3
+ 1
+ read-write
+
+
+ DCDET
+ Data contact detection
+ 4
+ 1
+ read-only
+
+
+ PDET
+ Primary detection
+ 5
+ 1
+ read-only
+
+
+ SDET
+ Secondary detection
+ 6
+ 1
+ read-only
+
+
+ PS2DET
+ DM pull-up detection
+ status
+ 7
+ 1
+ read-only
+
+
+ DPPU
+ DP pull-up control
+ 15
+ 1
+ read-write
+
+
+
+
+
+
+ MPU
+ Memory protection unit
+ MPU
+ 0xE000ED90
+
+ 0x0
+ 0x15
+ registers
+
+
+
+ MPU_TYPER
+ MPU_TYPER
+ MPU type register
+ 0x0
+ 0x20
+ read-only
+ 0X00000800
+
+
+ SEPARATE
+ Separate flag
+ 0
+ 1
+
+
+ DREGION
+ Number of MPU data regions
+ 8
+ 8
+
+
+ IREGION
+ Number of MPU instruction
+ regions
+ 16
+ 8
+
+
+
+
+ MPU_CTRL
+ MPU_CTRL
+ MPU control register
+ 0x4
+ 0x20
+ read-only
+ 0X00000000
+
+
+ ENABLE
+ Enables the MPU
+ 0
+ 1
+
+
+ HFNMIENA
+ Enables the operation of MPU during hard
+ fault
+ 1
+ 1
+
+
+ PRIVDEFENA
+ Enable priviliged software access to
+ default memory map
+ 2
+ 1
+
+
+
+
+ MPU_RNR
+ MPU_RNR
+ MPU region number register
+ 0x8
+ 0x20
+ read-write
+ 0X00000000
+
+
+ REGION
+ MPU region
+ 0
+ 8
+
+
+
+
+ MPU_RBAR
+ MPU_RBAR
+ MPU region base address
+ register
+ 0xC
+ 0x20
+ read-write
+ 0X00000000
+
+
+ REGION
+ MPU region field
+ 0
+ 4
+
+
+ VALID
+ MPU region number valid
+ 4
+ 1
+
+
+ ADDR
+ Region base address field
+ 5
+ 27
+
+
+
+
+ MPU_RASR
+ MPU_RASR
+ MPU region attribute and size
+ register
+ 0x10
+ 0x20
+ read-write
+ 0X00000000
+
+
+ ENABLE
+ Region enable bit.
+ 0
+ 1
+
+
+ SIZE
+ Size of the MPU protection
+ region
+ 1
+ 5
+
+
+ SRD
+ Subregion disable bits
+ 8
+ 8
+
+
+ B
+ memory attribute
+ 16
+ 1
+
+
+ C
+ memory attribute
+ 17
+ 1
+
+
+ S
+ Shareable memory attribute
+ 18
+ 1
+
+
+ TEX
+ memory attribute
+ 19
+ 3
+
+
+ AP
+ Access permission
+ 24
+ 3
+
+
+ XN
+ Instruction access disable
+ bit
+ 28
+ 1
+
+
+
+
+
+
+ STK
+ SysTick timer
+ STK
+ 0xE000E010
+
+ 0x0
+ 0x11
+ registers
+
+
+
+ CSR
+ CSR
+ SysTick control and status
+ register
+ 0x0
+ 0x20
+ read-write
+ 0X00000000
+
+
+ ENABLE
+ Counter enable
+ 0
+ 1
+
+
+ TICKINT
+ SysTick exception request
+ enable
+ 1
+ 1
+
+
+ CLKSOURCE
+ Clock source selection
+ 2
+ 1
+
+
+ COUNTFLAG
+ COUNTFLAG
+ 16
+ 1
+
+
+
+
+ RVR
+ RVR
+ SysTick reload value register
+ 0x4
+ 0x20
+ read-write
+ 0X00000000
+
+
+ RELOAD
+ RELOAD value
+ 0
+ 24
+
+
+
+
+ CVR
+ CVR
+ SysTick current value register
+ 0x8
+ 0x20
+ read-write
+ 0X00000000
+
+
+ CURRENT
+ Current counter value
+ 0
+ 24
+
+
+
+
+ CALIB
+ CALIB
+ SysTick calibration value
+ register
+ 0xC
+ 0x20
+ read-write
+ 0X00000000
+
+
+ TENMS
+ Calibration value
+ 0
+ 24
+
+
+ SKEW
+ SKEW flag: Indicates whether the TENMS
+ value is exact
+ 30
+ 1
+
+
+ NOREF
+ NOREF flag. Reads as zero
+ 31
+ 1
+
+
+
+
+
+
+ SCB
+ System control block
+ SCB
+ 0xE000ED00
+
+ 0x0
+ 0x41
+ registers
+
+
+
+ CPUID
+ CPUID
+ CPUID base register
+ 0x0
+ 0x20
+ read-only
+ 0x410FC241
+
+
+ Revision
+ Revision number
+ 0
+ 4
+
+
+ PartNo
+ Part number of the
+ processor
+ 4
+ 12
+
+
+ Architecture
+ Reads as 0xF
+ 16
+ 4
+
+
+ Variant
+ Variant number
+ 20
+ 4
+
+
+ Implementer
+ Implementer code
+ 24
+ 8
+
+
+
+
+ ICSR
+ ICSR
+ Interrupt control and state
+ register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ VECTACTIVE
+ Active vector
+ 0
+ 9
+
+
+ RETTOBASE
+ Return to base level
+ 11
+ 1
+
+
+ VECTPENDING
+ Pending vector
+ 12
+ 7
+
+
+ ISRPENDING
+ Interrupt pending flag
+ 22
+ 1
+
+
+ PENDSTCLR
+ SysTick exception clear-pending
+ bit
+ 25
+ 1
+
+
+ PENDSTSET
+ SysTick exception set-pending
+ bit
+ 26
+ 1
+
+
+ PENDSVCLR
+ PendSV clear-pending bit
+ 27
+ 1
+
+
+ PENDSVSET
+ PendSV set-pending bit
+ 28
+ 1
+
+
+ NMIPENDSET
+ NMI set-pending bit.
+ 31
+ 1
+
+
+
+
+ VTOR
+ VTOR
+ Vector table offset register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TBLOFF
+ Vector table base offset
+ field
+ 7
+ 25
+
+
+
+
+ AIRCR
+ AIRCR
+ Application interrupt and reset control
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ VECTCLRACTIVE
+ VECTCLRACTIVE
+ 1
+ 1
+
+
+ SYSRESETREQ
+ SYSRESETREQ
+ 2
+ 1
+
+
+ ENDIANESS
+ ENDIANESS
+ 15
+ 1
+
+
+ VECTKEYSTAT
+ Register key
+ 16
+ 16
+
+
+
+
+ SCR
+ SCR
+ System control register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SLEEPONEXIT
+ SLEEPONEXIT
+ 1
+ 1
+
+
+ SLEEPDEEP
+ SLEEPDEEP
+ 2
+ 1
+
+
+ SEVEONPEND
+ Send Event on Pending bit
+ 4
+ 1
+
+
+
+
+ CCR
+ CCR
+ Configuration and control
+ register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NONBASETHRDENA
+ Configures how the processor enters
+ Thread mode
+ 0
+ 1
+
+
+ USERSETMPEND
+ USERSETMPEND
+ 1
+ 1
+
+
+ UNALIGN__TRP
+ UNALIGN_ TRP
+ 3
+ 1
+
+
+ DIV_0_TRP
+ DIV_0_TRP
+ 4
+ 1
+
+
+ BFHFNMIGN
+ BFHFNMIGN
+ 8
+ 1
+
+
+ STKALIGN
+ STKALIGN
+ 9
+ 1
+
+
+
+
+ SHPR2
+ SHPR2
+ System handler priority
+ registers
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_11
+ Priority of system handler
+ 11
+ 24
+ 8
+
+
+
+
+ SHPR3
+ SHPR3
+ System handler priority
+ registers
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_14
+ Priority of system handler
+ 14
+ 16
+ 8
+
+
+ PRI_15
+ Priority of system handler
+ 15
+ 24
+ 8
+
+
+
+
+
+
+
diff --git a/board-support/stmicro-stm32/src/chips/STM32L0x3.svd b/board-support/stmicro-stm32/src/chips/STM32L0x3.svd
new file mode 100644
index 0000000..f128279
--- /dev/null
+++ b/board-support/stmicro-stm32/src/chips/STM32L0x3.svd
@@ -0,0 +1,22518 @@
+
+
+ STM32L0x3
+ 1.3
+ STM32L0x3
+
+
+ CM0+
+ r0p0
+ little
+ false
+ false
+ 3
+ false
+
+
+
+ 8
+
+ 32
+
+ 0x20
+ 0x0
+ 0xFFFFFFFF
+
+
+ AES
+ Advanced encryption standard hardware
+ accelerator
+ AES
+ 0x40026000
+
+ 0x0
+ 0x400
+ registers
+
+
+ AES_RNG_LPUART1
+ AES global interrupt RNG global interrupt and
+ LPUART1 global interrupt through
+ 29
+
+
+
+ CR
+ CR
+ control register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DMAOUTEN
+ Enable DMA management of data output
+ phase
+ 12
+ 1
+
+
+ DMAINEN
+ Enable DMA management of data input
+ phase
+ 11
+ 1
+
+
+ ERRIE
+ Error interrupt enable
+ 10
+ 1
+
+
+ CCFIE
+ CCF flag interrupt enable
+ 9
+ 1
+
+
+ ERRC
+ Error clear
+ 8
+ 1
+
+
+ CCFC
+ Computation Complete Flag
+ Clear
+ 7
+ 1
+
+
+ CHMOD
+ AES chaining mode
+ 5
+ 2
+
+
+ MODE
+ AES operating mode
+ 3
+ 2
+
+
+ DATATYPE
+ Data type selection (for data in and
+ data out to/from the cryptographic
+ block)
+ 1
+ 2
+
+
+ EN
+ AES enable
+ 0
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x4
+ 0x20
+ read-only
+ 0x00000000
+
+
+ WRERR
+ Write error flag
+ 2
+ 1
+
+
+ RDERR
+ Read error flag
+ 1
+ 1
+
+
+ CCF
+ Computation complete flag
+ 0
+ 1
+
+
+
+
+ DINR
+ DINR
+ data input register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AES_DINR
+ Data Input Register.
+ 0
+ 32
+
+
+
+
+ DOUTR
+ DOUTR
+ data output register
+ 0xC
+ 0x20
+ read-only
+ 0x00000000
+
+
+ AES_DOUTR
+ Data output register
+ 0
+ 32
+
+
+
+
+ KEYR0
+ KEYR0
+ key register 0
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AES_KEYR0
+ Data Output Register (LSB key
+ [31:0])
+ 0
+ 32
+
+
+
+
+ KEYR1
+ KEYR1
+ key register 1
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AES_KEYR1
+ AES key register (key
+ [63:32])
+ 0
+ 32
+
+
+
+
+ KEYR2
+ KEYR2
+ key register 2
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AES_KEYR2
+ AES key register (key
+ [95:64])
+ 0
+ 32
+
+
+
+
+ KEYR3
+ KEYR3
+ key register 3
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AES_KEYR3
+ AES key register (MSB key
+ [127:96])
+ 0
+ 32
+
+
+
+
+ IVR0
+ IVR0
+ initialization vector register
+ 0
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AES_IVR0
+ initialization vector register (LSB IVR
+ [31:0])
+ 0
+ 32
+
+
+
+
+ IVR1
+ IVR1
+ initialization vector register
+ 1
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AES_IVR1
+ Initialization Vector Register (IVR
+ [63:32])
+ 0
+ 32
+
+
+
+
+ IVR2
+ IVR2
+ initialization vector register
+ 2
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AES_IVR2
+ Initialization Vector Register (IVR
+ [95:64])
+ 0
+ 32
+
+
+
+
+ IVR3
+ IVR3
+ initialization vector register
+ 3
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AES_IVR3
+ Initialization Vector Register (MSB IVR
+ [127:96])
+ 0
+ 32
+
+
+
+
+
+
+ DAC
+ Digital-to-analog converter
+ DAC
+ 0x40007400
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CR
+ CR
+ control register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DMAUDRIE1
+ DAC channel1 DMA Underrun Interrupt
+ enable
+ 13
+ 1
+
+
+ DMAEN1
+ DAC channel1 DMA enable
+ 12
+ 1
+
+
+ MAMP1
+ DAC channel1 mask/amplitude
+ selector
+ 8
+ 4
+
+
+ WAVE1
+ DAC channel1 noise/triangle wave
+ generation enable
+ 6
+ 2
+
+
+ TSEL1
+ DAC channel1 trigger
+ selection
+ 3
+ 3
+
+
+ TEN1
+ DAC channel1 trigger
+ enable
+ 2
+ 1
+
+
+ BOFF1
+ DAC channel1 output buffer
+ disable
+ 1
+ 1
+
+
+ EN1
+ DAC channel1 enable
+ 0
+ 1
+
+
+
+
+ SWTRIGR
+ SWTRIGR
+ software trigger register
+ 0x4
+ 0x20
+ write-only
+ 0x00000000
+
+
+ SWTRIG1
+ DAC channel1 software
+ trigger
+ 0
+ 1
+
+
+
+
+ DHR12R1
+ DHR12R1
+ channel1 12-bit right-aligned data holding
+ register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC1DHR
+ DAC channel1 12-bit right-aligned
+ data
+ 0
+ 12
+
+
+
+
+ DHR12L1
+ DHR12L1
+ channel1 12-bit left-aligned data holding
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC1DHR
+ DAC channel1 12-bit left-aligned
+ data
+ 4
+ 12
+
+
+
+
+ DHR8R1
+ DHR8R1
+ channel1 8-bit right-aligned data holding
+ register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC1DHR
+ DAC channel1 8-bit right-aligned
+ data
+ 0
+ 8
+
+
+
+
+ DOR1
+ DOR1
+ channel1 data output register
+ 0x2C
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DACC1DOR
+ DAC channel1 data output
+ 0
+ 12
+
+
+
+
+ SR
+ SR
+ status register
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DMAUDR1
+ DAC channel1 DMA underrun
+ flag
+ 13
+ 1
+
+
+
+
+ DHR12R2
+ DHR12R2
+ channel2 12-bit right-aligned data holding
+ register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC2DHR
+ DAC channel2 12-bit right-aligned
+ data
+ 0
+ 12
+
+
+
+
+ DHR12L2
+ DHR12L2
+ channel2 12-bit left-aligned data holding
+ register
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC2DHR
+ DAC channel2 12-bit left-aligned
+ data
+ 4
+ 12
+
+
+
+
+ DHR8R2
+ DHR8R2
+ channel2 8-bit right-aligned data holding
+ register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC2DHR
+ DAC channel2 8-bit right-aligned
+ data
+ 0
+ 8
+
+
+
+
+ DHR12RD
+ DHR12RD
+ Dual DAC 12-bit right-aligned data holding
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC1DHR
+ DAC channel1 12-bit right-aligned
+ data
+ 0
+ 12
+
+
+ DACC2DHR
+ DAC channel2 12-bit right-aligned
+ data
+ 16
+ 12
+
+
+
+
+ DHR12LD
+ DHR12LD
+ Dual DAC 12-bit left-aligned data holding
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC1DHR
+ DAC channel1 12-bit left-aligned
+ data
+ 4
+ 12
+
+
+ DACC2DHR
+ DAC channel2 12-bit left-aligned
+ data
+ 20
+ 12
+
+
+
+
+ DHR8RD
+ DHR8RD
+ Dual DAC 8-bit right-aligned data holding
+ register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC1DHR
+ DAC channel1 8-bit right-aligned
+ data
+ 0
+ 8
+
+
+ DACC2DHR
+ DAC channel2 8-bit right-aligned
+ data
+ 8
+ 8
+
+
+
+
+ DOR2
+ DOR2
+ channel2 data output register
+ 0x30
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DACC2DOR
+ DAC channel2 data output
+ 0
+ 12
+
+
+
+
+
+
+ DMA1
+ Direct memory access controller
+ DMA
+ 0x40020000
+
+ 0x0
+ 0x400
+ registers
+
+
+ DMA1_Channel1
+ DMA1 Channel1 global interrupt
+ 9
+
+
+ DMA1_Channel2_3
+ DMA1 Channel2 and 3 interrupts
+ 10
+
+
+ DMA1_Channel4_7
+ DMA1 Channel4 to 7 interrupts
+ 11
+
+
+
+ ISR
+ ISR
+ interrupt status register
+ 0x0
+ 0x20
+ read-only
+ 0x00000000
+
+
+ TEIF7
+ Channel x transfer error flag (x = 1
+ ..7)
+ 27
+ 1
+
+
+ HTIF7
+ Channel x half transfer flag (x = 1
+ ..7)
+ 26
+ 1
+
+
+ TCIF7
+ Channel x transfer complete flag (x = 1
+ ..7)
+ 25
+ 1
+
+
+ GIF7
+ Channel x global interrupt flag (x = 1
+ ..7)
+ 24
+ 1
+
+
+ TEIF6
+ Channel x transfer error flag (x = 1
+ ..7)
+ 23
+ 1
+
+
+ HTIF6
+ Channel x half transfer flag (x = 1
+ ..7)
+ 22
+ 1
+
+
+ TCIF6
+ Channel x transfer complete flag (x = 1
+ ..7)
+ 21
+ 1
+
+
+ GIF6
+ Channel x global interrupt flag (x = 1
+ ..7)
+ 20
+ 1
+
+
+ TEIF5
+ Channel x transfer error flag (x = 1
+ ..7)
+ 19
+ 1
+
+
+ HTIF5
+ Channel x half transfer flag (x = 1
+ ..7)
+ 18
+ 1
+
+
+ TCIF5
+ Channel x transfer complete flag (x = 1
+ ..7)
+ 17
+ 1
+
+
+ GIF5
+ Channel x global interrupt flag (x = 1
+ ..7)
+ 16
+ 1
+
+
+ TEIF4
+ Channel x transfer error flag (x = 1
+ ..7)
+ 15
+ 1
+
+
+ HTIF4
+ Channel x half transfer flag (x = 1
+ ..7)
+ 14
+ 1
+
+
+ TCIF4
+ Channel x transfer complete flag (x = 1
+ ..7)
+ 13
+ 1
+
+
+ GIF4
+ Channel x global interrupt flag (x = 1
+ ..7)
+ 12
+ 1
+
+
+ TEIF3
+ Channel x transfer error flag (x = 1
+ ..7)
+ 11
+ 1
+
+
+ HTIF3
+ Channel x half transfer flag (x = 1
+ ..7)
+ 10
+ 1
+
+
+ TCIF3
+ Channel x transfer complete flag (x = 1
+ ..7)
+ 9
+ 1
+
+
+ GIF3
+ Channel x global interrupt flag (x = 1
+ ..7)
+ 8
+ 1
+
+
+ TEIF2
+ Channel x transfer error flag (x = 1
+ ..7)
+ 7
+ 1
+
+
+ HTIF2
+ Channel x half transfer flag (x = 1
+ ..7)
+ 6
+ 1
+
+
+ TCIF2
+ Channel x transfer complete flag (x = 1
+ ..7)
+ 5
+ 1
+
+
+ GIF2
+ Channel x global interrupt flag (x = 1
+ ..7)
+ 4
+ 1
+
+
+ TEIF1
+ Channel x transfer error flag (x = 1
+ ..7)
+ 3
+ 1
+
+
+ HTIF1
+ Channel x half transfer flag (x = 1
+ ..7)
+ 2
+ 1
+
+
+ TCIF1
+ Channel x transfer complete flag (x = 1
+ ..7)
+ 1
+ 1
+
+
+ GIF1
+ Channel x global interrupt flag (x = 1
+ ..7)
+ 0
+ 1
+
+
+
+
+ IFCR
+ IFCR
+ interrupt flag clear register
+ 0x4
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CTEIF7
+ Channel x transfer error clear (x = 1
+ ..7)
+ 27
+ 1
+
+
+ CHTIF7
+ Channel x half transfer clear (x = 1
+ ..7)
+ 26
+ 1
+
+
+ CTCIF7
+ Channel x transfer complete clear (x = 1
+ ..7)
+ 25
+ 1
+
+
+ CGIF7
+ Channel x global interrupt clear (x = 1
+ ..7)
+ 24
+ 1
+
+
+ CTEIF6
+ Channel x transfer error clear (x = 1
+ ..7)
+ 23
+ 1
+
+
+ CHTIF6
+ Channel x half transfer clear (x = 1
+ ..7)
+ 22
+ 1
+
+
+ CTCIF6
+ Channel x transfer complete clear (x = 1
+ ..7)
+ 21
+ 1
+
+
+ CGIF6
+ Channel x global interrupt clear (x = 1
+ ..7)
+ 20
+ 1
+
+
+ CTEIF5
+ Channel x transfer error clear (x = 1
+ ..7)
+ 19
+ 1
+
+
+ CHTIF5
+ Channel x half transfer clear (x = 1
+ ..7)
+ 18
+ 1
+
+
+ CTCIF5
+ Channel x transfer complete clear (x = 1
+ ..7)
+ 17
+ 1
+
+
+ CGIF5
+ Channel x global interrupt clear (x = 1
+ ..7)
+ 16
+ 1
+
+
+ CTEIF4
+ Channel x transfer error clear (x = 1
+ ..7)
+ 15
+ 1
+
+
+ CHTIF4
+ Channel x half transfer clear (x = 1
+ ..7)
+ 14
+ 1
+
+
+ CTCIF4
+ Channel x transfer complete clear (x = 1
+ ..7)
+ 13
+ 1
+
+
+ CGIF4
+ Channel x global interrupt clear (x = 1
+ ..7)
+ 12
+ 1
+
+
+ CTEIF3
+ Channel x transfer error clear (x = 1
+ ..7)
+ 11
+ 1
+
+
+ CHTIF3
+ Channel x half transfer clear (x = 1
+ ..7)
+ 10
+ 1
+
+
+ CTCIF3
+ Channel x transfer complete clear (x = 1
+ ..7)
+ 9
+ 1
+
+
+ CGIF3
+ Channel x global interrupt clear (x = 1
+ ..7)
+ 8
+ 1
+
+
+ CTEIF2
+ Channel x transfer error clear (x = 1
+ ..7)
+ 7
+ 1
+
+
+ CHTIF2
+ Channel x half transfer clear (x = 1
+ ..7)
+ 6
+ 1
+
+
+ CTCIF2
+ Channel x transfer complete clear (x = 1
+ ..7)
+ 5
+ 1
+
+
+ CGIF2
+ Channel x global interrupt clear (x = 1
+ ..7)
+ 4
+ 1
+
+
+ CTEIF1
+ Channel x transfer error clear (x = 1
+ ..7)
+ 3
+ 1
+
+
+ CHTIF1
+ Channel x half transfer clear (x = 1
+ ..7)
+ 2
+ 1
+
+
+ CTCIF1
+ Channel x transfer complete clear (x = 1
+ ..7)
+ 1
+ 1
+
+
+ CGIF1
+ Channel x global interrupt clear (x = 1
+ ..7)
+ 0
+ 1
+
+
+
+
+ CCR1
+ CCR1
+ channel x configuration
+ register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+ PL
+ Channel priority level
+ 12
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ HTIE
+ Half transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+
+
+ CNDTR1
+ CNDTR1
+ channel x number of data
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR1
+ CPAR1
+ channel x peripheral address
+ register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR1
+ CMAR1
+ channel x memory address
+ register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR2
+ CCR2
+ channel x configuration
+ register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+ PL
+ Channel priority level
+ 12
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ HTIE
+ Half transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+
+
+ CNDTR2
+ CNDTR2
+ channel x number of data
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR2
+ CPAR2
+ channel x peripheral address
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR2
+ CMAR2
+ channel x memory address
+ register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR3
+ CCR3
+ channel x configuration
+ register
+ 0x30
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+ PL
+ Channel priority level
+ 12
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ HTIE
+ Half transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+
+
+ CNDTR3
+ CNDTR3
+ channel x number of data
+ register
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR3
+ CPAR3
+ channel x peripheral address
+ register
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR3
+ CMAR3
+ channel x memory address
+ register
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR4
+ CCR4
+ channel x configuration
+ register
+ 0x44
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+ PL
+ Channel priority level
+ 12
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ HTIE
+ Half transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+
+
+ CNDTR4
+ CNDTR4
+ channel x number of data
+ register
+ 0x48
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR4
+ CPAR4
+ channel x peripheral address
+ register
+ 0x4C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR4
+ CMAR4
+ channel x memory address
+ register
+ 0x50
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR5
+ CCR5
+ channel x configuration
+ register
+ 0x58
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+ PL
+ Channel priority level
+ 12
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ HTIE
+ Half transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+
+
+ CNDTR5
+ CNDTR5
+ channel x number of data
+ register
+ 0x5C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR5
+ CPAR5
+ channel x peripheral address
+ register
+ 0x60
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR5
+ CMAR5
+ channel x memory address
+ register
+ 0x64
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR6
+ CCR6
+ channel x configuration
+ register
+ 0x6C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+ PL
+ Channel priority level
+ 12
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ HTIE
+ Half transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+
+
+ CNDTR6
+ CNDTR6
+ channel x number of data
+ register
+ 0x70
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR6
+ CPAR6
+ channel x peripheral address
+ register
+ 0x74
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR6
+ CMAR6
+ channel x memory address
+ register
+ 0x78
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR7
+ CCR7
+ channel x configuration
+ register
+ 0x80
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+ PL
+ Channel priority level
+ 12
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ HTIE
+ Half transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+
+
+ CNDTR7
+ CNDTR7
+ channel x number of data
+ register
+ 0x84
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR7
+ CPAR7
+ channel x peripheral address
+ register
+ 0x88
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR7
+ CMAR7
+ channel x memory address
+ register
+ 0x8C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CSELR
+ CSELR
+ channel selection register
+ 0xA8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ C7S
+ DMA channel 7 selection
+ 24
+ 4
+
+
+ C6S
+ DMA channel 6 selection
+ 20
+ 4
+
+
+ C5S
+ DMA channel 5 selection
+ 16
+ 4
+
+
+ C4S
+ DMA channel 4 selection
+ 12
+ 4
+
+
+ C3S
+ DMA channel 3 selection
+ 8
+ 4
+
+
+ C2S
+ DMA channel 2 selection
+ 4
+ 4
+
+
+ C1S
+ DMA channel 1 selection
+ 0
+ 4
+
+
+
+
+
+
+ CRC
+ Cyclic redundancy check calculation
+ unit
+ CRC
+ 0x40023000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ DR
+ DR
+ Data register
+ 0x0
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ DR
+ Data register bits
+ 0
+ 32
+
+
+
+
+ IDR
+ IDR
+ Independent data register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IDR
+ General-purpose 8-bit data register
+ bits
+ 0
+ 8
+
+
+
+
+ CR
+ CR
+ Control register
+ 0x8
+ 0x20
+ 0x00000000
+
+
+ REV_OUT
+ Reverse output data
+ 7
+ 1
+ read-write
+
+
+ REV_IN
+ Reverse input data
+ 5
+ 2
+ read-write
+
+
+ POLYSIZE
+ Polynomial size
+ 3
+ 2
+ read-write
+
+
+ RESET
+ RESET bit
+ 0
+ 1
+ write-only
+
+
+
+
+ INIT
+ INIT
+ Initial CRC value
+ 0x10
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ CRC_INIT
+ Programmable initial CRC
+ value
+ 0
+ 32
+
+
+
+
+ POL
+ POL
+ polynomial
+ 0x14
+ 0x20
+ read-write
+ 0x04C11DB7
+
+
+ Polynomialcoefficients
+ Programmable polynomial
+ 0
+ 32
+
+
+
+
+
+
+ GPIOA
+ General-purpose I/Os
+ GPIO
+ 0x50000000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ MODER
+ MODER
+ GPIO port mode register
+ 0x0
+ 0x20
+ read-write
+ 0xEBFFFCFF
+
+
+ MODE0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+ MODE1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ MODE2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ MODE3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ MODE4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ MODE5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ MODE6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ MODE7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ MODE8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ MODE9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ MODE10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ MODE11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ MODE12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ MODE13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ MODE14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ MODE15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+
+
+ OTYPER
+ OTYPER
+ GPIO port output type register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OT15
+ Port x configuration bits (y =
+ 0..15)
+ 15
+ 1
+
+
+ OT14
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 1
+
+
+ OT13
+ Port x configuration bits (y =
+ 0..15)
+ 13
+ 1
+
+
+ OT12
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 1
+
+
+ OT11
+ Port x configuration bits (y =
+ 0..15)
+ 11
+ 1
+
+
+ OT10
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 1
+
+
+ OT9
+ Port x configuration bits (y =
+ 0..15)
+ 9
+ 1
+
+
+ OT8
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 1
+
+
+ OT7
+ Port x configuration bits (y =
+ 0..15)
+ 7
+ 1
+
+
+ OT6
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 1
+
+
+ OT5
+ Port x configuration bits (y =
+ 0..15)
+ 5
+ 1
+
+
+ OT4
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 1
+
+
+ OT3
+ Port x configuration bits (y =
+ 0..15)
+ 3
+ 1
+
+
+ OT2
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 1
+
+
+ OT1
+ Port x configuration bits (y =
+ 0..15)
+ 1
+ 1
+
+
+ OT0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ OSPEEDR
+ OSPEEDR
+ GPIO port output speed
+ register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OSPEED15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ OSPEED14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ OSPEED13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ OSPEED12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ OSPEED11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ OSPEED10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ OSPEED9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ OSPEED8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ OSPEED7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ OSPEED6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ OSPEED5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ OSPEED4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ OSPEED3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ OSPEED2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ OSPEED1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ OSPEED0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ PUPDR
+ PUPDR
+ GPIO port pull-up/pull-down
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x24000000
+
+
+ PUPD15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ PUPD14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ PUPD13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ PUPD12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ PUPD11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ PUPD10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ PUPD9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ PUPD8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ PUPD7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ PUPD6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ PUPD5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ PUPD4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ PUPD3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ PUPD2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ PUPD1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ PUPD0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ IDR
+ IDR
+ GPIO port input data register
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ ID15
+ Port input data bit (y =
+ 0..15)
+ 15
+ 1
+
+
+ ID14
+ Port input data bit (y =
+ 0..15)
+ 14
+ 1
+
+
+ ID13
+ Port input data bit (y =
+ 0..15)
+ 13
+ 1
+
+
+ ID12
+ Port input data bit (y =
+ 0..15)
+ 12
+ 1
+
+
+ ID11
+ Port input data bit (y =
+ 0..15)
+ 11
+ 1
+
+
+ ID10
+ Port input data bit (y =
+ 0..15)
+ 10
+ 1
+
+
+ ID9
+ Port input data bit (y =
+ 0..15)
+ 9
+ 1
+
+
+ ID8
+ Port input data bit (y =
+ 0..15)
+ 8
+ 1
+
+
+ ID7
+ Port input data bit (y =
+ 0..15)
+ 7
+ 1
+
+
+ ID6
+ Port input data bit (y =
+ 0..15)
+ 6
+ 1
+
+
+ ID5
+ Port input data bit (y =
+ 0..15)
+ 5
+ 1
+
+
+ ID4
+ Port input data bit (y =
+ 0..15)
+ 4
+ 1
+
+
+ ID3
+ Port input data bit (y =
+ 0..15)
+ 3
+ 1
+
+
+ ID2
+ Port input data bit (y =
+ 0..15)
+ 2
+ 1
+
+
+ ID1
+ Port input data bit (y =
+ 0..15)
+ 1
+ 1
+
+
+ ID0
+ Port input data bit (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ ODR
+ ODR
+ GPIO port output data register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OD15
+ Port output data bit (y =
+ 0..15)
+ 15
+ 1
+
+
+ OD14
+ Port output data bit (y =
+ 0..15)
+ 14
+ 1
+
+
+ OD13
+ Port output data bit (y =
+ 0..15)
+ 13
+ 1
+
+
+ OD12
+ Port output data bit (y =
+ 0..15)
+ 12
+ 1
+
+
+ OD11
+ Port output data bit (y =
+ 0..15)
+ 11
+ 1
+
+
+ OD10
+ Port output data bit (y =
+ 0..15)
+ 10
+ 1
+
+
+ OD9
+ Port output data bit (y =
+ 0..15)
+ 9
+ 1
+
+
+ OD8
+ Port output data bit (y =
+ 0..15)
+ 8
+ 1
+
+
+ OD7
+ Port output data bit (y =
+ 0..15)
+ 7
+ 1
+
+
+ OD6
+ Port output data bit (y =
+ 0..15)
+ 6
+ 1
+
+
+ OD5
+ Port output data bit (y =
+ 0..15)
+ 5
+ 1
+
+
+ OD4
+ Port output data bit (y =
+ 0..15)
+ 4
+ 1
+
+
+ OD3
+ Port output data bit (y =
+ 0..15)
+ 3
+ 1
+
+
+ OD2
+ Port output data bit (y =
+ 0..15)
+ 2
+ 1
+
+
+ OD1
+ Port output data bit (y =
+ 0..15)
+ 1
+ 1
+
+
+ OD0
+ Port output data bit (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ BSRR
+ BSRR
+ GPIO port bit set/reset
+ register
+ 0x18
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BR15
+ Port x reset bit y (y =
+ 0..15)
+ 31
+ 1
+
+
+ BR14
+ Port x reset bit y (y =
+ 0..15)
+ 30
+ 1
+
+
+ BR13
+ Port x reset bit y (y =
+ 0..15)
+ 29
+ 1
+
+
+ BR12
+ Port x reset bit y (y =
+ 0..15)
+ 28
+ 1
+
+
+ BR11
+ Port x reset bit y (y =
+ 0..15)
+ 27
+ 1
+
+
+ BR10
+ Port x reset bit y (y =
+ 0..15)
+ 26
+ 1
+
+
+ BR9
+ Port x reset bit y (y =
+ 0..15)
+ 25
+ 1
+
+
+ BR8
+ Port x reset bit y (y =
+ 0..15)
+ 24
+ 1
+
+
+ BR7
+ Port x reset bit y (y =
+ 0..15)
+ 23
+ 1
+
+
+ BR6
+ Port x reset bit y (y =
+ 0..15)
+ 22
+ 1
+
+
+ BR5
+ Port x reset bit y (y =
+ 0..15)
+ 21
+ 1
+
+
+ BR4
+ Port x reset bit y (y =
+ 0..15)
+ 20
+ 1
+
+
+ BR3
+ Port x reset bit y (y =
+ 0..15)
+ 19
+ 1
+
+
+ BR2
+ Port x reset bit y (y =
+ 0..15)
+ 18
+ 1
+
+
+ BR1
+ Port x reset bit y (y =
+ 0..15)
+ 17
+ 1
+
+
+ BR0
+ Port x reset bit y (y =
+ 0..15)
+ 16
+ 1
+
+
+ BS15
+ Port x set bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ BS14
+ Port x set bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ BS13
+ Port x set bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ BS12
+ Port x set bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ BS11
+ Port x set bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ BS10
+ Port x set bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ BS9
+ Port x set bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ BS8
+ Port x set bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ BS7
+ Port x set bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ BS6
+ Port x set bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ BS5
+ Port x set bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ BS4
+ Port x set bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ BS3
+ Port x set bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ BS2
+ Port x set bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ BS1
+ Port x set bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ BS0
+ Port x set bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ LCKR
+ LCKR
+ GPIO port configuration lock
+ register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LCKK
+ Port x lock bit y (y=
+ 0..15)
+ 16
+ 1
+
+
+ LCK15
+ Port x lock bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ LCK14
+ Port x lock bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ LCK13
+ Port x lock bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ LCK12
+ Port x lock bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ LCK11
+ Port x lock bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ LCK10
+ Port x lock bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ LCK9
+ Port x lock bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ LCK8
+ Port x lock bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ LCK7
+ Port x lock bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ LCK6
+ Port x lock bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ LCK5
+ Port x lock bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ LCK4
+ Port x lock bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ LCK3
+ Port x lock bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ LCK2
+ Port x lock bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ LCK1
+ Port x lock bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ LCK0
+ Port x lock bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ AFRL
+ AFRL
+ GPIO alternate function low
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AFSEL7
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 28
+ 4
+
+
+ AFSEL6
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 24
+ 4
+
+
+ AFSEL5
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 20
+ 4
+
+
+ AFSEL4
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 16
+ 4
+
+
+ AFSEL3
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 12
+ 4
+
+
+ AFSEL2
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 8
+ 4
+
+
+ AFSEL1
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 4
+ 4
+
+
+ AFSEL0
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 0
+ 4
+
+
+
+
+ AFRH
+ AFRH
+ GPIO alternate function high
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AFSEL15
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 28
+ 4
+
+
+ AFSEL14
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 24
+ 4
+
+
+ AFSEL13
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 20
+ 4
+
+
+ AFSEL12
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 16
+ 4
+
+
+ AFSEL11
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 12
+ 4
+
+
+ AFSEL10
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 8
+ 4
+
+
+ AFSEL9
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 4
+ 4
+
+
+ AFSEL8
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 0
+ 4
+
+
+
+
+ BRR
+ BRR
+ GPIO port bit reset register
+ 0x28
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BR15
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 15
+ 1
+
+
+ BR14
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 14
+ 1
+
+
+ BR13
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 13
+ 1
+
+
+ BR12
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 12
+ 1
+
+
+ BR11
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 11
+ 1
+
+
+ BR10
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 10
+ 1
+
+
+ BR9
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 9
+ 1
+
+
+ BR8
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 8
+ 1
+
+
+ BR7
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 7
+ 1
+
+
+ BR6
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 6
+ 1
+
+
+ BR5
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 5
+ 1
+
+
+ BR4
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 4
+ 1
+
+
+ BR3
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 3
+ 1
+
+
+ BR2
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 2
+ 1
+
+
+ BR1
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 1
+ 1
+
+
+ BR0
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 0
+ 1
+
+
+
+
+
+
+ GPIOB
+ General-purpose I/Os
+ GPIO
+ 0x50000400
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ MODER
+ MODER
+ GPIO port mode register
+ 0x0
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ MODE15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ MODE14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ MODE13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ MODE12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ MODE11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ MODE10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ MODE9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ MODE8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ MODE7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ MODE6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ MODE5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ MODE4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ MODE3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ MODE2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ MODE1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ MODE0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ OTYPER
+ OTYPER
+ GPIO port output type register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OT15
+ Port x configuration bits (y =
+ 0..15)
+ 15
+ 1
+
+
+ OT14
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 1
+
+
+ OT13
+ Port x configuration bits (y =
+ 0..15)
+ 13
+ 1
+
+
+ OT12
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 1
+
+
+ OT11
+ Port x configuration bits (y =
+ 0..15)
+ 11
+ 1
+
+
+ OT10
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 1
+
+
+ OT9
+ Port x configuration bits (y =
+ 0..15)
+ 9
+ 1
+
+
+ OT8
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 1
+
+
+ OT7
+ Port x configuration bits (y =
+ 0..15)
+ 7
+ 1
+
+
+ OT6
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 1
+
+
+ OT5
+ Port x configuration bits (y =
+ 0..15)
+ 5
+ 1
+
+
+ OT4
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 1
+
+
+ OT3
+ Port x configuration bits (y =
+ 0..15)
+ 3
+ 1
+
+
+ OT2
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 1
+
+
+ OT1
+ Port x configuration bits (y =
+ 0..15)
+ 1
+ 1
+
+
+ OT0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ OSPEEDR
+ OSPEEDR
+ GPIO port output speed
+ register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OSPEED15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ OSPEED14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ OSPEED13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ OSPEED12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ OSPEED11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ OSPEED10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ OSPEED9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ OSPEED8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ OSPEED7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ OSPEED6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ OSPEED5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ OSPEED4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ OSPEED3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ OSPEED2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ OSPEED1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ OSPEED0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ PUPDR
+ PUPDR
+ GPIO port pull-up/pull-down
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PUPD15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ PUPD14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ PUPD13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ PUPD12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ PUPD11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ PUPD10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ PUPD9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ PUPD8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ PUPD7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ PUPD6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ PUPD5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ PUPD4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ PUPD3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ PUPD2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ PUPD1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ PUPD0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ IDR
+ IDR
+ GPIO port input data register
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ ID15
+ Port input data bit (y =
+ 0..15)
+ 15
+ 1
+
+
+ ID14
+ Port input data bit (y =
+ 0..15)
+ 14
+ 1
+
+
+ ID13
+ Port input data bit (y =
+ 0..15)
+ 13
+ 1
+
+
+ ID12
+ Port input data bit (y =
+ 0..15)
+ 12
+ 1
+
+
+ ID11
+ Port input data bit (y =
+ 0..15)
+ 11
+ 1
+
+
+ ID10
+ Port input data bit (y =
+ 0..15)
+ 10
+ 1
+
+
+ ID9
+ Port input data bit (y =
+ 0..15)
+ 9
+ 1
+
+
+ ID8
+ Port input data bit (y =
+ 0..15)
+ 8
+ 1
+
+
+ ID7
+ Port input data bit (y =
+ 0..15)
+ 7
+ 1
+
+
+ ID6
+ Port input data bit (y =
+ 0..15)
+ 6
+ 1
+
+
+ ID5
+ Port input data bit (y =
+ 0..15)
+ 5
+ 1
+
+
+ ID4
+ Port input data bit (y =
+ 0..15)
+ 4
+ 1
+
+
+ ID3
+ Port input data bit (y =
+ 0..15)
+ 3
+ 1
+
+
+ ID2
+ Port input data bit (y =
+ 0..15)
+ 2
+ 1
+
+
+ ID1
+ Port input data bit (y =
+ 0..15)
+ 1
+ 1
+
+
+ ID0
+ Port input data bit (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ ODR
+ ODR
+ GPIO port output data register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OD15
+ Port output data bit (y =
+ 0..15)
+ 15
+ 1
+
+
+ OD14
+ Port output data bit (y =
+ 0..15)
+ 14
+ 1
+
+
+ OD13
+ Port output data bit (y =
+ 0..15)
+ 13
+ 1
+
+
+ OD12
+ Port output data bit (y =
+ 0..15)
+ 12
+ 1
+
+
+ OD11
+ Port output data bit (y =
+ 0..15)
+ 11
+ 1
+
+
+ OD10
+ Port output data bit (y =
+ 0..15)
+ 10
+ 1
+
+
+ OD9
+ Port output data bit (y =
+ 0..15)
+ 9
+ 1
+
+
+ OD8
+ Port output data bit (y =
+ 0..15)
+ 8
+ 1
+
+
+ OD7
+ Port output data bit (y =
+ 0..15)
+ 7
+ 1
+
+
+ OD6
+ Port output data bit (y =
+ 0..15)
+ 6
+ 1
+
+
+ OD5
+ Port output data bit (y =
+ 0..15)
+ 5
+ 1
+
+
+ OD4
+ Port output data bit (y =
+ 0..15)
+ 4
+ 1
+
+
+ OD3
+ Port output data bit (y =
+ 0..15)
+ 3
+ 1
+
+
+ OD2
+ Port output data bit (y =
+ 0..15)
+ 2
+ 1
+
+
+ OD1
+ Port output data bit (y =
+ 0..15)
+ 1
+ 1
+
+
+ OD0
+ Port output data bit (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ BSRR
+ BSRR
+ GPIO port bit set/reset
+ register
+ 0x18
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BR15
+ Port x reset bit y (y =
+ 0..15)
+ 31
+ 1
+
+
+ BR14
+ Port x reset bit y (y =
+ 0..15)
+ 30
+ 1
+
+
+ BR13
+ Port x reset bit y (y =
+ 0..15)
+ 29
+ 1
+
+
+ BR12
+ Port x reset bit y (y =
+ 0..15)
+ 28
+ 1
+
+
+ BR11
+ Port x reset bit y (y =
+ 0..15)
+ 27
+ 1
+
+
+ BR10
+ Port x reset bit y (y =
+ 0..15)
+ 26
+ 1
+
+
+ BR9
+ Port x reset bit y (y =
+ 0..15)
+ 25
+ 1
+
+
+ BR8
+ Port x reset bit y (y =
+ 0..15)
+ 24
+ 1
+
+
+ BR7
+ Port x reset bit y (y =
+ 0..15)
+ 23
+ 1
+
+
+ BR6
+ Port x reset bit y (y =
+ 0..15)
+ 22
+ 1
+
+
+ BR5
+ Port x reset bit y (y =
+ 0..15)
+ 21
+ 1
+
+
+ BR4
+ Port x reset bit y (y =
+ 0..15)
+ 20
+ 1
+
+
+ BR3
+ Port x reset bit y (y =
+ 0..15)
+ 19
+ 1
+
+
+ BR2
+ Port x reset bit y (y =
+ 0..15)
+ 18
+ 1
+
+
+ BR1
+ Port x reset bit y (y =
+ 0..15)
+ 17
+ 1
+
+
+ BR0
+ Port x reset bit y (y =
+ 0..15)
+ 16
+ 1
+
+
+ BS15
+ Port x set bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ BS14
+ Port x set bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ BS13
+ Port x set bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ BS12
+ Port x set bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ BS11
+ Port x set bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ BS10
+ Port x set bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ BS9
+ Port x set bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ BS8
+ Port x set bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ BS7
+ Port x set bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ BS6
+ Port x set bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ BS5
+ Port x set bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ BS4
+ Port x set bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ BS3
+ Port x set bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ BS2
+ Port x set bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ BS1
+ Port x set bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ BS0
+ Port x set bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ LCKR
+ LCKR
+ GPIO port configuration lock
+ register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LCKK
+ Port x lock bit y (y=
+ 0..15)
+ 16
+ 1
+
+
+ LCK15
+ Port x lock bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ LCK14
+ Port x lock bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ LCK13
+ Port x lock bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ LCK12
+ Port x lock bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ LCK11
+ Port x lock bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ LCK10
+ Port x lock bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ LCK9
+ Port x lock bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ LCK8
+ Port x lock bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ LCK7
+ Port x lock bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ LCK6
+ Port x lock bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ LCK5
+ Port x lock bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ LCK4
+ Port x lock bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ LCK3
+ Port x lock bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ LCK2
+ Port x lock bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ LCK1
+ Port x lock bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ LCK0
+ Port x lock bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ AFRL
+ AFRL
+ GPIO alternate function low
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AFSEL7
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 28
+ 4
+
+
+ AFSEL6
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 24
+ 4
+
+
+ AFSEL5
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 20
+ 4
+
+
+ AFSEL4
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 16
+ 4
+
+
+ AFSEL3
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 12
+ 4
+
+
+ AFSEL2
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 8
+ 4
+
+
+ AFSEL1
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 4
+ 4
+
+
+ AFSEL0
+ Alternate function selection for port x
+ pin y (y = 0..7)
+ 0
+ 4
+
+
+
+
+ AFRH
+ AFRH
+ GPIO alternate function high
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AFSEL15
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 28
+ 4
+
+
+ AFSEL14
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 24
+ 4
+
+
+ AFSEL13
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 20
+ 4
+
+
+ AFSEL12
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 16
+ 4
+
+
+ AFSEL11
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 12
+ 4
+
+
+ AFSEL10
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 8
+ 4
+
+
+ AFSEL9
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 4
+ 4
+
+
+ AFSEL8
+ Alternate function selection for port x
+ pin y (y = 8..15)
+ 0
+ 4
+
+
+
+
+ BRR
+ BRR
+ GPIO port bit reset register
+ 0x28
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BR15
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 15
+ 1
+
+
+ BR14
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 14
+ 1
+
+
+ BR13
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 13
+ 1
+
+
+ BR12
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 12
+ 1
+
+
+ BR11
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 11
+ 1
+
+
+ BR10
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 10
+ 1
+
+
+ BR9
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 9
+ 1
+
+
+ BR8
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 8
+ 1
+
+
+ BR7
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 7
+ 1
+
+
+ BR6
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 6
+ 1
+
+
+ BR5
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 5
+ 1
+
+
+ BR4
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 4
+ 1
+
+
+ BR3
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 3
+ 1
+
+
+ BR2
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 2
+ 1
+
+
+ BR1
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 1
+ 1
+
+
+ BR0
+ Port x Reset bit y (y= 0 ..
+ 15)
+ 0
+ 1
+
+
+
+
+
+
+ GPIOC
+ 0x50000800
+
+
+ GPIOD
+ 0x50000C00
+
+
+ GPIOH
+ 0x50001C00
+
+
+ GPIOE
+ 0x50001000
+
+
+ LPTIM
+ Low power timer
+ LPTIM
+ 0x40007C00
+
+ 0x0
+ 0x400
+ registers
+
+
+ LPTIM1
+ LPTIMER1 interrupt through
+ EXTI29
+ 13
+
+
+
+ ISR
+ ISR
+ Interrupt and Status Register
+ 0x0
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DOWN
+ Counter direction change up to
+ down
+ 6
+ 1
+
+
+ UP
+ Counter direction change down to
+ up
+ 5
+ 1
+
+
+ ARROK
+ Autoreload register update
+ OK
+ 4
+ 1
+
+
+ CMPOK
+ Compare register update OK
+ 3
+ 1
+
+
+ EXTTRIG
+ External trigger edge
+ event
+ 2
+ 1
+
+
+ ARRM
+ Autoreload match
+ 1
+ 1
+
+
+ CMPM
+ Compare match
+ 0
+ 1
+
+
+
+
+ ICR
+ ICR
+ Interrupt Clear Register
+ 0x4
+ 0x20
+ write-only
+ 0x00000000
+
+
+ DOWNCF
+ Direction change to down Clear
+ Flag
+ 6
+ 1
+
+
+ UPCF
+ Direction change to UP Clear
+ Flag
+ 5
+ 1
+
+
+ ARROKCF
+ Autoreload register update OK Clear
+ Flag
+ 4
+ 1
+
+
+ CMPOKCF
+ Compare register update OK Clear
+ Flag
+ 3
+ 1
+
+
+ EXTTRIGCF
+ External trigger valid edge Clear
+ Flag
+ 2
+ 1
+
+
+ ARRMCF
+ Autoreload match Clear
+ Flag
+ 1
+ 1
+
+
+ CMPMCF
+ compare match Clear Flag
+ 0
+ 1
+
+
+
+
+ IER
+ IER
+ Interrupt Enable Register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DOWNIE
+ Direction change to down Interrupt
+ Enable
+ 6
+ 1
+
+
+ UPIE
+ Direction change to UP Interrupt
+ Enable
+ 5
+ 1
+
+
+ ARROKIE
+ Autoreload register update OK Interrupt
+ Enable
+ 4
+ 1
+
+
+ CMPOKIE
+ Compare register update OK Interrupt
+ Enable
+ 3
+ 1
+
+
+ EXTTRIGIE
+ External trigger valid edge Interrupt
+ Enable
+ 2
+ 1
+
+
+ ARRMIE
+ Autoreload match Interrupt
+ Enable
+ 1
+ 1
+
+
+ CMPMIE
+ Compare match Interrupt
+ Enable
+ 0
+ 1
+
+
+
+
+ CFGR
+ CFGR
+ Configuration Register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ENC
+ Encoder mode enable
+ 24
+ 1
+
+
+ COUNTMODE
+ counter mode enabled
+ 23
+ 1
+
+
+ PRELOAD
+ Registers update mode
+ 22
+ 1
+
+
+ WAVPOL
+ Waveform shape polarity
+ 21
+ 1
+
+
+ WAVE
+ Waveform shape
+ 20
+ 1
+
+
+ TIMOUT
+ Timeout enable
+ 19
+ 1
+
+
+ TRIGEN
+ Trigger enable and
+ polarity
+ 17
+ 2
+
+
+ TRIGSEL
+ Trigger selector
+ 13
+ 3
+
+
+ PRESC
+ Clock prescaler
+ 9
+ 3
+
+
+ TRGFLT
+ Configurable digital filter for
+ trigger
+ 6
+ 2
+
+
+ CKFLT
+ Configurable digital filter for external
+ clock
+ 3
+ 2
+
+
+ CKPOL
+ Clock Polarity
+ 1
+ 2
+
+
+ CKSEL
+ Clock selector
+ 0
+ 1
+
+
+
+
+ CR
+ CR
+ Control Register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNTSTRT
+ Timer start in continuous
+ mode
+ 2
+ 1
+
+
+ SNGSTRT
+ LPTIM start in single mode
+ 1
+ 1
+
+
+ ENABLE
+ LPTIM Enable
+ 0
+ 1
+
+
+
+
+ CMP
+ CMP
+ Compare Register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CMP
+ Compare value.
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ Autoreload Register
+ 0x18
+ 0x20
+ read-write
+ 0x00000001
+
+
+ ARR
+ Auto reload value.
+ 0
+ 16
+
+
+
+
+ CNT
+ CNT
+ Counter Register
+ 0x1C
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CNT
+ Counter value.
+ 0
+ 16
+
+
+
+
+
+
+ RNG
+ Random number generator
+ RNG
+ 0x40025000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CR
+ CR
+ control register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IE
+ Interrupt enable
+ 3
+ 1
+
+
+ RNGEN
+ Random number generator
+ enable
+ 2
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x4
+ 0x20
+ 0x00000000
+
+
+ SEIS
+ Seed error interrupt
+ status
+ 6
+ 1
+ read-write
+
+
+ CEIS
+ Clock error interrupt
+ status
+ 5
+ 1
+ read-write
+
+
+ SECS
+ Seed error current status
+ 2
+ 1
+ read-only
+
+
+ CECS
+ Clock error current status
+ 1
+ 1
+ read-only
+
+
+ DRDY
+ Data ready
+ 0
+ 1
+ read-only
+
+
+
+
+ DR
+ DR
+ data register
+ 0x8
+ 0x20
+ read-only
+ 0x00000000
+
+
+ RNDATA
+ Random data
+ 0
+ 32
+
+
+
+
+
+
+ RTC
+ Real-time clock
+ RTC
+ 0x40002800
+
+ 0x0
+ 0x400
+ registers
+
+
+ RTC
+ RTC global interrupt
+ 2
+
+
+
+ TR
+ TR
+ RTC time register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PM
+ AM/PM notation
+ 22
+ 1
+
+
+ HT
+ Hour tens in BCD format
+ 20
+ 2
+
+
+ HU
+ Hour units in BCD format
+ 16
+ 4
+
+
+ MNT
+ Minute tens in BCD format
+ 12
+ 3
+
+
+ MNU
+ Minute units in BCD format
+ 8
+ 4
+
+
+ ST
+ Second tens in BCD format
+ 4
+ 3
+
+
+ SU
+ Second units in BCD format
+ 0
+ 4
+
+
+
+
+ DR
+ DR
+ RTC date register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ YT
+ Year tens in BCD format
+ 20
+ 4
+
+
+ YU
+ Year units in BCD format
+ 16
+ 4
+
+
+ WDU
+ Week day units
+ 13
+ 3
+
+
+ MT
+ Month tens in BCD format
+ 12
+ 1
+
+
+ MU
+ Month units in BCD format
+ 8
+ 4
+
+
+ DT
+ Date tens in BCD format
+ 4
+ 2
+
+
+ DU
+ Date units in BCD format
+ 0
+ 4
+
+
+
+
+ CR
+ CR
+ RTC control register
+ 0x8
+ 0x20
+ 0x00000000
+
+
+ COE
+ Calibration output enable
+ 23
+ 1
+ read-write
+
+
+ OSEL
+ Output selection
+ 21
+ 2
+ read-write
+
+
+ POL
+ Output polarity
+ 20
+ 1
+ read-write
+
+
+ COSEL
+ Calibration output
+ selection
+ 19
+ 1
+ read-write
+
+
+ BKP
+ Backup
+ 18
+ 1
+ read-write
+
+
+ SUB1H
+ Subtract 1 hour (winter time
+ change)
+ 17
+ 1
+ write-only
+
+
+ ADD1H
+ Add 1 hour (summer time
+ change)
+ 16
+ 1
+ write-only
+
+
+ TSIE
+ Time-stamp interrupt
+ enable
+ 15
+ 1
+ read-write
+
+
+ WUTIE
+ Wakeup timer interrupt
+ enable
+ 14
+ 1
+ read-write
+
+
+ ALRBIE
+ Alarm B interrupt enable
+ 13
+ 1
+ read-write
+
+
+ ALRAIE
+ Alarm A interrupt enable
+ 12
+ 1
+ read-write
+
+
+ TSE
+ timestamp enable
+ 11
+ 1
+ read-write
+
+
+ WUTE
+ Wakeup timer enable
+ 10
+ 1
+ read-write
+
+
+ ALRBE
+ Alarm B enable
+ 9
+ 1
+ read-write
+
+
+ ALRAE
+ Alarm A enable
+ 8
+ 1
+ read-write
+
+
+ FMT
+ Hour format
+ 6
+ 1
+ read-write
+
+
+ BYPSHAD
+ Bypass the shadow
+ registers
+ 5
+ 1
+ read-write
+
+
+ REFCKON
+ RTC_REFIN reference clock detection
+ enable (50 or 60 Hz)
+ 4
+ 1
+ read-write
+
+
+ TSEDGE
+ Time-stamp event active
+ edge
+ 3
+ 1
+ read-write
+
+
+ WUCKSEL
+ Wakeup clock selection
+ 0
+ 3
+ read-write
+
+
+
+
+ ISR
+ ISR
+ RTC initialization and status
+ register
+ 0xC
+ 0x20
+ 0x00000000
+
+
+ TAMP2F
+ RTC_TAMP2 detection flag
+ 14
+ 1
+ read-write
+
+
+ TAMP1F
+ RTC_TAMP1 detection flag
+ 13
+ 1
+ read-write
+
+
+ TSOVF
+ Time-stamp overflow flag
+ 12
+ 1
+ read-write
+
+
+ TSF
+ Time-stamp flag
+ 11
+ 1
+ read-write
+
+
+ WUTF
+ Wakeup timer flag
+ 10
+ 1
+ read-write
+
+
+ ALRBF
+ Alarm B flag
+ 9
+ 1
+ read-write
+
+
+ ALRAF
+ Alarm A flag
+ 8
+ 1
+ read-write
+
+
+ INIT
+ Initialization mode
+ 7
+ 1
+ read-write
+
+
+ INITF
+ Initialization flag
+ 6
+ 1
+ read-only
+
+
+ RSF
+ Registers synchronization
+ flag
+ 5
+ 1
+ read-write
+
+
+ INITS
+ Initialization status flag
+ 4
+ 1
+ read-only
+
+
+ SHPF
+ Shift operation pending
+ 3
+ 1
+ read-only
+
+
+ WUTWF
+ Wakeup timer write flag
+ 2
+ 1
+ read-only
+
+
+ ALRBWF
+ Alarm B write flag
+ 1
+ 1
+ read-only
+
+
+ ALRAWF
+ Alarm A write flag
+ 0
+ 1
+ read-only
+
+
+
+
+ PRER
+ PRER
+ RTC prescaler register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PREDIV_A
+ Asynchronous prescaler
+ factor
+ 16
+ 7
+
+
+ PREDIV_S
+ Synchronous prescaler
+ factor
+ 0
+ 16
+
+
+
+
+ WUTR
+ WUTR
+ RTC wakeup timer register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ WUT
+ Wakeup auto-reload value
+ bits
+ 0
+ 16
+
+
+
+
+ ALRMAR
+ ALRMAR
+ RTC alarm A register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MSK4
+ Alarm A date mask
+ 31
+ 1
+
+
+ WDSEL
+ Week day selection
+ 30
+ 1
+
+
+ DT
+ Date tens in BCD format.
+ 28
+ 2
+
+
+ DU
+ Date units or day in BCD
+ format.
+ 24
+ 4
+
+
+ MSK3
+ Alarm A hours mask
+ 23
+ 1
+
+
+ PM
+ AM/PM notation
+ 22
+ 1
+
+
+ HT
+ Hour tens in BCD format.
+ 20
+ 2
+
+
+ HU
+ Hour units in BCD format.
+ 16
+ 4
+
+
+ MSK2
+ Alarm A minutes mask
+ 15
+ 1
+
+
+ MNT
+ Minute tens in BCD format.
+ 12
+ 3
+
+
+ MNU
+ Minute units in BCD
+ format.
+ 8
+ 4
+
+
+ MSK1
+ Alarm A seconds mask
+ 7
+ 1
+
+
+ ST
+ Second tens in BCD format.
+ 4
+ 3
+
+
+ SU
+ Second units in BCD
+ format.
+ 0
+ 4
+
+
+
+
+ ALRMBR
+ ALRMBR
+ RTC alarm B register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MSK4
+ Alarm B date mask
+ 31
+ 1
+
+
+ WDSEL
+ Week day selection
+ 30
+ 1
+
+
+ DT
+ Date tens in BCD format
+ 28
+ 2
+
+
+ DU
+ Date units or day in BCD
+ format
+ 24
+ 4
+
+
+ MSK3
+ Alarm B hours mask
+ 23
+ 1
+
+
+ PM
+ AM/PM notation
+ 22
+ 1
+
+
+ HT
+ Hour tens in BCD format
+ 20
+ 2
+
+
+ HU
+ Hour units in BCD format
+ 16
+ 4
+
+
+ MSK2
+ Alarm B minutes mask
+ 15
+ 1
+
+
+ MNT
+ Minute tens in BCD format
+ 12
+ 3
+
+
+ MNU
+ Minute units in BCD format
+ 8
+ 4
+
+
+ MSK1
+ Alarm B seconds mask
+ 7
+ 1
+
+
+ ST
+ Second tens in BCD format
+ 4
+ 3
+
+
+ SU
+ Second units in BCD format
+ 0
+ 4
+
+
+
+
+ WPR
+ WPR
+ write protection register
+ 0x24
+ 0x20
+ write-only
+ 0x00000000
+
+
+ KEY
+ Write protection key
+ 0
+ 8
+
+
+
+
+ SSR
+ SSR
+ RTC sub second register
+ 0x28
+ 0x20
+ read-only
+ 0x00000000
+
+
+ SS
+ Sub second value
+ 0
+ 16
+
+
+
+
+ SHIFTR
+ SHIFTR
+ RTC shift control register
+ 0x2C
+ 0x20
+ write-only
+ 0x00000000
+
+
+ ADD1S
+ Add one second
+ 31
+ 1
+
+
+ SUBFS
+ Subtract a fraction of a
+ second
+ 0
+ 15
+
+
+
+
+ TSTR
+ TSTR
+ RTC timestamp time register
+ 0x30
+ 0x20
+ read-only
+ 0x00000000
+
+
+ PM
+ AM/PM notation
+ 22
+ 1
+
+
+ HT
+ Hour tens in BCD format.
+ 20
+ 2
+
+
+ HU
+ Hour units in BCD format.
+ 16
+ 4
+
+
+ MNT
+ Minute tens in BCD format.
+ 12
+ 3
+
+
+ MNU
+ Minute units in BCD
+ format.
+ 8
+ 4
+
+
+ ST
+ Second tens in BCD format.
+ 4
+ 3
+
+
+ SU
+ Second units in BCD
+ format.
+ 0
+ 4
+
+
+
+
+ TSDR
+ TSDR
+ RTC timestamp date register
+ 0x34
+ 0x20
+ read-only
+ 0x00000000
+
+
+ WDU
+ Week day units
+ 13
+ 3
+
+
+ MT
+ Month tens in BCD format
+ 12
+ 1
+
+
+ MU
+ Month units in BCD format
+ 8
+ 4
+
+
+ DT
+ Date tens in BCD format
+ 4
+ 2
+
+
+ DU
+ Date units in BCD format
+ 0
+ 4
+
+
+
+
+ TSSSR
+ TSSSR
+ RTC time-stamp sub second
+ register
+ 0x38
+ 0x20
+ read-only
+ 0x00000000
+
+
+ SS
+ Sub second value
+ 0
+ 16
+
+
+
+
+ CALR
+ CALR
+ RTC calibration register
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CALP
+ Increase frequency of RTC by 488.5
+ ppm
+ 15
+ 1
+
+
+ CALW8
+ Use a 8-second calibration cycle
+ period
+ 14
+ 1
+
+
+ CALW16
+ Use a 16-second calibration cycle
+ period
+ 13
+ 1
+
+
+ CALM
+ Calibration minus
+ 0
+ 9
+
+
+
+
+ TAMPCR
+ TAMPCR
+ RTC tamper configuration
+ register
+ 0x40
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TAMP2MF
+ Tamper 2 mask flag
+ 21
+ 1
+
+
+ TAMP2NOERASE
+ Tamper 2 no erase
+ 20
+ 1
+
+
+ TAMP2IE
+ Tamper 2 interrupt enable
+ 19
+ 1
+
+
+ TAMP1MF
+ Tamper 1 mask flag
+ 18
+ 1
+
+
+ TAMP1NOERASE
+ Tamper 1 no erase
+ 17
+ 1
+
+
+ TAMP1IE
+ Tamper 1 interrupt enable
+ 16
+ 1
+
+
+ TAMPPUDIS
+ RTC_TAMPx pull-up disable
+ 15
+ 1
+
+
+ TAMPPRCH
+ RTC_TAMPx precharge
+ duration
+ 13
+ 2
+
+
+ TAMPFLT
+ RTC_TAMPx filter count
+ 11
+ 2
+
+
+ TAMPFREQ
+ Tamper sampling frequency
+ 8
+ 3
+
+
+ TAMPTS
+ Activate timestamp on tamper detection
+ event
+ 7
+ 1
+
+
+ TAMP2_TRG
+ Active level for RTC_TAMP2
+ input
+ 4
+ 1
+
+
+ TAMP2E
+ RTC_TAMP2 input detection
+ enable
+ 3
+ 1
+
+
+ TAMPIE
+ Tamper interrupt enable
+ 2
+ 1
+
+
+ TAMP1TRG
+ Active level for RTC_TAMP1
+ input
+ 1
+ 1
+
+
+ TAMP1E
+ RTC_TAMP1 input detection
+ enable
+ 0
+ 1
+
+
+
+
+ ALRMASSR
+ ALRMASSR
+ RTC alarm A sub second
+ register
+ 0x44
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MASKSS
+ Mask the most-significant bits starting
+ at this bit
+ 24
+ 4
+
+
+ SS
+ Sub seconds value
+ 0
+ 15
+
+
+
+
+ ALRMBSSR
+ ALRMBSSR
+ RTC alarm B sub second
+ register
+ 0x48
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MASKSS
+ Mask the most-significant bits starting
+ at this bit
+ 24
+ 4
+
+
+ SS
+ Sub seconds value
+ 0
+ 15
+
+
+
+
+ OR
+ OR
+ option register
+ 0x4C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ RTC_OUT_RMP
+ RTC_ALARM on PC13 output
+ type
+ 1
+ 1
+
+
+ RTC_ALARM_TYPE
+ RTC_ALARM on PC13 output
+ type
+ 0
+ 1
+
+
+
+
+ BKP0R
+ BKP0R
+ RTC backup registers
+ 0x50
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP1R
+ BKP1R
+ RTC backup registers
+ 0x54
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP2R
+ BKP2R
+ RTC backup registers
+ 0x58
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP3R
+ BKP3R
+ RTC backup registers
+ 0x5C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP4R
+ BKP4R
+ RTC backup registers
+ 0x60
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+
+
+ USART1
+ Universal synchronous asynchronous receiver
+ transmitter
+ USART
+ 0x40013800
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CR1
+ CR1
+ Control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ M1
+ Word length
+ 28
+ 1
+
+
+ EOBIE
+ End of Block interrupt
+ enable
+ 27
+ 1
+
+
+ RTOIE
+ Receiver timeout interrupt
+ enable
+ 26
+ 1
+
+
+ DEAT4
+ Driver Enable assertion
+ time
+ 25
+ 1
+
+
+ DEAT3
+ DEAT3
+ 24
+ 1
+
+
+ DEAT2
+ DEAT2
+ 23
+ 1
+
+
+ DEAT1
+ DEAT1
+ 22
+ 1
+
+
+ DEAT0
+ DEAT0
+ 21
+ 1
+
+
+ DEDT4
+ Driver Enable de-assertion
+ time
+ 20
+ 1
+
+
+ DEDT3
+ DEDT3
+ 19
+ 1
+
+
+ DEDT2
+ DEDT2
+ 18
+ 1
+
+
+ DEDT1
+ DEDT1
+ 17
+ 1
+
+
+ DEDT0
+ DEDT0
+ 16
+ 1
+
+
+ OVER8
+ Oversampling mode
+ 15
+ 1
+
+
+ CMIE
+ Character match interrupt
+ enable
+ 14
+ 1
+
+
+ MME
+ Mute mode enable
+ 13
+ 1
+
+
+ M0
+ Word length
+ 12
+ 1
+
+
+ WAKE
+ Receiver wakeup method
+ 11
+ 1
+
+
+ PCE
+ Parity control enable
+ 10
+ 1
+
+
+ PS
+ Parity selection
+ 9
+ 1
+
+
+ PEIE
+ PE interrupt enable
+ 8
+ 1
+
+
+ TXEIE
+ interrupt enable
+ 7
+ 1
+
+
+ TCIE
+ Transmission complete interrupt
+ enable
+ 6
+ 1
+
+
+ RXNEIE
+ RXNE interrupt enable
+ 5
+ 1
+
+
+ IDLEIE
+ IDLE interrupt enable
+ 4
+ 1
+
+
+ TE
+ Transmitter enable
+ 3
+ 1
+
+
+ RE
+ Receiver enable
+ 2
+ 1
+
+
+ UESM
+ USART enable in Stop mode
+ 1
+ 1
+
+
+ UE
+ USART enable
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ Control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ ADD4_7
+ Address of the USART node
+ 28
+ 4
+
+
+ ADD0_3
+ Address of the USART node
+ 24
+ 4
+
+
+ RTOEN
+ Receiver timeout enable
+ 23
+ 1
+
+
+ ABRMOD1
+ Auto baud rate mode
+ 22
+ 1
+
+
+ ABRMOD0
+ ABRMOD0
+ 21
+ 1
+
+
+ ABREN
+ Auto baud rate enable
+ 20
+ 1
+
+
+ MSBFIRST
+ Most significant bit first
+ 19
+ 1
+
+
+ TAINV
+ Binary data inversion
+ 18
+ 1
+
+
+ TXINV
+ TX pin active level
+ inversion
+ 17
+ 1
+
+
+ RXINV
+ RX pin active level
+ inversion
+ 16
+ 1
+
+
+ SWAP
+ Swap TX/RX pins
+ 15
+ 1
+
+
+ LINEN
+ LIN mode enable
+ 14
+ 1
+
+
+ STOP
+ STOP bits
+ 12
+ 2
+
+
+ CLKEN
+ Clock enable
+ 11
+ 1
+
+
+ CPOL
+ Clock polarity
+ 10
+ 1
+
+
+ CPHA
+ Clock phase
+ 9
+ 1
+
+
+ LBCL
+ Last bit clock pulse
+ 8
+ 1
+
+
+ LBDIE
+ LIN break detection interrupt
+ enable
+ 6
+ 1
+
+
+ LBDL
+ LIN break detection length
+ 5
+ 1
+
+
+ ADDM7
+ 7-bit Address Detection/4-bit Address
+ Detection
+ 4
+ 1
+
+
+
+
+ CR3
+ CR3
+ Control register 3
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ WUFIE
+ Wakeup from Stop mode interrupt
+ enable
+ 22
+ 1
+
+
+ WUS
+ Wakeup from Stop mode interrupt flag
+ selection
+ 20
+ 2
+
+
+ SCARCNT
+ Smartcard auto-retry count
+ 17
+ 3
+
+
+ DEP
+ Driver enable polarity
+ selection
+ 15
+ 1
+
+
+ DEM
+ Driver enable mode
+ 14
+ 1
+
+
+ DDRE
+ DMA Disable on Reception
+ Error
+ 13
+ 1
+
+
+ OVRDIS
+ Overrun Disable
+ 12
+ 1
+
+
+ ONEBIT
+ One sample bit method
+ enable
+ 11
+ 1
+
+
+ CTSIE
+ CTS interrupt enable
+ 10
+ 1
+
+
+ CTSE
+ CTS enable
+ 9
+ 1
+
+
+ RTSE
+ RTS enable
+ 8
+ 1
+
+
+ DMAT
+ DMA enable transmitter
+ 7
+ 1
+
+
+ DMAR
+ DMA enable receiver
+ 6
+ 1
+
+
+ SCEN
+ Smartcard mode enable
+ 5
+ 1
+
+
+ NACK
+ Smartcard NACK enable
+ 4
+ 1
+
+
+ HDSEL
+ Half-duplex selection
+ 3
+ 1
+
+
+ IRLP
+ Ir low-power
+ 2
+ 1
+
+
+ IREN
+ Ir mode enable
+ 1
+ 1
+
+
+ EIE
+ Error interrupt enable
+ 0
+ 1
+
+
+
+
+ BRR
+ BRR
+ Baud rate register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ DIV_Mantissa
+ DIV_Mantissa
+ 4
+ 12
+
+
+ DIV_Fraction
+ DIV_Fraction
+ 0
+ 4
+
+
+
+
+ GTPR
+ GTPR
+ Guard time and prescaler
+ register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ GT
+ Guard time value
+ 8
+ 8
+
+
+ PSC
+ Prescaler value
+ 0
+ 8
+
+
+
+
+ RTOR
+ RTOR
+ Receiver timeout register
+ 0x14
+ 0x20
+ read-write
+ 0x0000
+
+
+ BLEN
+ Block Length
+ 24
+ 8
+
+
+ RTO
+ Receiver timeout value
+ 0
+ 24
+
+
+
+
+ RQR
+ RQR
+ Request register
+ 0x18
+ 0x20
+ write-only
+ 0x0000
+
+
+ TXFRQ
+ Transmit data flush
+ request
+ 4
+ 1
+
+
+ RXFRQ
+ Receive data flush request
+ 3
+ 1
+
+
+ MMRQ
+ Mute mode request
+ 2
+ 1
+
+
+ SBKRQ
+ Send break request
+ 1
+ 1
+
+
+ ABRRQ
+ Auto baud rate request
+ 0
+ 1
+
+
+
+
+ ISR
+ ISR
+ Interrupt & status
+ register
+ 0x1C
+ 0x20
+ read-only
+ 0x00C0
+
+
+ REACK
+ REACK
+ 22
+ 1
+
+
+ TEACK
+ TEACK
+ 21
+ 1
+
+
+ WUF
+ WUF
+ 20
+ 1
+
+
+ RWU
+ RWU
+ 19
+ 1
+
+
+ SBKF
+ SBKF
+ 18
+ 1
+
+
+ CMF
+ CMF
+ 17
+ 1
+
+
+ BUSY
+ BUSY
+ 16
+ 1
+
+
+ ABRF
+ ABRF
+ 15
+ 1
+
+
+ ABRE
+ ABRE
+ 14
+ 1
+
+
+ EOBF
+ EOBF
+ 12
+ 1
+
+
+ RTOF
+ RTOF
+ 11
+ 1
+
+
+ CTS
+ CTS
+ 10
+ 1
+
+
+ CTSIF
+ CTSIF
+ 9
+ 1
+
+
+ LBDF
+ LBDF
+ 8
+ 1
+
+
+ TXE
+ TXE
+ 7
+ 1
+
+
+ TC
+ TC
+ 6
+ 1
+
+
+ RXNE
+ RXNE
+ 5
+ 1
+
+
+ IDLE
+ IDLE
+ 4
+ 1
+
+
+ ORE
+ ORE
+ 3
+ 1
+
+
+ NF
+ NF
+ 2
+ 1
+
+
+ FE
+ FE
+ 1
+ 1
+
+
+ PE
+ PE
+ 0
+ 1
+
+
+
+
+ ICR
+ ICR
+ Interrupt flag clear register
+ 0x20
+ 0x20
+ write-only
+ 0x0000
+
+
+ WUCF
+ Wakeup from Stop mode clear
+ flag
+ 20
+ 1
+
+
+ CMCF
+ Character match clear flag
+ 17
+ 1
+
+
+ EOBCF
+ End of block clear flag
+ 12
+ 1
+
+
+ RTOCF
+ Receiver timeout clear
+ flag
+ 11
+ 1
+
+
+ CTSCF
+ CTS clear flag
+ 9
+ 1
+
+
+ LBDCF
+ LIN break detection clear
+ flag
+ 8
+ 1
+
+
+ TCCF
+ Transmission complete clear
+ flag
+ 6
+ 1
+
+
+ IDLECF
+ Idle line detected clear
+ flag
+ 4
+ 1
+
+
+ ORECF
+ Overrun error clear flag
+ 3
+ 1
+
+
+ NCF
+ Noise detected clear flag
+ 2
+ 1
+
+
+ FECF
+ Framing error clear flag
+ 1
+ 1
+
+
+ PECF
+ Parity error clear flag
+ 0
+ 1
+
+
+
+
+ RDR
+ RDR
+ Receive data register
+ 0x24
+ 0x20
+ read-only
+ 0x0000
+
+
+ RDR
+ Receive data value
+ 0
+ 9
+
+
+
+
+ TDR
+ TDR
+ Transmit data register
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ TDR
+ Transmit data value
+ 0
+ 9
+
+
+
+
+
+
+ USART2
+ 0x40004400
+
+
+ USART4
+ 0x40004C00
+
+ USART4_USART5
+ USART4/USART5 global interrupt
+ 14
+
+
+ USART1
+ USART1 global interrupt
+ 27
+
+
+
+ USART5
+ 0x40005000
+
+ USART2
+ USART2 global interrupt
+ 28
+
+
+
+ TSC
+ Touch sensing controller
+ TSC
+ 0x40024000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TSC
+ Touch sensing interrupt
+ 8
+
+
+
+ CR
+ CR
+ control register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CTPH
+ Charge transfer pulse high
+ 28
+ 4
+
+
+ CTPL
+ Charge transfer pulse low
+ 24
+ 4
+
+
+ SSD
+ Spread spectrum deviation
+ 17
+ 7
+
+
+ SSE
+ Spread spectrum enable
+ 16
+ 1
+
+
+ SSPSC
+ Spread spectrum prescaler
+ 15
+ 1
+
+
+ PGPSC
+ pulse generator prescaler
+ 12
+ 3
+
+
+ MCV
+ Max count value
+ 5
+ 3
+
+
+ IODEF
+ I/O Default mode
+ 4
+ 1
+
+
+ SYNCPOL
+ Synchronization pin
+ polarity
+ 3
+ 1
+
+
+ AM
+ Acquisition mode
+ 2
+ 1
+
+
+ START
+ Start a new acquisition
+ 1
+ 1
+
+
+ TSCE
+ Touch sensing controller
+ enable
+ 0
+ 1
+
+
+
+
+ IER
+ IER
+ interrupt enable register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MCEIE
+ Max count error interrupt
+ enable
+ 1
+ 1
+
+
+ EOAIE
+ End of acquisition interrupt
+ enable
+ 0
+ 1
+
+
+
+
+ ICR
+ ICR
+ interrupt clear register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MCEIC
+ Max count error interrupt
+ clear
+ 1
+ 1
+
+
+ EOAIC
+ End of acquisition interrupt
+ clear
+ 0
+ 1
+
+
+
+
+ ISR
+ ISR
+ interrupt status register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MCEF
+ Max count error flag
+ 1
+ 1
+
+
+ EOAF
+ End of acquisition flag
+ 0
+ 1
+
+
+
+
+ IOHCR
+ IOHCR
+ I/O hysteresis control
+ register
+ 0x10
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ G8_IO4
+ G8_IO4
+ 31
+ 1
+
+
+ G8_IO3
+ G8_IO3
+ 30
+ 1
+
+
+ G8_IO2
+ G8_IO2
+ 29
+ 1
+
+
+ G8_IO1
+ G8_IO1
+ 28
+ 1
+
+
+ G7_IO4
+ G7_IO4
+ 27
+ 1
+
+
+ G7_IO3
+ G7_IO3
+ 26
+ 1
+
+
+ G7_IO2
+ G7_IO2
+ 25
+ 1
+
+
+ G7_IO1
+ G7_IO1
+ 24
+ 1
+
+
+ G6_IO4
+ G6_IO4
+ 23
+ 1
+
+
+ G6_IO3
+ G6_IO3
+ 22
+ 1
+
+
+ G6_IO2
+ G6_IO2
+ 21
+ 1
+
+
+ G6_IO1
+ G6_IO1
+ 20
+ 1
+
+
+ G5_IO4
+ G5_IO4
+ 19
+ 1
+
+
+ G5_IO3
+ G5_IO3
+ 18
+ 1
+
+
+ G5_IO2
+ G5_IO2
+ 17
+ 1
+
+
+ G5_IO1
+ G5_IO1
+ 16
+ 1
+
+
+ G4_IO4
+ G4_IO4
+ 15
+ 1
+
+
+ G4_IO3
+ G4_IO3
+ 14
+ 1
+
+
+ G4_IO2
+ G4_IO2
+ 13
+ 1
+
+
+ G4_IO1
+ G4_IO1
+ 12
+ 1
+
+
+ G3_IO4
+ G3_IO4
+ 11
+ 1
+
+
+ G3_IO3
+ G3_IO3
+ 10
+ 1
+
+
+ G3_IO2
+ G3_IO2
+ 9
+ 1
+
+
+ G3_IO1
+ G3_IO1
+ 8
+ 1
+
+
+ G2_IO4
+ G2_IO4
+ 7
+ 1
+
+
+ G2_IO3
+ G2_IO3
+ 6
+ 1
+
+
+ G2_IO2
+ G2_IO2
+ 5
+ 1
+
+
+ G2_IO1
+ G2_IO1
+ 4
+ 1
+
+
+ G1_IO4
+ G1_IO4
+ 3
+ 1
+
+
+ G1_IO3
+ G1_IO3
+ 2
+ 1
+
+
+ G1_IO2
+ G1_IO2
+ 1
+ 1
+
+
+ G1_IO1
+ G1_IO1
+ 0
+ 1
+
+
+
+
+ IOASCR
+ IOASCR
+ I/O analog switch control
+ register
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ G8_IO4
+ G8_IO4
+ 31
+ 1
+
+
+ G8_IO3
+ G8_IO3
+ 30
+ 1
+
+
+ G8_IO2
+ G8_IO2
+ 29
+ 1
+
+
+ G8_IO1
+ G8_IO1
+ 28
+ 1
+
+
+ G7_IO4
+ G7_IO4
+ 27
+ 1
+
+
+ G7_IO3
+ G7_IO3
+ 26
+ 1
+
+
+ G7_IO2
+ G7_IO2
+ 25
+ 1
+
+
+ G7_IO1
+ G7_IO1
+ 24
+ 1
+
+
+ G6_IO4
+ G6_IO4
+ 23
+ 1
+
+
+ G6_IO3
+ G6_IO3
+ 22
+ 1
+
+
+ G6_IO2
+ G6_IO2
+ 21
+ 1
+
+
+ G6_IO1
+ G6_IO1
+ 20
+ 1
+
+
+ G5_IO4
+ G5_IO4
+ 19
+ 1
+
+
+ G5_IO3
+ G5_IO3
+ 18
+ 1
+
+
+ G5_IO2
+ G5_IO2
+ 17
+ 1
+
+
+ G5_IO1
+ G5_IO1
+ 16
+ 1
+
+
+ G4_IO4
+ G4_IO4
+ 15
+ 1
+
+
+ G4_IO3
+ G4_IO3
+ 14
+ 1
+
+
+ G4_IO2
+ G4_IO2
+ 13
+ 1
+
+
+ G4_IO1
+ G4_IO1
+ 12
+ 1
+
+
+ G3_IO4
+ G3_IO4
+ 11
+ 1
+
+
+ G3_IO3
+ G3_IO3
+ 10
+ 1
+
+
+ G3_IO2
+ G3_IO2
+ 9
+ 1
+
+
+ G3_IO1
+ G3_IO1
+ 8
+ 1
+
+
+ G2_IO4
+ G2_IO4
+ 7
+ 1
+
+
+ G2_IO3
+ G2_IO3
+ 6
+ 1
+
+
+ G2_IO2
+ G2_IO2
+ 5
+ 1
+
+
+ G2_IO1
+ G2_IO1
+ 4
+ 1
+
+
+ G1_IO4
+ G1_IO4
+ 3
+ 1
+
+
+ G1_IO3
+ G1_IO3
+ 2
+ 1
+
+
+ G1_IO2
+ G1_IO2
+ 1
+ 1
+
+
+ G1_IO1
+ G1_IO1
+ 0
+ 1
+
+
+
+
+ IOSCR
+ IOSCR
+ I/O sampling control register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ G8_IO4
+ G8_IO4
+ 31
+ 1
+
+
+ G8_IO3
+ G8_IO3
+ 30
+ 1
+
+
+ G8_IO2
+ G8_IO2
+ 29
+ 1
+
+
+ G8_IO1
+ G8_IO1
+ 28
+ 1
+
+
+ G7_IO4
+ G7_IO4
+ 27
+ 1
+
+
+ G7_IO3
+ G7_IO3
+ 26
+ 1
+
+
+ G7_IO2
+ G7_IO2
+ 25
+ 1
+
+
+ G7_IO1
+ G7_IO1
+ 24
+ 1
+
+
+ G6_IO4
+ G6_IO4
+ 23
+ 1
+
+
+ G6_IO3
+ G6_IO3
+ 22
+ 1
+
+
+ G6_IO2
+ G6_IO2
+ 21
+ 1
+
+
+ G6_IO1
+ G6_IO1
+ 20
+ 1
+
+
+ G5_IO4
+ G5_IO4
+ 19
+ 1
+
+
+ G5_IO3
+ G5_IO3
+ 18
+ 1
+
+
+ G5_IO2
+ G5_IO2
+ 17
+ 1
+
+
+ G5_IO1
+ G5_IO1
+ 16
+ 1
+
+
+ G4_IO4
+ G4_IO4
+ 15
+ 1
+
+
+ G4_IO3
+ G4_IO3
+ 14
+ 1
+
+
+ G4_IO2
+ G4_IO2
+ 13
+ 1
+
+
+ G4_IO1
+ G4_IO1
+ 12
+ 1
+
+
+ G3_IO4
+ G3_IO4
+ 11
+ 1
+
+
+ G3_IO3
+ G3_IO3
+ 10
+ 1
+
+
+ G3_IO2
+ G3_IO2
+ 9
+ 1
+
+
+ G3_IO1
+ G3_IO1
+ 8
+ 1
+
+
+ G2_IO4
+ G2_IO4
+ 7
+ 1
+
+
+ G2_IO3
+ G2_IO3
+ 6
+ 1
+
+
+ G2_IO2
+ G2_IO2
+ 5
+ 1
+
+
+ G2_IO1
+ G2_IO1
+ 4
+ 1
+
+
+ G1_IO4
+ G1_IO4
+ 3
+ 1
+
+
+ G1_IO3
+ G1_IO3
+ 2
+ 1
+
+
+ G1_IO2
+ G1_IO2
+ 1
+ 1
+
+
+ G1_IO1
+ G1_IO1
+ 0
+ 1
+
+
+
+
+ IOCCR
+ IOCCR
+ I/O channel control register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ G8_IO4
+ G8_IO4
+ 31
+ 1
+
+
+ G8_IO3
+ G8_IO3
+ 30
+ 1
+
+
+ G8_IO2
+ G8_IO2
+ 29
+ 1
+
+
+ G8_IO1
+ G8_IO1
+ 28
+ 1
+
+
+ G7_IO4
+ G7_IO4
+ 27
+ 1
+
+
+ G7_IO3
+ G7_IO3
+ 26
+ 1
+
+
+ G7_IO2
+ G7_IO2
+ 25
+ 1
+
+
+ G7_IO1
+ G7_IO1
+ 24
+ 1
+
+
+ G6_IO4
+ G6_IO4
+ 23
+ 1
+
+
+ G6_IO3
+ G6_IO3
+ 22
+ 1
+
+
+ G6_IO2
+ G6_IO2
+ 21
+ 1
+
+
+ G6_IO1
+ G6_IO1
+ 20
+ 1
+
+
+ G5_IO4
+ G5_IO4
+ 19
+ 1
+
+
+ G5_IO3
+ G5_IO3
+ 18
+ 1
+
+
+ G5_IO2
+ G5_IO2
+ 17
+ 1
+
+
+ G5_IO1
+ G5_IO1
+ 16
+ 1
+
+
+ G4_IO4
+ G4_IO4
+ 15
+ 1
+
+
+ G4_IO3
+ G4_IO3
+ 14
+ 1
+
+
+ G4_IO2
+ G4_IO2
+ 13
+ 1
+
+
+ G4_IO1
+ G4_IO1
+ 12
+ 1
+
+
+ G3_IO4
+ G3_IO4
+ 11
+ 1
+
+
+ G3_IO3
+ G3_IO3
+ 10
+ 1
+
+
+ G3_IO2
+ G3_IO2
+ 9
+ 1
+
+
+ G3_IO1
+ G3_IO1
+ 8
+ 1
+
+
+ G2_IO4
+ G2_IO4
+ 7
+ 1
+
+
+ G2_IO3
+ G2_IO3
+ 6
+ 1
+
+
+ G2_IO2
+ G2_IO2
+ 5
+ 1
+
+
+ G2_IO1
+ G2_IO1
+ 4
+ 1
+
+
+ G1_IO4
+ G1_IO4
+ 3
+ 1
+
+
+ G1_IO3
+ G1_IO3
+ 2
+ 1
+
+
+ G1_IO2
+ G1_IO2
+ 1
+ 1
+
+
+ G1_IO1
+ G1_IO1
+ 0
+ 1
+
+
+
+
+ IOGCSR
+ IOGCSR
+ I/O group control status
+ register
+ 0x30
+ 0x20
+ 0x00000000
+
+
+ G8S
+ Analog I/O group x status
+ 23
+ 1
+ read-only
+
+
+ G7S
+ Analog I/O group x status
+ 22
+ 1
+ read-only
+
+
+ G6S
+ Analog I/O group x status
+ 21
+ 1
+ read-only
+
+
+ G5S
+ Analog I/O group x status
+ 20
+ 1
+ read-only
+
+
+ G4S
+ Analog I/O group x status
+ 19
+ 1
+ read-only
+
+
+ G3S
+ Analog I/O group x status
+ 18
+ 1
+ read-only
+
+
+ G2S
+ Analog I/O group x status
+ 17
+ 1
+ read-only
+
+
+ G1S
+ Analog I/O group x status
+ 16
+ 1
+ read-only
+
+
+ G8E
+ Analog I/O group x enable
+ 7
+ 1
+ read-write
+
+
+ G7E
+ Analog I/O group x enable
+ 6
+ 1
+ read-write
+
+
+ G6E
+ Analog I/O group x enable
+ 5
+ 1
+ read-write
+
+
+ G5E
+ Analog I/O group x enable
+ 4
+ 1
+ read-write
+
+
+ G4E
+ Analog I/O group x enable
+ 3
+ 1
+ read-write
+
+
+ G3E
+ Analog I/O group x enable
+ 2
+ 1
+ read-write
+
+
+ G2E
+ Analog I/O group x enable
+ 1
+ 1
+ read-write
+
+
+ G1E
+ Analog I/O group x enable
+ 0
+ 1
+ read-write
+
+
+
+
+ IOG1CR
+ IOG1CR
+ I/O group x counter register
+ 0x34
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CNT
+ Counter value
+ 0
+ 14
+
+
+
+
+ IOG2CR
+ IOG2CR
+ I/O group x counter register
+ 0x38
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CNT
+ Counter value
+ 0
+ 14
+
+
+
+
+ IOG3CR
+ IOG3CR
+ I/O group x counter register
+ 0x3C
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CNT
+ Counter value
+ 0
+ 14
+
+
+
+
+ IOG4CR
+ IOG4CR
+ I/O group x counter register
+ 0x40
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CNT
+ Counter value
+ 0
+ 14
+
+
+
+
+ IOG5CR
+ IOG5CR
+ I/O group x counter register
+ 0x44
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CNT
+ Counter value
+ 0
+ 14
+
+
+
+
+ IOG6CR
+ IOG6CR
+ I/O group x counter register
+ 0x48
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CNT
+ Counter value
+ 0
+ 14
+
+
+
+
+ IOG7CR
+ IOG7CR
+ I/O group x counter register
+ 0x4C
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CNT
+ Counter value
+ 0
+ 14
+
+
+
+
+ IOG8CR
+ IOG8CR
+ I/O group x counter register
+ 0x50
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CNT
+ Counter value
+ 0
+ 14
+
+
+
+
+
+
+ IWDG
+ Independent watchdog
+ IWDG
+ 0x40003000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ KR
+ KR
+ Key register
+ 0x0
+ 0x20
+ write-only
+ 0x00000000
+
+
+ KEY
+ Key value (write only, read
+ 0x0000)
+ 0
+ 16
+
+
+
+
+ PR
+ PR
+ Prescaler register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PR
+ Prescaler divider
+ 0
+ 3
+
+
+
+
+ RLR
+ RLR
+ Reload register
+ 0x8
+ 0x20
+ read-write
+ 0x00000FFF
+
+
+ RL
+ Watchdog counter reload
+ value
+ 0
+ 12
+
+
+
+
+ SR
+ SR
+ Status register
+ 0xC
+ 0x20
+ read-only
+ 0x00000000
+
+
+ WVU
+ Watchdog counter window value
+ update
+ 2
+ 1
+
+
+ RVU
+ Watchdog counter reload value
+ update
+ 1
+ 1
+
+
+ PVU
+ Watchdog prescaler value
+ update
+ 0
+ 1
+
+
+
+
+ WINR
+ WINR
+ Window register
+ 0x10
+ 0x20
+ read-write
+ 0x00000FFF
+
+
+ WIN
+ Watchdog counter window
+ value
+ 0
+ 12
+
+
+
+
+
+
+ WWDG
+ System window watchdog
+ WWDG
+ 0x40002C00
+
+ 0x0
+ 0x400
+ registers
+
+
+ WWDG
+ Window Watchdog interrupt
+ 0
+
+
+
+ CR
+ CR
+ Control register
+ 0x0
+ 0x20
+ read-write
+ 0x0000007F
+
+
+ WDGA
+ Activation bit
+ 7
+ 1
+
+
+ T
+ 7-bit counter (MSB to LSB)
+ 0
+ 7
+
+
+
+
+ CFR
+ CFR
+ Configuration register
+ 0x4
+ 0x20
+ read-write
+ 0x0000007F
+
+
+ EWI
+ Early wakeup interrupt
+ 9
+ 1
+
+
+ WDGTB1
+ Timer base
+ 8
+ 1
+
+
+ WDGTB0
+ WDGTB0
+ 7
+ 1
+
+
+ W
+ 7-bit window value
+ 0
+ 7
+
+
+
+
+ SR
+ SR
+ Status register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EWIF
+ Early wakeup interrupt
+ flag
+ 0
+ 1
+
+
+
+
+
+
+ USB_FS
+ Universal serial bus full-speed device
+ interface
+ USB
+ 0x40005C00
+
+ 0x0
+ 0x400
+ registers
+
+
+ USB
+ USB event interrupt through
+ EXTI18
+ 31
+
+
+
+ EP0R
+ EP0R
+ endpoint register
+ 0x0
+ 0x20
+ read-write
+ 0x0
+
+
+ CTR_RX
+ CTR_RX
+ 15
+ 1
+
+
+ DTOG_RX
+ DTOG_RX
+ 14
+ 1
+
+
+ STAT_RX
+ STAT_RX
+ 12
+ 2
+
+
+ SETUP
+ SETUP
+ 11
+ 1
+
+
+ EPTYPE
+ EPTYPE
+ 9
+ 2
+
+
+ EP_KIND
+ EP_KIND
+ 8
+ 1
+
+
+ CTR_TX
+ CTR_TX
+ 7
+ 1
+
+
+ DTOG_TX
+ DTOG_TX
+ 6
+ 1
+
+
+ STAT_TX
+ STAT_TX
+ 4
+ 2
+
+
+ EA
+ EA
+ 0
+ 4
+
+
+
+
+ EP1R
+ EP1R
+ endpoint register
+ 0x4
+ 0x20
+ read-write
+ 0x0
+
+
+ CTR_RX
+ CTR_RX
+ 15
+ 1
+
+
+ DTOG_RX
+ DTOG_RX
+ 14
+ 1
+
+
+ STAT_RX
+ STAT_RX
+ 12
+ 2
+
+
+ SETUP
+ SETUP
+ 11
+ 1
+
+
+ EPTYPE
+ EPTYPE
+ 9
+ 2
+
+
+ EP_KIND
+ EP_KIND
+ 8
+ 1
+
+
+ CTR_TX
+ CTR_TX
+ 7
+ 1
+
+
+ DTOG_TX
+ DTOG_TX
+ 6
+ 1
+
+
+ STAT_TX
+ STAT_TX
+ 4
+ 2
+
+
+ EA
+ EA
+ 0
+ 4
+
+
+
+
+ EP2R
+ EP2R
+ endpoint register
+ 0x8
+ 0x20
+ read-write
+ 0x0
+
+
+ CTR_RX
+ CTR_RX
+ 15
+ 1
+
+
+ DTOG_RX
+ DTOG_RX
+ 14
+ 1
+
+
+ STAT_RX
+ STAT_RX
+ 12
+ 2
+
+
+ SETUP
+ SETUP
+ 11
+ 1
+
+
+ EPTYPE
+ EPTYPE
+ 9
+ 2
+
+
+ EP_KIND
+ EP_KIND
+ 8
+ 1
+
+
+ CTR_TX
+ CTR_TX
+ 7
+ 1
+
+
+ DTOG_TX
+ DTOG_TX
+ 6
+ 1
+
+
+ STAT_TX
+ STAT_TX
+ 4
+ 2
+
+
+ EA
+ EA
+ 0
+ 4
+
+
+
+
+ EP3R
+ EP3R
+ endpoint register
+ 0xC
+ 0x20
+ read-write
+ 0x0
+
+
+ CTR_RX
+ CTR_RX
+ 15
+ 1
+
+
+ DTOG_RX
+ DTOG_RX
+ 14
+ 1
+
+
+ STAT_RX
+ STAT_RX
+ 12
+ 2
+
+
+ SETUP
+ SETUP
+ 11
+ 1
+
+
+ EPTYPE
+ EPTYPE
+ 9
+ 2
+
+
+ EP_KIND
+ EP_KIND
+ 8
+ 1
+
+
+ CTR_TX
+ CTR_TX
+ 7
+ 1
+
+
+ DTOG_TX
+ DTOG_TX
+ 6
+ 1
+
+
+ STAT_TX
+ STAT_TX
+ 4
+ 2
+
+
+ EA
+ EA
+ 0
+ 4
+
+
+
+
+ EP4R
+ EP4R
+ endpoint register
+ 0x10
+ 0x20
+ read-write
+ 0x0
+
+
+ CTR_RX
+ CTR_RX
+ 15
+ 1
+
+
+ DTOG_RX
+ DTOG_RX
+ 14
+ 1
+
+
+ STAT_RX
+ STAT_RX
+ 12
+ 2
+
+
+ SETUP
+ SETUP
+ 11
+ 1
+
+
+ EPTYPE
+ EPTYPE
+ 9
+ 2
+
+
+ EP_KIND
+ EP_KIND
+ 8
+ 1
+
+
+ CTR_TX
+ CTR_TX
+ 7
+ 1
+
+
+ DTOG_TX
+ DTOG_TX
+ 6
+ 1
+
+
+ STAT_TX
+ STAT_TX
+ 4
+ 2
+
+
+ EA
+ EA
+ 0
+ 4
+
+
+
+
+ EP5R
+ EP5R
+ endpoint register
+ 0x14
+ 0x20
+ read-write
+ 0x0
+
+
+ CTR_RX
+ CTR_RX
+ 15
+ 1
+
+
+ DTOG_RX
+ DTOG_RX
+ 14
+ 1
+
+
+ STAT_RX
+ STAT_RX
+ 12
+ 2
+
+
+ SETUP
+ SETUP
+ 11
+ 1
+
+
+ EPTYPE
+ EPTYPE
+ 9
+ 2
+
+
+ EP_KIND
+ EP_KIND
+ 8
+ 1
+
+
+ CTR_TX
+ CTR_TX
+ 7
+ 1
+
+
+ DTOG_TX
+ DTOG_TX
+ 6
+ 1
+
+
+ STAT_TX
+ STAT_TX
+ 4
+ 2
+
+
+ EA
+ EA
+ 0
+ 4
+
+
+
+
+ EP6R
+ EP6R
+ endpoint register
+ 0x18
+ 0x20
+ read-write
+ 0x0
+
+
+ CTR_RX
+ CTR_RX
+ 15
+ 1
+
+
+ DTOG_RX
+ DTOG_RX
+ 14
+ 1
+
+
+ STAT_RX
+ STAT_RX
+ 12
+ 2
+
+
+ SETUP
+ SETUP
+ 11
+ 1
+
+
+ EPTYPE
+ EPTYPE
+ 9
+ 2
+
+
+ EP_KIND
+ EP_KIND
+ 8
+ 1
+
+
+ CTR_TX
+ CTR_TX
+ 7
+ 1
+
+
+ DTOG_TX
+ DTOG_TX
+ 6
+ 1
+
+
+ STAT_TX
+ STAT_TX
+ 4
+ 2
+
+
+ EA
+ EA
+ 0
+ 4
+
+
+
+
+ EP7R
+ EP7R
+ endpoint register
+ 0x1C
+ 0x20
+ read-write
+ 0x0
+
+
+ CTR_RX
+ CTR_RX
+ 15
+ 1
+
+
+ DTOG_RX
+ DTOG_RX
+ 14
+ 1
+
+
+ STAT_RX
+ STAT_RX
+ 12
+ 2
+
+
+ SETUP
+ SETUP
+ 11
+ 1
+
+
+ EPTYPE
+ EPTYPE
+ 9
+ 2
+
+
+ EP_KIND
+ EP_KIND
+ 8
+ 1
+
+
+ CTR_TX
+ CTR_TX
+ 7
+ 1
+
+
+ DTOG_TX
+ DTOG_TX
+ 6
+ 1
+
+
+ STAT_TX
+ STAT_TX
+ 4
+ 2
+
+
+ EA
+ EA
+ 0
+ 4
+
+
+
+
+ CNTR
+ CNTR
+ control register
+ 0x40
+ 0x20
+ read-write
+ 0x0
+
+
+ CTRM
+ CTRM
+ 15
+ 1
+
+
+ PMAOVRM
+ PMAOVRM
+ 14
+ 1
+
+
+ ERRM
+ ERRM
+ 13
+ 1
+
+
+ WKUPM
+ WKUPM
+ 12
+ 1
+
+
+ SUSPM
+ SUSPM
+ 11
+ 1
+
+
+ RESETM
+ RESETM
+ 10
+ 1
+
+
+ SOFM
+ SOFM
+ 9
+ 1
+
+
+ ESOFM
+ ESOFM
+ 8
+ 1
+
+
+ L1REQM
+ L1REQM
+ 7
+ 1
+
+
+ L1RESUME
+ L1RESUME
+ 5
+ 1
+
+
+ RESUME
+ RESUME
+ 4
+ 1
+
+
+ FSUSP
+ FSUSP
+ 3
+ 1
+
+
+ LPMODE
+ LPMODE
+ 2
+ 1
+
+
+ PDWN
+ PDWN
+ 1
+ 1
+
+
+ FRES
+ FRES
+ 0
+ 1
+
+
+
+
+ ISTR
+ ISTR
+ interrupt status register
+ 0x44
+ 0x20
+ read-write
+ 0x0
+
+
+ CTR
+ CTR
+ 15
+ 1
+
+
+ PMAOVR
+ PMAOVR
+ 14
+ 1
+
+
+ ERR
+ ERR
+ 13
+ 1
+
+
+ WKUP
+ WKUP
+ 12
+ 1
+
+
+ SUSP
+ SUSP
+ 11
+ 1
+
+
+ RESET
+ RESET
+ 10
+ 1
+
+
+ SOF
+ SOF
+ 9
+ 1
+
+
+ ESOF
+ ESOF
+ 8
+ 1
+
+
+ L1REQ
+ L1REQ
+ 7
+ 1
+
+
+ DIR
+ DIR
+ 4
+ 1
+
+
+ EP_ID
+ EP_ID
+ 0
+ 4
+
+
+
+
+ FNR
+ FNR
+ frame number register
+ 0x48
+ 0x20
+ read-only
+ 0x0
+
+
+ RXDP
+ RXDP
+ 15
+ 1
+
+
+ RXDM
+ RXDM
+ 14
+ 1
+
+
+ LCK
+ LCK
+ 13
+ 1
+
+
+ LSOF
+ LSOF
+ 11
+ 2
+
+
+ FN
+ FN
+ 0
+ 11
+
+
+
+
+ DADDR
+ DADDR
+ device address
+ 0x4C
+ 0x20
+ read-write
+ 0x0
+
+
+ EF
+ EF
+ 7
+ 1
+
+
+ ADD
+ ADD
+ 0
+ 7
+
+
+
+
+ BTABLE
+ BTABLE
+ Buffer table address
+ 0x50
+ 0x20
+ read-write
+ 0x0
+
+
+ BTABLE
+ BTABLE
+ 3
+ 13
+
+
+
+
+ LPMCSR
+ LPMCSR
+ LPM control and status
+ register
+ 0x54
+ 0x20
+ 0x0
+
+
+ BESL
+ BESL
+ 4
+ 4
+ read-only
+
+
+ REMWAKE
+ REMWAKE
+ 3
+ 1
+ read-only
+
+
+ LPMACK
+ LPMACK
+ 1
+ 1
+ read-write
+
+
+ LPMEN
+ LPMEN
+ 0
+ 1
+ read-write
+
+
+
+
+ BCDR
+ BCDR
+ Battery charging detector
+ 0x58
+ 0x20
+ 0x0
+
+
+ DPPU
+ DPPU
+ 15
+ 1
+ read-write
+
+
+ PS2DET
+ PS2DET
+ 7
+ 1
+ read-only
+
+
+ SDET
+ SDET
+ 6
+ 1
+ read-only
+
+
+ PDET
+ PDET
+ 5
+ 1
+ read-only
+
+
+ DCDET
+ DCDET
+ 4
+ 1
+ read-only
+
+
+ SDEN
+ SDEN
+ 3
+ 1
+ read-write
+
+
+ PDEN
+ PDEN
+ 2
+ 1
+ read-write
+
+
+ DCDEN
+ DCDEN
+ 1
+ 1
+ read-write
+
+
+ BCDEN
+ BCDEN
+ 0
+ 1
+ read-write
+
+
+
+
+
+
+ CRS
+ Clock recovery system
+ CRS
+ 0x40006C00
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CR
+ CR
+ control register
+ 0x0
+ 0x20
+ read-write
+ 0x00002000
+
+
+ TRIM
+ HSI48 oscillator smooth
+ trimming
+ 8
+ 6
+
+
+ SWSYNC
+ Generate software SYNC
+ event
+ 7
+ 1
+
+
+ AUTOTRIMEN
+ Automatic trimming enable
+ 6
+ 1
+
+
+ CEN
+ Frequency error counter
+ enable
+ 5
+ 1
+
+
+ ESYNCIE
+ Expected SYNC interrupt
+ enable
+ 3
+ 1
+
+
+ ERRIE
+ Synchronization or trimming error
+ interrupt enable
+ 2
+ 1
+
+
+ SYNCWARNIE
+ SYNC warning interrupt
+ enable
+ 1
+ 1
+
+
+ SYNCOKIE
+ SYNC event OK interrupt
+ enable
+ 0
+ 1
+
+
+
+
+ CFGR
+ CFGR
+ configuration register
+ 0x4
+ 0x20
+ read-write
+ 0x2022BB7F
+
+
+ SYNCPOL
+ SYNC polarity selection
+ 31
+ 1
+
+
+ SYNCSRC
+ SYNC signal source
+ selection
+ 28
+ 2
+
+
+ SYNCDIV
+ SYNC divider
+ 24
+ 3
+
+
+ FELIM
+ Frequency error limit
+ 16
+ 8
+
+
+ RELOAD
+ Counter reload value
+ 0
+ 16
+
+
+
+
+ ISR
+ ISR
+ interrupt and status register
+ 0x8
+ 0x20
+ read-only
+ 0x00000000
+
+
+ FECAP
+ Frequency error capture
+ 16
+ 16
+
+
+ FEDIR
+ Frequency error direction
+ 15
+ 1
+
+
+ TRIMOVF
+ Trimming overflow or
+ underflow
+ 10
+ 1
+
+
+ SYNCMISS
+ SYNC missed
+ 9
+ 1
+
+
+ SYNCERR
+ SYNC error
+ 8
+ 1
+
+
+ ESYNCF
+ Expected SYNC flag
+ 3
+ 1
+
+
+ ERRF
+ Error flag
+ 2
+ 1
+
+
+ SYNCWARNF
+ SYNC warning flag
+ 1
+ 1
+
+
+ SYNCOKF
+ SYNC event OK flag
+ 0
+ 1
+
+
+
+
+ ICR
+ ICR
+ interrupt flag clear register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ESYNCC
+ Expected SYNC clear flag
+ 3
+ 1
+
+
+ ERRC
+ Error clear flag
+ 2
+ 1
+
+
+ SYNCWARNC
+ SYNC warning clear flag
+ 1
+ 1
+
+
+ SYNCOKC
+ SYNC event OK clear flag
+ 0
+ 1
+
+
+
+
+
+
+ Firewall
+ Firewall
+ Firewall
+ 0x40011C00
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ FIREWALL_CSSA
+ FIREWALL_CSSA
+ Code segment start address
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ADD
+ code segment start address
+ 8
+ 16
+
+
+
+
+ FIREWALL_CSL
+ FIREWALL_CSL
+ Code segment length
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LENG
+ code segment length
+ 8
+ 14
+
+
+
+
+ FIREWALL_NVDSSA
+ FIREWALL_NVDSSA
+ Non-volatile data segment start
+ address
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ADD
+ Non-volatile data segment start
+ address
+ 8
+ 16
+
+
+
+
+ FIREWALL_NVDSL
+ FIREWALL_NVDSL
+ Non-volatile data segment
+ length
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LENG
+ Non-volatile data segment
+ length
+ 8
+ 14
+
+
+
+
+ FIREWALL_VDSSA
+ FIREWALL_VDSSA
+ Volatile data segment start
+ address
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ADD
+ Volatile data segment start
+ address
+ 6
+ 10
+
+
+
+
+ FIREWALL_VDSL
+ FIREWALL_VDSL
+ Volatile data segment length
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LENG
+ Non-volatile data segment
+ length
+ 6
+ 10
+
+
+
+
+ FIREWALL_CR
+ FIREWALL_CR
+ Configuration register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ VDE
+ Volatile data execution
+ 2
+ 1
+
+
+ VDS
+ Volatile data shared
+ 1
+ 1
+
+
+ FPA
+ Firewall pre alarm
+ 0
+ 1
+
+
+
+
+
+
+ RCC
+ Reset and clock control
+ RCC
+ 0x40021000
+
+ 0x0
+ 0x400
+ registers
+
+
+ RCC
+ RCC global interrupt
+ 4
+
+
+
+ CR
+ CR
+ Clock control register
+ 0x0
+ 0x20
+ 0x00000300
+
+
+ PLLRDY
+ PLL clock ready flag
+ 25
+ 1
+ read-only
+
+
+ PLLON
+ PLL enable bit
+ 24
+ 1
+ read-write
+
+
+ RTCPRE
+ TC/LCD prescaler
+ 20
+ 2
+ read-write
+
+
+ CSSLSEON
+ Clock security system on HSE enable
+ bit
+ 19
+ 1
+ read-write
+
+
+ HSEBYP
+ HSE clock bypass bit
+ 18
+ 1
+ read-write
+
+
+ HSERDY
+ HSE clock ready flag
+ 17
+ 1
+ read-only
+
+
+ HSEON
+ HSE clock enable bit
+ 16
+ 1
+ read-write
+
+
+ MSIRDY
+ MSI clock ready flag
+ 9
+ 1
+ read-only
+
+
+ MSION
+ MSI clock enable bit
+ 8
+ 1
+ read-write
+
+
+ HSI16DIVF
+ HSI16DIVF
+ 4
+ 1
+ read-only
+
+
+ HSI16DIVEN
+ HSI16DIVEN
+ 3
+ 1
+ read-write
+
+
+ HSI16RDYF
+ Internal high-speed clock ready
+ flag
+ 2
+ 1
+ read-write
+
+
+ HSI16KERON
+ High-speed internal clock enable bit for
+ some IP kernels
+ 1
+ 1
+ read-only
+
+
+ HSI16ON
+ 16 MHz high-speed internal clock
+ enable
+ 0
+ 1
+ read-write
+
+
+ HSI16OUTEN
+ 16 MHz high-speed internal clock output
+ enable
+ 5
+ 1
+ read-write
+
+
+
+
+ ICSCR
+ ICSCR
+ Internal clock sources calibration
+ register
+ 0x4
+ 0x20
+ 0x0000B000
+
+
+ MSITRIM
+ MSI clock trimming
+ 24
+ 8
+ read-write
+
+
+ MSICAL
+ MSI clock calibration
+ 16
+ 8
+ read-only
+
+
+ MSIRANGE
+ MSI clock ranges
+ 13
+ 3
+ read-write
+
+
+ HSI16TRIM
+ High speed internal clock
+ trimming
+ 8
+ 5
+ read-write
+
+
+ HSI16CAL
+ nternal high speed clock
+ calibration
+ 0
+ 8
+ read-only
+
+
+
+
+ CRRCR
+ CRRCR
+ Clock recovery RC register
+ 0x8
+ 0x20
+ 0x00000000
+
+
+ HSI48CAL
+ 48 MHz HSI clock
+ calibration
+ 8
+ 8
+ read-only
+
+
+ HSI48RDY
+ 48MHz HSI clock ready flag
+ 1
+ 1
+ read-only
+
+
+ HSI48ON
+ 48MHz HSI clock enable bit
+ 0
+ 1
+ read-write
+
+
+ HSI48DIV6EN
+ 48 MHz HSI clock divided by 6 output
+ enable
+ 2
+ 1
+ read-write
+
+
+
+
+ CFGR
+ CFGR
+ Clock configuration register
+ 0xC
+ 0x20
+ 0x00000000
+
+
+ MCOPRE
+ Microcontroller clock output
+ prescaler
+ 28
+ 3
+ read-write
+
+
+ MCOSEL
+ Microcontroller clock output
+ selection
+ 24
+ 4
+ read-write
+
+
+ PLLDIV
+ PLL output division
+ 22
+ 2
+ read-write
+
+
+ PLLMUL
+ PLL multiplication factor
+ 18
+ 4
+ read-write
+
+
+ PLLSRC
+ PLL entry clock source
+ 16
+ 1
+ read-write
+
+
+ STOPWUCK
+ Wake-up from stop clock
+ selection
+ 15
+ 1
+ read-write
+
+
+ PPRE2
+ APB high-speed prescaler
+ (APB2)
+ 11
+ 3
+ read-write
+
+
+ PPRE1
+ APB low-speed prescaler
+ (APB1)
+ 8
+ 3
+ read-write
+
+
+ HPRE
+ AHB prescaler
+ 4
+ 4
+ read-write
+
+
+ SWS
+ System clock switch status
+ 2
+ 2
+ read-only
+
+
+ SW
+ System clock switch
+ 0
+ 2
+ read-write
+
+
+
+
+ CIER
+ CIER
+ Clock interrupt enable
+ register
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CSSLSE
+ LSE CSS interrupt flag
+ 7
+ 1
+
+
+ HSI48RDYIE
+ HSI48 ready interrupt flag
+ 6
+ 1
+
+
+ MSIRDYIE
+ MSI ready interrupt flag
+ 5
+ 1
+
+
+ PLLRDYIE
+ PLL ready interrupt flag
+ 4
+ 1
+
+
+ HSERDYIE
+ HSE ready interrupt flag
+ 3
+ 1
+
+
+ HSI16RDYIE
+ HSI16 ready interrupt flag
+ 2
+ 1
+
+
+ LSERDYIE
+ LSE ready interrupt flag
+ 1
+ 1
+
+
+ LSIRDYIE
+ LSI ready interrupt flag
+ 0
+ 1
+
+
+
+
+ CIFR
+ CIFR
+ Clock interrupt flag register
+ 0x14
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CSSHSEF
+ Clock Security System Interrupt
+ flag
+ 8
+ 1
+
+
+ CSSLSEF
+ LSE Clock Security System Interrupt
+ flag
+ 7
+ 1
+
+
+ HSI48RDYF
+ HSI48 ready interrupt flag
+ 6
+ 1
+
+
+ MSIRDYF
+ MSI ready interrupt flag
+ 5
+ 1
+
+
+ PLLRDYF
+ PLL ready interrupt flag
+ 4
+ 1
+
+
+ HSERDYF
+ HSE ready interrupt flag
+ 3
+ 1
+
+
+ HSI16RDYF
+ HSI16 ready interrupt flag
+ 2
+ 1
+
+
+ LSERDYF
+ LSE ready interrupt flag
+ 1
+ 1
+
+
+ LSIRDYF
+ LSI ready interrupt flag
+ 0
+ 1
+
+
+
+
+ CICR
+ CICR
+ Clock interrupt clear register
+ 0x18
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CSSHSEC
+ Clock Security System Interrupt
+ clear
+ 8
+ 1
+
+
+ CSSLSEC
+ LSE Clock Security System Interrupt
+ clear
+ 7
+ 1
+
+
+ HSI48RDYC
+ HSI48 ready Interrupt
+ clear
+ 6
+ 1
+
+
+ MSIRDYC
+ MSI ready Interrupt clear
+ 5
+ 1
+
+
+ PLLRDYC
+ PLL ready Interrupt clear
+ 4
+ 1
+
+
+ HSERDYC
+ HSE ready Interrupt clear
+ 3
+ 1
+
+
+ HSI16RDYC
+ HSI16 ready Interrupt
+ clear
+ 2
+ 1
+
+
+ LSERDYC
+ LSE ready Interrupt clear
+ 1
+ 1
+
+
+ LSIRDYC
+ LSI ready Interrupt clear
+ 0
+ 1
+
+
+
+
+ IOPRSTR
+ IOPRSTR
+ GPIO reset register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IOPHRST
+ I/O port H reset
+ 7
+ 1
+
+
+ IOPDRST
+ I/O port D reset
+ 3
+ 1
+
+
+ IOPCRST
+ I/O port A reset
+ 2
+ 1
+
+
+ IOPBRST
+ I/O port B reset
+ 1
+ 1
+
+
+ IOPARST
+ I/O port A reset
+ 0
+ 1
+
+
+ IOPERST
+ I/O port E reset
+ 4
+ 1
+
+
+
+
+ AHBRSTR
+ AHBRSTR
+ AHB peripheral reset register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CRYPRST
+ Crypto module reset
+ 24
+ 1
+
+
+ RNGRST
+ Random Number Generator module
+ reset
+ 20
+ 1
+
+
+ TOUCHRST
+ Touch Sensing reset
+ 16
+ 1
+
+
+ CRCRST
+ Test integration module
+ reset
+ 12
+ 1
+
+
+ MIFRST
+ Memory interface reset
+ 8
+ 1
+
+
+ DMARST
+ DMA reset
+ 0
+ 1
+
+
+
+
+ APB2RSTR
+ APB2RSTR
+ APB2 peripheral reset register
+ 0x24
+ 0x20
+ read-write
+ 0x000000000
+
+
+ DBGRST
+ DBG reset
+ 22
+ 1
+
+
+ USART1RST
+ USART1 reset
+ 14
+ 1
+
+
+ SPI1RST
+ SPI 1 reset
+ 12
+ 1
+
+
+ ADCRST
+ ADC interface reset
+ 9
+ 1
+
+
+ TM12RST
+ TIM22 timer reset
+ 5
+ 1
+
+
+ TIM21RST
+ TIM21 timer reset
+ 2
+ 1
+
+
+ SYSCFGRST
+ System configuration controller
+ reset
+ 0
+ 1
+
+
+
+
+ APB1RSTR
+ APB1RSTR
+ APB1 peripheral reset register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LPTIM1RST
+ Low power timer reset
+ 31
+ 1
+
+
+ DACRST
+ DAC interface reset
+ 29
+ 1
+
+
+ PWRRST
+ Power interface reset
+ 28
+ 1
+
+
+ CRSRST
+ Clock recovery system
+ reset
+ 27
+ 1
+
+
+ USBRST
+ USB reset
+ 23
+ 1
+
+
+ I2C2RST
+ I2C2 reset
+ 22
+ 1
+
+
+ I2C1RST
+ I2C1 reset
+ 21
+ 1
+
+
+ LPUART1RST
+ LPUART1 reset
+ 18
+ 1
+
+
+ LPUART12RST
+ UART2 reset
+ 17
+ 1
+
+
+ SPI2RST
+ SPI2 reset
+ 14
+ 1
+
+
+ WWDRST
+ Window watchdog reset
+ 11
+ 1
+
+
+ TIM6RST
+ Timer 6 reset
+ 4
+ 1
+
+
+ TIM2RST
+ Timer2 reset
+ 0
+ 1
+
+
+ TIM3RST
+ Timer3 reset
+ 1
+ 1
+
+
+ TIM7RST
+ Timer 7 reset
+ 5
+ 1
+
+
+ USART4RST
+ USART4 reset
+ 19
+ 1
+
+
+ USART5RST
+ USART5 reset
+ 20
+ 1
+
+
+ I2C3RST
+ I2C3 reset
+ 30
+ 1
+
+
+
+
+ IOPENR
+ IOPENR
+ GPIO clock enable register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IOPHEN
+ I/O port H clock enable
+ bit
+ 7
+ 1
+
+
+ IOPDEN
+ I/O port D clock enable
+ bit
+ 3
+ 1
+
+
+ IOPCEN
+ IO port A clock enable bit
+ 2
+ 1
+
+
+ IOPBEN
+ IO port B clock enable bit
+ 1
+ 1
+
+
+ IOPAEN
+ IO port A clock enable bit
+ 0
+ 1
+
+
+ IOPEEN
+ I/O port E clock enable
+ bit
+ 4
+ 1
+
+
+
+
+ AHBENR
+ AHBENR
+ AHB peripheral clock enable
+ register
+ 0x30
+ 0x20
+ read-write
+ 0x00000100
+
+
+ CRYPEN
+ Crypto clock enable bit
+ 24
+ 1
+
+
+ RNGEN
+ Random Number Generator clock enable
+ bit
+ 20
+ 1
+
+
+ TOUCHEN
+ Touch Sensing clock enable
+ bit
+ 16
+ 1
+
+
+ CRCEN
+ CRC clock enable bit
+ 12
+ 1
+
+
+ MIFEN
+ NVM interface clock enable
+ bit
+ 8
+ 1
+
+
+ DMAEN
+ DMA clock enable bit
+ 0
+ 1
+
+
+
+
+ APB2ENR
+ APB2ENR
+ APB2 peripheral clock enable
+ register
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DBGEN
+ DBG clock enable bit
+ 22
+ 1
+
+
+ USART1EN
+ USART1 clock enable bit
+ 14
+ 1
+
+
+ SPI1EN
+ SPI1 clock enable bit
+ 12
+ 1
+
+
+ ADCEN
+ ADC clock enable bit
+ 9
+ 1
+
+
+ MIFIEN
+ MiFaRe Firewall clock enable
+ bit
+ 7
+ 1
+
+
+ TIM22EN
+ TIM22 timer clock enable
+ bit
+ 5
+ 1
+
+
+ TIM21EN
+ TIM21 timer clock enable
+ bit
+ 2
+ 1
+
+
+ SYSCFGEN
+ System configuration controller clock
+ enable bit
+ 0
+ 1
+
+
+
+
+ APB1ENR
+ APB1ENR
+ APB1 peripheral clock enable
+ register
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LPTIM1EN
+ Low power timer clock enable
+ bit
+ 31
+ 1
+
+
+ DACEN
+ DAC interface clock enable
+ bit
+ 29
+ 1
+
+
+ PWREN
+ Power interface clock enable
+ bit
+ 28
+ 1
+
+
+ CRSEN
+ Clock recovery system clock enable
+ bit
+ 27
+ 1
+
+
+ USBEN
+ USB clock enable bit
+ 23
+ 1
+
+
+ I2C2EN
+ I2C2 clock enable bit
+ 22
+ 1
+
+
+ I2C1EN
+ I2C1 clock enable bit
+ 21
+ 1
+
+
+ LPUART1EN
+ LPUART1 clock enable bit
+ 18
+ 1
+
+
+ USART2EN
+ UART2 clock enable bit
+ 17
+ 1
+
+
+ SPI2EN
+ SPI2 clock enable bit
+ 14
+ 1
+
+
+ WWDGEN
+ Window watchdog clock enable
+ bit
+ 11
+ 1
+
+
+ TIM6EN
+ Timer 6 clock enable bit
+ 4
+ 1
+
+
+ TIM2EN
+ Timer2 clock enable bit
+ 0
+ 1
+
+
+ TIM3EN
+ Timer3 clock enable bit
+ 1
+ 1
+
+
+ TIM7EN
+ Timer 7 clock enable bit
+ 5
+ 1
+
+
+ USART4EN
+ USART4 clock enable bit
+ 19
+ 1
+
+
+ USART5EN
+ USART5 clock enable bit
+ 20
+ 1
+
+
+ I2C3EN
+ I2C3 clock enable bit
+ 30
+ 1
+
+
+
+
+ IOPSMEN
+ IOPSMEN
+ GPIO clock enable in sleep mode
+ register
+ 0x3C
+ 0x20
+ read-write
+ 0x0000008F
+
+
+ IOPHSMEN
+ IOPHSMEN
+ 7
+ 1
+
+
+ IOPDSMEN
+ IOPDSMEN
+ 3
+ 1
+
+
+ IOPCSMEN
+ IOPCSMEN
+ 2
+ 1
+
+
+ IOPBSMEN
+ IOPBSMEN
+ 1
+ 1
+
+
+ IOPASMEN
+ IOPASMEN
+ 0
+ 1
+
+
+ IOPESMEN
+ Port E clock enable during Sleep mode
+ bit
+ 4
+ 1
+
+
+
+
+ AHBSMENR
+ AHBSMENR
+ AHB peripheral clock enable in sleep mode
+ register
+ 0x40
+ 0x20
+ read-write
+ 0x01111301
+
+
+ CRYPSMEN
+ Crypto clock enable during sleep mode
+ bit
+ 24
+ 1
+
+
+ RNGSMEN
+ Random Number Generator clock enable
+ during sleep mode bit
+ 20
+ 1
+
+
+ TOUCHSMEN
+ Touch Sensing clock enable during sleep
+ mode bit
+ 16
+ 1
+
+
+ CRCSMEN
+ CRC clock enable during sleep mode
+ bit
+ 12
+ 1
+
+
+ SRAMSMEN
+ SRAM interface clock enable during sleep
+ mode bit
+ 9
+ 1
+
+
+ MIFSMEN
+ NVM interface clock enable during sleep
+ mode bit
+ 8
+ 1
+
+
+ DMASMEN
+ DMA clock enable during sleep mode
+ bit
+ 0
+ 1
+
+
+
+
+ APB2SMENR
+ APB2SMENR
+ APB2 peripheral clock enable in sleep mode
+ register
+ 0x44
+ 0x20
+ read-write
+ 0x00405225
+
+
+ DBGSMEN
+ DBG clock enable during sleep mode
+ bit
+ 22
+ 1
+
+
+ USART1SMEN
+ USART1 clock enable during sleep mode
+ bit
+ 14
+ 1
+
+
+ SPI1SMEN
+ SPI1 clock enable during sleep mode
+ bit
+ 12
+ 1
+
+
+ ADCSMEN
+ ADC clock enable during sleep mode
+ bit
+ 9
+ 1
+
+
+ TIM22SMEN
+ TIM22 timer clock enable during sleep
+ mode bit
+ 5
+ 1
+
+
+ TIM21SMEN
+ TIM21 timer clock enable during sleep
+ mode bit
+ 2
+ 1
+
+
+ SYSCFGSMEN
+ System configuration controller clock
+ enable during sleep mode bit
+ 0
+ 1
+
+
+
+
+ APB1SMENR
+ APB1SMENR
+ APB1 peripheral clock enable in sleep mode
+ register
+ 0x48
+ 0x20
+ read-write
+ 0xB8E64A11
+
+
+ LPTIM1SMEN
+ Low power timer clock enable during
+ sleep mode bit
+ 31
+ 1
+
+
+ DACSMEN
+ DAC interface clock enable during sleep
+ mode bit
+ 29
+ 1
+
+
+ PWRSMEN
+ Power interface clock enable during
+ sleep mode bit
+ 28
+ 1
+
+
+ CRSSMEN
+ Clock recovery system clock enable
+ during sleep mode bit
+ 27
+ 1
+
+
+ USBSMEN
+ USB clock enable during sleep mode
+ bit
+ 23
+ 1
+
+
+ I2C2SMEN
+ I2C2 clock enable during sleep mode
+ bit
+ 22
+ 1
+
+
+ I2C1SMEN
+ I2C1 clock enable during sleep mode
+ bit
+ 21
+ 1
+
+
+ LPUART1SMEN
+ LPUART1 clock enable during sleep mode
+ bit
+ 18
+ 1
+
+
+ USART2SMEN
+ UART2 clock enable during sleep mode
+ bit
+ 17
+ 1
+
+
+ SPI2SMEN
+ SPI2 clock enable during sleep mode
+ bit
+ 14
+ 1
+
+
+ WWDGSMEN
+ Window watchdog clock enable during
+ sleep mode bit
+ 11
+ 1
+
+
+ TIM6SMEN
+ Timer 6 clock enable during sleep mode
+ bit
+ 4
+ 1
+
+
+ TIM2SMEN
+ Timer2 clock enable during sleep mode
+ bit
+ 0
+ 1
+
+
+ TIM3SMEN
+ Timer3 clock enable during Sleep mode
+ bit
+ 1
+ 1
+
+
+ TIM7SMEN
+ Timer 7 clock enable during Sleep mode
+ bit
+ 5
+ 1
+
+
+ USART4SMEN
+ USART4 clock enable during Sleep mode
+ bit
+ 19
+ 1
+
+
+ USART5SMEN
+ USART5 clock enable during Sleep mode
+ bit
+ 20
+ 1
+
+
+ I2C3SMEN
+ 2C3 clock enable during Sleep mode
+ bit
+ 30
+ 1
+
+
+
+
+ CCIPR
+ CCIPR
+ Clock configuration register
+ 0x4C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ HSI48MSEL
+ 48 MHz HSI48 clock source selection
+ bit
+ 26
+ 1
+
+
+ LPTIM1SEL1
+ Low Power Timer clock source selection
+ bits
+ 19
+ 1
+
+
+ LPTIM1SEL0
+ LPTIM1SEL0
+ 18
+ 1
+
+
+ I2C1SEL1
+ I2C1 clock source selection
+ bits
+ 13
+ 1
+
+
+ I2C1SEL0
+ I2C1SEL0
+ 12
+ 1
+
+
+ LPUART1SEL1
+ LPUART1 clock source selection
+ bits
+ 11
+ 1
+
+
+ LPUART1SEL0
+ LPUART1SEL0
+ 10
+ 1
+
+
+ USART2SEL1
+ USART2 clock source selection
+ bits
+ 3
+ 1
+
+
+ USART2SEL0
+ USART2SEL0
+ 2
+ 1
+
+
+ USART1SEL1
+ USART1 clock source selection
+ bits
+ 1
+ 1
+
+
+ USART1SEL0
+ USART1SEL0
+ 0
+ 1
+
+
+ I2C3SEL
+ I2C3 clock source selection
+ bits
+ 16
+ 2
+
+
+
+
+ CSR
+ CSR
+ Control and status register
+ 0x50
+ 0x20
+ 0x0C000000
+
+
+ LPWRSTF
+ Low-power reset flag
+ 31
+ 1
+ read-write
+
+
+ WWDGRSTF
+ Window watchdog reset flag
+ 30
+ 1
+ read-write
+
+
+ IWDGRSTF
+ Independent watchdog reset
+ flag
+ 29
+ 1
+ read-write
+
+
+ SFTRSTF
+ Software reset flag
+ 28
+ 1
+ read-write
+
+
+ PORRSTF
+ POR/PDR reset flag
+ 27
+ 1
+ read-write
+
+
+ PINRSTF
+ PIN reset flag
+ 26
+ 1
+ read-write
+
+
+ OBLRSTF
+ OBLRSTF
+ 25
+ 1
+ read-write
+
+
+ RMVF
+ Remove reset flag
+ 24
+ 1
+ read-write
+
+
+ RTCRST
+ RTC software reset bit
+ 19
+ 1
+ read-write
+
+
+ RTCEN
+ RTC clock enable bit
+ 18
+ 1
+ read-write
+
+
+ RTCSEL
+ RTC and LCD clock source selection
+ bits
+ 16
+ 2
+ read-write
+
+
+ CSSLSED
+ CSS on LSE failure detection
+ flag
+ 14
+ 1
+ read-write
+
+
+ CSSLSEON
+ CSSLSEON
+ 13
+ 1
+ read-write
+
+
+ LSEDRV
+ LSEDRV
+ 11
+ 2
+ read-write
+
+
+ LSEBYP
+ External low-speed oscillator bypass
+ bit
+ 10
+ 1
+ read-write
+
+
+ LSERDY
+ External low-speed oscillator ready
+ bit
+ 9
+ 1
+ read-only
+
+
+ LSEON
+ External low-speed oscillator enable
+ bit
+ 8
+ 1
+ read-write
+
+
+ LSIRDY
+ Internal low-speed oscillator ready
+ bit
+ 1
+ 1
+ read-write
+
+
+ LSION
+ Internal low-speed oscillator
+ enable
+ 0
+ 1
+ read-write
+
+
+
+
+
+
+ SYSCFG_COMP
+ System configuration controller and
+ Comparator
+ SYSCFG
+ 0x40010000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CFGR1
+ CFGR1
+ SYSCFG configuration register
+ 1
+ 0x0
+ 0x20
+ 0x00000000
+
+
+ BOOT_MODE
+ Boot mode selected by the boot pins
+ status bits
+ 8
+ 2
+ read-only
+
+
+ MEM_MODE
+ Memory mapping selection
+ bits
+ 0
+ 2
+ read-write
+
+
+
+
+ CFGR2
+ CFGR2
+ SYSCFG configuration register
+ 2
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ I2C2_FMP
+ I2C2 Fm+ drive capability enable
+ bit
+ 13
+ 1
+
+
+ I2C1_FMP
+ I2C1 Fm+ drive capability enable
+ bit
+ 12
+ 1
+
+
+ I2C_PB9_FMP
+ Fm+ drive capability on PB9 enable
+ bit
+ 11
+ 1
+
+
+ I2C_PB8_FMP
+ Fm+ drive capability on PB8 enable
+ bit
+ 10
+ 1
+
+
+ I2C_PB7_FMP
+ Fm+ drive capability on PB7 enable
+ bit
+ 9
+ 1
+
+
+ I2C_PB6_FMP
+ Fm+ drive capability on PB6 enable
+ bit
+ 8
+ 1
+
+
+ FWDISEN
+ Firewall disable bit
+ 0
+ 1
+
+
+
+
+ EXTICR1
+ EXTICR1
+ external interrupt configuration register
+ 1
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ EXTI3
+ EXTI x configuration (x = 0 to
+ 3)
+ 12
+ 4
+
+
+ EXTI2
+ EXTI x configuration (x = 0 to
+ 3)
+ 8
+ 4
+
+
+ EXTI1
+ EXTI x configuration (x = 0 to
+ 3)
+ 4
+ 4
+
+
+ EXTI0
+ EXTI x configuration (x = 0 to
+ 3)
+ 0
+ 4
+
+
+
+
+ EXTICR2
+ EXTICR2
+ external interrupt configuration register
+ 2
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ EXTI7
+ EXTI x configuration (x = 4 to
+ 7)
+ 12
+ 4
+
+
+ EXTI6
+ EXTI x configuration (x = 4 to
+ 7)
+ 8
+ 4
+
+
+ EXTI5
+ EXTI x configuration (x = 4 to
+ 7)
+ 4
+ 4
+
+
+ EXTI4
+ EXTI x configuration (x = 4 to
+ 7)
+ 0
+ 4
+
+
+
+
+ EXTICR3
+ EXTICR3
+ external interrupt configuration register
+ 3
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ EXTI11
+ EXTI x configuration (x = 8 to
+ 11)
+ 12
+ 4
+
+
+ EXTI10
+ EXTI10
+ 8
+ 4
+
+
+ EXTI9
+ EXTI x configuration (x = 8 to
+ 11)
+ 4
+ 4
+
+
+ EXTI8
+ EXTI x configuration (x = 8 to
+ 11)
+ 0
+ 4
+
+
+
+
+ EXTICR4
+ EXTICR4
+ external interrupt configuration register
+ 4
+ 0x14
+ 0x20
+ read-write
+ 0x0000
+
+
+ EXTI15
+ EXTI x configuration (x = 12 to
+ 15)
+ 12
+ 4
+
+
+ EXTI14
+ EXTI14
+ 8
+ 4
+
+
+ EXTI13
+ EXTI13
+ 4
+ 4
+
+
+ EXTI12
+ EXTI12
+ 0
+ 4
+
+
+
+
+ CFGR3
+ CFGR3
+ SYSCFG configuration register
+ 3
+ 0x20
+ 0x20
+ 0x00000000
+
+
+ REF_LOCK
+ REF_CTRL lock bit
+ 31
+ 1
+ write-only
+
+
+ VREFINT_RDYF
+ VREFINT ready flag
+ 30
+ 1
+ read-only
+
+
+ VREFINT_COMP_RDYF
+ VREFINT for comparator ready
+ flag
+ 29
+ 1
+ read-only
+
+
+ VREFINT_ADC_RDYF
+ VREFINT for ADC ready flag
+ 28
+ 1
+ read-only
+
+
+ SENSOR_ADC_RDYF
+ Sensor for ADC ready flag
+ 27
+ 1
+ read-only
+
+
+ REF_RC48MHz_RDYF
+ VREFINT for 48 MHz RC oscillator ready
+ flag
+ 26
+ 1
+ read-only
+
+
+ ENREF_RC48MHz
+ VREFINT reference for 48 MHz RC
+ oscillator enable bit
+ 13
+ 1
+ read-write
+
+
+ ENBUF_VREFINT_COMP
+ VREFINT reference for comparator 2
+ enable bit
+ 12
+ 1
+ read-write
+
+
+ ENBUF_SENSOR_ADC
+ Sensor reference for ADC enable
+ bit
+ 9
+ 1
+ read-write
+
+
+ ENBUF_BGAP_ADC
+ VREFINT reference for ADC enable
+ bit
+ 8
+ 1
+ read-write
+
+
+ SEL_VREF_OUT
+ BGAP_ADC connection bit
+ 4
+ 2
+ read-write
+
+
+ EN_BGAP
+ Vref Enable bit
+ 0
+ 1
+ read-write
+
+
+
+
+ COMP1_CSR
+ COMP1_CSR
+ Comparator 1 control and status
+ register
+ 0x18
+ 0x20
+ 0x00000000
+
+
+ COMP1LOCK
+ COMP1_CSR register lock
+ bit
+ 31
+ 1
+ read-only
+
+
+ COMP1VALUE
+ Comparator 1 output status
+ bit
+ 30
+ 1
+ read-only
+
+
+ COMP1POLARITY
+ Comparator 1 polarity selection
+ bit
+ 15
+ 1
+ read-write
+
+
+ COMP1LPTIMIN1
+ Comparator 1 LPTIM input propagation
+ bit
+ 12
+ 1
+ read-write
+
+
+ COMP1WM
+ Comparator 1 window mode selection
+ bit
+ 8
+ 1
+ read-write
+
+
+ COMP1INNSEL
+ Comparator 1 Input Minus connection
+ configuration bit
+ 4
+ 2
+ read-write
+
+
+ COMP1EN
+ Comparator 1 enable bit
+ 0
+ 1
+ read-write
+
+
+
+
+ COMP2_CSR
+ COMP2_CSR
+ Comparator 2 control and status
+ register
+ 0x1C
+ 0x20
+ 0x00000000
+
+
+ COMP2LOCK
+ COMP2_CSR register lock
+ bit
+ 31
+ 1
+ read-only
+
+
+ COMP2VALUE
+ Comparator 2 output status
+ bit
+ 20
+ 1
+ read-only
+
+
+ COMP2POLARITY
+ Comparator 2 polarity selection
+ bit
+ 15
+ 1
+ read-write
+
+
+ COMP2LPTIMIN1
+ Comparator 2 LPTIM input 1 propagation
+ bit
+ 13
+ 1
+ read-write
+
+
+ COMP2LPTIMIN2
+ Comparator 2 LPTIM input 2 propagation
+ bit
+ 12
+ 1
+ read-write
+
+
+ COMP2INPSEL
+ Comparator 2 Input Plus connection
+ configuration bit
+ 8
+ 3
+ read-write
+
+
+ COMP2INNSEL
+ Comparator 2 Input Minus connection
+ configuration bit
+ 4
+ 3
+ read-write
+
+
+ COMP2SPEED
+ Comparator 2 power mode selection
+ bit
+ 3
+ 1
+ read-write
+
+
+ COMP2EN
+ Comparator 2 enable bit
+ 0
+ 1
+ read-write
+
+
+
+
+
+
+ SPI1
+ Serial peripheral interface
+ SPI
+ 0x40013000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ BIDIMODE
+ Bidirectional data mode
+ enable
+ 15
+ 1
+
+
+ BIDIOE
+ Output enable in bidirectional
+ mode
+ 14
+ 1
+
+
+ CRCEN
+ Hardware CRC calculation
+ enable
+ 13
+ 1
+
+
+ CRCNEXT
+ CRC transfer next
+ 12
+ 1
+
+
+ DFF
+ Data frame format
+ 11
+ 1
+
+
+ RXONLY
+ Receive only
+ 10
+ 1
+
+
+ SSM
+ Software slave management
+ 9
+ 1
+
+
+ SSI
+ Internal slave select
+ 8
+ 1
+
+
+ LSBFIRST
+ Frame format
+ 7
+ 1
+
+
+ SPE
+ SPI enable
+ 6
+ 1
+
+
+ BR
+ Baud rate control
+ 3
+ 3
+
+
+ MSTR
+ Master selection
+ 2
+ 1
+
+
+ CPOL
+ Clock polarity
+ 1
+ 1
+
+
+ CPHA
+ Clock phase
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ RXDMAEN
+ Rx buffer DMA enable
+ 0
+ 1
+
+
+ TXDMAEN
+ Tx buffer DMA enable
+ 1
+ 1
+
+
+ SSOE
+ SS output enable
+ 2
+ 1
+
+
+ FRF
+ Frame format
+ 4
+ 1
+
+
+ ERRIE
+ Error interrupt enable
+ 5
+ 1
+
+
+ RXNEIE
+ RX buffer not empty interrupt
+ enable
+ 6
+ 1
+
+
+ TXEIE
+ Tx buffer empty interrupt
+ enable
+ 7
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x8
+ 0x20
+ 0x0002
+
+
+ RXNE
+ Receive buffer not empty
+ 0
+ 1
+ read-only
+
+
+ TXE
+ Transmit buffer empty
+ 1
+ 1
+ read-only
+
+
+ CHSIDE
+ Channel side
+ 2
+ 1
+ read-only
+
+
+ UDR
+ Underrun flag
+ 3
+ 1
+ read-only
+
+
+ CRCERR
+ CRC error flag
+ 4
+ 1
+ read-write
+
+
+ MODF
+ Mode fault
+ 5
+ 1
+ read-only
+
+
+ OVR
+ Overrun flag
+ 6
+ 1
+ read-only
+
+
+ BSY
+ Busy flag
+ 7
+ 1
+ read-only
+
+
+ TIFRFE
+ TI frame format error
+ 8
+ 1
+ read-only
+
+
+
+
+ DR
+ DR
+ data register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ DR
+ Data register
+ 0
+ 16
+
+
+
+
+ CRCPR
+ CRCPR
+ CRC polynomial register
+ 0x10
+ 0x20
+ read-write
+ 0x0007
+
+
+ CRCPOLY
+ CRC polynomial register
+ 0
+ 16
+
+
+
+
+ RXCRCR
+ RXCRCR
+ RX CRC register
+ 0x14
+ 0x20
+ read-only
+ 0x0000
+
+
+ RxCRC
+ Rx CRC register
+ 0
+ 16
+
+
+
+
+ TXCRCR
+ TXCRCR
+ TX CRC register
+ 0x18
+ 0x20
+ read-only
+ 0x0000
+
+
+ TxCRC
+ Tx CRC register
+ 0
+ 16
+
+
+
+
+ I2SCFGR
+ I2SCFGR
+ I2S configuration register
+ 0x1C
+ 0x20
+ read-write
+ 0x0000
+
+
+ I2SMOD
+ I2S mode selection
+ 11
+ 1
+
+
+ I2SE
+ I2S Enable
+ 10
+ 1
+
+
+ I2SCFG
+ I2S configuration mode
+ 8
+ 2
+
+
+ PCMSYNC
+ PCM frame synchronization
+ 7
+ 1
+
+
+ I2SSTD
+ I2S standard selection
+ 4
+ 2
+
+
+ CKPOL
+ Steady state clock
+ polarity
+ 3
+ 1
+
+
+ DATLEN
+ Data length to be
+ transferred
+ 1
+ 2
+
+
+ CHLEN
+ Channel length (number of bits per audio
+ channel)
+ 0
+ 1
+
+
+
+
+ I2SPR
+ I2SPR
+ I2S prescaler register
+ 0x20
+ 0x20
+ read-write
+ 0x00000010
+
+
+ MCKOE
+ Master clock output enable
+ 9
+ 1
+
+
+ ODD
+ Odd factor for the
+ prescaler
+ 8
+ 1
+
+
+ I2SDIV
+ I2S Linear prescaler
+ 0
+ 8
+
+
+
+
+
+
+ SPI2
+ 0x40003800
+
+ SPI1
+ SPI1_global_interrupt
+ 25
+
+
+
+ I2C1
+ Inter-integrated circuit
+ I2C
+ 0x40005400
+
+ 0x0
+ 0x400
+ registers
+
+
+ SPI2
+ SPI2 global interrupt
+ 26
+
+
+
+ CR1
+ CR1
+ Control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PE
+ Peripheral enable
+ 0
+ 1
+
+
+ TXIE
+ TX Interrupt enable
+ 1
+ 1
+
+
+ RXIE
+ RX Interrupt enable
+ 2
+ 1
+
+
+ ADDRIE
+ Address match interrupt enable (slave
+ only)
+ 3
+ 1
+
+
+ NACKIE
+ Not acknowledge received interrupt
+ enable
+ 4
+ 1
+
+
+ STOPIE
+ STOP detection Interrupt
+ enable
+ 5
+ 1
+
+
+ TCIE
+ Transfer Complete interrupt
+ enable
+ 6
+ 1
+
+
+ ERRIE
+ Error interrupts enable
+ 7
+ 1
+
+
+ DNF
+ Digital noise filter
+ 8
+ 4
+
+
+ ANFOFF
+ Analog noise filter OFF
+ 12
+ 1
+
+
+ TXDMAEN
+ DMA transmission requests
+ enable
+ 14
+ 1
+
+
+ RXDMAEN
+ DMA reception requests
+ enable
+ 15
+ 1
+
+
+ SBC
+ Slave byte control
+ 16
+ 1
+
+
+ NOSTRETCH
+ Clock stretching disable
+ 17
+ 1
+
+
+ WUPEN
+ Wakeup from STOP enable
+ 18
+ 1
+
+
+ GCEN
+ General call enable
+ 19
+ 1
+
+
+ SMBHEN
+ SMBus Host address enable
+ 20
+ 1
+
+
+ SMBDEN
+ SMBus Device Default address
+ enable
+ 21
+ 1
+
+
+ ALERTEN
+ SMBUS alert enable
+ 22
+ 1
+
+
+ PECEN
+ PEC enable
+ 23
+ 1
+
+
+
+
+ CR2
+ CR2
+ Control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PECBYTE
+ Packet error checking byte
+ 26
+ 1
+
+
+ AUTOEND
+ Automatic end mode (master
+ mode)
+ 25
+ 1
+
+
+ RELOAD
+ NBYTES reload mode
+ 24
+ 1
+
+
+ NBYTES
+ Number of bytes
+ 16
+ 8
+
+
+ NACK
+ NACK generation (slave
+ mode)
+ 15
+ 1
+
+
+ STOP
+ Stop generation (master
+ mode)
+ 14
+ 1
+
+
+ START
+ Start generation
+ 13
+ 1
+
+
+ HEAD10R
+ 10-bit address header only read
+ direction (master receiver mode)
+ 12
+ 1
+
+
+ ADD10
+ 10-bit addressing mode (master
+ mode)
+ 11
+ 1
+
+
+ RD_WRN
+ Transfer direction (master
+ mode)
+ 10
+ 1
+
+
+ SADD
+ Slave address bit (master
+ mode)
+ 0
+ 10
+
+
+
+
+ OAR1
+ OAR1
+ Own address register 1
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OA1
+ Interface address
+ 0
+ 10
+
+
+ OA1MODE
+ Own Address 1 10-bit mode
+ 10
+ 1
+
+
+ OA1EN
+ Own Address 1 enable
+ 15
+ 1
+
+
+
+
+ OAR2
+ OAR2
+ Own address register 2
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OA2
+ Interface address
+ 1
+ 7
+
+
+ OA2MSK
+ Own Address 2 masks
+ 8
+ 3
+
+
+ OA2EN
+ Own Address 2 enable
+ 15
+ 1
+
+
+
+
+ TIMINGR
+ TIMINGR
+ Timing register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SCLL
+ SCL low period (master
+ mode)
+ 0
+ 8
+
+
+ SCLH
+ SCL high period (master
+ mode)
+ 8
+ 8
+
+
+ SDADEL
+ Data hold time
+ 16
+ 4
+
+
+ SCLDEL
+ Data setup time
+ 20
+ 4
+
+
+ PRESC
+ Timing prescaler
+ 28
+ 4
+
+
+
+
+ TIMEOUTR
+ TIMEOUTR
+ Status register 1
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIMEOUTA
+ Bus timeout A
+ 0
+ 12
+
+
+ TIDLE
+ Idle clock timeout
+ detection
+ 12
+ 1
+
+
+ TIMOUTEN
+ Clock timeout enable
+ 15
+ 1
+
+
+ TIMEOUTB
+ Bus timeout B
+ 16
+ 12
+
+
+ TEXTEN
+ Extended clock timeout
+ enable
+ 31
+ 1
+
+
+
+
+ ISR
+ ISR
+ Interrupt and Status register
+ 0x18
+ 0x20
+ 0x00000001
+
+
+ ADDCODE
+ Address match code (Slave
+ mode)
+ 17
+ 7
+ read-only
+
+
+ DIR
+ Transfer direction (Slave
+ mode)
+ 16
+ 1
+ read-only
+
+
+ BUSY
+ Bus busy
+ 15
+ 1
+ read-only
+
+
+ ALERT
+ SMBus alert
+ 13
+ 1
+ read-only
+
+
+ TIMEOUT
+ Timeout or t_low detection
+ flag
+ 12
+ 1
+ read-only
+
+
+ PECERR
+ PEC Error in reception
+ 11
+ 1
+ read-only
+
+
+ OVR
+ Overrun/Underrun (slave
+ mode)
+ 10
+ 1
+ read-only
+
+
+ ARLO
+ Arbitration lost
+ 9
+ 1
+ read-only
+
+
+ BERR
+ Bus error
+ 8
+ 1
+ read-only
+
+
+ TCR
+ Transfer Complete Reload
+ 7
+ 1
+ read-only
+
+
+ TC
+ Transfer Complete (master
+ mode)
+ 6
+ 1
+ read-only
+
+
+ STOPF
+ Stop detection flag
+ 5
+ 1
+ read-only
+
+
+ NACKF
+ Not acknowledge received
+ flag
+ 4
+ 1
+ read-only
+
+
+ ADDR
+ Address matched (slave
+ mode)
+ 3
+ 1
+ read-only
+
+
+ RXNE
+ Receive data register not empty
+ (receivers)
+ 2
+ 1
+ read-only
+
+
+ TXIS
+ Transmit interrupt status
+ (transmitters)
+ 1
+ 1
+ read-write
+
+
+ TXE
+ Transmit data register empty
+ (transmitters)
+ 0
+ 1
+ read-write
+
+
+
+
+ ICR
+ ICR
+ Interrupt clear register
+ 0x1C
+ 0x20
+ write-only
+ 0x00000000
+
+
+ ALERTCF
+ Alert flag clear
+ 13
+ 1
+
+
+ TIMOUTCF
+ Timeout detection flag
+ clear
+ 12
+ 1
+
+
+ PECCF
+ PEC Error flag clear
+ 11
+ 1
+
+
+ OVRCF
+ Overrun/Underrun flag
+ clear
+ 10
+ 1
+
+
+ ARLOCF
+ Arbitration lost flag
+ clear
+ 9
+ 1
+
+
+ BERRCF
+ Bus error flag clear
+ 8
+ 1
+
+
+ STOPCF
+ Stop detection flag clear
+ 5
+ 1
+
+
+ NACKCF
+ Not Acknowledge flag clear
+ 4
+ 1
+
+
+ ADDRCF
+ Address Matched flag clear
+ 3
+ 1
+
+
+
+
+ PECR
+ PECR
+ PEC register
+ 0x20
+ 0x20
+ read-only
+ 0x00000000
+
+
+ PEC
+ Packet error checking
+ register
+ 0
+ 8
+
+
+
+
+ RXDR
+ RXDR
+ Receive data register
+ 0x24
+ 0x20
+ read-only
+ 0x00000000
+
+
+ RXDATA
+ 8-bit receive data
+ 0
+ 8
+
+
+
+
+ TXDR
+ TXDR
+ Transmit data register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TXDATA
+ 8-bit transmit data
+ 0
+ 8
+
+
+
+
+
+
+ I2C2
+ 0x40005800
+
+ I2C1
+ I2C1 global interrupt
+ 23
+
+
+ I2C2
+ I2C2 global interrupt
+ 24
+
+
+
+ I2C3
+ 0x40007800
+
+
+ PWR
+ Power control
+ PWR
+ 0x40007000
+
+ 0x0
+ 0x400
+ registers
+
+
+ I2C3
+ I2C3 global interrupt
+ 21
+
+
+
+ CR
+ CR
+ power control register
+ 0x0
+ 0x20
+ read-write
+ 0x00001000
+
+
+ LPDS
+ Low-power deep sleep
+ 0
+ 1
+
+
+ PDDS
+ Power down deepsleep
+ 1
+ 1
+
+
+ CWUF
+ Clear wakeup flag
+ 2
+ 1
+
+
+ CSBF
+ Clear standby flag
+ 3
+ 1
+
+
+ PVDE
+ Power voltage detector
+ enable
+ 4
+ 1
+
+
+ PLS
+ PVD level selection
+ 5
+ 3
+
+
+ DBP
+ Disable backup domain write
+ protection
+ 8
+ 1
+
+
+ ULP
+ Ultra-low-power mode
+ 9
+ 1
+
+
+ FWU
+ Fast wakeup
+ 10
+ 1
+
+
+ VOS
+ Voltage scaling range
+ selection
+ 11
+ 2
+
+
+ DS_EE_KOFF
+ Deep sleep mode with Flash memory kept
+ off
+ 13
+ 1
+
+
+ LPRUN
+ Low power run mode
+ 14
+ 1
+
+
+
+
+ CSR
+ CSR
+ power control/status register
+ 0x4
+ 0x20
+ 0x00000000
+
+
+ BRE
+ Backup regulator enable
+ 9
+ 1
+ read-write
+
+
+ EWUP
+ Enable WKUP pin
+ 8
+ 1
+ read-write
+
+
+ BRR
+ Backup regulator ready
+ 3
+ 1
+ read-only
+
+
+ PVDO
+ PVD output
+ 2
+ 1
+ read-only
+
+
+ SBF
+ Standby flag
+ 1
+ 1
+ read-only
+
+
+ WUF
+ Wakeup flag
+ 0
+ 1
+ read-only
+
+
+ VOSF
+ Voltage Scaling select
+ flag
+ 4
+ 1
+ read-only
+
+
+ REGLPF
+ Regulator LP flag
+ 5
+ 1
+ read-only
+
+
+
+
+
+
+ Flash
+ Flash
+ Flash
+ 0x40022000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ ACR
+ ACR
+ Access control register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LATENCY
+ Latency
+ 0
+ 1
+
+
+ PRFTEN
+ Prefetch enable
+ 1
+ 1
+
+
+ SLEEP_PD
+ Flash mode during Sleep
+ 3
+ 1
+
+
+ RUN_PD
+ Flash mode during Run
+ 4
+ 1
+
+
+ DESAB_BUF
+ Disable Buffer
+ 5
+ 1
+
+
+ PRE_READ
+ Pre-read data address
+ 6
+ 1
+
+
+
+
+ PECR
+ PECR
+ Program/erase control register
+ 0x4
+ 0x20
+ read-write
+ 0x00000007
+
+
+ PELOCK
+ FLASH_PECR and data EEPROM
+ lock
+ 0
+ 1
+
+
+ PRGLOCK
+ Program memory lock
+ 1
+ 1
+
+
+ OPTLOCK
+ Option bytes block lock
+ 2
+ 1
+
+
+ PROG
+ Program memory selection
+ 3
+ 1
+
+
+ DATA
+ Data EEPROM selection
+ 4
+ 1
+
+
+ FTDW
+ Fixed time data write for Byte, Half
+ Word and Word programming
+ 8
+ 1
+
+
+ ERASE
+ Page or Double Word erase
+ mode
+ 9
+ 1
+
+
+ FPRG
+ Half Page/Double Word programming
+ mode
+ 10
+ 1
+
+
+ PARALLELBANK
+ Parallel bank mode
+ 15
+ 1
+
+
+ EOPIE
+ End of programming interrupt
+ enable
+ 16
+ 1
+
+
+ ERRIE
+ Error interrupt enable
+ 17
+ 1
+
+
+ OBL_LAUNCH
+ Launch the option byte
+ loading
+ 18
+ 1
+
+
+
+
+ PDKEYR
+ PDKEYR
+ Power down key register
+ 0x8
+ 0x20
+ write-only
+ 0x00000000
+
+
+ PDKEYR
+ RUN_PD in FLASH_ACR key
+ 0
+ 32
+
+
+
+
+ PEKEYR
+ PEKEYR
+ Program/erase key register
+ 0xC
+ 0x20
+ write-only
+ 0x00000000
+
+
+ PEKEYR
+ FLASH_PEC and data EEPROM
+ key
+ 0
+ 32
+
+
+
+
+ PRGKEYR
+ PRGKEYR
+ Program memory key register
+ 0x10
+ 0x20
+ write-only
+ 0x00000000
+
+
+ PRGKEYR
+ Program memory key
+ 0
+ 32
+
+
+
+
+ OPTKEYR
+ OPTKEYR
+ Option byte key register
+ 0x14
+ 0x20
+ write-only
+ 0x00000000
+
+
+ OPTKEYR
+ Option byte key
+ 0
+ 32
+
+
+
+
+ SR
+ SR
+ Status register
+ 0x18
+ 0x20
+ 0x00000004
+
+
+ BSY
+ Write/erase operations in
+ progress
+ 0
+ 1
+ read-only
+
+
+ EOP
+ End of operation
+ 1
+ 1
+ read-only
+
+
+ ENDHV
+ End of high voltage
+ 2
+ 1
+ read-only
+
+
+ READY
+ Flash memory module ready after low
+ power mode
+ 3
+ 1
+ read-only
+
+
+ WRPERR
+ Write protected error
+ 8
+ 1
+ read-write
+
+
+ PGAERR
+ Programming alignment
+ error
+ 9
+ 1
+ read-write
+
+
+ SIZERR
+ Size error
+ 10
+ 1
+ read-write
+
+
+ OPTVERR
+ Option validity error
+ 11
+ 1
+ read-write
+
+
+ RDERR
+ RDERR
+ 14
+ 1
+ read-write
+
+
+ NOTZEROERR
+ NOTZEROERR
+ 16
+ 1
+ read-write
+
+
+ FWWERR
+ FWWERR
+ 17
+ 1
+ read-write
+
+
+
+
+ OBR
+ OBR
+ Option byte register
+ 0x1C
+ 0x20
+ read-only
+ 0x00F80000
+
+
+ RDPRT
+ Read protection
+ 0
+ 8
+
+
+ BOR_LEV
+ BOR_LEV
+ 16
+ 4
+
+
+ SPRMOD
+ Selection of protection mode of WPR
+ bits
+ 8
+ 1
+
+
+
+
+ WRPR
+ WRPR
+ Write protection register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ WRP
+ Write protection
+ 0
+ 16
+
+
+
+
+
+
+ EXTI
+ External interrupt/event
+ controller
+ EXTI
+ 0x40010400
+
+ 0x0
+ 0x400
+ registers
+
+
+ PVD
+ PVD through EXTI line detection
+ 1
+
+
+ EXTI0_1
+ EXTI Line[1:0] interrupts
+ 5
+
+
+ EXTI2_3
+ EXTI Line[3:2] interrupts
+ 6
+
+
+ EXTI4_15
+ EXTI Line15 and EXTI4 interrupts
+ 7
+
+
+
+ IMR
+ IMR
+ Interrupt mask register
+ (EXTI_IMR)
+ 0x0
+ 0x20
+ read-write
+ 0xFF840000
+
+
+ IM0
+ Interrupt Mask on line 0
+ 0
+ 1
+
+
+ IM1
+ Interrupt Mask on line 1
+ 1
+ 1
+
+
+ IM2
+ Interrupt Mask on line 2
+ 2
+ 1
+
+
+ IM3
+ Interrupt Mask on line 3
+ 3
+ 1
+
+
+ IM4
+ Interrupt Mask on line 4
+ 4
+ 1
+
+
+ IM5
+ Interrupt Mask on line 5
+ 5
+ 1
+
+
+ IM6
+ Interrupt Mask on line 6
+ 6
+ 1
+
+
+ IM7
+ Interrupt Mask on line 7
+ 7
+ 1
+
+
+ IM8
+ Interrupt Mask on line 8
+ 8
+ 1
+
+
+ IM9
+ Interrupt Mask on line 9
+ 9
+ 1
+
+
+ IM10
+ Interrupt Mask on line 10
+ 10
+ 1
+
+
+ IM11
+ Interrupt Mask on line 11
+ 11
+ 1
+
+
+ IM12
+ Interrupt Mask on line 12
+ 12
+ 1
+
+
+ IM13
+ Interrupt Mask on line 13
+ 13
+ 1
+
+
+ IM14
+ Interrupt Mask on line 14
+ 14
+ 1
+
+
+ IM15
+ Interrupt Mask on line 15
+ 15
+ 1
+
+
+ IM16
+ Interrupt Mask on line 16
+ 16
+ 1
+
+
+ IM17
+ Interrupt Mask on line 17
+ 17
+ 1
+
+
+ IM18
+ Interrupt Mask on line 18
+ 18
+ 1
+
+
+ IM19
+ Interrupt Mask on line 19
+ 19
+ 1
+
+
+ IM20
+ Interrupt Mask on line 20
+ 20
+ 1
+
+
+ IM21
+ Interrupt Mask on line 21
+ 21
+ 1
+
+
+ IM22
+ Interrupt Mask on line 22
+ 22
+ 1
+
+
+ IM23
+ Interrupt Mask on line 23
+ 23
+ 1
+
+
+ IM24
+ Interrupt Mask on line 24
+ 24
+ 1
+
+
+ IM25
+ Interrupt Mask on line 25
+ 25
+ 1
+
+
+ IM26
+ Interrupt Mask on line 27
+ 26
+ 1
+
+
+ IM28
+ Interrupt Mask on line 27
+ 28
+ 1
+
+
+ IM29
+ Interrupt Mask on line 27
+ 29
+ 1
+
+
+
+
+ EMR
+ EMR
+ Event mask register (EXTI_EMR)
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EM0
+ Event Mask on line 0
+ 0
+ 1
+
+
+ EM1
+ Event Mask on line 1
+ 1
+ 1
+
+
+ EM2
+ Event Mask on line 2
+ 2
+ 1
+
+
+ EM3
+ Event Mask on line 3
+ 3
+ 1
+
+
+ EM4
+ Event Mask on line 4
+ 4
+ 1
+
+
+ EM5
+ Event Mask on line 5
+ 5
+ 1
+
+
+ EM6
+ Event Mask on line 6
+ 6
+ 1
+
+
+ EM7
+ Event Mask on line 7
+ 7
+ 1
+
+
+ EM8
+ Event Mask on line 8
+ 8
+ 1
+
+
+ EM9
+ Event Mask on line 9
+ 9
+ 1
+
+
+ EM10
+ Event Mask on line 10
+ 10
+ 1
+
+
+ EM11
+ Event Mask on line 11
+ 11
+ 1
+
+
+ EM12
+ Event Mask on line 12
+ 12
+ 1
+
+
+ EM13
+ Event Mask on line 13
+ 13
+ 1
+
+
+ EM14
+ Event Mask on line 14
+ 14
+ 1
+
+
+ EM15
+ Event Mask on line 15
+ 15
+ 1
+
+
+ EM16
+ Event Mask on line 16
+ 16
+ 1
+
+
+ EM17
+ Event Mask on line 17
+ 17
+ 1
+
+
+ EM18
+ Event Mask on line 18
+ 18
+ 1
+
+
+ EM19
+ Event Mask on line 19
+ 19
+ 1
+
+
+ EM20
+ Event Mask on line 20
+ 20
+ 1
+
+
+ EM21
+ Event Mask on line 21
+ 21
+ 1
+
+
+ EM22
+ Event Mask on line 22
+ 22
+ 1
+
+
+ EM23
+ Event Mask on line 23
+ 23
+ 1
+
+
+ EM24
+ Event Mask on line 24
+ 24
+ 1
+
+
+ EM25
+ Event Mask on line 25
+ 25
+ 1
+
+
+ EM26
+ Event Mask on line 26
+ 26
+ 1
+
+
+ EM28
+ Event Mask on line 28
+ 28
+ 1
+
+
+ EM29
+ Event Mask on line 29
+ 29
+ 1
+
+
+
+
+ RTSR
+ RTSR
+ Rising Trigger selection register
+ (EXTI_RTSR)
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ RT0
+ Rising trigger event configuration of
+ line 0
+ 0
+ 1
+
+
+ RT1
+ Rising trigger event configuration of
+ line 1
+ 1
+ 1
+
+
+ RT2
+ Rising trigger event configuration of
+ line 2
+ 2
+ 1
+
+
+ RT3
+ Rising trigger event configuration of
+ line 3
+ 3
+ 1
+
+
+ RT4
+ Rising trigger event configuration of
+ line 4
+ 4
+ 1
+
+
+ RT5
+ Rising trigger event configuration of
+ line 5
+ 5
+ 1
+
+
+ RT6
+ Rising trigger event configuration of
+ line 6
+ 6
+ 1
+
+
+ RT7
+ Rising trigger event configuration of
+ line 7
+ 7
+ 1
+
+
+ RT8
+ Rising trigger event configuration of
+ line 8
+ 8
+ 1
+
+
+ RT9
+ Rising trigger event configuration of
+ line 9
+ 9
+ 1
+
+
+ RT10
+ Rising trigger event configuration of
+ line 10
+ 10
+ 1
+
+
+ RT11
+ Rising trigger event configuration of
+ line 11
+ 11
+ 1
+
+
+ RT12
+ Rising trigger event configuration of
+ line 12
+ 12
+ 1
+
+
+ RT13
+ Rising trigger event configuration of
+ line 13
+ 13
+ 1
+
+
+ RT14
+ Rising trigger event configuration of
+ line 14
+ 14
+ 1
+
+
+ RT15
+ Rising trigger event configuration of
+ line 15
+ 15
+ 1
+
+
+ RT16
+ Rising trigger event configuration of
+ line 16
+ 16
+ 1
+
+
+ RT17
+ Rising trigger event configuration of
+ line 17
+ 17
+ 1
+
+
+ RT19
+ Rising trigger event configuration of
+ line 19
+ 19
+ 1
+
+
+ RT20
+ Rising trigger event configuration of
+ line 20
+ 20
+ 1
+
+
+ RT21
+ Rising trigger event configuration of
+ line 21
+ 21
+ 1
+
+
+ RT22
+ Rising trigger event configuration of
+ line 22
+ 22
+ 1
+
+
+
+
+ FTSR
+ FTSR
+ Falling Trigger selection register
+ (EXTI_FTSR)
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FT0
+ Falling trigger event configuration of
+ line 0
+ 0
+ 1
+
+
+ FT1
+ Falling trigger event configuration of
+ line 1
+ 1
+ 1
+
+
+ FT2
+ Falling trigger event configuration of
+ line 2
+ 2
+ 1
+
+
+ FT3
+ Falling trigger event configuration of
+ line 3
+ 3
+ 1
+
+
+ FT4
+ Falling trigger event configuration of
+ line 4
+ 4
+ 1
+
+
+ FT5
+ Falling trigger event configuration of
+ line 5
+ 5
+ 1
+
+
+ FT6
+ Falling trigger event configuration of
+ line 6
+ 6
+ 1
+
+
+ FT7
+ Falling trigger event configuration of
+ line 7
+ 7
+ 1
+
+
+ FT8
+ Falling trigger event configuration of
+ line 8
+ 8
+ 1
+
+
+ FT9
+ Falling trigger event configuration of
+ line 9
+ 9
+ 1
+
+
+ FT10
+ Falling trigger event configuration of
+ line 10
+ 10
+ 1
+
+
+ FT11
+ Falling trigger event configuration of
+ line 11
+ 11
+ 1
+
+
+ FT12
+ Falling trigger event configuration of
+ line 12
+ 12
+ 1
+
+
+ FT13
+ Falling trigger event configuration of
+ line 13
+ 13
+ 1
+
+
+ FT14
+ Falling trigger event configuration of
+ line 14
+ 14
+ 1
+
+
+ FT15
+ Falling trigger event configuration of
+ line 15
+ 15
+ 1
+
+
+ FT16
+ Falling trigger event configuration of
+ line 16
+ 16
+ 1
+
+
+ FT17
+ Falling trigger event configuration of
+ line 17
+ 17
+ 1
+
+
+ FT19
+ Falling trigger event configuration of
+ line 19
+ 19
+ 1
+
+
+ FT20
+ Falling trigger event configuration of
+ line 20
+ 20
+ 1
+
+
+ FT21
+ Falling trigger event configuration of
+ line 21
+ 21
+ 1
+
+
+ FT22
+ Falling trigger event configuration of
+ line 22
+ 22
+ 1
+
+
+
+
+ SWIER
+ SWIER
+ Software interrupt event register
+ (EXTI_SWIER)
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SWI0
+ Software Interrupt on line
+ 0
+ 0
+ 1
+
+
+ SWI1
+ Software Interrupt on line
+ 1
+ 1
+ 1
+
+
+ SWI2
+ Software Interrupt on line
+ 2
+ 2
+ 1
+
+
+ SWI3
+ Software Interrupt on line
+ 3
+ 3
+ 1
+
+
+ SWI4
+ Software Interrupt on line
+ 4
+ 4
+ 1
+
+
+ SWI5
+ Software Interrupt on line
+ 5
+ 5
+ 1
+
+
+ SWI6
+ Software Interrupt on line
+ 6
+ 6
+ 1
+
+
+ SWI7
+ Software Interrupt on line
+ 7
+ 7
+ 1
+
+
+ SWI8
+ Software Interrupt on line
+ 8
+ 8
+ 1
+
+
+ SWI9
+ Software Interrupt on line
+ 9
+ 9
+ 1
+
+
+ SWI10
+ Software Interrupt on line
+ 10
+ 10
+ 1
+
+
+ SWI11
+ Software Interrupt on line
+ 11
+ 11
+ 1
+
+
+ SWI12
+ Software Interrupt on line
+ 12
+ 12
+ 1
+
+
+ SWI13
+ Software Interrupt on line
+ 13
+ 13
+ 1
+
+
+ SWI14
+ Software Interrupt on line
+ 14
+ 14
+ 1
+
+
+ SWI15
+ Software Interrupt on line
+ 15
+ 15
+ 1
+
+
+ SWI16
+ Software Interrupt on line
+ 16
+ 16
+ 1
+
+
+ SWI17
+ Software Interrupt on line
+ 17
+ 17
+ 1
+
+
+ SWI19
+ Software Interrupt on line
+ 19
+ 19
+ 1
+
+
+ SWI20
+ Software Interrupt on line
+ 20
+ 20
+ 1
+
+
+ SWI21
+ Software Interrupt on line
+ 21
+ 21
+ 1
+
+
+ SWI22
+ Software Interrupt on line
+ 22
+ 22
+ 1
+
+
+
+
+ PR
+ PR
+ Pending register (EXTI_PR)
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PIF0
+ Pending bit 0
+ 0
+ 1
+
+
+ PIF1
+ Pending bit 1
+ 1
+ 1
+
+
+ PIF2
+ Pending bit 2
+ 2
+ 1
+
+
+ PIF3
+ Pending bit 3
+ 3
+ 1
+
+
+ PIF4
+ Pending bit 4
+ 4
+ 1
+
+
+ PIF5
+ Pending bit 5
+ 5
+ 1
+
+
+ PIF6
+ Pending bit 6
+ 6
+ 1
+
+
+ PIF7
+ Pending bit 7
+ 7
+ 1
+
+
+ PIF8
+ Pending bit 8
+ 8
+ 1
+
+
+ PIF9
+ Pending bit 9
+ 9
+ 1
+
+
+ PIF10
+ Pending bit 10
+ 10
+ 1
+
+
+ PIF11
+ Pending bit 11
+ 11
+ 1
+
+
+ PIF12
+ Pending bit 12
+ 12
+ 1
+
+
+ PIF13
+ Pending bit 13
+ 13
+ 1
+
+
+ PIF14
+ Pending bit 14
+ 14
+ 1
+
+
+ PIF15
+ Pending bit 15
+ 15
+ 1
+
+
+ PIF16
+ Pending bit 16
+ 16
+ 1
+
+
+ PIF17
+ Pending bit 17
+ 17
+ 1
+
+
+ PIF19
+ Pending bit 19
+ 19
+ 1
+
+
+ PIF20
+ Pending bit 20
+ 20
+ 1
+
+
+ PIF21
+ Pending bit 21
+ 21
+ 1
+
+
+ PIF22
+ Pending bit 22
+ 22
+ 1
+
+
+
+
+
+
+ ADC
+ Analog-to-digital converter
+ ADC
+ 0x40012400
+
+ 0x0
+ 0x400
+ registers
+
+
+ EXTI2_3
+ EXTI Line[3:2] interrupts
+ 6
+
+
+
+ ISR
+ ISR
+ interrupt and status register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ADRDY
+ ADC ready
+ 0
+ 1
+
+
+ EOSMP
+ End of sampling flag
+ 1
+ 1
+
+
+ EOC
+ End of conversion flag
+ 2
+ 1
+
+
+ EOS
+ End of sequence flag
+ 3
+ 1
+
+
+ OVR
+ ADC overrun
+ 4
+ 1
+
+
+ AWD
+ Analog watchdog flag
+ 7
+ 1
+
+
+ EOCAL
+ End Of Calibration flag
+ 11
+ 1
+
+
+
+
+ IER
+ IER
+ interrupt enable register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ADRDYIE
+ ADC ready interrupt enable
+ 0
+ 1
+
+
+ EOSMPIE
+ End of sampling flag interrupt
+ enable
+ 1
+ 1
+
+
+ EOCIE
+ End of conversion interrupt
+ enable
+ 2
+ 1
+
+
+ EOSIE
+ End of conversion sequence interrupt
+ enable
+ 3
+ 1
+
+
+ OVRIE
+ Overrun interrupt enable
+ 4
+ 1
+
+
+ AWDIE
+ Analog watchdog interrupt
+ enable
+ 7
+ 1
+
+
+ EOCALIE
+ End of calibration interrupt
+ enable
+ 11
+ 1
+
+
+
+
+ CR
+ CR
+ control register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ADEN
+ ADC enable command
+ 0
+ 1
+
+
+ ADDIS
+ ADC disable command
+ 1
+ 1
+
+
+ ADSTART
+ ADC start conversion
+ command
+ 2
+ 1
+
+
+ ADSTP
+ ADC stop conversion
+ command
+ 4
+ 1
+
+
+ ADVREGEN
+ ADC Voltage Regulator
+ Enable
+ 28
+ 1
+
+
+ ADCAL
+ ADC calibration
+ 31
+ 1
+
+
+
+
+ CFGR1
+ CFGR1
+ configuration register 1
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AWDCH
+ Analog watchdog channel
+ selection
+ 26
+ 5
+
+
+ AWDEN
+ Analog watchdog enable
+ 23
+ 1
+
+
+ AWDSGL
+ Enable the watchdog on a single channel
+ or on all channels
+ 22
+ 1
+
+
+ DISCEN
+ Discontinuous mode
+ 16
+ 1
+
+
+ AUTOFF
+ Auto-off mode
+ 15
+ 1
+
+
+ AUTDLY
+ Auto-delayed conversion
+ mode
+ 14
+ 1
+
+
+ CONT
+ Single / continuous conversion
+ mode
+ 13
+ 1
+
+
+ OVRMOD
+ Overrun management mode
+ 12
+ 1
+
+
+ EXTEN
+ External trigger enable and polarity
+ selection
+ 10
+ 2
+
+
+ EXTSEL
+ External trigger selection
+ 6
+ 3
+
+
+ ALIGN
+ Data alignment
+ 5
+ 1
+
+
+ RES
+ Data resolution
+ 3
+ 2
+
+
+ SCANDIR
+ Scan sequence direction
+ 2
+ 1
+
+
+ DMACFG
+ Direct memery access
+ configuration
+ 1
+ 1
+
+
+ DMAEN
+ Direct memory access
+ enable
+ 0
+ 1
+
+
+
+
+ CFGR2
+ CFGR2
+ configuration register 2
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OVSE
+ Oversampler Enable
+ 0
+ 1
+
+
+ OVSR
+ Oversampling ratio
+ 2
+ 3
+
+
+ OVSS
+ Oversampling shift
+ 5
+ 4
+
+
+ TOVS
+ Triggered Oversampling
+ 9
+ 1
+
+
+ CKMODE
+ ADC clock mode
+ 30
+ 2
+
+
+
+
+ SMPR
+ SMPR
+ sampling time register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SMPR
+ Sampling time selection
+ 0
+ 3
+
+
+
+
+ TR
+ TR
+ watchdog threshold register
+ 0x20
+ 0x20
+ read-write
+ 0x0FFF0000
+
+
+ HT
+ Analog watchdog higher
+ threshold
+ 16
+ 12
+
+
+ LT
+ Analog watchdog lower
+ threshold
+ 0
+ 12
+
+
+
+
+ CHSELR
+ CHSELR
+ channel selection register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CHSEL18
+ Channel-x selection
+ 18
+ 1
+
+
+ CHSEL17
+ Channel-x selection
+ 17
+ 1
+
+
+ CHSEL16
+ Channel-x selection
+ 16
+ 1
+
+
+ CHSEL15
+ Channel-x selection
+ 15
+ 1
+
+
+ CHSEL14
+ Channel-x selection
+ 14
+ 1
+
+
+ CHSEL13
+ Channel-x selection
+ 13
+ 1
+
+
+ CHSEL12
+ Channel-x selection
+ 12
+ 1
+
+
+ CHSEL11
+ Channel-x selection
+ 11
+ 1
+
+
+ CHSEL10
+ Channel-x selection
+ 10
+ 1
+
+
+ CHSEL9
+ Channel-x selection
+ 9
+ 1
+
+
+ CHSEL8
+ Channel-x selection
+ 8
+ 1
+
+
+ CHSEL7
+ Channel-x selection
+ 7
+ 1
+
+
+ CHSEL6
+ Channel-x selection
+ 6
+ 1
+
+
+ CHSEL5
+ Channel-x selection
+ 5
+ 1
+
+
+ CHSEL4
+ Channel-x selection
+ 4
+ 1
+
+
+ CHSEL3
+ Channel-x selection
+ 3
+ 1
+
+
+ CHSEL2
+ Channel-x selection
+ 2
+ 1
+
+
+ CHSEL1
+ Channel-x selection
+ 1
+ 1
+
+
+ CHSEL0
+ Channel-x selection
+ 0
+ 1
+
+
+
+
+ DR
+ DR
+ data register
+ 0x40
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DATA
+ Converted data
+ 0
+ 16
+
+
+
+
+ CALFACT
+ CALFACT
+ ADC Calibration factor
+ 0xB4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CALFACT
+ Calibration factor
+ 0
+ 7
+
+
+
+
+ CCR
+ CCR
+ ADC common configuration
+ register
+ 0x308
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRESC
+ ADC prescaler
+ 18
+ 4
+
+
+ VREFEN
+ VREFINT enable
+ 22
+ 1
+
+
+ TSEN
+ Temperature sensor enable
+ 23
+ 1
+
+
+ LFMEN
+ Low Frequency Mode enable
+ 25
+ 1
+
+
+
+
+
+
+ DBGMCU
+ Debug support
+ DBGMCU
+ 0x40015800
+
+ 0x0
+ 0x400
+ registers
+
+
+ ADC_COMP
+ ADC and comparator 1 and 2
+ 12
+
+
+
+ IDCODE
+ IDCODE
+ MCU Device ID Code Register
+ 0x0
+ 0x20
+ read-only
+ 0x0
+
+
+ DEV_ID
+ Device Identifier
+ 0
+ 12
+
+
+ REV_ID
+ Revision Identifier
+ 16
+ 16
+
+
+
+
+ CR
+ CR
+ Debug MCU Configuration
+ Register
+ 0x4
+ 0x20
+ read-write
+ 0x0
+
+
+ DBG_STOP
+ Debug Stop Mode
+ 1
+ 1
+
+
+ DBG_STANDBY
+ Debug Standby Mode
+ 2
+ 1
+
+
+ DBG_SLEEP
+ Debug Sleep Mode
+ 0
+ 1
+
+
+
+
+ APB1_FZ
+ APB1_FZ
+ APB Low Freeze Register
+ 0x8
+ 0x20
+ read-write
+ 0x0
+
+
+ DBG_TIMER2_STOP
+ Debug Timer 2 stopped when Core is
+ halted
+ 0
+ 1
+
+
+ DBG_TIMER6_STOP
+ Debug Timer 6 stopped when Core is
+ halted
+ 4
+ 1
+
+
+ DBG_RTC_STOP
+ Debug RTC stopped when Core is
+ halted
+ 10
+ 1
+
+
+ DBG_WWDG_STOP
+ Debug Window Wachdog stopped when Core
+ is halted
+ 11
+ 1
+
+
+ DBG_IWDG_STOP
+ Debug Independent Wachdog stopped when
+ Core is halted
+ 12
+ 1
+
+
+ DBG_I2C1_STOP
+ I2C1 SMBUS timeout mode stopped when
+ core is halted
+ 21
+ 1
+
+
+ DBG_I2C2_STOP
+ I2C2 SMBUS timeout mode stopped when
+ core is halted
+ 22
+ 1
+
+
+ DBG_LPTIMER_STOP
+ LPTIM1 counter stopped when core is
+ halted
+ 31
+ 1
+
+
+
+
+ APB2_FZ
+ APB2_FZ
+ APB High Freeze Register
+ 0xC
+ 0x20
+ read-write
+ 0x0
+
+
+ DBG_TIMER21_STOP
+ Debug Timer 21 stopped when Core is
+ halted
+ 2
+ 1
+
+
+ DBG_TIMER22_STO
+ Debug Timer 22 stopped when Core is
+ halted
+ 6
+ 1
+
+
+
+
+
+
+ TIM2
+ General-purpose-timers
+ TIM
+ 0x40000000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CKD
+ Clock division
+ 8
+ 2
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ CMS
+ Center-aligned mode
+ selection
+ 5
+ 2
+
+
+ DIR
+ Direction
+ 4
+ 1
+
+
+ OPM
+ One-pulse mode
+ 3
+ 1
+
+
+ URS
+ Update request source
+ 2
+ 1
+
+
+ UDIS
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ TI1S
+ TI1 selection
+ 7
+ 1
+
+
+ MMS
+ Master mode selection
+ 4
+ 3
+
+
+ CCDS
+ Capture/compare DMA
+ selection
+ 3
+ 1
+
+
+
+
+ SMCR
+ SMCR
+ slave mode control register
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ ETP
+ External trigger polarity
+ 15
+ 1
+
+
+ ECE
+ External clock enable
+ 14
+ 1
+
+
+ ETPS
+ External trigger prescaler
+ 12
+ 2
+
+
+ ETF
+ External trigger filter
+ 8
+ 4
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ TS
+ Trigger selection
+ 4
+ 3
+
+
+ SMS
+ Slave mode selection
+ 0
+ 3
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ TDE
+ Trigger DMA request enable
+ 14
+ 1
+
+
+ CC4DE
+ Capture/Compare 4 DMA request
+ enable
+ 12
+ 1
+
+
+ CC3DE
+ Capture/Compare 3 DMA request
+ enable
+ 11
+ 1
+
+
+ CC2DE
+ Capture/Compare 2 DMA request
+ enable
+ 10
+ 1
+
+
+ CC1DE
+ Capture/Compare 1 DMA request
+ enable
+ 9
+ 1
+
+
+ UDE
+ Update DMA request enable
+ 8
+ 1
+
+
+ TIE
+ Trigger interrupt enable
+ 6
+ 1
+
+
+ CC4IE
+ Capture/Compare 4 interrupt
+ enable
+ 4
+ 1
+
+
+ CC3IE
+ Capture/Compare 3 interrupt
+ enable
+ 3
+ 1
+
+
+ CC2IE
+ Capture/Compare 2 interrupt
+ enable
+ 2
+ 1
+
+
+ CC1IE
+ Capture/Compare 1 interrupt
+ enable
+ 1
+ 1
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC4OF
+ Capture/Compare 4 overcapture
+ flag
+ 12
+ 1
+
+
+ CC3OF
+ Capture/Compare 3 overcapture
+ flag
+ 11
+ 1
+
+
+ CC2OF
+ Capture/compare 2 overcapture
+ flag
+ 10
+ 1
+
+
+ CC1OF
+ Capture/Compare 1 overcapture
+ flag
+ 9
+ 1
+
+
+ TIF
+ Trigger interrupt flag
+ 6
+ 1
+
+
+ CC4IF
+ Capture/Compare 4 interrupt
+ flag
+ 4
+ 1
+
+
+ CC3IF
+ Capture/Compare 3 interrupt
+ flag
+ 3
+ 1
+
+
+ CC2IF
+ Capture/Compare 2 interrupt
+ flag
+ 2
+ 1
+
+
+ CC1IF
+ Capture/compare 1 interrupt
+ flag
+ 1
+ 1
+
+
+ UIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ TG
+ Trigger generation
+ 6
+ 1
+
+
+ CC4G
+ Capture/compare 4
+ generation
+ 4
+ 1
+
+
+ CC3G
+ Capture/compare 3
+ generation
+ 3
+ 1
+
+
+ CC2G
+ Capture/compare 2
+ generation
+ 2
+ 1
+
+
+ CC1G
+ Capture/compare 1
+ generation
+ 1
+ 1
+
+
+ UG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CCMR1_Output
+ CCMR1_Output
+ capture/compare mode register 1 (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OC2CE
+ Output compare 2 clear
+ enable
+ 15
+ 1
+
+
+ OC2M
+ Output compare 2 mode
+ 12
+ 3
+
+
+ OC2PE
+ Output compare 2 preload
+ enable
+ 11
+ 1
+
+
+ OC2FE
+ Output compare 2 fast
+ enable
+ 10
+ 1
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ OC1CE
+ Output compare 1 clear
+ enable
+ 7
+ 1
+
+
+ OC1M
+ Output compare 1 mode
+ 4
+ 3
+
+
+ OC1PE
+ Output compare 1 preload
+ enable
+ 3
+ 1
+
+
+ OC1FE
+ Output compare 1 fast
+ enable
+ 2
+ 1
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR1_Input
+ CCMR1_Input
+ capture/compare mode register 1 (input
+ mode)
+ CCMR1_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC2F
+ Input capture 2 filter
+ 12
+ 4
+
+
+ IC2PSC
+ Input capture 2 prescaler
+ 10
+ 2
+
+
+ CC2S
+ Capture/compare 2
+ selection
+ 8
+ 2
+
+
+ IC1F
+ Input capture 1 filter
+ 4
+ 4
+
+
+ IC1PSC
+ Input capture 1 prescaler
+ 2
+ 2
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR2_Output
+ CCMR2_Output
+ capture/compare mode register 2 (output
+ mode)
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OC4CE
+ Output compare 4 clear
+ enable
+ 15
+ 1
+
+
+ OC4M
+ Output compare 4 mode
+ 12
+ 3
+
+
+ OC4PE
+ Output compare 4 preload
+ enable
+ 11
+ 1
+
+
+ OC4FE
+ Output compare 4 fast
+ enable
+ 10
+ 1
+
+
+ CC4S
+ Capture/Compare 4
+ selection
+ 8
+ 2
+
+
+ OC3CE
+ Output compare 3 clear
+ enable
+ 7
+ 1
+
+
+ OC3M
+ Output compare 3 mode
+ 4
+ 3
+
+
+ OC3PE
+ Output compare 3 preload
+ enable
+ 3
+ 1
+
+
+ OC3FE
+ Output compare 3 fast
+ enable
+ 2
+ 1
+
+
+ CC3S
+ Capture/Compare 3
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR2_Input
+ CCMR2_Input
+ capture/compare mode register 2 (input
+ mode)
+ CCMR2_Output
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC4F
+ Input capture 4 filter
+ 12
+ 4
+
+
+ IC4PSC
+ Input capture 4 prescaler
+ 10
+ 2
+
+
+ CC4S
+ Capture/Compare 4
+ selection
+ 8
+ 2
+
+
+ IC3F
+ Input capture 3 filter
+ 4
+ 4
+
+
+ IC3PSC
+ Input capture 3 prescaler
+ 2
+ 2
+
+
+ CC3S
+ Capture/Compare 3
+ selection
+ 0
+ 2
+
+
+
+
+ CCER
+ CCER
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC4NP
+ Capture/Compare 4 output
+ Polarity
+ 15
+ 1
+
+
+ CC4P
+ Capture/Compare 3 output
+ Polarity
+ 13
+ 1
+
+
+ CC4E
+ Capture/Compare 4 output
+ enable
+ 12
+ 1
+
+
+ CC3NP
+ Capture/Compare 3 output
+ Polarity
+ 11
+ 1
+
+
+ CC3P
+ Capture/Compare 3 output
+ Polarity
+ 9
+ 1
+
+
+ CC3E
+ Capture/Compare 3 output
+ enable
+ 8
+ 1
+
+
+ CC2NP
+ Capture/Compare 2 output
+ Polarity
+ 7
+ 1
+
+
+ CC2P
+ Capture/Compare 2 output
+ Polarity
+ 5
+ 1
+
+
+ CC2E
+ Capture/Compare 2 output
+ enable
+ 4
+ 1
+
+
+ CC1NP
+ Capture/Compare 1 output
+ Polarity
+ 3
+ 1
+
+
+ CC1P
+ Capture/Compare 1 output
+ Polarity
+ 1
+ 1
+
+
+ CC1E
+ Capture/Compare 1 output
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT_H
+ High counter value (TIM2
+ only)
+ 16
+ 16
+
+
+ CNT_L
+ Low counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ARR_H
+ High Auto-reload value (TIM2
+ only)
+ 16
+ 16
+
+
+ ARR_L
+ Low Auto-reload value
+ 0
+ 16
+
+
+
+
+ CCR1
+ CCR1
+ capture/compare register 1
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR1_H
+ High Capture/Compare 1 value (TIM2
+ only)
+ 16
+ 16
+
+
+ CCR1_L
+ Low Capture/Compare 1
+ value
+ 0
+ 16
+
+
+
+
+ CCR2
+ CCR2
+ capture/compare register 2
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR2_H
+ High Capture/Compare 2 value (TIM2
+ only)
+ 16
+ 16
+
+
+ CCR2_L
+ Low Capture/Compare 2
+ value
+ 0
+ 16
+
+
+
+
+ CCR3
+ CCR3
+ capture/compare register 3
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR3_H
+ High Capture/Compare value (TIM2
+ only)
+ 16
+ 16
+
+
+ CCR3_L
+ Low Capture/Compare value
+ 0
+ 16
+
+
+
+
+ CCR4
+ CCR4
+ capture/compare register 4
+ 0x40
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR4_H
+ High Capture/Compare value (TIM2
+ only)
+ 16
+ 16
+
+
+ CCR4_L
+ Low Capture/Compare value
+ 0
+ 16
+
+
+
+
+ DCR
+ DCR
+ DMA control register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DBL
+ DMA burst length
+ 8
+ 5
+
+
+ DBA
+ DMA base address
+ 0
+ 5
+
+
+
+
+ DMAR
+ DMAR
+ DMA address for full transfer
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMAB
+ DMA register for burst
+ accesses
+ 0
+ 16
+
+
+
+
+ OR
+ OR
+ TIM2 option register
+ 0x50
+ 0x20
+ read-write
+ 0x0000
+
+
+ ETR_RMP
+ Timer2 ETR remap
+ 0
+ 3
+
+
+ TI4_RMP
+ Internal trigger
+ 3
+ 2
+
+
+
+
+
+
+ TIM3
+ 0x40000400
+
+ TIM2
+ TIM2 global interrupt
+ 15
+
+
+
+ TIM6
+ Basic-timers
+ TIM
+ 0x40001000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM3
+ TIM3 global interrupt
+ 16
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ OPM
+ One-pulse mode
+ 3
+ 1
+
+
+ URS
+ Update request source
+ 2
+ 1
+
+
+ UDIS
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ MMS
+ Master mode selection
+ 4
+ 3
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ UDE
+ Update DMA request enable
+ 8
+ 1
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ UIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ UG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ Low counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ARR
+ Low Auto-reload value
+ 0
+ 16
+
+
+
+
+
+
+ TIM7
+ 0x40001400
+
+ TIM6_DAC
+ TIM6 global interrupt and DAC
+ 17
+
+
+
+ TIM21
+ General-purpose-timers
+ TIM
+ 0x40010800
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM7
+ TIM7 global interrupt and DAC
+ 18
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+ UDIS
+ Update disable
+ 1
+ 1
+
+
+ URS
+ Update request source
+ 2
+ 1
+
+
+ OPM
+ One-pulse mode
+ 3
+ 1
+
+
+ DIR
+ Direction
+ 4
+ 1
+
+
+ CMS
+ Center-aligned mode
+ selection
+ 5
+ 2
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ CKD
+ Clock division
+ 8
+ 2
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ MMS
+ Master mode selection
+ 4
+ 3
+
+
+
+
+ SMCR
+ SMCR
+ slave mode control register
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ SMS
+ Slave mode selection
+ 0
+ 3
+
+
+ TS
+ Trigger selection
+ 4
+ 3
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ ETF
+ External trigger filter
+ 8
+ 4
+
+
+ ETPS
+ External trigger prescaler
+ 12
+ 2
+
+
+ ECE
+ External clock enable
+ 14
+ 1
+
+
+ ETP
+ External trigger polarity
+ 15
+ 1
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ TIE
+ Trigger interrupt enable
+ 6
+ 1
+
+
+ CC2IE
+ Capture/Compare 2 interrupt
+ enable
+ 2
+ 1
+
+
+ CC1IE
+ Capture/Compare 1 interrupt
+ enable
+ 1
+ 1
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC2OF
+ Capture/compare 2 overcapture
+ flag
+ 10
+ 1
+
+
+ CC1OF
+ Capture/Compare 1 overcapture
+ flag
+ 9
+ 1
+
+
+ TIF
+ Trigger interrupt flag
+ 6
+ 1
+
+
+ CC2IF
+ Capture/Compare 2 interrupt
+ flag
+ 2
+ 1
+
+
+ CC1IF
+ Capture/compare 1 interrupt
+ flag
+ 1
+ 1
+
+
+ UIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ TG
+ Trigger generation
+ 6
+ 1
+
+
+ CC2G
+ Capture/compare 2
+ generation
+ 2
+ 1
+
+
+ CC1G
+ Capture/compare 1
+ generation
+ 1
+ 1
+
+
+ UG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CCMR1_Output
+ CCMR1_Output
+ capture/compare mode register (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OC2M
+ Output Compare 2 mode
+ 12
+ 3
+
+
+ OC2PE
+ Output Compare 2 preload
+ enable
+ 11
+ 1
+
+
+ OC2FE
+ Output Compare 2 fast
+ enable
+ 10
+ 1
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ OC1M
+ Output Compare 1 mode
+ 4
+ 3
+
+
+ OC1PE
+ Output Compare 1 preload
+ enable
+ 3
+ 1
+
+
+ OC1FE
+ Output Compare 1 fast
+ enable
+ 2
+ 1
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR1_Input
+ CCMR1_Input
+ capture/compare mode register 1 (input
+ mode)
+ CCMR1_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC2F
+ Input capture 2 filter
+ 12
+ 4
+
+
+ IC2PSC
+ Input capture 2 prescaler
+ 10
+ 2
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ IC1F
+ Input capture 1 filter
+ 4
+ 4
+
+
+ IC1PSC
+ Input capture 1 prescaler
+ 2
+ 2
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCER
+ CCER
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC2NP
+ Capture/Compare 2 output
+ Polarity
+ 7
+ 1
+
+
+ CC2P
+ Capture/Compare 2 output
+ Polarity
+ 5
+ 1
+
+
+ CC2E
+ Capture/Compare 2 output
+ enable
+ 4
+ 1
+
+
+ CC1NP
+ Capture/Compare 1 output
+ Polarity
+ 3
+ 1
+
+
+ CC1P
+ Capture/Compare 1 output
+ Polarity
+ 1
+ 1
+
+
+ CC1E
+ Capture/Compare 1 output
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ARR
+ Auto-reload value
+ 0
+ 16
+
+
+
+
+ CCR1
+ CCR1
+ capture/compare register 1
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR1
+ Capture/Compare 1 value
+ 0
+ 16
+
+
+
+
+ CCR2
+ CCR2
+ capture/compare register 2
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR2
+ Capture/Compare 2 value
+ 0
+ 16
+
+
+
+
+ OR
+ OR
+ TIM21 option register
+ 0x50
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ETR_RMP
+ Timer21 ETR remap
+ 0
+ 2
+
+
+ TI1_RMP
+ Timer21 TI1
+ 2
+ 3
+
+
+ TI2_RMP
+ Timer21 TI2
+ 5
+ 1
+
+
+
+
+
+
+ TIM22
+ General-purpose-timers
+ TIM
+ 0x40011400
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM21
+ TIMER21 global interrupt
+ 20
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+ UDIS
+ Update disable
+ 1
+ 1
+
+
+ URS
+ Update request source
+ 2
+ 1
+
+
+ OPM
+ One-pulse mode
+ 3
+ 1
+
+
+ DIR
+ Direction
+ 4
+ 1
+
+
+ CMS
+ Center-aligned mode
+ selection
+ 5
+ 2
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ CKD
+ Clock division
+ 8
+ 2
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ MMS
+ Master mode selection
+ 4
+ 3
+
+
+
+
+ SMCR
+ SMCR
+ slave mode control register
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ SMS
+ Slave mode selection
+ 0
+ 3
+
+
+ TS
+ Trigger selection
+ 4
+ 3
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ ETF
+ External trigger filter
+ 8
+ 4
+
+
+ ETPS
+ External trigger prescaler
+ 12
+ 2
+
+
+ ECE
+ External clock enable
+ 14
+ 1
+
+
+ ETP
+ External trigger polarity
+ 15
+ 1
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ TIE
+ Trigger interrupt enable
+ 6
+ 1
+
+
+ CC2IE
+ Capture/Compare 2 interrupt
+ enable
+ 2
+ 1
+
+
+ CC1IE
+ Capture/Compare 1 interrupt
+ enable
+ 1
+ 1
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC2OF
+ Capture/compare 2 overcapture
+ flag
+ 10
+ 1
+
+
+ CC1OF
+ Capture/Compare 1 overcapture
+ flag
+ 9
+ 1
+
+
+ TIF
+ Trigger interrupt flag
+ 6
+ 1
+
+
+ CC2IF
+ Capture/Compare 2 interrupt
+ flag
+ 2
+ 1
+
+
+ CC1IF
+ Capture/compare 1 interrupt
+ flag
+ 1
+ 1
+
+
+ UIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ TG
+ Trigger generation
+ 6
+ 1
+
+
+ CC2G
+ Capture/compare 2
+ generation
+ 2
+ 1
+
+
+ CC1G
+ Capture/compare 1
+ generation
+ 1
+ 1
+
+
+ UG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CCMR1_Output
+ CCMR1_Output
+ capture/compare mode register (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OC2M
+ Output Compare 2 mode
+ 12
+ 3
+
+
+ OC2PE
+ Output Compare 2 preload
+ enable
+ 11
+ 1
+
+
+ OC2FE
+ Output Compare 2 fast
+ enable
+ 10
+ 1
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ OC1M
+ Output Compare 1 mode
+ 4
+ 3
+
+
+ OC1PE
+ Output Compare 1 preload
+ enable
+ 3
+ 1
+
+
+ OC1FE
+ Output Compare 1 fast
+ enable
+ 2
+ 1
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR1_Input
+ CCMR1_Input
+ capture/compare mode register 1 (input
+ mode)
+ CCMR1_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC2F
+ Input capture 2 filter
+ 12
+ 4
+
+
+ IC2PSC
+ Input capture 2 prescaler
+ 10
+ 2
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ IC1F
+ Input capture 1 filter
+ 4
+ 4
+
+
+ IC1PSC
+ Input capture 1 prescaler
+ 2
+ 2
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCER
+ CCER
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC2NP
+ Capture/Compare 2 output
+ Polarity
+ 7
+ 1
+
+
+ CC2P
+ Capture/Compare 2 output
+ Polarity
+ 5
+ 1
+
+
+ CC2E
+ Capture/Compare 2 output
+ enable
+ 4
+ 1
+
+
+ CC1NP
+ Capture/Compare 1 output
+ Polarity
+ 3
+ 1
+
+
+ CC1P
+ Capture/Compare 1 output
+ Polarity
+ 1
+ 1
+
+
+ CC1E
+ Capture/Compare 1 output
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ARR
+ Auto-reload value
+ 0
+ 16
+
+
+
+
+ CCR1
+ CCR1
+ capture/compare register 1
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR1
+ Capture/Compare 1 value
+ 0
+ 16
+
+
+
+
+ CCR2
+ CCR2
+ capture/compare register 2
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR2
+ Capture/Compare 2 value
+ 0
+ 16
+
+
+
+
+ OR
+ OR
+ TIM22 option register
+ 0x50
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ETR_RMP
+ Timer22 ETR remap
+ 0
+ 2
+
+
+ TI1_RMP
+ Timer22 TI1
+ 2
+ 2
+
+
+
+
+
+
+ LPUSART1
+ Universal synchronous asynchronous receiver
+ transmitter
+ USART
+ 0x40004800
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM22
+ TIMER22 global interrupt
+ 22
+
+
+
+ CR1
+ CR1
+ Control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ M1
+ Word length
+ 28
+ 1
+
+
+ DEAT4
+ Driver Enable assertion
+ time
+ 25
+ 1
+
+
+ DEAT3
+ DEAT3
+ 24
+ 1
+
+
+ DEAT2
+ DEAT2
+ 23
+ 1
+
+
+ DEAT1
+ DEAT1
+ 22
+ 1
+
+
+ DEAT0
+ DEAT0
+ 21
+ 1
+
+
+ DEDT4
+ Driver Enable de-assertion
+ time
+ 20
+ 1
+
+
+ DEDT3
+ DEDT3
+ 19
+ 1
+
+
+ DEDT2
+ DEDT2
+ 18
+ 1
+
+
+ DEDT1
+ DEDT1
+ 17
+ 1
+
+
+ DEDT0
+ DEDT0
+ 16
+ 1
+
+
+ CMIE
+ Character match interrupt
+ enable
+ 14
+ 1
+
+
+ MME
+ Mute mode enable
+ 13
+ 1
+
+
+ M0
+ Word length
+ 12
+ 1
+
+
+ WAKE
+ Receiver wakeup method
+ 11
+ 1
+
+
+ PCE
+ Parity control enable
+ 10
+ 1
+
+
+ PS
+ Parity selection
+ 9
+ 1
+
+
+ PEIE
+ PE interrupt enable
+ 8
+ 1
+
+
+ TXEIE
+ interrupt enable
+ 7
+ 1
+
+
+ TCIE
+ Transmission complete interrupt
+ enable
+ 6
+ 1
+
+
+ RXNEIE
+ RXNE interrupt enable
+ 5
+ 1
+
+
+ IDLEIE
+ IDLE interrupt enable
+ 4
+ 1
+
+
+ TE
+ Transmitter enable
+ 3
+ 1
+
+
+ RE
+ Receiver enable
+ 2
+ 1
+
+
+ UESM
+ USART enable in Stop mode
+ 1
+ 1
+
+
+ UE
+ USART enable
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ Control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ ADD4_7
+ Address of the USART node
+ 28
+ 4
+
+
+ ADD0_3
+ Address of the USART node
+ 24
+ 4
+
+
+ MSBFIRST
+ Most significant bit first
+ 19
+ 1
+
+
+ TAINV
+ Binary data inversion
+ 18
+ 1
+
+
+ TXINV
+ TX pin active level
+ inversion
+ 17
+ 1
+
+
+ RXINV
+ RX pin active level
+ inversion
+ 16
+ 1
+
+
+ SWAP
+ Swap TX/RX pins
+ 15
+ 1
+
+
+ STOP
+ STOP bits
+ 12
+ 2
+
+
+ CLKEN
+ Clock enable
+ 11
+ 1
+
+
+ ADDM7
+ 7-bit Address Detection/4-bit Address
+ Detection
+ 4
+ 1
+
+
+
+
+ CR3
+ CR3
+ Control register 3
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ WUFIE
+ Wakeup from Stop mode interrupt
+ enable
+ 22
+ 1
+
+
+ WUS
+ Wakeup from Stop mode interrupt flag
+ selection
+ 20
+ 2
+
+
+ DEP
+ Driver enable polarity
+ selection
+ 15
+ 1
+
+
+ DEM
+ Driver enable mode
+ 14
+ 1
+
+
+ DDRE
+ DMA Disable on Reception
+ Error
+ 13
+ 1
+
+
+ OVRDIS
+ Overrun Disable
+ 12
+ 1
+
+
+ CTSIE
+ CTS interrupt enable
+ 10
+ 1
+
+
+ CTSE
+ CTS enable
+ 9
+ 1
+
+
+ RTSE
+ RTS enable
+ 8
+ 1
+
+
+ DMAT
+ DMA enable transmitter
+ 7
+ 1
+
+
+ DMAR
+ DMA enable receiver
+ 6
+ 1
+
+
+ HDSEL
+ Half-duplex selection
+ 3
+ 1
+
+
+ EIE
+ Error interrupt enable
+ 0
+ 1
+
+
+
+
+ BRR
+ BRR
+ Baud rate register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ BRR
+ BRR
+ 0
+ 20
+
+
+
+
+ RQR
+ RQR
+ Request register
+ 0x18
+ 0x20
+ write-only
+ 0x0000
+
+
+ RXFRQ
+ Receive data flush request
+ 3
+ 1
+
+
+ MMRQ
+ Mute mode request
+ 2
+ 1
+
+
+ SBKRQ
+ Send break request
+ 1
+ 1
+
+
+
+
+ ISR
+ ISR
+ Interrupt & status
+ register
+ 0x1C
+ 0x20
+ read-only
+ 0x00C0
+
+
+ REACK
+ REACK
+ 22
+ 1
+
+
+ TEACK
+ TEACK
+ 21
+ 1
+
+
+ WUF
+ WUF
+ 20
+ 1
+
+
+ RWU
+ RWU
+ 19
+ 1
+
+
+ SBKF
+ SBKF
+ 18
+ 1
+
+
+ CMF
+ CMF
+ 17
+ 1
+
+
+ BUSY
+ BUSY
+ 16
+ 1
+
+
+ CTS
+ CTS
+ 10
+ 1
+
+
+ CTSIF
+ CTSIF
+ 9
+ 1
+
+
+ TXE
+ TXE
+ 7
+ 1
+
+
+ TC
+ TC
+ 6
+ 1
+
+
+ RXNE
+ RXNE
+ 5
+ 1
+
+
+ IDLE
+ IDLE
+ 4
+ 1
+
+
+ ORE
+ ORE
+ 3
+ 1
+
+
+ NF
+ NF
+ 2
+ 1
+
+
+ FE
+ FE
+ 1
+ 1
+
+
+ PE
+ PE
+ 0
+ 1
+
+
+
+
+ ICR
+ ICR
+ Interrupt flag clear register
+ 0x20
+ 0x20
+ write-only
+ 0x0000
+
+
+ WUCF
+ Wakeup from Stop mode clear
+ flag
+ 20
+ 1
+
+
+ CMCF
+ Character match clear flag
+ 17
+ 1
+
+
+ CTSCF
+ CTS clear flag
+ 9
+ 1
+
+
+ TCCF
+ Transmission complete clear
+ flag
+ 6
+ 1
+
+
+ IDLECF
+ Idle line detected clear
+ flag
+ 4
+ 1
+
+
+ ORECF
+ Overrun error clear flag
+ 3
+ 1
+
+
+ NCF
+ Noise detected clear flag
+ 2
+ 1
+
+
+ FECF
+ Framing error clear flag
+ 1
+ 1
+
+
+ PECF
+ Parity error clear flag
+ 0
+ 1
+
+
+
+
+ RDR
+ RDR
+ Receive data register
+ 0x24
+ 0x20
+ read-only
+ 0x0000
+
+
+ RDR
+ Receive data value
+ 0
+ 9
+
+
+
+
+ TDR
+ TDR
+ Transmit data register
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ TDR
+ Transmit data value
+ 0
+ 9
+
+
+
+
+
+
+ NVIC
+ Nested Vectored Interrupt
+ Controller
+ NVIC
+ 0xE000E100
+
+ 0x0
+ 0x33D
+ registers
+
+
+
+ ISER
+ ISER
+ Interrupt Set Enable Register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ICER
+ ICER
+ Interrupt Clear Enable
+ Register
+ 0x80
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ISPR
+ ISPR
+ Interrupt Set-Pending Register
+ 0x100
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ICPR
+ ICPR
+ Interrupt Clear-Pending
+ Register
+ 0x180
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ IPR0
+ IPR0
+ Interrupt Priority Register 0
+ 0x300
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_0
+ priority for interrupt 0
+ 0
+ 8
+
+
+ PRI_1
+ priority for interrupt 1
+ 8
+ 8
+
+
+ PRI_2
+ priority for interrupt 2
+ 16
+ 8
+
+
+ PRI_3
+ priority for interrupt 3
+ 24
+ 8
+
+
+
+
+ IPR1
+ IPR1
+ Interrupt Priority Register 1
+ 0x304
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_4
+ priority for interrupt n
+ 0
+ 8
+
+
+ PRI_5
+ priority for interrupt n
+ 8
+ 8
+
+
+ PRI_6
+ priority for interrupt n
+ 16
+ 8
+
+
+ PRI_7
+ priority for interrupt n
+ 24
+ 8
+
+
+
+
+ IPR2
+ IPR2
+ Interrupt Priority Register 2
+ 0x308
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_8
+ priority for interrupt n
+ 0
+ 8
+
+
+ PRI_9
+ priority for interrupt n
+ 8
+ 8
+
+
+ PRI_10
+ priority for interrupt n
+ 16
+ 8
+
+
+ PRI_11
+ priority for interrupt n
+ 24
+ 8
+
+
+
+
+ IPR3
+ IPR3
+ Interrupt Priority Register 3
+ 0x30C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_12
+ priority for interrupt n
+ 0
+ 8
+
+
+ PRI_13
+ priority for interrupt n
+ 8
+ 8
+
+
+ PRI_14
+ priority for interrupt n
+ 16
+ 8
+
+
+ PRI_15
+ priority for interrupt n
+ 24
+ 8
+
+
+
+
+ IPR4
+ IPR4
+ Interrupt Priority Register 4
+ 0x310
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_16
+ priority for interrupt n
+ 0
+ 8
+
+
+ PRI_17
+ priority for interrupt n
+ 8
+ 8
+
+
+ PRI_18
+ priority for interrupt n
+ 16
+ 8
+
+
+ PRI_19
+ priority for interrupt n
+ 24
+ 8
+
+
+
+
+ IPR5
+ IPR5
+ Interrupt Priority Register 5
+ 0x314
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_20
+ priority for interrupt n
+ 0
+ 8
+
+
+ PRI_21
+ priority for interrupt n
+ 8
+ 8
+
+
+ PRI_22
+ priority for interrupt n
+ 16
+ 8
+
+
+ PRI_23
+ priority for interrupt n
+ 24
+ 8
+
+
+
+
+ IPR6
+ IPR6
+ Interrupt Priority Register 6
+ 0x318
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_24
+ priority for interrupt n
+ 0
+ 8
+
+
+ PRI_25
+ priority for interrupt n
+ 8
+ 8
+
+
+ PRI_26
+ priority for interrupt n
+ 16
+ 8
+
+
+ PRI_27
+ priority for interrupt n
+ 24
+ 8
+
+
+
+
+ IPR7
+ IPR7
+ Interrupt Priority Register 7
+ 0x31C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_28
+ priority for interrupt n
+ 0
+ 8
+
+
+ PRI_29
+ priority for interrupt n
+ 8
+ 8
+
+
+ PRI_30
+ priority for interrupt n
+ 16
+ 8
+
+
+ PRI_31
+ priority for interrupt n
+ 24
+ 8
+
+
+
+
+
+
+ USB_SRAM
+ Universal serial bus full-speed device
+ interface
+ USB
+ 0x40006000
+
+ 0x0
+ 0x800
+ registers
+
+
+
+ EP0R
+ EP0R
+ endpoint 0 register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+
+
+
+
+ EP1R
+ EP1R
+ endpoint 1 register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+
+
+
+
+ EP2R
+ EP2R
+ endpoint 2 register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+
+
+
+
+ EP3R
+ EP3R
+ endpoint 3 register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+
+
+
+
+ EP4R
+ EP4R
+ endpoint 4 register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+
+
+
+
+ EP5R
+ EP5R
+ endpoint 5 register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+
+
+
+
+ EP6R
+ EP6R
+ endpoint 6 register
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+
+
+
+
+ EP7R
+ EP7R
+ endpoint 7 register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+
+
+
+
+ CNTR
+ CNTR
+ control register
+ 0x40
+ 0x20
+ read-write
+ 0x00000003
+
+
+ FRES
+ Force USB Reset
+ 0
+ 1
+
+
+ PDWN
+ Power down
+ 1
+ 1
+
+
+ LPMODE
+ Low-power mode
+ 2
+ 1
+
+
+ FSUSP
+ Force suspend
+ 3
+ 1
+
+
+ RESUME
+ Resume request
+ 4
+ 1
+
+
+ L1RESUME
+ LPM L1 Resume request
+ 5
+ 1
+
+
+ L1REQM
+ LPM L1 state request interrupt
+ mask
+ 7
+ 1
+
+
+ ESOFM
+ Expected start of frame interrupt
+ mask
+ 8
+ 1
+
+
+ SOFM
+ Start of frame interrupt
+ mask
+ 9
+ 1
+
+
+ RESETM
+ USB reset interrupt mask
+ 10
+ 1
+
+
+ SUSPM
+ Suspend mode interrupt
+ mask
+ 11
+ 1
+
+
+ WKUPM
+ Wakeup interrupt mask
+ 12
+ 1
+
+
+ ERRM
+ Error interrupt mask
+ 13
+ 1
+
+
+ PMAOVRM
+ Packet memory area over / underrun
+ interrupt mask
+ 14
+ 1
+
+
+ CTRM
+ Correct transfer interrupt
+ mask
+ 15
+ 1
+
+
+
+
+ ISTR
+ ISTR
+ interrupt status register
+ 0x44
+ 0x20
+ 0x00000000
+
+
+ EP_ID
+ Endpoint Identifier
+ 0
+ 4
+ read-only
+
+
+ DIR
+ Direction of transaction
+ 4
+ 1
+ read-only
+
+
+ L1REQ
+ LPM L1 state request
+ 7
+ 1
+ read-write
+
+
+ ESOF
+ Expected start frame
+ 8
+ 1
+ read-write
+
+
+ SOF
+ start of frame
+ 9
+ 1
+ read-write
+
+
+ RESET
+ reset request
+ 10
+ 1
+ read-write
+
+
+ SUSP
+ Suspend mode request
+ 11
+ 1
+ read-write
+
+
+ WKUP
+ Wakeup
+ 12
+ 1
+ read-write
+
+
+ ERR
+ Error
+ 13
+ 1
+ read-write
+
+
+ PMAOVR
+ Packet memory area over /
+ underrun
+ 14
+ 1
+ read-write
+
+
+ CTR
+ Correct transfer
+ 15
+ 1
+ read-only
+
+
+
+
+ FNR
+ FNR
+ frame number register
+ 0x48
+ 0x20
+ read-only
+ 0x0000
+
+
+ FN
+ Frame number
+ 0
+ 11
+
+
+ LSOF
+ Lost SOF
+ 11
+ 2
+
+
+ LCK
+ Locked
+ 13
+ 1
+
+
+ RXDM
+ Receive data - line status
+ 14
+ 1
+
+
+ RXDP
+ Receive data + line status
+ 15
+ 1
+
+
+
+
+ DADDR
+ DADDR
+ device address
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ ADD
+ Device address
+ 0
+ 7
+
+
+ EF
+ Enable function
+ 7
+ 1
+
+
+
+
+ BTABLE
+ BTABLE
+ Buffer table address
+ 0x50
+ 0x20
+ read-write
+ 0x0000
+
+
+ BTABLE
+ Buffer table
+ 3
+ 13
+
+
+
+
+ LPMCSR
+ LPMCSR
+ LPM control and status
+ register
+ 0x54
+ 0x20
+ 0x0000
+
+
+ LPMEN
+ LPM support enable
+ 0
+ 1
+ read-write
+
+
+ LPMACK
+ LPM Token acknowledge
+ enable
+ 1
+ 1
+ read-write
+
+
+ REMWAKE
+ bRemoteWake value
+ 3
+ 1
+ read-only
+
+
+ BESL
+ BESL value
+ 4
+ 4
+ read-only
+
+
+
+
+ BCDR
+ BCDR
+ Battery charging detector
+ 0x58
+ 0x20
+ 0x0000
+
+
+ BCDEN
+ Battery charging detector
+ 0
+ 1
+ read-write
+
+
+ DCDEN
+ Data contact detection
+ 1
+ 1
+ read-write
+
+
+ PDEN
+ Primary detection
+ 2
+ 1
+ read-write
+
+
+ SDEN
+ Secondary detection
+ 3
+ 1
+ read-write
+
+
+ DCDET
+ Data contact detection
+ 4
+ 1
+ read-only
+
+
+ PDET
+ Primary detection
+ 5
+ 1
+ read-only
+
+
+ SDET
+ Secondary detection
+ 6
+ 1
+ read-only
+
+
+ PS2DET
+ DM pull-up detection
+ status
+ 7
+ 1
+ read-only
+
+
+ DPPU
+ DP pull-up control
+ 15
+ 1
+ read-write
+
+
+
+
+
+
+ LCD
+ Liquid crystal display controller
+ LCD
+ 0x40002400
+
+ 0x0
+ 0x400
+ registers
+
+
+ LCD
+ LCD global interrupt
+ 30
+
+
+
+ CR
+ CR
+ control register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BIAS
+ Bias selector
+ 5
+ 2
+
+
+ DUTY
+ Duty selection
+ 2
+ 3
+
+
+ VSEL
+ Voltage source selection
+ 1
+ 1
+
+
+ LCDEN
+ LCD controller enable
+ 0
+ 1
+
+
+
+
+ FCR
+ FCR
+ frame control register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PS
+ PS 16-bit prescaler
+ 22
+ 4
+
+
+ DIV
+ DIV clock divider
+ 18
+ 4
+
+
+ BLINK
+ Blink mode selection
+ 16
+ 2
+
+
+ BLINKF
+ Blink frequency selection
+ 13
+ 3
+
+
+ CC
+ Contrast control
+ 10
+ 3
+
+
+ DEAD
+ Dead time duration
+ 7
+ 3
+
+
+ PON
+ Pulse ON duration
+ 4
+ 3
+
+
+ UDDIE
+ Update display done interrupt
+ enable
+ 3
+ 1
+
+
+ SOFIE
+ Start of frame interrupt
+ enable
+ 1
+ 1
+
+
+ HD
+ High drive enable
+ 0
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x8
+ 0x20
+ 0x00000020
+
+
+ FCRSF
+ LCD Frame Control Register
+ Synchronization flag
+ 5
+ 1
+ read-only
+
+
+ RDY
+ Ready flag
+ 4
+ 1
+ read-only
+
+
+ UDD
+ Update Display Done
+ 3
+ 1
+ read-only
+
+
+ UDR
+ Update display request
+ 2
+ 1
+ write-only
+
+
+ SOF
+ Start of frame flag
+ 1
+ 1
+ read-only
+
+
+ ENS
+ ENS
+ 0
+ 1
+ read-only
+
+
+
+
+ CLR
+ CLR
+ clear register
+ 0xC
+ 0x20
+ write-only
+ 0x00000000
+
+
+ UDDC
+ Update display done clear
+ 3
+ 1
+
+
+ SOFC
+ Start of frame flag clear
+ 1
+ 1
+
+
+
+
+ RAM_COM0
+ RAM_COM0
+ display memory
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ S30
+ S30
+ 30
+ 1
+
+
+ S29
+ S29
+ 29
+ 1
+
+
+ S28
+ S28
+ 28
+ 1
+
+
+ S27
+ S27
+ 27
+ 1
+
+
+ S26
+ S26
+ 26
+ 1
+
+
+ S25
+ S25
+ 25
+ 1
+
+
+ S24
+ S24
+ 24
+ 1
+
+
+ S23
+ S23
+ 23
+ 1
+
+
+ S22
+ S22
+ 22
+ 1
+
+
+ S21
+ S21
+ 21
+ 1
+
+
+ S20
+ S20
+ 20
+ 1
+
+
+ S19
+ S19
+ 19
+ 1
+
+
+ S18
+ S18
+ 18
+ 1
+
+
+ S17
+ S17
+ 17
+ 1
+
+
+ S16
+ S16
+ 16
+ 1
+
+
+ S15
+ S15
+ 15
+ 1
+
+
+ S14
+ S14
+ 14
+ 1
+
+
+ S13
+ S13
+ 13
+ 1
+
+
+ S12
+ S12
+ 12
+ 1
+
+
+ S11
+ S11
+ 11
+ 1
+
+
+ S10
+ S10
+ 10
+ 1
+
+
+ S09
+ S09
+ 9
+ 1
+
+
+ S08
+ S08
+ 8
+ 1
+
+
+ S07
+ S07
+ 7
+ 1
+
+
+ S06
+ S06
+ 6
+ 1
+
+
+ S05
+ S05
+ 5
+ 1
+
+
+ S04
+ S04
+ 4
+ 1
+
+
+ S03
+ S03
+ 3
+ 1
+
+
+ S02
+ S02
+ 2
+ 1
+
+
+ S01
+ S01
+ 1
+ 1
+
+
+ S00
+ S00
+ 0
+ 1
+
+
+
+
+ RAM_COM1
+ RAM_COM1
+ display memory
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ S31
+ S31
+ 31
+ 1
+
+
+ S30
+ S30
+ 30
+ 1
+
+
+ S29
+ S29
+ 29
+ 1
+
+
+ S28
+ S28
+ 28
+ 1
+
+
+ S27
+ S27
+ 27
+ 1
+
+
+ S26
+ S26
+ 26
+ 1
+
+
+ S25
+ S25
+ 25
+ 1
+
+
+ S24
+ S24
+ 24
+ 1
+
+
+ S23
+ S23
+ 23
+ 1
+
+
+ S22
+ S22
+ 22
+ 1
+
+
+ S21
+ S21
+ 21
+ 1
+
+
+ S20
+ S20
+ 20
+ 1
+
+
+ S19
+ S19
+ 19
+ 1
+
+
+ S18
+ S18
+ 18
+ 1
+
+
+ S17
+ S17
+ 17
+ 1
+
+
+ S16
+ S16
+ 16
+ 1
+
+
+ S15
+ S15
+ 15
+ 1
+
+
+ S14
+ S14
+ 14
+ 1
+
+
+ S13
+ S13
+ 13
+ 1
+
+
+ S12
+ S12
+ 12
+ 1
+
+
+ S11
+ S11
+ 11
+ 1
+
+
+ S10
+ S10
+ 10
+ 1
+
+
+ S09
+ S09
+ 9
+ 1
+
+
+ S08
+ S08
+ 8
+ 1
+
+
+ S07
+ S07
+ 7
+ 1
+
+
+ S06
+ S06
+ 6
+ 1
+
+
+ S05
+ S05
+ 5
+ 1
+
+
+ S04
+ S04
+ 4
+ 1
+
+
+ S03
+ S03
+ 3
+ 1
+
+
+ S02
+ S02
+ 2
+ 1
+
+
+ S01
+ S01
+ 1
+ 1
+
+
+ S00
+ S00
+ 0
+ 1
+
+
+
+
+ RAM_COM2
+ RAM_COM2
+ display memory
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ S31
+ S31
+ 31
+ 1
+
+
+ S30
+ S30
+ 30
+ 1
+
+
+ S29
+ S29
+ 29
+ 1
+
+
+ S28
+ S28
+ 28
+ 1
+
+
+ S27
+ S27
+ 27
+ 1
+
+
+ S26
+ S26
+ 26
+ 1
+
+
+ S25
+ S25
+ 25
+ 1
+
+
+ S24
+ S24
+ 24
+ 1
+
+
+ S23
+ S23
+ 23
+ 1
+
+
+ S22
+ S22
+ 22
+ 1
+
+
+ S21
+ S21
+ 21
+ 1
+
+
+ S20
+ S20
+ 20
+ 1
+
+
+ S19
+ S19
+ 19
+ 1
+
+
+ S18
+ S18
+ 18
+ 1
+
+
+ S17
+ S17
+ 17
+ 1
+
+
+ S16
+ S16
+ 16
+ 1
+
+
+ S15
+ S15
+ 15
+ 1
+
+
+ S14
+ S14
+ 14
+ 1
+
+
+ S13
+ S13
+ 13
+ 1
+
+
+ S12
+ S12
+ 12
+ 1
+
+
+ S11
+ S11
+ 11
+ 1
+
+
+ S10
+ S10
+ 10
+ 1
+
+
+ S09
+ S09
+ 9
+ 1
+
+
+ S08
+ S08
+ 8
+ 1
+
+
+ S07
+ S07
+ 7
+ 1
+
+
+ S06
+ S06
+ 6
+ 1
+
+
+ S05
+ S05
+ 5
+ 1
+
+
+ S04
+ S04
+ 4
+ 1
+
+
+ S03
+ S03
+ 3
+ 1
+
+
+ S02
+ S02
+ 2
+ 1
+
+
+ S01
+ S01
+ 1
+ 1
+
+
+ S00
+ S00
+ 0
+ 1
+
+
+
+
+ RAM_COM3
+ RAM_COM3
+ display memory
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ S31
+ S31
+ 31
+ 1
+
+
+ S30
+ S30
+ 30
+ 1
+
+
+ S29
+ S29
+ 29
+ 1
+
+
+ S28
+ S28
+ 28
+ 1
+
+
+ S27
+ S27
+ 27
+ 1
+
+
+ S26
+ S26
+ 26
+ 1
+
+
+ S25
+ S25
+ 25
+ 1
+
+
+ S24
+ S24
+ 24
+ 1
+
+
+ S23
+ S23
+ 23
+ 1
+
+
+ S22
+ S22
+ 22
+ 1
+
+
+ S21
+ S21
+ 21
+ 1
+
+
+ S20
+ S20
+ 20
+ 1
+
+
+ S19
+ S19
+ 19
+ 1
+
+
+ S18
+ S18
+ 18
+ 1
+
+
+ S17
+ S17
+ 17
+ 1
+
+
+ S16
+ S16
+ 16
+ 1
+
+
+ S15
+ S15
+ 15
+ 1
+
+
+ S14
+ S14
+ 14
+ 1
+
+
+ S13
+ S13
+ 13
+ 1
+
+
+ S12
+ S12
+ 12
+ 1
+
+
+ S11
+ S11
+ 11
+ 1
+
+
+ S10
+ S10
+ 10
+ 1
+
+
+ S09
+ S09
+ 9
+ 1
+
+
+ S08
+ S08
+ 8
+ 1
+
+
+ S07
+ S07
+ 7
+ 1
+
+
+ S06
+ S06
+ 6
+ 1
+
+
+ S05
+ S05
+ 5
+ 1
+
+
+ S04
+ S04
+ 4
+ 1
+
+
+ S03
+ S03
+ 3
+ 1
+
+
+ S02
+ S02
+ 2
+ 1
+
+
+ S01
+ S01
+ 1
+ 1
+
+
+ S00
+ S00
+ 0
+ 1
+
+
+
+
+ RAM_COM4
+ RAM_COM4
+ display memory
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ S31
+ S31
+ 31
+ 1
+
+
+ S30
+ S30
+ 30
+ 1
+
+
+ S29
+ S29
+ 29
+ 1
+
+
+ S28
+ S28
+ 28
+ 1
+
+
+ S27
+ S27
+ 27
+ 1
+
+
+ S26
+ S26
+ 26
+ 1
+
+
+ S25
+ S25
+ 25
+ 1
+
+
+ S24
+ S24
+ 24
+ 1
+
+
+ S23
+ S23
+ 23
+ 1
+
+
+ S22
+ S22
+ 22
+ 1
+
+
+ S21
+ S21
+ 21
+ 1
+
+
+ S20
+ S20
+ 20
+ 1
+
+
+ S19
+ S19
+ 19
+ 1
+
+
+ S18
+ S18
+ 18
+ 1
+
+
+ S17
+ S17
+ 17
+ 1
+
+
+ S16
+ S16
+ 16
+ 1
+
+
+ S15
+ S15
+ 15
+ 1
+
+
+ S14
+ S14
+ 14
+ 1
+
+
+ S13
+ S13
+ 13
+ 1
+
+
+ S12
+ S12
+ 12
+ 1
+
+
+ S11
+ S11
+ 11
+ 1
+
+
+ S10
+ S10
+ 10
+ 1
+
+
+ S09
+ S09
+ 9
+ 1
+
+
+ S08
+ S08
+ 8
+ 1
+
+
+ S07
+ S07
+ 7
+ 1
+
+
+ S06
+ S06
+ 6
+ 1
+
+
+ S05
+ S05
+ 5
+ 1
+
+
+ S04
+ S04
+ 4
+ 1
+
+
+ S03
+ S03
+ 3
+ 1
+
+
+ S02
+ S02
+ 2
+ 1
+
+
+ S01
+ S01
+ 1
+ 1
+
+
+ S00
+ S00
+ 0
+ 1
+
+
+
+
+ RAM_COM5
+ RAM_COM5
+ display memory
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ S31
+ S31
+ 31
+ 1
+
+
+ S30
+ S30
+ 30
+ 1
+
+
+ S29
+ S29
+ 29
+ 1
+
+
+ S28
+ S28
+ 28
+ 1
+
+
+ S27
+ S27
+ 27
+ 1
+
+
+ S26
+ S26
+ 26
+ 1
+
+
+ S25
+ S25
+ 25
+ 1
+
+
+ S24
+ S24
+ 24
+ 1
+
+
+ S23
+ S23
+ 23
+ 1
+
+
+ S22
+ S22
+ 22
+ 1
+
+
+ S21
+ S21
+ 21
+ 1
+
+
+ S20
+ S20
+ 20
+ 1
+
+
+ S19
+ S19
+ 19
+ 1
+
+
+ S18
+ S18
+ 18
+ 1
+
+
+ S17
+ S17
+ 17
+ 1
+
+
+ S16
+ S16
+ 16
+ 1
+
+
+ S15
+ S15
+ 15
+ 1
+
+
+ S14
+ S14
+ 14
+ 1
+
+
+ S13
+ S13
+ 13
+ 1
+
+
+ S12
+ S12
+ 12
+ 1
+
+
+ S11
+ S11
+ 11
+ 1
+
+
+ S10
+ S10
+ 10
+ 1
+
+
+ S09
+ S09
+ 9
+ 1
+
+
+ S08
+ S08
+ 8
+ 1
+
+
+ S07
+ S07
+ 7
+ 1
+
+
+ S06
+ S06
+ 6
+ 1
+
+
+ S05
+ S05
+ 5
+ 1
+
+
+ S04
+ S04
+ 4
+ 1
+
+
+ S03
+ S03
+ 3
+ 1
+
+
+ S02
+ S02
+ 2
+ 1
+
+
+ S01
+ S01
+ 1
+ 1
+
+
+ S00
+ S00
+ 0
+ 1
+
+
+
+
+ RAM_COM6
+ RAM_COM6
+ display memory
+ 0x44
+ 0x20
+ read-write
+ 0x00000000
+
+
+ S31
+ S31
+ 31
+ 1
+
+
+ S30
+ S30
+ 30
+ 1
+
+
+ S29
+ S29
+ 29
+ 1
+
+
+ S28
+ S28
+ 28
+ 1
+
+
+ S27
+ S27
+ 27
+ 1
+
+
+ S26
+ S26
+ 26
+ 1
+
+
+ S25
+ S25
+ 25
+ 1
+
+
+ S24
+ S24
+ 24
+ 1
+
+
+ S23
+ S23
+ 23
+ 1
+
+
+ S22
+ S22
+ 22
+ 1
+
+
+ S21
+ S21
+ 21
+ 1
+
+
+ S20
+ S20
+ 20
+ 1
+
+
+ S19
+ S19
+ 19
+ 1
+
+
+ S18
+ S18
+ 18
+ 1
+
+
+ S17
+ S17
+ 17
+ 1
+
+
+ S16
+ S16
+ 16
+ 1
+
+
+ S15
+ S15
+ 15
+ 1
+
+
+ S14
+ S14
+ 14
+ 1
+
+
+ S13
+ S13
+ 13
+ 1
+
+
+ S12
+ S12
+ 12
+ 1
+
+
+ S11
+ S11
+ 11
+ 1
+
+
+ S10
+ S10
+ 10
+ 1
+
+
+ S09
+ S09
+ 9
+ 1
+
+
+ S08
+ S08
+ 8
+ 1
+
+
+ S07
+ S07
+ 7
+ 1
+
+
+ S06
+ S06
+ 6
+ 1
+
+
+ S05
+ S05
+ 5
+ 1
+
+
+ S04
+ S04
+ 4
+ 1
+
+
+ S03
+ S03
+ 3
+ 1
+
+
+ S02
+ S02
+ 2
+ 1
+
+
+ S01
+ S01
+ 1
+ 1
+
+
+ S00
+ S00
+ 0
+ 1
+
+
+
+
+ RAM_COM7
+ RAM_COM7
+ display memory
+ 0x4C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ S31
+ S31
+ 31
+ 1
+
+
+ S30
+ S30
+ 30
+ 1
+
+
+ S29
+ S29
+ 29
+ 1
+
+
+ S28
+ S28
+ 28
+ 1
+
+
+ S27
+ S27
+ 27
+ 1
+
+
+ S26
+ S26
+ 26
+ 1
+
+
+ S25
+ S25
+ 25
+ 1
+
+
+ S24
+ S24
+ 24
+ 1
+
+
+ S23
+ S23
+ 23
+ 1
+
+
+ S22
+ S22
+ 22
+ 1
+
+
+ S21
+ S21
+ 21
+ 1
+
+
+ S20
+ S20
+ 20
+ 1
+
+
+ S19
+ S19
+ 19
+ 1
+
+
+ S18
+ S18
+ 18
+ 1
+
+
+ S17
+ S17
+ 17
+ 1
+
+
+ S16
+ S16
+ 16
+ 1
+
+
+ S15
+ S15
+ 15
+ 1
+
+
+ S14
+ S14
+ 14
+ 1
+
+
+ S13
+ S13
+ 13
+ 1
+
+
+ S12
+ S12
+ 12
+ 1
+
+
+ S11
+ S11
+ 11
+ 1
+
+
+ S10
+ S10
+ 10
+ 1
+
+
+ S09
+ S09
+ 9
+ 1
+
+
+ S08
+ S08
+ 8
+ 1
+
+
+ S07
+ S07
+ 7
+ 1
+
+
+ S06
+ S06
+ 6
+ 1
+
+
+ S05
+ S05
+ 5
+ 1
+
+
+ S04
+ S04
+ 4
+ 1
+
+
+ S03
+ S03
+ 3
+ 1
+
+
+ S02
+ S02
+ 2
+ 1
+
+
+ S01
+ S01
+ 1
+ 1
+
+
+ S00
+ S00
+ 0
+ 1
+
+
+
+
+
+
+ MPU
+ Memory protection unit
+ MPU
+ 0xE000ED90
+
+ 0x0
+ 0x15
+ registers
+
+
+
+ MPU_TYPER
+ MPU_TYPER
+ MPU type register
+ 0x0
+ 0x20
+ read-only
+ 0X00000800
+
+
+ SEPARATE
+ Separate flag
+ 0
+ 1
+
+
+ DREGION
+ Number of MPU data regions
+ 8
+ 8
+
+
+ IREGION
+ Number of MPU instruction
+ regions
+ 16
+ 8
+
+
+
+
+ MPU_CTRL
+ MPU_CTRL
+ MPU control register
+ 0x4
+ 0x20
+ read-only
+ 0X00000000
+
+
+ ENABLE
+ Enables the MPU
+ 0
+ 1
+
+
+ HFNMIENA
+ Enables the operation of MPU during hard
+ fault
+ 1
+ 1
+
+
+ PRIVDEFENA
+ Enable priviliged software access to
+ default memory map
+ 2
+ 1
+
+
+
+
+ MPU_RNR
+ MPU_RNR
+ MPU region number register
+ 0x8
+ 0x20
+ read-write
+ 0X00000000
+
+
+ REGION
+ MPU region
+ 0
+ 8
+
+
+
+
+ MPU_RBAR
+ MPU_RBAR
+ MPU region base address
+ register
+ 0xC
+ 0x20
+ read-write
+ 0X00000000
+
+
+ REGION
+ MPU region field
+ 0
+ 4
+
+
+ VALID
+ MPU region number valid
+ 4
+ 1
+
+
+ ADDR
+ Region base address field
+ 5
+ 27
+
+
+
+
+ MPU_RASR
+ MPU_RASR
+ MPU region attribute and size
+ register
+ 0x10
+ 0x20
+ read-write
+ 0X00000000
+
+
+ ENABLE
+ Region enable bit.
+ 0
+ 1
+
+
+ SIZE
+ Size of the MPU protection
+ region
+ 1
+ 5
+
+
+ SRD
+ Subregion disable bits
+ 8
+ 8
+
+
+ B
+ memory attribute
+ 16
+ 1
+
+
+ C
+ memory attribute
+ 17
+ 1
+
+
+ S
+ Shareable memory attribute
+ 18
+ 1
+
+
+ TEX
+ memory attribute
+ 19
+ 3
+
+
+ AP
+ Access permission
+ 24
+ 3
+
+
+ XN
+ Instruction access disable
+ bit
+ 28
+ 1
+
+
+
+
+
+
+ STK
+ SysTick timer
+ STK
+ 0xE000E010
+
+ 0x0
+ 0x11
+ registers
+
+
+
+ CSR
+ CSR
+ SysTick control and status
+ register
+ 0x0
+ 0x20
+ read-write
+ 0X00000000
+
+
+ ENABLE
+ Counter enable
+ 0
+ 1
+
+
+ TICKINT
+ SysTick exception request
+ enable
+ 1
+ 1
+
+
+ CLKSOURCE
+ Clock source selection
+ 2
+ 1
+
+
+ COUNTFLAG
+ COUNTFLAG
+ 16
+ 1
+
+
+
+
+ RVR
+ RVR
+ SysTick reload value register
+ 0x4
+ 0x20
+ read-write
+ 0X00000000
+
+
+ RELOAD
+ RELOAD value
+ 0
+ 24
+
+
+
+
+ CVR
+ CVR
+ SysTick current value register
+ 0x8
+ 0x20
+ read-write
+ 0X00000000
+
+
+ CURRENT
+ Current counter value
+ 0
+ 24
+
+
+
+
+ CALIB
+ CALIB
+ SysTick calibration value
+ register
+ 0xC
+ 0x20
+ read-write
+ 0X00000000
+
+
+ TENMS
+ Calibration value
+ 0
+ 24
+
+
+ SKEW
+ SKEW flag: Indicates whether the TENMS
+ value is exact
+ 30
+ 1
+
+
+ NOREF
+ NOREF flag. Reads as zero
+ 31
+ 1
+
+
+
+
+
+
+ SCB
+ System control block
+ SCB
+ 0xE000ED00
+
+ 0x0
+ 0x41
+ registers
+
+
+
+ CPUID
+ CPUID
+ CPUID base register
+ 0x0
+ 0x20
+ read-only
+ 0x410FC241
+
+
+ Revision
+ Revision number
+ 0
+ 4
+
+
+ PartNo
+ Part number of the
+ processor
+ 4
+ 12
+
+
+ Architecture
+ Reads as 0xF
+ 16
+ 4
+
+
+ Variant
+ Variant number
+ 20
+ 4
+
+
+ Implementer
+ Implementer code
+ 24
+ 8
+
+
+
+
+ ICSR
+ ICSR
+ Interrupt control and state
+ register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ VECTACTIVE
+ Active vector
+ 0
+ 9
+
+
+ RETTOBASE
+ Return to base level
+ 11
+ 1
+
+
+ VECTPENDING
+ Pending vector
+ 12
+ 7
+
+
+ ISRPENDING
+ Interrupt pending flag
+ 22
+ 1
+
+
+ PENDSTCLR
+ SysTick exception clear-pending
+ bit
+ 25
+ 1
+
+
+ PENDSTSET
+ SysTick exception set-pending
+ bit
+ 26
+ 1
+
+
+ PENDSVCLR
+ PendSV clear-pending bit
+ 27
+ 1
+
+
+ PENDSVSET
+ PendSV set-pending bit
+ 28
+ 1
+
+
+ NMIPENDSET
+ NMI set-pending bit.
+ 31
+ 1
+
+
+
+
+ VTOR
+ VTOR
+ Vector table offset register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TBLOFF
+ Vector table base offset
+ field
+ 7
+ 25
+
+
+
+
+ AIRCR
+ AIRCR
+ Application interrupt and reset control
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ VECTCLRACTIVE
+ VECTCLRACTIVE
+ 1
+ 1
+
+
+ SYSRESETREQ
+ SYSRESETREQ
+ 2
+ 1
+
+
+ ENDIANESS
+ ENDIANESS
+ 15
+ 1
+
+
+ VECTKEYSTAT
+ Register key
+ 16
+ 16
+
+
+
+
+ SCR
+ SCR
+ System control register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SLEEPONEXIT
+ SLEEPONEXIT
+ 1
+ 1
+
+
+ SLEEPDEEP
+ SLEEPDEEP
+ 2
+ 1
+
+
+ SEVEONPEND
+ Send Event on Pending bit
+ 4
+ 1
+
+
+
+
+ CCR
+ CCR
+ Configuration and control
+ register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NONBASETHRDENA
+ Configures how the processor enters
+ Thread mode
+ 0
+ 1
+
+
+ USERSETMPEND
+ USERSETMPEND
+ 1
+ 1
+
+
+ UNALIGN__TRP
+ UNALIGN_ TRP
+ 3
+ 1
+
+
+ DIV_0_TRP
+ DIV_0_TRP
+ 4
+ 1
+
+
+ BFHFNMIGN
+ BFHFNMIGN
+ 8
+ 1
+
+
+ STKALIGN
+ STKALIGN
+ 9
+ 1
+
+
+
+
+ SHPR2
+ SHPR2
+ System handler priority
+ registers
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_11
+ Priority of system handler
+ 11
+ 24
+ 8
+
+
+
+
+ SHPR3
+ SHPR3
+ System handler priority
+ registers
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_14
+ Priority of system handler
+ 14
+ 16
+ 8
+
+
+ PRI_15
+ Priority of system handler
+ 15
+ 24
+ 8
+
+
+
+
+
+
+
diff --git a/.gitmodules b/board-support/stmicro-stm32/src/hals/STM32F103.zig
similarity index 100%
rename from .gitmodules
rename to board-support/stmicro-stm32/src/hals/STM32F103.zig
diff --git a/board-support/stmicro-stm32/src/hals/STM32F103/gpio.zig b/board-support/stmicro-stm32/src/hals/STM32F103/gpio.zig
new file mode 100644
index 0000000..811a80c
--- /dev/null
+++ b/board-support/stmicro-stm32/src/hals/STM32F103/gpio.zig
@@ -0,0 +1,160 @@
+const std = @import("std");
+const assert = std.debug.assert;
+
+const microzig = @import("microzig");
+pub const peripherals = microzig.chip.peripherals;
+
+const GPIOA = peripherals.GPIOA;
+const GPIOB = peripherals.GPIOB;
+const GPIOC = peripherals.GPIOC;
+const GPIOD = peripherals.GPIOD;
+const GPIOE = peripherals.GPIOE;
+const GPIOF = peripherals.GPIOF;
+const GPIOG = peripherals.GPIOG;
+
+const GPIO = @TypeOf(GPIOA);
+
+const log = std.log.scoped(.gpio);
+
+pub const Function = enum {};
+
+pub const Mode = union(enum) {
+ input: InputMode,
+ output: OutputMode,
+};
+
+pub const InputMode = enum(u2) {
+ analog,
+ floating,
+ pull,
+ reserved,
+};
+
+pub const OutputMode = enum(u2) {
+ general_purpose_push_pull,
+ general_purpose_open_drain,
+ alternate_function_push_pull,
+ alternate_function_open_drain,
+};
+
+pub const Speed = enum(u2) {
+ reserved,
+ max_10MHz,
+ max_2MHz,
+ max_50MHz,
+};
+
+pub const IrqLevel = enum(u2) {
+ low,
+ high,
+ fall,
+ rise,
+};
+
+pub const IrqCallback = fn (gpio: u32, events: u32) callconv(.C) void;
+
+pub const Enabled = enum {
+ disabled,
+ enabled,
+};
+
+pub const Pull = enum {
+ up,
+ down,
+};
+
+// NOTE: With this current setup, every time we want to do anythting we go through a switch
+// Do we want this?
+pub const Pin = packed struct(u8) {
+ number: u4,
+ port: u3,
+ padding: u1,
+
+ pub fn init(port: u3, number: u4) Pin {
+ return Pin{
+ .number = number,
+ .port = port,
+ .padding = 0,
+ };
+ }
+ inline fn write_pin_config(gpio: Pin, config: u32) void {
+ const port = gpio.get_port();
+ if (gpio.number <= 7) {
+ const offset = @as(u5, gpio.number) << 2;
+ port.CRL.raw &= ~(@as(u32, 0b1111) << offset);
+ port.CRL.raw |= config << offset;
+ } else {
+ const offset = (@as(u5, gpio.number) - 8) << 2;
+ port.CRH.raw &= ~(@as(u32, 0b1111) << offset);
+ port.CRH.raw |= config << offset;
+ }
+ }
+
+ fn mask(gpio: Pin) u16 {
+ return @as(u16, 1) << gpio.number;
+ }
+
+ // NOTE: Im not sure I like this
+ // We could probably calculate an offset from GPIOA?
+ pub fn get_port(gpio: Pin) GPIO {
+ return switch (gpio.port) {
+ 0 => GPIOA,
+ 1 => GPIOB,
+ 2 => GPIOC,
+ 3 => GPIOD,
+ 4 => GPIOE,
+ 5 => GPIOF,
+ 6 => GPIOG,
+ 7 => @panic("The STM32 only has ports 0..6 (A..G)"),
+ };
+ }
+
+ pub inline fn set_mode(gpio: Pin, mode: Mode) void {
+ switch (mode) {
+ .input => |in| gpio.set_input_mode(in),
+ .output => |out| gpio.set_output_mode(out, .max_2MHz),
+ }
+ }
+
+ pub inline fn set_input_mode(gpio: Pin, mode: InputMode) void {
+ const m_mode = @as(u32, @intFromEnum(mode));
+ const config: u32 = m_mode << 2;
+ gpio.write_pin_config(config);
+ }
+
+ pub inline fn set_output_mode(gpio: Pin, mode: OutputMode, speed: Speed) void {
+ const s_speed = @as(u32, @intFromEnum(speed));
+ const m_mode = @as(u32, @intFromEnum(mode));
+ const config: u32 = s_speed + (m_mode << 2);
+ gpio.write_pin_config(config);
+ }
+
+ pub inline fn set_pull(gpio: Pin, pull: Pull) void {
+ var port = gpio.get_port();
+ switch (pull) {
+ .up => port.BSRR.raw = gpio.mask(),
+ .down => port.BRR.raw = gpio.mask(),
+ }
+ }
+
+ pub inline fn read(gpio: Pin) u1 {
+ const port = gpio.get_port();
+ return if (port.IDR.raw & gpio.mask() != 0)
+ 1
+ else
+ 0;
+ }
+
+ pub inline fn put(gpio: Pin, value: u1) void {
+ var port = gpio.get_port();
+ switch (value) {
+ 0 => port.BSRR.raw = gpio.mask() << 16,
+ 1 => port.BSRR.raw = gpio.mask(),
+ }
+ }
+
+ pub inline fn toggle(gpio: Pin) void {
+ var port = gpio.get_port();
+ port.ODR.raw ^= gpio.mask();
+ }
+};
diff --git a/board-support/stmicro-stm32/src/hals/STM32F103/hal.zig b/board-support/stmicro-stm32/src/hals/STM32F103/hal.zig
new file mode 100644
index 0000000..fafa677
--- /dev/null
+++ b/board-support/stmicro-stm32/src/hals/STM32F103/hal.zig
@@ -0,0 +1,3 @@
+pub const pins = @import("pins.zig");
+
+pub fn init() void {}
diff --git a/board-support/stmicro-stm32/src/hals/STM32F103/pins.zig b/board-support/stmicro-stm32/src/hals/STM32F103/pins.zig
new file mode 100644
index 0000000..021dd6c
--- /dev/null
+++ b/board-support/stmicro-stm32/src/hals/STM32F103/pins.zig
@@ -0,0 +1,237 @@
+const std = @import("std");
+const assert = std.debug.assert;
+const comptimePrint = std.fmt.comptimePrint;
+const StructField = std.builtin.Type.StructField;
+
+const microzig = @import("microzig");
+
+const RCC = microzig.chip.peripherals.RCC;
+
+const gpio = @import("gpio.zig");
+// const pwm = @import("pwm.zig");
+// const adc = @import("adc.zig");
+// const resets = @import("resets.zig");
+
+pub const Pin = enum {
+ PIN0,
+ PIN1,
+ PIN2,
+ PIN3,
+ PIN4,
+ PIN5,
+ PIN6,
+ PIN7,
+ PIN8,
+ PIN9,
+ PIN10,
+ PIN11,
+ PIN12,
+ PIN13,
+ PIN14,
+ PIN15,
+ pub const Configuration = struct {
+ name: ?[]const u8 = null,
+ // function: Function = .SIO,
+ mode: ?gpio.Mode = null,
+ speed: ?gpio.Speed = null,
+ pull: ?gpio.Pull = null,
+ // input/output enable
+ // schmitt trigger
+ // hysteresis
+
+ pub fn get_mode(comptime config: Configuration) gpio.Mode {
+ return if (config.mode) |mode|
+ mode
+ // else if (comptime config.function.is_pwm())
+ // .out
+ // else if (comptime config.function.is_uart_tx())
+ // .out
+ // else if (comptime config.function.is_uart_rx())
+ // .in
+ // else if (comptime config.function.is_adc())
+ // .in
+ else
+ @panic("TODO");
+ }
+ };
+};
+
+pub fn GPIO(comptime port: u3, comptime num: u4, comptime mode: gpio.Mode) type {
+ return switch (mode) {
+ .input => struct {
+ const pin = gpio.Pin.init(port, num);
+
+ pub inline fn read(self: @This()) u1 {
+ _ = self;
+ return pin.read();
+ }
+ },
+ .output => struct {
+ const pin = gpio.Pin.init(port, num);
+
+ pub inline fn put(self: @This(), value: u1) void {
+ _ = self;
+ pin.put(value);
+ }
+
+ pub inline fn toggle(self: @This()) void {
+ _ = self;
+ pin.toggle();
+ }
+ },
+ };
+}
+
+pub fn Pins(comptime config: GlobalConfiguration) type {
+ comptime {
+ var fields: []const StructField = &.{};
+ for (@typeInfo(GlobalConfiguration).Struct.fields) |port_field| {
+ if (@field(config, port_field.name)) |port_config| {
+ for (@typeInfo(Port.Configuration).Struct.fields) |field| {
+ if (@field(port_config, field.name)) |pin_config| {
+ var pin_field = StructField{
+ .is_comptime = false,
+ .default_value = null,
+
+ // initialized below:
+ .name = undefined,
+ .type = undefined,
+ .alignment = undefined,
+ };
+
+ pin_field.name = pin_config.name orelse field.name;
+ pin_field.type = GPIO(@intFromEnum(@field(Port, port_field.name)), @intFromEnum(@field(Pin, field.name)), pin_config.mode orelse .{ .input = .{.floating} });
+ pin_field.alignment = @alignOf(field.type);
+
+ fields = fields ++ &[_]StructField{pin_field};
+ }
+ }
+ }
+ }
+
+ return @Type(.{
+ .Struct = .{
+ .layout = .Auto,
+ .is_tuple = false,
+ .fields = fields,
+ .decls = &.{},
+ },
+ });
+ }
+}
+
+pub const Port = enum {
+ GPIOA,
+ GPIOB,
+ GPIOC,
+ GPIOD,
+ GPIOE,
+ GPIOF,
+ GPIOG,
+ pub const Configuration = struct {
+ PIN0: ?Pin.Configuration = null,
+ PIN1: ?Pin.Configuration = null,
+ PIN2: ?Pin.Configuration = null,
+ PIN3: ?Pin.Configuration = null,
+ PIN4: ?Pin.Configuration = null,
+ PIN5: ?Pin.Configuration = null,
+ PIN6: ?Pin.Configuration = null,
+ PIN7: ?Pin.Configuration = null,
+ PIN8: ?Pin.Configuration = null,
+ PIN9: ?Pin.Configuration = null,
+ PIN10: ?Pin.Configuration = null,
+ PIN11: ?Pin.Configuration = null,
+ PIN12: ?Pin.Configuration = null,
+ PIN13: ?Pin.Configuration = null,
+ PIN14: ?Pin.Configuration = null,
+ PIN15: ?Pin.Configuration = null,
+
+ comptime {
+ const pin_field_count = @typeInfo(Pin).Enum.fields.len;
+ const config_field_count = @typeInfo(Configuration).Struct.fields.len;
+ if (pin_field_count != config_field_count)
+ @compileError(comptimePrint("{} {}", .{ pin_field_count, config_field_count }));
+ }
+ };
+};
+
+pub const GlobalConfiguration = struct {
+ GPIOA: ?Port.Configuration = null,
+ GPIOB: ?Port.Configuration = null,
+ GPIOC: ?Port.Configuration = null,
+ GPIOD: ?Port.Configuration = null,
+ GPIOE: ?Port.Configuration = null,
+ GPIOF: ?Port.Configuration = null,
+ GPIOG: ?Port.Configuration = null,
+
+ comptime {
+ const port_field_count = @typeInfo(Port).Enum.fields.len;
+ const config_field_count = @typeInfo(GlobalConfiguration).Struct.fields.len;
+ if (port_field_count != config_field_count)
+ @compileError(comptimePrint("{} {}", .{ port_field_count, config_field_count }));
+ }
+
+ pub fn apply(comptime config: GlobalConfiguration) Pins(config) {
+ inline for (@typeInfo(GlobalConfiguration).Struct.fields) |port_field| {
+ if (@field(config, port_field.name)) |port_config| {
+ comptime var input_gpios: u16 = 0;
+ comptime var output_gpios: u16 = 0;
+ comptime {
+ inline for (@typeInfo(Port.Configuration).Struct.fields) |field|
+ if (@field(port_config, field.name)) |pin_config| {
+ const gpio_num = @intFromEnum(@field(Pin, field.name));
+
+ switch (pin_config.get_mode()) {
+ .input => input_gpios |= 1 << gpio_num,
+ .output => output_gpios |= 1 << gpio_num,
+ }
+ };
+ }
+
+ // TODO: ensure only one instance of an input function exists
+ const used_gpios = comptime input_gpios | output_gpios;
+
+ if (used_gpios != 0) {
+ const offset = @intFromEnum(@field(Port, port_field.name)) + 2;
+ const bit = @as(u32, 1 << offset);
+ RCC.APB2ENR.raw |= bit;
+ // Delay after setting
+ _ = RCC.APB2ENR.raw & bit;
+ }
+
+ inline for (@typeInfo(Port.Configuration).Struct.fields) |field| {
+ if (@field(port_config, field.name)) |pin_config| {
+ var pin = gpio.Pin.init(@intFromEnum(@field(Port, port_field.name)), @intFromEnum(@field(Pin, field.name)));
+ pin.set_mode(pin_config.mode.?);
+ }
+ }
+
+ if (input_gpios != 0) {
+ inline for (@typeInfo(Port.Configuration).Struct.fields) |field|
+ if (@field(port_config, field.name)) |pin_config| {
+ var pin = gpio.Pin.init(@intFromEnum(@field(Port, port_field.name)), @intFromEnum(@field(Pin, field.name)));
+ const pull = pin_config.pull orelse continue;
+ if (comptime pin_config.get_mode() != .input)
+ @compileError("Only input pins can have pull up/down enabled");
+
+ pin.set_pull(pull);
+ };
+ }
+ }
+ }
+
+ // fields in the Pins(config) type should be zero sized, so we just
+ // default build them all (wasn't sure how to do that cleanly in
+ // `Pins()`
+ var ret: Pins(config) = undefined;
+ inline for (@typeInfo(Pins(config)).Struct.fields) |field| {
+ if (field.default_value) |default_value| {
+ @field(ret, field.name) = @as(*const field.field_type, @ptrCast(default_value)).*;
+ } else {
+ @field(ret, field.name) = .{};
+ }
+ }
+ return ret;
+ // validate selected function
+ }
+};
diff --git a/board-support/stmicro-stm32/src/hals/STM32F303.zig b/board-support/stmicro-stm32/src/hals/STM32F303.zig
new file mode 100644
index 0000000..17c6999
--- /dev/null
+++ b/board-support/stmicro-stm32/src/hals/STM32F303.zig
@@ -0,0 +1,602 @@
+//! For now we keep all clock settings on the chip defaults.
+//! This code currently assumes the STM32F303xB / STM32F303xC clock configuration.
+//! TODO: Do something useful for other STM32f30x chips.
+//!
+//! Specifically, TIM6 is running on an 8 MHz clock,
+//! HSI = 8 MHz is the SYSCLK after reset
+//! default AHB prescaler = /1 (= values 0..7):
+//!
+//! ```
+//! RCC.CFGR.modify(.{ .HPRE = 0 });
+//! ```
+//!
+//! so also HCLK = 8 MHz.
+//! And with the default APB1 prescaler = /2:
+//!
+//! ```
+//! RCC.CFGR.modify(.{ .PPRE1 = 4 });
+//! ```
+//!
+//! results in PCLK1,
+//! and the resulting implicit factor *2 for TIM2/3/4/6/7
+//! makes TIM6 run at 8MHz/2*2 = 8 MHz.
+//!
+//! The above default configuration makes U(S)ART2..5
+//! (which use PCLK1 without that implicit *2 factor)
+//! run at 4 MHz by default.
+//!
+//! USART1 uses PCLK2, which uses the APB2 prescaler on HCLK,
+//! default APB2 prescaler = /1:
+//!
+//! ```
+//! RCC.CFGR.modify(.{ .PPRE2 = 0 });
+//! ```
+//!
+//! and therefore USART1 runs on 8 MHz.
+
+const std = @import("std");
+const runtime_safety = std.debug.runtime_safety;
+
+const micro = @import("microzig");
+const SPI1 = micro.peripherals.SPI1;
+const RCC = micro.peripherals.RCC;
+const USART1 = micro.peripherals.USART1;
+const GPIOA = micro.peripherals.GPIOA;
+const GPIOB = micro.peripherals.GPIOB;
+const GPIOC = micro.peripherals.GPIOC;
+const I2C1 = micro.peripherals.I2C1;
+
+pub const cpu = @import("cpu");
+
+pub const clock = struct {
+ pub const Domain = enum {
+ cpu,
+ ahb,
+ apb1,
+ apb2,
+ };
+};
+
+// Default clock frequencies after reset, see top comment for calculation
+pub const clock_frequencies = .{
+ .cpu = 8_000_000,
+ .ahb = 8_000_000,
+ .apb1 = 8_000_000,
+ .apb2 = 8_000_000,
+};
+
+pub fn parse_pin(comptime spec: []const u8) type {
+ const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme.";
+
+ if (spec[0] != 'P')
+ @compileError(invalid_format_msg);
+ if (spec[1] < 'A' or spec[1] > 'H')
+ @compileError(invalid_format_msg);
+
+ const pin_number: comptime_int = std.fmt.parseInt(u4, spec[2..], 10) catch @compileError(invalid_format_msg);
+
+ return struct {
+ /// 'A'...'H'
+ const gpio_port_name = spec[1..2];
+ const gpio_port = @field(micro.peripherals, "GPIO" ++ gpio_port_name);
+ const suffix = std.fmt.comptimePrint("{d}", .{pin_number});
+ };
+}
+
+fn set_reg_field(reg: anytype, comptime field_name: anytype, value: anytype) void {
+ var temp = reg.read();
+ @field(temp, field_name) = value;
+ reg.write(temp);
+}
+
+pub const gpio = struct {
+ pub fn set_output(comptime pin: type) void {
+ set_reg_field(RCC.AHBENR, "IOP" ++ pin.gpio_port_name ++ "EN", 1);
+ set_reg_field(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b01);
+ }
+
+ pub fn set_input(comptime pin: type) void {
+ set_reg_field(RCC.AHBENR, "IOP" ++ pin.gpio_port_name ++ "EN", 1);
+ set_reg_field(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b00);
+ }
+
+ pub fn read(comptime pin: type) micro.gpio.State {
+ const idr_reg = pin.gpio_port.IDR;
+ const reg_value = @field(idr_reg.read(), "IDR" ++ pin.suffix); // TODO extract to getRegField()?
+ return @as(micro.gpio.State, @enumFromInt(reg_value));
+ }
+
+ pub fn write(comptime pin: type, state: micro.gpio.State) void {
+ switch (state) {
+ .low => set_reg_field(pin.gpio_port.BRR, "BR" ++ pin.suffix, 1),
+ .high => set_reg_field(pin.gpio_port.BSRR, "BS" ++ pin.suffix, 1),
+ }
+ }
+};
+
+pub const uart = struct {
+ pub const DataBits = enum(u4) {
+ seven = 7,
+ eight = 8,
+ };
+
+ /// uses the values of USART_CR2.STOP
+ pub const StopBits = enum(u2) {
+ one = 0b00,
+ half = 0b01,
+ two = 0b10,
+ one_and_half = 0b11,
+ };
+
+ /// uses the values of USART_CR1.PS
+ pub const Parity = enum(u1) {
+ even = 0,
+ odd = 1,
+ };
+};
+
+pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type {
+ if (!(index == 1)) @compileError("TODO: only USART1 is currently supported");
+ if (pins.tx != null or pins.rx != null)
+ @compileError("TODO: custom pins are not currently supported");
+
+ return struct {
+ parity_read_mask: u8,
+
+ const Self = @This();
+
+ pub fn init(config: micro.uart.Config) !Self {
+ // The following must all be written when the USART is disabled (UE=0).
+ if (USART1.CR1.read().UE == 1)
+ @panic("Trying to initialize USART1 while it is already enabled");
+ // LATER: Alternatively, set UE=0 at this point? Then wait for something?
+ // Or add a destroy() function which disables the USART?
+
+ // enable the USART1 clock
+ RCC.APB2ENR.modify(.{ .USART1EN = 1 });
+ // enable GPIOC clock
+ RCC.AHBENR.modify(.{ .IOPCEN = 1 });
+ // set PC4+PC5 to alternate function 7, USART1_TX + USART1_RX
+ GPIOC.MODER.modify(.{ .MODER4 = 0b10, .MODER5 = 0b10 });
+ GPIOC.AFRL.modify(.{ .AFRL4 = 7, .AFRL5 = 7 });
+
+ // clear USART1 configuration to its default
+ USART1.CR1.raw = 0;
+ USART1.CR2.raw = 0;
+ USART1.CR3.raw = 0;
+
+ // set word length
+ // Per the reference manual, M[1:0] means
+ // - 00: 8 bits (7 data + 1 parity, or 8 data), probably the chip default
+ // - 01: 9 bits (8 data + 1 parity)
+ // - 10: 7 bits (7 data)
+ // So M1==1 means "7-bit mode" (in which
+ // "the Smartcard mode, LIN master mode and Auto baud rate [...] are not supported");
+ // and M0==1 means 'the 9th bit (not the 8th bit) is the parity bit'.
+ const m1: u1 = if (config.data_bits == .seven and config.parity == null) 1 else 0;
+ const m0: u1 = if (config.data_bits == .eight and config.parity != null) 1 else 0;
+ // Note that .padding0 = bit 28 = .M1 (.svd file bug?), and .M == .M0.
+ USART1.CR1.modify(.{ .padding0 = m1, .M = m0 });
+
+ // set parity
+ if (config.parity) |parity| {
+ USART1.CR1.modify(.{ .PCE = 1, .PS = @intFromEnum(parity) });
+ } else USART1.CR1.modify(.{ .PCE = 0 }); // no parity, probably the chip default
+
+ // set number of stop bits
+ USART1.CR2.modify(.{ .STOP = @intFromEnum(config.stop_bits) });
+
+ // set the baud rate
+ // TODO: Do not use the _board_'s frequency, but the _U(S)ARTx_ frequency
+ // from the chip, which can be affected by how the board configures the chip.
+ // In our case, these are accidentally the same at chip reset,
+ // if the board doesn't configure e.g. an HSE external crystal.
+ // TODO: Do some checks to see if the baud rate is too high (or perhaps too low)
+ // TODO: Do a rounding div, instead of a truncating div?
+ const usartdiv = @as(u16, @intCast(@divTrunc(micro.clock.get().apb1, config.baud_rate)));
+ USART1.BRR.raw = usartdiv;
+ // Above, ignore the BRR struct fields DIV_Mantissa and DIV_Fraction,
+ // those seem to be for another chipset; .svd file bug?
+ // TODO: We assume the default OVER8=0 configuration above.
+
+ // enable USART1, and its transmitter and receiver
+ USART1.CR1.modify(.{ .UE = 1 });
+ USART1.CR1.modify(.{ .TE = 1 });
+ USART1.CR1.modify(.{ .RE = 1 });
+
+ // For code simplicity, at cost of one or more register reads,
+ // we read back the actual configuration from the registers,
+ // instead of using the `config` values.
+ return read_from_registers();
+ }
+
+ pub fn get_or_init(config: micro.uart.Config) !Self {
+ if (USART1.CR1.read().UE == 1) {
+ // UART1 already enabled, don't reinitialize and disturb things;
+ // instead read and use the actual configuration.
+ return read_from_registers();
+ } else return init(config);
+ }
+
+ fn read_from_registers() Self {
+ const cr1 = USART1.CR1.read();
+ // As documented in `init()`, M0==1 means 'the 9th bit (not the 8th bit) is the parity bit'.
+ // So we always mask away the 9th bit, and if parity is enabled and it is in the 8th bit,
+ // then we also mask away the 8th bit.
+ return Self{ .parity_read_mask = if (cr1.PCE == 1 and cr1.M == 0) 0x7F else 0xFF };
+ }
+
+ pub fn can_write(self: Self) bool {
+ _ = self;
+ return switch (USART1.ISR.read().TXE) {
+ 1 => true,
+ 0 => false,
+ };
+ }
+
+ pub fn tx(self: Self, ch: u8) void {
+ while (!self.can_write()) {} // Wait for Previous transmission
+ USART1.TDR.modify(ch);
+ }
+
+ pub fn txflush(_: Self) void {
+ while (USART1.ISR.read().TC == 0) {}
+ }
+
+ pub fn can_read(self: Self) bool {
+ _ = self;
+ return switch (USART1.ISR.read().RXNE) {
+ 1 => true,
+ 0 => false,
+ };
+ }
+
+ pub fn rx(self: Self) u8 {
+ while (!self.can_read()) {} // Wait till the data is received
+ const data_with_parity_bit: u9 = USART1.RDR.read().RDR;
+ return @as(u8, @intCast(data_with_parity_bit & self.parity_read_mask));
+ }
+ };
+}
+
+const enable_stm32f303_debug = false;
+
+fn debug_print(comptime format: []const u8, args: anytype) void {
+ if (enable_stm32f303_debug) {
+ micro.debug.writer().print(format, args) catch {};
+ }
+}
+
+/// This implementation does not use AUTOEND=1
+pub fn I2CController(comptime index: usize, comptime pins: micro.i2c.Pins) type {
+ if (!(index == 1)) @compileError("TODO: only I2C1 is currently supported");
+ if (pins.scl != null or pins.sda != null)
+ @compileError("TODO: custom pins are not currently supported");
+
+ return struct {
+ const Self = @This();
+
+ pub fn init(config: micro.i2c.Config) !Self {
+ // CONFIGURE I2C1
+ // connected to APB1, MCU pins PB6 + PB7 = I2C1_SCL + I2C1_SDA,
+ // if GPIO port B is configured for alternate function 4 for these PB pins.
+
+ // 1. Enable the I2C CLOCK and GPIO CLOCK
+ RCC.APB1ENR.modify(.{ .I2C1EN = 1 });
+ RCC.AHBENR.modify(.{ .IOPBEN = 1 });
+ debug_print("I2C1 configuration step 1 complete\r\n", .{});
+ // 2. Configure the I2C PINs for ALternate Functions
+ // a) Select Alternate Function in MODER Register
+ GPIOB.MODER.modify(.{ .MODER6 = 0b10, .MODER7 = 0b10 });
+ // b) Select Open Drain Output
+ GPIOB.OTYPER.modify(.{ .OT6 = 1, .OT7 = 1 });
+ // c) Select High SPEED for the PINs
+ GPIOB.OSPEEDR.modify(.{ .OSPEEDR6 = 0b11, .OSPEEDR7 = 0b11 });
+ // d) Select Pull-up for both the Pins
+ GPIOB.PUPDR.modify(.{ .PUPDR6 = 0b01, .PUPDR7 = 0b01 });
+ // e) Configure the Alternate Function in AFR Register
+ GPIOB.AFRL.modify(.{ .AFRL6 = 4, .AFRL7 = 4 });
+ debug_print("I2C1 configuration step 2 complete\r\n", .{});
+
+ // 3. Reset the I2C
+ I2C1.CR1.modify(.{ .PE = 0 });
+ while (I2C1.CR1.read().PE == 1) {}
+ // DO NOT RCC.APB1RSTR.modify(.{ .I2C1RST = 1 });
+ debug_print("I2C1 configuration step 3 complete\r\n", .{});
+
+ // 4-6. Configure I2C1 timing, based on 8 MHz I2C clock, run at 100 kHz
+ // (Not using https://controllerstech.com/stm32-i2c-configuration-using-registers/
+ // but copying an example from the reference manual, RM0316 section 28.4.9.)
+ if (config.target_speed != 100_000) @panic("TODO: Support speeds other than 100 kHz");
+ I2C1.TIMINGR.modify(.{
+ .PRESC = 1,
+ .SCLL = 0x13,
+ .SCLH = 0xF,
+ .SDADEL = 0x2,
+ .SCLDEL = 0x4,
+ });
+ debug_print("I2C1 configuration steps 4-6 complete\r\n", .{});
+
+ // 7. Program the I2C_CR1 register to enable the peripheral
+ I2C1.CR1.modify(.{ .PE = 1 });
+ debug_print("I2C1 configuration step 7 complete\r\n", .{});
+
+ return Self{};
+ }
+
+ pub const WriteState = struct {
+ address: u7,
+ buffer: [255]u8 = undefined,
+ buffer_size: u8 = 0,
+
+ pub fn start(address: u7) !WriteState {
+ return WriteState{ .address = address };
+ }
+
+ pub fn write_all(self: *WriteState, bytes: []const u8) !void {
+ debug_print("I2C1 writeAll() with {d} byte(s); buffer={any}\r\n", .{ bytes.len, self.buffer[0..self.buffer_size] });
+
+ std.debug.assert(self.buffer_size < 255);
+ for (bytes) |b| {
+ self.buffer[self.buffer_size] = b;
+ self.buffer_size += 1;
+ if (self.buffer_size == 255) {
+ try self.send_buffer(1);
+ }
+ }
+ }
+
+ fn send_buffer(self: *WriteState, reload: u1) !void {
+ debug_print("I2C1 sendBuffer() with {d} byte(s); RELOAD={d}; buffer={any}\r\n", .{ self.buffer_size, reload, self.buffer[0..self.buffer_size] });
+ if (self.buffer_size == 0) @panic("write of 0 bytes not supported");
+
+ std.debug.assert(reload == 0 or self.buffer_size == 255); // see TODOs below
+
+ // As master, initiate write from address, 7 bit address
+ I2C1.CR2.modify(.{
+ .ADD10 = 0,
+ .SADD1 = self.address,
+ .RD_WRN = 0, // write
+ .NBYTES = self.buffer_size,
+ .RELOAD = reload,
+ });
+ if (reload == 0) {
+ I2C1.CR2.modify(.{ .START = 1 });
+ } else {
+ // TODO: The RELOAD=1 path is untested but doesn't seem to work yet,
+ // even though we make sure that we set NBYTES=255 per the docs.
+ }
+ for (self.buffer[0..self.buffer_size]) |b| {
+ // wait for empty transmit buffer
+ while (I2C1.ISR.read().TXE == 0) {
+ debug_print("I2C1 waiting for ready to send (TXE=0)\r\n", .{});
+ }
+ debug_print("I2C1 ready to send (TXE=1)\r\n", .{});
+ // Write data byte
+ I2C1.TXDR.modify(.{ .TXDATA = b });
+ }
+ self.buffer_size = 0;
+ debug_print("I2C1 data written\r\n", .{});
+ if (reload == 1) {
+ // TODO: The RELOAD=1 path is untested but doesn't seem to work yet,
+ // the following loop never seems to finish.
+ while (I2C1.ISR.read().TCR == 0) {
+ debug_print("I2C1 waiting transmit complete (TCR=0)\r\n", .{});
+ }
+ debug_print("I2C1 transmit complete (TCR=1)\r\n", .{});
+ } else {
+ while (I2C1.ISR.read().TC == 0) {
+ debug_print("I2C1 waiting for transmit complete (TC=0)\r\n", .{});
+ }
+ debug_print("I2C1 transmit complete (TC=1)\r\n", .{});
+ }
+ }
+
+ pub fn stop(self: *WriteState) !void {
+ try self.send_buffer(0);
+ // Communication STOP
+ debug_print("I2C1 STOPping\r\n", .{});
+ I2C1.CR2.modify(.{ .STOP = 1 });
+ while (I2C1.ISR.read().BUSY == 1) {}
+ debug_print("I2C1 STOPped\r\n", .{});
+ }
+
+ pub fn restart_read(self: *WriteState) !ReadState {
+ try self.send_buffer(0);
+ return ReadState{ .address = self.address };
+ }
+ pub fn restart_write(self: *WriteState) !WriteState {
+ try self.send_buffer(0);
+ return WriteState{ .address = self.address };
+ }
+ };
+
+ pub const ReadState = struct {
+ address: u7,
+ read_allowed: if (runtime_safety) bool else void = if (runtime_safety) true else {},
+
+ pub fn start(address: u7) !ReadState {
+ return ReadState{ .address = address };
+ }
+
+ /// Fails with ReadError if incorrect number of bytes is received.
+ pub fn read_no_eof(self: *ReadState, buffer: []u8) !void {
+ if (runtime_safety and !self.read_allowed) @panic("second read call not allowed");
+ std.debug.assert(buffer.len < 256); // TODO: use RELOAD to read more data
+
+ // As master, initiate read from accelerometer, 7 bit address
+ I2C1.CR2.modify(.{
+ .ADD10 = 0,
+ .SADD1 = self.address,
+ .RD_WRN = 1, // read
+ .NBYTES = @as(u8, @intCast(buffer.len)),
+ });
+ debug_print("I2C1 prepared for read of {} byte(s) from 0b{b:0<7}\r\n", .{ buffer.len, self.address });
+
+ // Communication START
+ I2C1.CR2.modify(.{ .START = 1 });
+ debug_print("I2C1 RXNE={}\r\n", .{I2C1.ISR.read().RXNE});
+ debug_print("I2C1 STARTed\r\n", .{});
+ debug_print("I2C1 RXNE={}\r\n", .{I2C1.ISR.read().RXNE});
+
+ if (runtime_safety) self.read_allowed = false;
+
+ for (buffer, 0..) |_, i| {
+ // Wait for data to be received
+ while (I2C1.ISR.read().RXNE == 0) {
+ debug_print("I2C1 waiting for data (RXNE=0)\r\n", .{});
+ }
+ debug_print("I2C1 data ready (RXNE=1)\r\n", .{});
+
+ // Read first data byte
+ buffer[i] = I2C1.RXDR.read().RXDATA;
+ }
+ debug_print("I2C1 data: {any}\r\n", .{buffer});
+ }
+
+ pub fn stop(_: *ReadState) !void {
+ // Communication STOP
+ I2C1.CR2.modify(.{ .STOP = 1 });
+ while (I2C1.ISR.read().BUSY == 1) {}
+ debug_print("I2C1 STOPped\r\n", .{});
+ }
+
+ pub fn restart_read(self: *ReadState) !ReadState {
+ debug_print("I2C1 no action for restart\r\n", .{});
+ return ReadState{ .address = self.address };
+ }
+ pub fn restart_write(self: *ReadState) !WriteState {
+ debug_print("I2C1 no action for restart\r\n", .{});
+ return WriteState{ .address = self.address };
+ }
+ };
+ };
+}
+
+/// An STM32F303 SPI bus
+pub fn SpiBus(comptime index: usize) type {
+ if (!(index == 1)) @compileError("TODO: only SPI1 is currently supported");
+
+ return struct {
+ const Self = @This();
+
+ /// Initialize and enable the bus.
+ pub fn init(config: micro.spi.BusConfig) !Self {
+ _ = config; // unused for now
+
+ // CONFIGURE SPI1
+ // connected to APB2, MCU pins PA5 + PA7 + PA6 = SPC + SDI + SDO,
+ // if GPIO port A is configured for alternate function 5 for these PA pins.
+
+ // Enable the GPIO CLOCK
+ RCC.AHBENR.modify(.{ .IOPAEN = 1 });
+
+ // Configure the I2C PINs for ALternate Functions
+ // - Select Alternate Function in MODER Register
+ GPIOA.MODER.modify(.{ .MODER5 = 0b10, .MODER6 = 0b10, .MODER7 = 0b10 });
+ // - Select High SPEED for the PINs
+ GPIOA.OSPEEDR.modify(.{ .OSPEEDR5 = 0b11, .OSPEEDR6 = 0b11, .OSPEEDR7 = 0b11 });
+ // - Configure the Alternate Function in AFR Register
+ GPIOA.AFRL.modify(.{ .AFRL5 = 5, .AFRL6 = 5, .AFRL7 = 5 });
+
+ // Enable the SPI1 CLOCK
+ RCC.APB2ENR.modify(.{ .SPI1EN = 1 });
+
+ SPI1.CR1.modify(.{
+ .MSTR = 1,
+ .SSM = 1,
+ .SSI = 1,
+ .RXONLY = 0,
+ .SPE = 1,
+ });
+ // the following configuration is assumed in `transceiveByte()`
+ SPI1.CR2.raw = 0;
+ SPI1.CR2.modify(.{
+ .DS = 0b0111, // 8-bit data frames, seems default via '0b0000 is interpreted as 0b0111'
+ .FRXTH = 1, // RXNE event after 1 byte received
+ });
+
+ return Self{};
+ }
+
+ /// Switch this SPI bus to the given device.
+ pub fn switch_to_device(_: Self, comptime cs_pin: type, config: micro.spi.DeviceConfig) void {
+ _ = config; // for future use
+
+ SPI1.CR1.modify(.{
+ .CPOL = 1, // TODO: make configurable
+ .CPHA = 1, // TODO: make configurable
+ .BR = 0b111, // 1/256 the of PCLK TODO: make configurable
+ .LSBFIRST = 0, // MSB first TODO: make configurable
+ });
+ gpio.set_output(cs_pin);
+ }
+
+ /// Begin a transfer to the given device. (Assumes `switchToDevice()` was called.)
+ pub fn begin_transfer(_: Self, comptime cs_pin: type, config: micro.spi.DeviceConfig) void {
+ _ = config; // for future use
+ gpio.write(cs_pin, .low); // select the given device, TODO: support inverse CS devices
+ debug_print("enabled SPI1\r\n", .{});
+ }
+
+ /// The basic operation in the current simplistic implementation:
+ /// send+receive a single byte.
+ /// Writing `null` writes an arbitrary byte (`undefined`), and
+ /// reading into `null` ignores the value received.
+ pub fn transceive_byte(_: Self, optional_write_byte: ?u8, optional_read_pointer: ?*u8) !void {
+
+ // SPIx_DR's least significant byte is `@bitCast([dr_byte_size]u8, ...)[0]`
+ const dr_byte_size = @sizeOf(@TypeOf(SPI1.DR.raw));
+
+ // wait unril ready for write
+ while (SPI1.SR.read().TXE == 0) {
+ debug_print("SPI1 TXE == 0\r\n", .{});
+ }
+ debug_print("SPI1 TXE == 1\r\n", .{});
+
+ // write
+ const write_byte = if (optional_write_byte) |b| b else undefined; // dummy value
+ @as([dr_byte_size]u8, @bitCast(SPI1.DR.*))[0] = write_byte;
+ debug_print("Sent: {X:2}.\r\n", .{write_byte});
+
+ // wait until read processed
+ while (SPI1.SR.read().RXNE == 0) {
+ debug_print("SPI1 RXNE == 0\r\n", .{});
+ }
+ debug_print("SPI1 RXNE == 1\r\n", .{});
+
+ // read
+ var data_read = SPI1.DR.raw;
+ _ = SPI1.SR.read(); // clear overrun flag
+ const dr_lsb = @as([dr_byte_size]u8, @bitCast(data_read))[0];
+ debug_print("Received: {X:2} (DR = {X:8}).\r\n", .{ dr_lsb, data_read });
+ if (optional_read_pointer) |read_pointer| read_pointer.* = dr_lsb;
+ }
+
+ /// Write all given bytes on the bus, not reading anything back.
+ pub fn write_all(self: Self, bytes: []const u8) !void {
+ for (bytes) |b| {
+ try self.transceive_byte(b, null);
+ }
+ }
+
+ /// Read bytes to fill the given buffer exactly, writing arbitrary bytes (`undefined`).
+ pub fn read_into(self: Self, buffer: []u8) !void {
+ for (buffer, 0..) |_, i| {
+ try self.transceive_byte(null, &buffer[i]);
+ }
+ }
+
+ pub fn end_transfer(_: Self, comptime cs_pin: type, config: micro.spi.DeviceConfig) void {
+ _ = config; // for future use
+ // no delay should be needed here, since we know SPIx_SR's TXE is 1
+ debug_print("(disabling SPI1)\r\n", .{});
+ gpio.write(cs_pin, .high); // deselect the given device, TODO: support inverse CS devices
+ // HACK: wait long enough to make any device end an ongoing transfer
+ var i: u8 = 255; // with the default clock, this seems to delay ~185 microseconds
+ while (i > 0) : (i -= 1) {
+ asm volatile ("nop");
+ }
+ }
+ };
+}
diff --git a/board-support/stmicro-stm32/src/hals/STM32F407.zig b/board-support/stmicro-stm32/src/hals/STM32F407.zig
new file mode 100644
index 0000000..6c4dd20
--- /dev/null
+++ b/board-support/stmicro-stm32/src/hals/STM32F407.zig
@@ -0,0 +1,623 @@
+//! For now we keep all clock settings on the chip defaults.
+//! This code currently assumes the STM32F405xx / STM32F407xx clock configuration.
+//! TODO: Do something useful for other STM32F40x chips.
+//!
+//! Specifically, TIM6 is running on a 16 MHz clock,
+//! HSI = 16 MHz is the SYSCLK after reset
+//! default AHB prescaler = /1 (= values 0..7):
+//!
+//! ```
+//! RCC.CFGR.modify(.{ .HPRE = 0 });
+//! ```
+//!
+//! so also HCLK = 16 MHz.
+//! And with the default APB1 prescaler = /1:
+//!
+//! ```
+//! RCC.CFGR.modify(.{ .PPRE1 = 0 });
+//! ```
+//!
+//! results in PCLK1 = 16 MHz.
+//!
+//! The above default configuration makes U(S)ART2..5
+//! receive a 16 MHz clock by default.
+//!
+//! USART1 and USART6 use PCLK2, which uses the APB2 prescaler on HCLK,
+//! default APB2 prescaler = /1:
+//!
+//! ```
+//! RCC.CFGR.modify(.{ .PPRE2 = 0 });
+//! ```
+//!
+//! and therefore USART1 and USART6 receive a 16 MHz clock.
+//!
+
+const std = @import("std");
+const micro = @import("microzig");
+const peripherals = micro.peripherals;
+const RCC = peripherals.RCC;
+
+pub const clock = struct {
+ pub const Domain = enum {
+ cpu,
+ ahb,
+ apb1,
+ apb2,
+ };
+};
+
+// Default clock frequencies after reset, see top comment for calculation
+pub const clock_frequencies = .{
+ .cpu = 16_000_000,
+ .ahb = 16_000_000,
+ .apb1 = 16_000_000,
+ .apb2 = 16_000_000,
+};
+
+pub fn parse_pin(comptime spec: []const u8) type {
+ const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme.";
+
+ if (spec[0] != 'P')
+ @compileError(invalid_format_msg);
+ if (spec[1] < 'A' or spec[1] > 'I')
+ @compileError(invalid_format_msg);
+
+ return struct {
+ const pin_number: comptime_int = std.fmt.parseInt(u4, spec[2..], 10) catch @compileError(invalid_format_msg);
+ /// 'A'...'I'
+ const gpio_port_name = spec[1..2];
+ const gpio_port = @field(peripherals, "GPIO" ++ gpio_port_name);
+ const suffix = std.fmt.comptimePrint("{d}", .{pin_number});
+ };
+}
+
+fn set_reg_field(reg: anytype, comptime field_name: anytype, value: anytype) void {
+ var temp = reg.read();
+ @field(temp, field_name) = value;
+ reg.write(temp);
+}
+
+pub const gpio = struct {
+ pub const AlternateFunction = enum(u4) {
+ af0,
+ af1,
+ af2,
+ af3,
+ af4,
+ af5,
+ af6,
+ af7,
+ af8,
+ af9,
+ af10,
+ af11,
+ af12,
+ af13,
+ af14,
+ af15,
+ };
+
+ pub fn set_output(comptime pin: type) void {
+ set_reg_field(RCC.AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1);
+ set_reg_field(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b01);
+ }
+
+ pub fn set_input(comptime pin: type) void {
+ set_reg_field(RCC.AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1);
+ set_reg_field(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b00);
+ }
+
+ pub fn set_alternate_function(comptime pin: type, af: AlternateFunction) void {
+ set_reg_field(RCC.AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1);
+ set_reg_field(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b10);
+ if (pin.pin_number < 8) {
+ set_reg_field(@field(pin.gpio_port, "AFRL"), "AFRL" ++ pin.suffix, @intFromEnum(af));
+ } else {
+ set_reg_field(@field(pin.gpio_port, "AFRH"), "AFRH" ++ pin.suffix, @intFromEnum(af));
+ }
+ }
+
+ pub fn read(comptime pin: type) micro.gpio.State {
+ const idr_reg = pin.gpio_port.IDR;
+ const reg_value = @field(idr_reg.read(), "IDR" ++ pin.suffix); // TODO extract to getRegField()?
+ return @as(micro.gpio.State, @enumFromInt(reg_value));
+ }
+
+ pub fn write(comptime pin: type, state: micro.gpio.State) void {
+ switch (state) {
+ .low => set_reg_field(pin.gpio_port.BSRR, "BR" ++ pin.suffix, 1),
+ .high => set_reg_field(pin.gpio_port.BSRR, "BS" ++ pin.suffix, 1),
+ }
+ }
+};
+
+pub const uart = struct {
+ pub const DataBits = enum {
+ seven,
+ eight,
+ nine,
+ };
+
+ /// uses the values of USART_CR2.STOP
+ pub const StopBits = enum(u2) {
+ one = 0b00,
+ half = 0b01,
+ two = 0b10,
+ one_and_half = 0b11,
+ };
+
+ /// uses the values of USART_CR1.PS
+ pub const Parity = enum(u1) {
+ even = 0,
+ odd = 1,
+ };
+
+ const PinDirection = std.meta.FieldEnum(micro.uart.Pins);
+
+ /// Checks if a pin is valid for a given uart index and direction
+ pub fn is_valid_pin(comptime pin: type, comptime index: usize, comptime direction: PinDirection) bool {
+ const pin_name = pin.name;
+
+ return switch (direction) {
+ .tx => switch (index) {
+ 1 => std.mem.eql(u8, pin_name, "PA9") or std.mem.eql(u8, pin_name, "PB6"),
+ 2 => std.mem.eql(u8, pin_name, "PA2") or std.mem.eql(u8, pin_name, "PD5"),
+ 3 => std.mem.eql(u8, pin_name, "PB10") or std.mem.eql(u8, pin_name, "PC10") or std.mem.eql(u8, pin_name, "PD8"),
+ 4 => std.mem.eql(u8, pin_name, "PA0") or std.mem.eql(u8, pin_name, "PC10"),
+ 5 => std.mem.eql(u8, pin_name, "PC12"),
+ 6 => std.mem.eql(u8, pin_name, "PC6") or std.mem.eql(u8, pin_name, "PG14"),
+ else => unreachable,
+ },
+ // Valid RX pins for the UARTs
+ .rx => switch (index) {
+ 1 => std.mem.eql(u8, pin_name, "PA10") or std.mem.eql(u8, pin_name, "PB7"),
+ 2 => std.mem.eql(u8, pin_name, "PA3") or std.mem.eql(u8, pin_name, "PD6"),
+ 3 => std.mem.eql(u8, pin_name, "PB11") or std.mem.eql(u8, pin_name, "PC11") or std.mem.eql(u8, pin_name, "PD9"),
+ 4 => std.mem.eql(u8, pin_name, "PA1") or std.mem.eql(u8, pin_name, "PC11"),
+ 5 => std.mem.eql(u8, pin_name, "PD2"),
+ 6 => std.mem.eql(u8, pin_name, "PC7") or std.mem.eql(u8, pin_name, "PG9"),
+ else => unreachable,
+ },
+ };
+ }
+};
+
+pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type {
+ if (index < 1 or index > 6) @compileError("Valid USART index are 1..6");
+
+ const usart_name = std.fmt.comptimePrint("USART{d}", .{index});
+ const tx_pin =
+ if (pins.tx) |tx|
+ if (uart.is_valid_pin(tx, index, .tx))
+ tx
+ else
+ @compileError(std.fmt.comptimePrint("Tx pin {s} is not valid for UART{}", .{ tx.name, index }))
+ else switch (index) {
+ // Provide default tx pins if no pin is specified
+ 1 => micro.Pin("PA9"),
+ 2 => micro.Pin("PA2"),
+ 3 => micro.Pin("PB10"),
+ 4 => micro.Pin("PA0"),
+ 5 => micro.Pin("PC12"),
+ 6 => micro.Pin("PC6"),
+ else => unreachable,
+ };
+
+ const rx_pin =
+ if (pins.rx) |rx|
+ if (uart.is_valid_pin(rx, index, .rx))
+ rx
+ else
+ @compileError(std.fmt.comptimePrint("Rx pin {s} is not valid for UART{}", .{ rx.name, index }))
+ else switch (index) {
+ // Provide default rx pins if no pin is specified
+ 1 => micro.Pin("PA10"),
+ 2 => micro.Pin("PA3"),
+ 3 => micro.Pin("PB11"),
+ 4 => micro.Pin("PA1"),
+ 5 => micro.Pin("PD2"),
+ 6 => micro.Pin("PC7"),
+ else => unreachable,
+ };
+
+ // USART1..3 are AF7, USART 4..6 are AF8
+ const alternate_function = if (index <= 3) .af7 else .af8;
+
+ const tx_gpio = micro.Gpio(tx_pin, .{
+ .mode = .alternate_function,
+ .alternate_function = alternate_function,
+ });
+ const rx_gpio = micro.Gpio(rx_pin, .{
+ .mode = .alternate_function,
+ .alternate_function = alternate_function,
+ });
+
+ return struct {
+ parity_read_mask: u8,
+
+ const Self = @This();
+
+ pub fn init(config: micro.uart.Config) !Self {
+ // The following must all be written when the USART is disabled (UE=0).
+ if (@field(peripherals, usart_name).CR1.read().UE == 1)
+ @panic("Trying to initialize " ++ usart_name ++ " while it is already enabled");
+ // LATER: Alternatively, set UE=0 at this point? Then wait for something?
+ // Or add a destroy() function which disables the USART?
+
+ // enable the USART clock
+ const clk_enable_reg = switch (index) {
+ 1, 6 => RCC.APB2ENR,
+ 2...5 => RCC.APB1ENR,
+ else => unreachable,
+ };
+ set_reg_field(clk_enable_reg, usart_name ++ "EN", 1);
+
+ tx_gpio.init();
+ rx_gpio.init();
+
+ // clear USART configuration to its default
+ @field(peripherals, usart_name).CR1.raw = 0;
+ @field(peripherals, usart_name).CR2.raw = 0;
+ @field(peripherals, usart_name).CR3.raw = 0;
+
+ // Return error for unsupported combinations
+ if (config.data_bits == .nine and config.parity != null) {
+ // TODO: should we consider this an unsupported word size or unsupported parity?
+ return error.UnsupportedWordSize;
+ } else if (config.data_bits == .seven and config.parity == null) {
+ // TODO: should we consider this an unsupported word size or unsupported parity?
+ return error.UnsupportedWordSize;
+ }
+
+ // set word length
+ // Per the reference manual, M means
+ // - 0: 1 start bit, 8 data bits (7 data + 1 parity, or 8 data), n stop bits, the chip default
+ // - 1: 1 start bit, 9 data bits (8 data + 1 parity, or 9 data), n stop bits
+ const m: u1 = if (config.data_bits == .nine or (config.data_bits == .eight and config.parity != null)) 1 else 0;
+ @field(peripherals, usart_name).CR1.modify(.{ .M = m });
+
+ // set parity
+ if (config.parity) |parity| {
+ @field(peripherals, usart_name).CR1.modify(.{ .PCE = 1, .PS = @intFromEnum(parity) });
+ } // otherwise, no need to set no parity since we reset Control Registers above, and it's the default
+
+ // set number of stop bits
+ @field(peripherals, usart_name).CR2.modify(.{ .STOP = @intFromEnum(config.stop_bits) });
+
+ // set the baud rate
+ // Despite the reference manual talking about fractional calculation and other buzzwords,
+ // it is actually just a simple divider. Just ignore DIV_Mantissa and DIV_Fraction and
+ // set the result of the division as the lower 16 bits of BRR.
+ // TODO: We assume the default OVER8=0 configuration above (i.e. 16x oversampling).
+ // TODO: Do some checks to see if the baud rate is too high (or perhaps too low)
+ // TODO: Do a rounding div, instead of a truncating div?
+ const clocks = micro.clock.get();
+ const bus_frequency = switch (index) {
+ 1, 6 => clocks.apb2,
+ 2...5 => clocks.apb1,
+ else => unreachable,
+ };
+ const usartdiv = @as(u16, @intCast(@divTrunc(bus_frequency, config.baud_rate)));
+ @field(peripherals, usart_name).BRR.raw = usartdiv;
+
+ // enable USART, and its transmitter and receiver
+ @field(peripherals, usart_name).CR1.modify(.{ .UE = 1 });
+ @field(peripherals, usart_name).CR1.modify(.{ .TE = 1 });
+ @field(peripherals, usart_name).CR1.modify(.{ .RE = 1 });
+
+ // For code simplicity, at cost of one or more register reads,
+ // we read back the actual configuration from the registers,
+ // instead of using the `config` values.
+ return read_from_registers();
+ }
+
+ pub fn get_or_init(config: micro.uart.Config) !Self {
+ if (@field(peripherals, usart_name).CR1.read().UE == 1) {
+ // UART1 already enabled, don't reinitialize and disturb things;
+ // instead read and use the actual configuration.
+ return read_from_registers();
+ } else return init(config);
+ }
+
+ fn read_from_registers() Self {
+ const cr1 = @field(peripherals, usart_name).CR1.read();
+ // As documented in `init()`, M0==1 means 'the 9th bit (not the 8th bit) is the parity bit'.
+ // So we always mask away the 9th bit, and if parity is enabled and it is in the 8th bit,
+ // then we also mask away the 8th bit.
+ return Self{ .parity_read_mask = if (cr1.PCE == 1 and cr1.M == 0) 0x7F else 0xFF };
+ }
+
+ pub fn can_write(self: Self) bool {
+ _ = self;
+ return switch (@field(peripherals, usart_name).SR.read().TXE) {
+ 1 => true,
+ 0 => false,
+ };
+ }
+
+ pub fn tx(self: Self, ch: u8) void {
+ while (!self.can_write()) {} // Wait for Previous transmission
+ @field(peripherals, usart_name).DR.modify(ch);
+ }
+
+ pub fn txflush(_: Self) void {
+ while (@field(peripherals, usart_name).SR.read().TC == 0) {}
+ }
+
+ pub fn can_read(self: Self) bool {
+ _ = self;
+ return switch (@field(peripherals, usart_name).SR.read().RXNE) {
+ 1 => true,
+ 0 => false,
+ };
+ }
+
+ pub fn rx(self: Self) u8 {
+ while (!self.can_read()) {} // Wait till the data is received
+ const data_with_parity_bit: u9 = @field(peripherals, usart_name).DR.read();
+ return @as(u8, @intCast(data_with_parity_bit & self.parity_read_mask));
+ }
+ };
+}
+
+pub const i2c = struct {
+ const PinLine = std.meta.FieldEnum(micro.i2c.Pins);
+
+ /// Checks if a pin is valid for a given i2c index and line
+ pub fn is_valid_pin(comptime pin: type, comptime index: usize, comptime line: PinLine) bool {
+ const pin_name = pin.name;
+
+ return switch (line) {
+ .scl => switch (index) {
+ 1 => std.mem.eql(u8, pin_name, "PB6") or std.mem.eql(u8, pin_name, "PB8"),
+ 2 => std.mem.eql(u8, pin_name, "PB10") or std.mem.eql(u8, pin_name, "PF1") or std.mem.eql(u8, pin_name, "PH4"),
+ 3 => std.mem.eql(u8, pin_name, "PA8") or std.mem.eql(u8, pin_name, "PH7"),
+ else => unreachable,
+ },
+ // Valid RX pins for the UARTs
+ .sda => switch (index) {
+ 1 => std.mem.eql(u8, pin_name, "PB7") or std.mem.eql(u8, pin_name, "PB9"),
+ 2 => std.mem.eql(u8, pin_name, "PB11") or std.mem.eql(u8, pin_name, "PF0") or std.mem.eql(u8, pin_name, "PH5"),
+ 3 => std.mem.eql(u8, pin_name, "PC9") or std.mem.eql(u8, pin_name, "PH8"),
+ else => unreachable,
+ },
+ };
+ }
+};
+
+pub fn I2CController(comptime index: usize, comptime pins: micro.i2c.Pins) type {
+ if (index < 1 or index > 3) @compileError("Valid I2C index are 1..3");
+
+ const i2c_name = std.fmt.comptimePrint("I2C{d}", .{index});
+ const scl_pin =
+ if (pins.scl) |scl|
+ if (uart.is_valid_pin(scl, index, .scl))
+ scl
+ else
+ @compileError(std.fmt.comptimePrint("SCL pin {s} is not valid for I2C{}", .{ scl.name, index }))
+ else switch (index) {
+ // Provide default scl pins if no pin is specified
+ 1 => micro.Pin("PB6"),
+ 2 => micro.Pin("PB10"),
+ 3 => micro.Pin("PA8"),
+ else => unreachable,
+ };
+
+ const sda_pin =
+ if (pins.sda) |sda|
+ if (uart.is_valid_pin(sda, index, .sda))
+ sda
+ else
+ @compileError(std.fmt.comptimePrint("SDA pin {s} is not valid for UART{}", .{ sda.name, index }))
+ else switch (index) {
+ // Provide default sda pins if no pin is specified
+ 1 => micro.Pin("PB7"),
+ 2 => micro.Pin("PB11"),
+ 3 => micro.Pin("PC9"),
+ else => unreachable,
+ };
+
+ const scl_gpio = micro.Gpio(scl_pin, .{
+ .mode = .alternate_function,
+ .alternate_function = .af4,
+ });
+ const sda_gpio = micro.Gpio(sda_pin, .{
+ .mode = .alternate_function,
+ .alternate_function = .af4,
+ });
+
+ // Base field of the specific I2C peripheral
+ const i2c_base = @field(peripherals, i2c_name);
+
+ return struct {
+ const Self = @This();
+
+ pub fn init(config: micro.i2c.Config) !Self {
+ // Configure I2C
+
+ // 1. Enable the I2C CLOCK and GPIO CLOCK
+ RCC.APB1ENR.modify(.{ .I2C1EN = 1 });
+ RCC.AHB1ENR.modify(.{ .GPIOBEN = 1 });
+
+ // 2. Configure the I2C PINs
+ // This takes care of setting them alternate function mode with the correct AF
+ scl_gpio.init();
+ sda_gpio.init();
+
+ // TODO: the stuff below will probably use the microzig gpio API in the future
+ const scl = scl_pin.source_pin;
+ const sda = sda_pin.source_pin;
+ // Select Open Drain Output
+ set_reg_field(@field(scl.gpio_port, "OTYPER"), "OT" ++ scl.suffix, 1);
+ set_reg_field(@field(sda.gpio_port, "OTYPER"), "OT" ++ sda.suffix, 1);
+ // Select High Speed
+ set_reg_field(@field(scl.gpio_port, "OSPEEDR"), "OSPEEDR" ++ scl.suffix, 0b10);
+ set_reg_field(@field(sda.gpio_port, "OSPEEDR"), "OSPEEDR" ++ sda.suffix, 0b10);
+ // Activate Pull-up
+ set_reg_field(@field(scl.gpio_port, "PUPDR"), "PUPDR" ++ scl.suffix, 0b01);
+ set_reg_field(@field(sda.gpio_port, "PUPDR"), "PUPDR" ++ sda.suffix, 0b01);
+
+ // 3. Reset the I2C
+ i2c_base.CR1.modify(.{ .PE = 0 });
+ while (i2c_base.CR1.read().PE == 1) {}
+
+ // 4. Configure I2C timing
+ const bus_frequency_hz = micro.clock.get().apb1;
+ const bus_frequency_mhz: u6 = @as(u6, @intCast(@divExact(bus_frequency_hz, 1_000_000)));
+
+ if (bus_frequency_mhz < 2 or bus_frequency_mhz > 50) {
+ return error.InvalidBusFrequency;
+ }
+
+ // .FREQ is set to the bus frequency in Mhz
+ i2c_base.CR2.modify(.{ .FREQ = bus_frequency_mhz });
+
+ switch (config.target_speed) {
+ 10_000...100_000 => {
+ // CCR is bus_freq / (target_speed * 2). We use floor to avoid exceeding the target speed.
+ const ccr = @as(u12, @intCast(@divFloor(bus_frequency_hz, config.target_speed * 2)));
+ i2c_base.CCR.modify(.{ .CCR = ccr });
+ // Trise is bus frequency in Mhz + 1
+ i2c_base.TRISE.modify(bus_frequency_mhz + 1);
+ },
+ 100_001...400_000 => {
+ // TODO: handle fast mode
+ return error.InvalidSpeed;
+ },
+ else => return error.InvalidSpeed,
+ }
+
+ // 5. Program the I2C_CR1 register to enable the peripheral
+ i2c_base.CR1.modify(.{ .PE = 1 });
+
+ return Self{};
+ }
+
+ pub const WriteState = struct {
+ address: u7,
+ buffer: [255]u8 = undefined,
+ buffer_size: u8 = 0,
+
+ pub fn start(address: u7) !WriteState {
+ return WriteState{ .address = address };
+ }
+
+ pub fn write_all(self: *WriteState, bytes: []const u8) !void {
+ std.debug.assert(self.buffer_size < 255);
+ for (bytes) |b| {
+ self.buffer[self.buffer_size] = b;
+ self.buffer_size += 1;
+ if (self.buffer_size == 255) {
+ try self.send_buffer();
+ }
+ }
+ }
+
+ fn send_buffer(self: *WriteState) !void {
+ if (self.buffer_size == 0) @panic("write of 0 bytes not supported");
+
+ // Wait for the bus to be free
+ while (i2c_base.SR2.read().BUSY == 1) {}
+
+ // Send start
+ i2c_base.CR1.modify(.{ .START = 1 });
+
+ // Wait for the end of the start condition, master mode selected, and BUSY bit set
+ while ((i2c_base.SR1.read().SB == 0 or
+ i2c_base.SR2.read().MSL == 0 or
+ i2c_base.SR2.read().BUSY == 0))
+ {}
+
+ // Write the address to bits 7..1, bit 0 stays at 0 to indicate write operation
+ i2c_base.DR.modify(@as(u8, @intCast(self.address)) << 1);
+
+ // Wait for address confirmation
+ while (i2c_base.SR1.read().ADDR == 0) {}
+
+ // Read SR2 to clear address condition
+ _ = i2c_base.SR2.read();
+
+ for (self.buffer[0..self.buffer_size]) |b| {
+ // Write data byte
+ i2c_base.DR.modify(b);
+ // Wait for transfer finished
+ while (i2c_base.SR1.read().BTF == 0) {}
+ }
+ self.buffer_size = 0;
+ }
+
+ pub fn stop(self: *WriteState) !void {
+ try self.send_buffer();
+ // Communication STOP
+ i2c_base.CR1.modify(.{ .STOP = 1 });
+ while (i2c_base.SR2.read().BUSY == 1) {}
+ }
+
+ pub fn restart_read(self: *WriteState) !ReadState {
+ try self.send_buffer();
+ return ReadState{ .address = self.address };
+ }
+ pub fn restart_write(self: *WriteState) !WriteState {
+ try self.send_buffer();
+ return WriteState{ .address = self.address };
+ }
+ };
+
+ pub const ReadState = struct {
+ address: u7,
+
+ pub fn start(address: u7) !ReadState {
+ return ReadState{ .address = address };
+ }
+
+ /// Fails with ReadError if incorrect number of bytes is received.
+ pub fn read_no_eof(self: *ReadState, buffer: []u8) !void {
+ std.debug.assert(buffer.len < 256);
+
+ // Send start and enable ACK
+ i2c_base.CR1.modify(.{ .START = 1, .ACK = 1 });
+
+ // Wait for the end of the start condition, master mode selected, and BUSY bit set
+ while ((i2c_base.SR1.read().SB == 0 or
+ i2c_base.SR2.read().MSL == 0 or
+ i2c_base.SR2.read().BUSY == 0))
+ {}
+
+ // Write the address to bits 7..1, bit 0 set to 1 to indicate read operation
+ i2c_base.DR.modify((@as(u8, @intCast(self.address)) << 1) | 1);
+
+ // Wait for address confirmation
+ while (i2c_base.SR1.read().ADDR == 0) {}
+
+ // Read SR2 to clear address condition
+ _ = i2c_base.SR2.read();
+
+ for (buffer, 0..) |_, i| {
+ if (i == buffer.len - 1) {
+ // Disable ACK
+ i2c_base.CR1.modify(.{ .ACK = 0 });
+ }
+
+ // Wait for data to be received
+ while (i2c_base.SR1.read().RxNE == 0) {}
+
+ // Read data byte
+ buffer[i] = i2c_base.DR.read();
+ }
+ }
+
+ pub fn stop(_: *ReadState) !void {
+ // Communication STOP
+ i2c_base.CR1.modify(.{ .STOP = 1 });
+ while (i2c_base.SR2.read().BUSY == 1) {}
+ }
+
+ pub fn restart_read(self: *ReadState) !ReadState {
+ return ReadState{ .address = self.address };
+ }
+ pub fn restart_write(self: *ReadState) !WriteState {
+ return WriteState{ .address = self.address };
+ }
+ };
+ };
+}
diff --git a/board-support/stmicro-stm32/src/hals/STM32F429.zig b/board-support/stmicro-stm32/src/hals/STM32F429.zig
new file mode 100644
index 0000000..0f5204d
--- /dev/null
+++ b/board-support/stmicro-stm32/src/hals/STM32F429.zig
@@ -0,0 +1,92 @@
+//! For now we keep all clock settings on the chip defaults.
+//! This code should work with all the STM32F42xx line
+//!
+//! Specifically, TIM6 is running on a 16 MHz clock,
+//! HSI = 16 MHz is the SYSCLK after reset
+//! default AHB prescaler = /1 (= values 0..7):
+//!
+//! ```
+//! RCC.CFGR.modify(.{ .HPRE = 0 });
+//! ```
+//!
+//! so also HCLK = 16 MHz.
+//! And with the default APB1 prescaler = /1:
+//!
+//! ```
+//! RCC.CFGR.modify(.{ .PPRE1 = 0 });
+//! ```
+//!
+//! results in PCLK1 = 16 MHz.
+//!
+//! TODO: add more clock calculations when adding Uart
+
+const std = @import("std");
+const micro = @import("microzig");
+const peripherals = micro.peripherals;
+const RCC = peripherals.RCC;
+
+pub const clock = struct {
+ pub const Domain = enum {
+ cpu,
+ ahb,
+ apb1,
+ apb2,
+ };
+};
+
+// Default clock frequencies after reset, see top comment for calculation
+pub const clock_frequencies = .{
+ .cpu = 16_000_000,
+ .ahb = 16_000_000,
+ .apb1 = 16_000_000,
+ .apb2 = 16_000_000,
+};
+
+pub fn parsePin(comptime spec: []const u8) type {
+ const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme.";
+
+ if (spec[0] != 'P')
+ @compileError(invalid_format_msg);
+ if (spec[1] < 'A' or spec[1] > 'K')
+ @compileError(invalid_format_msg);
+
+ const pin_number: comptime_int = std.fmt.parseInt(u4, spec[2..], 10) catch @compileError(invalid_format_msg);
+
+ return struct {
+ /// 'A'...'K'
+ const gpio_port_name = spec[1..2];
+ const gpio_port = @field(peripherals, "GPIO" ++ gpio_port_name);
+ const suffix = std.fmt.comptimePrint("{d}", .{pin_number});
+ };
+}
+
+fn setRegField(reg: anytype, comptime field_name: anytype, value: anytype) void {
+ var temp = reg.read();
+ @field(temp, field_name) = value;
+ reg.write(temp);
+}
+
+pub const gpio = struct {
+ pub fn setOutput(comptime pin: type) void {
+ setRegField(RCC.AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1);
+ setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b01);
+ }
+
+ pub fn setInput(comptime pin: type) void {
+ setRegField(RCC.AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1);
+ setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b00);
+ }
+
+ pub fn read(comptime pin: type) micro.gpio.State {
+ const idr_reg = pin.gpio_port.IDR;
+ const reg_value = @field(idr_reg.read(), "IDR" ++ pin.suffix); // TODO extract to getRegField()?
+ return @as(micro.gpio.State, @enumFromInt(reg_value));
+ }
+
+ pub fn write(comptime pin: type, state: micro.gpio.State) void {
+ switch (state) {
+ .low => setRegField(pin.gpio_port.BSRR, "BR" ++ pin.suffix, 1),
+ .high => setRegField(pin.gpio_port.BSRR, "BS" ++ pin.suffix, 1),
+ }
+ }
+};
diff --git a/board-support/stmicro-stm32/test/programs/minimal.zig b/board-support/stmicro-stm32/test/programs/minimal.zig
new file mode 100644
index 0000000..5258ce3
--- /dev/null
+++ b/board-support/stmicro-stm32/test/programs/minimal.zig
@@ -0,0 +1,5 @@
+const micro = @import("microzig");
+
+pub fn main() void {
+ // This function will contain the application logic.
+}
diff --git a/board-support/stmicro-stm32/test/stm32f103.robot b/board-support/stmicro-stm32/test/stm32f103.robot
new file mode 100644
index 0000000..28c77fe
--- /dev/null
+++ b/board-support/stmicro-stm32/test/stm32f103.robot
@@ -0,0 +1,10 @@
+*** Settings ***
+Suite Setup Setup
+Suite Teardown Teardown
+Test Teardown Test Teardown
+Resource ${RENODEKEYWORDS}
+
+*** Test Cases ***
+Should Print Help
+ ${x}= Execute Command help
+ Should Contain ${x} Available commands: